FS98O22-DS-14_EN JUL 2011 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y REV. 1.4 Datasheet FS98O22 8-bit MCU with 4k program EPROM, 256-byte RAM, 1 low noise OPAMP, 8-ch 14-bit ADC, 4 × 20 LCD driver and RTC FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Fortune Semiconductor Corporation 富晶電子股份有限公司 28F,No.27, Sec. 2, Zhongzheng E. Rd., Danshui Dist, New Taipei City 251, Taiwan Tel.:886-2-28094742 Fax:886-2-28094874 www.ic-fortune.com This manual contains new product information. Fortune Semiconductor Corporation reserves the rights to modify the product specification without further notice. No liability is assumed by Fortune Semiconductor Corporation as a result of the use of this product. No rights under any patent accompany the sale of the product. Rev. 1.4 2/146 FS98O22 Contents DEVICE OVERVIEW ................................................................................................................................................... 10 1.1 High Performance RISC CPU ..................................................................................................... 10 1.2 Peripheral Features..................................................................................................................... 10 1.3 Analog Features .......................................................................................................................... 10 1.4 Special Microcontroller Features ............................................................................................... 10 1.5 CMOS Technology ...................................................................................................................... 10 1.6 Applications................................................................................................................................. 11 1.7 Ordering Information .................................................................................................................. 11 1.8 Pin Configuration ........................................................................................................................ 12 1.9 Pin Description ............................................................................................................................ 13 1.10 Functional Block Diagram .......................................................................................................... 14 1.11 CPU Core ..................................................................................................................................... 16 1.12 Clocking Scheme/Instruction Cycle .......................................................................................... 18 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1. 2. ELECTRICAL CHARACTERISTICS ........................................................................................................................... 19 2.1 Absolute Maximum Ratings ....................................................................................................... 19 2.2 DC Characteristics (VDD=3V, TA=25℃, unless otherwise noted) ............................................ 19 2.3 ADC Characteristics (VDD=3V, TA=25℃, unless otherwise noted) ......................................... 20 2.4 OPAMP Characteristics (VDD=3V, TA=25℃, unless otherwise noted) .................................... 20 2.5 Temperature Characteristics(VDD=3V) ........................................................................................... 20 3. MEMORY ORGANIZATION ......................................................................................................................................... 21 3.1 Program Memory Structure ........................................................................................................ 21 3.2 Data Memory Structure ............................................................................................................... 21 3.3 System Special Registers........................................................................................................... 22 3.3.1 3.3.2 3.3.3 3.3.4 3.4 4. Special Register Contents after External Reset (Power On Reset) and WDT Reset . 22 IND and FSR Registers ................................................................................................... 23 STATUS Register ............................................................................................................. 24 INTE and INTF registers.................................................................................................. 25 Peripheral Special Registers ...................................................................................................... 27 POWER SYSTEM ....................................................................................................................................................... 29 4.1 Voltage Doubler ........................................................................................................................... 33 4.2 Voltage Regulator ........................................................................................................................ 35 4.3 Analog Bias Circuit ..................................................................................................................... 36 4.4 Analog Common Voltage Generator .......................................................................................... 37 4.5 Low Battery Comparator ............................................................................................................ 38 Rev. 1.4 3/146 FS98O22 4.6 CLOCK SYSTEM ........................................................................................................................................................ 40 5.1 Oscillator State ............................................................................................................................ 41 5.2 CPU Instruction Cycle ................................................................................................................ 42 5.3 ADC Sample Frequency ............................................................................................................. 43 5.4 Beeper Clock ............................................................................................................................... 44 5.5 Voltage Doubler Operation Frequency ...................................................................................... 45 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 5. Bandgap Voltage and Temperature Sensor .............................................................................. 39 6. 5.6 Chopper Operation Amplifier Input Control Signal .................................................................. 46 5.7 TMCLK -- Timer and LCD Module Input Clock .......................................................................... 47 TIMER MODULE, WATCH DOG TIMER AND PROGRAMMABLE COUNTER ........................................................... 48 6.1 Timer Module ............................................................................................................................... 53 6.1.1 6.1.2 7. Timer module interrupt ................................................................................................... 54 Using Timer with External/Internal Clock...................................................................... 55 6.2 Watch Dog Timer ......................................................................................................................... 57 6.3 Dual 16-bit Programmable Counter ........................................................................................... 58 I/O PORT..................................................................................................................................................................... 62 7.1 Digital I/O Port with Analog Input Channel Shared: PT1[7:0] .................................................. 75 7.2 Digital I/O Port and External Interrupt Input : PT2[0], PT2[1], PT3[0], PT3[1]......................... 77 7.3 Digital I/O Port or PDM Output : PT2[2] and PT2[5] .................................................................. 79 7.4 Digital I/O Port or I2C Serial Port : PT2[3]/SDA, PT2[4]/SCL .................................................... 80 7.5 Digital I/O Port : PT2[6] ............................................................................................................... 82 7.6 Digital I/O Port or Buzzer Output : PT2[7] ................................................................................. 84 8. PDM (PULSE DENSITY MODULATOR) MODULE...................................................................................................... 86 9. I2C MODULE (SLAVE MODE ONLY) .......................................................................................................................... 93 10. ANALOG FUNCTION NETWORK............................................................................................................................. 100 10.1 Analog to Digital Converter (ADC) :......................................................................................... 109 10.2 OPAMP : OP1 ............................................................................................................................. 113 11. ADC APPLICATION GUIDE ...................................................................................................................................... 115 11.1 ADC Output Format .................................................................................................................. 115 11.2 ADC Linear Range..................................................................................................................... 115 11.3 ADC Output Rate and Settling Time ........................................................................................ 115 11.4 ADC Input Offset ....................................................................................................................... 115 11.5 ADC Digital Output .................................................................................................................... 116 11.6 ADC Resolution ......................................................................................................................... 116 12. LOW NOISE OPERATION AMPLIFIER GUIDE......................................................................................................... 117 12.1 Single End Amplifier Application ............................................................................................. 117 Rev. 1.4 4/146 FS98O22 12.2 Differential Amplifier ................................................................................................................. 118 13. LCD DRIVER............................................................................................................................................................. 119 14. HALT AND SLEEP MODES ...................................................................................................................................... 131 15. INSTRUCTION SET .................................................................................................................................................. 132 15.1 Instruction Set Summary.......................................................................................................... 132 15.2 Instruction Description ............................................................................................................. 134 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 16. PACKAGE INFORMATION ....................................................................................................................................... 145 16.1 Package Outline ........................................................................................................................ 145 16.2 Package Outline(3.2mm QFP100) ............................................................................................ 146 17. REVISION HISTORY ................................................................................................................................................. 146 Rev. 1.4 5/146 FS98O22 Figure List FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Figure 1-1 FS98O22 pin configuration ......................................................................................... 12 Figure 1-2 FS98O22 function block .............................................................................................. 14 Figure 1-3 FS98O22 CPU core function block ............................................................................. 16 Figure 1-4 FS98O22 instruction cycle .......................................................................................... 18 Figure 2-1 VDDA vs Temp @ VDD=3V Figure 2-2 VREF vs Temp @ VDD=3V....................... 20 Figure 2-3 LVR vs Temp @ VDD=3V ............................................................................................. 20 Figure 3-1 FS98O22 program memory structure ......................................................................... 21 Figure 3-2 IND & FSR function description .................................................................................. 23 Figure 4-1 FS98O22 power system block .................................................................................... 29 Figure 4-2 Voltage Doubler ............................................................................................................ 33 Figure 4-3 Voltage regulator .......................................................................................................... 35 Figure 4-4 analog bias circuit ....................................................................................................... 36 Figure 4-5 analog common voltage generator ............................................................................. 37 Figure 4-6 low battery comparator function block ...................................................................... 38 Figure 4-7 Bandgap voltage and temperature sensor function block ....................................... 39 Figure 5-1 FS98O22 clock system function block ....................................................................... 40 Figure 5-2 FS98O22 oscillator state block ................................................................................... 41 Figure 6-1 FS98O22 timer module function block ....................................................................... 53 Figure 6-2 watch dog timer function block .................................................................................. 57 Figure 6-3 Programmable Counter Working block diagram ....................................................... 58 Figure 6-4 Programmable Counter Counter mode ...................................................................... 59 Figure 6-5 Programmable Counter Pulse Width Measurement mode ....................................... 60 Figure 6-6 Programmable Counter Frequency Measurement mode.......................................... 61 Figure 7-1 PT1[7:0] function block ............................................................................................... 75 Figure 7-2 PT2[0] PT2[1] PT3[0] PT3[1] function block ............................................................... 77 Figure 7-3 PT2[2] function block................................................................................................... 79 Figure 7-4 PT2[3] PT2[4] function block ....................................................................................... 80 Figure 7-5 PT2[6] function block................................................................................................... 82 Figure 7-6 PT2[7] function block................................................................................................... 84 Figure 8-1 FS98O22 PDM module function block........................................................................ 86 Figure 8-2 PDM module signal generation ................................................................................... 87 Figure 9-1 FS98O22 I2C module communication ........................................................................ 93 Figure 9-2 I2C module function block .......................................................................................... 94 Figure 9-3 I2C waveform for reception ......................................................................................... 98 Figure 9-4 I2C waveforms for transmission ................................................................................. 99 Figure 10-1 FS98O22 analog function network ......................................................................... 100 Figure 10-2 FS98O22 ADC function block.................................................................................. 109 Figure 12-1 single end amplifier application example ............................................................... 117 Figure 12-2 differential amplifier example .................................................................................. 118 Figure 13-1 LCD driver control block .......................................................................................... 119 Figure 13-2 LCD control mode ..................................................................................................... 119 Figure 13-3 LCD duty mode working cycle ................................................................................ 121 Figure 13-4 1/3 bias LCD power system circuit connection example...................................... 122 Figure 13-5 1/3 bias LCD power system clock .......................................................................... 122 Figure 13-6 1/2 bias LCD power system circuit connection example...................................... 123 Figure 13-7 1/2 bias LCD power system clock .......................................................................... 123 Figure 16-1 FS98O22 package outline ........................................................................................ 145 Figure 16-2 FS98O22 3.2mm QFP100 package outline ............................................................. 146 Rev. 1.4 6/146 FS98O22 Table List FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Table 1-1 Ordering Information ...................................................................................................... 11 Table 1-2 FS98O22 pin description ............................................................................................... 13 Table 1-3 FS98O22 main function description table.................................................................... 15 Table 1-4 FS98O22 CPU core block diagram description table .................................................. 17 Table 2-1 FS98O22 absolute maximum rating table .................................................................... 19 Table 2-2 FS98O22 DC characteristics ......................................................................................... 19 Table 2-3 FS98O22 ADC characteristics ....................................................................................... 20 Table 2-4 FS98O22 OPAMP characteristics ................................................................................. 20 Table 3-1 FS98O22 Data memory structure ................................................................................. 21 Table 3-2 system register table ..................................................................................................... 22 Table 3-3 special register reset table ............................................................................................ 22 Table 3-4 peripheral special registers table ................................................................................. 27 Table 4-1 FS98O22 power system register table ......................................................................... 30 Table 4-2 Voltage Doubler register table ...................................................................................... 33 Table 4-3 Voltage Doubler operation frequency selection table ................................................. 34 Table 4-4 voltage regulator register table .................................................................................... 35 Table 4-5 analog bias circuit register table .................................................................................. 36 Table 4-6 analog common voltage generator register table ....................................................... 37 Table 4-7 low battery comparator register table .......................................................................... 38 Table 4-8 low battery comparator voltage detection selection table ......................................... 38 Table 4-9 bandgap voltage and temperature sensor register table ........................................... 39 Table 5-1 FS98O22 clock system register table ........................................................................... 40 Table 5-2 FS98O22 clock system register table ........................................................................... 41 Table 5-3 MCK selection table ....................................................................................................... 41 Table 5-4 CLK selection table ........................................................................................................ 41 Table 5-5 oscillator state selection table ...................................................................................... 42 Table 5-6 FS98O22 CPU instruction cycle register table ............................................................ 42 Table 5-7 MCK selection table ....................................................................................................... 42 Table 5-8 instruction cycle selection table ................................................................................... 42 Table 5-9 ADC sample frequency selection table ........................................................................ 43 Table 5-10 beeper clock register table.......................................................................................... 44 Table 5-11 MCK selection table ..................................................................................................... 44 Table 5-12 CLK selection table ...................................................................................................... 44 Table 5-13 beeper clock selection table ....................................................................................... 44 Table 5-14 register and the beeper clock selection table ........................................................... 45 Table 5-15 MCK selection table ..................................................................................................... 45 Table 5-16 Voltage Doubler operation frequency selection table ............................................... 45 Table 5-17 CLK selection table ...................................................................................................... 46 Table 5-18 MCK selection table ..................................................................................................... 46 Table 5-19 chopper control signal selection table ...................................................................... 46 Table 5-20 TMCLK selection table................................................................................................. 47 Table 6-1 Timer module and watch dog timer register table ...................................................... 48 Table 6-2 timer module interrupt register table ........................................................................... 54 Table 6-3 timer selection table ...................................................................................................... 54 Table 6-4 external timer setup register table ............................................................................... 55 Table 6-5 CLK selection table ........................................................................................................ 55 Table 6-6 MCK selection table ....................................................................................................... 55 Table 6-7 TMCLK selection table .................................................................................................. 55 Table 6-8 registers and timer selection table ............................................................................... 56 Table 6-9 watch dog timer register table ...................................................................................... 57 Table 6-10 Programmable Counter working mode selection table ............................................ 58 Table 6-11 Programmable Counter Clock signal selection table ............................................... 59 Table 7-1 FS98O22 I/O port register table .................................................................................... 62 Table 7-2 PT1 register table ........................................................................................................... 76 Table 7-3 PT2 register table ........................................................................................................... 78 Table 7-4 PT2 register table ........................................................................................................... 80 Table 7-5 PT2 register table ........................................................................................................... 81 Table 7-6 PT2 register table ........................................................................................................... 83 Table 7-7 PT2[7] register table ...................................................................................................... 85 Rev. 1.4 7/146 FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Table 8-1 PDM module register table ............................................................................................ 88 Table 8-2 PMD register table ......................................................................................................... 92 Table 8-3 PDM CLK selection table ............................................................................................... 92 Table 9-1 I2C module register table .............................................................................................. 95 Table 9-2 I2C register table ............................................................................................................ 98 Table 10-1 analog function network register table .................................................................... 101 Table 10-2 ADC function register table ........................................................................................ 110 Table 10-3 FTIN selection table .................................................................................................... 110 Table 10-4 FTB selection table ..................................................................................................... 110 Table 10-5 INH selection table ...................................................................................................... 111 Table 10-6 INL selection table ...................................................................................................... 111 Table 10-7 ADG selection table .................................................................................................... 111 Table 10-8 VRH selection table .................................................................................................... 111 Table 10-9 SVRL selection table................................................................................................... 112 Table 10-10 ADC output rate selection table ............................................................................... 112 Table 10-11 ADC sample frequency selection table ................................................................... 112 Table 10-12 FS98O22 OPAMP register table ............................................................................... 113 Table 10-13 OP1P selection table................................................................................................. 113 Table 10-14 OP1N selection table ................................................................................................ 113 Table 10-15 chopper mode selection table ................................................................................. 114 Table 11-1 ADC rolling counts versus ADM ................................................................................ 116 Table 11-2 ADC rolling counts versus VR ................................................................................... 116 Table 13-1 LCD frame frequency selection table ....................................................................... 120 Table 13-2 LCD duty selection table ........................................................................................... 120 Table 13-3 FS98O22 LCD driver register table ........................................................................... 124 Table 13-4 LCD driver register table ........................................................................................... 129 Table 13-5 CLK selection table .................................................................................................... 129 Table 13-6 MCK selection table ................................................................................................... 129 Table 13-7 TMCLK selection table............................................................................................... 129 Table 13-8 LCD frame frequency selection table ....................................................................... 130 Table 13-9 LCD duty control mode selection table.................................................................... 130 Table 15-1 FS98O22 instruction set table................................................................................... 132 Rev. 1.4 8/146 FS98O22 Register List FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register STATUS at address 04H ................................................................................................. 24 Register INTE at address 07H ....................................................................................................... 25 Register INTF at address 06H ....................................................................................................... 26 Register PCK at address 15H ........................................................................................................ 30 Register NETE at address 1CH ..................................................................................................... 31 Register NETF at address 1DH ..................................................................................................... 32 Register SVD at address 1FH ........................................................................................................ 32 Register CTAH at address 08H...................................................................................................... 48 Register CTAL at address 09H ...................................................................................................... 48 Register CTBH at address 0AH ..................................................................................................... 49 Register CTBL at address 0BH ..................................................................................................... 49 Register CTCON at address 0CH .................................................................................................. 50 Register WDTCON at address 0DH............................................................................................... 51 Register TMOUT at address 0EH .................................................................................................. 52 Register TMCON at address 0FH .................................................................................................. 52 Register PT1 at address 20H ......................................................................................................... 63 Register PT1EN at address 21H .................................................................................................... 63 Register PT1PU at address 22H .................................................................................................... 63 Register AIENB1 at address 23H .................................................................................................. 65 Register PT2 at address 24H ......................................................................................................... 66 Register PT2EN at address 25H .................................................................................................... 67 Register PT2PU at address 26H .................................................................................................... 68 Register PT2MR at address 27H ................................................................................................... 69 Register PT3 at address 28H ......................................................................................................... 70 Register PT3EN at address 29H .................................................................................................... 71 Register PT3PU at address 2AH ................................................................................................... 72 Register PT3MR at address 2BH................................................................................................... 73 Register PT2OCB at address 37H ................................................................................................. 74 Register PT2MR at address 27H ................................................................................................... 88 Register PMD1H at address 30H ................................................................................................... 89 Register PMD1L at address 31H ................................................................................................... 89 Register PMD2H at address 30H ................................................................................................... 90 Register PMD2L at address 31H ................................................................................................... 90 Register PMCON at address 36H .................................................................................................. 91 Register I2CCON at address 57H .................................................................................................. 95 Register I2CSTA at address 58H ................................................................................................... 96 Register I2CADD at address 59H .................................................................................................. 96 Register I2CBUF at address 5AH .................................................................................................. 97 Register ADOH at address 10H ................................................................................................... 102 Register ADOL at address 11H ................................................................................................... 102 Register ADOLL at address 12H ................................................................................................. 103 Register ADCON at address 13H ................................................................................................ 103 Register PCK at address 15H ...................................................................................................... 104 Register NETA at address 18H .................................................................................................... 105 Register NETB at address 19H ................................................................................................... 106 Register NETC at address 1AH ................................................................................................... 107 Register NETD at address 1BH ................................................................................................... 108 Register LCD1 at address 40H .................................................................................................... 124 Register LCD2 at address 41H .................................................................................................... 125 Register LCD3 at address 42H .................................................................................................... 125 Register LCD4 at address 43H .................................................................................................... 126 Register LCD5 at address 44H .................................................................................................... 126 Register LCD6 at address 45H .................................................................................................... 127 Register LCDENR at address 54H .............................................................................................. 128 Rev. 1.4 9/146 FS98O22 1. Device Overview The FS98O22 is a CMOS 8-bit single chip microcontroller(MCU) with embedded a 4kx16 bits one-time programmable (OTP) ROM, a 8-channel 14-bit fully differential input analog to digital converter, low noise amplifier, and 4 x 20 LCD driver. The FS98O22 is best suited for applications such as electrical scale, meter, and sensor or transducer measurement application etc. 1.1. 8-bit single chip microcontroller(MCU). Embedded 4k x 16 bits program memory with one-time programmable (OTP) ROM. 256-byte data memory (SRAM). Only 37 single word instructions to learn 8-level memory stacks. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y High Performance RISC CPU 1.2. 1.3. 1.4. 1.5. Peripheral Features 16-bit bi-directional I/O port. PDM (Pulse Density Modulator) output. Buzzer output. I2C serial I/O port (slave mode only). 4 x 20 LCD drivers. One 8-channel 14-bit fully differential input analog to digital converter(ADC) One low noise amplifier Analog Features 8-channel Sigma-Delta ADC with programmable output rate and resolution. Low noise (1μV Vpp without chopper, 0.5μV Vpp with chopper, 0.1Hz~1Hz) OPAMP with chopper controller. Special Microcontroller Features External 32768Hz crystal oscillator (RTC). Embedded Low Voltage Reset (LVR) and Low Voltage Detector (LVD). Embedded charge pump (Voltage Doubler) and voltage regulator (3.6V regulated output). Embedded bandgap voltage reference (typical 1.16V±50mV, 100ppm/°C). 8 Interrupt sources (external: 5, internal: 3). Internal silicon temperature sensor. Watchdog timer (WDT). Embedded 1.0 MHz oscillator. Package: 73-pin dice form, 100-pin LQFP. CMOS Technology Voltage operation ranges from 2.2V to 3.6V. Operation current is less than 4 mA; sleep mode current is about 3μA. Rev. 1.4 10/146 FS98O22 1.6. 1.7. Applications Sensor or transducer measurement applications. Electronic kitchen scale, personal scale. Digital meter. Ordering Information Table 1-1 Ordering Information Description Package Type MCU with OTP ROM; The customer has to 73-pin Dice form, 100-pin LQFP program the compiled hex code into OTP ROM. MCU with program type; FSC programs the 73-pin Dice form, 100-pin LQFP customer‟s compiled hex code into OTP ROM at factory before shipping. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Product Number FS98O22 FS98O22-nnnV Note1: Code number (nnnV) is assigned for customer. Note2: Code number (nnn = 001~999); Version (V = A~Z). Rev. 1.4 11/146 FS98O22 Pin Configuration FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1.8. Figure 1-1 FS98O22 pin configuration Rev. 1.4 12/146 FS98O22 1.9. Pin Description Table 1-2 FS98O22 pin description In/Out P I/O O I/O I I/O I/O Pin No 5 7 8 9, 10 11 12 13~20 21~22 39~40 23,36 24 25 38 41 42 37 43~46 51~70 71~74 83 84 85~87 88 89 90 91 92 93 94 95 96 97 98 99 100 - Description Programming Power Supply OPAMP 1 Output Band gap Reference Output ADC Pre-Filter Capacitor Connection Analog Circuit Bias Current Input Analog Ground Digital I/O Port or Analog input channel FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Name VPP OP1O REFO FTB, FTC VB AGND PT1<0~7>/AIN0~7 PT2<0~1>/INT0~1, PT3<0~1>/INT2~3 PT2<2,5>/PDM1,2 PT2<3>/SDA PT2<4>/SCL PT2<7>/BZ PT3<2>/PFI PT3<3>/PFO PT2<6>, PT3<4~7> SEG20~SEG1 COM4~COM1 LCA LCB V3,V2,V1 VDDA VS VGG VSSP CB CA VDDP VDD VSS XOUT XIN TST RST NC Rev. 1.4 I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O P P P P P I/O I/O P P P O I I I - Digital I/O Port and External Interrupt input Digital I/O Port or PDM output Digital I/O Port or I2C serial Bi-Directional data line Digital I/O Port or I2C clock input Digital I/O Port or Buzzer Output Digital I/O Port or Programmable Frequency Input Digital I/O Port or Programmable Frequency Output Digital I/O Port LCD Segment Driver Output LCD Common Driver Output LCD Charge Pump Capacitor Positive Connection LCD Charge Pump Capacitor Negative Connection LCD Bias Analog Power Output Voltage Source from VDDA Charge Pump Voltage Charge Pump Negative Power Supply Charge Pump Capacitor Negative Connection Charge Pump Capacitor Positive Connection Charge Pump Positive Power Supply Positive Power Supply Negative Power Supply (Ground) 32768Hz Oscillator Output 32768Hz Oscillator Input Testing Mode CPU Reset No Connection 13/146 FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1.10. Functional Block Diagram Figure 1-2 FS98O22 function block Rev. 1.4 14/146 FS98O22 There are 5 kinds of functional blocks in the Function Block Diagram, described as table 1-3: Table 1-3 FS98O22 main function description table Item CPU Kernel Sub Item FS98O22 CPU Core OTP Program Memory Data Memory FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Clock sys Description Please refer to Chapter 1.11 for detailed description OTP: One Time Programmable 8k bytes is used for 4k line programming instructions FS98O22 has 256 bytes SRAM embedded in it. (128 bytes registers, 256 general data memory) There are two clock sources in FS98O22. One is the internal clock which generates 1M HZ for CPU works, and the other is an external one which provide 32768 HZ clock signal to the chip. Clock Counter for Time out interrupt and Watch dog Timer Embedded 4 X 20 LCD driver Embedded Serial Port for Communication, It support I2C protocol which is designed by Philips Similar to PWM function User should connect a Buzzer to the embedded buzzer port to receive the warning or reminding signal. FS98O22 embeds Dual 16-bit Programmable Counter which could be used to do three kinds of processes: Counter, Pulse Width Measurement and Frequency Measurement. FS98O22 support 2 External Interrupt port An embedded Sigma-Delta Analog to Digital Converter which converts the analog signal of the sensor to a digital number. FS98O22 has an embedded low noise OP amplifier for pre-processing the signal, which is connected to the ADC to get a better A/D resolution or amplify the signal to fit the ADC Input range. FS98O22 has a special power system. The power system can supply a fixed voltage for CPU and ADC. The input voltage of the chip can be within a certain range and floating. The PT1 port has 8 bits. User can define these 8 bits for general purpose or special assignment as ADC input. The PT2 port has 8 bits. User can define these 8 bits for general purpose or some special function as External Interrupt, I2C, PDM and the Buzzer. Digital Function Timer Module LCD Module I2C PDM Buzzer Programmable Counter Analog Function Ext. INT ADC OP Amplifier Power Function Power Module General Purpose I/O PT1 PT2 Rev. 1.4 15/146 FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1.11. CPU Core Figure 1-3 FS98O22 CPU core function block The “CPU Core Block Diagram” shown in Section 1.11 mainly includes 7 important registers and 2 memory units. Please see the Figure 1-3 and the Table 1-4 for detailed information. Rev. 1.4 16/146 FS98O22 Table 1-4 FS98O22 CPU core block diagram description table Sub Items Program Counter Description This Register plays an important role in all the CPU working cycle. It records the pointer of the instruction that the CPU processes every cycle in the Program Memory. In a general CPU cycle, Program Counter pushes the Program Memory Address (12bits), instruction pointer, into the Program Memory and then increments for the next cycle. Stack Register Stack Register is used for recording the program return instruction pointer. When the program calls function, Program Counter will push the instruction pointer into the Stack Register. After finish this function, Stack Register pushes the instruction pointer back to the Program Counter to resume the original program process. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Items Registers Instruction Register After Program Counter pushes the instruction pointer (Program Memory Address) into the Program Memory, Program Memory pushes the Program Memory Data (16bits), instruction, into Instruction Register for reference. FS98O22 instruction has 16 bits, and contains 3 kinds of information as Direct Address, Direct Data and Control Information. CPU could push the Direct Data into Work Register or do some process for the register stored in the Data Memory pointed by the Direct Address by Control Information. Instruction Decoder Instruction Register pushes the Control Information to the Instruction Decoder to decode and then sends the decoded information to related registers. File Select Register In FS98O22 Instruction Sets, FSR (File Select Register) is used for indirect data process. User could fill the FSR with the Data Memory Address of some register, and then process this register by IND Register. CPU will fill the IND Register with the data address in the Data Memory as FSR. Work Register Work Register is used for buffering the data which is stored in some memory address of Data Memory. While CPU processes some register data by ALU, the following status may change as follows: PD, TO, DC, C and Z. Please refer to Section 3.3.2 for detailed introduction. Status Register Memory Program Memory Data Memory Rev. 1.4 Direct Address (8bits) It is the Data Memory Address. CPU can use this address to process the Data Memory. Direct Data (8bits) It is the value which CPU used for processing Work Register by the ALU (arithmetic and logic unit). Control Information It records the information for the ALU to process. FS98O22 has an embedded 4k bytes OTP (One Time Programmable) ROM as Program Memory. Because the OPCODE of the instruction is 16 bits, user could program 4k instructions in FS98O22 at most. Program Memory Address Bus is 12 bits, and the Data Bus is 16bits. FS98O22 has an embedded 256 bytes SRAM as Data Memory. The Data Memory Address Bus is 8 bits, and Data Bus is 8 bits. 17/146 FS98O22 1.12. Clocking Scheme/Instruction Cycle FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y One Instruction cycle (CPU cycle) includes 4 steps and the CPU could process 2 steps per CPU Clock. Users can setup the MCK Register to decide the step timing. Please refer to Chapter 5 for related information. For Example, if the MCK Register is filled with 0x04h (MCK = ICK, Instruction Cycle = MCK / 2, ICK = 1MHZ), the step timing is 500k HZ, and one instruction cycle needs 4us (2 x 1/500k sec) to complete. The 4 steps are described as follows. Please refer to the CPU core (Section 1.11) to understand these 4 steps. 1. Fetch Program Counter pushes the Instruction Pointer into Program Memory, and the pointed Data in the Program Memory is stored in the Instruction Register. 2. Decode The Instruction Register pushes the Direct Address to Address MUX, or pushes the Direct Data to Data MUX, and pushes the Control Information into Instruction Decoder to decode the OPCODE. 3. Execute ALU executes the process based on the decoded Control Information. 4. Write Back Push the ALU result to Work Register or Assigned Data Memory Address. Because one OPCODE can only have either Direct Address or Direct Data, sometimes user needs 2 instructions to complete one simple job. For example, if user want to fill Data Memory address 0x55h with data 0xFFh, user needs to process 【movlw 0xFFh】 to filled Work Register with 0xFFh, and then process 【movwf 0x55h】to fill Data Memory 0x55h with Work Register content. For the same reason, CPU needs 2 instruction cycles to complete some kinds of instructions such as call, goto…etc. Please see the Figure 1-4. Figure 1-4 FS98O22 instruction cycle Rev. 1.4 18/146 FS98O22 2. Electrical Characteristics 2.1. Absolute Maximum Ratings Table 2-1 FS98O22 absolute maximum rating table Unit V V C C FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Parameter Rating Supply Voltage on VDD 3.6 Input Voltage on any pin -0.3 to VDD+0.3 Ambient Operating Temperature -40* to +85 Storage Temperature -55 to +150 Soldering Temperature, Time 260C, 10 Sec * FS98O22 passed -40C LTOL (Low Temperature Operating Life) test (VDD=3V) 2.2. DC Characteristics (VDD=3V, TA=25℃, unless otherwise noted) Table 2-2 FS98O22 DC characteristics Symbol Parameter VDD Operation Power Voltage IDD1 IDD2 IPO VIH VIL VIHSH VIHSL IPU IOH IOL VDDA IREG Min 2.2 MCK=1MHz, CPUCLK=MCK/2, Charge Pump, ADC,OPAMP ON Internal Oscillator Off, Supply Current 2 MCK=32768Hz LCD ON. Sleep Mode Supply Current Sleep Instruction Digital Input High Voltage PT1, Reset 0.7 Digital Input Low Voltage PT1, Reset Schmitt-trigger port Input Hys. High Voltage Schmitt-trigger port Input Hys. Low Voltage Pull up Current Vin=0 High Level Output Current VOH=VDD-0.3 V Low Level Output Current VOL=0.3 V Analog Power VDD=3V VDDA Regulator Output Internal Voltage Double Current VDDA=0.95*VDDA(unload) Supply Current 1 VCVDD VDDA Voltage Coefficient A AGND Analog Ground Voltage VREF Build in Reference Voltage Build in Reference Voltage TCREF Temperature Coefficient Low Battery Detection VLBAT Voltage VSR VS Switch Resistor FRC Internal RC oscillator FWDT Internal WDT Clock Rev. 1.4 Test Conditions Typ Max 3.6 4 8 mA 15 3 0.45 0.20 20 7 5 3.5 0.3 6 -2 Unit V μA μA VDD VDD VDD VDD μA mA mA V mA 2 %/V VDDA/2 1.18 V V Ta=-40~80℃ 100 ppm/℃ S_LB [1:0]=00 S_LB [1:0]=01 2.3 3.5 10 1.0 2.1 To AGND 0.7 V 1.3 Ω MHz KHz 19/146 FS98O22 2.3. ADC Characteristics (VDD=3V, TA=25℃, unless otherwise noted) Table 2-3 FS98O22 ADC characteristics Symbol Parameter ADC Common Mode Input Range VADIN ADC Differential Mode Input Range Resolution ADC Linearity Error ADC Input Offset Voltage With Zero Cancellation VRFIN=0.44V VRFIN=0.44V VAIN=0 -0.1 Typ. Max. Unit 0 2.3 V 15625 0 0.6 1 31250 +0.1 V Counts mV 0 V FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y VACIN Test Conditions Min. INH,INL,VRH,VRL to 0.6 VSS (INH,INL), (VRH,VRL) 2.4. OPAMP Characteristics (VDD=3V, TA=25℃, unless otherwise noted) Table 2-4 FS98O22 OPAMP characteristics Test Conditions Min. Typ. 1.5 20 1.0 0.5 10 100 Rs<100 Rs=100 , 0.1Hz~1Hz Rs=100 , 0.1Hz~1Hz 0.5 0.5 S_CHCK[1:0]=11 Temperature Characteristics(VDD=3V) Max. Unit mV V Vpp Vpp pA pA V V Hz pF 30 300 2.4 2.4 1k 50 100 V 2.5. Parameter Input Offset Input Offset Voltage with Chopper Input Reference Noise Input Reference Noise with Chopper Input Bias Current Input Bias Current with Chopper Input Common Mode Range Output Voltage Range Chopper Clock Frequency Capacitor Load ) Symbol VDDA Temperature Coefficient(Average) R E F T e m p e r a t u r e C ( V F 1 . 2 2 5 0 E 3.7200 1 . 2 2 0 0 1 . 2 1 5 0 1 . 2 1 0 0 3.6200 1 . 2 0 5 0 3.6000 1 . 2 0 0 0 1 . 9 5 0 3.6800 R 3.6600 3.6400 V VDDA(V) 3.7000 3.5800 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Temperature (Deg) - - 1 5 - 4 - 0 3 -0 2 0 1 10 0 20 0 30 T Figure 2-1 VDDA vs Temp @ VDD=3V 40 50 e 60 m 70 80 p 90 100 110 120 130 140 150 e r a t u Figure 2-2 VREF vs Temp @ VDD=3V LVR Temperature Coefficient(Average) 2.75 LVR(V) 2.50 2.25 2.00 1.75 1.50 1 2 3 4 5 6 7 8 9 10 Temperature(Deg) Figure 2-3 LVR vs Temp @ VDD=3V 1 Use ADOH, ADOL and ADOLL (Extra ADC output register) three register (24 bits ADC output) Rev. 1.4 20/146 r e ( D e g FS98O22 3. 3.1. Memory Organization Program Memory Structure FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y FS98O22 has an 12bits Program Counter which is capable of addressing a 4k x 16bits program memory space and a 8 level depth 12bits Stack Register. The Start up/Reset Vector is at 0x0000H. When FS98O22 is started or its program is reset, the Program Counter will point to Reset Vector. The Interrupt Vector is at 0x0004H. No matter what ISR is processed, the Program Counter will point to Interrupt Vector. Please see Figure 3-1. Figure 3-1 FS98O22 program memory structure 3.2. Data Memory Structure FS98O22 has 384-byte Data Memory. The data memory is partitioned into three parts. The area with address 00h~07h is reserved for system special registers, such as indirect address, indirect address pointer, status register, working register, interrupt flag, interrupt control register. The address 08h~7Fh areas are peripheral special registers, such as I/O ports, timer, ADC, signal conditional network control register, LCD driver. The address 80h~17Fh areas are SRAM for general data memory. Please see Table 3-1. Table 3-1 FS98O22 Data memory structure Rev. 1.4 Start Address End Address Data Memory 0X00H 0X07H System Special Registers 0X08H 0X7FH Peripheral Special Registers 0X80H 0X17FH General Data Memory(256 bytes) 21/146 FS98O22 3.3. System Special Registers The System Special Registers are designed to complete CPU Core functions, and consists of indirect address, indirect address pointer, status register, work register, interrupt flag, and interrupt control register. Please see Section 1.11 for related CPU work flow chart. Table 3-2 system register table Address Name IND0 IND1 FSR0 FSR1 STATUS WORK INTF 07H INTE 16H 17H INTF2 INTE2 3.427 3.4.1 1.11/3.4.1 1.11/3.4.1 1.11/3.4.2 1.11 Value on Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power on 2 Reset Use contents of FSR0 to address data memory uuuuuuuu Use contents of FSR1 to address data memory uuuuuuuu Indirect data memory address pointer 0 uuuuuuuu Indirect data memory address pointer 1 uuuuuuuu IRP1 IRP0 PD TO DC C Z 00u00uuu WORK register uuuuuuuu I2CI 00000000 TMIF ADIF E1IF E0IF F I2CI 00000000 GIE TMIE ADIE E1IE E0IE E CTIF E3IF E2IF 00000000 CTIE E3IE E2IE 00000000 Bit 7 Bit 6 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 00H 01H 02H 03H 04H 05H 06H Referenced Section 3.3.1. 3/6/7/9/10/11 3/6/7/9/10/11 6/7 6/7 Special Register Contents after External Reset (Power On Reset) and WDT Reset Table 3-3 special register reset table Register Address 04H 0DH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 37H 57H 58H 59H 5AH 2 Register Content Register Name External Reset WDT Reset STATUS 00u00uuu uuuu1uuu WDTCON 00000000 uuuuuuuu PT1 00000000 uuuuuuuu PT1EN 00000000 uuuuuuuu PT1PU 00000000 uuuuuuuu AIENB1 00000000 uuuuuuuu PT2 00000000 uuuuuuuu PT2EN 00000000 uuuuuuuu PT2PU 00000000 uuuuuuuu PT2MR 00000000 uuuuuuuu PT3 00000000 uuuuuuuu PT3EN 00000000 uuuuuuuu PT3PU 00000000 uuuuuuuu PT3MR 00000000 uuuuuuuu PT2OC uuu11uuu uuuuuuuu I2CCON 0001uuuu uuuuuuuu STA uu0000u0 uuuuuuuu I2CADD 00000000 uuuuuuuu I2CBUF 00000000 uuuuuuuu u mean unknown or unchanged Rev. 1.4 22/146 FS98O22 3.3.2. IND and FSR Registers FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y The IND (Indirect Addressing) register is not a physical register, but indirect addressing needs the IND register. Any instruction using the IND register actually accesses the register pointed by the FSR (File Select Register). While user reads data from the IND register, the CPU gets the data from the Data Memory at the address stored in FSR. While user writes the data into IND register, CPU actually saves the data into Data Memory at the address stored in FSR. Please see Figure 3-2. Figure 3-2 IND & FSR function description Rev. 1.4 23/146 FS98O22 3.3.3. STATUS Register The STATUS register contains the arithmetic status of ALU and the RESET status. The STATUS register is similar to other registers, and can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bit, then the writing to these three bits is disabled. These bits are set or cleared according to the device logic. The TO and PD bits are not writable. Register STATUS at address 04H R/W-0 R/W-0 STATUS IRP1 IRP0 U-X R-0 R-0 R/W-X R/W-X R/W-X PD TO DC C Z FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y property Bit7 Bit 7 Bit0 IRP1: Indirect address 1 page select 1 = Indirect address 1 extend memory address is set (Memory 1XXH) 0 = Indirect address 1 extend memory address is Not set (Memory 0XXH) Bit 6 IRP0: Indirect address 0 page select 1 = Indirect address 0 extend memory address is set (Memory 1XXH) 0 = Indirect address 0 extend memory address is Not set (Memory 0XXH) Bit 4 PD: Power down Flag. 1 = By execution of SLEEP instruction 0 = After power-on reset Bit 3 TO: Watch Dog Time Out Flag. Cleared by writing 0 and Set by Watch Dog Time Out 1 = A Watch Dog Timer time-out occurred 0 = After power-on reset Bit 2 DC: Digit Carry Flag/borrow Flag, for ADDWFI and SUBWFI (for borrow the polarity is reversed) th 1 = If there is a carry out from the 4 bit of the result th 0 = No carry out from the 4 bit of the result Bit 1 C: Carry Flag/borrow Flag (~Borrow) (for borrow the polarity is reversed) 1 = If there is a carry out from the Most Significant bit of the result 0 = No carry out from the most significant bit of the result Bit 0 Z: Zero Flag 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is NOT zero Rev. 1.4 24/146 FS98O22 3.3.4. INTE and INTF registers The INTE and INTF registers are readable and writable registers, and contain enable and flag bits for interrupt devices. Register INTE at address 07H property R/W-0 INTE GIE U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMIE I2CIE ADIE E1IE E0IE Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit7 Bit 7 GIE: Global Interrupt Enable flag 1 = Enable all unmasked interrupts 0 = Disable all interrupts Bit 4 TMIE: 8-bit Timer Interrupt Enable flag 1 = Enable Timer interrupt 0 = Disable Timer interrupt Bit 3 I2CIE: I2C Interface Interrupt Enable flag 1 = Enable I2C interface interrupt 0 = Disable I2C interface interrupt Bit 2 ADIE: Analog to Digital converter Interrupt Enable flag 1 = Enable analog to digital converter interrupt 0 = Disable analog to digital converter interrupt Bit 1 E1IE: PT2.1 External Interrupt Enable flag 1 = Enable PT2.1 external interrupt 0 = Disable PT2.1 external interrupt Bit 0 E0IE: PT2.0 External Interrupt Enable flag 1 = Enable PT2.0 external interrupt 0 = Disable PT2.0 external interrupt property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 25/146 FS98O22 Register INTF at address 06H property U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMIF I2CIF ADIF E1IF E0IF INTF Bit7 TMIF: 8-bit Timer Interrupt Flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 4 Bit0 1 = Timer interrupt occurred (must be cleared in software) 0 = No Timer interrupt Bit 3 I2CIF: I2C Interface Interrupt Flag 1 = I2C Interface interrupt occurred (must be cleared in software) 0 = No I2C Interface interrupt Bit 2 ADIF: Analog to digital converter Interrupt Flag 1 = Analog to digital converter Interrupt occurred (must be cleared in software) 0 = No Analog to digital converter Interrupt Bit 1 E1IF: PT2.1 External Interrupt Flag 1 = PT2.1 External Interrupt occurred (must be cleared in software) 0 = No PT2.1 External Interrupt Bit 0 E0IF: PT2.0 External Interrupt Flag 1 = PT2.0 External Interrupt occurred (must be cleared in software) 0 = No PT2.0 External Interrupt property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit unknown is 26/146 FS98O22 3.4. Peripheral Special Registers The Peripheral Special Registers are designed for Peripheral functions, such as I/O ports, timer, ADC, signal conditional network control register, LCD driver. Please see Table 3-4 and the following Chapters for detailed description of these peripheral functions. Table 3-4 peripheral special registers table Address Referenced Section Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 08H 09H 0AH 0BH Value on Bit 2 Bit 1 Bit 0 Power on Reset CTAH 6.3 CTA[15:8] uuuuuuuu CTAL 6.3 CTA[7:0] uuuuuuuu CTBH 6.3 CTB[15:8] uuuuuuuu CTBL 6.3 CTB[7:0] uuuuuuuu FQT CTCON 6.3 TON MUXSEL[2:0] TE OVAB 0000000u MB WDTCON 6.2 WTDTEN WTS [2:0] 0uuuu000 TMOUT 6.1 TMOUT [7:0] 00000000 TMCON 6.1 TRST TMEN INS [2:0] 1uuu0000 ADOH 10/11 ADO [15:8] 00000000 ADOL 10/11 ADO [7:0] 00000000 ADOLL Extra ADC output register 00000000 ADCON 10/11 ADRST ADM [2:0] uuuu0000 MCK M2_C M1_C M0_ 00000000 5 M7_CK M6_CK M5_CK M3_CK K K CK PCK S_CH1CK S_BE S_P 00000000 4/5/7.5/10 ENPUMP [1:0] EP CK NETA 10/11 SINL[1:0] SINH[2:0] SFTA[2:0] 00000000 NETB 10/11 SOP1N[1:0] SVRL[1:0] SVRH[1:0] 00000000 NETC ADE 00000000 10/11 SREFO ADG[1:0] AZ N NETD 10/11 OP1EN SOP1P[2:0] 00000000 NETE 4/10/11 ENVS SILB[1:0] ENLB 00000000 NETF ENA ENV 00000000 4/10/11 ENBAND ENVDDA GND B SVD LBO uuuuuuuu 4.5 UT PT1 7 PT1 [7:0] uuuuuuuu PT1EN 7 PT1EN [7:0] 00000000 PT1PU 7 PT1PU [7:0] 00000000 AIENB1 7 AIENB[7:6] AIENB[5:0] 00000000 PT2 7 PT2 [7:0] uuuuuuuu PT2EN 7 PT2EN [7:0] 00000000 PT2PU 7 PT2PU [7:0] 00000000 PT2MR 7.2/7.5/8 BZEN PM2EN PM1EN E1M[1:0] E0M[1:0] 00000000 PT3 PT3 [7:0] uuuuuuuu PT3EN PT3EN [7:0] 00000000 PT3PU PT3PU [7:0] 00000000 PT3MR PFOEN E3M[1:0] E2M[1:0] 00000000 PMD1H 8 PMD1[15:8] 00000000 PMD1L 8 PMD1[7:0] 00000000 PMD2H PDMD2[15:8] 00000000 PMD2L PDMD2[7:0] 00000000 PMCON 8 PDMEN PMCS[2:0] 00000000 PT2OCB 9 PT2OC[4:3] uuu11uuu LCD1 13 SEG2 [3:0]] SEG1 [3:0] uuuuuuuu LCD2 13 SEG4 [3:0] SEG3 [3:0] uuuuuuuu LCD3 13 SEG6 [3:0] SEG5 [3:0] uuuuuuuu LCD4 13 SEG8 [3:0] SEG7 [3:0] uuuuuuuu LCD5 13 SEG10 [3:0] SEG9 [3:0] uuuuuuuu LCD6 13 SEG12 [3:0] SEG11 [3:0] uuuuuuuu LCD7 13 SEG14 [3:0] SEG13 [3:0] uuuuuuuu LCD8 13 SEG16 [3:0] SEG15 [3:0] uuuuuuuu LCD9 13 SEG18 [3:0] SEG17 [3:0] uuuuuuuu Name 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 18H 19H 1AH 1BH 1CH 1DH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 30H 31H 32H 33H 36H 37H 40H 41H 42H 43H 44H 45H 46H 47H 48H Rev. 1.4 27/146 FS98O22 Address Name Referenced Section 49H 54H LCD10 LCDENR 13 57H 58H 59H 5AH I2CCON I2CSTA I2CADD I2CBUF 9 9 9 9 Bit 6 Bit 5 Bit 4 SEG20 [3:0] LCDCKS [1:0] WCOL I2COV LCDEN I2CEN CKP DA P I2CADD [7:0] I2CBUF [7:0] Value on Bit 2 Bit 1 Bit 0 Power on Reset SEG19 [3:0] uuuuuuuu LCD_DUTY[ ENP 00000000 LEVEL 1:0] MPL 0001uuuu S RW BF uu0000u0 00000000 00000000 Bit 3 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 13 Bit 7 Rev. 1.4 28/146 FS98O22 4. Power System FS98O22 has a special power system that can supply a fixed voltage (3.6V) for CPU and ADC. FS98O22 could work when the supply voltage is within a specified range, fixed or floating. The power system has 6 function engines as Voltage Doubler, Voltage Regulator, Analog Bias Circuit, Common Voltage Generator Low Battery Comparator and Band gap Voltage / Temperature Sensor. Through the first 4 function engines, the system can generate 3 Voltage level as VGG = 2VDDP, VDDA = 3.6V, AGND = 1.8V. Please see Figure 4-1. Voltage Doubler The acceptable VDD range for FS98O22 is from 2.2V to 3.6V. Voltage Doubler raises the voltage of VGG 3 to 2 times of VDDP . VGG is used as the input of Voltage Regulator. It is from 4.4V to 7.2V. Please see Section 4.1 for detailed register setting. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1. 2. Voltage Regulator The fixed voltage is important when the Analog function is working. Voltage Regulator raises the voltage of VDDA to fixed 3.6V. Although the input voltage of Voltage Regulator, VGG, is from 4.4V to 7.2V (It depends on the voltage of VDD), the minimum possible voltage is still higher than 3.6V, so Voltage Regulator could surely supply VDDA as 3.6V. Please refer to Section 4.2 for detailed register setting. 3. Analog Bias Circuit Analog Bias Circuit is used to set VB to 3.6V. VB is used for FS98O22 Analog Function Network. The user needs to enable Analog Bias Circuit, and then the Analog Functions such as ADC or OPAMP can work correctly. Please refer to Section 4.3 for detailed register setting. 4. Common Voltage Generator FS98O22 sets the analog ground to half VDDA. Please refer to Section 4.4 for detailed register setting. Figure 4-1 FS98O22 power system block 3 VDDP means the VDD for Charge Pump (Voltage Doubler). User usually connects the VDDP to VDD. VSSP means the VSS for Charge Pump (Voltage Doubler). User usually connects the VSSP to VSS. Rev. 1.4 29/146 FS98O22 Table 4-1 FS98O22 power system register table Address Name 15H 1CH 1DH 1FH PCK NETE NETF SVD Referenced Section 4/5/7.5/10 4/10/11 4/10/11 4.5 Bit 7 Bit 6 Bit 5 ENPUMP ENBAND ENVDDA Bit 4 Bit 3 Bit 2 ENVS -SILB[1:0] Bit 1 Bit 0 -S_PCK ENLB ENAGND ENVB LBOUT Value on Power on Reset 00000000 00000000 00000000 uuuuuuuu FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register PCK at address 15H property U-0 R/W-0 U-0 U-0 U-0 ENPUM P PCK U-0 -- U-0 R/W-0 -- S_PCK Bit7 Bit 6 Bit0 ENPUMP: Voltage Doubler enabled flag 1 = Voltage Doubler is enabled 0 = Voltage Doubler is disabled Bit 0 S_PCK: Voltage Doubler operation frequency selector 1 = Voltage Doubler Operation Frequency = MCK/100 (Please see Chapter 5) 0 = Voltage Doubler Operation Frequency = MCK/200 (Please see Chapter 5) property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 30/146 FS98O22 Register NETE at address 1CH property U-0 U-0 U-0 NETE R/W-0 R/W-0 ENVS R/W-0 SILB[1:0] R/W-0 ENLB Bit7 Bit0 ENVS: VDDA Voltage Source enable flag (Please read Section 4.2 for detailed description) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 4 U-0 1 = VDDA is connected to VS. VS could be used as a voltage source. 0 = VDDA and VS are disconnected. Bit 3-2 SILB[1:0]: Low Battery Comparator Input Selector (Please refer to Section 4.5 for detailed description) 11 = No definition. The Low Battery Comparator Input is floating. 10 = Low Battery Comparator Input is selected as external analog input AIN4 01 = Low Battery Comparator Input is selected as 3.65V 00 = Low Battery Comparator Input is selected as 2.45V Bit 1 ENLB: Low Battery Comparator enable flag (Please refer to Section 4.5 for detailed description) 1 = Low Battery Comparator is enabled 0 = Low Battery Comparator is disabled property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 31/146 FS98O22 Register NETF at address 1DH property U-0 NETF R/W-0 R/W-0 ENBAND ENVDDA U-0 U-0 U-0 R/W-0 R/W-0 ENAGND ENVB Bit7 ENBAND: Band gap Voltage enable flag (Please refer to Section 4.6 for detailed description) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 6 Bit0 1 = The Band gap Voltage and Temperature Sensor are enabled, REFO to AGND is about 1.16V 0 = The Band gap Voltage and Temperature Sensor are disabled Bit 5 ENVDDA: Voltage Regulator enable flag (Please refer to Section 4.5 for detailed description) 1 = Voltage Regulator is enabled, VDDA is 3.6V 0 = Voltage Regulator is disabled. VDDA can be from external power supply. Bit 1 ENAGND: Analog Common Voltage Generator enable flag (Please see Section 4.4 for detailed description) 1 = Analog Common Voltage Generator is enabled. AGND = 1/2 VDDA 0 = Analog Common Voltage Generator is disabled. AGND is floating. Bit 0 ENVB: Analog Bias Circuit enable flag (Please see Section 4.3 for detailed description) 1 = Analog Bias Circuit is enabled. Analog system (ADC and OPAMP) can work correctly. 0 = Analog Bias Circuit is disabled. Analog system can NOT work Register SVD at address 1FH property U-X U-X U-X U-X U-X U-X U-X SVD LBOUT Bit7 Bit 0 R-X Bit0 LBOUT: Low Battery Comparator output (Please refer to Section 4.5 for detailed description) 1 = The Voltage selected by SILB[1:0] is higher than 1.2V. 0 = The Voltage selected by SILB[1:0] is lower than 1.2V property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 32/146 FS98O22 4.1. Voltage Doubler FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y C1 10uF Figure 4-2 Voltage Doubler 4 Voltage Doubler is used for generating VGG which provide input for VDDA Voltage Regulator. The inputs of Voltage Doubler are VDDP, VSSP, CA and CB. The related registers are S_PCK and ENPUMP. The Output is VGG. Please see Figure 4-2. Table 4-2 Voltage Doubler register table Address Name 14H 15H MCK PCK Referenced Section 5 4/5/7.5/10 Bit 7 M7_CK Bit 6 Bit 5 M6_CK M5_CK ENPUMP Bit 4 Bit 3 M3_CK Bit 2 -- Bit 1 Bit 0 M2_CK M1_CK M0_CK -S_PCK Value on Power on Reset 00000000 00000000 Operations: 1. 2. 3. 4. 5. 4 5 Connect the pins VDDP and VSSP to VDD (2.2V~3.6V) and VSS (system ground). Put a 10uF capacitance between CA and CB. 5 Select the Voltage Doubler Operation frequency by setting S_PCK and M0_CK according to the following table Set the ENPUMP flag. The output, VGG, will be 2 times of VDDP. Please refer to Section 4.2 for detailed description about VDDA and Voltage regulator. M0_CK is the 1st bit of the MCK register. Please refer to Section 5.0 Rev. 1.4 33/146 FS98O22 Table 4-3 Voltage Doubler operation frequency selection table M0_CK S_PCK Voltage Doubler Operation Frequency 0 0 MCK/200 0 1 MCK/100 1 X ECK/32 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y If the user doesn‟t want the VGG to be generated from the Voltage Doubler, then the ENPUMP should be set to disable the voltage Doubler, and input the VGG pin a voltage as voltage regulator power supply. Rev. 1.4 34/146 FS98O22 Voltage Regulator FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.2. Figure 4-3 Voltage regulator Voltage Regulator is used for generating VDDA (3.6V). The input is VGG which is generated by Voltage Doubler (please see the Section 4.1). The control Register flags are ENVDDA and ENVS. The Outputs are VDDA and VS. Please see Figure 4-3. Table 4-4 voltage regulator register table Address Name 1CH 1DH NETE NETF Referenced Section 4/10/11 4/10/11 Bit 7 Value on Power on Reset ENVS SILB[1:0] ENLB 00000000 ENBAND ENVDDA ENAGND ENVB 00000000 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Operations 1. 2. 3. 4. Operate as Section 4.1 to get the VGG (2 times of VDD or external Power Supply). Set the ENVDDA flag. The output, VDDA, is 3.6V. If the user wants VDDA as output voltage source, then the ENVS flag should be set. VS will be the same as VDDA. Rev. 1.4 35/146 FS98O22 Analog Bias Circuit FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.3. Figure 4-4 analog bias circuit Analog Bias Circuit is used to activate VB (reference VDDA) as the power supply voltage for analog circuit (include ADC, OPAMP, Low Battery Comparator) and LCD driver. The Control register flag is ENVB. Please see Figure 4-4. Table 4-5 analog bias circuit register table Address Name Referenced Section 1DH NETF 4/10/11 Bit 7 Bit 6 Bit 5 ENBAND ENVDDA Bit 4 Bit 3 Bit 2 Value on Bit 0 Power on Reset ENAGND ENVB 00000000 Bit 1 Operation: 1. 2. 3. 4. Operate as Section 4.1 to get the VGG (2 times of VDD or external Power Supply). Operate as Section 4.2 to get the VDDA (3.6V). Set the ENVB flag. The VB will be 3.6V (same as VDDA) and the analog function network and the LCD driver can be activate correctly. Note that Pin VB must be connected with a 10nF capacitor to VSS for reducing Voltage Doubler noise. Rev. 1.4 36/146 FS98O22 Analog Common Voltage Generator FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.4. Figure 4-5 analog common voltage generator 6 Analog Common Voltage Generator is used to provide a voltage at the halt of AGND as 1/2 VDDA . The Control register is ENAGND and the output is AGND. Please see Figure 4-5. Table 4-6 analog common voltage generator register table Address Name Referenced Section 1DH NETF 4/10/11 Bit 7 Bit 6 Bit 5 ENBAND ENVDDA Bit 4 Bit 3 Bit 2 Value on Bit 0 Power on Reset ENAGND ENVB 00000000 Bit 1 Operation: 1. 2. 3. 4. 5. 6 Operate following the steps Chapter 4.1 to get the VGG (2 times VDD or external Power Supply). Operate as Section 4.2 to get the VDDA (3.6V) Operate as Section 4.3 to activate the Analog Bias Circuit Set the ENAGND register flag. The output, AGND, will be 1/2 VDDA When VDDA is 3.6V, AGND would be 1.8V Rev. 1.4 37/146 FS98O22 Low Battery Comparator FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.5. Figure 4-6 low battery comparator function block Low Battery Comparator is used for VDD low voltage detection. FS98O22 embeds a voltage divider which can generate 1/2 VDD and the 1/3 VDD. A multiplexer is used to connect the voltage divides to component input. The multiplexer‟s output is compares with 1.2V. The Control register flags are SILB[1:0] and the ENLB. The Output flag is LBOUT which is for read only. Please see Figure 4-6. Table 4-7 low battery comparator register table Address Name 1CH 1FH NETE SVD Referenced Section 4/10/11 4.5 Bit 7 Bit 6 Bit 5 Bit 4 ENVS Bit 3 Bit 2 SILB[1:0] Bit 1 ENLB Bit 0 LBOUT Value on Power on Reset 00000000 uuuuuuuu Operation: 1. 2. 3. 4. Operate as Section 4.1 to get the VGG (2 times VDD or external Power Supply). Operate as Section 4.2 to get the VDDA (3.6V) Operate as Section 4.3 to active the Analog Bias Circuit Set SILB to choose the Comparator input. Please see Table 4-8 Table 4-8 low battery comparator voltage detection selection table 5. 6. SILB [1:0] Detection Voltage if LBOUT = 1 00 1/2 VDD VDD > 2.3 volt 01 1/3 VDD VDD > 3.5 volt 10 AIN AIN > 1.2 volt Set the ENLB register flag, and the Low Battery Comparator is enabled. The output, LBOUT, is the result of the comparator. Rev. 1.4 38/146 FS98O22 Bandgap Voltage and Temperature Sensor FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.6. Figure 4-7 Bandgap voltage and temperature sensor function block REFO is low temperature coefficient bandgap voltage reference output. Its voltage to AGND is 1.16V, and the typical temperature coefficient is 150ppm/C. FS98O22 embeds a Temperature Sensor to measure the IC temperature from the differential voltage between TEMPH and TEMPL (typically 550μV50μV/C). Its working range is 100 ~ 200 mV. User can connect the TEMPH and TEMPL to an ADC to get the IC temperature. Please refer to Chapter 10 and Chapter 11 for detailed instruction of ADC. Both the bandgap Voltage Reference and the Temperature sensor are controlled by ENBAND register flag. Please see Figure 4-7. Table 4-9 bandgap voltage and temperature sensor register table Referenced Bit 7 Bit 6 Section ENBAND NETF 4/10/11 Address Name 1DH Bit 5 ENVDDA Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ENAGND ENVB Value on Power on Reset 00000000 Operation: 1. 2. 3. 4. 5. 6. Operate as Section 4.1 to get the VGG (2 times VDD or external Power Supply). Operate as Section 4.2 to get the VDDA (3.6V) Operate as Section 4.3 to enable the Analog Bias Circuit Set the ENBAND register flag. Check REFO. Its value with respect to AGND should be about 1.16V The output, TEMPH and TEMPL, will show the IC temperature as the differential voltage. Rev. 1.4 39/146 FS98O22 5. Clock System Table 5-1 FS98O22 clock system register table Address Name MCK PCK 5 4/5/7.5/10 Bit 7 Bit 6 Bit 5 M7_CK M6_CK ENPUMP M5_CK Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M3_CK M2_CK M1_CK M0_CK S_CH1CK [1:0] S_BEEP S_PCK Value on Power on Reset 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 14H 15H Referenced Section Figure 5-1 FS98O22 clock system function block The clock system provides clock signals for the following 7 function blocks: Voltage Doubler, ADC, CPU core, OPAMP, Buzzer, Timer module and LCD. Users could use 10 register flags to generate all kinds of clock signals for the above 7 function blocks. These 10 register flags are M0_CK, M1_CK, M2_CK, M3_CK, M5_CK, M6_CK, M7_CK, S_PCK, S_CH1CK[1:0] and S_BEEP. The detailed setup will be illustrated in following sections. Please see Figure 5-1. Rev. 1.4 40/146 FS98O22 Oscillator State FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 5.1. Figure 5-2 FS98O22 oscillator state block Table 5-2 FS98O22 clock system register table Address Name 14H MCK Referenced Value on Power Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Section on Reset 5 M7_CK M6_CK M5_CK M3_CK M2_CK M1_CK M0_CK 00000000 There are two clock sources in FS98O22. One is the internal clock which generates 1 MHZ for CPU, and the other is an external one which provides 32768 HZ clock signal to the Chip. Users should choose one clock to use as MCK. Please see Figure 5-2. There are 2 clock signals working in FS98O22: MCK and CLK. Users should use Table 5-2 and 5-3 to setup MCK and CLK based on the M0_CK, M1_CK and M3_CK. Table 5-3 MCK selection table M3_CK M0_CK MCK X 0 ICK 0 1 ECK 1 1 ECK/2 Table 5-4 CLK selection table Rev. 1.4 M1_CK CLK 0 MCK 1 MCK/4 41/146 FS98O22 To enable the internal and external oscillators, users need to set the right values for M7_CK and M6_CK as shown in Table 5-4. If users execute the sleep instruction to make FS98O22 enter the SLEEP mode, both the internal oscillators and the external oscillator will be disabled. Table 5-5 oscillator state selection table Input Sleep instruction Oscillator State M7_CK M6_CK Internal External X Disable Disable 7 X FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 5.2. 0 0 0 Enable Enable 0 0 1 Enable Disable 0 1 0 Disable Enable 0 1 1 Enable Disable CPU Instruction Cycle Table 5-6 FS98O22 CPU instruction cycle register table Address Name 14H MCK Referenced Bit 7 Bit 6 Bit 5 Section 5 M7_CK M6_CK M5_CK Bit 4 Value on Power on Reset M3_CK M2_CK M1_CK M0_CK 00000000 Bit 3 Bit 2 Bit 1 Bit 0 8 User can setup M0_CK, M1_CK, M2_CK and M3_CK to select the instruction cycle . In order to maintain a stable ADC output, user could clear M2_CK to make CPU have a different operation clock cycle from ADC. In the applications where a resolution of ADC is more than 13 bits, M2_CK should be set to zero. Table 5-7 MCK selection table M3_CK M0_CK MCK X 0 ICK (1MHZ) 0 1 ECK (32768 HZ) 1 1 ECK/2 (16384HZ) Table 5-8 instruction cycle selection table M2_CK M1_CK Instruction Cycle 0 0 MCK/6.5 0 1 MCK/12.5 1 0 MCK/2 1 1 MCK/4 7 X means “don‟t care” Users must make sure that switching from one oscillator to the other can be made only after the oscillator ‟s output is stabilized. An NOP command should be added after the switching. 8 Rev. 1.4 42/146 FS98O22 5.3. ADC Sample Frequency FS98O22 embeds one sigma delta ADC which needs clock input to generate digital output. When users want N ADC have N bits resolution digital output, ADC needs 2 clocks cycles input. (Please refer to Chapter 10 and Chapter 11 for detailed description) User should setup the M1_CK to decide the ADC sample frequency. Please see Table 5-9. Table 5-9 ADC sample frequency selection table ADC sample Frequency (ADCF) 0 MCK/25 1 MCK/50 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y M1_CK Rev. 1.4 43/146 FS98O22 5.4. Beeper Clock Table 5-10 beeper clock register table Name 14H 15H MCK PCK Referenced Bit 7 Bit 6 Bit 5 Section 5 M7_CK M6_CK M5_CK ENPU 4/5/7.5/10 MP Bit 4 Value on Power on Reset M3_CK M2_CK M1_CK M0_CK 00000000 S_BEE 00000000 S_CH1CK [1:0] S_PCK P Bit 3 Bit 2 Bit 1 Bit 0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Address FS98O22 has a Beeper Clock which is used as the buzzer source. (Please refer to Section 7.5 for how to use Buzzer) User could change the Beeper clock frequency by setting M0_CK, M1_CK, M3_CK and S_BEEP register flags according to Table 5-11, Table 5-12 and Table 5-13. Table 5-11 MCK selection table M3_CK M0_CK MCK X 0 ICK 0 1 ECK 1 1 ECK/2 Table 5-12 CLK selection table M1_CK CLK 0 MCK 1 MCK/4 Table 5-13 beeper clock selection table Rev. 1.4 M0_CK S_BEEP Beeper Clock X 0 CLK/250 0 1 CLK/375 1 1 ECK/8 44/146 FS98O22 Table 5-14 shows the relation between clock signals and the register flags. Please see Table 5-14) Table 5-14 register and the beeper clock selection table M1_CK M3_CK S_BEEP MCK CLK beep clock 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 32768 16384 32768 16384 1000000 1000000 1000000 1000000 1000000 1000000 1000000 1000000 32768 16384 32768 16384 32768 16384 8192 4096 1000000 1000000 1000000 1000000 250000 250000 250000 250000 32768 16384 8192 4096 4096 4096 4096 4096 4000 4000 2666.6667 2666.6667 1000 1000 666.6667 666.6667 131.072 65.536 32.768 16.384 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y M0_CK 5.5. Voltage Doubler Operation Frequency FS98O22 embeds a switching voltage regulator. Users can use M0_CK and S_PCK register flags to decide the operation frequency as in Table 5-15 and Table 5-16. Table 5-15 MCK selection table M3_CK M0_CK MCK X 0 ICK 0 1 ECK 1 1 ECK/2 Table 5-16 Voltage Doubler operation frequency selection table Rev. 1.4 M0_CK S_PCK Voltage Doubler Operation Frequency 0 0 MCK/200 0 1 MCK/100 1 X ECK/32 (1024 HZ) 45/146 FS98O22 5.6. Chopper Operation Amplifier Input Control Signal The OPAMP embedded in FS98O22 has a chopper function to cancel the inverting and non-inverting sides voltage bias offsets. After the Chopper operation, OPAMP input voltage bias is removed. Users could setup the S_CH1CK[1:0] to choose the Chopper Control Signal. (Please see Table 5-17, Table 5-18 and Table 5-19) Table 5-17 CLK selection table M1_CK FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y CLK 0 MCK 1 MCK/4 Table 5-18 MCK selection table M3_CK M0_CK MCK X 0 ICK 0 1 ECK 1 1 ECK/2 Table 5-19 chopper control signal selection table Rev. 1.4 S_CH1CK [1] S_CH1CK [0] Chopper Control Signal 0 0 0 0 1 1 1 0 CLK/500 1 1 CLK/1000 46/146 FS98O22 5.7. TMCLK – Timer and LCD Module Input Clock TMCLK is the clock for FS98O22 Timer and LCD Module. Users can use Table 5-20 to choose TMCLK frequency by setting the right values for M5_CK. Table 5-20 TMCLK selection table TMCLK (Timer and LCD Module input Clock) 0 CLK/1000 1 ECK/32 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y M5_CK Rev. 1.4 47/146 FS98O22 6. Timer Module, Watch Dog Timer and Programmable Counter Table 6-1 Timer module and watch dog timer register table Address Value on Power on Reset 00u00uuu 00000000 00000000 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 0000000u 0uuuu000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 04H 06H 07H 08H 09H 0AH 0BH 0CH 0DH Referenced Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Section STATUS 1.11/3.4.2 -TO ---INTF 3/6/7/9/10/11 TMIF ----INTE 3/6/7/9/10/11 GIE TMIE ----CTAH 6.3 CTA[15:8] CTAL 6.3 CTA[7:0] CTBH 6.3 CTB[15:8] CTBL 6.3 CTB[7:0] CTCON 6.3 TON MUXSEL[2:0] TE FQTMB OVAB WDTCO 6.2 WDTEN WTS [2:0] N TMOUT 6.1 TMOUT [7:0] TMCON 6.1 TRST TMEN INS [2:0] Name 0EH 0FH 00000000 1uuu0000 The Registers are described as follows. Register CTAH at address 08H property R –X R-X R-X CTAH R-X R-X R-X R-X R-X CTA[15:8] Bit7 Bit0 Register CTAL at address 09H property R-X R-X R-X CTAL R-X R-X R-X R-X CTA[7:0] Bit7 Bit 15-0 R-X Bit0 CTA[15:0]: Programmable Counter 16-bit Counter A register (Please refer to Section 6.3 for detail) property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 48/146 FS98O22 Register CTBH at address 0AH property R/W-X R/W-X R/W-X CTBH R/W-X R/W-X R/W-X R/W-X R/W-X CTB[15:8] Bit7 Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register CTBL at address 0BH property R/W-X R/W-X R/W-X CTBL R/W-X R/W-X R/W-X R/W-X CTB[7:0] Bit7 Bit 15-0 R/W-X Bit0 CTB[15:0]: Programmable Counter 16-bit Counter B register (Please refer to Section 6.3 for detail) property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 49/146 FS98O22 Register CTCON at address 0CH property R/W-0 CTCON TON R/W-0 R/W-0 R/W-0 MUXSEL[2:0] R/W-0 R/W-0 R/W-0 R/W-X TE FQTMB OVAB -- Bit7 Bit 7 Bit0 TON: 16-bit Counter input signal switch (Please refer to Section 6.2 for detail) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 = The 16-bit Counter input signal switch is ON. 0 = The 16-bit Counter input signal switch is OFF. Bit 6 MUXSEL[2]: Programmable Counter Counter/Pulse Width measurement mode selector. 1 = Programmable Counter is used as Pulse Width measurement. 0 = Programmable Counter is used as General Counter. Bit 5-4 MUXSEL[1:0]: Counter A clock source select multiplexer 1. 11 = PFI, GPIO 3 port 2. 10 = ECK, External Clock (32768HZ) 01 = Instruction clock, please see Section 5.2 00 = ICK, Internal Clock (1MHZ) Bit 3 TE: PFI signal inverting register 1 = PFI signal is inverted 0 = PFI signal is NOT inverted Bit 2 FQTMB: Programmable Counter Frequency measurement mode enabled register flag. 1 = Programmable Counter is used as Frequency measurement. 0 = Programmable Counter is used as General Counter or Pulse Width measurement. Bit 1 OVAB: Programmable Counter interrupt source selector 1 = Programmable Counter interrupt source is Counter A. 0 = Programmable Counter interrupt source is Counter B. property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 50/146 FS98O22 Register WDTCON at address 0DH property R/W-0 WDTCON U-X U-X U-X U-X R/W-0 WDTEN R/W-0 WTS [2:0] Bit7 Bit0 WDTEN: Watch Dog Timer enable flag (Please refer to Section 6.2 for detail) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7 R/W-0 1 = Watch Dog Timer is enabled. 0 = Watch Dog Timer is disabled Bit 2-0 WTS [2:0]: Watch Dog Timer counter 2 Input Selector (Please refer to Chapter 6.2 for details) 111 = Watch Dog Timer Counter 2 Input is WDTA[0] 110 = Watch Dog Timer Counter 2 Input is WDTA[1] 101 = Watch Dog Timer Counter 2 Input is WDTA[2] 100 = Watch Dog Timer Counter 2 Input is WDTA[3] 011 = Watch Dog Timer Counter 2 Input is WDTA[4] 010 = Watch Dog Timer Counter 2 Input is WDTA[5] 001 = Watch Dog Timer Counter 2 Input is WDTA[6] 000 = Watch Dog Timer Counter 2 Input is WDTA[7] property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 51/146 FS98O22 Register TMOUT at address 0EH property R-0 R-0 R-0 R-0 TMOUT R-0 R-0 R-0 TMOUT [7:0] Bit7 Bit0 TMOUT [7:0]: Timer module 8-bit counter output (Please refer to Section 6.1 for detail) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-0 R-0 Register TMCON at address 0FH property R/W-1 TMCON TRST U-X U-X U-X R/W-0 R/W-0 TMEN R/W-0 INS [2:0] Bit7 Bit 7 R/W-0 Bit0 TRST: Timer Module reset flag (Please refer to Section 6.1 for detail) 1 = Timer Module Counter works normally. 0 = Timer Module Counter is reset.(After resetting the Counter, TRST will reset itself) Bit 3 TMEN: Timer Module enable flag (Please refer to Section 6.1 for detail) 1 = Timer Module Counter will active. 0 = Timer Module Counter will be disabled. Bit 2-0 INS [2:0]: Timer Module interrupt Signal Selector (Please refer to Chapter 6.1 for detail) 111 = TMOUT[7] is selected as Timer Module interrupt Signal 110 = TMOUT[6] is selected as Timer Module interrupt Signal 101 = TMOUT[5] is selected as Timer Module interrupt Signal 100 = TMOUT[4] is selected as Timer Module interrupt Signal 011 = TMOUT[3] is selected as Timer Module interrupt Signal 010 = TMOUT[2] is selected as Timer Module interrupt Signal 001 = TMOUT[1] is selected as Timer Module interrupt Signal 000 = TMOUT[0] is selected as Timer Module interrupt Signal property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared X = Bit is unknown There are two timers in FS98O22: Timer Module and Watch Dog Timer. Please see the following sections for detail. Rev. 1.4 52/146 FS98O22 6.1. Timer Module The Timer module has the following features: 8-bit Timer Counter Internal (1 MHZ) or External (32768HZ) clock selection Time out Interrupt Signal selection FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y TMOUT[7:0] TMEN EN Out 8 to 1 Mux Timer Interrupt Signal 8 bits Counter TMCLK Frequency Divider TMCLK/4 CK Reset TMRST Figure 6-1 FS98O22 timer module function block Please see Figure 6-1. The input of Timer Module is TMCLK. (Please refer to Section 5.7 for the detailed setting) FS98O22 embeds a Frequency Divider in the Timer Module to divide the TMCLK by 4, and treats the divided clock signal as 8-bit counter input clock. When a user sets the Timer Module enable flag, the 8-bit counter will activate, and the TMOUT[7:0] will increase from 0x00H to 0xFFH. User needs to setup INS (Timer Module interrupt Signal Selector) to select the time out interrupt signal. When timer out event happens, the interrupt Flag will set itself and the program counter will jump to 0x04H for ISR (Interrupt Service Routine) Rev. 1.4 53/146 FS98O22 6.1.1. Timer module interrupt Table 6-2 timer module interrupt register table Address 06H 07H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMIF -- -- -- -- TMIE -- -- -- -- TMOUT [7:0] TMEN Value on Power on Reset 00000000 00000000 00000000 1uuu0000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 0EH 0FH Referenced Bit 7 Section INTF 3/6/7/9/10/1 1 INTE 3/6/7/9/10/1 GIE 1 TMOUT 6.1 TMCON 6.1 TRST Name INS [2:0] Operation: 1. 2. 3. 4. 5. 6. Operate as Section 5.7 to setup the TMCLK for Timer module input Setup the INS[2:0] to select timer interrupt source. Please see Table 6-3. Set the TMIE and GIE register flags to enable the Timer interrupt. Set the TMEN register flag to enable Timer module 8-bit counter. Clear the TRST register flag to reset the Timer module 8-bit counter When time out event happens, TMIF register flag will reset itself, and the program counter will reset to 0x04H Table 6-3 timer selection table Rev. 1.4 INS[2:0] interrupt source Time at TMCLK=1024Hz (ECK/32) 000 TMOUT[0] 1/128 sec. 001 TMOUT[1] 1/64 sec. 010 TMOUT[2] 1/32 sec. 011 TMOUT[3] 1/16 sec. 100 TMOUT[4] 1/8 sec. 101 TMOUT[5] 1/4 sec. 110 TMOUT[6] 1/2 sec. 111 TMOUT[7] 1 sec. 54/146 FS98O22 6.1.2. Using Timer with External/Internal Clock The user could see the Table 6-4, 6-5, 6-6 and 6-7 to setup related registers to decide the clock source. Table 6-4 external timer setup register table Address Name 14H MCK Detail on Chapter 5 Bit 7 Bit 6 Bit 5 Bit 4 M7_CK M6_CK M5_CK Value on Power on Reset M3_CK M2_CK M1_CK M0_CK 00000000 Bit 3 Bit 2 Bit 1 Bit 0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Table 6-5 CLK selection table M1_CK CLK 0 MCK 1 MCK/4 Table 6-6 MCK selection table M3_CK M0_CK MCK X 0 ICK 0 1 ECK 1 1 ECK/2 Table 6-7 TMCLK selection table Rev. 1.4 M5_CK TMCLK (Timer and LCD Module input Clock) 0 CLK/1000 1 ECK/32 55/146 FS98O22 Users can use Table 6-8 to select TMCLK clock source based on M0_CK, M1_CK, M3_CK and M5_CK register flag. Table 6-8 registers and timer selection table M1_CK M3_CK M5_CK MCK CLK TMCLK 0 0 0 1 1000000 1000000 1024 0 0 1 1 1000000 1000000 1024 0 1 0 1 1000000 500000 1024 0 1 1 1 1000000 500000 1024 1 0 0 1 32768 32768 1024 1 1 0 1 32768 16384 1024 1 0 1 1 16384 16384 1024 1 1 1 1 16384 8192 1024 0 0 0 0 1000000 1000000 1000 0 0 1 0 1000000 1000000 1000 0 1 0 0 1000000 500000 500 0 1 1 0 1000000 500000 500 1 0 0 0 32768 32768 32.768 1 1 0 0 32768 16384 16.384 1 0 1 0 16384 16384 16.384 1 1 1 0 16384 8192 8.192 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y M0_CK Rev. 1.4 56/146 FS98O22 6.2. Watch Dog Timer Watch Dog Timer Oscillator WDTA[7:0] 8 bits Counter1 Multiplex 8 bits Counter2 WDTOUT FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y WDTEN WDTS[2:0] CLRWDT Figure 6-2 watch dog timer function block Please see Figure 6-2. WDT (Watch Dog Timer) is used to prevent the program from being out of control by any uncertain reason. When WDT is active, it will reset the CPU when the WDT timeout. Generally, the program run in FS98O22 needs to reset the WDT before the WDT times out every time to reset the CPU. When some trouble happens, the program will be reset to the general situation by WDT and the program won‟t reset the WDT in that situation. The input of Watch Dog Timer is WDTEN and WDTS[2:0] register flags. The output of Watch Dog Timer is TO register flag. When a user sets the WDTEN, the embedded Watch Dog Timer Oscillator (3 KHZ) will become active, and the generated clock will be pushed into the “8-bit counter 1” as shown in Figure 6-2. The output of the “8-bit counter 1”, WDTA[7:0], is a virtual signal which is sent to one multiplexer. The multiplexer is controlled by the register flags, WDTS[2:0]. The output signal is used as the “8-bit Counter 2” clock input. When “8-bit Counter 2” overflows, it will send WDTOUT to reset the CPU (Program Counter will jump to 0x00H to reset the program) and set TO flag. Users could reset the WDT by the instruction – CLRWDT. Table 6-9 watch dog timer register table Address Name 04H 0DH STAT US WDT CON Referenced Section Bit 7 Bit 6 Bit 5 1.11/3.4.2 6.3 Bit 4 Bit 3 -- TO Bit 2 Bit 1 WDTEN -- Bit 0 -- WDTS [2:0] -- Value on Power on Reset 00u00uuu 0uuuu000 Operation: 1. Setup the WDTS[2:0] to decide the WDT timeout frequency. 2. Set WDTEN register flag to enable the WDT. 3. Process the CLRWDT instruction to reset the WDT in the program. Rev. 1.4 57/146 FS98O22 6.3. Dual 16-bit Programmable Counter Content ( u mean unknown or unchanged) CTIF CTIE CTA[15:8] CTA[7:0] CTB[15:8] CTB[7:0] MUXSEL[2:0] TE FQTMB PFOEN - - - Reset State 00000000 00000000 00000000 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 0000000u 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Address Name 07H INTE GIE 16H INTF2 17H INTE2 08H CTAH 09H CTAL 0AH CTBH 0BH CTBL 0CH CTCON TON 2BH PT3MR OVAB - Figure 6-3 Programmable Counter Working block diagram FS98O22 embeds Dual 16-bit Programmable Counter. It could be used under three working modes: Counter mode, Pulse Width Measurement mode and Frequency Measurement mode. Users could setup MUXSEL[2] and FQTMB register flags to deice the working mode. Table 6-10 Programmable Counter working mode selection table Working mode Counter mode Pulse Width Measurement mode Frequency Measurement mode NONE Rev. 1.4 MUXSEL[2] 0 1 0 1 FQTMB 0 0 1 1 58/146 FS98O22 Counter mode: There are two 16-bit counters (CTA and CTB) in Programmable Counter unit. Operation: 1. 2. Clear FQTMB and MUXSEL[2] register flags to make the Programmable Counter work as Counter. Setup MUXSEL[1:0] to decide the input clock signal. Table 6-11 Programmable Counter Clock signal selection table Clock signal PFI ECK Instruction Cycle ICK FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y MUXSEL[1:0] 11 10 01 00 3. 4. 5. 6. 7. 8. 9. If PFI is assigned to be the Clock signal, users could set TE to invert the PFI voltage level. Clear OVAB register flag to set the CTA as the working counter. When CTA counter overflows, the interrupt (CTIE) will be triggered. Clear CTIF and set the CTIE and GIE register flag to enable the Programmable Counter interrupt. Setup CTB[15:0]. CTA[15:0] will be filled with the same value as CTB[15:0]. When CTA[15:0] overflows, it will be filled with the same value again. User could decide CTA timeout by setting up CTB[15:0] register. Set TON to start the counter. When CTA counter overflows, the interrupt will be triggered. Users could clear TON register flag to stop the counting process. CLK TON Software Set Software Clear CTA_CLK CTA XXXX FFF9 CTB XXXX FFF9 FFFA FFFB FFFC FFFD FFFE FFFF FFF9 FFFA 0 1 X FFFC FFFD FFFE FFFF FFFA FFFB FFFC FFFD FFFE FFFF FFFA FFFB FFFC FFFA Software Write into CTB (CTA same as CTB) INT FFFB 1 Software Write into CTB CTIF When CTIE=1 Software Clear Software no Clear Figure 6-4 Programmable Counter/TimerCounter Mode Counter mode Rev. 1.4 59/146 FS98O22 Pulse Width Measurement mode: Programmable Counter could be used to measure the time when a signal holds its voltage level in high or low. Operation: 1. 2. 3. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4. Clear FQTMB and clear MUXSEL[2] register flags to make the Programmable Counter work as Pulse Width Measurement. Setup MUXSEL[1:0] to decide the input clock signal. PFI is the signal which is ready to measure the pulse width. Users could set TE to invert the PFI voltage level. Clear OVAB register flag to set the CTA as the working counter. When CTA counter overflows, the interrupt (CTIE) will be triggered. Clear CTIF and set the CTIE and GIE register flags to enable the Programmable Counter interrupt. Setup CTB[15:0]. CTA[15:0] will be filled with the same value as CTB[15:0]. When CTA[15:0] overflows, it will be filled with the same value again. User could decide CTA timeout by setting up CTB[15:0] register. Set TON to start the Pulse Width Measurement. When PFI signal is from high to low, CTA counter will stop counting and clear TON register flag. Interrupt will be triggered at the same time. Users could read the CTA counter value to know the pulse width of PFI. If CTA counter overflows, and the PFI signal is still high, the interrupt will be triggered, but CTA will count again. 5. 6. 7. 8. 9. CLK TON Software Set PFII CTA_CLK CTA XXXX 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 Software Write into CTB (CTA same as CTB) INT X 1 CTIF When CTIE=1 Figure 6-5 Programmable Counter Pulse Width Measurement mode Pulse Width Measurement Mode Rev. 1.4 60/146 FS98O22 Frequency Measurement mode: Programmable Counter could be used to measure a signal frequency. Operation: 1. 2. 3. 4. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 5. 6. Set FQTMB and clear MUXSEL[2] register flags to make the Programmable Counter work as Frequency Measurement. Setup MUXSEL[1:0] to decide the input clock signal. PFI is the signal which is ready to measure the frequency. Users could set TE to invert the PFI voltage level. Clear OVAB register flag to set the CTA as the working counter. When CTA counter overflows, the interrupt (CTIE) will be triggered. Clear CTIF and set the CTIE and GIE register flags to enable the Programmable Counter interrupt. Setup CTB[15:0]. CTA[15:0] will be filled with the same value as CTB[15:0]. When CTA[15:0] overflows, it will be filled with the same value again. User could decide CTA timeout by setting up CTB[15:0] register. Set TON to start the Frequency Measurement. When CTA counter overflows, the interrupt will be triggered. TON register flag will be clear automatically. Users could read the CTB value to know the PFI signal frequency. 7. 8. 9. CLK PFII TON Software Set CTA_CLK CTB_CLK FQTMB CTA XXXX FFEA CTB XXXX FFEA FFEB FFEC FFED FFEB FFEE FFEF FFEC FFF0 FFF1 FFF2 FFED FFF3 FFF4 FFEE FFF5 FFF6 FFF7 FFEF FFF8 FFF9 FFF0 FFFA FFFB FFFC FFFD FFF1 FFFE FFFF 0000 FFF2 Software Write into CTB (CTA same as CTB) INT X 1 CTIF When CTIE=1 Frequency Measurement Mode Figure 6-6 Programmable Counter Frequency Measurement mode Rev. 1.4 61/146 FS98O22 7. I/O Port Table 7-1 FS98O22 I/O port register table Address Name INTF INTE INTF2 INTE2 PT1 PT1EN PT1PU AIENB1 PT2 PT2EN PT2PU PT2MR PT3 PT3EN PT3PU PT3MR PT2OC B Bit 7 Bit 6 Bit 5 GIE Bit 4 Bit 3 --- I2CIF I2CIE Bit 2 Bit 1 --- PT1 [7:0] PT1EN [7:0] PT1PU [7:0] AIENB[5:0] PT2 [7:0] PT2EN [7:0] PT2PU [7:0] PM1EN E1M[1:0] PT3 [7:0] PT3EN [7:0] PT3PU [7:0] PFOEN E3M[1:0] E1IF E1IE E3IF E3IE Bit 0 E0IF E0IE E2IF E2IE Value on Power on Reset 00000000 00000000 00000000 00000000 uuuuuuuu 00000000 00000000 00000000 uuuuuuuu 00000000 00000000 00000000 uuuuuuuu 00000000 00000000 00000000 uuu11uuu FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 06H 07H 16H 17H 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 37H Detail on Chapter 3/6/7/9/10/11 3/6/7/9/10/11 6/7 6/7 7 7 7 7 7 7 7 7.2/7.5/8 9 AIENB[7:6] BZEN PT2OC[4:3] E0M[1:0] E2M[1:0] The GPIO (General Purpose Input Output) in a micro-controller is used for general purpose input or output function. Users could use these ports to get digital signal or transmit data to any other digital device. Some GPIOs in FS98O22 are also defined for other special functions. In this Chapter, the GPIO will be illustrated as the GPIO function. The special functions defined in the GPIO will be illustrated in the following Chapters. Rev. 1.4 62/146 FS98O22 Register PT1 at address 20H property R/W-X R/W-X R/W-X PT1 R/W-X R/W-X R/W-X R/W-X R/W-X PT1 [7:0] Bit7 Bit 7-0 Bit0 PT1[7:0]: GPIO Port 1 data flag (Please refer to Section 7.1 for detail) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT1[7] = GPIO Port 1 bit 7 data flag PT1[6] = GPIO Port 1 bit 6 data flag PT1[5] = GPIO Port 1 bit 5 data flag PT1[4] = GPIO Port 1 bit 4 data flag PT1[3] = GPIO Port 1 bit 3 data flag PT1[2] = GPIO Port 1 bit 2 data flag PT1[1] = GPIO Port 1 bit 1 data flag PT1[0] = GPIO Port 1 bit 0 data flag Register PT1EN at address 21H property R/W-0 R/W-0 R/W-0 PT1EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PT1EN [7:0] Bit7 Bit 7-0 Bit0 PT1EN [7:0]: GPIO Port 1 Input / Output control flag (Please refer to Section 7.1 for detail) PT1EN[7] = GPIO Port 1 bit 7 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT1EN[6] = GPIO Port 1 bit 6 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT1EN[5] = GPIO Port 1 bit 5 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT1EN[4] = GPIO Port 1 bit 4 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT1EN[3] = GPIO Port 1 bit 3 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT1EN[2] = GPIO Port 1 bit 2 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT1EN[1] = GPIO Port 1 bit 1 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT1EN[0] = GPIO Port 1 bit 0 I/O control flag ; 0 = defined as input port, 1 = defined as output port property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared X = Bit is unknown Register PT1PU at address 22H Rev. 1.4 63/146 FS98O22 property R/W-0 R/W-0 R/W-0 PT1PU R/W-0 R/W-0 R/W-0 Bit0 PT1PU [7:0]: GPIO Port 1 Pull up resistor enable flag (Please refer to Section 7.1 for detail) PT1EN[7] = GPIO Port 1 bit 7 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y resistor R/W-0 PT1PU [7:0] Bit7 Bit 7-0 R/W-0 resistor resistor resistor resistor resistor resistor resistor PT1EN[6] = GPIO Port 1 bit 6 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT1EN[5] = GPIO Port 1 bit 5 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT1EN[4] = GPIO Port 1 bit 4 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT1EN[3] = GPIO Port 1 bit 3 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT1EN[2] = GPIO Port 1 bit 2 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT1EN[1] = GPIO Port 1 bit 1 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT1EN[0] = GPIO Port 1 bit 0 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 64/146 FS98O22 Register AIENB1 at address 23H property R/W-0 R/W-0 R/W-0 AIENB1 R/W-0 R/W-0 R/W-0 R/W-0 AIENB[7:0] Bit7 Bit0 AIENB1[7:0]: GPIO Port 1 Analog / Digital control flag (Please refer to Section 7.1 for detail) AIENB1[7] = GPIO Port 1 bit 7 D/A flag ; 0 = defined as Analog channel, 1 = defined as Digital FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-0 R/W-0 channel channel AIENB1[6] = GPIO Port 1 bit 6 D/A flag ; 0 = defined as Analog channel, 1 = defined as Digital AIENB1[5] = GPIO Port 1 bit 5 D/A flag ; 0 = defined as Analog channel, 1 = defined as Digital channel channel channel channel channel channel AIENB1[4] = GPIO Port 1 bit 4 D/A flag ; 0 = defined as Analog channel, 1 = defined as Digital AIENB1[3] = GPIO Port 1 bit 3 D/A flag ; 0 = defined as Analog channel, 1 = defined as Digital AIENB1[2] = GPIO Port 1 bit 2 D/A flag ; 0 = defined as Analog channel, 1 = defined as Digital AIENB1[1] = GPIO Port 1 bit 1 D/A flag ; 0 = defined as Analog channel, 1 = defined as Digital AIENB1[0] = GPIO Port 1 bit 0 D/A flag ; 0 = defined as Analog channel, 1 = defined as Digital property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 65/146 FS98O22 Register PT2 at address 24H property R/W-X R/W-X R/W-X PT2 R/W-X R/W-X R/W-X R/W-X PT2 [7:0] Bit7 Bit 7-0 R/W-X Bit0 PT2[7 :0] : GPIO Port 2 data flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT2[7] = GPIO Port 2 bit 7 data flag PT2[6] = GPIO Port 2 bit 6 data flag PT2[5] = GPIO Port 2 bit 5 data flag PT2[4] = GPIO Port 2 bit 4 data flag PT2[3] = GPIO Port 2 bit 3 data flag PT2[2] = GPIO Port 2 bit 2 data flag PT2[1] = GPIO Port 2 bit 1 data flag PT2[0] = GPIO Port 2 bit 0 data flag property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 66/146 FS98O22 Register PT2EN at address 25H property R/W-0 R/W-0 R/W-0 PT2EN R/W-0 R/W-0 R/W-0 R/W-0 PT2EN [7:0] Bit7 Bit 7-0 R/W-0 Bit0 PT2EN [7 :0] : GPIO Port 2 Input / Output control flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT2EN[7] = GPIO Port 2 bit 7 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT2EN[6] = GPIO Port 2 bit 6 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT2EN[5] = GPIO Port 2 bit 5 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT2EN[4] = GPIO Port 2 bit 4 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT2EN[3] = GPIO Port 2 bit 3 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT2EN[2] = GPIO Port 2 bit 2 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT2EN[1] = GPIO Port 2 bit 1 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT2EN[0] = GPIO Port 2 bit 0 I/O control flag ; 0 = defined as input port, 1 = defined as output port property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 67/146 FS98O22 Register PT2PU at address 26H R/W-0 R/W-0 R/W-0 PT2PU R/W-0 R/W-0 R/W-0 R/W-0 PT2PU [7:0] Bit7 Bit0 PT2PU [7:0]: GPIO Port 2 Pull up resistor enable flag PT2PU[7] = GPIO Port 2 bit 7 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-0 R/W-0 resistor resistor resistor resistor resistor resistor resistor resistor PT2PU[6] = GPIO Port 2 bit 6 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up PT2PU[5] = GPIO Port 2 bit 5 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up PT2PU[4] = GPIO Port 2 bit 4 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up PT2PU[3] = GPIO Port 2 bit 3 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up PT2PU[2] = GPIO Port 2 bit 2 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up PT2PU[1] = GPIO Port 2 bit 1 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up PT2PU[0] = GPIO Port 2 bit 0 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 68/146 FS98O22 Register PT2MR at address 27H property R/W-0 PT2MR BZEN U-0 U-0 R/W-0 PM1EN R/W-0 R/W-0 E1M[1:0] R/W-0 E0M[1:0] Bit7 Bit 7 R/W-0 Bit0 BZEN: Buzzer enable flag (Please refer to Section 7.5 for detail) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 = Buzzer function is enabled, GPIO Port 2 bit 7 is defined as Buzzer output. 0 = Buzzer function is disabled, GPIO Port 2 bit 7 is defined as GPIO. Bit 4 PM1EN: PDM Module enable flag (Please refer to Chapter 8 for detail) 1 = PDM Module is enabled, GPIO Port 2 bit 2 is defined as PDM output. 0 = PDM Module is disabled, GPIO Port 2 bit 2 is defined as GPIO. Bit 3-2 E1M[1:0]: GPIO Port 2 bit 1 interrupt trigger mode (Please refer to Section 7.2 for detail) 11 = External Interrupt 1 (GPIO Port 2 bit 1) is triggered at state change 10 = External Interrupt 1 (GPIO Port 2 bit 1) is triggered at state change 01 = External Interrupt 1 (GPIO Port 2 bit 1) is triggered at positive edge 00 = External Interrupt 1 (GPIO Port 2 bit 1) is triggered at negative edge Bit 1-0 E0M[1:0]: GPIO Port 2 bit 0 interrupt trigger mode (Please refer to Section 7.2 for detail) 11 = External Interrupt 0 (GPIO Port 2 bit 0) is triggered at state change 10 = External Interrupt 0 (GPIO Port 2 bit 0) is triggered at state change 01 = External Interrupt 0 (GPIO Port 2 bit 0) is triggered at positive edge 00 = External Interrupt 0 (GPIO Port 2 bit 0) is triggered at negative edge property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 69/146 FS98O22 Register PT3 at address 28H property R/W-X R/W-X R/W-X PT3 R/W-X R/W-X R/W-X R/W-X PT3 [7:0] Bit7 Bit0 PT3[7 :0] : GPIO Port 3 data flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-0 R/W-X PT3[7] = GPIO Port 3 bit 7 data flag PT3[6] = GPIO Port 3 bit 6 data flag PT3[5] = GPIO Port 3 bit 5 data flag PT3[4] = GPIO Port 3 bit 4 data flag PT3[3] = GPIO Port 3 bit 3 data flag PT3[2] = GPIO Port 3 bit 2 data flag PT3[1] = GPIO Port 3 bit 1 data flag PT3[0] = GPIO Port 3 bit 0 data flag property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 70/146 FS98O22 Register PT3EN at address 29H property R/W-0 R/W-0 R/W-0 PT3EN R/W-0 R/W-0 R/W-0 R/W-0 PT3EN [7:0] Bit7 Bit 7-0 R/W-0 Bit0 PT3EN [7 :0] : GPIO Port 3 Input / Output control flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT3EN[7] = GPIO Port 3 bit 7 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT3EN[6] = GPIO Port 3 bit 6 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT3EN[5] = GPIO Port 3 bit 5 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT3EN[4] = GPIO Port 3 bit 4 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT3EN[3] = GPIO Port 3 bit 3 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT3EN[2] = GPIO Port 3 bit 2 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT3EN[1] = GPIO Port 3 bit 1 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT3EN[0] = GPIO Port 3 bit 0 I/O control flag ; 0 = defined as input port, 1 = defined as output port property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 71/146 FS98O22 Register PT3PU at address 2AH R/W-0 R/W-0 R/W-0 PT3PU R/W-0 R/W-0 R/W-0 R/W-0 PT3PU [7:0] Bit7 Bit0 PT3PU [7:0]: GPIO Port 3 Pull up resistor enable flag PT3PU[7] = GPIO Port 3 bit 7 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-0 R/W-0 resistor resistor resistor resistor resistor resistor resistor resistor PT3PU[6] = GPIO Port 3 bit 6 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT3PU[5] = GPIO Port 3 bit 5 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT3PU[4] = GPIO Port 3 bit 4 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT3PU[3] = GPIO Port 3 bit 3 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT3PU[2] = GPIO Port 3 bit 2 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT3PU[1] = GPIO Port 3 bit 1 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up PT3PU[0] = GPIO Port 3 bit 0 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 72/146 FS98O22 Register PT3MR at address 2BH property R/W-0 U-0 U-0 PT3MR R/W-0 R/W-0 PFOEN R/W-0 E3M[1:0] R/W-0 E2M[1:0] Bit7 Bit 4 R/W-0 Bit0 PFOEN: Programmable Counter Enabled register flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 = Programmable Counter is enabled 0 = Programmable Counter is disabled Bit 3-2 E3M[1:0]: GPIO Port 3 bit 1 interrupt trigger mode (Please refer to Section 7.2 for detail) 11 = External Interrupt 4 (GPIO Port 3 bit 1) is triggered at state change 10 = External Interrupt 4 (GPIO Port 3 bit 1) is triggered at state change 01 = External Interrupt 4 (GPIO Port 3 bit 1) is triggered at positive edge 00 = External Interrupt 4 (GPIO Port 3 bit 1) is triggered at negative edge Bit 1-0 E2M[1:0]: GPIO Port 3 bit 0 interrupt trigger mode (Please refer to Section 7.2 for detail) 11 = External Interrupt 3 (GPIO Port 3 bit 0) is triggered at state change 10 = External Interrupt 3 (GPIO Port 3 bit 0) is triggered at state change 01 = External Interrupt 3 (GPIO Port 3 bit 0) is triggered at positive edge 00 = External Interrupt 3 (GPIO Port 3 bit 0) is triggered at negative edge property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 73/146 FS98O22 Register PT2OCB at address 37H property U-X U-X U-X PT2OCB R/W-1 R/W-1 U-X U-X PT2OC[4:3] Bit7 Bit0 PT2OC[4:3]: GPIO Port 2 Open Drain control flag PT2OC[4] = GPIO Port 2 bit 4 Open Drain control flag ; 0 = normal digital I/O, 1 = Open Drain FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 4-3 U-X Control Control PT2OC[3] = GPIO Port 2 bit 3 Open Drain control flag ; 0 = normal digital I/O, 1 = Open Drain property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 74/146 FS98O22 Digital I/O Port with Analog Input Channel Shared: PT1[7:0] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.1. Figure 7-1 PT1[7:0] function block GPIO Port 1 (PT1[7:0]) function block is shown in Figure 7-1. The main function of the GPIO is for data exchange between the Data bus and the ports. Users could control the PT1EN[7:0] register flags to decide the input and output direction. The input and output function and the related functions are explained as follows: Input: GPIO Port 1 Bit0 to Bit7 (PT1[7:0]) could be used to get both the digital signal and the analog signal. User should control the AIENB[7:0] register flags to decide the input type. If user sets the AIENB, the AND gate embedded in the GPIO Port1 will allow the digital data to connect to the data bus. Otherwise, the Input signals will be defined as analog signals and sent to the related function blocks (ADC, OPAMP…etc) Output FS98O22 sends the digital data out by an embedded D Flip Flop. When the program sends data out through PT1, the data will be sent to data bus first, and then the D Flip Flop will latch the signal for PT1 output while the Write signal and AR (FS98O22 internal device address pointer) is pointed to PT1. Pull up resistor 9 FS98O22 embeds an internal pull up resistor function in PT1 with about 1000k ohm resistor . Users could control the PT1PU[7:0] register flags to decide the connections to pull up resistor. When a port is connected to the pull up resistor, the input data is, by default, assigned to high (data 1). 9 The pull up current is about 10uA. Remember to disable PT1PU before program falls into Sleep mode. Rev. 1.4 75/146 FS98O22 Table 7-2 PT1 register table Detail on Chapter PT1 7 PT1EN 7 PT1PU 7 AIENB1 7 Address Name 20H 21H 22H 23H Bit 7 Bit 6 AIENB[7:6] Bit 5 Bit 4 Bit 3 Bit 2 PT1 [7:0] PT1EN [7:0] PT1PU [7:0] AIENB[5:0] Bit 1 Bit 0 Value on Power on Reset uuuuuuuu 00000000 00000000 00000000 Read data Operation 10 Clear the PT1EN[n] register flags. The PT1[n] will be defined as an input port. Set the PT1PU[n] register as required. The PT1[n] will be connected to an internal pull up resistor. Set the AIENB[n] register flags if the input signals are analog signals.(n = 7 to 0) 11 Clear the AIENB[n] register flags if the input signals are analog signals. (n = 7 to 0 ) The VDDA Regulator must be enabled first, and then the AIN0~AIN7 can work correctly. (Please refer to Chapter 4) After the signal input from outside, users can get the data through PT1[n] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1. 2. 3. 4. 5. 6. Write data Operation 1. 2. 3. Set the PT1EN[n] register flags. The PT1[n] will be defined as an output port. Set the PT1PU[n] register as required. The PT1[n] will be connected to an internal pull up resistor. Set the PT1[n] to output the data. The embedded D Flip Flop will latch the data till PT1[n] is changed. Notice Operation 1. 2. 10 11 To keep low operation current in SLEEP mode, set AIENB[7:0] to let the PT1 be floating. Parallel a small resistor (about 10k ohm) between ports and VDD to increase the possible output current when the PT1PU[n] is set. n means the bits indexes user want to control PT1 bit6 and bit7 could only be defined as digital signal input. Rev. 1.4 76/146 FS98O22 Digital I/O Port and External Interrupt Input : PT2[0], PT2[1], PT3[0], PT3[1] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.2. Figure 7-2 PT2[0] PT2[1] PT3[0] PT3[1] function block GPIO Port 2 Bit1 and Bit 0 (PT2[1:0])and Port 3 Bit1 and Bit 0 (PT3[1:0]) function block is shown in Figure 7-2. The main function of the GPIO is input and output data between the Data bus and the ports. Users could control the PT2EN[1:0] and PT3EN[1:0] register flags to decide the input output direction. The input and output function and the related functions are explained as follows: Input: GPIO Port 2 Bit1 and Bit0 (PT2[1:0]) could be the external interrupt ports as INT1 and INT0 or be the general I/O ports. User should control INTE register E0IE and E1IE flags to decide if the interrupt is enabled. The interrupt trigger mode is selected by E0M[1:0] and E1M[1:0] register flags. The input port has a Schmitt trigger in it, and the up/down trigger voltage level is 0.45VDD/0.2VDD. GPIO Port 3 Bit1 and Bit0 (PT3[1:0]) could be the external interrupt ports as INT3 and INT2 or be the general I/O ports. User should control INTE register E2IE and E3IE flags to decide if the interrupt is enabled. The interrupt trigger mode is selected by E2M[1:0] and E3M[1:0] register flags. The input port has a Schmitt trigger in it, and the up/down trigger voltage level is 0.45VDD/0.2VDD. Output FS98O22 sends the digital data out by an embedded D Flip Flop. When the program sends data out through PT2 or PT3, the data will be sent to data bus first, and then the D Flip Flop will latch the signal for PT2/PT3 output while the Write signal and AR (FS98O22 internal device address pointer) is pointed to PT2/PT3. Pull up resistor 12 FS98O22 embeds an internal pull up resistor function in PT2 with about 1000k ohm resistor . Users could control the PT2PU[1:0] register flags to decide the connections to pull up resistor. When a port is connected to the pull up resistor, the input data is, by default, assigned to high (data 1). 12 The pull up current is about 10uA. Remember to disable PT1PU before program falls into Sleep mode. Rev. 1.4 77/146 FS98O22 Table 7-3 PT2 register table 06H 07H 24H 25H 26H 27H 28H 29H 2AH Referenced Bit 7 Section INTF 3/6/7/9/10/11 INTE 3/6/7/9/10/11 GIE PT2 7 PT2EN 7 PT2PU 7 PT2MR 7.2/7.5/8 -PT3 PT3EN PT3PU 2BH PT3MR Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 ----PT2 [7:0] PT2EN [7:0] PT2PU [7:0] -E1M[1:0] PT3 [7:0] PT3EN [7:0] PT3PU [7:0] PFOE E3M[1:0] N Bit 1 Bit 0 E1IF E1IE E0IF E0IE E0M[1:0] Value on Power on Reset 00000000 00000000 uuuuuuuu 00000000 00000000 00000000 uuuuuuuu 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Address Name E2M[1:0] 00000000 Read data Operation 1. 2. 3. 13 Clear the PT2EN[n] /PT3EN[n] register flags. The PT2[n]/PT3[n] will be defined as an input port. Set the PT2PU[n]/PT3PU[n] register as required. The PT2[n]/PT3[n] will be connected to an internal pull up resistor. After the signal input from outside, user could get the data through PT2[n]/PT3[n] Write data Operation 1. 2. 3. Set the PT2EN[n]/PT3EN[n] register flags. The PT2[n]/PT3[n] will be defined as an output port. Set the PT2PU[n]/PT3PU[n] register as required. The PT2[n]/PT3[n] will be connected to an internal pull up resistor. Set the PT2[n]/PT3[n] to output the data. The embedded D Flip Flop will latch the data till PT2[n]/PT3[n] is changed. External Interrupt Operation (negative edge trigger for example) 1. 2. 3. 4. 5. 6. Clear the PT2EN[n]/PT3EN[n] register flags. The PT2[n]/PT3[n] will be defined as an input port. Set the PT2PU[n]/PT3PU[n] register. The PT2[n]/PT3[n] will be connected to an internal pull up resistor. Set the E0M[1:0] as 00 to define INT0 interrupt trigger mode as “negative edge trigger”. Set the E1M[1:0] as 00 to define INT1 interrupt trigger mode as “negative edge trigger”. Set the E2M[1:0] as 00 to define INT2 interrupt trigger mode as “negative edge trigger”. Set the E3M[1:0] as 00 to define INT3 interrupt trigger mode as “negative edge trigger”. Notice Operation 1. 13 Parallel a small resistor (about 10k ohm) between ports and VDD to increase the possible output current when the PT2PU[n]/PT3PU[n] is set. n means the bits indexes user want to control Rev. 1.4 78/146 FS98O22 Digital I/O Port or PDM Output : PT2[2] and PT2[5] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.3. Figure 7-3 PT2[2] function block GPIO Port 2 Bit2 (PT2[2]) and GPIO Port 2 Bit5 (PT2[5]) function block is shown in Figure 7-3. The main function of the GPIO is input and output data between the Data bus and the ports. User could control the PT2EN[2]/ PT2EN[5] register flags to decide the input output direction. The input and output function and the related functions are explained as follows: Input: GPIO Port 2 Bit2 (PT1[2]) and GPIO Port 2 Bit5 (PT1[5]) could be the PDM (Pulse Density Modulator) output port or be the general I/O port. User should setup PM1EN/ PM2EN register flag to decide if the PDM is enabled. The detailed PDM usage is described in Chapter 8. The input port has a Schmitt trigger in it, and the up/down trigger voltage level is 0.45VDD/0.2VDD. Output FS98O22 sends the digital data out by an embedded D Flip Flop. When the program sends data out through PT2, the data will be sent to data bus first, and then the D Flip Flop will latch the signal for PT2 output while the Write signal and AR (FS98O22 internal device address pointer) is pointed to PT2. Pull up resistor 14 FS98O22 embeds an internal pull up resistor function in PT2 with about 1000k ohm resistor . Users could control the PT2PU[2]/PT2PU[5] register flags to decide the connection to pull up resistor. When a port is connected to the pull up resistor, the input data is, by default, assigned to high (data 1). 14 The pull up current is about 10uA. Remember to disable PT1PU before program falls into Sleep mode. Rev. 1.4 79/146 FS98O22 Table 7-4 PT2 register table Address Name 24H 25H 26H 27H PT2 PT2EN PT2PU PT2MR Detail on Chapter 7 7 7 7.2/7.5/8 Bit 7 -- Bit 6 Bit 5 PM2EN Bit 4 Bit 3 Bit 2 Bit 1 PT2 [7:0] PT2EN [7:0] PT2PU [7:0] PM1EN -- Bit 0 -- Value on Power on Reset uuuuuuuu 00000000 00000000 00000000 Read data Operation 15 Clear the PT2EN[n] register flags. The PT2[n] will be defined as an input port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor. After the signal input from outside, user could get the data through PT2[n] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1. 2. 3. Write data Operation 1. 2. 3. Set the PT2EN[n] register flags. The PT2[n] will be defined as an output port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor. Set the PT2[n] to output the data. The embedded D Flip Flop will latch the data till user change PT2[n]. Notice Operation 1. Parallel a small resistor (about 10k ohm) between ports and VDD to increase the possible output current when the PT2PU[n] is set. 7.4. Digital I/O Port or I2C Serial Port : PT2[3]/SDA, PT2[4]/SCL Figure 7-4 PT2[3] PT2[4] function block GPIO Port 2 Bit4 and Bit 3 (PT2[4:3]) function block is shown in Figure 7-4. The main function of the GPIO is input and output data between the Data bus and the ports. Users could control the PT2EN[4:3] register flags to decide the input output direction. The input and output function and the related functions are explained as follows: 15 n means the bits indexes user want to control Rev. 1.4 80/146 FS98O22 Input: GPIO Port 2 Bit4 and Bit3 (PT2[4:3]) could be the I2C Module SCL and SDA ports or be the general I/O ports. User should setup I2CEN register flag to decide the I2C Module is enabled or not. The detailed I2C Module usage is described in Chapter 9. The input port has a Schmitt trigger in it, and the up/down trigger voltage level is 0.45VDD/0.2VDD. Output FS98O22 sends the digital data out by an embedded D Flip Flop. When the program sends data out through PT2, the data will be sent to data bus first, and then the D Flip Flop will latch the signal for PT2 output while the Write signal and AR (FS98O22 internal device address pointer) is pointed to PT2. Pull up resistor FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 16 FS98O22 embeds an internal pull up resistor function in PT2 with about 1000k ohm resistor . User could control the PT2PU[4:3] register flags to decide the connections to pull up resistor. When a port is connected to the pull up resistor, the input data is, by default, assigned to high (data 1). Open Drain Control FS98O22 embeds an internal Open Drain Control function in PT2[4:3]. Users could control the PT2OC[4:3] register flags to decide if the Open Drain Control function is enabled. When the user assigns these 2 ports to be SCL and SDA, PT2OC[4:3] should be set. Please refer to Chapter 9. Table 7-5 PT2 register table Referenced Bit 7 Section PT2 7 PT2EN 7 PT2PU 7 PT2OC 9 B Address Name 24H 25H 26H 37H Bit 6 Bit 5 Bit 4 Bit 3 PT2 [7:0] PT2EN [7:0] PT2PU [7:0] PT2OC[4:3] Bit 2 Bit 1 Bit 0 Value on Power on Reset uuuuuuuu 00000000 00000000 uuu11uuu Read data Operation 1. 2. 3. 4. 17 Clear the PT2EN[n] register flags. The PT2[n] will be defined as an input port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor. Set the PT2OC[n] register as required. The PT2[n] will be connected to an internal pull low resistor. After the signal input from outside, user could get the data through PT2[n] Write data Operation 1. 2. 3. 4. Set the PT2EN[n] register flags. The PT2[n] will be defined as an output port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor. Set the PT2OC[n] register as required. The PT2[n] will be connected to an internal pull low resistor. Set the PT2[n] to output the data. The embedded D Flip Flop will latch the data till PT2[n] is changed. Notice Operation 1. 2. 16 17 Parallel a small resistor (about 10k ohm) between ports and VDD to enlarge the possible output current when the PT2PU[n] is set. The Pull up resistor function and the Open drain control function should NOT be enabled at the same time. The pull up current is about 10uA. Remember to disable PT1PU before program falls into Sleep mode. n means the bit index that a user want to control Rev. 1.4 81/146 FS98O22 Digital I/O Port : PT2[6] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.5. Figure 7-5 PT2[6] function block GPIO Port 2 Bit 6 (PT2[6]) function block is shown in Figure 7-5. The main function of the GPIO is input and output data between the Data bus and the ports. Users could control the PT2EN[6] register flags to decide the input output direction. The input and output function are explained as follows: Input: GPIO Port 2 Bit 6 (PT2[6]) could only be the general I/O ports. The input port has a Schmitt trigger in it, and the up/down trigger voltage level is 0.45VDD/0.2VDD. Output FS98O22 sends the digital data out by an embedded D Flip Flop. When the program sends data out through PT2, the data will be sent to data bus first, and then the D Flip Flop will latch the signal for PT2 output while the Write signal and AR (FS98O22 internal device address pointer) is pointed to PT2. Pull up resistor 18 FS98O22 embeds an internal pull up resistor function in PT2 with about 1000k ohm resistor . User could control the PT2PU[6] register flags to set the connections to pull up resistor. When a port is connected to the pull up resistor, the input data is, by default, assigned to high (data 1). 18 The pull up current is about 10uA. Remember to disable PT1PU before program falls into Sleep mode. Rev. 1.4 82/146 FS98O22 Table 7-6 PT2 register table Address 24H 25H 26H 27H Referenced Bit 7 Section PT2 7 PT2EN 7 PT2PU 7 PT2MR 7.2/7.5/8 BZEN Name Bit 6 Bit 5 Bit 4 Bit 3 PT2 [7:0] PT2EN [7:0] PT2PU [7:0] --- Bit 2 Bit 1 Bit 0 -- Value on Power on Reset uuuuuuuu 00000000 00000000 00000000 Read data Operation 19 Clear the PT2EN[n] register flags. The PT2[n] will be defined as an input port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor. After the signal input from outside, user could get the data through PT2[n] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1. 2. 3. Write data Operation 1. 2. 3. Set the PT2EN[n] register flags. The PT2[n] will be defined as an output port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor. Set the PT2[n] to output the data. The embedded D Flip Flop will latch the data till PT2[n] is changed. Notice Operation 1. 19 Parallel a small resistor (about 10k ohm) between ports and VDD to increase the possible output current when the PT2PU[n] is set. n means the bits indexes user want to control Rev. 1.4 83/146 FS98O22 Digital I/O Port or Buzzer Output : PT2[7] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.6. Figure 7-6 PT2[7] function block GPIO Port 2 Bit2 (PT2[2]) function block is shown in Figure 7-6. The main function of the GPIO is input and output data between the Data bus and the ports. Users could control the PT2EN[2] register flags to decide the input output direction. The input and output function and the related functions are explained as follows: Input: GPIO Port 2 Bit2 (PT1[2]) could be the Buzzer output port or be the general I/O port. User should setup BZEN register flag to decide if the Buzzer output is enabled. The detailed Buzzer usage is described in Section 5.4. Output FS98O22 sends the digital data out by an embedded D Flip Flop. When the program sends data out through PT2, the data will be sent to data bus first, and then the D Flip Flop will latch the signal for PT2 output while the Write signal and AR (FS98O22 internal device address pointer) is pointed to PT2. Pull up resistor 20 FS98O22 embeds an internal pull up resistor function in PT2 with about 1000k ohm resistor . User could control the PT2PU[2] register flags to set the connection to pull up resistor. When a port is connected to the pull up resistor, the input data is, by default, assigned to high (data 1). 20 The pull up current is about 10uA. Remember to disable PT1PU before program falls into Sleep mode. Rev. 1.4 84/146 FS98O22 Table 7-7 PT2[7] register table Referenced Section PT2 7 PT2EN 7 PT2PU 7 Address Name 24H 25H 26H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PT2 [7:0] PT2EN [7:0] PT2PU [7:0] Value on Power on Reset uuuuuuuu 00000000 00000000 Read data Operation 21 Clear the PT2EN[n] register flags. The PT2[n] will be defined as an input port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor. After the signal input from outside, user could get the data through PT2[n] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1. 2. 3. Write data Operation 1. 2. 3. Set the PT2EN[n] register flags. The PT2[n] will be defined as an output port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor. Set the PT2[n] to output the data. The embedded D Flip Flop will latch the data till PT2[n] is changed. Buzzer Output Operation 1. 2. 3. 4. Set the PT2EN[7] register flags. The PT2[7] will be defined as an output port. Please refer to Section 5.4 for the Buzzer Clock setting. Set the BZEN register flag. The PT2[7] will become the buzzer output port. Connect a buzzer to PT2 bit7. The Buzzer will work correctly. Notice Operation 1. 21 Parallel a small resistor (about 10k ohm) between ports and VDD to increase the possible output current when the PT2PU[n] is set. n means the bits indexes user want to control Rev. 1.4 85/146 FS98O22 8. PDM (Pulse Density Modulator) Module FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Please see Figure 8-1 and Figure 8-2. The GPIO port 2 bit 2 (PT2[2]) could be defined as either PDM module output or General purpose I/O. User could control the PDMEN register flags to decide the definition. The PDM module is the function FS98O22 uses for implementing the PWM (Pulse Width Modulation). Its working flowchart and usage will be described in this Chapter. First of all, a user needs to setup the PMCS register flag 22 to decide the PDM CLK which is generated by a Frequency divider from the MCK . Then, the PDM CLK will be divided into 16 internal clock signals named PDM15, PDM14,…, PDM0. Finally, the user should control the PMD1 (PMD1H and PMD1L) register flag to do the combination of these 16 internal clock signals. For example, if the PMD1 is set as 0x1228H, the output signal is assigned to be the combination of PDM12, PDM9, PDM5 and PDM3. If the PMD1 is set as 0x6000H, the output signal is assigned to be the combination of PDM14 and PDM13 (please refer to the following figure).The PMD1 value could be assigned from 0 to 65535, and the 23 output signal duty cycle could be from 0 to 65535/65536 . For example, when user sets the PMD1 as 0x6000H (24576), the equivalent PWM duty cycle is 24576/65536. Figure 8-1 FS98O22 PDM module function block 22 Please refer to Chapter 5 for MCK detailed information. The PDM couldn‟t generate signal as duty cycle 1, user needs to define the port as General purpose I/O and keep it at high voltage level (data 1) manually to represent Duty Cycle 1. 23 Rev. 1.4 86/146 FS98O22 PDM15 PDM14 PDM13 PDM12 … … FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y If PMD1 = 0x5000H PDM out If PMD1 = 0xC000H PDM out Figure 8-2 PDM module signal generation Rev. 1.4 87/146 FS98O22 Table 8-1 PDM module register table Address Name 27H 30H 31H 32H 33H 36H PT2MR PMD1H PMD1L PMD2H PMD2L PMCON Referenced Section 7.2/7.5/8 8 8 Bit 7 Bit 6 Bit 5 -- Bit 4 Bit 3 Bit 2 PM1EN -PMD1[15:8] PMD1[7:0] PDMD2[15:8] PDMD2[7:0] PDMEN 8 Bit 1 Bit 0 -- PMCS[2:0] Value on Power on Reset 00000000 00000000 00000000 00000000 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register PT2MR at address 27H property U-0 U-0 U-0 PT2MR -- PM2EN R/W-0 U-0 PM1EN U-0 -- Bit7 Bit 6 U-0 U-0 -- Bit0 PM1EN: PT2[5] output multiplexer (Please refer to Section 7.3 for details) 1 = GPIO Port 2 bit 5 (PT2[5]) is defined as PDM output. 0 = GPIO Port 2 bit 5 (PT2[5]) is defined as GPIO. Bit 4 PM1EN: PT2[2] output multiplexer (Please refer to Section 7.3 for details) 1 = GPIO Port 2 bit 2 (PT2[2]) is defined as PDM output. 0 = GPIO Port 2 bit 2 (PT2[2]) is defined as GPIO. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 88/146 FS98O22 Register PMD1H at address 30H property R/W-0 R/W-0 R/W-0 PMD1H R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMD1[15:8] Bit7 Bit0 Register PMD1L at address 31H R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y property PMD1L PMD1[7:0] Bit7 Bit 15-0 Bit0 PMD1[15:0]: PDM Module Data output Control Register 1 PMD1[15] = PDM15 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 2 PMD1[14] = PDM14 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 3 PMD1[13] = PDM13 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 4 PMD1[12] = PDM12 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 5 PMD1[11] = PDM11 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 6 PMD1[10] = PDM10 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 7 PMD1[9] = PDM9 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 8 PMD1[8] = PDM8 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 9 PMD1[7] = PDM7 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 10 PMD1[6] = PDM6 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 11 PMD1[5] = PDM5 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 12 PMD1[4] = PDM4 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 13 PMD1[3] = PDM3 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 14 PMD1[2] = PDM2 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 15 PMD1[1] = PDM1 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable 16 PMD1[0] = PDM0 (PDM CLK/2 )Signal Combination enable flag. 0 = Enable ; 1 = Disable property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 89/146 FS98O22 Register PMD2H at address 30H property R/W-0 R/W-0 R/W-0 PMD2H R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMD2[15:8] Bit7 Bit0 Register PMD2L at address 31H R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y property PMD2L PMD2[7:0] Bit7 Bit 15-0 Bit0 PMD2[15:0]: PDM Module Data output Control Register PMD2[15] = PDM15 (PDM CLK/21)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[14] = PDM14 (PDM CLK/22)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[13] = PDM13 (PDM CLK/23)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[12] = PDM12 (PDM CLK/24)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[11] = PDM11 (PDM CLK/25)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[10] = PDM10 (PDM CLK/26)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[9] = PDM9 (PDM CLK/27)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[8] = PDM8 (PDM CLK/28)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[7] = PDM7 (PDM CLK/29)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[6] = PDM6 (PDM CLK/210)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[5] = PDM5 (PDM CLK/211)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[4] = PDM4 (PDM CLK/212)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[3] = PDM3 (PDM CLK/213)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[2] = PDM2 (PDM CLK/214)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[1] = PDM1 (PDM CLK/215)Signal Combination enable flag. 0 = Enable ; 1 = Disable PMD2[0] = PDM0 (PDM CLK/216)Signal Combination enable flag. 0 = Enable ; 1 = Disable Rev. 1.4 90/146 FS98O22 Register PMCON at address 36H property U-0 U-0 U-0 PMCON R/W-0 U-0 R/W-0 PDMEN R/W-0 PMCS[2:0] Bit7 Bit 4 R/W-0 Bit0 PDMEN: PDM Module enable flag (Please refer to Chapter 8 for details) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 = PDM Module is enabled, GPIO Port 2 bit 2 could be defined as PDM output. 0 = PDM Module is disabled, GPIO Port 2 bit 2 could be defined as GPIO. Bit 2-0 PMCS[2:0]: PDM CLK frequency Selector 111 = PDM CLK frequency is as MCK/128 110 = PDM CLK frequency is as MCK/64 101 = PDM CLK frequency is as MCK/32 100 = PDM CLK frequency is as MCK/16 011 = PDM CLK frequency is as MCK/8 010 = PDM CLK frequency is as MCK/4 001 = PDM CLK frequency is as MCK/2 000 = PDM CLK frequency is the same as MCK property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 91/146 FS98O22 Table 8-2 PMD register table Address 14H 25H 27H Value on Power on Reset 00000000 00000000 00000000 00000000 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 30H 31H 36H Detail on Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Chapter MCK 5 M7_CK M6_CK M5_CK M3_CK M2_CK M1_CK M0_CK PT2EN 7 PT2EN [7:0] PT2MR PM1E 7.2/7.5/8 ---N PMD1H 8 PMD1[15:8] PMD1L 8 PMD1[7:0] PMCON PDME 8 PMCS[2:0] N Name PDM Operation 1. 2. 3. 4. 5. 6. Setup M0_CK, M3_CK to decide the MCK.(Please refer to Section 5.1 for detailed instruction for setup) Set PDMEN to enable the PDM Module. Setup PMCS[2:0] to decide the PDM CLK frequency. Setup PMD1[15:0] to decide the PDM output signal. Set PT2EN[2] to assign the PT2[2] to be an output port. Set PM1EN to assign the PT2[2] to be PDM Module output. Table 8-3 PDM CLK selection table Rev. 1.4 PWCS PDM CLK frequency 000 MCK 001 MCK/2 010 MCK/4 011 MCK/8 100 MCK/16 101 MCK/32 110 MCK/64 111 MCK/128 92/146 FS98O22 9. I2C Module (slave mode only) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y FS98O22 embeds a slave mode I2C module. The two pins, SCL and SDA, are used to perform the I2C system. The pin SCL is assigned to be the clock pin, and the pin SDA is assigned to be the data pin in the I2C module. In an I2C system, there are master side and slave side. Master side would send the clock, slave ID and the commands to slave side. One master could connect to several slave sides with different IDs. First of all, the slave side would check if the ID sent by master side is the same as itself. If the ID matched, slave side would check the following bit from master. If the bit was high, it means that master side want to transfer some data or command to slave, so slave side should sent back an acknowledgement signal and then receive the data from master side. On the other hand, if the bit was low, it means that master side want to receive the data from slave side, so slave side should sent back an acknowledgement signal and then transmit the data back.( Please see Figure 9-1) Master to slave Slave to master …. Master receive data Master transmit data start slave ID R ack data start slave ID R ack Data1 ack stop ack …. stop Figure 9-1 FS98O22 I2C module communication In the I2C module embedded in FS98O22, there are 5 register flags shown in following figure. The SCL and SDA signal is connected to I2CSR and the Start and stop bit detector. The I2CSR is assigned to be the data buffer. When some signal is sent from master, the Start and stop bit detector will respond to the situation, and the Match detector will determine if the input data is matched with the slave ID. If it matches the ID, the user should send back the acknowledgement (data high) to respond to the master side. No matter whether the I2C module sends the data or receives the data, the I2CBUF is assigned to be the buffer. When the module receives the data, the data signals will be stored in the I2CSR, and send the whole data to I2CBUF after the data is sent completely. Rev. 1.4 93/146 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y FS98O22 Figure 9-2 I2C module function block Rev. 1.4 94/146 FS98O22 Table 9-1 I2C module register table Address Name 57H 58H 59H 5AH I2CCON I2CSTA I2CADD I2CBUF Referenced Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Section 9 WCOL I2COV I2CEN CKP 9 DA P S RW 9 I2CADD [7:0] 9 I2CBUF [7:0] Bit 1 Value on Power on Reset 0001uuuu uu0000u0 00000000 00000000 Bit 0 BF FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register I2CCON at address 57H property R/W-0 R/W-0 R/W-0 R/W-1 I2CCON WCOL I2COV I2CEN CKP U-X U-X U-X Bit7 Bit 7 U-X Bit0 WCOL: Write collision detector register flag. 1 = The I2CBUF register is written while it is still transmitting the previous data. 0 = No write collision is happened. This register should be clear in software. Bit 6 I2COV: Receive overflow detector register flag 1 = A byte is received while theI2CBUF is still holding the previous data. 0 = No receive overflow is happened. This register should be clear in software Bit 5 I2CEN: I2C module enable flag 1 = I2C module is enabled. 0 = I2C module is disabled. Bit 4 CKP: SCK signal control register 1 = SCK pin is enabled. 0 = SCK pin is disabled and hold to low. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 95/146 FS98O22 Register I2CSTA at address 58H property U-X U-X I2CSTA R/W-0 R/W-0 R/W-0 R/W-0 DA P S RW U-X BF Bit7 Bit0 DA: Data / Address bit register flag. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 5 R/W-0 1 = The last received byte is data. 0 = The last received byte is address. Bit 4 P: Stop bit register flag 1 = A stop bit is detected. 0 = No stop bit is detected. When the I2C module is disabled, this bit would be clear. Bit 3 S: Start bit register flag 1 = A start bit is detected. 0 = No start bit is detected. When the I2C module is disabled, this bit would be clear. Bit 2 RW: Read / Write register flag 1 = Read command is detected. 0 = Write command is detected. Bit 0 BF: I2CBUF full register flag. 1 = I2CBUF is full. The user could get data from I2CBUF register. 0 = I2CBUF is empty. Register I2CADD at address 59H property R/W-0 R/W-0 R/W-0 I2CADD R/W-0 R/W-0 R/W-0 R/W-0 I2CADD [7:0] Bit7 Bit 7-0 R/W-0 Bit0 I2CADD[7:0]: I2C module slave mode ID buffer register. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 96/146 FS98O22 Register I2CBUF at address 5AH property R/W-0 R/W-0 R/W-0 I2CBUF R/W-0 R/W-0 R/W-0 R/W-0 I2CBUF [7:0] Bit7 Bit0 I2CBUF[7:0]: I2C module Data buffer register. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-0 R/W-0 Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit unknown is 97/146 FS98O22 Table 9-2 I2C register table Address Referenced Section Bit 7 INTF 3/6/7/9/10/11 INTE 3/6/7/9/10/11 GIE PT2OCB 9 I2CCON 9 WCOL I2CSTA 9 I2CADD 9 I2CBUF 9 Bit 6 I2COV Bit 5 I2CEN DA Bit 4 Bit 3 -I2CIF -I2CIE PT2OC[4:3] CKP P S I2CADD [7:0] I2CBUF [7:0] Bit 2 Bit 1 Bit 0 --- --- --- RW BF Value on Power on Reset 00000000 00000000 uuu11uuu 0001uuuu uu0000u0 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 06H 07H 37H 57H 58H 59H 5AH Name I2C data receive operation: (master to slave) 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Configure SCL and SDA pins as open-drain through the PTOCB[4:3] Set I2CEN register flag to enable the I2C module. Clear I2CIF to reset the I2C interrupt. Set I2CIE and GIE to enable the I2C interrupt. Wait for the interrupt. When the I2C master device sends data to slave side, the data (ID) transmitted from the master device will be sent to I2CBUF, and the BF register flag will be set. If the RW register flag is set, the I2C module will enter the receive mode. The acknowledgement signal will be sent automatically and an interrupt will occur. Clear the I2CIF and reset the interrupt to wait for the interrupt happened again. When an interrupt occurs, read the I2CBUF for receiving the data transmitted from master side. The acknowledgement signal will be sent automatically. If the user doesn‟t read the data from I2CBUF, the BF register flag will be held high. When the data is sent to slave again, the I2COV register flag will be set, and the interrupt will NOT happen. Figure 9-3 I2C waveform for reception Rev. 1.4 98/146 FS98O22 I2C data transmit operation: 1. 2. 3. 4. 5. 6. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7. 8. 9. Configure SCL and SDA pins as open-drain through the PTOCB[4:3]. Set I2CEN register flag to enable the I2C module. Clear I2CIF to reset the I2C interrupt. Set I2CIE and GIE to enable the I2C interrupt. Wait for the interrupt. When the I2C master device sends data to slave side, the data (ID) transmitted from the master device will be sent to I2CBUF, and the BF register flag will be set. If the RW register flag is clear, the I2C module will enter the transmit mode. The acknowledgement signal will be sent automatically and the interrupt will happen. Set the CKP register flag to hold the SCK to low, and then write the data, which is ready to send to master side, to I2CBUF. Clear the I2CIF and reset the interrupt to wait for the interrupt to happen again. Clear the CKP register flag to enable the SCK pin. The master side will start to get the data. When interrupt happen, the master side has already finished the transmission, the acknowledgement has been sent back to salve side, and the BF register flag has been clear. 10. 11. 12. Figure 9-4 I2C waveforms for transmission Rev. 1.4 99/146 FS98O22 10. Analog Function Network Please see Figure 10-1. FS98O22 Analog Function Network has 2 main functions: Low Noise OP Amplifier (OPAMP) and Sigma Delta Analog to Digital Converter (ADC). OPAMP is used to amplify the input analog signal for ADC. ADC is used to convert the analog signal to digital signal. The OPAMP has 2 input ports as inverting side and non-inverting side. Users could setup SOP1P[2:0] and SOP1N[1:0] to choose the input signals. S_CH1CK[1:0] and OP1EN register flags are used to control OPAMP and OP1O is the OPAMP output port. The detailed operations will be described in Section 10.2. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y The embedded ADC contains sigma delta modulator and digital comb filter. It is a fully differential input system. User could give 2 signals for differential reference and 2 signals for differential input. ADC will convert the ratio of differential input to differential reference to 14-bit digital output. The related control instructions will be illustrated in Section 10.1. Figure 10-1 FS98O22 analog function network Rev. 1.4 100/146 FS98O22 Table 10-1 analog function network register table Address Name INTF INTE ADOH ADOL ADOLL ADCON PCK NETA NETB NETC NETD Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 --ADIF ----ADIE --ADO [15:8] ADO [7:0] Extra ADC output register ADRST ADM [2:0] S_CH1CK [1:0] --SINH[2:0] SFTA[2:0] SOP1N[1:0] SVRL[1:0] SVRH[1:0] ADG[1:0] ADEN AZ OP1EN SOP1P[2:0] Value on Power on Reset 00000000 00000000 00000000 00000000 00000000 uuuu0000 00000000 00000000 00000000 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 06H 07H 10H 11H 12H 13H 15H 18H 19H 1AH 1BH Referenced Bit 7 Bit 6 Section 3/6/7/9/10/11 3/6/7/9/10/11 GIE 10/11 10/11 10/11 10/11 4/5/7.5/10 -10/11 SINL[1:0] 10/11 10/11 SREFO 10/11 Rev. 1.4 101/146 FS98O22 Register ADOH at address 10H Property R-0 R-0 R-0 R-0 ADOH R-0 R-0 R-0 R-0 ADO [15:8] Bit7 Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register ADOL at address 11H property R-0 R-0 R-0 R-0 ADOL R-0 R-0 R-0 ADO [7:0] Bit7 Bit 15-0 R-0 Bit0 ADO [15:0]: ADC Digital Output ADO[15] = ADC Digital Output sign bit. 0 = Output is positive; 1 = Output is negative. ADO[14] = ADC Digital Output sign bit. 0 = Output is positive; 1 = Output is negative. ADO[13] = ADC Digital Output Data bit 13. ADO[12] = ADC Digital Output Data bit 12. ADO[11] = ADC Digital Output Data bit 11. ADO[10] = ADC Digital Output Data bit 10. ADO[9] = ADC Digital Output Data bit 9. ADO[8] = ADC Digital Output Data bit 8. ADO[7] = ADC Digital Output Data bit 7. ADO[6] = ADC Digital Output Data bit 6. ADO[5] = ADC Digital Output Data bit 5. ADO[4] = ADC Digital Output Data bit 4. ADO[3] = ADC Digital Output Data bit 3. ADO[2] = ADC Digital Output Data bit 2. ADO[1] = ADC Digital Output Data bit 1. ADO[0] = ADC Digital Output Data bit 0. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 102/146 FS98O22 Register ADOLL at address 12H property R-0 R-0 R-0 ADOLL R-0 R-0 R-0 R-0 R-0 Extra ADC output register Bit7 Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Users could take the value of 3 registers, ADOH, ADOL and ADOLL as 24 bits ADC output. Register ADCON at address 13H property U-X U-X U-X U-X ADCON R/W-0 R/W-0 ADRST R/W-0 ADM [2:0] Bit7 Bit 3 R/W-0 Bit0 ADRST: ADC comb filter enable register (Please refer to Section 10.1 for detail) 1 = ADC comb filter is enabled, ADC could work correctly. 0 = ADC comb filter is disabled, ADC digital output will be zero. Bit 2-0 ADM [2:0]: ADC output rate selector 111 = ADC output rate is ADCF/8000 24 110 = ADC output rate is ADCF/8000 101 = ADC output rate is ADCF/4000 100 = ADC output rate is ADCF/2000 011 = ADC output rate is ADCF/1000 010 = ADC output rate is ADCF/500 001 = ADC output rate is ADCF/250 000 = ADC output rate is ADCF/125 property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared 24 X = Bit is unknown Please refer to Section 5.3 for ADCF information. Rev. 1.4 103/146 FS98O22 Register PCK at address 15H property U-0 PCK U-0 U-0 -- U-0 R/W-0 R/W-0 S_CH1CK [1:0] U-0 U-0 -- -- Bit7 S_CH1CK [1:0]: OPAMP Control Register (Please refer to Section 10.2) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 3-2 Bit0 11 = The OPAMP Chopper mode is enabled, and the Chopper frequency is CLK/1000 10 = The OPAMP Chopper mode is enabled, and the Chopper frequency is CLK/500 01 = The OPAMP Chopper mode is disabled. OPAMP input operation mode is set to be “-Offset”. 00 = The OPAMP Chopper mode is disabled. OPAMP input operation mode is set to be “+Offset”. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 104/146 FS98O22 Register NETA at address 18H property R/W-0 NETA R/W-0 R/W-0 SINL[1:0] R/W-0 R/W-0 R/W-0 SINH[2:0] R/W-0 SFTA[2:0] Bit7 Bit0 SINL[1:0]: ADC negative input port signal multiplexer (Please refer to Section 10.1) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-6 R/W-0 11 = The ADC negative input port is connected to TEMPL. (Please refer to Section 4.6) 10 = The ADC negative input port is connected to AIN3 (PT1[3]). 01 = The ADC negative input port is connected to AIN2 (PT1[2]). 00 = The ADC negative input port is connected to AIN1 (PT1[1]). Bit 5-3 10.1) SINH[2:0]: Embedded ADC Low Pass Filter input port signal multiplexer (Please refer to Section 111 = The ADC Low Pass Filter input port is connected to AGND. (Please refer to Section 4.4) 110 = The ADC Low Pass Filter input port is connected to AIN4 (PT1[4]). 101 = The ADC Low Pass Filter input port is connected to AIN5 (PT1[5]). 100 = The ADC Low Pass Filter input port is connected to TEMPH. (Please refer to Section 4.6) input). input). 011 = The ADC Low Pass Filter input port is connected to VRL (ADC referenced voltage negative 010 = The ADC Low Pass Filter input port is connected to VRH (ADC referenced voltage positive 001 = The ADC Low Pass Filter input port is connected to OP1P (OPAMP non-inverting input port). 000 = The ADC Low Pass Filter input port is connected to OP1O (OPAMP output port). Bit 2 SFTA [2]: FTIN and FTB connector ( ADC Low Pass Filter enable flag) 1 = FTIN and FTB is short. ADC Low Pass Filter is enabled. 0 = FTIN and FTB is open. ADC Low Pass Filter is disabled. Bit 1-0 SFTA [1:0]: ADC positive input port signal multiplexer (Please refer to Section 10.1) 11 = The ADC positive input port is connected to AIN3 (PT1[3]). 10 = The ADC positive input port is connected to AIN2 (PT1[2]). 01 = The ADC positive input port is connected to FTIN (SINH[2:0] multiplexer output port). 00 = The ADC positive input port is connected to FTB (FTIN output signal after Low Pass filter). Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 105/146 FS98O22 Register NETB at address 19H property U-0 U-0 NETB R/W-0 R/W-0 SOP1N[1:0] R/W-0 R/W-0 R/W-0 SVRL[1:0] SVRH[1:0] Bit7 Bit0 SOP1N[1:0]: OPAMP inverting input port signal multiplexer (Please refer to Section 10.2) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 5-4 R/W-0 11 = The OPAMP inverting input port is connected to AIN6 (PT1[3]). 10 = The OPAMP inverting input port is connected to AIN5 (PT1[5]). 01 = The OPAMP inverting input port is connected to AIN4 (PT1[4]). 00 = The OPAMP inverting input port is connected to OP1O (OPAMP output port). Bit 3-2 10.1) SVRL[1:0]: ADC reference voltage negative input port signal multiplexer (Please refer to Section 25 11 = The ADC negative referenced input port is connected to VR2P (1/5 REFO ). 10 = The ADC negative referenced input port is connected to AIN2 (PT1[2]). 01 = The ADC negative referenced input port is connected to AIN1 (PT1[1]). 00 = The ADC negative referenced input port is connected to AGND (Please refer to Section 4.4). Bit 1-0 10.1) SVRH[1:0]: ADC reference voltage positive input port signal multiplexer (Please refer to Section 11 = The ADC negative referenced input port is connected to VR2P (1/5 REFO). 10 = The ADC negative referenced input port is connected to VR1P (2/5 REFO). 01 = The ADC negative referenced input port is connected to AIN3 (PT1[3]). 00 = The ADC negative referenced input port is connected to AIN0 (PT1[0]). Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared 25 X = Bit is unknown Please refer to Section 4.6 for REFO detailed information Rev. 1.4 106/146 FS98O22 Register NETC at address 1AH property R/W-0 NETC SREFO U-0 U-0 U-0 R/W-0 R/W-0 ADG[1:0] R/W-0 R/W-0 ADEN AZ Bit7 SREFO: Internal Reference Voltage enable flag. (Please refer to Section 10.1) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7 Bit0 1 = Internal Reference Voltage is enabled. VR1P = 2/5 REFO, VR2P = 1/5 REFO 0 = Internal Reference Voltage is disabled. VR1P and VR2P are floating. Bit 3-2 ADG[1:0]: Internal ADC input gain. (Please refer to Section 10.1) 11 = Internal ADC input gain is 7/3 10 = Internal ADC input gain is 2 01 = Internal ADC input gain is 1 00 = Internal ADC input gain is 2/3 Bit 1 ADEN: ADC enable flag. (Please refer to Section 10.1) 1 = ADC is enabled. 0 = ADC is disabled. Bit 0 AZ: ADC differential input ports short controller. (Please refer to Section 10.1) 1 = ADC differential input ports are short and both connect to INL 26 (SINL output). 0 = ADC differential input ports are NOT short. The 2 ports connect to INH and INL. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared X = Bit is unknown 26 That means the ADC input differential voltage is zero. ADC output should be zero counts. User could measure ADC offset counts when the AZ register flag is set. Rev. 1.4 107/146 FS98O22 Register NETD at address 1BH property U-0 U-0 U-0 NETD U-0 R/W-0 R/W-0 OP1EN R/W-0 SOP1P[2:0] Bit7 Bit0 OP1EN: OPAMP enable flag. (Please refer to Section 10.2) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 3 R/W-0 1 = OPAMP is enabled. 0 = OPAMP is disabled. Bit 2-0 10.2) SOP1P[2:0]: OPAMP non-inverting input port signal multiplexer (Please refer to Section 111 = The OPAMP non-inverting input port is connected to AIN7 (PT1[7]) 110 = The OPAMP non-inverting input port is connected to AIN6 (PT1[6]) 101 = The OPAMP non-inverting input port is connected to AIN5 (PT1[5]). 100 = The OPAMP non-inverting input port is connected to AIN4 (PT1[4]). 011 = The OPAMP non-inverting input port is connected to AIN3 (PT1[3]). 010 = The OPAMP non-inverting input port is connected to AIN2 (PT1[2]). 001 = The OPAMP non-inverting input port is connected to AIN1 (PT1[1]). 000 = The OPAMP non-inverting input port is connected to AIN0 (PT1[0]). Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit unknown is 108/146 FS98O22 10.1. Analog to Digital Converter (ADC) : FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Please see Figure 10-2. ADC Module contains 3 main functions – Low Pass Filter, Sigma Delta Modulator and Comb Filter. Before doing the AD conversion, User could reduce the low frequency noise by the embedded Low Pass Filter. The SINH[2:0] register flags are used to choose the input signal. SFTA[2] flag is used to enable the Filter. Sigma Delta Modulator and Comb Filter are used to complete the AD Converter. First of all the Modulator will output serial bits to show the ratio of the difference between INH and INL to the difference between VRH and VRL. For example, if the ratio of VRH and VRL to INH and INL is 7/10, the output bit series will be 7 „bit1‟ every 10 bits in average. Comb Filter is used to increase the SNR(signal-noise ratio) and the real ADC output, ADO, will be 14-bit precision in FS98O22. Figure 10-2 FS98O22 ADC function block Rev. 1.4 109/146 FS98O22 Table 10-2 ADC function register table Address 06H 07H Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- ADIF -- -- -- -- ADIE -- -- ADO [15:8] ADO [7:0] ADRST ---SINH[2:0] -SVRL[1:0] ADG[1:0] ADM [2:0] M1_CK -SFTA[2:0] SVRH[1:0] ADEN AZ Value on Power on Reset 00000000 00000000 00000000 00000000 uuuu0000 00000000 00000000 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 10H 11H 13H 14H 18H 19H 1AH Referenced Bit 7 Bit 6 Section INTF 3/6/7/9/10/1 1 INTE 3/6/7/9/10/1 GIE 1 ADOH 10/11 ADOL 10/11 ADCON 10/11 MCK 5 --NETA 10/11 SINL[1:0] NETB 10/11 NETC 10/11 SREFO Name ADC Operation 1. 2. 3. 4. Operate as in Section 4.1 to get the VGG (2 times VDD or external Power Supply). Operate as in Section 4.2 to get the VDDA (3.6V) Operate as in Section 4.3 to enable the Analog Bias Circuit Set SINH[2:0] and SFTA[2:0] to decide the ADC positive input port signal.(Table 10-3, 10-4 and 10-5) Table 10-3 FTIN selection table SINH[2:0] FTIN 000 OP1O 001 OP1P 010 VRH 011 VRL 100 TEMPH 101 AIN5 110 AIN4 111 AGND Table 10-4 FTB selection table 27 SFTA[2] 27 FTB 0 ADC Low Pass Filter is disabled 1 ADC Low Pass Filter is enabled The input of ADC Low Pass Filter is FTIN, and the output is FTB Rev. 1.4 110/146 FS98O22 Table 10-5 INH selection table INH (ADC positive input port signal) 00 FTB 01 FTIN 10 AIN2 11 AIN3 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y SFTA[1:0] 5. Set SINL[1:0] to decide the ADC negative input port signal. (Table 10-6) Table 10-6 INL selection table 6. SINL[1:0] INL (ADC negative input port signal) 00 AIN1 01 AIN2 10 AIN3 11 TEMPL Set ADG[1:0] to decide the ADC input gain. (Table 10-7) Table 10-7 ADG selection table 7. 8. ADG[1:0] ADC input gain 00 2/3 01 1 10 2 11 7/3 Set SREFO register flag to enable the VR1P and VR2P if needed. (VR1P = 2/5 REFO, VR2P = 1/5 REFO) Set SVRH[1:0] to decide the ADC reference voltage positive input port signal. (Table 10-8) Table 10-8 VRH selection table 9. SVRH[1:0] VRH (ADC reference voltage positive input) 00 AIN0 01 AIN3 10 VR1P 11 VR2P Set SVRL[1:0] to decide the ADC reference voltage negative input port signal. (Table 10-9) Rev. 1.4 111/146 FS98O22 Table 10-9 SVRL selection table VRL (ADC reference voltage negative input) 00 AGND 01 AIN1 10 AIN2 11 VR2P FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y SVRL[1:0] 10. Set ADM[2:0] to decide the ADC output rate. (Table 10-10 and 10-11) Table 10-10 ADC output rate selection table ADM[2:0] ADC Output Rate 000 ADCF/125 001 ADCF/250 010 ADCF/500 011 ADCF/1000 100 ADCF/2000 101 ADCF/4000 110 ADCF/8000 111 ADCF/8000 Table 10-11 ADC sample frequency selection table 11. 12. 13. 14. 15. 16. M1_CK ADC sample Frequency (ADCF) 0 MCK/25 1 MCK/50 Set ADIE and GIE register flags to enable the ADC interrupt Set ADEN register flag, the embedded - modulator will be enabled. Set ADRST register flag, the comb filter will be enabled. When the ADC interrupt happen, read the ADO[15:0] to get the ADC output.(ADO[15:14] are signed bits) Set AZ register flag to make the ADC positive and negative input port be internally short. Read the ADO[15:0] to get the ADC offset (The ADO should be zero if the offset is zero) Clear AZ register flag to make the ADC work normally. Rev. 1.4 112/146 FS98O22 10.2. OPAMP : OP1 Table 10-12 FS98O22 OPAMP register table Address Name 15H 19H 1BH PCK NETB NETD Referenced Section 4/5/7.5/10 10/11 10/11 Bit 7 Bit 6 -- Bit 5 Bit 4 SOP1N[1:0] Bit 3 Bit 2 Bit 1 Bit 0 S_CH1CK [1:0] ----OP1EN SOP1P[2:0] Value on Power on Reset 00000000 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y OPAMP Operation 1. Set SOP1P[2:0] to decide the OPAMP non-inverting input port signal. (Table 10-13) Table 10-13 OP1P selection table 2. SOP1P[2:0] OP1P (OPAMP non-inverting input) 000 AIN0 001 AIN1 010 AIN2 011 AIN3 100 AIN4 101 AIN5 110 AIN6 111 AIN7 Set SOP1N[1:0] to decide the OPAMP inverting input port signal. (Table 10-14) Table 10-14 OP1N selection table 3. SOP1N[1:0] OP1N (OPAMP inverting input) 00 OP1O 01 AIN4 10 AIN5 11 AIN6 Set S_CH1CK[1:0] to decide the OPAMP chopper mode.(Please see Section 3.6 for details) Rev. 1.4 113/146 FS98O22 Table 10-15 chopper mode selection table OPAMP chopper mode (input operation) 00 +Offset 01 -Offset 10 CLK/500 chopper frequency 11 CLK/1000 chopper frequency FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y S_CH1CK[1:0] 4. Set OP1EN to enable the OPAMP. Rev. 1.4 114/146 FS98O22 11. ADC Application Guide The ADC used in FS98O22 is a - ADC with fully differential inputs and fully differential reference voltage inputs. Its maximum output is 15625. The conversion equation is as follows: Dout 15625 * G * G is ADC input gain. (refer to Section 10.1 ADC operation step 6) VIH is ADC’s positive input voltage VIL is ADC’s negative input voltage Vio is ADC’s offset on the input terminals (Vio could be measured by using AZ register flag. See Section 11.4) VRH is the voltage at the positive input of Reference Voltage VRL is the voltage at the negative input of Reference Voltage Vro is the offset on the input terminals of Reference Voltage (Generally speaking, Vro could be ignored) The value (VRH-VRL+Vro) should be positive. When G * (VIH-VIL+Vio) / (VRH-VRL+Vro) 1, Dout=15625 When G * (VIH-VIL+Vio) / (VRH-VRL+Vro) -1, Dout=-15625 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y VIH - VIL Vio VRH - VRL Vro 11.1. ADC Output Format th CPU can read ADO[14:0] as ADC‟s 15-bit output. Note that the output is in 2‟s complement format. The 14 bit of ADO[14:0] is sign bit. When the sign bit is cleared, the ADC output denotes a positive number, When the sign bit is set, the ADC output denotes a negative number. Example: ADO[15:0] = 0X257FH, then Dout = 9599. ADO[15:0] = 0XE2F7H, then Dout = - (not (E2F7H) +1) = -7433. 11.2. ADC Linear Range ADC is close to saturation when G * (VIH-VIL+Vio) / (VRH-VRL+Vro) is close to 1, and has good linearity in the range of 0.95. 11.3. ADC Output Rate and Settling Time ADC output is the results of sigma delta modulator and the comb filter. The analog input signal needs to be 28 sampled N times and processed by the ADC and then the user could get one digital output. Generally speaking, the more times ADC samples the analog input signal, the more precise the digital output is. When the user decides the sampling frequency and sampling counts, and then enables the ADC module, ADC module will send out a 15-bit signed digital output data every sampling N times and trigger the ADC interrupt. In fact, every ADC output includes previous 2*N times sampling results. Generally speaking, if ADC inputs, reference voltage, ADG, AZ are switched, the previous two ADC digital outputs are normally unstable ones, the third output and beyond are stable. 11.4. ADC Input Offset ADC Input Offset Vio is NOT a constant. It drifts with temperature and common mode voltage at the inputs. 28 „N times‟ could be decided by setting ADM register flag (Please refer to Section 10.1). FS98O22 ADC sampling frequency is decided by M1_CK( Please refer to Section 5.3). Rev. 1.4 115/146 FS98O22 To get a correct ADC result, Doff(ADC input offset digital output) should be deducted from the Dout. The instruction is as follows: 1. 2. 3. 4. Set AZ bit, and VIH and VIL will short. Dout will be 15625 *G * (Vio) / (VRH-VRL+Vro). It‟s called Doff. Save Doff in memory, and then Clear AZ bit to restart the ADC module. Pass the first 2 ADC interrupts for ignoring the unstable ADC result. When measuring analog signal, Doff should be deducted. 11.5. ADC Digital Output FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y The ADC digital output deducted by Doff is ADC Gain. The ADC Gain doesn‟t change as VDD changes. The suggested values for common mode voltages at ADC input and reference voltage are 1V~2V. ADC input gain could be set by ADG[1:0] register flag. Please see Section 10.1 for detail. 11.6. ADC Resolution ADC resolution is mainly affected by the ADC sampling counts and the ADC reference voltage. Generally speaking, the more times ADC samples the analog input signal, the more precise the digital output is. The ADC sampling counts could be decided by ADM[2:0] register flag. The ADC digital output rolling counts versus ADM[2:0] and Reference voltage table are shown as follows: (VRH, VRL) =0.4V, (VIH, VIL) =0.2V, VRL=VIL=AGND. G=1 Table 11-1 ADC rolling counts versus ADM ADM 000 001 010 011 100 101 110 Rolling counts 10 6 4 3 3 2 1 (VRH, VRL) =VR, (VIH, VIL) =1/2 VR, VRL=VIL=AGND. G=1 ADM=101 Table 11-2 ADC rolling counts versus VR VR 0.05 0.1 0.2 0.3 0.4 0.6 0.8 1.0 Rolling counts 31 15 5 3 2 2 4 9 Rev. 1.4 116/146 FS98O22 12. Low Noise Operation Amplifier Guide The input noise of CMOS OPAMP is generally much larger than the one of a Bipolar OPAMP. Moreover, the flick noise (1/f noise) of CMOS is a killer for low frequency small signal measurement. But the need for input bias current in Bipolar OPAMP causes that some transducers can not be used. In general, bipolar process is not good for highly integrated Ics. FS98O22 use special CMOS low noise circuit design, and under normal conditions, the input noise is controlled under 1μVpp (0.1Hz~1Hz). FS98O22 is good for transducer applications because there is no need to consider input bias current. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Most of the input noise in CMOS OPAMP comes from input differential amplification. S_CHCK can be set to switch the differential amplification: 00 for positive Offset Voltage, 01 for negative Offset voltage. When using one clock pulse to switch input differential amplification, that is called chopper mode. In general, chopper frequency is set between 1 kHz and 2 KHz. Under chopper mode, the input noise peak-to-peak voltage in FS98O22 is less than 0.5μV (0.1Hz~1Hz). But an equivalent input current of less than 100pA is generated, due to the effect of switching. 12.1. Single End Amplifier Application Measurement of small signal usually takes consideration of the drifting of an OPAMP offset voltage. In the Figure below, the negative input is connected to AGND. It is also possible to measure the ADC‟s negative input and deduct this value; in order to correct the error caused by the Amplifier‟s offset voltage drifting. Because AGND provides current output in applications, AIN1 is used as negative input measurement point to avoid unnecessary voltage error. OPAMP input offset is amplified by an amplifier then inputted to ADC. Too much amplification can cause OPAMP output move beyond ADC linear operation range. Hence, under normal conditions, OPAMP amplification should be less than 50 times. Please see Figure 12-1 for example. Figure 12-1 single end amplifier application example Rev. 1.4 117/146 FS98O22 12.2. Differential Amplifier Measurement of differential signal is often used in bridge sensor applications. As shown in the differential amplifier below, VS Pin is used as power input for bridge sensor, ADC reference voltage is also from VS Pin after voltage division. When there is a small change in VS, ADC output does not change. Connecting AIN2 to ADC negative input can adjust the zero point of bridge sensor. When starting chopper mode, the amplification should be less than 100 times. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Please see Figure 12-2 for example. Figure 12-2 differential amplifier example Rev. 1.4 118/146 FS98O22 13. LCD Driver FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y FS98O22 embeds a LCD driver. The control signal are COM1~COM4 and SEG1~SEG12. The user could set the SEG register flags to drive a static or multiplexed LCD panel. FS98O22 LCD driver could drive up to 20 segments multiplexed with up to 4 commons. Please see Figure 13-1. COM1~COM4 4X20 LCD FS98O22 SEG1 ~ SEG20 Figure 13-1 LCD driver control block FS98O22 LCD driver has 4 kinds of control mode: static, 1/2 duty, 1/3 duty and 1/4 duty. The control mode depends on the LCD panel The user could setup LCD_DUTY[1:0] register flags to choose one. Take a 1/4 duty control mode number LCD for example, if the user wants to show number 9 in LCD, the SEG 1 includes 4 commons as [1,0,1,1] and the SEG2 include 4 commons as [1,1,1,1]. Please see Figure 13-2. Static mode 1/2 duty mode 1/3 duty mode 1/4 duty mode Figure 13-2 LCD control mode Rev. 1.4 119/146 FS98O22 The LCD frame frequency could be setup by setting the LCDCKS[1:0] register flags. FS98O22 divides the LCD Module input clock to get LCDCK. (Please see Table 13-1 and Table 13-2) Table 13-1 LCD frame frequency selection table LCDCKS [1:0] LCD frame frequency (LCDCK) LCD Input clock Frequency/8 01 LCD Input clock Frequency/16 10 LCD Input clock Frequency/32 11 LCD Input clock Frequency/64 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 00 Table 13-2 LCD duty selection table LCD_DUTY [1:0] Control mode Rev. 1.4 SEG 1 – SEG12 bit7 bit6 bit5 bit4 bit3 bit2 - - COM2 COM1 - - COM3 COM2 COM1 - 00 static - - 01 1/2 - - 10 1/3 - 11 1/4 COM4 bit1 bit0 COM2 COM1 COM3 COM2 COM1 COM3 COM2 COM1 COM4 COM3 COM2 COM1 120/146 FS98O22 LCDCK COM1 1/4 duty COM2 COM3 COM4 COM1 COM2 COM3 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1/3 duty COM4 COM1 1/2 duty COM2 COM3 COM4 COM1 static COM2 COM3 COM4 Figure 13-3 LCD duty mode working cycle Rev. 1.4 121/146 FS98O22 FS98O22 LCD driver has 3 voltage bias ports, such as V1, V2 and V3, and 2 kinds of power mode: 1/3 bias and 1/2 bias. Please see the following description to setup the LCD power system. 1/3 bias power system (Please see Figure 13-4 and 13-5) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Figure 13-4 1/3 bias LCD power system circuit connection example 1/4 duty, 1/3 bias 1/3duty, 1/3bias Figure 13-5 1/3 bias LCD power system clock Rev. 1.4 122/146 FS98O22 1/2 bias power system (Please see Figure 13-6 and 13-17) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Figure 13-6 1/2 bias LCD power system circuit connection example 1/4 duty, 1/2 bias 1/3duty, 1/2bias Figure 13-7 1/2 bias LCD power system clock Rev. 1.4 123/146 FS98O22 Table 13-3 FS98O22 LCD driver register table Address Bit 4 Value on Power on Reset SEG1 [3:0] uuuuuuuu SEG3 [3:0] uuuuuuuu SEG5 [3:0] uuuuuuuu SEG7 [3:0] uuuuuuuu SEG9 [3:0] uuuuuuuu SEG11 [3:0] uuuuuuuu SEG13 [3:0] uuuuuuuu SEG15 [3:0] uuuuuuuu SEG17 [3:0] uuuuuuuu SEG19 [3:0] uuuuuuuu LEVEL LCD_DUTY[1:0] ENPMPL 00000000 Bit 3 Bit 2 Bit 1 Bit 0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 54H Referenced Bit 7 Bit 6 Bit 5 Section LCD1 13 SEG2 [3:0] LCD2 13 SEG4 [3:0] LCD3 13 SEG6 [3:0] LCD4 13 SEG8 [3:0] LCD5 13 SEG10 [3:0] LCD6 13 SEG12 [3:0] LCD7 13 SEG14 [3:0] LCD8 13 SEG16 [3:0] LCD9 13 SEG18 [3:0] LCD10 13 SEG20 [3:0] LCDENR 13 LCDCKS [1:0] LCDEN Name Register LCD1 at address 40H property R/W-X R/W-X LCD1 R/W-X R/W-X R/W-X R/W-X SEG2 [3:0] R/W-X SEG1 [3:0] Bit7 Bit 7-4 R/W-X Bit0 SEG2[3]: LCD driver control signal: SEG2 with COM4 data. SEG2[2]: LCD driver control signal: SEG2 with COM3 data. SEG2[1]: LCD driver control signal: SEG2 with COM2 data. SEG2[0]: LCD driver control signal: SEG2 with COM1 data. Bit 3-0 SEG1[3]: LCD driver control signal: SEG1 with COM4 data. SEG1[2]: LCD driver control signal: SEG1 with COM3 data. SEG1[1]: LCD driver control signal: SEG1 with COM2 data. SEG1[0]: LCD driver control signal: SEG1 with COM1 data. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 124/146 FS98O22 Register LCD2 at address 41H property R/W-X R/W-X LCD2 R/W-X R/W-X R/W-X R/W-X SEG4 [3:0] R/W-X SEG3 [3:0] Bit7 Bit0 SEG4[3]: LCD driver control signal: SEG4 with COM4 data. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-4 R/W-X SEG4[2]: LCD driver control signal: SEG4 with COM3 data. SEG4[1]: LCD driver control signal: SEG4 with COM2 data. SEG4[0]: LCD driver control signal: SEG4 with COM1 data. Bit 3-0 SEG3[3]: LCD driver control signal: SEG3 with COM4 data. SEG3[2]: LCD driver control signal: SEG3 with COM3 data. SEG3[1]: LCD driver control signal: SEG3 with COM2 data. SEG3[0]: LCD driver control signal: SEG3 with COM1 data. Register LCD3 at address 42H property R/W-X R/W-X LCD3 R/W-X R/W-X R/W-X R/W-X SEG6 [3:0] R/W-X SEG5 [3:0] Bit7 Bit 7-4 R/W-X Bit0 SEG6[3]: LCD driver control signal: SEG6 with COM4 data. SEG6[2]: LCD driver control signal: SEG6 with COM3 data. SEG6[1]: LCD driver control signal: SEG6 with COM2 data. SEG6[0]: LCD driver control signal: SEG6 with COM1 data. Bit 3-0 SEG5[3]: LCD driver control signal: SEG5 with COM4 data. SEG5[2]: LCD driver control signal: SEG5 with COM3 data. SEG5[1]: LCD driver control signal: SEG5 with COM2 data. SEG5[0]: LCD driver control signal: SEG5 with COM1 data. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 125/146 FS98O22 Register LCD4 at address 43H property R/W-X R/W-X LCD4 R/W-X R/W-X R/W-X R/W-X SEG8 [3:0] R/W-X SEG7 [3:0] Bit7 Bit0 SEG8[3]: LCD driver control signal: SEG8 with COM4 data. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-4 R/W-X SEG8[2]: LCD driver control signal: SEG8 with COM3 data. SEG8[1]: LCD driver control signal: SEG8 with COM2 data. SEG8[0]: LCD driver control signal: SEG8 with COM1 data. Bit 3-0 SEG7[3]: LCD driver control signal: SEG7 with COM4 data. SEG7[2]: LCD driver control signal: SEG7 with COM3 data. SEG7[1]: LCD driver control signal: SEG7 with COM2 data. SEG7[0]: LCD driver control signal: SEG7 with COM1 data. Register LCD5 at address 44H property R/W-X R/W-X LCD5 R/W-X R/W-X R/W-X R/W-X SEG10 [3:0] R/W-X SEG9 [3:0] Bit7 Bit 7-4 R/W-X Bit0 SEG10[3]: LCD driver control signal: SEG10 with COM4 data. SEG10[2]: LCD driver control signal: SEG10 with COM3 data. SEG10[1]: LCD driver control signal: SEG10 with COM2 data. SEG10[0]: LCD driver control signal: SEG10 with COM1 data. Bit 3-0 SEG9[3]: LCD driver control signal: SEG9 with COM4 data. SEG9[2]: LCD driver control signal: SEG9 with COM3 data. SEG9[1]: LCD driver control signal: SEG9 with COM2 data. SEG9[0]: LCD driver control signal: SEG9 with COM1 data. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 126/146 FS98O22 Register LCD6 at address 45H property R/W-X R/W-X LCD6 R/W-X R/W-X R/W-X R/W-X SEG12 [3:0] R/W-X R/W-X SEG11 [3:0] Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit7 Bit 7-4 SEG12[3]: LCD driver control signal: SEG12 with COM4 data. SEG12[2]: LCD driver control signal: SEG12 with COM3 data. SEG12[1]: LCD driver control signal: SEG12 with COM2 data. SEG12[0]: LCD driver control signal: SEG12 with COM1 data. Bit 3-0 SEG11[3]: LCD driver control signal: SEG11 with COM4 data. SEG11[2]: LCD driver control signal: SEG11 with COM3 data. SEG11[1]: LCD driver control signal: SEG11 with COM2 data. SEG11[0]: LCD driver control signal: SEG11 with COM1 data. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 127/146 FS98O22 Register LCDENR at address 54H property LCDENR R/W-0 R/W-0 LCDCKS [1:0] R/W-0 U-0 R/W-0 LCDEN LEVEL R/W-0 LCD_DUTY[1:0] Bit7 Bit 7-6 R/W-0 R/W-0 ENPMPL Bit0 LCDCKS[1:0]: LCD frame frequency selector FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 11 = LCD frame frequency is assigned to be LCD input clock frequency/8 10 = LCD frame frequency is assigned to be LCD input clock frequency/16 01 = LCD frame frequency is assigned to be LCD input clock frequency/32 00 = LCD frame frequency is assigned to be LCD input clock frequency/64 Bit 5 LCDEN: LCD driver enable register flag 1 = The LCD driver is enabled. LCD clock is started 0 = The LCD driver is disabled. LCD clock is stopped Bit 3 LEVEL: LCD driver voltage bias selector. 0 = LCD driver voltage bias is assigned to be 1/3 bias. 1 = LCD driver voltage bias is assigned to be 1/2 bias. Bit 2-1 LCD_DUTY[1:0]: LCD driver control mode (SEG duty cycle) 11 = LCD driver control mode is assigned to be 1/4 duty cycle mode. 10 = LCD driver control mode is assigned to be 1/3 duty cycle mode. 01 = LCD driver control mode is assigned to be 1/2 duty cycle mode. 00 = LCD driver control mode is assigned to be static mode Bit 0 ENPMPL: LCD driver charge pump enable register flag 1 = LCD driver charge pump is enabled. 0 = LCD driver charge pump is disabled. Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset „1‟ = Bit is Set „0‟ = Bit is Cleared Rev. 1.4 X = Bit is unknown 128/146 FS98O22 Table 13-4 LCD driver register table Address Name Referenced Section 14H 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 54H MCK LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCDENR 5 13 13 13 13 13 13 13 13 13 13 13 Bit 7 Bit 6 Bit 5 Bit 4 -M5_CK SEG2 [3:0] SEG4 [3:0] SEG6 [3:0] SEG8 [3:0] SEG10 [3:0] SEG12 [3:0] SEG14 [3:0] SEG16 [3:0] SEG18 [3:0] SEG20 [3:0] LCDCKS [1:0] LCDEN Bit 2 Bit 1 M3_CK Bit 0 -M1_CK M0_CK SEG1 [3:0] SEG3 [3:0] SEG5 [3:0] SEG7 [3:0] SEG9 [3:0] SEG11 [3:0] SEG13 [3:0] SEG15 [3:0] SEG17 [3:0] SEG19 [3:0] LEVEL LCD_DUTY[1:0] ENPMPL Value on Power on Reset 00000000 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y -- Bit 3 LCD operation 1. 2. 3. 4. Connect the 20 segment ports and 4 common ports to LCD panel. Setup LEVEL register flag to decide the LCD driver power system. (0 = 1/3 bias, 1 = 1/2 bias) Set ENPMPL to enable the LCD charge pump. Setup M0_CK,M1_CK,M3_CK and M5_CK to decide the LCD input clock frequency.(Refer to Section 5.7) Table 13-5 CLK selection table M1_CK CLK 0 MCK 1 MCK/4 Table 13-6 MCK selection table M3_CK M0_CK MCK X 0 ICK 0 1 ECK 1 1 ECK/2 Table 13-7 TMCLK selection table M5_CK TMCLK (Timer and LCD Module input Clock) 0 CLK/1000 1 ECK/32 5. Setup LCDCKS[1:0] register flags to decide the LCD Clock frequency. Rev. 1.4 129/146 FS98O22 Table 13-8 LCD frame frequency selection table LCDCKS [1:0] LCD frame frequency (LCDCK) LCD Input clock Frequency/8 01 LCD Input clock Frequency/16 10 LCD Input clock Frequency/32 11 LCD Input clock Frequency/64 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 00 6. Setup LCD_DUTY[1:0] register flag to decide the control mode.(SEG duty cycle) Table 13-9 LCD duty control mode selection table 7. LCD_DUTY [1:0] Control mode 00 static 01 1/2 10 1/3 11 1/4 Set LCDEN to enable the LCD driver. Rev. 1.4 130/146 FS98O22 14. Halt and Sleep Modes FS98O22 supports low power working mode. When the user want FS98O22 to do nothing and just stand by, FS98O22 could be set to Halt mode or Sleep mode to reduce the power consumption by stopping the CPU core working. The two modes will be described below. Halt Mode FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y After CPU executes a Halt command, CPU Program Counter (PC) stops counting until an interrupt command is issued. To avoid program errors caused by Interrupt Return, it is suggested to add a NOP command after Halt to guarantee the program‟s normal execution when turning back. Sleep Mode After CPU executes Sleep command, all oscillators stop working until an external interrupt command is issued or the CPU is reset. To avoid program errors caused by Interrupt return, it is suggested to add a NOP command after Sleep to guarantee the program‟s normal execution. The sleep mode power consumption is about 3 uA. To make sure that CPU consumes minimum power in Sleep mode, it is necessary to close all power blocks and analog circuits before issuing the Sleep command, and make sure that all I/O Ports are in VDD or VSS voltage levels. It is recommended that users execute the following program before issuing the Sleep command: CLRF NETA ; As Reset state CLRF NETB ; As Reset state CLRF NETC ; As Reset state CLRF NETD ; As Reset state CLRF NETE ; As Reset state CLRF NETF CLRF PT1PU ; Pull up resistor is disconnected CLRF PT1EN ; PT1[7:0] is assigned to be input ports. CLRF AINENB ; Set PT1 as Analog Input Pin MOVLW MOVWF interrupt) 01h PT2PU MOVLW 0Feh MOVWF PT2EN ; PT2 Pull up resistor is disconnected except port 0(external ; PT2 ports are assigned to be output ports except port 0 CLRF PT2 ; Set PT2 [7:1] Output Low CLRF INTF ; Clear the interrupt flags MOVLW 081h MOVWF INTE SLEEP NOP wakes up. Rev. 1.4 ; As Reset state ; Enable the external interrupt ; Set the FS98O22 into Sleep mode ; Guarantee that the program works normally when CPU 131/146 FS98O22 Instruction Set The FS98O22 instruction set consists of 37 instructions. Each instruction could be converted to 16-bit OPCODE. The detailed descriptions are shown in the following sections. 14.1. Instruction Set Summary Table 14-1 FS98O22 instruction set table Operation [W] [W] + k [PC] [PC] + 1 + [W] [Destination] [f] + [W] [Destination] [f] + [W] + C [W] [W] AND k [Destination] [W] AND [f] [f<b>] 0 [f<b>] 1 Skip if [f<b>] = 0 Skip if [f<b>] = 1 Push PC + 1 and GOTO k [f] 0 Clear watch dog timer [f] NOT([f]) [Destination] [f] -1 [Destination] [f] -1, skip if the result is zero PC k CPU Stop [Destination] [f] +1 [Destination] [f] + 1, skip if the result is zero [W] [W] | k [Destination] [W] | [f] [W] [f] [W] k [f] [W] No operation Pop PC and GIE = 1 RETURN and W = k Pop PC [Destination<n+1>] [f<n>] [Destination<n-1>] [f<n>] Stop OSC [W] k – [W] [Destination] [f] – [W] ‧ [Destination] [f] – [W] –C [W] [W] XOR k [Destination] [W] XOR [f] Cycle 1 2 1 1 1 1 1 1 1, 2 1, 2 2 1 1 1 1 1, 2 2 1 1 1, 2 C, DC, Z None C, DC, Z C, DC, Z Z Z None None None None None Z None Z Z None None None Z None Flag 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 Z Z None None None None None None None C,Z C, Z PD C, DC, Z C, DC, Z C, DC, Z 1 1 Z Z FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Instruction ADDLW k ADDPCW ADDWF f, d ADDWFC f, d ANDLW k ANDWF f, d BCF f, b BSF f, b BTFSC f, b BTFSS f, b CALL k CLRF f CLRWDT COMF f, d DECF f, d DECFSZ f, d GOTO k HALT INCF f, d INCFSZ f, d IORLW k IORWF f, d MOVFW f MOVLW k MOVWF f NOP RETFIE RETLW k RETURN RLF f, d RRF f, d SLEEP SUBLW k SUBWF f, d SUBWFC f, d XORLW k XORWF f, d Rev. 1.4 132/146 FS98O22 Note: f: memory address (00h ~ 7Fh). W: work register. k: literal field, constant data or label. d: destination select: d=0 store result in W, d=1: store result in memory address f. b: bit select (0~7). [f]: the content of memory address f. PC: program counter. C: Carry flag DC: Digit carry flag Z: Zero flag PD: power down flag TO: watchdog time out flag WDT: watchdog timer counter FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Rev. 1.4 133/146 FS98O22 14.2. Instruction Description (By alphabetically) ADDLW Syntax FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Operation Flag Affected Description Cycle Example: ADDLW 08h Add Literal to W ADDLW k 0 k FFh [W] [W] + k C, DC, Z The content of Work register add literal “k” in Work register 1 Before instruction: W = 08h After instruction: W = 10h ADDPCW Syntax Operation Flag Affected Description Cycle Example 1: ADDPCW Example 2: ADDPCW Example 3: ADDPCW Add W to PC ADDPCW [PC] [PC] + 1 + [W], [W] < 79h [PC] [PC] + 1 + ([W] – 100h), otherwise None The relative address PC + 1 + W are loaded into PC. 2 Before instruction: W = 7Fh, PC = 0212h After instruction: PC = 0292h Before instruction: W = 80h, PC = 0212h After instruction: PC = 0193h Before instruction: W = Feh, PC = 0212h After instruction: PC = 0211h Add W to f ADDWF f, d 0 f FFh d [0,1] Operation [Destination] [f] + [W] Flag Affected C, CD, Z Description Add the content of the W register and [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in f. Cycle 1 Example 1: Before instruction: ADDWF OPERAND, 0 OPERAND = C2h W = 17h After instruction: OPERAND = C2h W = D9h Example 2: Before instruction: ADDWF OPERAND, 1 OPERAND = C2h W = 17h After instruction: OPERAND = D9h W = 17h ADDWF Syntax Rev. 1.4 134/146 FS98O22 Add W, f and Carry ADDWFC f, d 0 f FFh d [0,1] Operation [Destination] [f] + [W] + C Flag Affected C, DC, Z Description Add the content of the W register, [f] and Carry bit. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in f. Cycle 1 Example Before instruction: ADDWFC OPERAND,1 C = 1 OPERAND = 02h W = 4Dh FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y ADDWFC Syntax After instruction: C=0 OPERAND = 50h W = 4Dh ANDLW Syntax Operation Flag Affected Description Cycle Example: ANDLW 5Fh ANDWF Syntax Operation Flag Affected Description Cycle Example 1: ANDWF OPERAND,0 Example 2: ANDWF OPERAND,1 Rev. 1.4 AND literal with W ANDLW k 0 k FFh [W] [W] AND k Z AND the content of the W register with the eight-bit literal “k”. The result is stored in the W register. 1 Before instruction: W = A3h After instruction: W = 03h AND W and f ANDWF f, d 0 f FFh d [0,1] [Destination] [W] AND [f] Z AND the content of the W register with [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in f. 1 Before instruction: W = 0Fh, OPERAND = 88h After instruction: W = 08h, OPERAND = 88h Before instruction: W = 0Fh, OPERAND = 88h After instruction: W = 88h, OPERAND = 08h 135/146 FS98O22 BCF Syntax FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Operation Flag Affected Description Cycle Example: BCF FLAG, 2 Bit Clear f BCF f, b 0 f FFh 0b7 [f<b>] 0 None Bit b in [f] is reset to 0. 1 Before instruction: FLAG = 8Dh After instruction: FLAG = 89h BSF Syntax Operation Flag Affected Description Cycle Example: BSF FLAG, 2 Bit Set f BSF f, b 0 f FFh 0b7 [f<b>] 1 None Bit b in [f] is set to 1. 1 Before instruction: FLAG = 89h After instruction: FLAG = 8Dh Bit Test skip if Clear BTFSC f, b 0 f FFh 0b7 Operation Skip if [f<b>] = 0 Flag Affected None Description If bit „b‟ in [f] is 0, the next fetched instruction is discarded and a NOP is executed instead making it a two-cycle instruction. Cycle 1, 2 Example: Before instruction: Node BTFSC FLAG, PC = address (Node) 2 After instruction: OP1 : If FLAG<2> = 0 OP2 : PC = address(OP2) If FLAG<2> = 1 PC = address(OP1) BTFSC Syntax Bit Test skip if Set BTFSS f, b 0 f FFh 0b7 Operation Skip if [f<b>] = 1 Flag Affected None Description If bit „b‟ in [f] is 1, the next fetched instruction is discarded and a NOP is executed instead making it a two-cycle instruction. Cycle 1, 2 Example: Before instruction: Node BTFSS FLAG, PC = address (Node) 2 After instruction: OP1 : If FLAG<2> = 0 OP2 : PC = address(OP1) If FLAG<2> = 1 PC = address(OP2) BTFSS Syntax Rev. 1.4 136/146 FS98O22 CALL Syntax Operation Flag Affected Description Cycle Clear f CLRF f 0 f 255 [f] 0 None Reset the content of memory address f 1 Before instruction: WORK = 5Ah After instruction: WORK = 00h FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y CLRF Syntax Subroutine CALL CALL k 0 k 1FFFh Push Stack [Top Stack] PC + 1 PC k None Subroutine Call. First, return address PC + 1 is pushed onto the stack. The immediate address is loaded into PC. 2 Operation Flag Affected Description Cycle Example: CLRF WORK CLRWDT Syntax Operation Flag Affected Description Cycle Example: CLRWDT Clear watch dog timer CLRWDT Watch dog timer counter will be reset None CLRWDT instruction will reset watch dog timer counter. 1 After instruction: WDT = 0 COMF Syntax Complement f COMF f, d 0 f 255 d [0,1] [f] NOT([f]) Z [f] is complemented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f] 1 Before instruction: W = 88h, OPERAND = 23h After instruction: W = DCh, OPERAND = 23h Before instruction: W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = DCh Operation Flag Affected Description Cycle Example 1: COMF OPERAND,0 Example 2: COMF OPERAND,1 Rev. 1.4 137/146 FS98O22 DECF Syntax Operation Flag Affected Description FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Cycle Example 1: DECF OPERAND,0 Decrement f DECF f, d 0 f 255 d [0,1] [Destination] [f] -1 Z [f] is decremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. 1 Before instruction: W = 88h, OPERAND = 23h After instruction: W = 22h, OPERAND = 23h Before instruction: W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = 22h Example 2: DECF OPERAND,1 Decrement f, skip if zero DECFSZ f, d 0 f FFh d [0,1] Operation [Destination] [f] -1, skip if the result is zero Flag Affected None Description [f] is decremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. If the result is 0, then the next fetched instruction is discarded and a NOP is executed instead making it a two-cycle instruction. Cycle 1, 2 Example: Before instruction: Node DECFSZ PC = address (Node) FLAG, 1 After instruction: OP1 : [FLAG] = [FLAG] – 1 OP2 : If [FLAG] = 0 PC = address(OP1) If [FLAG] 0 PC = address(OP2) DECFSZ Syntax GOTO Syntax Operation Flag Affected Description Cycle HALT Syntax Operation Flag Affected Description Cycle Rev. 1.4 Unconditional Branch GOTO k 0 k 1FFFh PC k None The immediate address is loaded into PC. 2 Stop CPU Core Clock HALT CPU Stop None CPU clock is stopped. Oscillator is running. CPU can be waked up by internal and external interrupt sources. 1 138/146 FS98O22 INCF Syntax Operation Flag Affected Description FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Cycle Example 1: INCF OPERAND,0 Increment f INCF f, d 0 f FFh d [0,1] [Destination] [f] +1 Z [f] is incremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. 1 Before instruction: W = 88h, OPERAND = 23h After instruction: W = 24h, OPERAND = 23h Before instruction: W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = 24h Example 2: INCF OPERAND,1 Increment f, skip if zero INCFSZ f, d 0 f FFh d [0,1] Operation [Destination] [f] + 1, skip if the result is zero Flag Affected None Description [f] is incremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. If the result is 0, then the next fetched instruction is discarded and a NOP is executed instead making it a two-cycle instruction. Cycle 1, 2 Example: Before instruction: Node INCFSZ FLAG, PC = address (Node) 1 After instruction: OP1 : [FLAG] = [FLAG] + 1 OP2 : If [FLAG] = 0 PC = address(OP2) If [FLAG] 0 PC = address(OP1) INCFSZ Syntax IORLW Syntax Operation Flag Affected Description Cycle Example: IORLW Rev. 1.4 85h Inclusive OR literal with W IORLW k 0 k FFh [W] [W] | k Z Inclusive OR the content of the W register and the eight-bit literal “k”. The result is stored in the W register. 1 Before instruction: W = 69h After instruction: W = Edh 139/146 FS98O22 Inclusive OR W with f IORWF f, d 0 f FFh d [0,1] Operation [Destination] [W] | [f] Flag Affected Z Description Inclusive OR the content of the W register and [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. Cycle 1 Example: Before instruction: IORWF OPERAND,1 W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = Abh FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y IORWF Syntax Move f to W MOVFW f 0 f FFh Operation [W] [f] Flag Affected None Description Move data from [f] to the W register. Cycle 1 Example: Before instruction: MOVFW OPERAND W = 88h, OPERAND = 23h After instruction: W = 23h, OPERAND = 23h MOVFW Syntax MOVLW Syntax Operation Flag Affected Description Cycle Example: MOVLW 23h Move literal to W MOVLW k 0 k FFh [W] k None Move the eight-bit literal “k” to the content of the W register. 1 Before instruction: W = 88h After instruction: W = 23h Move W to f MOVWF f 0 f FFh Operation [f] [W] Flag Affected None Description Move data from the W register to [f]. Cycle 1 Example: Before instruction: MOVWF OPERAND W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = 88h MOVWF Syntax NOP Syntax Operation Flag Affected Description Cycle Rev. 1.4 No Operation NOP No Operation None No operation. NOP is used for one instruction cycle delay. 1 140/146 FS98O22 RETFIE Syntax Operation Flag Affected Description Cycle Return and move literal to W RETLW k 0 k FFh [W] k [Top Stack] => PC Pop Stack None Move the eight-bit literal “k” to the content of the W register. The program counter is loaded from the top stack, then pop stack. 2 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y RETLW Syntax Return from Interrupt RETFIE [Top Stack] => PC Pop Stack 1 => GIE None The program counter is loaded from the top stack, then pop stack. Setting the GIE bit enables interrupts. 2 Operation Flag Affected Description Cycle Return Syntax Operation Flag Affected Description Cycle RLF Syntax Operation Flag Affected Description Cycle Example: RLF OPERAND, 1 Rev. 1.4 Return from Subroutine RETURN [Top Stack] => PC Pop Stack None The program counter is loaded from the top stack, then pop stack. 2 Rotate left [f] through Carry RLF f, d 0 f FFh d [0,1] [Destination<n+1>] [f<n>] [Destination<0>] C C [f<7>] C, Z [f] is rotated one bit to the left through the Carry bit. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. 1 Before instruction: C=0 W = 88h, OPERAND = E6h After instruction: C=1 W = 88h, OPERAND = CCh 141/146 FS98O22 RRF Syntax Operation FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Flag Affected Description Rotate right [f] through Carry RRF f, d 0 f FFh d [0,1] [Destination<n-1>] [f<n>] [Destination<7>] C C [f<7>] C [f] is rotated one bit to the right through the Carry bit. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. Cycle Example: RRF OPERAND, 0 1 Before instruction: C=0 OPERAND = 95h After instruction: C=1 W = 4Ah, OPERAND = 95h SLEEP Syntax Operation Flag Affected Description Cycle Oscillator stop SLEEP CPU oscillator is stopped PD 29 CPU oscillator is stopped. CPU can be waked up by external interrupt sources. 1 SUBLW Syntax Subtract W from literal SUBLW k 0 k FFh [W] k – [W] C, DC, Z Subtract the content of the W register from the eight-bit literal “k”. The result is stored in the W register. 1 Before instruction: W = 01h After instruction: W = 01h C=1 Z=0 Before instruction: W = 02h After instruction: W = 00h C=1 Z=1 Before instruction: W = 03h After instruction: W = FFh C=0 Z=0 Operation Flag Affected Description Cycle Example 1: SUBLW 02h Example 2: SUBLW 02h Example 3: SUBLW 02h 29 Please make sure all interrupt flags are cleared before running SLEEP; "NOP" command must follow HALT and SLEEP commands. Rev. 1.4 142/146 FS98O22 Subtract W from f SUBWF f, d 0 f FFh d [0,1] Operation [Destination] [f] – [W] Flag Affected C, DC, Z Description Subtract the content of the W register from [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f], Cycle 1 Example 1: Before instruction: SUBWF OPERAND, OPERAND = 33h, W = 01h 1 After instruction: OPERAND = 32h C=1 Z=0 Example 2: Before instruction: SUBWF OPERAND, OPERAND = 01h, W = 01h 1 After instruction: OPERAND = 00h C=1 Z=1 Example 3: Before instruction: SUBWF OPERAND, OPERAND = 04h, W = 05h 1 After instruction: OPERAND = FFh C=0 Z=0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y SUBWF Syntax SUBWFC Syntax Operation Flag Affected Description Cycle Example 1: SUBWFC OPERAND, 1 Example 2: SUBWFC OPERAND, 1 Example 3: SUBWFC OPERAND, 1 Rev. 1.4 Subtract W and Carry from f SUBWFC f, d 0 f FFh d [0,1] ‧ [Destination] [f] – [W] –C C, DC, Z Subtract the content of the W register from [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. 1 Before instruction: OPERAND = 33h, W = 01h C=1 After instruction: OPERAND = 32h, C = 1, Z = 0 Before instruction: OPERAND = 02h, W = 01h C=0 After instruction: OPERAND = 00h, C = 1, Z = 1 Before instruction: OPERAND = 04h, W = 05h C=0 After instruction: OPERAND = Feh, C = 0, Z = 0 143/146 FS98O22 XORLW Syntax Operation Flag Affected Description 5Fh 1 Before instruction: W = Ach After instruction: W = F3h FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Cycle Example: XORLW Exclusive OR literal with W XORLW k 0 k FFh [W] [W] XOR k Z Exclusive OR the content of the W register and the eight-bit literal “k”. The result is stored in the W register. Exclusive OR W and f XORWF f, d 0 f FFh d [0,1] Operation [Destination] [W] XOR [f] Flag Affected Z Description Exclusive OR the content of the W register and [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. Cycle 1 Example: Before instruction: XORWF OPERAND, OPERAND = 5Fh, W = Ach 1 After instruction: OPERAND = F3h XORWF Syntax Rev. 1.4 144/146 FS98O22 15. Package Information FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 15.1. Package Outline Figure 15-1 FS98O22 package outline Rev. 1.4 145/146 FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 15.2. Package Outline(3.2mm QFP100) Figure 15-2 FS98O22 3.2mm QFP100 package outline 16. Revision History Ver. 1.0 1.1 Date 2006/2/16 2006/3/29 1.2 1.3 2008/12/25 2009/07/08 Page All 17~19 23 134~135 33 20 1.4 2011/07/21 20 20 Rev. 1.4 Description Initial release. PC stack numbers modified 6 to 8, and PC bitwidth modified 11 to 12 PC stack numbers modified 6 to 8, and PC bitwidth modified 11 to 12 LEVEL setting of LCD bias Low Battery Comparator Input Selector Revise Ambient Operating Temperature from -10~85 C to -40~85 C and add LTOL test condition description Revise Sleep Current Unit:μ A Revise Electrical Characteristics input offset TYP:1.5mV 146/146