QIMONDA HYB18L128160BC-7.5

January 2007
HYB18L128160BF-7.5
HYE18L128160BF-7.5
HYB18L128160 B C- 7 . 5
HYE18L128160 B C- 7 . 5
DRAMs for Mobile Applications
128-Mbit Mobile-RAM
Data S heet
Rev. 1.71
Data Sheet,
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
HYB18L128160BF-7.5; HYE18L128160BF-7.5; HYB18L128160BC-7.5; HYE18L128160BC-7.5
Revision History:
All
Rev. 1.71
New Qimonda Template
Previous Revision:
1.70
all
new template (logo)
all
VDD, VDDQ changed to 1.70V-1.95V
Previous Revision:
2
2007-01
1.61
added disclaimer
49
Figure 47: Updated
28
Figure 25: Updated
12
Chapter 2.1: added to note 6: Programming of the Extended Mode Register...
14
Extended Mode Register table: Editorial changes
Chapter 2.2.1.6: Editorial change
39
Chapter 2.4.9.2: changed last paragraph by: If during normal operation...
15, 28, 46, 46
Table 8, Table 12 and Table 21: tIH changed
Table 21: note 7 changed: If tT > 1ns, a value of [0.5 x (tT -1)] ns...
Table 20: editorial changes
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Rev. 1.71, 2007-01
05282004-NZNK-8T0D
2
2005-03-07
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
OverviewFeatures
1
Overview
This chapter gives an overview of the DRAMs for Mobile Applications product family and describes its main
characteristics.
1.1
Features
The DRAMs for Mobile Applications offers the following key features:
General Features
•
•
•
•
•
•
•
•
•
•
•
•
4 banks × 2 Mbit × 16 organization
Fully synchronous to positive clock edge
Four internal banks for concurrent operation
Programmable CAS latency: 2, 3
Programmable burst length: 1, 2, 4, 8 or full page
Programmable wrap sequence: sequential or interleaved
Programmable drive strength
Auto refresh and self refresh modes
4096 refresh cycles / 64 ms
Auto precharge
Commercial (0 °C to +70 °C) and extended (-25 °C to +85 °C) operating temperature range
54-ball P-VFBGA package (12.0 × 8.0 × 1.0 mm)
Power Saving Features
•
•
•
•
•
Low supply voltages: VDD = 1.70V to 1.95V, VDDQ = 1.70V to 1.95V
Optimized self refresh (IDD6) and standby currents (IDD2/IDD3)
Programmable Partial Array Self Refresh (PASR)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Power-Down and Deep Power Down modes
Table 1
Performance
Part Number Speed Code
- 7.5
Speed Grade
Access Time (tAC.max)
Clock Cycle Time (tCK.min)
Table 2
133
MHz
CL = 3
5.4
ns
CL = 2
6.0
ns
CL = 3
7.5
ns
CL = 2
9.5
ns
Memory Addressing Scheme
Item
Addresses
Banks
BA0, BA1
Rows
A0 - A11
Columns
A0 - A8
Data Sheet
Unit
3
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
OverviewPin Configuration
Table 3
Ordering Information
Type
Package
Description
Commercial Temperature Range
P-VFBGA-54-2 133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM
HYB18L128160BC-7.5
Extended Temperature Range
P-VFBGA-54-2 133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM
HYE18L128160BC-7.5
Table 4
Type
Ordering Information for Green Products
1)
Package
Description
Commercial Temperature Range
P-VFBGA-54-2 133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM
HYB18L128160BF-7.5
Extended Temperature Range
HYE18L128160BF-7.5
P-VFBGA-54-2 133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM
1) HYB / HYE: Designator for memory products (HYB: standard temp. range; HYE: extended temp. range)
18L: 1.8V Mobile-RAM
128: 128 MBit density
160: 16 bit interface width
B: die revision
C / F: lead-containing product (C) / green product (F)
-7.5: speed grade(s): min. clock cycle time
1.2
Pin Configuration
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Figure 1
Data Sheet
Standard Ballout 128-Mbit Mobile-RAM
4
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
OverviewDescription
1.3
Description
The HY[B/E]18L128160B[C/F] is a high-speed CMOS, dynamic random-access memory containing 134,217,728
bits. It is internally configured as a quad-bank DRAM.
The HY[B/E]18L128160B[C/F] achieves high speed data transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are
burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4,
8 or full page) in a programmed sequence.
The device operation is fully synchronous: all inputs are registered at the positive edge of CLK.
The HY[B/E]18L128160B[C/F] is especially designed for mobile applications. It operates from a 1.8V power
supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor
(OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep PowerDown (DPD) mode.
The HY[B/E]18L128160B[C/F] is housed in a 54-ball P-VFBGA package. It is available in Commercial (0 °C to
70 °C) and Extended (-25 °C to +85 °C) temperature range.
Data Sheet
5
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
OverviewDescription
C om m and
D ec ode
CS
RAS
CAS
WE
Co ntro l L ogi c
CKE
CLK
9
Data Sheet
4096
(4096 x 512 x 16)
2
Sense
Amplifier
2
Column Address
Counter / Latch
2
Data
Output
Reg.
16
B a nk Co lu m n Log ic
2
Figure 2
12
Bank 0
Memory Array
12
14
R efre sh C oun ter
A0-A11
BA0,BA1
A dd res s R e gis ter
12
B ank 0
R ow A ddres s L atc h
& Deco de r
12
Mode
Registers
R ow A ddres s M u x
Bank 3
Bank 2
Bank 1
IO Gating
DQM Mask Logic
9
16
Data
Input
Reg.
LDQM
UDQM
DQ0DQ15
Column
Decoder
Functional Block Diagram
6
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
OverviewPin Definition and Description
1.4
Pin Definition and Description
Table 5
Pin Description
Ball
Type
Detailed Function
CLK
Input
Clock: all inputs are sampled on the positive edge of CLK.
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWERDOWN (row active in any bank) or SUSPEND (access in progress). Input buffers,
excluding CLK and CKE are disabled during power-down. Input buffers, excluding CKE
are disabled during SELF REFRESH.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for
external bank selection on systems with multiple memory banks. CS is considered part of
the command code.
RAS, CAS,
WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered.
DQ0 - DQ15 I/O
Data Inputs/Output: Bi-directional data bus (16 bit)
LDQM,
UDQM
Input
Input/Output Mask: input mask signal for WRITE cycles and output enable for READ
cycles. For WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as
an output enable and places the output buffers in High-Z state when HIGH (two clocks
latency).
LDQM corresponds to the data on DQ0 - DQ7; UDQM to the data on DQ8 - DQ15.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE
or PRECHARGE command is being applied. BA0, BA1 also determine which mode
register is to be loaded during a MODE REGISTER SET command (MRS or EMRS).
A0 - A11
Input
Address Inputs: A0 - A11 define the row address during an ACTIVE command cycle. A0
- A8 define the column address during a READ or WRITE command cycle. In addition,
A10 (= AP) controls Auto Precharge operation at the end of the burst read or write cycle.
During a PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls
which bank(s) are to be precharged: if A10 is HIGH, all four banks will be precharged
regardless of the state of BA0 and BA1; if A10 is LOW, BA0, BA1 define the bank to be
precharged. During MODE REGISTER SET commands, the address inputs hold the
op-code to be loaded.
VDDQ
Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity:
VDDQ = 1.70V to 1.95V
VSSQ
Supply I/O Ground
VDD
Supply Power Supply: Power for the core logic and input buffers, VDD = 1.70V to 1.95V
VSS
Supply Ground
N.C.
–
Data Sheet
No Connect
7
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionPower On and Initialization
2
Functional Description
The 128-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits.
It is internally configured as a quad-bank DRAM.
READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A11
select the row). The address bits registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command description and device operation.
2.1
Power On and Initialization
The Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 3). Operational
procedures other than those specified may result in undefined operation.
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Figure 3
Data Sheet
Power-Up Sequence and Mode Register Sets
8
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionRegister Definition
1. At first, device core power (VDD) and device IO power (VDDQ) must be brought up simultaneously. Typically VDD
and VDDQ are driven from a single power converter output.
Assert and hold CKE and DQM to a HIGH level.
2. After VDD and VDDQ are stable and CKE is HIGH, apply stable clocks.
3. Wait for 200µs while issuing NOP or DESELECT commands.
4. Issue a PRECHARGE ALL command, followed by NOP or DESELECT commands for at least tRP period.
5. Issue two AUTO REFRESH commands, each followed by NOP or DESELECT commands for at least tRFC
period.
6. Issue two MODE REGISTER SET commands for programming the Mode Register and Extended Mode
Register, each followed by NOP or DESELECT commands for at least tMRD period; the order in which both
registers are programmed is not important. Programming of the Extended Mode Register may be omitted when
default values (half drive strength, 4 bank refresh) will be used.
Following these steps, the Mobile-RAM is ready for normal operation.
2.2
Register Definition
2.2.1
Mode Register
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes
the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst
mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it is programmed again or the device loses power.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements results in unspecified operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
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Field
Bits
Type
Description
WB
9
w
Write Burst Mode
0B
Burst Write
1B
Single Write
CL
[6:4]
w
CAS Latency
010B 2
011B 3
Note: All other bit combinations are RESERVED.
BT
3
Data Sheet
w
Burst Type
0B
Sequential
1B
Interleaved
9
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionRegister Definition
Field
Bits
Type
Description
BL
[2:0]
w
Burst Length
000B 1
001B 2
010B 4
011B 8
111B full page (Sequential burst type only)
Note: All other bit combinations are RESERVED.
2.2.1.1
Burst Length
READ and WRITE accesses to the Mobile-RAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst
types, and a full-page burst mode is available for the sequential burst type.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary
is reached. The block is uniquely selected by A1-A8 when the burst length is set to two, by A2-A8 when the burst
length is set to four and by A3-A8 when the burst length is set to eight. The remaining (least significant) address
bit(s) is (are) used to select the starting location within the block.
Full page bursts wrap within the page if the boundary is reached. Please note that full page bursts do not selfterminate; this implies that full-page read or write bursts with Auto Precharge are not legal commands.
Table 6
Burst Definition
Burst Length
Starting Column Address
A2
A1
A0
Sequential
Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
2
4
8
Full Page
Order of Accesses Within a Burst
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
n
n
n
Cn, Cn+1, Cn+2, …
not supported
NotesNotes
1.
2.
3.
4.
For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block.
For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block.
For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block.
For a full page burst, A0-Ai select the starting data element.
Data Sheet
10
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionRegister Definition
5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the
block.
2.2.1.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 6.
2.2.1.3
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock
edge n + m (for details please refer to the READ command description).
2.2.1.4
Write Burst Mode
When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write
accesses consist of single data elements only.
2.2.1.5
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array
Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive
strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE
REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed
again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified
time before initiating any subsequent operation. Violating either of these requirements result in unspecified
operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
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Bits
Type
Description
DS
[6:5]
w
Selectable Drive Strength
00B Full Drive Strength
01B Half Drive Strength (default)
Note: All other bit combinations are RESERVED.
TCSR [4:3]
Data Sheet
w
Temperature Compensated Self Refresh
XXB Superseded by on-chip temperature sensor (see text)
11
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionState Diagram
Field
Bits
Type
Description
PAS
R
[2:0]
w
Partial Array Self Refresh
000B all banks (default)
001B 1/2 array (BA1 = 0)
010B 1/4 array (BA1 = BA0 = 0)
101B 1/8 array (BA1 = BA0 = RA11 = 0)
110B 1/16 array (BA1 = BA0 = RA11 = RA10 = 0)
Note: All other bit combinations are RESERVED.
2.2.1.6
Partial Array Self Refresh (PASR)
Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be
restricted to variable portions of the total array. The selection comprises all four banks, two banks, one bank, half
of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost after a
period defined by tREF (cf. Table 14).
2.2.1.7
Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature
Sensor
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain
the stored information. This refresh requirement heavily depends on the die temperature: high temperatures
correspond to short refresh periods, and low temperatures correspond to long refresh periods.
The Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die
temperature and adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the
TCSR bits in the Extended Mode Register obsolete. It also is the superior solution in terms of compatibility and
power-saving, because
•
•
•
it is fully compatible to all processors that do not support the Extended Mode Register
it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the
lack of an external temperature sensor
it does not require any processor interaction for regular TCSR updates
2.2.1.8
Selectable Drive Strength
The drive strength of the DQ output buffers is selectable via bits A5 and A6 and shall be set load dependent. The
half drive strength is suitable for typical Mobile-RAM applications. The full drive strength is intended for heavier
loaded systems. I-V curves for full drive strength and half drive strength can be found in Table 24.
2.3
Data Sheet
State Diagram
12
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionState Diagram
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72)4%!7R ITE
WITH!U
TO0R ECHA
RGE
!#4
!C TIV E
02%
0R ECHARG
E
"34
"URST4ER MIN
A
TE
-23
-ODE2E
GIS TER 3E
T
State Diagram
13
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4
Commands
Table 7
Command Overview
Command
CS RAS CAS WE DQM
NOP DESELECT
Address
Notes
1)
H
X
X
X
X
X
L
H
H
H
X
X
ACT ACTIVE (Select bank and row)
L
L
H
H
X
Bank / Row
2)
RD
READ (Select bank and column and start read burst)
L
H
L
H
L/H
Bank / Col
3)
WR
WRITE (Select bank and column and start write burst) L
H
L
L
L/H
Bank / Col
BST
BURST TERMINATE or
DEEP POWER DOWN
L
H
H
L
X
X
4)
PRE PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
5)
ARF AUTO REFRESH or
SELF REFRESH (enter self refresh mode)
L
L
L
H
X
X
6)7)
MRS MODE REGISTER SET
L
L
L
L
X
Op-Code
8)
–
Data Write / Output Enable
–
–
–
–
L
–
9)
–
Write Mask / Output Disable (High-Z)
–
–
–
–
H
–
NO OPERATION
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A11 provide row address.
3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature (non
persistent), A10 LOW disables the Auto Precharge feature.
4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE
command is defined for READ or WRITE bursts with Auto Precharge disabled only.
5) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other
combinations of BA0, BA1 are reserved; A0 - A11 provide the op-code to be written to the selected mode register.
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read
cycles;
DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are
placed in High-Z state (two clocks latency) during read cycles.
Address (A0 - A11, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)
are all registered on the positive edge of CLK. Figure 5 shows the basic timing parameters, which apply to all
commands and operations.
Data Sheet
14
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
T#+
T#(
T#,
#,+
T)3 T)(
)NPUT
6ALID
6ALID
6ALID
$O
NgT#A
RE
!
!
"
!"!
#3
#
+
%2
!
3#
!
37
%
Figure 5
Address / Command Inputs Timing Parameters
Table 8
Inputs Timing Parameters
Parameter
Symbol
- 7.5
min.
Clock cycle time
CL = 3
tCK
CL = 2
Clock frequency
CL = 3
fCK
CL = 2
Unit
Notes
max.
7.5
––
ns
9.5
––
ns
––
133
MHz
––
105
MHz
––
––
Clock high-level width
tCH
2.5
––
ns
––
Clock low-level width
tCL
2.5
––
ns
––
Address and command input setup time
tIS
1.5
––
ns
––
Address and command input hold time
tIH
0.5
––
ns
––
2.4.1
NO OPERATION (NOP)
#,+
#+%
(IG
H #3
2!3
#!3
7%
!!
"!
"
!
$O
NgT#A
R E
Figure 6
No Operation Command
The NO OPERATION (NOP) command is used to perform a NOP to a Mobile-RAM which is selected (CS = LOW).
This prevents unwanted commands from being registered during idle states. Operations already in progress are
not affected.
Data Sheet
15
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4.2
DESELECT
The DESELECT function (CS = HIGH) prevents new commands from being executed by the Mobile-RAM. The
Mobile-RAM is effectively deselected. Operations already in progress are not affected.
2.4.3
MODE REGISTER SET
#,+
#+%
(IG
H #3
2!3
#!3
7%
!!
#ODE
"!
"
!
#ODE
$O
NgT#A
R E
Figure 7
Mode Register Set Command
The Mode Register and Extended Mode Register are loaded via inputs A0 - A11 (see mode register descriptions
in Chapter 2.2). The MODE REGISTER SET command can only be issued when all banks are idle and no bursts
are in progress. A subsequent executable command cannot be issued until tMRD is met.
#,+
#OM
MA
ND
-23
./0
6ALID
T-2$ !DDRE
SS
#ODE
6ALID
$O
NgT#A
RE
#ODE
-OD
E2E
GIS TER%X TEN
DED-OD
E2E
GIS TERSE
LE
CTIO
N
"!
"!
ANDOPCO
DE!
!
Figure 8
Mode Register Definition
Table 9
Timing Parameters for Mode Register Set Command
Parameter
Symbol
- 7.5
min.
MODE REGISTER SET command period
Data Sheet
tMRD
16
2
Units
Notes
max.
—
tCK
—
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4.4
ACTIVE
#,+
#+%
(IG
H #3
2!3
#!3
7%
!!
2!
"!
"
!
"!
$O
NgT#A
R E
"!
"
ANK!
DD
RES S
2!2O
W!
DDR ESS Figure 9
ACTIVE Command
Before any READ or WRITE commands can be issued to a bank within the Mobile-RAM, a row in that bank must
be “opened” (activated). This is accomplished via the ACTIVE command and addresses A0 - A11, BA0 and BA1
(see Figure 9), which decode and select both the bank and the row to be activated. After opening a row (issuing
an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification.
A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active
row has been “closed” (precharged).
The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A
subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands
to different banks is defined by tRRD.
#,+
#OM
MA
ND
!#4
!!
2/7
2/7
#/,
"!"!
"!X
"!Y
"!Y
./0
!#4
./0
T22$ ./0
2$7
2
./0
T2#$ $O
NgT#A
R E
Figure 10
Data Sheet
Bank Activate Timings
17
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
Table 10
Timing Parameters for ACTIVE Command
Parameter
Symbol
- 7.5
min.
Units
Notes
max.
ACTIVE to ACTIVE command period
tRC
67
—
ns
ACTIVE to READ or WRITE delay
tRCD
19
—
ns
ACTIVE bank A to ACTIVE bank B delay
tRRD
15
—
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
2.4.5
READ
#,+
#+%
(IG
H #3
2!3
#!3
7%
! !
#!
%NAB
LE!
0
!
"!
"
!
Figure 11
$ISA
BLE!0
"!"
AN
K!D
DRES S #!
#
O
LUMN
!
DD
RES S
!0!
UTO0
RE
CH
AR GE
"!
$O
NgT#
AR E
!0
READ Command
Subsequent to programming the mode register with CAS latency and burst length, READ bursts are initiated with
a READ command, as shown in Figure 11. Basic timings for the DQs are shown in Figure 12; they apply to all
read operations and therefore are omitted from all subsequent timing diagrams.
The starting column and bank addresses are provided with the READ command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row being accessed starts precharge
at the completion of the burst, provided tRAS has been satisfied. For the generic READ commands used in the
following illustrations, Auto Precharge is disabled.
Data Sheet
18
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
T$1:
$1 T!#
T!#
T,:
T/(
$1
$/N
T(:
T/(
$/N
$O
NgT#A
RE
Figure 12
Data Sheet
Basic READ Timing Parameters for DQs
19
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
Table 11
Timing Parameters for READ
Parameter
Symbol
- 7.5
Units
min.
Access time from CLK
Notes
max.
CL = 3
tAC
—
5.4
ns
CL = 2
tAC
—
6.0
ns
tLZ
1.0
—
ns
DQ high-impedance time from CLK
tHZ
3.0
7.0
ns
Data out hold time
tOH
2.5
–
ns
—
DQM to DQ High-Z delay (READ Commands)
tDQZ
—
2
tCK
—
ACTIVE to ACTIVE command period
tRC
67
—
ns
1)
ACTIVE to READ or WRITE delay
tRCD
19
—
ns
ACTIVE to PRECHARGE command period
tRAS
45
100k
ns
PRECHARGE command period
tRP
19
—
ns
DQ low-impedance time from CLK
—
—
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 13 and Figure 14 show single READ bursts for each supported CAS latency setting.
#,+
T2#$ T2!3 #OMM
AND
!#4
./0
2%!$
!DD
RESS "A!
2OWX "A!
#OLN
!!0 2OWX $IS!
0
T20
T2#
./0
./0
./0
02%
./0
!#4
"A!
2OWB
0RE
!LL
!0
2OWB
0RE"
ANK!
#,
$1
$/N
$/N
$/N
"A!#O
LNBANK !C OLU
MNN
!0!UTO0R EC HA
RG
E
$/N$A
TA/UTFROM
COLU
M
NN
$IS !0
$ISA
BLE
!U
TO0REC HAR GE
"URST,ENG
THIN
THECAS ESHOW
N
TELE
ME
NTS OF$A
TA/
UTAREP
ROVID
ED
IN
THEPROGR AMME
DORDER FOLLO
WING
$/
N
SU
BSE
QUEN
Figure 13
Data Sheet
$/N
$O
NgT#A
RE
Single READ Burst (CAS Latency = 2)
20
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
T2#$ T2!3 #OMM
AND
!#4
./0
./0
2%!
$
!DD
RESS "A!
2OW
X "A!
#OLN !!0 2OW
X $IS !
0
T20
T2#
./0
./0
./0
02%
./0
./0
!#4
"A!
2OW
B 0RE!LL
!0
2OW
B 0RE"
ANK!
#,
$1
$/N
$/N
$/N
$/N
$O
NgT#A
RE
"A!#O
LNBANK !C OLU
MNN
!0!UTO0R ECHA
RGE
$/N$A
TA/UTFROM
COLU
M
NN
$IS !0$IS ABLE
!UTO0REC HARGE
"URST,ENG
THIN
THECAS ESHOW
N
TELE
ME
NTS OF$A
TA/
UTAREP
ROVID
ED
IN
THEPROGR AMME
DORDER FOLLO
WING
$/
N
SU
BSE
QUEN
Figure 14
Single READ Burst (CAS Latency = 3)
Data from any READ burst may be concatenated with data from a subsequent READ command. In either case, a
continuous flow of data can be maintained. A READ command can be initiated on any clock cycle following a
previous READ command, and may be performed to the same or a different (active) bank. The first data element
from the new burst follows either the last element of a completed burst (Figure 15) or the last desired data element
of a longer burst which is being truncated (Figure 16). The new READ command should be issued x cycles after
the first READ command, where x equals the number of desired data elements.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
2%!$
./0
./0
./0
./0
"A!
#OLB
#,
$1
$/N
$/N
$/N
$/N
$/B
$/B
$/B
$/N
$/N
$/N
$/N
$/B
$/B
#,
$1
"A!#
OLNB"AN
K!#OLU
MNNB $/N
B$A
TA/UTFROMCOLU
MN
NB
"URST,ENGTHIN
TH
ECA
SESHO
WN
SUBSEQ
UENTELE
M
ENTSO
F$A
TA/U
TAREPROVID
E
DIN
THE
PROG
RAMM
EDORDE
RFOLLOW
IN
G$/
N B
Figure 15
Data Sheet
$O
NgT#A
RE
Consecutive READ Bursts
21
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
#OM
MA
ND
2%!$
2%!$
2%!$
2%!$
!DDRE
SS
"A!
#OLN
"A!
#OLA
"A!
#OLX "A!
#OLM
./0
./0
./0
./0
./0
#,
$1
$/N
$/A
$/X
$/M
$/M
$/M
$/M
$/N
$/A
$/X
$/M
$/M
$/M
#,
$1
$O
NgT#A
RE
"A!#O
LNETC "AN
K!#O
LU
MNNETC $/N
ETC $A
TA/U
TFRO
MCOLU
MNNE
TC
"URST,ENGTHIN
TH
ECASESHO
WN
BURS TSARE
TERM
IN
ATED
BYCON
SE
CUTIV E2%
!
$CO
M
MA
NDS
VID
EDIN
THEPR OGRA
MMED
ORDE
RFOLLO
W
IN
G$/
M
SUBSEQ
UENTELE
MENTSO
F$A
TA/U
TAR EPRO
Figure 16
Random READ Bursts
Non-consecutive READ bursts are shown in Figure 17.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
./0
2%!$
./0
./0
./0
"A!
#OLB
#,
$1
$/N
$/N
$/N
$/N
$/N
$/N
$/N
$/B
$/B
#,
$1
$/N
$/B
"A!#
OLNB"AN
K!#OLU
MNNB
$/N
B$A
TA/UTFROMCOLU
MN
NB
"URST,ENGTHIN
TH
ECA
SESHO
WN
SUBSEQ
UENTELE
MEN
TSO
F$A
TA/U
TAREPR OVID
ED
IN
THE
PROG
RAMMED
ORDE
RFOLLOW
IN
G$/
N B
Figure 17
Data Sheet
$O
NgT#A
RE
Non-Consecutive READ Bursts
22
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4.5.1
READ Burst Termination
Data from any READ burst may be truncated using the BURST TERMINATE command (see Page 34), provided
that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the
BURST TERMINATE command must be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. This is shown in Figure 18. The
BURST TERMINATE command may be used to terminate a full-page READ which does not self-terminate.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
"34
./0
./0
./0
./0
./0
#,
$1
$/N
$/N
$/N
$/N
$/N
#,
$1
$/N
"A!#
OLN"ANK !#O
LU
MNN
$/N
$A
TA/U
TFRO
MCOLU
MNN
"URST,ENGTHIN
TH
ECASESHO
WN
SUBSE
Q
UENTELE
MEN
TSO
F$A
TA/U
TAREPR OVID
ED
IN
THE
PROGRA
MMED
ORDE
RFOLLOW
IN
G$/
N 4HE
BURSTIS TER MIN
ATEDAFTERTHE
RDDATA
ELE
ME
NT
Figure 18
Terminating a READ Burst
2.4.5.2
Clock Suspend Mode for READ Cycles
$O
NgT#A
RE
Clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. As long as
CKE is registered LOW, the following internal clock pulse(s) will be ignored and data on DQ will remain driven, as
shown in Figure 19.
Data Sheet
23
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
#+%
INTER NAL
CLO
CK
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
T#3,
$1
./0
T#3,
$/N
./0
T#3,
$/N
$/N
$/N
$O
NgT#A
RE
"A!#O
LNETC "AN
K!#O
LU
MNNETC $/N
ETC $A
TA/U
TFRO
MCOLU
MNNE
TC
#,
IN
THECASESH
OWN
#LOCK SU
SPEND
LATENCYT#3,IS CLO
CK CYCLE
Figure 19
Clock Suspend Mode for READ Bursts
2.4.5.3
READ - DQM Operation
DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing
parameters as listed in Table 11 also apply to this DQM operation. The read burst in progress is not affected and
will continue as programmed.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
./0
./0
./0
./0
T$1:
$1 $1
$/N
$/N
$O
NgT#A
RE
"A!#O
LNBA
NK!
COLU
MN
N
$/N
$A
TA/U
TFRO
MCOLU
MNN
#,
IN
THECASESH
OWN
$1-READ
LA
TENCYT$1:IS CLO
CKCYCLE
S
Figure 20
READ Burst - DQM Operation
2.4.5.4
READ to WRITE
$/N
A READ burst may be followed by or truncated with a WRITE command. The WRITE command can be performed
to the same or a different (active) bank. Care must be taken to avoid bus contention on the DQs; therefore it is
recommended that the DQs are held in High-Z state for a minimum of 1 clock cycle. This can be achieved by either
delaying the WRITE command, or suppressing the data-out from the READ by pulling DQM HIGH two clock cycles
Data Sheet
24
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
prior to the WRITE command, as shown in Figure 21. With the registration of the WRITE command, DQM acts as
a write mask: when asserted HIGH, input data will be masked and no write will be performed.
#,+
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
./0
./0
./0
./0
72)4%
./0
./0
"A!
#OLB
$1 #,
$1
$/N
$/N
(IG
H:
$)B
$)B
$)B
$/N
(IG
H:
$)B
$)B
$)B
#,
$1
$O
NgT#A
RE
"A!#O
LNBB
ANK!COLU
MN
NB
$/N
$ATA
/UTFR OMC OLU
MNN $
)B$
ATA)NTOCOLU
MNB
$1-IS ASSER TED(
)'
(TOSET$1
STO(IG
H:
STA
TEFORC LO
CKCYC LE
PRIO
RTOTHE72)4%
COMM
AND
Figure 21
READ to WRITE Timing
2.4.5.5
READ to PRECHARGE
A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that
Auto Precharge was not activated. This is shown in Figure 22.
The PRECHARGE command should be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. Following the PRECHARGE
command, a subsequent ACTIVE command to the same bank cannot be issued until tRP is met. Please note that
part of the row precharge time is hidden during the access of the last data elements.
In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same READ burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.
Data Sheet
25
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
T20
#OM
MA
ND
2%!$
!DDRE
SS
"A!
#OLN
!
!0 $IS!0
./0
./0
./0
02%
./0
./0
!#4
"A!
2OWA
"A!
0RE!
LL
!0
0RE"
ANK !
#,
$1
$/N
$/N
$/N
$/N
$O
NgT#A
RE
"A!#
OLNBAN
K!
COLU
MNN "!
!M
2O
WBAN
K!ROWX
$/N
$A
TA/U
TFRO
MCOLU
MNN
"URST,ENGTHIN
TH
ECASESHO
WN
#!3LA
TENCY IN
THECAS ESHOW
N
SUBSEQ
UENTELE
MEN
TSO
F$A
TA/U
TAREPR OVID
ED
IN
THE
PROGRA
MMED
ORDE
RFOLLOW
IN
G$/
N
Figure 22
READ to PRECHARGE Timing
2.4.6
WRITE
#,+
#+%
(IG
H #3
2!3
#!3
7%
! !
#!
%NAB
LE!
0
!
!0
$ISA
BLE!0
"!
"
!
Figure 23
"!
"!"
AN
K!
DD
RES S
#!
#O
LUM
N
!
DD
RESS !0!
UTO0
RE
CHA
RGE
$O
NgT#
AR E
WRITE Command
WRITE bursts are initiated with a WRITE command, as shown in Figure 23. Basic timings for the DQs are shown
in Figure 24; they apply to all write operations.
The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the
Data Sheet
26
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
completion of the write burst. For the generic WRITE commands used in the following illustrations, Auto Precharge
is disabled.
#,+
T)(
T)3
$1 T)(
T)3
$1
$)N
$)N
$O
NgT#A
RE
Figure 24
Basic WRITE Timing Parameters for DQs
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and
subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst,
assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data
is ignored.
Figure 25 and Figure 26 show a single WRITE burst for each supported CAS latency setting.
Data Sheet
27
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
Table 12
Timing Parameters for WRITE
Parameter
Symbol
- 7.5
min.
Units
Notes
max.
DQ and DQM input setup time
tIS
1.5
—
ns
—
DQ input hold time
tIH
0.8
—
ns
—
0.5
—
ns
—
DQM input hold time
DQM write mask latency
tDQW
0
—
tCK
—
ACTIVE to ACTIVE command period
tRC
67
—
ns
1)
ACTIVE to READ or WRITE delay
tRCD
19
—
ns
ACTIVE to PRECHARGE command period
tRAS
45
100k
ns
WRITE recovery time
tWR
14
—
ns
PRECHARGE command period
tRP
19
—
ns
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
#,+
T2#$ #OM
MAND
!#4
./0
T72
T2!3 72)4%
"A!
!DDRES S 2
OWX
"A!
#OLN
!!0
2OWX $IS
!0
T20
T2#
./0
./0
./0
./0
02%
./0
!#4
"A!
2OWB
0RE!
LL
!0
2OWB
0RE
"A
NK!
$1
$)N
$)N
$)N
$)N
"A!#O
LNBANK !C OLU
MNN
$)N$
ATA)NTOC OLU
MNN
"URST,ENG
THIN
THECAS ESHOW
N
SU
BSEQUEN
TELEME
NTS OF$A
TA)NAREPROV ID
E
DIN
THE
PROG
RAMM
EDORDE
RFOLLOW
IN
G$)N
Figure 25
Data Sheet
$O
NgT#A
RE
WRITE Burst (CAS Latency = 2)
28
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
T2#$ #OM
MAND !#4
./0
T72
T2!3 ./0
"A!
!DDRES S 2
OWN
72)4
%
T20
T2#
./0
./0
./0
./0
02%
./0
./0
"A!
#OLN
!#4
"A!
2OWB
0RE!
LL
!!0
2OXW
$IS
!0
$1
$)N
2OW
B
!0
0RE"A
NK !
$)N
$)N
$)N
"A!#O
LNBANK !C OLU
MNN
$)N$
ATA)NTOC O
LU
MNN
"URST,ENG
THIN
THECAS ESHOW
N
SU
BSEQUEN
TELEME
NTS OF$A
TA)NAREPROV ID
E
DIN
THE
PROG
RAMM
EDORDE
RFOLLOW
IN
G$)N
Figure 26
$O
NgT#A
RE
WRITE Burst (CAS Latency = 3)
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either
case, a continuous flow of input data can be maintained. A WRITE command can be issued on any positive edge
of clock following the previous WRITE command. The first data element from the new burst is applied after either
the last element of a completed burst (Figure 27) or the last desired data element of a longer burst which is being
truncated (Figure 28). The new WRITE command should be issued x cycles after the first WRITE command,
where x equals the number of desired data elements.
#,+
#OM
MA
ND
!DDRE
SS
$1
./0
72)4%
./0
./0
./0
"A!
#OLN
$)N
72)4%
./0
./0
./0
$)B
$)B
$)B
"A!
#OLB
$)N
$)N
$)N
$)B
"A!#
OLNB"AN
K!#OLU
MNNB $)NB
$A
TA
)NTOCOLU
M
NNB WN
"URST,ENGTHIN
TH
ECA
SESHO
SUBSEQU
ENTELE
MENTSOF$A
TA)NAR EPR OVID
EDIN
THEPR OG
RAMME
DOR DERFO
LLO
WIN
G$)NB Figure 27
Data Sheet
$O
NgT#A
RE
Consecutive WRITE Bursts
29
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
#OM
MA
ND
./0
!DDRE
SS
$1
72)4%
72)4%
72)4%
72)4%
"A!
#OLN
"A!
#OLA
"A!
#OLX "A!
#OLM
$)N
$)A
$)X
$)M
./0
./0
./0
$)M
$)M
$)M
"A!#O
LNETC "AN
K!#O
LU
MNNETC $)NETC $A
TA)NTOCO
LU
MNNETC
WN
BU
RSTSAR ETERM
IN
ATED
BYCON
SECUTIVE
72)4%C OMM
AN
DS
"URST,ENGTHIN
TH
ECASESHO
EDIN
THEPR OGRA
MME
DOR DERFO
LLO
WIN
G$)M
SUBSEQUE
NTELE
MENTSOF$A
TA)NAR EPR OVID
Figure 28
./0
$O
NgT#A
RE
Random WRITE Bursts
Non-consecutive WRITE bursts are shown in Figure 29.
#,+
#OM
MA
ND
!DDRE
SS
$1
./0
72)4%
./0
./0
./0
"A!
#OLN
$)N
./0
72)4%
./0
./0
$)B
$)B
"A!
#OLB
$)N
$)N
$)N
$)B
"A!#
OLNB"AN
K!#OLU
MNNB $)NB
$A
TA
)NTOCOLU
M
NNB "URST,ENGTHIN
TH
ECA
SESHO
WN
SUBSEQU
ENTELE
MENTSOF$A
TA)NAR EPR OVID
EDIN
THEPR OG
RAMME
DOR DERFO
LLO
WIN
G$)NB Figure 29
Non-Consecutive WRITE Bursts
2.4.6.1
WRITE Burst Termination
$O
NgT#A
RE
Data from any WRITE burst may be truncated using the BURST TERMINATE command (see Page 34), provided
that Auto Precharge was not activated. The input data provided coincident with the BURST TERMINATE
command will be ignored. This is shown in Figure 30. The BURST TERMINATE command may be used to
terminate a full-page WRITE which does not self-terminate.
Data Sheet
30
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
#OM
MA
ND
./0
72)4%
./0
./0
$)N
$)N
"34
./0
./0
"A!
#OLN
!DDRE
SS
$1
$)N
$O
NgT#A
RE
"A!#
OLN"ANK !#O
LU
MNN
$)N$A
TA)NTOCO
LU
MN
N
"URST,ENGTHIN
TH
ECA
SE
SHO
WN
MENTSOF$A
TA)NAR EWR ITTENIN
THE
PRO
GRAMM
EDORD
ERFOLLO
WIN
G$
)N
SUBSEQUE
NTELE
RTHE
RDDATA
ELE
MEN
T
4HEBURSTIS TER MIN
ATEDAFTE
Figure 30
Terminating a WRITE Burst
2.4.6.2
Clock Suspend Mode for WRITE Cycles
Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long
as CKE is registered LOW, the following internal clock pulse(s) will be ignored and no data will be captured, as
shown in Figure 31.
#,+
#+%
INTER NAL
CLO
CK
#OM
MA
ND
!DDRE
SS
./0
72)4%
./0
$)N
T#3,
$)N
Data Sheet
T#3,
$)N
$O
NgT#A
RE
"A!#O
LNETC "AN
K!#O
LU
MNNETC $/N
ETC $A
TA/U
TFRO
MCOLU
MNNE
TC
#,
IN
THECASESH
OWN
#LOCK SU
SPEND
LATENCYT#3,IS CLO
CKCYCLE
Figure 31
./0
"A!
#OLN
T#3,
$1
./0
Clock Suspend Mode for WRITE Bursts
31
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4.6.3
WRITE - DQM Operation
DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be
performed. The generic timing parameters as listed in Table 12 also apply to this DQM operation. The write burst
in progress is not affected and will continue as programmed.
#,+
#OM
MA
ND
./0
72)4%
./0
./0
./0
$)N
$)N
./0
"A!
#OLN
!DDRE
SS $1 $1
$)N
$O
NgT#A
RE
"A!#
OLN"ANK !#O
LU
MNN
$)N$A
TA)NTOCOLU
MN
N
"URST,ENGTHIN
TH
ECASESHO
WN
SU
BSE
QUE
NTELE
MENTSOF$A
TA)NAR EPR OVID
EDIN
THEPR OGRAM
ME
DOR DERFO
LLO
WIN
G
BEIN
GMA
SKED
$)NWITHTH
EFIR STELEM
ENT$)N
$1-WR ITELATE
NCY IS CLO
CKCYCLE
S
Figure 32
WRITE Burst - DQM Operation
2.4.6.4
WRITE to READ
A WRITE burst may be followed by, or truncated with a READ command. The READ command can be performed
to the same or a different (active) bank. With the registration of the READ command, data inputs will be ignored
and no WRITE will be performed, as shown in Figure 33.
#,+
#OM
MA
ND
!DDRE
SS
72)4%
./0
./0
"A!
#OLN
2%!$
./0
./0
./0
./0
"A!
#OLB
#,
$1
$)N
$)N
(IG
H :
$)N
7RITEDATA
AREIGNO
RED
$1
$)N
$)N
$/B
$/B
$/B
$/B
$)B
#,
(IGH
:
$)N
"A!#O
LNBB
ANK!COLU
MN
NB
$O
NgT#A
RE
$)N$A
TA)NTOCOLUMN
N $/
B$ATA
/UTFRO
MCOLU
MN
B
TH
ECASESHO
WN
"URST,ENGTHIN
G
$)N$
/
B
SUBSEQU
ENTELE
MENTSOF$A
TA)N/
UTAREPR OVID
ED
INTHEPROGRA
MME
DORDER FOLLOWIN
$)N
IS IG
N
OREDDUE
TO2
%!
$COMM
AND
.O
$1
-MAS KING
REQUIR EDATTHIS POIN
T
Figure 33
Data Sheet
WRITE to READ Timing
32
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4.6.5
WRITE to PRECHARGE
A WRITE burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that
Auto Precharge was not activated. This is shown in Figure 34.
The PRECHARGE command should be issued tWR after the clock edge at which the last desired data element of
the WRITE burst was registered. Additionally, when truncating a WRITE burst, DQM must be pulled to mask input
data presented during tWR prior to the PRECHARGE command. Following the PRE-CHARGE command, a
subsequent ACTIVE command to the same bank cannot be issued until tRP is met.
In the case of a WRITE being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same WRITE burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.
#,+
T72
#OMM
AND
./0
72)4%
!DDR ESS
"A!
#OLN
!
!0 $IS!0
./0
./0
./0
T20
02%
"A!
./0
!#4
"A!
2OWA
0RE!
LL
!0
0RE"
ANK !
$1-
$1
$)N
$)N
$)N
"A!#O
LNBA
NK!
COLU
MN
N
!0!UTO
0R ECHA
RGE
$O
NgT#A
RE
$)N$A
TA)NTOCOLU
MN
N
$IS !0
$
IS ABLE!U
TO0R EC HA
RGE
"URST,ENGTHIN
TH
ECASESHO
WN
MENTSOF$A
TA)NAR EPR OVID
EDIN
THEPR OGRAM
ME
DOR DERFO
LLO
WIN
G$)N
SUBSEQUE
NTELE
$)N
IS MAS KEDD
UETO$1
-PULLE
D()'(
DURIN
GT72
DPR IO
RTO
02%
#
(
!
2
'%COMMA
ND
PERIO
Figure 34
Data Sheet
WRITE to PRECHARGE Timing
33
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4.7
BURST TERMINATE
#,+
#+%
(IG
H #3
2!3
#!3
7%
!!
"!
"
!
$O
NgT#A
R E
Figure 35
BURST TERMINATE Command
The BURST TERMINATE command is used to truncate READ or WRITE bursts (with Auto Precharge disabled).
The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be
truncated, as shown in Figure 18 and Figure 30, respectively.
The BURST TERMINATE command is not allowed for truncation of READ or WRITE bursts with Auto Precharge
enabled.
2.4.8
PRECHARGE
#,+
#+%
(IG
H #3
2!3
#!3
7%
! !
!
!LL"
ANK S !
/NE
"A
NK "!
"
!
"!
$O
NgT#A
R E
"!
"
ANK!
DD
RES S
IF!
,
O
THE
RW
ISE
$
O
NgT#
A
RE Figure 36
Data Sheet
PRECHARGE command
34
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t
Care”.
Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row
in that bank, or if the previously open row is already in the process of precharging.
2.4.8.1
AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but
without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction
with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or
WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto Precharge is
non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto
Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time, as described for each burst type.
Table 13
Timing Parameters for PRECHARGE
Parameter
Symbol
- 7.5
min.
Units
Notes
max.
ACTIVE to PRECHARGE command period
tRAS
45
100k
ns
WRITE recovery time
tWR
14
–
ns
PRECHARGE command period
tRP
19
–
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
2.4.8.2
CONCURRENT AUTO PRECHARGE
A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE
command issued to a different bank.
Figure 37 shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n
will begin when the READ to bank m is registered.
Figure 38 shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge)
to bank m. The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled
HIGH two clock cycles prior to the WRITE to prevent bus contention.
Figure 39 shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
to bank m. The precharge to bank n will begin tWR after the new command to bank m is registered. The last valid
data-in to bank n is one clock cycle prior to the READ to bank m.
Figure 40 shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto
Precharge) to bank m. The precharge to bank n will begin tWR after the WRITE to bank m is registered. The last
valid data-in to bank n is one clock cycle prior to the WRITE to bank m.
Data Sheet
35
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
#OM
MA
ND
./0
2$ !0
./0
"ANKN
#OLB
!DDRE
SS
2%!$
./0
./0
./0
./0
"ANKM
#OLX #,
$1
T20
BA
NKN
$/B
$/B
$/X
$/X $O
NgT#A
RE
2$!
02EA
DWITH!UTO0R ECHA
RGE 2%!
$
2EA
DWITHORWITHO
UT!UTO0R ECHA
RGE
#,
AND
"URS T,EN
GTHINTH
ECASE
SHOWN
2EADWITH!
UTO0R EC HAR GETOBAN
KNIS IN
TER RUP
TEDBYSUB
SEQ
UENT2E
ADTOB
ANKM
Figure 37
$/X READ with Auto Precharge Interrupted by READ
#,+
#OM
MA
ND
./0
2$ !0
./0
./0
"ANKN
#OLB
!DDRE
SS
72)4%
./0
./0
./0
"ANKM
#OLX $1 #,
$1
T20
BA
NKN
$/B
$)X $)X
$)X
$O
NgT#A
RE
2$ !0
2E
ADWITH!UTO0R ECHA
RGE 72)4%
7R ITE
WITHORWITH
OUT!UTO0
R ECHARG
E
#,
AND
"URS T,EN
GTHINTH
ECASE
SHOWN
2EADWITH!
UTO0R EC HAR GETOBAN
KNIS IN
TERRUP
TEDBYSUBSEQ
UENT7R ITETOBANK M
Figure 38
$)X READ with Auto Precharge Interrupted by WRITE
#,+
#OM
MA
ND
72 !0
!DDRE
SS
"ANKN
#OLB
./0
2%!$
./0
./0
$/B
./0
$/B
T20
BA
NKN
$/X
$/X $/X 72 !
07R ITEW
ITH!U
TO0REC HAR GE 2
%!
$2E
A
DWITHOR WITHOU
T!UTO0RE
CHAR GE
#,
AND
"URS T,EN
GTHINTH
ECASE
SHOWN
7RITE
WITH!U
TO0R ECH
ARGETOBANKNIS IN
TER RUPTED
BYSU
BSE
QUEN
T2E
AD
TOBANK M
Figure 39
Data Sheet
./0
"ANKM
#OLX T72
BA
NKN
#,
$1
./0
$/X $O
NgT#A
RE
WRITE with Auto Precharge Interrupted by READ
36
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
#,+
#OM
MA
ND
72 !0
!DDRE
SS
"ANKN
#OLB
./0
72)4%
./0
./0
$)B
./0
$)B
$)X $)X
T20
BA
NKN
$)X
$)X
72 !0
7R ITEWITH!U
TO0REC HARG
E 7
2)4%7R ITEW
ITHORWITHO
UT!U
TO0R EC HARG
E
SHO
WN
"URST,ENGTHIN
TH
ECASE
7RITE
WITH!U
TO0R ECH
ARGETOBANKNIS IN
TER RUPTED
BYSU
BSEQUEN
T7R ITETOBAN
KM
Figure 40
Data Sheet
./0
"ANKM
#OLX T72
BA
NKN
$1
./0
$O
NgT#A
RE
WRITE with Auto Precharge Interrupted by WRITE
37
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4.9
AUTO REFRESH and SELF REFRESH
The Mobile-RAM requires a refresh of all rows in a rolling interval. Each refresh is generated in one of two ways:
by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode.
2.4.9.1
AUTO REFRESH
#,+
#+%
(IG
H #3
2!3
#!3
7%
!!
"!
"
!
$O
NgT#A
R E
Figure 41
AUTO REFRESH Command
Auto Refresh is used during normal operation of the Mobile-RAM. The command is non persistent, so it must be
issued each time a refresh is required. A minimum row cycle time (tRC) is required between two AUTO REFRESH
commands. The same rule applies to any access command after the auto refresh operation. All banks must be
precharged prior to the AUTO REFRESH command.
The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The Mobile-RAM requires AUTO REFRESH cycles at an average periodic
interval of 7.8 µs (max.). Partial array mode has no influence on auto refresh mode.
#,+
T20
#OMM
AND
02%
./0
T2#
!2&
T2#
./0
./0
$1
Data Sheet
./0
!#4
2OWN
0RE!
LL
(IG
H :
$O
NgT#A
RE
"A!2O
WNBA
NK!ROWN
Figure 42
./0
"A!
2OWN
!DD
RESS !!0 !2&
Auto Refresh
38
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
2.4.9.2
SELF REFRESH
#,+
#+%
#3
2!3
#!3
7%
!!
"!
"
!
$O
NgT#A
R E
Figure 43
SELF REFRESH Entry Command
The SELF REFRESH command can be used to retain data in the Mobile-RAM, even if the rest of the system is
powered down. When in the self refresh mode, the Mobile-RAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH command except CKE is LOW. Input signals except
CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting SELF REFRESH requires a stable clock prior to CKE returning HIGH. Once CKE is
HIGH, NOP commands must be issued for tRC because time is required for a completion of any internal refresh in
progress.
If during normal operation burst auto refresh or user controlled refresh is used, add 4096 auto refresh cycles just
before self refresh entry and just after self refresh exit.
#,+
T20
T2#
T32% 8
T2#
#+%
#OMM
AND
02%
./0
!2&
./0
./0
./0
!2&
./0
"A!
2OWN
!DD
RESS !!0 $1
!#4
2OWN
0RE!LL
(IGH
:
$
ON
gT#A
RE
3ELF2E
FRE
SH
%NTRY #O
MMAN
D
Figure 44
Data Sheet
3ELF2E
FRES H
%XIT#O
MM
AND
%XITFROM
3ELF2E
FRESH
!NY#O
MM
AND
!UTO2E
FRESH
2ECOMM
ENDED Self Refresh Entry and Exit
39
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionCommands
Table 14
Timing Parameters for AUTO REFRESH and SELF REFRESH
Parameter
Symbol
- 7.5
min.
Units
Notes
max.
ACTIVE to ACTIVE command period
tRC
67
–
ns
PRECHARGE command period
tRP
19
–
ns
Refresh period (4096 rows)
tREF
–
64
ms
Self refresh exit time
tSREX
1
–
tCK
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
2.4.10
POWER DOWN
#,+
#+%
#3
2!3
#!3
7%
!!
"!
"
!
$O
NgT#A
R E
Figure 45
Power Down Entry Command
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs
when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input
and output buffers, excluding CLK and CKE. CKE LOW must be maintained during power-down.
Power-down duration is limited by the refresh requirements of the device (tREF).
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT
command). One clock delay is required for power down entry and exit.
Data Sheet
40
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionFunction Truth Tables
#,+
T20
#+%
#OMM
AND
02%
./0
./0
./0
!DD
RESS !!0 6ALID
6ALID
0RE!
LL
6ALID
(IG
H :
$1
0OW
ER $O
WN
%NTR Y
%XITFRO
M
0OWE
R$O
WN
!NY
#OMMAN
D
0RECHA
RGE0OWE
R$O
WN
MOD
ESH
OWN
ALLBAN
KSARE
ID
LE
AND
T20
MET
WHE
N0OW
E
R$O
WN
%
NTRY#O
MMA
NDISISS UED
Figure 46
Power Down Entry and Exit
2.4.10.1
DEEP POWER DOWN
$O
NgT#A
RE
The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current
consumption. Deep power down mode is entered using the BURST TERMINATE command (cf. Figure 18) except
that CKE is LOW. All internal voltage generators inside the device are stopped and all memory data is lost in this
mode. To enter the deep power down mode all banks must be precharged.
The deep power down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command
sequence as for power-up initialization, including the 200µs initial pause, has to be applied before any other
command may be issued (cf. Figure 3 and Figure 4).
2.5
Function Truth Tables
Table 15
Current State Bank n - Command to Bank n
Current State
Any
Idle
Row Active
Data Sheet
CS
RAS CAS WE Command / Action
Notes
H
X
X
X
DESELECT (NOP / continue previous operation)
1)2)3)4)5)6)
L
H
H
H
NO OPERATION (NOP / continue previous operation)
to
L
L
H
H
ACTIVE (select and activate row)
to
L
L
L
H
AUTO REFRESH
to 7)
L
L
L
L
MODE REGISTER SET
to
L
L
H
L
PRECHARGE
to , 8)
L
H
L
H
READ (select column and start READ burst)
to , 9)
L
H
L
L
WRITE (select column and start WRITE burst)
to ,
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
to , 10)
41
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionFunction Truth Tables
Table 15
Current State Bank n - Command to Bank n (cont’d)
Current State
Read
(AutoPrecharge
Disabled)
Write
(AutoPrecharge
Disabled)
CS
RAS CAS WE Command / Action
Notes
L
H
L
H
READ (select column and start new READ burst)
to ,
L
H
L
L
WRITE (select column and start new WRITE burst)
to ,
L
L
H
L
PRECHARGE (truncate READ burst, start precharge)
to ,
L
H
H
L
BURST TERMINATE
to 11)
L
H
L
H
READ (select column and start READ burst)
to ,
L
H
L
L
WRITE (select column and start WRITE burst)
to ,
L
L
H
L
PRECHARGE (truncate WRITE burst, start precharge)
to ,
L
H
H
L
BURST TERMINATE
to ,
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was self
refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions:
Idle:The bank has been precharged, and tRP has been met.
Row Active:A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read:A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Write:A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and according to Table 16.
Precharging:Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank
is in the “idle” state.
Row Activating:Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank
is in the “row active” state.
Read with AP
Enabled:Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write with AP
Enabled:Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied
on each positive clock edge during these states.
Refreshing:Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the
SDRAM is in the “all banks idle” state.
Accessing Mode
Register:Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once
tMRD is met, the SDRAM is in the “all banks idle” state.
Precharging All:Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all
banks are in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle and no bursts are in progress.
8) Same as NOP command in that state.
9) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and
READs or WRITEs with Auto Precharge disabled.
10) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
11) Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
Data Sheet
42
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionFunction Truth Tables
Table 16
Current State Bank n - Command to Bank m (different bank)
Current State
CS
RAS CAS WE Command / Action
Notes
H
X
X
X
DESELECT (NOP / continue previous operation)
1)2)3)4)5)6)
L
H
H
H
NO OPERATION (NOP / continue previous operation)
to
Idle
X
X
X
X
Any command otherwise allowed to bank n
to
Row
Activating,
Active, or
Precharging
L
L
H
H
ACTIVE (select and activate row)
to
L
H
L
H
READ (select column and start READ burst)
to 7)
L
H
L
L
WRITE (select column and start WRITE burst)
to
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
to
L
L
H
H
ACTIVE (select and activate row)
to
L
H
L
H
READ (select column and start READ burst)
to
L
H
L
L
WRITE (select column and start WRITE burst)
to 8)
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
to
L
L
H
H
ACTIVE (select and activate row)
to
L
H
L
H
READ (select column and start READ burst)
to
L
H
L
L
WRITE (select column and start WRITE burst)
to
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
to
L
L
H
H
ACTIVE (select and activate row)
to
L
H
L
H
READ (select column and start READ burst)
to , 9)
L
H
L
L
WRITE (select column and start WRITE burst)
to
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
to
L
L
H
H
ACTIVE (select and activate row)
to
L
H
L
H
READ (select column and start READ burst)
to ,
L
H
L
L
WRITE (select column and start WRITE burst)
to ,
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
to
Any
Read (AutoPrecharge
Disabled)
Write (AutoPrecharge
Disabled)
Read
(with AutoPrecharge)
Write
(with AutoPrecharge)
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was Self
Refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands
shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is
allowable). Exceptions are covered in the notes below.
3) Current state definitions:
Idle:The bank has been precharged, and tRP has been met.
Row Active:A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register
accesses are in progress.
Read:A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Write:A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been
terminated.
Read with AP
Enabled:Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write with AP
Enabled:Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
4) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
6) All states and sequences not shown are illegal or reserved.
Data Sheet
43
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Functional DescriptionFunction Truth Tables
7) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and
READs or WRITEs with Auto Precharge disabled.
8) Requires appropriate DQM masking.
9) Concurrent Auto Precharge: bank n will start precharging when its burst has been interrupted by a READ or WRITE
command to bank m.
Table 17
Truth Table - CKE
CKEn-1 CKEn
Current State
Command
Action
Notes
L
Power Down
X
Maintain Power Down
1)2)3)4)
Self Refresh
X
Maintain Self Refresh
to
Clock Suspend
X
Maintain Clock Suspend
to
Deep Power Down
X
Maintain Deep Power
Down
to
Power Down
DESELECT or NOP
Exit Power Down
to
Self Refresh
DESELECT or NOP
Exit Self Refresh
to 5)
Clock Suspend
X
Exit Clock Suspend
to
Deep Power Down
X
Exit Deep Power Down
to , 6)
All Banks Idle
DESELECT or NOP
Enter Precharge Power
Down
to
Bank(s) Active
DESELECT or NOP
Enter Active Power Down
to
All Banks Idle
AUTO REFRESH
Enter Self Refresh
to
Read / Write burst
(valid)
Enter Clock Suspend
to
L
H
H
1)
2)
3)
4)
5)
6)
L
H
L
H
to
see Table 15 and Table 16
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state immediately prior to clock edge n.
COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n.
All states and sequences not shown are illegal or reserved.
DESELECT or NOP commands should be issued on any clock edges occurring during tRC period.
Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.
Data Sheet
44
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical CharacteristicsOperating Conditions
3
Electrical Characteristics
3.1
Operating Conditions
Table 18
Absolute Maximum Ratings
Parameter
Symbol
Values
min.
Unit
max.
Power Supply Voltage
VDD
-0.3
2.7
V
Power Supply Voltage for Output Buffer
VDDQ
-0.3
2.7
V
Input Voltage
VIN
-0.3
VDDQ + 0.3
V
Output Voltage
VOUT
-0.3
vDDQ + 0.3
V
Commercial
TC
0
+70
°C
Extended
TC
-25
+85
°C
Storage Temperature
TSTG
-55
+150
°C
Power Dissipation
PD
–
0.7
W
Short Circuit Output Current
IOUT
–
50
mA
Operation Case Temperature
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
Table 19
Pin Capacitances1)2)
Parameter
Symbol
Values
min.
Unit
max.
Input capacitance: CLK
CI1
1.5
3.0
pF
Input capacitance: all other input pins
CI2
1.5
3.0
pF
Input/Output capacitance: DQ
CIO
3.0
5.0
pF
1) These values are not subject to production test but verified by device characterization.
2) Input capacitance is measured according to JEP147 with VDD, VDDQ applied and all other pins (except the pin under test)
floating. DQ’s should be in high impedance state. This may be achieved by pulling CKE to low level.
Data Sheet
45
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical CharacteristicsAC Characteristics
Table 20
Electrical Characteristics1)
Parameter
Symbol
Values
Unit
min.
Notes
max.
Power Supply Voltage
VDD
1.70
1.95
V
—
Power Supply Voltage for DQ Output Buffer
VDDQ
1.70
1.95
V
—
Input high voltage
VIH
0.8 × VDDQ
VDDQ + 0.3
V
2)
Input low voltage
VIL
-0.3
0.3
V
Output high voltage (IOH = -0.1 mA)
VOH
VDDQ - 0.2
—
V
—
Output low voltage (IOL = 0.1 mA)
VOL
–
0.2
V
—
Input leakage current
IIL
-1.0
1.0
µΑ
—
Output leakage current
IOL
-1.5
1.5
µA
—
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); all voltages referenced to VSS. VSS and VSSQ must be at same
potential.
2) VIH may overshoot to VDD + 0.8 V for pulse width < 4 ns; VIL may undershoot to -0.8 V for pulse width < 4 ns.
Pulse width measured at 50% with amplitude measured between peak voltage and DC reference level.
3.2
AC Characteristics
Table 21
AC Characteristics1)2)3)4)
Parameter
Symbol
- 7.5
min.
Clock cycle time
CL = 3
tCK
CL = 2
Clock frequency
CL = 3
fCK
CL = 2
Access time from CLK
CL = 3
tAC
CL = 2
Unit Notes
max.
7.5
—
ns
9.5
—
ns
—
133
MHz
—
105
MHz
—
5.4
ns
—
6.0
ns
—
—
5)6)
Clock high-level width
tCH
2.5
—
ns
—
Clock low-level width
tCL
2.5
—
ns
—
Address, data and command input setup time
tIS
1.5
—
ns
7)
Address and command input hold time
tIH
0.5
—
ns
0.8
—
ns
Data (DQ) input hold time
MODE REGISTER SET command period
tMRD
2
—
tCK
—
DQ low-impedance time from CLK
tLZ
1.0
—
ns
—
DQ high-impedance time from CLK
tHZ
3.0
7.0
ns
—
Data out hold time
tOH
2.5
—
ns
DQM to DQ High-Z delay (READ Commands)
tDQZ
—
2
tCK
—
DQM write mask latency
tDQW
0
—
tCK
—
ACTIVE to ACTIVE command period
tRC
67
—
ns
8)
ACTIVE to READ or WRITE delay
tRCD
19
—
ns
ACTIVE bank A to ACTIVE bank B delay
tRRD
15
—
ns
ACTIVE to PRECHARGE command period
tRAS
45
100k
ns
Data Sheet
46
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical CharacteristicsAC Characteristics
Table 21
AC Characteristics1)2)3)4) (cont’d)
Parameter
Symbol
- 7.5
min.
Unit Notes
max.
9)
WRITE recovery time
tWR
14
—
ns
PRECHARGE command period
tRP
19
—
ns
Refresh period (4096 rows)
tREF
—
64
ms
—
Self refresh exit time
tSREX
1
—
tCK
—
0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); VDD = VDDQ = 1.70V to 1.95V;
All parameters assumes proper device initialization.
AC timing tests measured at 0.9 V.
The transition time is measured between VIH and VIL; all AC characteristics assume tT = 1 ns.
Specified tAC and tOH parameters are measured with a 30 pF capacitive load only as shown in Figure 47.
If tT(CLK) > 1 ns, a value of (tT/2 - 0.5) ns has to be added to this parameter.
If tT > 1 ns, a value of [0.5 x (tT - 1)] ns has to be added to this parameter.
These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when fCK ≤ 72 MHz.
With fCK > 72 MHz two clock cycles for tWR are mandatory. Qimonda recommends to use two clock cycles for the write
recovery time in all applications.
1)
2)
3)
4)
5)
6)
7)
8)
)/
P&
Figure 47
Data Sheet
Test Load for DQ Pins
47
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical CharacteristicsOperating Currents
3.3
Operating Currents
Table 22
Maximum Operating Currents1)
Parameter & Test Conditions
Symbol
Values
Unit Notes
Operating current:
one bank: active / read / precharge, BL = 1, tRC = tRCmin
IDD1
60
mA
Precharge power-down standby current:
all banks idle, CS ≥ VIHmin, CKE ≤ VILmax,
inputs changing once every two clock cycles
IDD2P
0.6
mA
Precharge power-down standby current with clock stop:
all banks idle, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD2PS
0.5
mA
Precharge non power-down standby current:
all banks idle, CS ≥ VIHmin, CKE ≥ VIHmin,
inputs changing once every two clock cycles
IDD2N
13
mA
Precharge non power-down standby current with clock stop:
all banks idle, CS ≥ VIHmin, CKE ≥ VIHmin, all inputs stable
IDD2NS
1.0
mA
Active power-down standby current:
one bank active, CS ≥ VIHmin, CKE ≤ VILmax,
inputs changing once every two clock cycles
IDD3P
1.0
mA
Active power-down standby current with clock stop:
one bank active, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD3PS
0.75
mA
Active non power-down standby current:
one bank active, CS ≥ VIHmin, CKE ≥ VIHmin,
inputs changing once every two clock cycles
IDD3N
15
mA
Active non power-down standby current with clock stop:
one bank active, CS ≥ VIHmin, CKE ≥ VIHmin, all inputs stable
IDD3NS
1.5
mA
Operating burst read current:
all banks active; continuous burst read,
inputs changing once every two clock cycles
IDD4
45
mA
Auto-Refresh current:
tRC = tRCmin, “burst refresh”,
inputs changing once every two clock cycles
IDD5
90
mA
Self Refresh current:
self refresh mode, CS ≥ VIHmin, CKE ≤ VILmax, all inputs stable
IDD6
see Table 23
Deep Power Down current
IDD7
20
- 7.5
2)3)
—
—
—
—
—
µA
—
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); VDD = VDDQ = 1.70V to 1.95V;
Recommended Operating Conditions unless otherwise noted
2) These values are measured with tCK = 7.5 ns
3) All parameters are measured with no output loads.
Data Sheet
48
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Electrical CharacteristicsPull-up and Pull-down Characteristics
Self Refresh Currents1)2)
Table 23
Parameter & Test Conditions
Max.
Symbol
Temperature
Self Refresh Current:
Self refresh mode,
full array activation
(PASR = 000)
85 °C
IDD6
Values
typ.
Unit
max.
400
470
70 °C
285
—
45 °C
200
—
25 °C
180
—
Self Refresh Current:
Self refresh mode,
half array activation
(PASR = 001)
85 °C
340
400
70 °C
250
—
45 °C
185
—
25 °C
170
—
Self Refresh Current:
Self refresh mode,
quarter array activation
(PASR = 010)
85 °C
310
360
70 °C
240
—
45 °C
175
—
25 °C
165
—
µA
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25 °C ≤ TC ≤ 85 °C (ext.); VDD = VDDQ = 1.70V to 1.95V
2) The On-Chip Temperature Sensor (OCTS) adjusts the refresh rate in self refresh mode to the component’s actual
temperature with a much finer resolution than supported by the 4 distinct temperature levels as defined by JEDEC for
TCSR. At production test the sensor is calibrated, and IDD6 max. current is measured at 85°C. Typ. values are obtained
from device characterization.
3.4
Pull-up and Pull-down Characteristics
Table 24
Half Drive Strength and Full Drive Strength
Voltage
(V)
Half Drive Strength
Pull-Down Current
(mA)
Nominal
Low
Nominal
High
Full Drive Strength
Pull-Up Current (mA)
Nominal
Low
Nominal
High
Pull-Down Current
(mA)
Nominal
Low
Nominal
High
Pull-Up Current (mA)
Nominal
Low
Nominal
High
0.00
0.0
0.0
-19.7
-33.4
0.0
0.0
-39.3
-66.7
0.40
15.1
20.5
-18.8
-32.0
30.2
41.0
-37.6
-63.9
0.65
20.3
28.5
-18.2
-31.0
40.5
57.0
-36.4
-61.9
0.85
22.0
32.0
-17.6
-29.9
43.9
64.0
-35.1
-59.8
1.00
22.6
33.5
-16.7
-28.7
45.2
67.0
-33.3
-57.3
1.40
23.5
35.0
-9.4
-20.4
46.9
70.0
-18.8
-40.7
1.50
23.6
35.3
-6.6
-17.1
47.2
70.5
-13.2
-34.1
1.65
23.8
35.5
-1.8
-11.4
47.5
71.0
-3.5
-22.7
1.80
23.9
35.7
3.8
-4.8
47.7
71.4
7.5
-9.6
1.95
24.0
35.9
9.8
2.5
48.0
71.8
19.6
5.0
The above characteristics are specified under nominal process variation / condition
Temperature (Tj): Nominal = 50 °C, VDDQ: Nominal = 1.80 V
Data Sheet
49
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Package Outlines
4
Package Outlines
Figure 48 P-VFBGA-54-2 (Plastic Very Thin Fine Ball Grid Array Package)
You can find all of our packages, sorts of packing and others in our
Qimonda
Internet
Page
“Products”:
http://www.Qimonda.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
50
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Data Sheet
Standard Ballout 128-Mbit Mobile-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power-Up Sequence and Mode Register Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address / Command Inputs Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
No Operation Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bank Activate Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Basic READ Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Single READ Burst (CAS Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Single READ Burst (CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Random READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Non-Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock Suspend Mode for READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
READ Burst - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
READ to WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
READ to PRECHARGE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Basic WRITE Timing Parameters for DQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
WRITE Burst (CAS Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
WRITE Burst (CAS Latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Consecutive WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Random WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Non-Consecutive WRITE Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Clock Suspend Mode for WRITE Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
WRITE Burst - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WRITE to READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WRITE to PRECHARGE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
BURST TERMINATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PRECHARGE command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
READ with Auto Precharge Interrupted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
READ with Auto Precharge Interrupted by WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WRITE with Auto Precharge Interrupted by READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WRITE with Auto Precharge Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Auto Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SELF REFRESH Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Self Refresh Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power Down Entry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Test Load for DQ Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
P-VFBGA-54-2 (Plastic Very Thin Fine Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . . . . 50
51
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128-Mbit Mobile-RAM
List of Tables
Table 1
Table 2
Table 4
Table 3
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Data Sheet
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information for Green Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inputs Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timing Parameters for Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Timing Parameters for ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Timing Parameters for READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Timing Parameters for WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timing Parameters for PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Timing Parameters for AUTO REFRESH and SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Current State Bank n - Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Current State Bank n - Command to Bank m (different bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Truth Table - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Maximum Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Self Refresh Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Half Drive Strength and Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
52
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128-Mbit Mobile-RAM
Table of Contents
1
1.1
1.2
1.3
1.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
4
5
7
2
2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
2.2.1.5
2.2.1.6
2.2.1.7
2.2.1.8
2.3
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.5.3
2.4.5.4
2.4.5.5
2.4.6
2.4.6.1
2.4.6.2
2.4.6.3
2.4.6.4
2.4.6.5
2.4.7
2.4.8
2.4.8.1
2.4.8.2
2.4.9
2.4.9.1
2.4.9.2
2.4.10
2.4.10.1
2.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power On and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Partial Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature Sensor . . . . . . . . 12
Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MODE REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
READ Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock Suspend Mode for READ Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
READ - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
WRITE Burst Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock Suspend Mode for WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
WRITE - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CONCURRENT AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AUTO REFRESH and SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DEEP POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3
3.1
3.2
3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pull-up and Pull-down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
45
45
46
48
49
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Data Sheet
53
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Data Sheet
54
Rev. 1.71, 2007-01
05282004-NZNK-8T0D
Data Sheet,
Edition 2007-01
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Under no circumstances may the Qimonda product as referred to in this Data Sheet be used in
1. Any applications that are intended for military usage (including but not limited to weaponry), or
2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining
or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if
a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or
(ii) Cause the failure of such Critical Systems; or
b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or
(ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to
property, whether tangible or intangible).
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