FAST/TTL 3-Bit Schematic 3-Bit Programmable Delay Modules PLDM4 Series FAST/TTL Logic Vcc P1 P2 P3 16 11 10 9 Output Buffer 3-Bit Programmable Delay Line 7 Delay Steps -- 4 ns Inherent Delay Available in Surface Mount 4 5 7 8 IN OUT E GND Electrical Specifications at 25OC 3-Bit FAST Part Number Delay per Step (ns) PLDM4-0.5 PLDM4-0.7 PLDM4-0.8 PLDM4-1 PLDM4-1.2 PLDM4-1.25 PLDM4-1.3 PLDM4-1.5 PLDM4-1.8 PLDM4-2 PLDM4-2.5 PLDM4-2.6 PLDM4-3 0.5 ± .25 0.7 ± .30 0.8 ± .30 1.0 ± .4 1.2 ± .4 1.25 ± .5 1.3 ± .5 1.5 ± .5 1.8 ± .6 2.0 ± .7 2.5 ± .7 2.6 ± .7 3.0 ± .7 Error ref. to 000 (ns) ± .30 ± .40 ± .50 ± .50 ± .60 ± .70 ± .70 ± .70 ± .80 ± .80 ± .90 ± .90 ± 1.0 Initial Delay (ns) 000 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 4 ± 1.0 Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1) 000 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 001 0.5 0.7 0.8 1.0 1.2 1.25 1.3 1.5 1.8 2.0 2.5 2.6 3.0 010 1.0 1.4 1.6 2.0 2.4 2.50 2.6 3.0 3.6 4.0 5.0 5.2 6.0 011 1.5 2.1 2.4 3.0 3.6 3.75 3.9 4.5 5.4 6.0 7.5 7.8 9.0 100 2.0 2.8 3.2 4.0 4.8 5.00 5.2 6.0 7.2 8.0 10.0 10.4 12.0 101 2.5 3.5 4.0 5.0 6.0 6.25 6.5 7.5 9.0 10.0 12.5 13.0 15.0 110 3.0 4.2 4.8 6.0 7.2 7.50 7.8 9.0 10.8 12.0 15.0 15.6 18.0 111 3.5 4.9 5.6 7.0 8.4 8.75 9.1 10.5 12.6 14.0 17.5 18.2 21.0 CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays referenced to Initial Delay, Setting "000." For example, the setting "111" delay of PLDM4-10 is 70.0 ± 3.0ns ref. to "000," and 74.0 ± 4.0ns referenced to the input. _ ENABLE input (Pin 7) is active low. Output will be disabled ( low) when " E " is high. INPUT FAN-IN: Input, pin 4, is loaded by the internal passive network and 8 gate inputs (74F type). The source driving Pin 4 should be FAST/TTL (74S/74F) type or equivalent, and should not be used to drive any load other than the delay line input. Dimensions in Inches (mm) .260 .300 (6.60) (7.62) TYP. MAX. .120 (3.05) MIN. .020 (0.51) TYP. TYP. 16-Pin SMD Pkg. Unused leads are NOT removed. To Specify SMD Package, Add "G" Suffix to P/N Examples: PLDM4-1.25G, PLDM4-2G VCC Supply Voltage ................................... 5.00 ± 0.25 VDC ICC Supply Current .......................... 60 mA typ., 80 mA max Logic “1” Input *: VIH ..................... 2.00 V min., 5.50 V max. IIH ............................... 50 µA max. @ 2.70V Logic “0” Input *: VIL ....................................... 0.80 V max. IIL ............................................ -0.6 mA mA VOH Logic “1” Voltage Out ................................... 2.40 V min. VOL Logic “0” Voltage Out ................................ 0.50 V max. PWI Input Pulse Width ............................. 40% of Delay min. Operating Temperature Range ......................... -0O to +70OC Storage Temperature Range ...................... -65O to +150OC 1.02 (25.9) .400 (10.16) MAX. .010 (0.25) .285 (7.24) TYP. MAX. * Refer to "INPUT FAN-IN" note above. IIL/IIH specified for Programming pins 9, 10 & 11. UKRPEXV LQGXVWULHV LQF TYP. .010 (0.25) .300 (7.62) .050 .100 (1.27) (2.54) TYP. OPERATING SPECIFICATIONS www.rhombus-ind.com MAX. MAX. VCC Supply Voltage ............................................... 5.00VDC Input Pulse Voltage ................................................... 3.20V Input Pulse Rise Time ....................................... 3.0 ns max. Input Pulse Width / Period ........................... 1000 / 2000 ns 1. Measurements made at 25OC 2. Delay Times measured at 1.50V level of leading edge. 3. Rise Times measured from 0.75V to 2.40V. 4. 10pf probe and fixture load on output. 6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH .400 (10.16) .810 (20.57) TEST CONDITIONS -- FAST / TTL .020 (0.51) .040 (1.02) .100 (2.54) TYP. TYP. TYP. .015 (0.38) .025 (0.64) .510 (12.95) .480 (12.19) )RU RWKHU YDOXHV &XVWRP 'HVLJQV FRQWDFW IDFWRU\ [email protected] 24 TEL: (714) 898-0960 FAX: (714) 896-0971 PLDM4-G 2001-01