PECL3 Series 10K ECL Logic 3-Bit Programmable Delay Modules Electrical Specifications at 25OC Error ref. 3-Bit 10K ECL Delay per to 000 Part Number Step (ns) (ns) PECL3-0.5 0.5 ± .25 ± .30 PECL3-0.75 0.75 ± .3 ± .50 PECL3-1 1.0 ± .4 ± .50 PECL3-1.2 1.2 ± .4 ± .60 PECL3-1.25 1.25 ± .5 ± .70 PECL3-1.3 1.3 ± .5 ± .70 PECL3-1.5 1.5 ± .5 ± .70 PECL3-1.75 1.75 ± .6 ± .80 PECL3-2 2.0 ± .7 ± .80 PECL3-2.5 2.5 ± .7 ± .90 PECL3-3 3.0 ± .7 ± 1.0 PECL3-5 5.0 ± 1.0 ± 1.5 PECL3-10 10.0 ± 1.5 ± 3.0 Initial Delay (ns) 000 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 3 ± 0.5 Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1) 000 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 001 0.5 0.75 1.0 1.2 1.25 1.3 1.5 1.75 2.0 2.5 3.0 5.0 10.0 010 1.0 1.50 2.0 2.4 2.50 2.6 3.0 3.50 4.0 5.0 6.0 10.0 20.0 011 1.5 2.25 3.0 3.6 3.75 3.9 4.5 5.25 6.0 7.5 9.0 15.0 30.0 100 2.0 3.00 4.0 4.8 5.00 5.2 6.0 7.00 8.0 10.0 12.0 20.0 40.0 101 2.5 3.75 5.0 6.0 6.25 6.5 7.5 8.75 10.0 12.5 15.0 25.0 50.0 110 3.0 4.50 6.0 7.2 7.50 7.8 9.0 10.50 12.0 15.0 18.0 30.0 60.0 111 3.5 5.25 7.0 8.4 8.75 9.1 10.5 12.25 14.0 17.5 21.0 35.0 70.0 3PECLH Series 10KH ECL Logic 3-Bit Programmable Delay Modules Electrical Specifications at 25OC 3-Bit 10KH ECL Part Number Delay per Step (ns) 3PECLH-0.5 3PECLH0.75 3PECLH-1 3PECLH-1.2 3PECLH1.25 3PECLH-1.3 3PECLH-1.5 3PECLH1.75 3PECLH-2 3PECLH-2.5 3PECLH-3 3PECLH-5 3PECLH-10 0.5 ± .25 0.75 ± .3 1.0 ± .4 1.2 ± .4 1.25 ± .5 1.3 ± .5 1.5 ± .5 1.75 ± .6 2.0 ± .7 2.5 ± .7 3.0 ± .7 5.0 ± 1.0 10.0 ± 1.5 Error ref. to 000 (ns) ± .30 ± .50 ± .50 ± .60 ± .70 ± .70 ± .70 ± .80 ± .80 ± .90 ± 1.0 ± 1.5 ± 3.0 Initial Delay (ns) 000 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 1.5 ± 0.5 Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1) 000 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 001 0.5 0.75 1.0 1.2 1.25 1.3 1.5 1.75 2.0 2.5 3.0 5.0 10.0 010 1.0 1.50 2.0 2.4 2.50 2.6 3.0 3.50 4.0 5.0 6.0 10.0 20.0 CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays Referenced to Initial Delay, Setting "000." For example the setting "111" delay of PECL3-2 is 14.0 ± 0.8 ns ref. to "000," and 17.0 ± 1.3 ns referenced to the input. ENABLE input, Pin 2, is active low. Output will be disabled ( low) when " E " is high. 011 1.5 2.25 3.0 3.6 3.75 3.9 4.5 5.25 6.0 7.5 9.0 15.0 30.0 100 2.0 3.00 4.0 4.8 5.00 5.2 6.0 7.00 8.0 10.0 12.0 20.0 40.0 Dimensions in Inches (mm) .120 (3.05) MIN. Rhombus Industries Inc. 111 3.5 5.25 7.0 8.4 8.75 9.1 10.5 12.25 14.0 17.5 21.0 35.0 70.0 ECL 3-Bit 16-Pin Schematic OUT P2 P3 16 15 10 9 Output Buffer 3-Bit Programmable Delay Line 1 2 6 Vcc E IN 7 8 P1 Vee .400 (10.16) MAX. GENERAL: For Operating Specifications and Test Conditions, see Tables IV, V and VII on page 5 of this catalog. Delays specified for the Leading Edge. .260 .300 (6.60) (7.62) TYP. MAX. .050 .100 .020 (0.51) (1.27) (2.54) TYP. TYP. TYP. Specifications subject to change without notice. 110 3.0 4.50 6.0 7.2 7.50 7.8 9.0 10.50 12.0 15.0 18.0 30.0 60.0 Vcc INPUT LOADING: Input, Pin 6, internally connected to eight ECL gate inputs terminated by Thevenin equivalent of 100 Ohms to -2V. .810 (20.57) MAX. 101 2.5 3.75 5.0 6.0 6.25 6.5 7.5 8.75 10.0 12.5 15.0 25.0 50.0 Operating Temp. Range ....................................... -30OC to +85OC Temperature Coefficient ............................... < 300ppm/OC typical Minimum Input Pulse Width ............................ 35% of max. Delay Supply Current, IEE ................................. 75 mA typ., 85 mA max. .010 (0.25) TYP. .300 (7.62) For other values & Custom Designs, contact factory. 27 PECL3 4/98 15801 Chemical Lane, Huntington Beach, CA 92649-1595 Tel: (714) 898-0960 • Fax: (714) 896-0971