XILINX XC3S500E

<BL Blue>
Platform Flash In-System
Programmable Configuration
PROMS
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DS123 (v2.9) May 09, 2006
Product Specification
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Features
•
•
In-System Programmable PROMs for Configuration of
Xilinx FPGAs
♦
•
3.3V supply voltage
Low-Power Advanced CMOS NOR FLASH Process
♦
•
Serial FPGA configuration interface (up to 33 MHz)
Endurance of 20,000 Program/Erase Cycles
♦
•
Operation over Full Industrial Temperature Range
(–40°C to +85°C)
Available in small-footprint VO20 and VOG20
packages.
•
IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
•
JTAG Command Initiation of Standard FPGA
Configuration
•
Cascadable for Storing Longer or Multiple Bitstreams
•
Dedicated Boundary-Scan (JTAG) I/O Power Supply
(VCCJ)
•
I/O Pins Compatible with Voltage Levels Ranging From
1.5V to 3.3V
•
Design Support Using the Xilinx Alliance ISE and
Foundation ISE Series Software Packages
•
XCF01S/XCF02S/XCF04S
XCF08P/XCF16P/XCF32P
♦
1.8V supply voltage
♦
Serial or parallel FPGA configuration interface
(up to 33 MHz)
♦
Available in small-footprint VO48, VOG48, FS48,
and FSG48 packages
♦
Design revision technology enables storing and
accessing multiple design revisions for
configuration
♦
Built-in data decompressor compatible with Xilinx
advanced compression technology
Table 1: Platform Flash PROM Features
Packages
Program
In-system
via JTAG
Serial
Config.
1.8V – 3.3V 2.5V – 3.3V
VO20/VOG20
✓
✓
3.3V
1.8V – 3.3V 2.5V – 3.3V
VO20/VOG20
✓
✓
4 Mbit
3.3V
1.8V – 3.3V 2.5V – 3.3V
VO20/VOG20
✓
✓
XCF08P
8 Mbit
1.8V
1.5V – 3.3V 2.5V – 3.3V
VO48/VOG48
FS48/FSG48
✓
XCF16P
16 Mbit
1.8V
1.5V – 3.3V 2.5V – 3.3V
VO48/VOG48
FS48/FSG48
XCF32P
32 Mbit
1.8V
1.5V – 3.3V 2.5V – 3.3V
VO48/VOG48
FS48/FSG48
Device
Density
VCCINT
XCF01S
1 Mbit
3.3V
XCF02S
2 Mbit
XCF04S
VCCO Range
VCCJ Range
Parallel
Config.
Design
Revisioning
Compression
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Description
Xilinx introduces the Platform Flash series of in-system
programmable configuration PROMs. Available in 1 to 32
Megabit (Mbit) densities, these PROMs provide an
easy-to-use, cost-effective, and reprogrammable method
for storing large Xilinx FPGA configuration bitstreams. The
Platform Flash PROM series includes both the 3.3V
XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS
version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that
support Master Serial and Slave Serial FPGA configuration
modes (Figure 1, page 2). The XCFxxP version includes
32-Mbit, 16-Mbit, and 8-Mbit PROMs that support Master
Serial, Slave Serial, Master SelectMAP, and Slave
SelectMAP FPGA configuration modes (Figure 2, page 2).
A summary of the Platform Flash PROM family members
and supported features is shown in Table 1.
© 2003-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
CLK
CE
OE/RESET
TCK
TMS
TDI
Control
and
JTAG
Interface
Data
Memory
Data
Address
CEO
Serial
Interface
DATA (D0)
Serial Mode
TDO
CF
ds123_01_30603
Figure 1: XCFxxS Platform Flash PROM Block Diagram
FI
CLK
CE
EN_EXT_SEL
OE/RESET
BUSY
OSC
CLKOUT
Decompressor
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Serial
or
Parallel
Interface
Data
Address
Memory
Data
CEO
DATA (D0)
(Serial/Parallel Mode)
D[1:7]
(Parallel Mode)
CF
REV_SEL [1:0]
ds123_19_122105
Figure 2: XCFxxP Platform Flash PROM Block Diagram
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. With CF High, a
short access time after CE and OE are enabled, data is
available on the PROM DATA (D0) pin that is connected to
the FPGA DIN pin. New data is available a short access
time after each rising clock edge. The FPGA generates the
appropriate number of clock pulses to complete the
configuration.
the PROMs DATA (D0-D7) pins. New data is available a
short access time after each rising clock edge. The data is
clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator can be used in the Slave
Parallel /Slave SelecMAP mode.
When the FPGA is in Slave Serial mode, the PROM and the
FPGA are both clocked by an external clock source, or
optionally, for the XCFxxP PROM only, the PROM can be
used to drive the FPGA’s configuration clock.
The XCFxxP version of the Platform Flash PROM provides
additional advanced features. A built-in data decompressor
supports utilizing compressed PROM files, and design
revisioning allows multiple design revisions to be stored on
a single PROM or stored across several PROMs. For design
revisioning, external pins or internal control bits are used to
select the active design revision.
The XCFxxP version of the Platform Flash PROM also
supports Master SelectMAP and Slave SelectMAP (or
Slave Parallel) FPGA configuration modes. When the FPGA
is in Master SelectMAP mode, the FPGA generates a
configuration clock that drives the PROM. When the FPGA
is in Slave SelectMAP Mode, either an external oscillator
generates the configuration clock that drives the PROM and
the FPGA, or optionally, the XCFxxP PROM can be used to
drive the FPGA’s configuration clock. With BUSY Low and
CF High, after CE and OE are enabled, data is available on
Multiple Platform Flash PROM devices can be cascaded to
support the larger configuration files required when
targeting larger FPGA devices or targeting multiple FPGAs
daisy chained together. When utilizing the advanced
features for the XCFxxP Platform Flash PROM, such as
design revisioning, programming files which span cascaded
PROM devices can only be created for cascaded chains
containing only XCFxxP PROMs. If the advanced XCFxxP
features are not enabled, then the cascaded chain can
include both XCFxxP and XCFxxS PROMs.
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
The Platform Flash PROMs are compatible with all of the existing FPGA device families. A reference list of Xilinx FPGAs and
the respective compatible Platform Flash PROMs is given in Table 2. A list of Platform Flash PROMs and their capacities is
given in Table 3, page 4.
Table 2: Xilinx FPGAs and Compatible Platform Flash
PROMs
FPGA
Configuration
Bitstream
Table 2: Xilinx FPGAs and Compatible Platform Flash
PROMs (Continued)
FPGA
Platform Flash PROM (1)
Configuration
Bitstream
Platform Flash PROM (1)
Virtex-II (3)
Virtex-5 LX
XC5VLX30
8,374,016
XCF08P
XC2V40
XC5VLX50
12,556,672
XCF16P
XC2V80
360,096
XCF01S
635,296
XCF01S
1,697,184
XCF02S
XC5VLX85
21,845,632
XCF32P
XC2V250
XC5VLX110
29,124,608
XCF32P
XC2V500
2,761,888
XCF04S
XC5VLX220
53,139,456
XCF32P+XCF32P
XC2V1000
4,082,592
XCF04S
XC2V1500
5,659,296
XCF08P
XC2V2000
7,492,000
XCF08P
XCF08P
XC2V3000
10,494,368
XCF16P
15,659,936
XCF16P
XC5VLX330
79,704,832 XCF32P+XCF32P+XCF16P
Virtex-4 LX
XC4VLX15
4,765,568
XC4VLX25
7,819,904
XCF08P
XC2V4000
XC4VLX40
12,259,712
XCF16P
XC2V6000
21,849,504
XCF32P
XC4VLX60
17,717,632
XCF32P
XC2V8000
29,063,072
XCF32P
630,048
XCF01S
XC4VLX80
23,291,008
XCF32P
Virtex-E
XC4VLX100
30,711,680
XCF32P
XCV50E
XC4VLX160
40,347,008
XCF32P+XCF08P
XCV100E
863,840
XCF01S
XCF32P+XCF32P
XCV200E
1,442,016
XCF02S
XCV300E
1,875,648
XCF02S
XCF08P
XCV400E
2,693,440
XCF04S
3,430,400
XCF04S
XCF04S
XC4VLX200
51,367,808
Virtex-4 FX
XC4VFX12
4,765,568
XC4VFX20
7,242,624
XCF08P
XCV405E
XC4VFX40
14,936,192
XCF16P
XCV600E
3,961,632
XC4VFX60
21,002,880
XCF32P
XCV812E
6,519,648
XCF08P
6,587,520
XCF08P
XC4VFX100
33,065,408
XCF32P
XCV1000E
XC4VFX140
47,856,896
XCF32P+XCF16P
XCV1600E
8,308,992
XCF08P
XCV2000E
10,159,648
XCF16P
XCF16P
XCV2600E
12,922,336
XCF16P
16,283,712
XCF16P
Virtex-4 SX
XC4VSX25
9,147,648
XC4VSX35
13,700,288
XCF16P
XCV3200E
XC4VSX55
22,749,184
XCF32P
Virtex
Virtex-II Pro X
XCV50
559,200
XCF01S
XC2VPX20
8,214,560
XCF08P
XCV100
781,216
XCF01S
XC2VPX70
26,098,976
XCF32P
XCV150
1,040,096
XCF01S
Virtex-II Pro
XCV200
1,335,840
XCF02S
XC2VP2
1,305,376
XCF02S
XCV300
1,751,808
XCF02S
XC2VP4
3,006,496
XCF04S
XCV400
2,546,048
XCF04S
XC2VP7
4,485,408
XCF08P
XCV600
3,607,968
XCF04S
4,715,616
XCF08P
6,127,744
XCF08P
XC2VP20
8,214,560
XCF08P
XCV800
XC2VP30
11,589,920
XCF16P
XCV1000
XC2VP40
15,868,192
XCF16P
Spartan-3E
XC2VP50
19,021,344
XCF32P
XC3S100E
581,344
XCF01S
XC2VP70
26,098,976
XCF32P
XC3S250E
1,352,192
XCF02S
XC2VP100
34,292,768
XCF32P (2)
XC3S500E
2,267,136
XCF04S
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
Table 2: Xilinx FPGAs and Compatible Platform Flash
PROMs (Continued)
FPGA
Configuration
Bitstream
Platform Flash PROM (1)
XC3S1200E
3,832,320
XCF04S
XC3S1600E
5,957,760
XCF08P
3,223,488
XCF04S
XC3S1500L
5,214,784
XCF08P
XC3S5000L
13,271,936
XCF16P
Spartan-3
XC3S50
439,264
XCF01S
XC3S200
1,047,616
XCF01S
XC3S400
1,699,136
XCF02S
XC3S1000
3,223,488
XCF04S
XC3S1500
5,214,784
XCF08P
XC3S2000
7,673,024
XCF08P
XC3S4000
11,316,864
XCF16P
XC3S5000
13,271,936
XCF16P
630,048
XCF01S
Spartan-IIE
XC2S50E
XC2S100E
863,840
XCF01S
XC2S150E
1,134,496
XCF02S
XC2S200E
1,442,016
XCF02S
XC2S300E
1,875,648
XCF02S
XC2S400E
2,693,440
XCF04S
XC2S600E
3,961,632
XCF04S
XC2S15
197,696
XCF01S
XC2S30
336,768
XCF01S
In-System Programming
In-System Programmable PROMs can be programmed
individually, or two or more can be daisy-chained together
and programmed in-system via the standard 4-pin JTAG
protocol as shown in Figure 3. In-system programming
offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices. The
programming data sequence is delivered to the device
using either Xilinx iMPACT software and a Xilinx download
cable, a third-party JTAG development system, a
JTAG-compatible board tester, or a simple microprocessor
interface that emulates the JTAG instruction sequence. The
iMPACT software also outputs serial vector format (SVF)
files for use with any tools that accept SVF format, including
automatic test equipment. During in-system programming,
the CEO output is driven High. All other outputs are held in
a high-impedance state or held at clamp levels during
in-system programming. In-system programming is fully
supported across the recommended operating voltage and
temperature ranges.
Spartan-3L
XC3S1000L
Programming
Spartan-II
V CC
GND
XC2S50
559,200
XCF01S
XC2S100
781,216
XCF01S
XC2S150
1,040,096
XCF01S
XC2S200
1,335,840
XCF02S
(a)
2.
3.
OE/RESET
If design revisioning or other advanced feature support is
required, the XCFxxP can be used as an alternative to the
XCF01S, XCF02S, or XCF04S.
Assumes compression used.
The largest possible Virtex-II bitstream sizes are specified. Refer
to the Virtex-II User Guide for information on bitgen options
which affect bitstream size.
Table 3: Platform Flash PROM Capacity
Platform
Flash PROM
DS026_02_082703
Figure 3: JTAG In-System Programming Operation
(a) Solder Device to PCB
(b) Program Using Download Cable
Notes:
1.
(b)
Configuration
Bits
Platform
Flash PROM
Configuration
Bits
XCF01S
1,048,576 XCF08P
8,388,608
XCF02S
2,097,152 XCF16P
16,777,216
XCF04S
4,194,304 XCF32P
33,554,432
DS123 (v2.9) May 09, 2006
The 1/2/4 Mbit XCFxxS Platform Flash PROMs in-system
programming algorithm results in issuance of an internal
device reset that causes OE/RESET to pulse Low.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx MultiPRO Desktop Tool or a third-party device
programmer. This provides the added flexibility of using
pre-programmed devices with an in-system programmable
option for future enhancements and design changes.
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Platform Flash In-System Programmable Configuration PROMS
Reliability and Endurance
Xilinx in-system programmable products provide a
guaranteed endurance level of 20,000 in-system
program/erase cycles and a minimum data retention of 20
years. Each device meets all functional, performance, and
data retention specifications within this endurance limit.
operations. For the XCFxxS PROM, the read protect
security bit is set for the entire device, and resetting the read
protect security bit requires erasing the entire device. For
the XCFxxP PROM the read protect security bit can be set
for individual design revisions, and resetting the read
protect bit requires erasing the particular design revision.
Write Protection
Design Security
The Xilinx in-system programmable Platform Flash PROM
devices incorporate advanced data security features to fully
protect the FPGA programming data against unauthorized
reading via JTAG. The XCFxxP PROMs can also be
programmed to prevent inadvertent writing via JTAG.
Table 4 and Table 5 show the security settings available for
the XCFxxS PROM and XCFxxP PROM, respectively.
The XCFxxP PROM device also allows the user to write
protect (or lock) a particular design revision to prevent
inadvertent erase or program operations. Once set, the
write protect security bit for an individual design revision
must be reset (using the UNLOCK command followed by
ISC_ERASE command) before an erase or program
operation can be performed.
Table 4: XCFxxS Device Data Security Options
Read Protection
Read Protect
The read protect security bit can be set by the user to
prevent the internal programming pattern from being read or
copied via JTAG. Read protection does not prevent write
Read/Verify
Inhibited
Program
Inhibited
Erase
Inhibited
Reset (default)
✓
Set
Table 5: XCFxxP Design Revision Data Security Options
Read Protect
Reset (default)
Reset (default)
Read/Verify
Inhibited
Write Protect
Program Inhibited
Erase Inhibited
✓
✓
✓
✓
Reset (default)
Set
Set
Reset (default)
✓
Set
Set
✓
IEEE 1149.1 Boundary-Scan (JTAG)
Instruction Register
The Platform Flash PROM family is compatible with the IEEE
1149.1 boundary-scan standard and the IEEE 1532
in-system configuration standard. A Test Access Port (TAP)
and registers are provided to support all required boundary
scan instructions, as well as many of the optional
instructions specified by IEEE Std. 1149.1. In addition, the
JTAG interface is used to implement in-system programming
(ISP) to facilitate configuration, erasure, and verification
operations on the Platform Flash PROM device. Table 6,
page 6 lists the required and optional boundary-scan
instructions supported in the Platform Flash PROMs. Refer
to the IEEE Std. 1149.1 specification for a complete
description of boundary-scan architecture and the required
and optional instructions.
The Instruction Register (IR) for the Platform Flash PROM
is connected between TDI and TDO during an instruction
scan sequence. In preparation for an instruction scan
sequence, the instruction register is parallel loaded with a
fixed instruction capture pattern. This pattern is shifted out
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI.
Caution!
The XCFxxP JTAG TAP pause states are not fully compliant with
the JTAG 1149.1 specification. If a temporary pause of a JTAG shift operation is
required, then stop the JTAG TCK clock and maintain the JTAG TAP within the
JTAG Shift-IR or Shift-DR TAP state. Do not transition the XCFxxP JTAG TAP
through the JTAG Pause-IR or Pause-DR TAP state to temporarily pause a
JTAG shift operation.
DS123 (v2.9) May 09, 2006
XCFxxS Instruction Register (8 bits wide)
The Instruction Register (IR) for the XCFxxS PROM is eight
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in Table 7, page 6.
The instruction capture pattern shifted out of the XCFxxS
device includes IR[7:0]. IR[7:5] are reserved bits and are set
to a logic 0. The ISC Status field, IR[4], contains logic 1 if
the device is currently in In-System Configuration (ISC)
mode; otherwise, it contains logic 0. The Security field,
IR[3], contains logic 1 if the device has been programmed
with the security option turned on; otherwise, it contains
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Platform Flash In-System Programmable Configuration PROMS
Erase/Program (ER/PROG) Error field, IR[6:5], contains a
10 when an erase or program operation is a success;
otherwise a 01 when an erase or program operation fails.
The Erase/Program (ER/PROG) Status field, IR[4], contains
a logic 0 when the device is busy performing an erase or
programming operation; otherwise, it contains a logic 1. The
ISC Status field, IR[3], contains logic 1 if the device is
currently in In-System Configuration (ISC) mode; otherwise,
it contains logic 0. The DONE field, IR[2], contains logic 1 if
the sampled design revision has been successfully
programmed; otherwise, a logic 0 indicates incomplete
programming. The remaining bits IR[1:0] are set to 01 as
defined by IEEE Std. 1149.1.
logic 0. IR[2] is unused, and is set to '0'. The remaining bits
IR[1:0] are set to '01' as defined by IEEE Std. 1149.1.
XCFxxP Instruction Register (16 bits wide)
The Instruction Register (IR) for the XCFxxP PROM is sixteen
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in Table 8, page 6.
The instruction capture pattern shifted out of the XCFxxP
device includes IR[15:0]. IR[15:9] are reserved bits and are
set to a logic 0. The ISC Error field, IR[8:7], contains a 10
when an ISC operation is a success; otherwise a 01 when
an In-System Configuration (ISC) operation fails. The
Table 6: Platform Flash PROM Boundary Scan Instructions
XCFxxS IR[7:0]
(hex)
XCFxxP IR[15:0]
(hex)
BYPASS
FF
FFFF
Enables BYPASS
SAMPLE/PRELOAD
01
0001
Enables boundary-scan SAMPLE/PRELOAD operation
EXTEST
00
0000
Enables boundary-scan EXTEST operation
CLAMP
FA
00FA
Enables boundary-scan CLAMP operation
HIGHZ
FC
00FC
Places all outputs in high-impedance state
simultaneously
IDCODE
FE
00FE
Enables shifting out 32-bit IDCODE
USERCODE
FD
00FD
Enables shifting out 32-bit USERCODE
00EE
Initiates FPGA configuration by pulsing CF pin Low
once. (For the XCFxxP this command also resets the
selected design revision based on either the external
REV_SEL[1:0] pins or on the internal design revision
selection bits.) (1)
Boundary-Scan Command
Instruction Description
Required Instructions
Optional Instructions
Platform Flash PROM
Specific Instructions
CONFIG
EE
Notes:
1.
For more information see "Initiating FPGA Configuration," page 13.
Table 7: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
TDI →
IR[7:5]
IR[4]
IR[3]
IR[2]
IR[1:0]
Reserved
ISC Status
Security
0
01
→ TDO
Table 8: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
TDI →
IR[15:9]
IR[8:7]
IR[6:5]
IR[4]
IR[3]
IR[2]
IR[1:0]
Reserved
ISC Error
ER/PROG
Error
ER/PROG
Status
ISC Status
DONE
01
DS123 (v2.9) May 09, 2006
→ TDO
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Platform Flash In-System Programmable Configuration PROMS
Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST,
SAMPLE/PRELOAD, and CLAMP instructions. Each output
pin on the Platform Flash PROM has two register stages
which contribute to the boundary-scan register, while each
input pin has only one register stage. The bidirectional pins
have a total of three register stages which contribute to the
boundary-scan register. For each output pin, the register
stage nearest to TDI controls and observes the output state,
and the second stage closest to TDO controls and observes
the High-Z enable state of the output pin. For each input pin,
a single register stage controls and observes the input state
of the pin. The bidirectional pin combines the three bits, the
input stage bit is first, followed by the output stage bit and
finally the output enable stage bit. The output enable stage
bit is closest to TDO.
See the XCFxxS/XCFxxP Pin Names and Descriptions
Tables in the "Pinouts and Pin Descriptions," page 37
section for the boundary-scan bit order for all connected
device pins, or see the appropriate BSDL file for the
complete boundary-scan bit order description under the
"attribute BOUNDARY_REGISTER" section in the BSDL
file. The bit assigned to boundary-scan cell 0 is the LSB in
the boundary-scan register, and is the register bit closest to
TDO.
Identification Registers
IDCODE Register
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for
examination by using the IDCODE instruction. The IDCODE
is available to any other system component via JTAG.
Table 9 lists the IDCODE register values for the Platform
Flash PROMs.
Table 9: IDCODES Assigned to Platform Flash PROMs
Device
IDCODE (1) (hex)
XCF01S
<v>5044093
XCF02S
<v>5045093
XCF04S
<v>5046093
XCF08P
<v>5057093
XCF16P
<v>5058093
XCF32P
<v>5059093
The <v> in the IDCODE field represents the device’s revision
code (in hex) and may vary.
DS123 (v2.9) May 09, 2006
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the PROM family code
a = the specific Platform Flash PROM product ID
c = the Xilinx manufacturer's ID
The LSB of the IDCODE register is always read as logic 1
as defined by IEEE Std. 1149.1.
USERCODE Register
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply
information about the device's programmed contents. By
using the USERCODE instruction, a user-programmable
identification code can be shifted out for examination. This
code is loaded into the USERCODE register during
programming of the Platform Flash PROM. If the device is
blank or was not loaded during programming, the
USERCODE register contains FFFFFFFFh.
Customer Code Register
For the XCFxxP Platform Flash PROM, in addition to the
USERCODE, a unique 32-byte Customer Code can be
assigned to each design revision enabled for the PROM.
The Customer Code is set during programming, and is
typically used to supply information about the design
revision contents. A private JTAG instruction is required to
read the Customer Code. If the PROM is blank, or the
Customer Code for the selected design revision was not
loaded during programming, or if the particular design
revision is erased, the Customer Code will contain all ones.
Platform Flash PROM TAP
Characteristics
The Platform Flash PROM family performs both in-system
programming and IEEE 1149.1 boundary-scan (JTAG)
testing via a single 4-wire Test Access Port (TAP). This
simplifies system designs and allows standard Automatic
Test Equipment to perform both functions. The AC
characteristics of the Platform Flash PROM TAP are
described as follows.
TAP Timing
Notes:
1.
The IDCODE register has the following binary format:
Figure 4, page 8 shows the timing relationships of the TAP
signals. These TAP timing characteristics are identical for
both boundary-scan and ISP operations.
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Platform Flash In-System Programmable Configuration PROMS
TCKMIN
TCK
TMSS
TMSH
TMS
TDIS
TDIH
TDI
TDOV
TDO
DS026_04_020300
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 10 shows the timing parameters for the TAP waveforms shown in Figure 4.
Table 10: Test Access Port Timing Parameters
Symbol
Description
Min
Max
Units
TCKMIN
TCK minimum clock period when VCCJ = 2.5V or 3.3V
100
–
ns
TMSS
TMS setup time when VCCJ = 2.5V or 3.3V
10
–
ns
TMSH
TMS hold time when VCCJ = 2.5V or 3.3V
25
–
ns
TDIS
TDI setup time when VCCJ = 2.5V or 3.3V
10
–
ns
TDIH
TDI hold time when VCCJ = 2.5V or 3.3V
25
–
ns
TDOV
TDO valid delay when VCCJ = 2.5V or 3.3V
–
30
ns
Additional Features for the XCFxxP
Internal Oscillator
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
an optional internal oscillator which can be used to drive the
CLKOUT and DATA pins on FPGA configuration interface.
The internal oscillator can be enabled when programming
the PROM, and the oscillator can be set to either the default
frequency or to a slower frequency ("XCFxxP PROM as
Configuration Master with Internal Oscillator as Clock
Source," page 33).
CLKOUT
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include
the programmable option to enable the CLKOUT signal
which allows the PROM to provide a source synchronous
clock aligned to the data on the configuration interface. The
CLKOUT signal is derived from one of two clock sources: the
CLK input pin or the internal oscillator. The input clock source
is selected during the PROM programming sequence.
Output data is available on the rising edge of CLKOUT.
DS123 (v2.9) May 09, 2006
The CLKOUT signal is enabled during programming, and is
active when CE is Low and OE/RESET is High. On CE
rising edge transition, if OE/RESET is High and the PROM
terminal count has not been reached, then CLKOUT
remains active for an additional eights clock cycles before
being disabled. On a OE/RESET falling edge transition,
CLKOUT is immediately disabled. When disabled, the
CLKOUT pin is put into a high-impedance state and should
be pulled High externally to provide a known state.
When cascading Platform Flash PROMs with CLKOUT
enabled, after completing it's data transfer, the first PROM
disables CLKOUT and drives the CEO pin enabling the next
PROM in the PROM chain. The next PROM will begin
driving the CLKOUT signal once that PROM is enabled and
data is available for transfer.
During high-speed parallel configuration without
compression, the FPGA drives the BUSY signal on the
configuration interface. When BUSY is asserted High, the
PROMs internal address counter stops incrementing, and
the current data value is held on the data outputs. While
BUSY is High, the PROM will continue driving the CLKOUT
signal to the FPGA, clocking the FPGA’s configuration logic.
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Platform Flash In-System Programmable Configuration PROMS
When the FPGA deasserts BUSY, indicating that it is ready
to receive additional configuration data, the PROM will
begin driving new data onto the configuration interface.
Decompression
The 8/16/32 Mbit XCFxxP Platform Flash PROMs include a
built-in data decompressor compatible with Xilinx advanced
compression technology. Compressed Platform Flash
PROM files are created from the target FPGA bitstream(s)
using the iMPACT software. Only Slave Serial and Slave
SelectMAP (parallel) configuration modes are supported for
FPGA configuration when using a XCFxxP PROM
programmed with a compressed bitstream. Compression
rates will vary depending on several factors, including the
target device family and the target design contents.
The decompression option is enabled during the PROM
programming sequence. The PROM decompresses the
stored data before driving both clock and data onto the
FPGA's configuration interface. If Decompression is
enabled, then the Platform Flash clock output pin
(CLKOUT) must be used as the clock signal for the
configuration interface, driving the target FPGA's
configuration clock input pin (CCLK). Either the PROM's
CLK input pin or the internal oscillator must be selected as
the source for CLKOUT. Any target FPGA connected to the
PROM must operate as slave in the configuration chain,
with the configuration mode set to Slave Serial mode or
Slave SelectMap (parallel) mode.
When decompression is enabled, the CLKOUT signal
becomes a controlled clock output with a reduced maximum
frequency. When decompressed data is not ready, the
CLKOUT pin is put into a high-Z state and must be pulled
High externally to provide a known state.
The BUSY input is automatically disabled when
decompression is enabled.
Design Revisioning
Design Revisioning allows the user to create up to four
unique design revisions on a single PROM or stored across
multiple cascaded PROMs. Design Revisioning is supported
for the 8/16/32 Mbit XCFxxP Platform Flash PROMs in both
serial and parallel modes. Design Revisioning can be used
with compressed PROM files, and also when the CLKOUT
feature is enabled. The PROM programming files along with
the revision information files (.cfi) are created using the
iMPACT software. The .cfi file is required to enable design
revision programming in iMPACT.
A single design revision is composed of from 1 to n 8-Mbit
memory blocks. If a single design revision contains less
than 8 Mbits of data, then the remaining space is padded
with all ones. A larger design revision can span several
8-Mbit memory blocks, and any space remaining in the last
8-Mbit memory block is padded with all ones.
DS123 (v2.9) May 09, 2006
•
A single 32-Mbit PROM contains four 8-Mbit memory
blocks, and can therefore store up to four separate
design revisions: one 32-Mbit design revision, two
16-Mbit design revisions, three 8-Mbit design revisions,
four 8-Mbit design revisions, and so on.
•
Because of the 8-Mbit minimum size requirement for
each revision, a single 16-Mbit PROM can only store
up to two separate design revisions: one 16-Mbit
design revision, one 8-Mbit design revision, or two
8-Mbit design revisions.
•
A single 8-Mbit PROM can store only one 8-Mbit
design revision.
Larger design revisions can be split over several cascaded
PROMs. For example, two 32-Mbit PROMs can store up to
four separate design revisions: one 64-Mbit design revision,
two 32-Mbit design revisions, three 16-Mbit design revisions,
four 16-Mbit design revisions, and so on. When cascading
one 16-Mbit PROM and one 8-Mbit PROM, there are 24 Mbits
of available space, and therefore up to three separate design
revisions can be stored: one 24-Mbit design revision, two
8-Mbit design revisions, or three 8-Mbit design revisions.
See Figure 5, page 10 for a few basic examples of how
multiple revisions can be stored. The design revision
partitioning is handled automatically during file generation
in iMPACT.
During the PROM file creation, each design revision is
assigned a revision number:
Revision 0 = '00'
Revision 1 = '01'
Revision 2 = '10'
Revision 3 = '11'
After programming the Platform Flash PROM with a set of
design revisions, a particular design revision can be
selected using the external REV_SEL[1:0] pins or using the
internal programmable design revision control bits. The
EN_EXT_SEL pin determines if the external pins or internal
bits are used to select the design revision. When
EN_EXT_SEL is Low, design revision selection is controlled
by the external Revision Select pins, REV_SEL[1:0]. When
EN_EXT_SEL is High, design revision selection is
controlled by the internal programmable Revision Select
control bits. During power up, the design revision selection
inputs (pins or control bits) are sampled internally. After
power up, the design revision selection inputs are sampled
again when any of the following events occur:
•
On the rising edge of CE
•
On the falling edge of OE/RESET (when CE is Low)
•
On the rising edge of CF (when CE is Low)
•
When reconfiguration is initiated by using the JTAG
CONFIG instruction.
The data from the selected design revision is then
presented on the FPGA configuration interface.
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Platform Flash In-System Programmable Configuration PROMS
PROM 0
PROM 0
REV 0
(8 Mbits)
REV 0
(8 Mbits)
PROM 0
PROM 0
PROM 0
REV 0
(8 Mbits)
REV 0
(16 Mbits)
REV 1
(8 Mbits)
REV 1
(8 Mbits)
REV 0
(32 Mbits)
REV 1
(24 Mbits)
REV 2
(8 Mbits)
REV 2
(16 Mbits)
REV 1
(16 Mbits)
REV 3
(8 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
(a) Design Revision storage examples for a single XCF32P PROM
PROM 0
PROM 0
REV 0
(16 Mbits)
REV 0
(16 Mbits)
PROM 0
PROM 0
PROM 0
REV 0
(16 Mbits)
REV 0
(32 Mbits)
REV 1
(16 Mbits)
REV 1
(16 Mbits)
PROM 1
PROM 1
REV 0
(32 Mbits)
REV 1
(16 Mbits)
PROM 1
PROM 1
PROM 1
REV 1
(32 Mbits)
REV 0
(32 Mbits)
REV 2
(16 Mbits)
REV 2
(32 Mbits)
REV 1
(32 Mbits)
REV 3
(16 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
(b) Design Revision storage examples spanning two XCF32P PROMs
ds123_20_102103
Figure 5: Design Revision Storage Examples
PROM to FPGA Configuration Mode and Connections Summary
The FPGA's I/O, logical functions, and internal
interconnections are established by the configuration data
contained in the FPGA’s bitstream. The bitstream is loaded
into the FPGA either automatically upon power up, or on
command, depending on the state of the FPGA's mode
pins. Xilinx Platform Flash PROMs are designed to
download directly to the FPGA configuration interface.
FPGA configuration modes which are supported by the
XCFxxS Platform Flash PROMs include: Master Serial and
Slave Serial. FPGA configuration modes which are
supported by the XCFxxP Platform Flash PROMs include:
Master Serial, Slave Serial, Master SelectMAP, and Slave
SelectMAP. Below is a short summary of the supported
FPGA configuration modes. See the respective FPGA data
sheet for device configuration details, including which
configuration modes are supported by the targeted FPGA
device.
FPGA Master Serial Mode
In Master Serial mode, the FPGA automatically loads the
configuration bitstream in bit-serial form from external
memory synchronized by the configuration clock (CCLK)
generated by the FPGA. Upon power-up or reconfiguration,
the FPGA's mode select pins are used to select the Master
Serial configuration mode. Master Serial Mode provides a
simple configuration interface. Only a serial data line, a
clock line, and two control lines (INIT and DONE) are
required to configure an FPGA. Data from the PROM is
read out sequentially on a single data line (DIN), accessed
via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The serial
bitstream data must be set up at the FPGA’s DIN input pin a
short time before each rising edge of the FPGA's internally
generated CCLK signal.
Typically, a wide range of frequencies can be selected for
the FPGA’s internally generated CCLK which always starts
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
at a slow default frequency. The FPGA’s bitstream contains
configuration bits which can switch CCLK to a higher
frequency for the remainder of the Master Serial
configuration sequence. The desired CCLK frequency is
selected during bitstream generation.
Connecting the FPGA device to the configuration PROM for
Master Serial Configuration Mode (Figure 6, page 14):
•
The DATA output of the PROM(s) drive the DIN input of
the lead FPGA device.
•
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s)
•
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
•
The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
•
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
active supply current ("DC Characteristics Over
Operating Conditions," page 26).
•
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
FPGA Slave Serial Mode
In Slave Serial mode, the FPGA loads the configuration
bitstream in bit-serial form from external memory
synchronized by an externally supplied clock. Upon
power-up or reconfiguration, the FPGA's mode select pins
are used to select the Slave Serial configuration mode.
Slave Serial Mode provides a simple configuration interface.
Only a serial data line, a clock line, and two control lines
(INIT and DONE) are required to configure an FPGA. Data
from the PROM is read out sequentially on a single data line
(DIN), accessed via the PROM's internal address counter
which is incremented on every valid rising edge of CCLK.
The serial bitstream data must be set up at the FPGA’s DIN
input pin a short time before each rising edge of the
externally provided CCLK.
Connecting the FPGA device to the configuration PROM for
Slave Serial Configuration Mode (Figure 7, page 15):
•
The DATA output of the PROM(s) drive the DIN input of
the lead FPGA device.
•
The PROM CLKOUT (for XCFxxP only) or an external
clock source drives the FPGA's CCLK input.
DS123 (v2.9) May 09, 2006
•
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
•
The OE/RESET pins of all PROMs are connected to
the INIT_B (or INIT) pins of all FPGA devices. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration.
•
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
active supply current ("DC Characteristics Over
Operating Conditions," page 26).
•
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
Serial Daisy Chain
Multiple FPGAs can be daisy-chained for serial
configuration from a single source. After a particular FPGA
has been configured, the data for the next device is routed
internally to the FPGA’s DOUT pin. Typically the data on the
DOUT pin changes on the falling edge of CCLK, although
for some devices the DOUT pin changes on the rising edge
of CCLK. Consult the respective device data sheets for
detailed information on a particular FPGA device. For
clocking the daisy-chained configuration, either the first
FPGA in the chain can be set to Master Serial, generating
the CCLK, with the remaining devices set to Slave Serial
(Figure 8, page 16), or all the FPGA devices can be set to
Slave Serial and an externally generated clock can be used
to drive the FPGA's configuration interface (Figure 7,
page 15 or Figure 12, page 20).
FPGA Master SelectMAP (Parallel) Mode
(XCFxxP PROM Only)
In Master SelectMAP mode, byte-wide data is written into
the FPGA, typically with a BUSY flag controlling the flow of
data, synchronized by the configuration clock (CCLK)
generated by the FPGA. Upon power-up or reconfiguration,
the FPGA's mode select pins are used to select the Master
SelectMAP configuration mode. The configuration interface
typically requires a parallel data bus, a clock line, and two
control lines (INIT and DONE). In addition, the FPGA’s Chip
Select, Write, and BUSY pins must be correctly controlled to
enable SelectMAP configuration. The configuration data is
read from the PROM byte by byte on pins [D0..D7],
accessed via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The
bitstream data must be set up at the FPGA’s [D0..D7] input
pins a short time before each rising edge of the FPGA's
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Platform Flash In-System Programmable Configuration PROMS
internally generated CCLK signal. If BUSY is asserted
(High) by the FPGA, the configuration data must be held
until BUSY goes Low. An external data source or external
pull-down resistors must be used to enable the FPGA's
active Low Chip Select (CS or CS_B) and Write (WRITE or
RDWR_B) signals to enable the FPGA's SelectMAP
configuration process.
The Master SelectMAP configuration interface is clocked by
the FPGA’s internal oscillator. Typically, a wide range of
frequencies can be selected for the internally generated
CCLK which always starts at a slow default frequency. The
FPGA’s bitstream contains configuration bits which can
switch CCLK to a higher frequency for the remainder of the
Master SelectMAP configuration sequence. The desired
CCLK frequency is selected during bitstream generation.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained using the persist option.
Connecting the FPGA device to the configuration PROM for
Master SelectMAP (Parallel) Configuration Mode (Figure 9,
page 17):
•
The DATA outputs of the PROM(s) drive the [D0..D7]
input of the lead FPGA device.
•
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s)
•
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
•
The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
•
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
active supply current ("DC Characteristics Over
Operating Conditions," page 26).
•
For high-frequency parallel configuration, the BUSY
pins of all PROMs are connected to the FPGA's BUSY
output. This connection assures that the next data
transition for the PROM is delayed until the FPGA is
ready for the next configuration data byte.
•
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
DS123 (v2.9) May 09, 2006
FPGA Slave SelectMAP (Parallel) Mode
(XCFxxP PROM Only)
In Slave SelectMAP mode, byte-wide data is written into the
FPGA, typically with a BUSY flag controlling the flow of data,
synchronized by an externally supplied configuration clock
(CCLK). Upon power-up or reconfiguration, the FPGA's mode
select pins are used to select the Slave SelectMAP
configuration mode. The configuration interface typically
requires a parallel data bus, a clock line, and two control lines
(INIT and DONE). In addition, the FPGA’s Chip Select, Write,
and BUSY pins must be correctly controlled to enable
SelectMAP configuration. The configuration data is read from
the PROM byte by byte on pins [D0..D7], accessed via the
PROM's internal address counter which is incremented on
every valid rising edge of CCLK. The bitstream data must be
set up at the FPGA’s [D0..D7] input pins a short time before
each rising edge of the provided CCLK. If BUSY is asserted
(High) by the FPGA, the configuration data must be held until
BUSY goes Low. An external data source or external
pull-down resistors must be used to enable the FPGA's active
Low Chip Select (CS or CS_B) and Write (WRITE or
RDWR_B) signals to enable the FPGA's SelectMAP
configuration process.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained using the persist option.
Connecting the FPGA device to the configuration PROM for
Slave SelectMAP (Parallel) Configuration Mode (Figure 10,
page 18):
•
The DATA outputs of the PROM(s) drives the [D0..D7]
inputs of the lead FPGA device.
•
The PROM CLKOUT (for XCFxxP only) or an external
clock source drives the FPGA's CCLK input.
•
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
•
The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
•
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary ICC
active supply current ("DC Characteristics Over
Operating Conditions," page 26).
•
For high-frequency parallel configuration, the BUSY
pins of all PROMs are connected to the FPGA's BUSY
output. This connection assures that the next data
transition for the PROM is delayed until the FPGA is
ready for the next configuration data byte.
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•
Platform Flash In-System Programmable Configuration PROMS
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
FPGA SelectMAP (Parallel) Device Chaining
(XCFxxP PROM Only)
Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and be made to start up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, DONE, INIT, Data ([D0..D7]), Write (WRITE or
RDWR_B), and BUSY pins of all the devices in parallel. If all
devices are to be configured with the same bitstream,
readback is not being used, and the CCLK frequency
selected does not require the use of the BUSY signal, the
CS_B pins can be connected to a common line so all of the
devices are configured simultaneously (Figure 10,
page 18).
With additional control logic, the individual devices can be
loaded separately by asserting the CS_B pin of each device
in turn and then enabling the appropriate configuration data.
The PROM can also store the individual bitstreams for each
FPGA for SelectMAP configuration in separate design
revisions. When design revisioning is utilized, additional
control logic can be used to select the appropriate bitstream
by asserting the EN_EXT_SEL pin, and using the
REV_SEL[1:0] pins to select the required bitstream, while
asserting the CS_B pin for the FPGA the bitstream is
targeting (Figure 13, page 21).
For clocking the parallel configuration chain, either the first
FPGA in the chain can be set to Master SelectMAP,
generating the CCLK, with the remaining devices set to
Slave SelectMAP, or all the FPGA devices can be set to
Slave SelectMAP and an externally generated clock can be
used to drive the configuration interface. Again, the
respective device data sheets should be consulted for
detailed information on a particular FPGA device, including
which configuration modes are supported by the targeted
FPGA device.
Cascading Configuration PROMs
When configuring multiple FPGAs in a serial daisy chain,
configuring multiple FPGAs in a SelectMAP parallel chain,
or configuring a single FPGA requiring a larger
configuration bitstream, cascaded PROMs provide
additional memory (Figure 8, page 16, Figure 11, page 19,
Figure 12, page 20, and Figure 13, page 21). Multiple
Platform Flash PROMs can be concatenated by using the
CEO output to drive the CE input of the downstream device.
The clock signal and the data outputs of all Platform Flash
DS123 (v2.9) May 09, 2006
PROMs in the chain are interconnected. After the last data
from the first PROM is read, the first PROM asserts its CEO
output Low and drives its outputs to a high-impedance
state. The second PROM recognizes the Low level on its CE
input and immediately enables its outputs.
After configuration is complete, address counters of all
cascaded PROMs are reset if the PROM OE/RESET pin
goes Low or CE goes High.
When utilizing the advanced features for the XCFxxP
Platform Flash PROM, including the clock output (CLKOUT)
option, decompression option, or design revisioning,
programming files which span cascaded PROM devices
can only be created for cascaded chains containing only
XCFxxP PROMs. If the advanced features are not used,
then cascaded PROM chains can contain both XCFxxP and
XCFxxS PROMs.
Initiating FPGA Configuration
The options for initiating FPGA configuration via the
Platform Flash PROM include:
•
Automatic configuration on power up
•
Applying an external PROG_B (or PROGRAM) pulse
•
Applying the JTAG CONFIG instruction
Following the FPGA’s power-on sequence or the assertion
of the PROG_B (or PROGRAM) pin the FPGA’s
configuration memory is cleared, the configuration mode is
selected, and the FPGA is ready to accept a new
configuration bitstream. The FPGA’s PROG_B pin can be
controlled by an external source, or alternatively, the
Platform Flash PROMs incorporate a CF pin that can be
tied to the FPGA’s PROG_B pin. Executing the CONFIG
instruction through JTAG pulses the CF output Low once for
300-500 ns, resetting the FPGA and initiating configuration.
The iMPACT software can issue the JTAG CONFIG
command to initiate FPGA configuration by setting the
"Load FPGA" option.
When using the XCFxxP Platform Flash PROM with design
revisioning enabled, the CF pin should always be connected
to the PROG_B (or PROGRAM) pin on the FPGA to ensure
that the current design revision selection is sampled when
the FPGA is reset. The XCFxxP PROM samples the current
design revision selection from the external REV_SEL pins
or the internal programmable Revision Select bits on the
rising edge of CF. When the JTAG CONFIG command is
executed, the XCFxxP will sample the new design revision
selection before initiating the FPGA configuration
sequence. When using the XCFxxP Platform Flash PROM
without design revisioning, if the CF pin is not connected to
the FPGA PROG_B (or PROGRAM) pin, then the XCFxxP
CF pin must be tied High.
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Platform Flash In-System Programmable Configuration PROMS
Configuration PROM to FPGA Device Interface Connection Diagrams
(2)
VCCJ VCCO VCCINT
VCCINT
D0
4.7 kΩ
4.7 kΩ
VCCO
(1)
DIN
MODE PINS
(1)
VCCO(2)
(2)
DIN
VCCJ
CCLK
Xilinx FPGA
Master Serial
Platform Flash
PROM
DONE
INIT_B
PROG_B
CLK
CCLK
CE
DONE
DOUT
CEO
OE/RESET
(3)
INIT_B
DIN
CCLK
PROG_B
TDI
TDI
TMS
TMS
INIT_B
TCK
TCK
PROG_B
CF
DONE
...OPTIONAL
Slave FPGAs
with identical
configurations
...OPTIONAL
Daisy-chained
Slave FPGAs
with different
configurations
TDO
TDO
GND
TDI
TMS
TCK
TDO
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. For the
XCFxxP, if CF is not connected to PROGB, then it must be tied to VCCO via a 4.7 kΩ pull-up resistor.
ds123_11_122105
Figure 6: Configuring in Master Serial Mode
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
(2)
VCCO
VCCJ VCCO VCCINT
VCCINT
D0
4.7 kΩ
4.7 kΩ
External (3)
Oscillator
(1)
DIN
MODE PINS
(1)
(2)
VCCO
(2)
VCCJ
DIN
CCLK
Xilinx FPGA
Slave Serial
Platform Flash
PROM
DONE
INIT_B
PROG_B
(3)
CCLK
CE
DONE
CLK
DOUT
CEO
OE/RESET
(4)
INIT_B
DIN
CCLK
PROG_B
TDI
TDI
TMS
TMS
INIT_B
TCK
TCK
PROG_B
CF
DONE
...OPTIONAL
Slave FPGAs
with identical
configurations
...OPTIONAL
Daisy-chained
Slave FPGAs
with different
configurations
TDO
TDO
GND
TDI
TMS
TCK
TDO
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or
optionally—for the XCFxxP Platform Flash PROM only—the CLKOUT signal can be used to drive the
FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used, then CLKOUT must
be tied to a 4.7KΩ resistor pulled up to VCCO.
4 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. For the
XCFxxP, if CF is not connected to PROGB, then it must be tied to VCCO via a 4.7 kΩ pull-up resistor.
ds123_12_122105
Figure 7: Configuring in Slave Serial Mode
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
VCCINT
D0
VCCINT
D0
Cascaded
PROM
(PROM 1)
First
PROM
(PROM 0)
TCK
TCK
DIN
VCCJ
Platform Flash
PROM
TMS
MODE PINS(1)
MODE PINS
DOUT
Platform Flash
PROM
TMS
(1)
DIN
(2)
(2)
VCCJ
TDI
(1)
VCCO(2)
VCCO(2)
TDI
4.7 kΩ
VCCO(2)
VCCJ VCCO VCCINT
4.7 kΩ
VCCJ VCCO VCCINT
CLK
CE
CLK
CCLK
CCLK
CE
DONE
DONE
INIT_B
INIT_B
PROG_B
PROG_B
CEO
CEO
OE/RESET
OE/RESET
CF
(3)
TDO
Xilinx FPGA
Slave Serial
Xilinx FPGA
Master Serial
CF
(3)
TDI
TMS
TDO
TCK
GND
TDO
GND
TDI
TDO
TDI
TMS
TMS
TCK
TCK
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 For the XCFxxS the CF pin is an output pin. For the XCFxxP the CF pin is a bidirectional pin. For the
XCFxxP, if CF is not connected to PROGB, then it must be tied to VCCO via a 4.7 kΩ pull-up resistor.
TDO
GND
ds123_13_122105
Figure 8: Configuring Multiple Devices in Master/Slave Serial Mode
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
VCCJ VCCO VCCINT
VCCINT
D[0:7]
4.7 kΩ
4.7 kΩ
VCCO(2)
(1)
D[0:7]
MODE PINS
VCCO(2)
RDWR_B
(2)
CS_B
VCCJ
XCFxxP
Platform Flash
PROM
Xilinx FPGA
Master SelectMAP
CLK
CCLK
CE
DONE
TDI
TDI
TMS
TMS
TCK
I/O
(3)
1KΩ
1KΩ
D[0:7]
CEO
OE/RESET
I/O(3)
(1)
CCLK
INIT_B
CF
(5)
PROG_B
BUSY
(4)
BUSY(4)
DONE
INIT_B
PROG_B
TCK
...OPTIONAL
Slave FPGAs
with identical
configurations
(4)
BUSY
TDO
TDO
GND
TDI
TMS
TCK
TDO
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for highfrequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be
tied to VCCO via a 4.7 kΩ pull-up resistor.
ds123_14_122105
Figure 9: Configuring in Master SelectMAP Mode
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
(2)
VCCO
VCCJ VCCO VCCINT
VCCINT
D[0:7]
4.7 kΩ
4.7 kΩ
External (5)
Oscillator
(1)
D[0:7]
MODE PINS
(1)
(2)
RDWR_B
(2)
CS_B
VCCO
VCCJ
XCFxxP
Platform Flash
PROM
Xilinx FPGA
Slave SelectMAP
(5)
CCLK
CE
DONE
CLK
TDI
TDI
TMS
TMS
TCK
TCK
I/O
(3)
1KΩ
D[0:7]
CCLK
INIT_B
(6)
PROG_B
(4)
BUSY(4)
CF
BUSY
(3)
1KΩ
CEO
OE/RESET
I/O
DONE
INIT_B
PROG_B
...OPTIONAL
Slave FPGAs
with identical
configurations
(4)
BUSY
TDO
TDO
GND
TDI
TMS
TCK
TDO
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down externally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for highfrequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or, optionally, the
CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal
is used, then CLKOUT must be tied to a 4.7 KΩ resistor pulled up to VCCO.
6 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be
tied to VCCO via a 4.7 kΩ pull-up resistor.
ds123_15_122105
Figure 10: Configuring in Slave SelectMAP Mode
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
VCCINT
VCCJ
D[0:7]
VCCINT
(2)
VCCO
(2)
VCCJ
VCCO
(1)
D[0:7]
D[0:7]
MODE PINS
(2)
RDWR_B
I/O
CS_B
Xilinx FPGA
Slave SelectMAP
CLK
CCLK
CCLK
CE
DONE
DONE
INIT_B
INIT_B
TDI
CF
(5)
CF
(5)
PROG_B
PROG_B
TMS
TMS
BUSY(4)
BUSY
(4)
BUSY
TCK
TCK
TDO
OE/RESET
(4)
BUSY
(4)
TDI
TDO
TMS
TCK
GND
(3)
CEO
TDI
TDO
I/O
CS_B
1KΩ
Xilinx FPGA
Master SelectMAP
I/O(3)
(3)
RDWR_B
First
PROM
(PROM 0)
OE/RESET
(1)
I/O(3)
1KΩ
CEO
(1)
1KΩ
CE
MODE PINS
1KΩ
CLK
D[0:7]
(2)
XCFxxP
Platform Flash
PROM
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
4.7 kΩ
VCCO(2)
VCCJ VCCO VCCINT
4.7 kΩ
VCCJ VCCO VCCINT
TDO
GND
TDI
TDI
TMS
TMS
TCK
TCK
GND
GND
TDO
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for highfrequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be tied to
VCCO via a 4.7 kΩ pull-up resistor.
ds123_16_122105
Figure 11: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
VCCJ VCCO VCCINT
VCCJ VCCO VCCINT
VCCO
(2)
External (3)
Oscillator
D0
VCCINT
D0
VCCINT
VCCO
VCCO
VCCJ(2)
VCCJ
XCFxxP
Platform Flash
PROM
XCFxxP
Platform Flash
PROM
DOUT
(3)
CLK
CE
CEO
First
PROM
(PROM 0)
OE/RESET
TMS
TCK
TCK
(1)
(3)
CCLK
CCLK
CE
DONE
DONE
CEO
INIT_B
INIT_B
CF
PROG_B
PROG_B
TDO
TDI
TDI
TMS
TMS
TCK
TCK
OE/RESET
(4)
CF
TDO
Xilinx FPGA
Slave Serial
Xilinx FPGA
Slave Serial
CLK
(4)
TMS
MODE PINS
DIN
(2)
Cascaded
PROM
(PROM 1)
TDI
MODE PINS(1)
DIN
(2)
(2)
TDI
4.7 kΩ
4.7 kΩ
(1)
TDI
TMS
TDO
TCK
EN_EXT_SEL
EN_EXT_SEL
REV_SEL[1:0]
REV_SEL[1:0]
GND
GND
GND
TDO
GND
EN_EXT_SEL
Design
Revision
Control
Logic
REV_SEL[1:0]
DONE
CF / PROG_B
Notes
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2. For compatible voltages, refer to the appropriate data sheet.
3. In Slave Serial mode, the configuration interface can be clocked by an external oscillator, or optionally the CLKOUT
signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is used,
then CLKOUT must be tied to a 4.7 KΩ resistor pulled up to VCCO.
4. For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it
must be tied to VCCO via a 4.7 kΩ pull-up resistor.
ds123_17_122105
Figure 12: Configuring Multiple Devices with Design Revisioning in Slave Serial Mode
DS123 (v2.9) May 09, 2006
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VCCJ
Platform Flash In-System Programmable Configuration PROMS
VCCO VCCINT
VCCJ
VCCO VCCINT
VCCO
(2)
VCCINT
VCCO
(2)
VCCJ
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
CLK
(5)
CE
CEO
TDI
TMS
TMS
TCK
TCK
MODE PINS
(1)
D[0:7]
RDWR_B
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
Xilinx FPGA
Slave SelectMAP
MODE PINS
(1)
RDWR_B
I/O
CS_B
(3)
I/O
CS_B
Xilinx FPGA
Slave SelectMAP
CLK(5)
CCLK
CCLK
CE
DONE
DONE
(3)
CEO
INIT_B
INIT_B
(6)
PROG_B
PROG_B
(4)
BUSY(4)
BUSY(4)
OE/RESET
CF
(6)
CF
BUSY
(4)
BUSY
TDO
D[0:7]
(2)
OE/RESET
TDI
D[0:7]
(2)
1KΩ
VCCJ
D[0:7]
(2)
VCCO
(1)
1KΩ
VCCINT
4.7 kΩ
4.7 kΩ
External (5)
Oscillator
TDI
TMS
TDO
TCK
EN_EXT_SEL
EN_EXT_SEL
REV_SEL[1:0]
REV_SEL[1:0]
GND
TDO
TDI
TDO
TDI
TMS
TMS
TCK
TCK
TDO
GND
GND
GND
EN_EXT_SEL
Design
REV_SEL[1:0]
Revision
CF
Control
DONE
Logic
PROG_B
CS_B[1:0]
Notes:
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2. For compatible voltages, refer to the appropriate data sheet.
3. RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4. The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5. In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or optionally the
CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is
used, then it must be tied to a 4.7KΩ resistor pulled up to VCCO.
6 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be
tied to VCCO via a 4.7 kΩ pull-up resistor
ds123_18_122105
Figure 13: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
Reset and Power-On Reset Activation
At power up, the device requires the VCCINT power supply to
monotonically rise to the nominal operating voltage within
the specified VCCINT rise time. If the power supply cannot
meet this requirement, then the device might not perform
power-on reset properly. During the power-up sequence,
OE/RESET is held Low by the PROM. Once the required
supplies have reached their respective POR (Power On
Reset) thresholds, the OE/RESET release is delayed (TOER
minimum) to allow more margin for the power supplies to
stabilize before initiating configuration. The OE/RESET pin
is connected to an external 4.7kΩ pull-up resistor and also
to the target FPGA's INIT pin. For systems utilizing
slow-rising power supplies, an additional power monitoring
circuit can be used to delay the target configuration until the
system power reaches minimum operating voltages by
holding the OE/RESET pin Low. When OE/RESET is
released, the FPGA’s INIT pin is pulled High allowing the
FPGA's configuration sequence to begin. If the power drops
below the power-down threshold (VCCPD), the PROM resets
and OE/RESET is again held Low until the after the POR
threshold is reached. OE/RESET polarity is not
programmable. These power-up requirements are shown
graphically in Figure 14, page 22.
For a fully powered Platform Flash PROM, a reset occurs
whenever OE/RESET is asserted (Low) or CE is
deasserted (High). The address counter is reset, CEO is
driven High, and the remaining outputs are placed in a
high-impedance state.
Notes:
1. The XCFxxS PROM only requires VCCINT to rise above
its POR threshold before releasing OE/RESET.
2. The XCFxxP PROM requires both VCCINT to rise above
its POR threshold and for VCCO to reach the
recommended operating voltage level before releasing
OE/RESET.
Recommended Operating Range
VCCINT
Delay or Restart
Configuration
200 µs ramp
50 ms ramp
VCCPOR
VCCPD
A slow-ramping VCCINT supply may still
be below the minimum operating
voltage when OE/RESET is released.
In this case, the configuration
sequence must be delayed until both
VCCINT and VCCO have reached their
recommended operating conditions.
TOER
TOER
TIME (ms)
TRST
ds123_21_103103
Figure 14: Platform Flash PROM Power-Up Requirements
I/O Input Voltage Tolerance and Power Sequencing
The I/Os on each re-programmable Platform Flash PROM
are fully 3.3V-tolerant. This allows 3V CMOS signals to
connect directly to the inputs without damage. The core
power supply (VCCINT), JTAG pin power supply (VCCJ),
output power supply (VCCO), and external 3V CMOS I/O
signals can be applied in any order.
Additionally, for the XCFxxS PROM only, when VCCO is
supplied at 2.5V or 3.3V and VCCINT is supplied at 3.3V, the
I/Os are 5V-tolerant. This allows 5V CMOS signals to connect
directly to the inputs on a powered XCFxxS PROM without
damage. Failure to power the PROM correctly while supplying
a 5V input signal may result in damage to the XCFxxS device.
DS123 (v2.9) May 09, 2006
Standby Mode
The PROM enters a low-power standby mode whenever CE
is deasserted (High). In standby mode, the address counter
is reset, CEO is driven High, and the remaining outputs are
placed in a high-impedance state regardless of the state of
the OE/RESET input. For the device to remain in the
low-power standby mode, the JTAG pins TMS, TDI, and
TDO must not be pulled Low, and TCK must be stopped
(High or Low).
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330Ω
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Platform Flash In-System Programmable Configuration PROMS
external buffer should be used to drive the LED circuit to
ensure valid transitions on the PROM’s CE pin. If low-power
standby mode is not required for the PROM, then the CE pin
should be connected to ground.
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and is also connected to the
PROM CE pin to enable low-power standby mode, then an
Table 11: Truth Table for XCFxxS PROM Control Inputs
Control Inputs
OE/RESET
CE
High
Low
Low
X (1)
Internal Address
Outputs
DATA
CEO
ICC
If address < TC (2) : increment
Active
High
Active
If address = TC (2) : don't change
High-Z
Low
Reduced
Low
Held reset
High-Z
High
Active
High
Held reset
High-Z
High
Standby
Notes:
1.
2.
X = don’t care.
TC = Terminal Count = highest address value.
Table 12: Truth Table for XCFxxP PROM Control Inputs
Control Inputs
OE/RESET
CE
CF
Internal Address
BUSY(5)
DATA
CEO
CLKOUT
ICC
Active
High
Active
Active
If address < TC (2) and
address = EA (3) : don't change
High-Z
High
High-Z
Reduced
Else
If address = TC (2) : don't change
High-Z
Low
High-Z
Reduced
Active and
Unchanged
High
Active
Active
If address
address <
High
Low
High
High
Low
High
High
Low
↑
Low
X
Low
High
X
X
Low
High
X (1)
X
X
Outputs
< TC (2)
EA (3) :
and
increment
Unchanged
Reset (4)
Active
High
Active
Active
Held
reset (4)
High-Z
High
High-Z
Active
Held
reset (4)
High-Z
High
High-Z
Standby
Notes:
1.
2.
3.
4.
5.
X = don’t care.
TC = Terminal Count = highest address value.
For the XCFxxP with Design Revisioning enabled, EA = end address (last address in the selected design revision).
For the XCFxxP with Design Revisioning enabled, Reset = address reset to the beginning address of the selected bank. If Design
Revisioning is not enabled, then Reset = address reset to address 0.
The BUSY input is only enabled when the XCFxxP is programmed for parallel data output and decompression is not enabled.
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
DC Electrical Characteristics
Absolute Maximum Ratings
Symbol
Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
Units
VCCINT
Internal supply voltage relative to GND
–0.5 to +4.0
–0.5 to +2.7
V
VCCO
I/O supply voltage relative to GND
–0.5 to +4.0
–0.5 to +4.0
V
VCCJ
JTAG I/O supply voltage relative to GND
–0.5 to +4.0
–0.5 to +4.0
V
VIN
Input voltage with respect to GND
VCCO < 2.5V
–0.5 to +3.6
–0.5 to +3.6
V
VCCO ≥ 2.5V
–0.5 to +5.5
–0.5 to +3.6
V
VCCO < 2.5V
–0.5 to +3.6
–0.5 to +3.6
V
VCCO ≥ 2.5V
–0.5 to +5.5
–0.5 to +3.6
V
–65 to +150
–65 to +150
°C
+125
+125
°C
VTS
Voltage applied to High-Z output
TSTG
Storage temperature (ambient)
TJ
Junction temperature
Notes:
1.
2.
3.
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device
pins can undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being
limited to 200 mA.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com.
Supply Voltage Requirements for Power-On Reset and Power-Down
Symbol
XCF01S, XCF02S,
XCF04S
Description
XCF08P, XCF16P,
XCF32P
Units
Min
Max
Min
Max
0.2
50
0.2
50
ms
1
–
0.5
–
V
0.5
3
0.5
30
ms
TVCC
VCCINT rise time from 0V to nominal voltage (2)
VCCPOR
POR threshold for the VCCINT supply
TOER
OE/RESET release delay following POR (3)
VCCPD
Power-down threshold for VCCINT supply
–
1
–
0.5
V
TRST
Time required to trigger a device reset when the VCCINT
supply drops below the maximum VCCPD threshold
10
–
10
–
ms
Notes:
1.
2.
3.
VCCINT, VCCO, and VCCJ supplies may be applied in any order.
At power up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified TVCC
rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure 14,
page 22.
If the VCCINT and VCCO supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released,
then the configuration data from the PROM will not be available at the recommended threshold levels. The configuration sequence must be
delayed until both VCCINT and VCCO have reached their recommended operating conditions.
DS123 (v2.9) May 09, 2006
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24
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Platform Flash In-System Programmable Configuration PROMS
Recommended Operating Conditions
Symbol
VCCINT
Description
XCF08P, XCF16P, XCF32P
Units
Min
Typ
Max
Min
Typ
Max
3.0
3.3
3.6
1.65
1.8
2.0
V
3.3V Operation
3.0
3.3
3.6
3.0
3.3
3.6
V
2.5V Operation
2.3
2.5
2.7
2.3
2.5
2.7
V
1.8V Operation
1.7
1.8
1.9
1.7
1.8
1.9
V
1.5V Operation
–
–
–
TBD
1.5
TBD
V
3.3V Operation
3.0
3.3
3.6
3.0
3.3
3.6
V
2.5V Operation
2.3
2.5
2.7
2.3
2.5
2.7
V
3.3V Operation
0
–
0.8
0
–
0.8
V
2.5V Operation
0
–
0.7
0
–
0.7
V
1.8V Operation
–
–
20% VCCO
–
–
20% VCCO
V
1.5V Operation
–
–
–
0
–
TBD
V
3.3V Operation
2.0
–
5.5
2.0
–
3.6
V
High-level input 2.5V Operation
voltage
1.8V Operation
1.7
–
5.5
1.7
–
3.6
V
70% VCCO
–
3.6
70% VCCO
–
3.6
V
1.5V Operation
–
–
–
TBD
–
3.6
V
time(1)
–
–
500
–
–
500
ns
0
–
VCCO
0
–
VCCO
V
–40
–
85
–40
–
85
°C
Min
Max
Units
20
–
Years
Internal voltage supply
VCCO
Supply voltage
for output
drivers
VCCJ
XCF01S, XCF02S, XCF04S
Supply voltage
for JTAG output
drivers
VIL
Low-level input
voltage
VIH
TIN
Input signal transition
VO
Output voltage
TA
Operating ambient temperature
Notes:
1.
Input signal transition time measured between 10% VCCO and 90% VCCO .
Quality and Reliability Characteristics
Symbol
Description
TDR
Data retention
NPE
Program/erase cycles (Endurance)
20,000
–
Cycles
VESD
Electrostatic discharge (ESD)
2,000
–
Volts
DS123 (v2.9) May 09, 2006
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25
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Platform Flash In-System Programmable Configuration PROMS
DC Characteristics Over Operating Conditions
Symbol
XCF01S, XCF02S,
XCF04S
Description
ICCINT
ICCO (1)
Units
Test
Conditions
Min
Max
Test
Conditions
Min
Max
High-level output voltage for 3.3V outputs
IOH = –4 mA
2.4
–
IOH = –4 mA
2.4
–
V
High-level output voltage for 2.5V outputs
IOH = –500 µA
VCCO
– 0.4
–
IOH = –500 µA
VCCO
– 0.4
–
V
High-level output voltage for 1.8V outputs
IOH = –50 µA
VCCO
– 0.4
–
IOH = –50 µA
VCCO
– 0.4
–
V
High-level output voltage for 1.5V outputs
–
–
–
IOH = TBD
TBD
–
V
Low-level output voltage for 3.3V outputs
IOL = 4 mA
–
0.4
IOL = 4 mA
–
0.4
V
VOH
VOL
XCF08P, XCF16P,
XCF32P
Low-level output voltage for 2.5V outputs
IOL = 500 µA
–
0.4
IOL = 500 µA
–
0.4
V
Low-level output voltage for 1.8V outputs
IOL = 50 µA
–
0.4
IOL = 50 µA
–
0.4
V
Low-level output voltage for 1.5V outputs
–
–
–
IOL = TBD
–
TBD
V
Internal voltage supply current, active mode
33 MHz
–
10
33 MHz
–
10
mA
Output driver supply current, active serial mode
33 MHz
–
10
33 MHz
–
10
mA
–
–
–
33 MHz
–
40
mA
Output driver supply current, active parallel mode
ICCJ
JTAG supply current, active mode
Note (2)
–
5
Note (2)
–
5
mA
ICCINTS
Internal voltage supply current, standby mode
Note (3)
–
5
Note (3)
–
1
mA
ICCOS
Output driver supply current, standby mode
Note (3)
–
1
Note (3)
–
1
mA
ICCJS
JTAG supply current, standby mode
Note (3)
–
1
Note (3)
–
1
mA
IILJ
JTAG pins TMS, TDI, and TDO pull-up current
VCCJ = max
VIN = GND
–
100
VCCJ = max
VIN = GND
–
100
µA
IIL
Input leakage current
VCCINT = max
VCCO = max
VIN = GND or
VCCO
–10
10
VCCINT = max
VCCO = max
VIN = GND or
VCCO
–10
10
µA
IIH
Input and output High-Z leakage current
VCCINT = max
VCCO = max
VIN = GND or
VCCO
–10
10
VCCINT = max
VCCO = max
VIN = GND or
VCCO
–10
10
µA
IILP
Source current through internal pull-ups on
EN_EXT_SEL, REV_SEL0, REV_SEL1
–
–
–
VCCINT = max
VCCO = max
VIN = GND or
VCCO
–
100
µA
-100
–
µA
–
–
–
VCCINT = max
VCCO = max
VIN = GND or
VCCO
Input capacitance
VIN = GND
f = 1.0 MHz
–
8
VIN = GND
f = 1.0 MHz
–
8
pF
Output capacitance
VIN = GND
f = 1.0 MHz
–
14
VIN = GND
f = 1.0 MHz
–
14
pF
IIHP
Sink current through internal pull-down on BUSY
CIN
COUT
Notes:
1.
2.
3.
Output driver supply current specification based on no load conditions.
TDI/TMS/TCK non-static (active).
CE High, OE Low, and TMS/TDI/TCK static.
DS123 (v2.9) May 09, 2006
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26
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Platform Flash In-System Programmable Configuration PROMS
AC Electrical Characteristics
AC Characteristics Over Operating Conditions
XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock Source
TSCE
CE
THCE
THOE
TCYC
OE/RESET
TLC
THC
CLK
TSB
BUSY
(optional)
TOE
THB
TOH
TCAC
TDF
TCE
DATA
THCF
TOH
TCF
CF
EN_EXT_SEL
REV_SEL[1:0]
TSXT
THXT
TSRV
TSXT
THRV
TSRV
THXT
THRV
ds123_22_122905
Symbol
XCF01S, XCF02S,
XCF04S
Description
Min
THCF
TCF
300
ns
CF hold time to guarantee design revision selection is
sampled when VCCO = 1.8V(9)
300
300
ns
CF to data delay when VCCO = 3.3V or 2.5V(8)
–
–
–
25
ns
CF to data delay when VCCO = 1.8V(8)
–
–
–
25
ns
–
10
–
25
ns
–
30
–
25
ns
–
15
–
25
ns
–
30
–
25
ns
–
15
–
25
ns
CLK to data delay (7) when VCCO = 1.8V
–
30
–
25
ns
Data hold from CE, OE/RESET, CLK, or CF
when VCCO = 3.3V or 2.5V(8)
0
–
5
–
ns
TOH
Data hold from CE, OE/RESET, CLK, or CF
when VCCO = 1.8V(8)
0
–
5
–
ns
delay (6)
when VCCO = 3.3V or 2.5V
OE/RESET to data delay (6) when VCCO = 1.8V
delay (5)
when VCCO = 3.3V or 2.5V
CE to data delay (5) when VCCO = 1.8V
CLK to data
TCAC
Units
Max
300
CE to data
TCE
Min
CF hold time to guarantee design revision selection is
sampled when VCCO = 3.3V or 2.5V(9)
OE/RESET to data
TOE
Max
XCF08P, XCF16P,
XCF32P
delay (7)
DS123 (v2.9) May 09, 2006
when VCCO = 3.3V or 2.5V
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27
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Platform Flash In-System Programmable Configuration PROMS
Symbol
TDF
TCYC
XCF01S, XCF02S,
XCF04S
Description
Max
Min
Max
CE or OE/RESET to data float delay (2)
when VCCO = 3.3V or 2.5V
–
25
–
45
ns
CE or OE/RESET to data float delay (2)
when VCCO = 1.8V
–
30
–
45
ns
Clock period (6) (serial mode) when VCCO = 3.3V or 2.5V
30
–
25
–
ns
Clock period (6) (serial mode) when VCCO = 1.8V
67
–
25
–
ns
–
–
30
–
ns
–
–
30
–
ns
10
–
12
–
ns
15
–
12
–
ns
10
–
12
–
ns
Clock
period (6)
CLK Low
(parallel mode) when VCCO = 3.3V or 2.5V
TSCE
THCE
THOE
TSB
THB
TSXT
THXT
TSRV
time(3)
when VCCO = 3.3V or 2.5V
CLK Low time(3) when VCCO = 1.8V
CLK High
THC
Units
Min
Clock period (6) (parallel mode) when VCCO = 1.8V
TLC
XCF08P, XCF16P,
XCF32P
time(3)
when VCCO = 3.3V or 2.5V
CLK High time (3) when VCCO = 1.8V
15
–
12
–
ns
counting) (3)
20
–
30
–
ns
CE setup time to CLK (guarantees proper counting) (3)
when VCCO = 1.8V
30
30
–
ns
CE hold time (guarantees counters are reset)(5)
when VCCO = 3.3V or 2.5V
250
–
2000
–
ns
CE hold time (guarantees counters are reset)(5)
when VCCO = 1.8V
250
–
2000
–
ns
OE/RESET hold time (guarantees counters are reset)(6)
when VCCO = 3.3V or 2.5V
250
–
2000
–
ns
OE/RESET hold time (guarantees counters are reset)(6)
when VCCO = 1.8V
250
–
2000
–
ns
–
–
12
–
ns
–
–
12
–
ns
–
–
8
–
ns
–
–
8
–
ns
EN_EXT_SEL setup time to CF, CE or OE/RESET
when VCCO = 3.3V or 2.5V(8)
–
–
300
–
ns
EN_EXT_SEL setup time to CF, CE or OE/RESET
when VCCO = 1.8V(8)
–
–
300
–
ns
EN_EXT_SEL hold time from CF, CE or OE/RESET
when VCCO = 3.3V or 2.5V(8)
–
–
300
–
ns
EN_EXT_SEL hold time from CF, CE or OE/RESET
when VCCO = 1.8V(8)
–
–
300
–
ns
REV_SEL setup time to CF, CE or OE/RESET
when VCCO = 3.3V or 2.5V(8)
–
–
300
–
ns
REV_SEL setup time to CF, CE or OE/RESET
when VCCO = 1.8V(8)
–
–
300
–
ns
CE setup time to CLK (guarantees proper
when VCCO = 3.3V or 2.5V
BUSY setup time to CLK when VCCO = 3.3V or 2.5V(8)
BUSY setup time to CLK when VCCO =
1.8V(8)
BUSY hold time to CLK when VCCO = 3.3V or 2.5V(8)
BUSY hold time to CLK when VCCO =
DS123 (v2.9) May 09, 2006
1.8V(8)
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28
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Platform Flash In-System Programmable Configuration PROMS
Symbol
THRV
XCF01S, XCF02S,
XCF04S
Description
XCF08P, XCF16P,
XCF32P
Units
Min
Max
Min
Max
REV_SEL hold time from CF, CE or OE/RESET
when VCCO = 3.3V or 2.5V(8)
–
–
300
–
ns
REV_SEL hold time from CF, CE or OE/RESET
when VCCO = 1.8V(8)
–
–
300
–
ns
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady-state active levels.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
If THCE High < 2 µs, TCE = 2 µs.
If THOE Low < 2 µs, TOE = 2 µs.
This is the minimum possible TCYC. Actual TCYC = TCAC + FPGA Data setup time. Example: With the XCF32P in serial mode with VCCO at
3.3V, if FPGA data setup time = 15 ns, then the actual TCYC = 25 ns +15 ns = 40 ns.
Guaranteed by design; not tested.
CF, EN_EXT_SEL, REV_SEL[1:0], and BUSY are inputs for the XCFxxP PROM only.
When JTAG CONFIG command is issued, PROM will drive CF Low for at least the THCF minimum.
DS123 (v2.9) May 09, 2006
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29
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Platform Flash In-System Programmable Configuration PROMS
XCFxxP PROM as Configuration Master with CLK Input Pin as Clock Source
CE
THCE
THOE
OE/RESET
TCYCO
TLC
THC
CLK
TCLKO
CLKOUT
TCECC
TSB
TOECC
BUSY
(optional)
THB T
CCDD
TDDC
TCECF
TOECF
TCOH
TOE
TCE
DATA
TCF
TCFCC
TEOH
TDF
THCF
CF
EN_EXT_SEL
REV_SEL[1:0]
TSXT
THXT
TSRV
TSXT
THRV
TSRV
THXT
THRV
Note: 8 CLKOUT cycles are output after CE rising edge, before CLKOUT
tristates, if OE/RESET remains high, and terminal count has not been reached.
Symbol
Description
ds123_25_122905
XCF08P, XCF16P,
XCF32P
Min
THCF
TCF
TOE
TCE
TEOH
TDF
TOECF
TCECF
Units
Max
CF hold time to guarantee design revision selection is sampled
when VCCO = 3.3V or 2.5V(11)
300
300
CF hold time to guarantee design revision selection is sampled
when VCCO = 1.8V(11)
300
300
CF to data delay when VCCO = 3.3V or 2.5V
–
TBD
ns
CF to data delay when VCCO = 1.8V
–
TBD
ns
OE/RESET to data
delay (6)
when VCCO = 3.3V or 2.5V
–
25
ns
OE/RESET to data
delay (6)
when VCCO = 1.8V
–
25
ns
CE to data
delay (5)
when VCCO = 3.3V or 2.5V
–
25
ns
CE to data
delay (5)
when VCCO = 1.8V
–
25
ns
Data hold from CE, OE/RESET, or CF when VCCO = 3.3V or 2.5V
5
–
ns
Data hold from CE, OE/RESET, or CF when VCCO = 1.8V
5
–
ns
CE or OE/RESET to data float
delay (2)
when VCCO = 3.3V or 2.5V
–
45
ns
CE or OE/RESET to data float
delay (2)
when VCCO = 1.8V
–
45
ns
OE/RESET to CLKOUT float
delay(2)
when VCCO = 3.3V or 2.5V
–
TBD
ns
OE/RESET to CLKOUT float
delay(2)
when VCCO = 1.8V
–
TBD
ns
CE to CLKOUT float
delay(2)
when VCCO = 3.3V or 2.5V
–
TBD
ns
CE to CLKOUT float
delay(2)
when VCCO = 1.8V
–
TBD
ns
DS123 (v2.9) May 09, 2006
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30
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Platform Flash In-System Programmable Configuration PROMS
Symbol
TCYCO
TLC
THC
THCE
THOE
TSB
THB
TCLKO
TCECC
XCF08P, XCF16P,
XCF32P
Description
Clock
period (7)
Clock
period (7)
Clock
period (7)
Clock
period (7)
Min
Max
(serial mode) when VCCO = 3.3V or 2.5V
30
–
ns
(serial mode) when VCCO = 1.8V
30
–
ns
(parallel mode) when VCCO = 3.3V or 2.5V
35
–
ns
(parallel mode) when VCCO = 1.8V
35
–
ns
CLK Low
time(3)
when VCCO = 3.3V or 2.5V
12
–
ns
CLK Low
time(3)
when VCCO = 1.8V
12
–
ns
CLK High
time(3)
when VCCO = 3.3V or 2.5V
12
–
ns
CLK High
time(3)
when VCCO = 1.8V
12
–
ns
CE hold time (guarantees counters are
reset)(5)
when VCCO = 3.3V or 2.5V
2000
–
ns
CE hold time (guarantees counters are
reset)(5)
when VCCO = 1.8V
2000
–
ns
OE/RESET hold time (guarantees counters are
reset)(6)
when VCCO = 3.3V or 2.5V
2000
–
ns
OE/RESET hold time (guarantees counters are
reset)(6)
when VCCO = 1.8V
2000
–
ns
BUSY setup time to CLKOUT when VCCO = 3.3V or 2.5V
12
–
ns
BUSY setup time to CLKOUT when VCCO = 1.8V
12
–
ns
BUSY hold time to CLKOUT when VCCO = 3.3V or 2.5V
8
–
ns
BUSY hold time to CLKOUT when VCCO = 1.8V
8
–
ns
CLK input to CLKOUT output delay when VCCO = 3.3V or 2.5V
–
35
ns
CLK input to CLKOUT output delay when VCCO = 1.8V
–
35
ns
CLK input to CLKOUT output delay when VCCO = 3.3V or 2.5V
with decompression (12)
–
35
ns
CLK input to CLKOUT output delay when VCCO = 1.8V
with decompression (12)
–
35
ns
CE to CLKOUT delay(8) when VCCO = 3.3V or 2.5V
0
2 CLK
cycles
–
CE to CLKOUT delay (8) when VCCO = 1.8V
0
2 CLK
cycles
–
OE/RESET to CLKOUT delay(8) when VCCO = 3.3V or 2.5V
0
2 CLK
cycles
–
OE/RESET to CLKOUT delay(8) when VCCO = 1.8V
0
2 CLK
cycles
–
CF to CLKOUT delay(8) when VCCO = 3.3V or 2.5V
0
TBD
–
0
TBD
–
–
30
ns
–
30
ns
TOECC
TCFCC
TCCDD
TDDC
CF to CLKOUT
delay(8) when
VCCO = 1.8V
CLKOUT to data delay when VCCO = 3.3V or
CLKOUT to data delay when VCCO =
2.5V(9)
1.8V(9)
Data setup time to CLKOUT when VCCO = 3.3V or 2.5V with
Data setup time to CLKOUT when VCCO = 1.8V with
decompression (9)(12)
decompression (9)(12)
Data hold from CLKOUT when VCCO = 3.3V or 2.5V
TCOH
5
ns
5
ns
3
–
ns
3
–
ns
3
–
ns
3
–
ns
EN_EXT_SEL setup time to CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
EN_EXT_SEL setup time to CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
Data hold from CLKOUT when VCCO = 1.8V
Data hold from CLKOUT when VCCO = 3.3V or 2.5V with
Data hold from CLKOUT when VCCO = 1.8V with
TSXT
Units
DS123 (v2.9) May 09, 2006
decompression (12)
decompression (12)
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31
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Platform Flash In-System Programmable Configuration PROMS
Symbol
THXT
TSRV
THRV
Description
XCF08P, XCF16P,
XCF32P
Units
Min
Max
EN_EXT_SEL hold time from CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
EN_EXT_SEL hold time from CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
REV_SEL setup time to CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
REV_SEL setup time to CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
REV_SEL hold time from CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
REV_SEL hold time from CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
Notes:
1.
2.
3.
4.
5.
6.
7.
AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
Float delays are measured with 5 pF AC loads.Transition is measured at ±200 mV from steady-state active levels.
Guaranteed by design, not tested.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
If THCE High < 2 µs, TCE = 2 µs.
If THOE Low < 2 µs, TOE = 2 µs.
This is the minimum possible TCYCO. Actual TCYCO = TCCDD + FPGA Data setup time. Example: With the XCF32P in serial mode with VCCO
at 3.3V, if FPGA Data setup time = 15 ns, then the actual TCYCO = 25 ns +15 ns = 40 ns.
8. The delay before the enabled CLKOUT signal begins clocking data out of the device is dependent on the clocking configuration. The delay
before CLKOUT is enabled will increase if decompression is enabled.
9. Slower CLK frequency option may be required to meet the FPGA data sheet setup time.
10. When decompression is enabled, the CLKOUT signal becomes a controlled clock output. When decompressed data is available, CLKOUT
will toggle at ½ the source clock frequency (either ½ the selected internal clock frequency or ½ the external CLK input frequency). When
decompressed data is not available, the CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a 4.7kΩ
pull-up to VCCO.
11. When JTAG CONFIG command is issued, PROM will drive CF Low for at least the THCF minimum.
DS123 (v2.9) May 09, 2006
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32
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Platform Flash In-System Programmable Configuration PROMS
XCFxxP PROM as Configuration Master with Internal Oscillator as Clock Source
CE
THCE
THOE
OE/RESET
CLKOUT
TCEC
TSB
TOEC
BUSY
(optional)
THB
TCDD
TDDC
TCECF
TOECF
TCOH
TOE
TCE
DATA
TCF
TCFC
TEOH
TDF
THCF
CF
EN_EXT_SEL
REV_SEL[1:0]
TSXT
THXT
TSRV
TSXT
THRV
TSRV
THXT
THRV
Note: 8 CLKOUT cycles are output after CE rising edge, before CLKOUT
tristates, if OE/RESET remains high, and terminal count has not been reached.
Symbol
Description
ds123_26_122905
XCF08P, XCF16P,
XCF32P
Min
THCF
TCF
TOE
TCE
TEOH
TDF
TOECF
TCECF
THCE
Units
Max
CF hold time to guarantee design revision selection is sampled
when VCCO = 3.3V or 2.5V(12)
300
300
CF hold time to guarantee design revision selection is sampled
when VCCO = 1.8V(12)
300
300
CF to data delay when VCCO = 3.3V or 2.5V
–
TBD
ns
CF to data delay when VCCO = 1.8V
–
TBD
ns
OE/RESET to data
delay(6)
when VCCO = 3.3V or 2.5V
–
25
ns
OE/RESET to data
delay(6)
when VCCO = 1.8V
–
25
ns
CE to data
delay(5)
when VCCO = 3.3V or 2.5V
–
25
ns
CE to data
delay(5)
when VCCO = 1.8V
–
25
ns
Data hold from CE, OE/RESET, or CF when VCCO = 3.3V or 2.5V
5
–
ns
Data hold from CE, OE/RESET, or CF when VCCO = 1.8V
5
–
ns
CE or OE/RESET to data float
delay (2)
when VCCO = 3.3V or 2.5V
–
45
ns
CE or OE/RESET to data float
delay (2)
when VCCO = 1.8V
–
45
ns
OE/RESET to CLKOUT float
delay(2)
when VCCO = 3.3V or 2.5V
–
TBD
ns
OE/RESET to CLKOUT float
delay(2)
when VCCO = 1.8V
–
TBD
ns
CE to CLKOUT float
delay(2)
when VCCO = 3.3V or 2.5V
–
TBD
ns
CE to CLKOUT float
delay(2)
when VCCO = 1.8V
–
TBD
ns
CE hold time (guarantees counters are
reset) (5)
when VCCO = 3.3V or 2.5V
2000
–
ns
CE hold time (guarantees counters are
reset) (5)
when VCCO = 1.8V
2000
–
ns
DS123 (v2.9) May 09, 2006
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33
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Platform Flash In-System Programmable Configuration PROMS
Symbol
THOE
TSB
THB
TCEC
TOEC
TCFC
TCDD
TDDC
TCOH
THXT
TSRV
THRV
FF
Units
Min
Max
when VCCO = 3.3V or 2.5V
2000
–
ns
when VCCO = 1.8V
2000
–
ns
BUSY setup time to CLKOUT when VCCO = 3.3V or 2.5V
12
–
ns
BUSY setup time to CLKOUT when VCCO = 1.8V
12
–
ns
BUSY hold time to CLKOUT when VCCO = 3.3V or 2.5V
8
–
ns
BUSY hold time to CLKOUT when VCCO = 1.8V
8
–
ns
0
1
µs
0
1
µs
OE/RESET hold time (guarantees counters are
reset) (6)
OE/RESET hold time (guarantees counters are
reset) (6)
CE to CLKOUT
delay(7)
CE to CLKOUT
delay (7) when
when VCCO = 3.3V or 2.5V
VCCO = 1.8V
OE/RESET to CLKOUT
delay(7)
when VCCO = 3.3V or 2.5V
0
1
µs
OE/RESET to CLKOUT
delay(7)
when VCCO = 1.8V
0
1
µs
CF to CLKOUT
delay(7) when
VCCO = 3.3V or 2.5V
0
TBD
–
CF to CLKOUT
delay(7) when
VCCO = 1.8V
0
TBD
–
–
30
ns
–
30
ns
CLKOUT to data delay when VCCO = 3.3V or
CLKOUT to data delay when VCCO =
2.5V(8)
1.8V(8)
Data setup time to CLKOUT
when VCCO = 3.3V or 2.5V with decompression (8)(11)
5
ns
Data setup time to CLKOUT when VCCO = 1.8V with decompression(8)(11)
5
ns
Data hold from CLKOUT when VCCO = 3.3V or 2.5V
3
–
ns
3
–
ns
3
–
ns
3
–
ns
EN_EXT_SEL setup time to CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
EN_EXT_SEL setup time to CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
EN_EXT_SEL hold time from CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
EN_EXT_SEL hold time from CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
REV_SEL setup time to CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
REV_SEL setup time to CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
REV_SEL hold time from CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
REV_SEL hold time from CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
25
50
MHz
12.5
25
MHz
Data hold from CLKOUT when VCCO = 1.8V
Data hold from CLKOUT when VCCO = 3.3V or 2.5V with
Data hold from CLKOUT when VCCO = 1.8V with
TSXT
XCF08P, XCF16P,
XCF32P
Description
CLKOUT default (fast)
decompression(11)
frequency(9)
CLKOUT default (fast) frequency with
DS123 (v2.9) May 09, 2006
decompression(11)
decompression(11)
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34
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Platform Flash In-System Programmable Configuration PROMS
Symbol
FS
Description
CLKOUT alternate (slower)
frequency(10)
CLKOUT alternate (slower) frequency with
decompression(11)
XCF08P, XCF16P,
XCF32P
Units
Min
Max
12.5
25
MHz
6
12.5
MHz
Notes:
1.
2.
3.
4.
5.
6.
7.
AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady-state active levels.
Guaranteed by design, not tested.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
If THCE High < 2 µs, TCE = 2 µs.
If THOE Low < 2 µs, TOE = 2 µs.
The delay before the enabled CLKOUT signal begins clocking data out of the device is dependent on the clocking configuration. The delay
before CLKOUT is enabled will increase if decompression is enabled.
8. Slower CLK frequency option may be required to meet the FPGA data sheet setup time.
9. Typical CLKOUT default (fast) period = 25 ns (40 MHz)
10. Typical CLKOUT alternate (slower) period = 50 ns (20 MHz)
11. When decompression is enabled, the CLKOUT signal becomes a controlled clock output. When decompressed data is available, CLKOUT
will toggle at ½ the source clock frequency (either ½ the selected internal clock frequency or ½ the external CLK input frequency). When
decompressed data is not available, the CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a 4.7kΩ
pull-up to VCCO.
12. When JTAG CONFIG command is issued, PROM will drive CF Low for at least the THCF minimum.
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
AC Characteristics Over Operating Conditions When Cascading
OE/RESET
CE
CLK
CLKOUT
(optional)
TCDF
TCODF
DATA
Last Bit
First Bit
TOCE
TOOE
TOCK
TCOCE
CEO
ds123_23_102203
Symbol
TCDF
TOCK
TOCE
TOOE
TCOCE
TCODF
XCF01S, XCF02S,
XCF04S
Description
XCF08P, XCF16P,
XCF32P
Units
Min
Max
Min
Max
CLK to output float delay (2,3)
when VCCO = 2.5V or 3.3V
–
25
–
20
ns
CLK to output float delay (2,3) when VCCO = 1.8V
–
35
–
20
ns
CLK to CEO
delay (3,5)
when VCCO = 2.5V or 3.3V
–
20
–
20
ns
CLK to CEO
delay (3,5)
when VCCO = 1.8V
–
35
–
20
ns
CE to CEO
delay (3,6)
–
20
–
80
ns
CE to CEO delay (3,6) when VCCO = 1.8V
–
35
–
80
ns
OE/RESET to CEO delay (3) when VCCO = 2.5V or 3.3V
–
20
–
80
ns
–
35
–
80
ns
CLKOUT to CEO delay when VCCO = 2.5V or 3.3V
–
–
–
20
ns
CLKOUT to CEO delay when VCCO = 1.8V
–
–
–
20
ns
CLKOUT to output float delay
when VCCO = 2.5V or 3.3V
–
–
–
25
ns
CLKOUT to output float delay when VCCO = 1.8V
–
–
–
25
ns
OE/RESET to CEO
when VCCO = 2.5V or 3.3V
delay (3)
when VCCO = 1.8V
Notes:
1. AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins are set to persist as configuration pins, the minimum
period is increased based on the CLK to CEO and CE to data propagation delays:
- TCYC minimum = TOCK + TCE + FPGA Data setup time.
- TCAC maximum = TOCK + TCE
6. For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins become general I/O pins after configuration; to allow for
the disable to propagate to the cascaded PROMs and to avoid contention on the data lines following configuration, the minimum
period is increased based on the CE to CEO and CE to data propagation delays:
- TCYC minimum = TOCE + TCE
- TCAC maximum = TOCK + TCE
DS123 (v2.9) May 09, 2006
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36
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Platform Flash In-System Programmable Configuration PROMS
Pinouts and Pin Descriptions
The XCFxxS Platform Flash PROM is available in the VO20 and VOG20 packages. The XCFxxP Platform Flash PROM is
available in the VO48, VOG48, FS48, and FSG48 packages.
Notes:
1.
VO20/VOG20 denotes a 20-pin (TSSOP) Plastic Thin Shrink Small Outline Package
2.
VO48/VOG48 denotes a 48-pin (TSOP) Plastic Thin Small Outline Package.
3.
FS48/FSG48 denotes a 48-pin (TFBGA) Plastic Thin Fine Pitch Ball Grid Array (0.8 mm pitch).
XCFxxS Pinouts and Pin Descriptions
XCFxxS VO20/VOG20 Pin Names and Descriptions
Table 13 provides a list of the pin names and descriptions for the XCFxxS 20-pin VO20/VOG20 package.
Table 13: XCFxxS Pin Names and Descriptions
Pin Name
D0
CLK
OE/RESET
CE
CF
CEO
Boundary
Scan Order
Boundary Scan
Function
4
Data Out
3
Output Enable
0
Data In
20
Data In
19
Data Out
18
Output Enable
15
Data In
22
Data Out
21
Output Enable
12
Data Out
11
Output Enable
TMS
Mode Select
TCK
Clock
Pin Description
20-pin TSSOP
(VO20/VOG20)
D0 is the DATA output pin to provide data for configuring an
FPGA in serial mode. The D0 output is set to a
high-impedance state during ISPEN (when not clamped).
1
Configuration Clock Input. Each rising edge on the CLK input
increments the internal address counter if the CLK input is
selected, CE is Low, and OE/RESET is High.
3
Output Enable/Reset (Open-Drain I/O). When Low, this input
holds the address counter reset and the DATA output is in a
high-impedance state. This is a bidirectional open-drain pin
that is held Low while the PROM completes the internal
power-on reset sequence. Polarity is not programmable.
8
Chip Enable Input. When CE is High, the device is put into
low-power standby mode, the address counter is reset, and
the DATA pins are put in a high-impedance state.
10
Configuration Pulse (Open-Drain Output). Allows JTAG
CONFIG instruction to initiate FPGA configuration without
powering down FPGA. This is an open-drain output that is
pulsed Low by the JTAG CONFIG command.
7
Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
13
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50 KΩ resistive
pull-up to VCCJ to provide a logic 1 to the device if the pin is
not driven.
5
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
programming electronics.
6
4
TDI
Data In
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50 KΩ
resistive pull-up to VCCJ to provide a logic 1 to the device if the
pin is not driven.
TDO
Data Out
JTAG Serial Data Output. This pin is the serial output for all
JTAG instruction and data registers. TDO has an internal
50 KΩ resistive pull-up to VCCJ to provide a logic 1 to the
system if the pin is not driven.
17
+3.3V Supply. Positive 3.3V supply voltage for internal logic.
18
VCCINT
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
Table 13: XCFxxS Pin Names and Descriptions
Pin Name
Boundary
Scan Order
Boundary Scan
Function
Pin Description
20-pin TSSOP
(VO20/VOG20)
VCCO
+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the output voltage drivers and
input buffers.
19
VCCJ
+3.3V or 2.5V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the TDO output voltage driver
and TCK, TMS, and TDI input buffers.
20
GND
Ground
11
DNC
Do not connect. (These pins must be left unconnected.)
2, 9, 12, 14, 15, 16
XCFxxS VO20/VOG20 Pinout Diagram
D0
1
20
VCCJ
(DNC)
2
19
VCCO
CLK
3
18
VCCINT
TDI
4
17
TDO
TMS
5
TCK
6
CF
VO20/VOG20
16
Top View
(DNC)
15
(DNC)
7
14
(DNC)
OE/RESET
8
13
CEO
(DNC)
9
12
(DNC)
10
11
GND
CE
ds123_02_071304
Figure 15: VO20/VOG20 Pinout Diagram (Top View)
with Pin Names
DS123 (v2.9) May 09, 2006
www.xilinx.com
38
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Platform Flash In-System Programmable Configuration PROMS
XCFxxP Pinouts and Pin Descriptions
VXCFxxP O48/VOG48 and FS48/FSG48 Pin Names and Descriptions
Table 14 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48
packages.
Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48)
Pin Name
D0
D1
D2
D3
D4
D5
D6
D7
48-pin
TSOP
(VO48/
VOG48)
48-pin
TFBGA
(FS48/
FSG48)
28
H6
29
H5
32
E5
33
D5
43
C5
44
B5
47
A5
48
A6
Configuration Clock Input. An internal programmable control
bit selects between the internal oscillator and the CLK input
pin as the clock source to control the configuration sequence.
Each rising edge on the CLK input increments the internal
address counter if the CLK input is selected, CE is Low,
OE/RESET is High, BUSY is Low (parallel mode only), and
CF is High.
12
B3
Output Enable/Reset (Open-Drain I/O).
When Low, this input holds the address counter reset and the
Data Out
DATA and CLKOUT outputs are placed in a high-impedance
Output Enable state. This is a bidirectional open-drain pin that is held Low
while the PROM completes the internal power-on reset
sequence. Polarity is not programmable.
11
A3
Chip Enable Input. When CE is High, the device is put into
low-power standby mode, the address counter is reset, and
the DATA and CLKOUT outputs are placed in a
high-impedance state.
13
B4
Configuration Pulse (Open-Drain I/O). As an output, this pin
allows the JTAG CONFIG instruction to initiate FPGA
configuration without powering down the FPGA. This is an
open-drain signal that is pulsed Low by the JTAG CONFIG
Data Out
command. As an input, on the rising edge of CF, the current
design revision selection is sampled and the internal address
Output Enable counter is reset to the start address for the selected revision.
If unused, the CF pin must be pulled High using an external
4.7 KΩ pull-up to VCCO.
6
D1
Boundary
Scan Order
Boundary
Scan
Function
28
Data Out
27
Output Enable
26
Data Out
25
Output Enable
24
Data Out
23
22
21
20
19
18
17
D0 is the DATA output pin to provide data for configuring an
Output Enable FPGA in serial mode.
D0-D7 are the DATA output pins to provide parallel data for
Data Out
configuring a Xilinx FPGA in SelectMap (parallel) mode.
Output Enable
The D0 output is set to a high-impedance state during ISPEN
(when not clamped).
Data Out
The D1-D7 outputs are set to a high-impedance state during
Output Enable ISPEN (when not clamped) and when serial mode is selected
for configuration. The D1-D7 pins can be left unconnected
Data Out
when the PROM is used in serial mode.
Output Enable
16
Data Out
15
Output Enable
14
Data Out
13
Output Enable
01
Data In
CLK
04
OE/RESET
03
02
00
Data In
Data In
CE
11
CF
10
09
DS123 (v2.9) May 09, 2006
Pin Description
Data In
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39
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Platform Flash In-System Programmable Configuration PROMS
Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Continued)
48-pin
TSOP
(VO48/
VOG48)
48-pin
TFBGA
(FS48/
FSG48)
10
D2
25
H4
26
G3
27
G4
Busy Input. The BUSY input is enabled when parallel mode
is selected for configuration. When BUSY is High, the internal
address counter stops incrementing and the current data
remains on the data pins. On the first rising edge of CLK after
BUSY transitions from High to Low, the data for the next
address is driven on the data pins. When serial mode or
decompression is enabled during device programming, the
BUSY input is disabled. BUSY has an internal 50 KΩ
resistive pull-down to GND to provide a logic 0 to the device
if the pin is not driven.
5
C1
Configuration Clock Output. An internal Programmable
control bit enables the CLKOUT signal, which is sourced from
Output Enable either the internal oscillator or the CLK input pin. Each rising
edge of the selected clock source increments the internal
address counter if data is available, CE is Low, and
OE/RESET is High. Output data is available on the rising
edge of CLKOUT. CLKOUT is disabled if CE is High or
OE/RESET is Low. If decompression is enabled, CLKOUT is
parked High when decompressed data is not ready. When
CLKOUT is disabled, the CLKOUT pin is put into a high-Z
state. If CLKOUT is used, then it must be pulled High
externally using a 4.7 KΩ pull-up to VCCO.
9
C2
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50 KΩ resistive
pull-up to VCCJ to provide a logic 1 to the device if the pin is
not driven.
21
E2
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
programming electronics.
20
H3
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50 KΩ
resistive pull-up to VCCJ to provide a logic 1 to the device if
the pin is not driven.
19
G1
TDO
JTAG Serial Data Output. This pin is the serial output for all
JTAG instruction and data registers. TDO has an internal
50KΩ resistive pull-up to VCCJ to provide a logic 1 to the
system if the pin is not driven.
22
E6
VCCINT
+1.8V Supply. Positive 1.8V supply voltage for internal logic.
4, 15, 34
B1, E1,
G6
Pin Name
CEO
Boundary
Scan Order
Boundary
Scan
Function
06
Data Out
05
31
Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain. This output is
Output Enable Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
Data In
EN_EXT_SEL
REV_SEL0
30
Data In
29
Data In
REV_SEL1
12
Data In
BUSY
08
07
CLKOUT
Enable External Selection Input. When this pin is Low, design
revision selection is controlled by the Revision Select pins.
When this pin is High, design revision selection is controlled
by the internal programmable Revision Select control bits.
EN_EXT_SEL has an internal 50KΩ resistive pull-up to VCCO
to provide a logic 1 to the device if the pin is not driven.
Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low,
the Revision Select pins are used to select the design
revision to be enabled, overriding the internal programmable
Revision Select control bits. The Revision Select[1:0] inputs
have an internal 50 KΩ resistive pull-up to VCCO to provide a
logic 1 to the device if the pins are not driven.
Data Out
Mode Select
TMS
Clock
TCK
Data In
TDI
Data Out
DS123 (v2.9) May 09, 2006
Pin Description
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40
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Platform Flash In-System Programmable Configuration PROMS
Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Continued)
Pin Description
48-pin
TSOP
(VO48/
VOG48)
48-pin
TFBGA
(FS48/
FSG48)
VCCO
+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the output voltage drivers and
input buffers.
8, 30,
38, 45
B2, C6,
D6, G5
VCCJ
+3.3V or 2.5V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the TDO output voltage driver
and TCK, TMS, and TDI input buffers.
24
H2
GND
Ground
2, 7,
A1, A2,
17, 23,
B6, F1,
31, 36, 46 F5, F6, H1
Do Not Connect. (These pins must be left unconnected.)
1, 3,
14, 16,
18, 35, 37,
39, 40, 41,
42
Pin Name
Boundary
Scan Order
Boundary
Scan
Function
DNC
A4, C3,
C4, D3,
D4, E3,
E4, F2,
F3, F4,
G2
XCFxxP VO48/VOG48 Pinout Diagram
DNC
GND
DNC
VCCINT
BUSY
CF
GND
VCCO
CLKOUT
CEO
OE/RESET
CLK
CE
DNC
VCCINT
DNC
GND
DNC
TDI
TCK
TMS
TDO
GND
VCCJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VO48/VOG48
Top
View
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D7
D6
GND
VCCO
D5
D4
DNC
DNC
DNC
DNC
VCCO
DNC
GND
DNC
VCCINT
D3
D2
GND
VCCO
D1
D0
REV_SEL1
REV_SEL0
EN_EXT_SEL
ds123_24_070505
Figure 16: VO48/VOG48 Pinout Diagram (Top View) with Pin Names
DS123 (v2.9) May 09, 2006
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Platform Flash In-System Programmable Configuration PROMS
XCFxxP FS48/FSG48 Pin Names
XCFxxP FS48/FSG48 Pinout Diagram
Table 15: XCFxxP Pin Names (FS48/FSG48)
Pin
Number
Pin Name
Pin
Number
Pin Name
A1
GND
E1
VCCINT
A2
GND
E2
TMS
A3
OE/RESET
E3
DNC
A
A4
DNC
E4
DNC
B
A5
D6
E5
D2
C
A6
D7
E6
TDO
B1
VCCINT
F1
GND
B2
VCCO
F2
DNC
B3
CLK
F3
DNC
B4
CE
F4
DNC
B5
D5
F5
GND
B6
GND
F6
GND
C1
BUSY
G1
TDI
C2
CLKOUT
G2
DNC
C3
DNC
G3
REV_SEL0
C4
DNC
G4
REV_SEL1
C5
D4
G5
VCCO
C6
VCCO
G6
VCCINT
D1
CF
H1
GND
D2
CEO
H2
VCCJ
D3
DNC
H3
TCK
D4
DNC
H4
EN_EXT_SEL
D5
D3
H5
D1
D6
VCCO
H6
D0
FS48/FSG48
Top View
1
2
3
4
5
6
D
E
F
G
H
ds121_01_071604
DS123 (v2.9) May 09, 2006
Figure 17: FS48/FSG48 Pinout Diagram (Top View)
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Platform Flash In-System Programmable Configuration PROMS
Ordering Information
XCF04S VO20 C
Device Number
XCF01S
XCF02S
XCF04S
Operating Range/Processing
C = (TA = –40°C to +85°C)
Package Type
VO20 = 20-pin TSSOP Package
VOG20 = 20-pin TSSOP Package, Pb-free
XCF32P FS48 C
Device Number
XCF08P
XCF16P
XCF32P
Operating Range/Processing
C = (TA = –40°C to +85°C)
Package Type
VO48 = 48-pin TSOP Package
VOG48 = 48-pin TSOP Package, Pb-free
FS48 = 48-pin TFBGA Package
FSG48 = 48-pin TFBGA Package, Pb-free
Valid Ordering Combinations
XCF01SVO20 C
XCF08PVO48 C
XCF08PFS48 C
XCF01SVOG20 C
XCF08PVOG48 C
XCF08PFSG48 C
XCF02SVO20 C
XCF16PVO48 C
XCF16PFS48 C
XCF02SVOG20 C
XCF16PVOG48 C
XCF16PFSG48 C
XCF04SVO20 C
XCF32PVO48 C
XCF32PFS48 C
XCF04SVOG20 C
XCF32PVOG48 C
XCF32PFSG48 C
Marking Information
XCF04S-V
Device Number
XCF01S
XCF02S
XCF04S
XCF08P
XCF16P
XCF32P
DS123 (v2.9) May 09, 2006
Operating Range/Processing
C = (TA = –40°C to +85°C)
Package Type
V = 20-pin TSSOP Package (VO20)
VG = 20-pin TSSOP Package, Pb-free (VOG20)
VO48 = 48-pin TSOP Package (VO48)
VOG48 = 48-pin TSOP Package, Pb-free (VOG48)
F48 = 48-pin TFBGA Package (FS48)
FG48 = 48-pin TFBGA Package, Pb-free (FSG48)
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Platform Flash In-System Programmable Configuration PROMS
Revision History
The following table shows the revision history for this document.
Date
Version
04/29/03
1.0
Xilinx Initial Release.
06/03/03
1.1
Made edits to all pages.
11/05/03
2.0
Major revision.
11/18/03
2.1
Pinout corrections as follows:
• Table 14:
♦ For VO48 package, removed 38 from VCCINT and added it to VCCO.
♦ For FS48 package, removed pin D6 from VCCINT and added it to VCCO.
• Table 15 (FS48 package):
♦ For pin D6, changed name from VCCINT to VCCO.
♦ For pin A4, changed name from GND to DNC.
• Figure 16 (VO48 package): For pin 38, changed name from VCCINT to VCCO.
12/15/03
2.2
• Added specification (4.7kΩ) for recommended pull-up resistor on OE/RESET pin to section
"Reset and Power-On Reset Activation," page 22.
• Added paragraph to section "Standby Mode," page 22, concerning use of a pull-up resistor
and/or buffer on the DONE pin.
05/07/04
2.3
• Section "Features," page 1: Added package styles and 33 MHz configuration speed limit to
itemized features.
• Section "Description," page 1 and following: Added state conditions for CF and BUSY to the
descriptive text.
• Table 2, page 3: Updated Virtex-II configuration bitstream sizes.
• Section "Design Revisioning," page 9: Rewritten.
• Section "PROM to FPGA Configuration Mode and Connections Summary," page 10 and
following, five instances: Added instruction to tie CF High if it is not tied to the FPGA’s PROG_B
(PROGRAM) input.
• Figure 6, page 14, through Figure 13, page 21: Added footnote indicating the directionality of the
CF pin in each configuration.
• Section "I/O Input Voltage Tolerance and Power Sequencing," page 22: Rewritten.
• Table 12, page 23: Added CF column to truth table, and added an additional row to document
the Low state of CF.
• Section "Absolute Maximum Ratings," page 24: Revised VIN and VTS for ’P’ devices.
• Section "Supply Voltage Requirements for Power-On Reset and Power-Down," page 24:
♦ Revised footnote callout number on TOER from Footnote (4) to Footnote (3).
♦ Added Footnote (2) callout to TVCC.
• Section "Recommended Operating Conditions," page 25:
♦ Added Typical (Typ) parameter columns and parameters for VCCINT and VCCO/VCCJ.
♦ Added 1.5V operation parameter row to VIL and VIH, ’P’ devices.
♦ Revised VIH Min, 2.5V operation, from 2.0V to 1.7V.
♦ Added parameter row TIN and Max parameters
• (Continued on next page)
05/07/04
(cont’d)
2.3
(cont’d)
• Section "DC Characteristics Over Operating Conditions," page 26:
♦ Added parameter row and parameters for parallel configuration mode, ’P’ devices, to ICCO .
♦ Added Footnote (1) and Footnote (2) with callouts in the Test Conditions column for ICCJ,
ICCINTS, ICCOS, and ICCJS, to define active and standby mode requirements.
• Section "AC Characteristics Over Operating Conditions," page 27:
♦ Corrected description for second TCAC parameter line to show parameters for 1.8V VCCO .
♦ Revised Footnote (7) to indicate VCCO = 3.3V.
♦ Applied Footnote (7) to second TCYC parameter line.
• Section "AC Characteristics Over Operating Conditions When Cascading," page 36: Revised
Footnote (5)TCYC Min and TCAC Min formulas.
• Table 14, page 39:
♦ Added additional state conditions to CLK description.
♦ Added function of resetting the internal address counter to CF description.
DS123 (v2.9) May 09, 2006
Revision
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Platform Flash In-System Programmable Configuration PROMS
07/20/04
2.4
• Added Pb-free package options VOG20, FSG48, and VOG48.
• Figure 6, page 14, and Figure 7, page 15: Corrected connection name for FPGA DOUT
(OPTIONAL Daisy-chained Slave FPGAs with different configurations) from DOUT to DIN.
• Section "Absolute Maximum Ratings," page 24: Removed parameter TSOL from table. (TSOL
information can be found in Package User Guide.)
• Table 2, page 3: Removed reference to XC2VP125 FPGA.
10/18/04
2.5
•
•
•
•
•
03/14/05
2.6
•
•
•
•
•
•
•
07/11/05
2.7
• Move from "Preliminary" to "Product Specification"
• Corrections to Virtex-4 configuration bitstream values
• Minor changes to Figure 7, page 15, Figure 12, page 20, Figure 13, page 21, and Figure 16,
page 41
• Change to "Internal Oscillator," page 8 description
• Change to "CLKOUT," page 8 description
DS123 (v2.9) May 09, 2006
Table 1, page 1: Broke out VCCO / VCCJ into two separate columns.
Table 9, page 7: Added clarification of ID code die revision bits.
Table 10, page 8: Deleted TCKMIN2 (bypass mode) and renamed TCKMIN1 to TCKMIN.
Table "Recommended Operating Conditions," page 25: Separated VCCO and VCCJ parameters.
Table "DC Characteristics Over Operating Conditions," page 26:
♦ Added most parameter values for XCF08P, XCF16P, XCF32P devices.
♦ Added Footnote (1) to ICCO specifying no-load conditions.
• Table "AC Characteristics Over Operating Conditions," page 27:
♦ Added most parameter values for XCF08P, XCF16P, XCF32P devices.
♦ Expanded Footnote (1) to include XCF08P, XCF16P, XCF32P devices.
♦ Added Footnote (8) through (11) relating to CLKOUT conditions for various parameters.
♦ Added rows to TCYC specifying parameters for parallel mode.
♦ Added rows specifying parameters with decompression for TCLKO, TCOH, TFF, TSF.
♦ Added TDDC (setup time with decompression).
• Table "AC Characteristics Over Operating Conditions When Cascading," page 36:
♦ Added most parameter values for XCF08P, XCF16P, XCF32P devices.
♦ Separated Footnote (5) into Footnotes (5) and (6) to specify different derivations of TCYC,
depending on whether dual-purpose configuration pins persist as configuration pins, or
become general I/O pins after configuration.
Added Virtex-4 LX/FX/SX configuration data to Table 2.
Corrected Virtex-II configuration data in Table 2.
Corrected Virtex-II Pro configuration data in Table 2.
Added Spartan-3L configuration data to Table 2.
Added Spartan-3E configuration data to Table 2.
Paragraph added to FPGA Master SelectMAP (Parallel) Mode (1), Page 11.
Changes to DC Characteristics
♦ TOER changed, Page 26.
♦ IOL changed for VOL, Page 26.
♦ VCCO added to test conditions for IIL, IILP, IIHP,and IIH, Page 26. Values modified for IILP and
IIHP.
• Changes to AC Characteristics
♦ TLC and THC modified for 1.8V, Page 31.
♦ New rows added for TCEC and TOEC, Page 30.
• Minor changes to grammar and punctuation.
• Added explanation of "Preliminary" to DC and AC Electrical Characteristics.
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Platform Flash In-System Programmable Configuration PROMS
12/29/05
2.8
• Update to the first paragraph of "IEEE 1149.1 Boundary-Scan (JTAG)," page 5.
• Added JTAG cautionary note to Page 5.
• Corrected logic values for Erase/Program (ER/PROG) Status field, IR[4], listed under "XCFxxP
Instruction Register (16 bits wide)," page 6.
• Sections "XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock
Source," page 27, "XCFxxP PROM as Configuration Master with CLK Input Pin as Clock
Source," page 30 and "XCFxxP PROM as Configuration Master with Internal Oscillator as Clock
Source," page 33 added to "AC Characteristics Over Operating Conditions," page 27.
• Notes for Figure 6, page 14, Figure 7, page 15, Figure 8, page 16, Figure 9, page 17, Figure 10,
page 18, Figure 11, page 19, Figure 12, page 20, and Figure 13, page 21 updated to specify the
need for a pull-up resistor if CF is not connected to PROGB.
• Enhanced description under section "CLKOUT," page 8.
• Enhanced description on design revision sampling under section "Design Revisioning," page 9.
• Figure 4 and Figure 5 renamed to Table 7, page 6 and Table 8, page 6 respectively. All tables,
figures, and table and figure references renumber this point forward.
• Value for "ICCINT," page 26 updated from 5mA to 1mA for XCFxxP.
• Block diagram in Figure 2, page 2 updated to show clock source muxing and route clocking to all
functional blocks.
05/09/06
2.9
• Added Virtex-5 LX support to Table 2, page 3.
• "VIL" maximum for 2.5V operation in "Recommended Operating Conditions," page 25 updated
to match LVCMOS25 standard.
DS123 (v2.9) May 09, 2006
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