SILAN SC74HC595D

SC74HC595
8-BIT SHIFT REGISTER (SERIAL INPUT, 3S PARALLEL OUTPUT WITH
LATCHES)
DESCRIPTION
SC74HC595 utilizes advanced CMOS technology, and has
8-bit shift register with serial input, serial/parallel output and 8bit tri-state output flip-latch. The pin configuration is in accord
SOP-16-300-1.27
SOP-16-225-1.27
with the 54LS/74LS series, and the operating speed is similar
to 54LS/74LS. This circuit has the protecting circuit for all the
inputs and outputs to avoid the damage caused by the static
SSOP-16-300-0.65
discharge. And it has the ability of driving load and features
high noise immunity.
The register and flip-latch both have separate clock inputs
(SCK and RCK). The serial input data (IS) is stored into
register at the rising edge of SCK; the data of register is stored
DIP-16-300-2.54 TSSOP-16-225-0.65
into flip-latch at the rising edge of RCK. The low level of clear
port ( SCLR ) only reset the register, and is no effect to fliplatch. When the control enable ( G ) is high level, the parallel-
ORDERING INFORMATION
out is level Z.
FEATURES
Device
Package
SC74HC595
DIP-16-300-2.54
* Wide operating voltage range
2~6V
SC74HC595A
SOP-16-225-1.27
* Low input current
1µA
SC74HC595B
SOP-16-300-1.27
SC74HC595C
TSSOP-16-225-0.65
SC74HC595D
SSOP-16-300-0.65
* High output driving ability
15 LS-TTL loads
* High operating speed(Typical)
fmax=55MHz (VCC=5V)
* Low supply current
80µA
APPLICATIONS
* LED screen
RECOMANDED OPERATING CONDITIONS
Characteristics
Symbol
Ratings
Unit
Power Supply Voltage
VCC
2~6
V
Input Voltage
VIN
0~VCC
V
Output Voltage
VOUT
0~VCC
V
Operating Temperature
Topr
-40~+85
°C
Input Rise and Fall Time
Tr, Tf
VCC =2.0V
0~1000
ns
VCC =4.5V
0~500
ns
VCC =6.0V
0~400
ns
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Page 1 of 13
SC74HC595
DC ELECTRICAL CHARACTERISTICS (Tamb=25°C)
Characteristics
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage ( OH’
)
Symbol
VIH
VIL
Testing conditions
Min.
Typ.
Max.
2.0
1.5
--
--
4.5
3.15
--
--
6.0
4.2
--
2.0
--
--
0.5
4.5
--
--
1.35
6.0
--
--
1.8
2.0
1.9
2.0
--
4.4
4.5
--
5.9
6.0
--
VCC(V)
Conditions
IO=-20µA
4.5
VOH
6.0
VIN=VIH or VIL
4.5
IO=-4.0mA
4.18
4.31
--
6.0
IO=-5.2mA
5.68
5.8
--
1.9
2.0
--
2.0
High Level Output
Voltage (QA~QH)
IO=-20µA
4.5
VOH
6.0
VIN=VIH or VIL
Voltage (OH’
)
4.18
4.31
--
6.0
IO=-7.8mA
5.68
5.8
--
--
0.0
0.1
--
0.0
0.1
--
0.0
0.1
IO=20µA
6.0
VIN=VIH or VIL
4.5
IO=4.0mA
--
0.17
0.26
6.0
IO=5.2mA
--
0.18
0.26
--
0.0
0.1
--
0.0
0.1
--
0.0
0.1
2.0
Low Level Output
Voltage (QA~QH)
Input Leakage Current
Tri-state Output
Current
Quiescent Supply
Current
IO=20µA
4.5
VOL
---
IO=-6.0mA
4.5
VOL
4.5
6.0
4.5
2.0
Low Level Output
4.4
5.9
6.0
VIN=VIH or VIL
Unit
V
V
V
V
V
V
4.5
IO=6.0mA
--
0.17
0.26
6.0
IO=7.8mA
--
0.18
0.26
--
--
±0.1
µA
--
--
±0.5
µA
-
--
4
µA
II
6.0
IOZ
6.0
ICC
6.0
VIN=VCC or GND
VIN=VIH
or
VIL
VOUT=VCC or GND
VIN=VCC or GND
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Page 2 of 13
SC74HC595
DC ELECTRICAL CHARACTERISTICS (Tamb=-40~85°C)
Characteristics
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage ( OH’
)
Symbol
VIH
VIL
Testing conditions
Min.
Typ.
Max.
2.0
1.5
--
--
4.5
3.15
--
--
6.0
4.2
--
--
2.0
--
--
0.5
4.5
--
--
1.35
6.0
--
--
1.8
2.0
1.9
--
--
4.4
--
--
5.9
--
--
VCC(V)
Conditions
IO=-20µA
4.5
VOH
6.0
VIN=VIH or VIL
4.5
IO=-4.0mA
4.13
--
--
6.0
IO=-5.2mA
5.63
--
--
1.9
--
--
2.0
High Level Output
Voltage (QA~QH)
IO=-20µA
4.5
VOH
6.0
VIN=VIH or VIL
Voltage (OH’
)
4.13
--
--
6.0
IO=-7.8mA
5.63
--
--
--
--
0.1
--
--
0.1
--
--
0.1
IO=20µA
6.0
VIN=VIH or VIL
4.5
IO=4.0mA
--
--
0.33
6.0
IO=5.2mA
--
--
0.33
--
--
0.1
--
--
0.1
--
--
0.1
2.0
Low Level Output
Voltage (QA~QH)
Input Leakage Current
Tri-state Output
Current
Quiescent Supply
Current
IO=20µA
4.5
VOL
---
IO=-6.0mA
4.5
VOL
---
4.5
2.0
Low Level Output
4.4
5.9
6.0
VIN=VIH or VIL
Unit
V
V
V
V
V
V
4.5
IO=6.0mA
--
--
0.33
6.0
IO=7.8mA
--
--
0.33
--
--
±0.1
µA
--
--
±0.5
µA
--
--
4
µA
II
6.0
IOZ
6.0
ICC
6.0
VIN=VCC or GND
VIN= VIH or VIL
VOUT=VCC or GND
VIN=VCC or GND
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Page 3 of 13
SC74HC595
AC ELECTRICAL CHARACTERISTICS(CL=50pF INPUT Tr=Tf=6ns Tamb=25°C)
Characteristics
Symbol
Testing conditions
Min.
Typ.
Max.
--
25
60
--
7
12
6.0
--
6
10
2.0
--
30
75
--
8
15
6.0
--
7
13
2.0
--
45
125
--
15
25
6.0
--
13
21
2.0
--
60
175
--
18
35
6.0
--
15
30
2.0
--
60
150
--
20
30
VCC(V)
CL(pF)
2.0
Output Transition Time (Qn)
Output Transition Time (QH’
)
tTLH
tTHL
tTLH
tTHL
Propagation Delay Time(SCK-
tPLH
QH’
)
tPHL
Propagation Delay Time
tPLH
(SCLR-QH’
)
tPHL
4.5
4.5
4.5
4.5
4.5
50
50
50
50
50
Propagation Delay Time (RCK-
tPLH
6.0
--
17
26
QN)
tPHL
2.0
--
75
190
--
25
38
6.0
--
22
32
2.0
--
45
135
--
15
27
4.5
4.5
Tri-state Output Enable Time
RL=1kΩ
6.0
--
13
23
tPZH
2.0
--
60
175
--
20
35
6.0
--
17
30
2.0
--
30
150
4.5
--
15
30
6.0
--
14
26
2.0
6.0
17
--
tPLZ
tPHZ
4.5
Maximum Clock
50
tPZL
4.5
Tri-state Output Disable Time
150
fMAX
150
50
50
RL=1kΩ
RL=1kΩ
30
50
--
6.0
35
59
--
2.0
5.2
14
--
26
40
--
31
45
--
4.5
150
6.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(To be continued)
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SC74HC595
(Continued)
Characteristics
Symbol
Testing conditions
Min.
Typ.
Max.
--
17
75
--
6
15
6.0
--
6
13
2.0
--
20
75
--
6
15
6.0
--
6
13
2.0
--
25
50
--
5
10
6.0
--
4
9
2.0
--
35
75
--
8
15
6.0
--
6
13
2.0
--
40
100
--
10
20
6.0
--
7
17
2.0
--
--
0
--
--
0
6.0
--
--
0
2.0
--
15
50
--
3
10
--
3
9
CIN
--
5
10
CPD(*)
--
184
VCC(V)
CL(pF)
2.0
Minimum Pulse Width
(SCK, RCK)
Minimum Pulse Width
( SCLR )
Minimum Set-up Time
(SI-SCK)
Minimum Set-up Time
(SCK-RCK)
Minimum Set-up Time
( SCLR -RCK)
Minimum Hold Time
Minimum Clear Time
tW(H)
tW(L)
tS
tS
tS
tH
tREM
4.5
4.5
4.5
4.5
4.5
4.5
4.5
50
50
50
50
50
50
50
6.0
Input Capacitance
Power Dissipation Capacitance
Unit
ns
ns
ns
ns
ns
ns
ns
pF
pF
(*): CPD is defined as the internal equivalent capacitance of the IC. It is calculated from the operating current
without load; and the average operating current can be obtained by the equation: I CC (opr) =CPD*VCC*fIN+ICC.
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Page 5 of 13
SC74HC595
AC ELECTRICAL CHARACTERISTICS(CL=50pF INPUT Tr=Tf=6ns Tamb=-40~85°C)
Characteristics
Symbol
Testing conditions
Min.
Typ.
Max.
--
--
75
--
--
15
6.0
--
--
13
2.0
--
--
95
--
--
19
6.0
--
--
16
2.0
--
--
155
--
--
31
6.0
--
--
66
2.0
--
--
220
--
--
44
6.0
--
--
37
2.0
--
--
190
--
--
38
VCC(V)
CL(pF)
2.0
Output Transition Time (Qn)
Output Transition Time (QH’
)
tTLH
tTHL
tTLH
tTHL
Propagation Delay Time (SCK-
tPLH
QH’
)
tPHL
Propagation Delay Time
tPLH
(SCLR-QH’
)
tPHL
4.5
4.5
4.5
4.5
4.5
50
50
50
50
50
Propagation Delay Time (RCK-
tPLH
6.0
--
--
32
QN)
tPHL
2.0
--
--
240
--
--
48
6.0
--
--
41
2.0
--
--
170
--
--
34
4.5
4.5
Tri-state Output Enable Time
RL=1kΩ
6.0
--
--
29
tPZH
2.0
--
--
220
--
--
44
6.0
--
--
37
2.0
--
--
190
4.5
--
--
38
6.0
--
--
32
2.0
4.8
--
--
24
--
--
6.0
28
--
--
2.0
4.2
--
--
21
--
--
25
--
--
tPLZ
tPHZ
4.5
Maximum Clock
50
tPZL
4.5
Tri-state Output Disable Time
150
fMAX
4.5
150
50
50
150
6.0
RL=1kΩ
RL=1kΩ
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(To be continued)
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Page 6 of 13
SC74HC595
(Continued)
Characteristics
Symbol
Testing conditions
Min.
Typ.
Max.
--
--
95
--
--
19
6.0
--
--
16
2.0
--
--
95
--
--
19
6.0
--
--
16
2.0
--
--
65
--
--
13
6.0
--
--
11
2.0
--
--
95
--
--
19
6.0
--
--
16
2.0
--
--
125
--
--
25
6.0
--
--
21
2.0
--
--
0
--
--
0
6.0
--
--
0
2.0
--
--
65
--
--
13
--
--
11
CIN
--
--
10
pF
CPD(*)
--
--
--
pF
VCC(V)
CL(pF)
2.0
Minimum Pulse Width
(SCK, RCK)
Minimum Pulse Width
( SCLR )
Minimum Set-up Time
(SI-RCK)
Minimum Set-up Time
(SCK-RCK)
Minimum Set-up Time
( SCLR -RCK)
Minimum Hold Time
Minimum Clear Time
tW(H)
tW(L)
tS
tS
tS
tH
tREM
4.5
4.5
4.5
4.5
4.5
4.5
4.5
50
50
50
50
50
50
50
6.0
Input Capacitance
Power Dissipation Capacitance
Unit
ns
ns
ns
ns
ns
ns
ns
(*): CPD is defined as the internal equivalent capacitance of the IC. It is calculated from the operating current
without load; and the average operating current can be obtained by the equation: I CC (opr) =CPD*VCC*fIN+ICC.
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Page 7 of 13
SC74HC595
PIN CONFIGURATION
PIN DESCRIPTION
Pin no.
Name
I/O
1~7, 15
QA ~ QH
O
Parallel data output
Pin description
9
QH’
O
Serial data output
10
SCLR
I
Reset signal of register
11
SCK
I
Register clock
13
G
I
Data output enable
14
SI
I
Serial data input
12
RCK
I
Flip-latch clock
8
GND
I/O
Ground
16
VCC
I/O
Power supply
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SC74HC595
LOGIC DIAGRAM
Serial input SI
SCK
SCLR
RCK
G
14
11
3 state shift register
9
Serial output
OH’
10
12
13
8-bit storage register
3 state buffer
VCC =16
GND=8
QA QB QC QD QE QF QG QH
Parallel output ports
TIMING CHART
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SC74HC595
TRUTH TABLE
Input
Output
SI
SCK
SCLR
RCK
G
X
X
X
X
H
QA ~QH outputs disable
X
X
X
X
L
QA ~QH outputs enable
X
X
L
X
X
Register reset
X
H
X
X
Storage the data into register at the rising edge of SCK
X
H
X
X
The state of register is unchangeable
X
X
X
X
Storage the data into flip-latch at the rising edge of RCK
X
X
X
X
The state of flip-latch is unchangeable
X: irrelevant
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SC74HC595
PACKAGE OUTLINE
DIP-16-300-2.54
UNIT: mm
SOP-16-225-1.27
UNIT: mm
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REV:1.0
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Page 11 of 13
SC74HC595
PACKAGE OUTLINE
TSSOP-16-225-0.65
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
7.62
5.30±0.30
UNIT: mm
7.80±0.40
SOP-16-300-1.27
UNIT: mm
REV:1.0
2006.04.19
Page 12 of 13
SC74HC595
PACKAGE OUTLINE
SSOP-16-300-0.65
UNIT: mm
0
8°
0.18±0.015
0.33
0.65
6.15±0.20
1.65±0.20
0.15±0.05
HANDLING MOS DEVICES:
Electrostatic charges can exist in many things. All of our MOS devices are internally protected against
electrostatic discharge but they can be damaged if the following precautions are not taken:
• Persons at a work bench should be earthed via a wrist strap.
• Equipment cases should be earthed.
• All tools used during assembly, including soldering tools and solder baths, must be earthed.
• MOS devices should be packed for dispatch in antistatic/conductive containers.
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2006.04.19
Page 13 of 13