SC2596 Low Voltage Integrated DDR Termination Regulator POWER MANAGEMENT Description Features The SC2596 is an integrated linear DDR termination device, which provides a complete solution for DDR termination regulator designs; while meeting the JEDEC requirements of SSTL-2 and SSTL-18 specifications for DDR-SDRAM termination. The SC2596 regulates up to +/- 2.5A for DDR-I and +/1.5A for DDR-II application requirements. VTT is regulated to track the VREF voltage over the entire current range with shoot through protection. A V SENSE pin is incorporated to provide excellent load regulation, along with a buffered reference voltage for internal use. Sourcing or sinking 2.5A for DDR-I Sourcing or sinking 1.5A for DDR-II AVCC undervoltage lockout Reference output Minimum number of external components Accurate internal voltage divider Disable function, puts device into sleep mode Thermal shutdown Over current protection Available in SOIC-8 EDP package WEEE and RoHS compliant Applications The SC2596 also features a disable function which is to tri-state the output during Suspend To Ram (STR) states by pulling the EN pin low. DDR-I and DDR-II memory termination SSTL-2 and SSTL-3 termination HSTL termination PC motherboards Graphics boards Disk drives CD-ROM drives Typical Application Circuit VDDQ SC2596 EN VDDQ VSENSE PVCC VREF GND EN AVCC AVCC VTT VTT VREF 0 Revision: July 18, 2007 1 www.semtech.com SC2596 POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. P a r a m et er Symb ol M a xi m u m Un i ts PVCC, AVCC, VDDQ to GND VCC -0.3 to +6.0 V Maximum Junction Temperature Range TJ -40 to +125 O C Storage Temperature Range TSTG -65 to +150 O C Peak IR Reflow Temperature 10-40S T PKG 260 O C ESD Rating (Human Body Model) ESD 2 kV Electrical Characteristics (DDR-I) Unless otherwise specified: TJ = -40oC to +125oC, AVCC = PVCC = 2.5V, VDDQ = 2.5V. S y m b ol Te s t C o n d i t i o n s Min Ty p M ax Units Reference Voltage V REF IREF_OUT = 0mA 0.49VDDQ 0.5VDDQ 0.51VDDQ V VREF Output Impedance ZVREF IREF = -30uA to +30uA (VTT - VREF) IOUT = 0A IOUT = -1.5A IOUT = +1.5A IQ ILOAD = 0A P ar am et er V TT Output Regulation (1) Quiescent Current -25 AVCC Enable Threshold VDDQ Input Impedance Quiescent Current in Shutdown ZVDDQ EN = 0 EN Pin Leakage Current IQ_SD EN = 0 EN Threshold Voltage VH VL 2007 Semtech Corp. IV TT_L 0 +25 mV 400 700 uA 2.1 2.2 V 100 ISD V TT Leakage Current in Shutdown Ω 230 150 kΩ 250 uA 1 uA 2 V 0.8 SD = 0V, V TT = 1.25V, at 25 OC 2 6 uA www.semtech.com SC2596 POWER MANAGEMENT Electrical Characteristics (DDR-I Cont.) Unless otherwise specified: TJ = -40oC to +125oC, AVCC = PVCC = 2.5V, VDDQ = 2.5V. P ar am et er S y m b ol VSEN SE Current Thermal Shutdown Thermal Shutdown Hysteresis Te s t C o n d i t i o n s Min Ty p M ax Units ISENSE 50 200 nA TSD 160 O TSD_HYS 10 O C C Note: (1) Regulation is measured by using a load current pulse. (Pulse Width less than 10mS, Duty Cycle less than 2%, TA = 25 oC) Electrical Characteristics (DDR-II) Unless otherwise specified: TJ = -40oC to +125oC, AVCC = 3.3V, PVCC = VDDQ = 1.8V. S y m b ol Te s t C o n d i t i o n s Min Ty p M ax Units Reference Voltage V REF IREF_OUT = 0mA 0.49VDDQ 0.5VDDQ 0.51VDDQ V VREF Outp ut Impedance ZVREF IREF = -30uA to +30uA (VTT - VREF) IOUT = 0A IOUT = -1.0A IOUT = +1.0A IQ ILOAD = 0A P ar am et er V TT Outp ut Regulation (1) Quiescent Current -25 AVCC Enable Threshold VDDQ Inp ut Impedance ZVDDQ 0 +25 mV 400 700 uA 2.1 2.2 V 100 ISD EN = 0 150 EN Pin Leakage Current IQ_SD EN = 0 0.5 EN Threshold Voltage VH VL Quiescent Current in Shutdown Ω 230 kΩ 250 uA uA 2 V 0.8 V TT Leakage Current in Shutdown IV TT_L VSEN SE Current ISENSE 50 TSD 160 O TSD_HYS 10 O Thermal Shutdown Thermal Shutdown Hysteresis SD = 0V, V TT = 0.9V, at 25 OC 6 uA 200 nA C C Note: (1) Regulation is measured by using a load current pulse. (Pulse Width less than 10mS, Duty Cycle less than 2%, TA = 25 oC) 2007 Semtech Corp. 3 www.semtech.com SC2596 POWER MANAGEMENT PRELIMINARY Waveforms AVCC AVCC VDDQ//PVCC VDDQ//PVCC Vref VREF VTT VTT Start up. Shut down. AVCC AVCC PVCC PVCC EN EN VTT VTT Shut down by EN. Start up by EN. AVCC PVCC//VDDQ AVCC PVCC VTT VTT IO IO 1A load 2007 Semtech Corp. Transient with +/- 1A load 4 www.semtech.com SC2596 POWER MANAGEMENT Waveforms 4.0 Output Current (A) Output Current (A) 4.0 3.5 3.0 2.5 3.5 3.0 2.5 2.0 2.0 2 2.5 3 3.5 4 4.5 5 2 5.5 2.5 3 4 4.5 5 5.5 5 5.5 AVCC (V) AVCC (V) Maximum Sourcing Current vs AVCC. (VDDQ=1.8V, PVCC=2.5V) Maximum Sinking Current vs AVCC. (VDDQ=1.8V, PVCC=2.5V) 3.0 4.0 Output Current (A) Output Current (A) 3.5 2.5 2.0 1.5 3.5 3.0 2.5 2.0 1.0 2 2.5 3 3.5 4 4.5 5 2 5.5 3 3.5 4 4.5 AVCC(V) AVCC(V) Maximum Sinking Current vs AVCC. (VDDQ=1.8V, PVCC=1.8V) Maximum Sourcing Current vs AVCC. (VDDQ=1.8V, PVCC=1.8V) 2007 Semtech Corp. 2.5 5 www.semtech.com SC2596 POWER MANAGEMENT Pin Configuration PRELIMINARY Ordering Information TOP VIEW P ar t N u m b er P a c k a g e ( 3) Te m p . R a n g e ( T A ) SC2596SETRT(1) SOIC-8L EDP -40 to +105 OC SC2596EVB (2) GND 1 8 VTT EN 2 7 PVCC VSENSE 3 6 AVCC VREF 4 5 VDDQ Evaluation Board Notes: (1)Only available in tape and reel packaging. A reel contains 2500 devices for EDP SOIC-8. (2) EVB provided with EDP SOIC-8 package. (3) Lead free product. This product is fully WEEE and RoHS compliant. (SOIC-8L-EDP) 2007 Semtech Corp. 6 www.semtech.com SC2596 POWER MANAGEMENT Pin Descriptions Pin # P i n N am e 1 GN D 2 EN 3 VSEN SE VSEN SE p in is a feedback p in. Connect a 10nF to 100nF Ceramic cap acitor between this p in to ground and p lace this cap acitor close to VSEN SE p in is required to avoid oscillation during transient condition. 4 V REF VREF p in is an outp ut p in, which p rovides the buffered outp ut of the internal reference voltage. A 100nF ceramic cap acitor should be connected from VREF p in to ground with shor t trace. 5 VDDQ The VDDQ p in is an inp ut p in for creating internal reference voltage to regulate V TT. The VDDQ voltage is connected to an internal resistor divider. The central tap of resistor divider (VDDQ/2) is connected to the internal voltage buffer, which outp ut is connected to VREF p in and the non-inver ting inp ut of the error amp lifier as the reference voltage. With the feedback loop closed, the V TT outp ut voltage will always track the VDDQ/2 p recisely. It is recommended that a 1uF ceramic cap acitor should be added next to the VDDQ p in to ground to increase the noise immunity. 6 AVCC The AVCC p in is used to sup p ly all of the internal control circuitry. The AVCC voltage has to be greater than its UVLO threshold voltage (2.1V typ ical) to allow the SC2596 to be in normal op eration. If AVCC voltage is lower than the UVLO threshold voltage, the V TT p in should be in high imp edance status. 7 PVCC The PVCC p in p rovides the rail voltage from where the V TT p in draws load current. There is a limitation between AVCC and PVCC. The PVCC voltage must be less or equal to AVCC voltage to ensure the correct outp ut voltage regulation. The V TT source current cap ability is dep endent on PVCC voltage. Higher the voltage on PVCC, higher the source current. 8 V TT The V TT p in is the outp ut of SC2596. It can sink and source continuous current while keep ing excellent load regulation. It is recommended that one should use at least one 220uF low ESR cap acitor and a 1uF ceramic cap acitor or on e 220u F h i gh ESR electrol y ti c cap aci tor an d a 6.8u F cerami c cap aci tor, which are p laced on the V TT strip p lane to ground reducing the voltage sp ike under load transient condition. THERMAL PAD Pad for heatsinking p urp oses. Connect to ground p lane using multip le vias. N ot connected internally. 2007 Semtech Corp. P i n Fu n c t i o n Ground. Enable p in. SC2596 is disabled when EN p in is low. 7 www.semtech.com SC2596 POWER MANAGEMENT Block Diagram PRELIMINARY EN AVCC PVCC UVLO + Thermal Shutdown VDDQ - + + - Vref Buffer AntiShootthru + Driver Circuit VTT Error Am p. GND VREF Vsense Description ERROR AMP SC2596 is a low-voltage, low-dropout DDR termination regulator with separate power supply to support both DDR1 and DDR2 applications. AVCC and PVCC can be tied together for DDR1 and can also be separated for DDR2. Low input offset op-amp for the main linear regulator. It controls the VTT output voltage and which side of the MOSFET to turn on (or turn off) to achieve zero shoot through current. ANTI-Shoot Thought Driver SC2596 regulates VTT to the voltage of VREF. VTT will sink or source upto 2.5A. Internal shoot-through protection ensure both top and bottom MOSFET will not conduct while maintaining fast source-to-sink load transient. Thermal shut-down and internal current limit protect SC2596 from shorted load or over-heated Buffer stage takes the error voltage to control MOSFET. Internal current limit is incorporated to protect from shorted load. THERMAL SHUTDOWN & UVLO VREF BUFF The Thermal shutdown block prevent the junction temperature exceed 165 oC. UVLO circuit to ensure proper power is available for correct operation of the IC. VREF is derived from VDDQ with an accurate divide by op-amps(VREF Buffer). It is capable to sink and source 30uA. It is used as the reference voltage to the Error amp. A 100nF or higher capacitor is recommended for VREF pin to ground; To enhance the noise immunity from board, an additional pull-down resistor (1MΩ) is recomanded as well from VREF pin to ground. 2007 Semtech Corp. 8 www.semtech.com SC2596 POWER MANAGEMENT Application Information cause a large trace inductance and trace resistance. Consider the load transient condition, a fast load current going through VTT strip plane will create a voltage spike on VTT plane and a DC voltage drop for load current. It is recommanded the VSENSE pin should be connected center of VTT plane to improve regulation and transient response. Overview Double Data Rate (DDR) SDRAM was defined by JEDEC 1997. Its clock speed is the same as previous SDRAM but data transfer speed is twice than previous SDRAM. By now, the requirement voltage range is changed from 3.3V to 2.5V or 1.8V; the power dissipation is smaller than SDRAM. For above reasons, it is very popular and widely used in M/B, N/B, Video-cards, CD ROM drives, Disk drives. A longer trace of VSENSE may pick up noise and cause the error of load regulation. Hence designer should avoid a longer trace between VSENSE to VTT plane. A 100nF ceramic capacitor close to VSENSE pin is required. Regarding the DDR power management solution, there are two topologies can be selected for system designers. One is switching mode regulator that has bigger sink/ source current capability, but the cost is higher and needs more board space. Another solution is linear mode regulator, which costs less, and needs less board space. For two DIMM motherboards, system designers usually choose the linear mode regulator for DDR power management solution. VREF VREF pin is an output pin to provid internal reference voltage. System designer can use the voltage for Northbridge chipset and memory. It is necessary to add a ceramic capacitor (100nF) from VREF pin to ground with shortest trace. Thermal shutdown Typical Application Circuits & Waveforms The SC2596 has built-in thermal detected circuit to prevent this device from over temperature and damage. The SC2596 goes into shunt down mode when temperature is higher than 165OC. The protection condition will release when the temperature of device drop down by 10OC. Four different application circuits are shown below in Figure 1, Figure 2, Figure 3 and Figure 4. Each circuit is designed for a specific condition. See Note a. and b. below for recommended power up sequencing. AVCC and PVCC The AVCC pin, PVCC pin and the VDDQ pin can be tied together for SSTL-2 application (Figure 1). It only needs a 2.5V power rail for normal operation. System designer can save the PCB space and reduce the cost. Application_1: Standard SSTL-2 Application AVCC and PVCC are the input supply pins for the SC2596. AVCC is supply voltage for all the internal control circuitry. The AVCC voltage has to be greater than its UVLO threshold voltage (2.1V typical) to allow the SC2596 to be normal operation. VDDQ 2.5V SC2596 1 The PVCC pin provides the rail voltage from where the VTT pin draws load current. There is a limitation between AVCC and PVCC. The PVCC voltage must be less or equal to AVCC voltage to ensure the correct VTT output voltage regulation. 2 VTT EN PVCC VSENSE AVCC VREF VDDQ 8 VTT 1.25V 7 EN 3 6 VREF Csense 4 1.25V 10nF VSENSE 5 Cin1 Cin2 1uF 100uF 220uF Cout Cref 100nF 0 VSENSE pin is a feedback pin from VTT plane. VTT plane is always a narrow and long strip plane in most montherboard applications. This long strip plane will © 2007 Semtech Corp. GND Figure 1: Standard SSTL-2 application. 9 www.semtech.com SC2596 POWER MANAGEMENT Application Information (Cont.) PRELIMINARY Application_2: Lower Power Loss Configuration for SSTL-2 Application_3: High Source Current Configuration If there is a need for VTT to source more current, especially for DDR-II applications, the system designer can tie the AVCC and PVCC to 3.3V while has the VDDQ tie to 1. 8V. This configuration can ensure more than 2A source and sink capability from the VTT rail. If power loss is a major concern, separating the PVCC form AVCC and VDDQ will be a good choice (Figure 2). The PVCC can operate at lower voltage (1.8V to 2.5V) if 2.5V voltage is applied on AVCC and the VDDQ, the source current is lower due to the lower operating voltage applied on the PVCC. SC2596 1 SC2596 1 EN GND 2 VTT EN 2.5V PVCC 2 8 VTT PVCC VTT EN PVCC VSENSE AVCC 8 3 AVCC VDDQ 6 4 0.9V 2.5V VREF Csense 4 1.25V VREF VDDQ Csense VSENSE 5 10nF 10nF Cref Cin2 Cin1 100nF 1uF 100uF 220uF 0.9V Cin1 Cin2 Cout 1uF 100uF 220uF 7 6 VDDQ VREF 3 VTT 3.3V EN 1.25V 2.5V 7 GND VREF 1M VDDQ 5 1.8V Cref 100nF Cout 0 Figure 4: High current set up for SSTL-18(DDR-II). 0 Notes: Figure 2: Lower power loss for SSTL-2(DDR-I). (a) The preferred configuration for DDR-I applications is to tie AVCC and PVCC to VDDQ, which is typically 2.5V. (b) If AVCC and PVCC rails are tied together, then the VDDQ cannot lead the AVCC and PVCC. SC2596 1 GND VTT 8 VTT 2.5V 2 EN PVCC VSENSE AVCC 0.9V 7 EN 3 6 VDDQ VREF Csense 4 0.9V 10nF VREF VDDQ 5 1.8V Cin1 Cin2 1uF 100uF 220uF Cout Cref 100nF 0 Figure 3: Lower power loss for SSTL-18(DDR-II). © 2007 Semtech Corp. 10 www.semtech.com SC2596 POWER MANAGEMENT Application Information (Cont.) Layout guidelines 1) The EDP SO-8 package of SC2596 can improve the thermal impedance (θJC) significantly. A suitable thermal pad should be add when PCB layout. Some thermal vias are required to connect the thermal pad to the PCB ground layer. This will improve the thermal performance. Please refer to the recommanded landing pattern. 2) To increase the noise immunity, a ceramic capacitor of 100nF is required to decouple the VREF pin with the shortest connection trace. 3) To reduce the noise on input power rail for standard SSTL-2 application, a 100 µF low ESR capacitor and a 1µF ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection. 4) VTT output copper plane should be as large as possible. A 4.7uF to 10µF capacitor have to be used to decouple the VTT pin. 5) The trace between VSENSE pin and VTT rail should be as short as possible and put a 10nF ~100nF capacitor close this vsense pin. 2007 Semtech Corp. 11 www.semtech.com SC2596 POWER MANAGEMENT PRELIMINARY Typical Application Circuit VDDQ 1.8V U3 1 EN 2 3 4 VREF 1M GND VTT EN PVCC VSENSE AVCC VREF VDDQ 8 VTT 0.9V 7 6 3.3V 5 C1 C2 100nF R1 0.9V SC2596 10nF C3 C4 C5 1uF 100uF 220uF 0 DDR-II VTT Solution Bill of Material R ef Qty 1 1 C1 100nF, 25V, X5R,Ceramic, 0603 Yageo 2 1 C2 10nF, 16V, X5R, Ceramic , 0603 Yageo 3 1 C3 1uF, 16V, X5R, Ceramic , 0603 Yageo 4 1 C6 10uF, 16V, X5R, Ceramic , 1206 Yageo 5 1 C4 100uF, 6.3V, Aluminum Yageo 6 1 C5 220uF, 6.3V, Aluminum Rubycon 7 1 R1 1M OHM Yageo 8 1 U1 SC2596 Semtech 2007 Semtech Corp. R ef eren ce P ar t N u m b e r / Val u e 12 M an u f act u r er www.semtech.com SC2596 POWER MANAGEMENT Outline Drawing - Power SOIC-8L (EDP) A D e N DIM 2X E/2 E1 1 E 2 ccc C 2X N/2 TIPS e/2 B D aaa C SEATING PLANE A2 A C A1 bxN bbb DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX A A1 A2 b c D E1 E e F h L L1 N 01 aaa bbb ccc .053 .069 .000 .005 .049 .065 .012 .020 .007 .010 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .086 .090 .094 .010 .020 .016 .028 .041 (.041) 8 0 8 .004 .010 .008 1.75 1.35 0.13 0.00 1.65 1.25 0.31 0.51 0.25 0.17 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 2.19 2.29 2.39 0.25 0.50 0.40 0.72 1.04 (1.05) 8 0 8 0.10 0.25 0.20 C A-B D h F EXPOSED PAD h H F c GAGE PLANE 0.25 L (L1) SEE DETAIL A 01 A DETAIL SIDE VIEW NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MS-012, VARIATION BA. 4. -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H- Land Pattern - Power SOIC-8L (EDP) SOLDER MASK E D DIM (C) G F Z Y THERMAL VIA ? 0.36mm P X DIMENSIONS INCHES MILLIMETERS C D E F G P X Y Z (.205) .098 .201 .096 .118 .050 .024 .087 .291 (5.20) 2.49 5.10 2.44 3.00 1.27 0.60 2.20 7.40 NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 300A. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 © 2007 Semtech Corp. 13 www.semtech.com