ST
ST3010
Audio Decoder/Encoder
Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification.
Some parameters are subject to change.
1. FEATURES
24-bit DSP based voice/audio processor
Operation voltage
– Core logic: 2.25V~2.7V
– I/O pads: 3.0V~3.6V
Voltage regulator for core logic
Low Voltage Reset (LVR)
_ 2.5V low voltage reset
One PLL to generate high system frequency from a
3MHz source
_ 12M~30MHz PLL output
Tow clock sources
_ Crystal...........................................................3MHz
_ External input...……………………………......3MHz
Low power down current
_Typical current: 3uA
One 16-bit programmable Timer
One clocking output
One external interrupt
_ Edge/level trigger supported
One 16-bit direct-drive DAC
– Maximum current: 145mA
MCU interfaces
_ Parallel mode
Two Serial PORT interfaces(SP)
_ Programmable data length from 8-bit to 16-bit
_ I2S, Left/Right Justified interfaces to external DAC/ADC
Function List
_LBRC playback (1.2Kbps, 1.6Kbps, 2.4Kbps for 8KHz)
(1.6Kbps, 2.2Kbps, 3.3Kbps for 11KHz)
1. AB-Repeat
2. Time stretch
(speed up x2, speed down x2)
3. Combine syllable
_Audio Playback (CBR, VBR-- all bit rate)
1. Forward/Backward play , AB-Repeat
2. Encryption
3. Spectrum gain
4. Time stretch
(speed up x1.5, speed down x1.5)
5. Combine syllable
_Wav Playback
1. Forward/Backward play, AB-Repeat
_Wav Record {MS-ADPCM(3.8:1)}
1. Software AGC
2. GENERAL DESCRIPTION
The ST3010 is a highly integrated and cost-effective 24-bit
DSP based audio processor for various consumer applications.
It consists of one powerful DSP for advanced voice decoder
and encoder algorithms of natural speech with less memory. It
provides low bit rate compression (LBRC) for voice playback
and audio playback.
One external interrupt pin can be requested by external
devices.
System clock comes from 3MHz crystal or external input.
One internal 16-bit DAC can provide significant volume
equipping with internal amplifier. For particular application or
recorder, two general audio interfaces are supported to
interface with external DAC/ADC. Audio interface can be
configured to I2S or Left/Right Justified compatible mode.
ST3010 has 32 I/Os and these can be either GPIO or
functional pins. Each pin can be programmed to input or output.
There are serial and parallel interfaces for various connections
with different MCUs.
Ver 0.7
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ST3010
2.1 Block Diagram
Figure 2-1
Ver 0.7
ST3010 Block Diagram
2/13
2007-06-14
ST3010
3. SIGNAL DESCRIPTIONS
Table 3-1
Function
Group
System control
Special I/O
GPIO
External
Interrupt
Serial Port0/
DPA[4:0]
Serial Port1/
DPA[12:8]
MCU Interface
Ver 0.7
Signal Function Description
Pin Name
Pin #
I/O
Description
RESET
PWD
PWDA
OSCXI
OSXO
ECLK
1
1
1
1
1
1
I
I
O
I
O
I
CMODE[1:0]
2
I
TEST[2:0]
SO[1:0]/
DPA[7,15]
CLKO/
DPA[6]
DAP[13,14],
DPB[0:15]
3
I
2
O
1
O
18
I/O
XREQ/DPA[5]
1
I
TF0/DPA[0]
RF0/DPA[1]
TX0/DPA[2]
RX0/DPA[3]
SCLK0/DPA[4]
TF1/DPA[8]
RF1/DPA[9]
TX1/DPA[10]
RX1/DPA[11]
SCLK1/DPA[12]
D[0]/SCL
D[1]/SDI
D[2]/SDO
D[3:7]
1
1
1
1
1
1
1
1
1
1
1
1
1
5
O
I
O
I
O
O
I
O
I
O
I/O
I/O
I/O
I/O
WR
1
I
Parallel : Write enable, low active
RD
1
I
Parallel : Read enable, low active
CS
1
I
Parallel : Chip select, low active
CMD
1
I
REQ
RDY
1
1
O
O
PMODE
1
I
System reset, low active
Power down, low active
Power down acknowledge, high active
Crystal input or R-oscillator input
Crystal output
External clock input
Clock source select
01=Crystal
1X=ECLK
Test mode
SO0/DPA[7], SO1/DPA[15]
Clock output/DPA[6]
General I/O
External interrupt/DPA[5]
Transmit frame synchronization/DPA[0]
Receive frame synchronization/DPA[1]
Serial data transmit/DPA[2]
Serial data receive/DPA[3]
Serial clock/DPA[4]
Transmit frame synchronization/DPA[8]
Receive frame synchronization/DPA[9]
Serial data transmit/DPA[10]
Serial data receive/DPA[11]
Serial clock/DPA[12]
Parallel : Data bus
Parallel : Data bus
Parallel : Data bus
Parallel : Data bus
Parallel : Command/data select
“H”: Data
“L”: Command
DSP wants to sent command to MCU, low active
DSP permit MCU access data, low active
Parallel interface select
0: Standard parallel (default)
1: Special parallel
3/13
2007-06-14
ST3010
Power
Regulator
DAC
Ver 0.7
P/S
1
I
VDD25
VSS25
VDD33
VSS33
REGVDD33
REGVSS33
PLLVDD25
PLLVSS25
PLLVDD25A
PLLVSS25A
DACVDD33A
DACVSS33A
DACOVDD33A
DACOVSS33A
VCCOUT
VREF
DACO
DACOB
VCM
2
2
2
2
1
1
1
1
1
1
1
1
2
2
1
1
2
2
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
Parallel/serial interface select
0: Serial
1: Parallel
2.5V power
2.5V power ground
3.3V power
3.3V power ground
Digital power input of regulator
Digital power ground of regulator
Digital power input of PLL
Digital power ground of PLL
Analog power input of PLL
Analog power ground of PLL
Analog power input of DAC
Analog power ground of DAC
Analog power input of DAC output stage
Analog power ground of DAC output stage
2.5V output of regulator
Voltage reference
DAC direct drive pin(+)
DAC direct drive pin(-)
Common mode voltage reference
4/13
2007-06-14
ST3010
4. ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Rations
*Note: Stresses above those listed under “Absolute Maximum
DC Supply Voltage: VDD33 ---------------- -0.3V to +4.5V
Operating Ambient Temperature --------- -10°C to +60°C
Storage Temperature ------------------------ -10°C to +125°C
Ratings” may cause permanent damage to the device. All the
ranges are stress ratings only. Functional operation of this
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied or
intended. Exposed to the absolute maximum rating conditions
for extended periods may affect device reliability.
4.2 DC Electrical Characteristics
Table 4-1
DC Electrical Characteristics
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25°C, unless otherwise specified
Parameter
Symbol
Min.
Operating Voltage
VDD33
3.0
Operating Voltage
VDD25
2.25
Operating Current
IOP1
30
Power Down Current
IPD
3
Output driving
Iod
15
mA
Output sinking
Ios
27
mA
Input low voltage
VIL
0.7
V
Input high voltage
VIH
1.3
V
Pull-up resistor
RPU
49
KΩ
Pull-down resistor
RPD
51
KΩ
Low Voltage Reset Level
VLVR
Ver 0.7
2.4
Typ.
2.5
2.5
5/13
Max.
Unit
3.6
V
2.7
V
mA
4.5
2.6
Condition
Run at 24MHz without speaker
µA
V
2007-06-14
ST3010
4.3 AC Electrical Characteristics
Figure 4-1
Figure 4-2
Ver 0.7
Serial Interface Timing Diagram
Parallel Interface Timing Diagram
6/13
2007-06-14
ST3010
Table 4-2
Timing parameters for 0
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25°C
Symbol
Characteristic
Min.
st
Rating
Typ.
Max.
Unit
tCSS
CS low to 1 SCL rising
100
nS
tCYC
tDS
SCL cycle time
Data valid prior SCL falling
200
0
nS
nS
tDH
tDD
Data Hold time after SCL rising
SDO output delay from SCL falling
10
Table 4-3
10
nS
nS
Timing parameters for 0
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25°C
Rating
Typ.
Symbol
Characteristic
tCH
tCS
Cmd pin hold time
Cmd pin setup time
5
5
nS
nS
tCYC
tCCLW
System cycle time
Write pulse width
3.5D
0.5D
nS
nS
tCCHW
tCCLR
Enable H write width
Read pulse width
3D
0.5D
nS
nS
tCCHR
tDS
Enable H read width
Write data setup time
3D
0.5D
nS
nS
tDH
tACC
Write data hold time
Read access time
5
tOH
Read data disable time
4
Min.
Max.
10
Unit
nS
nS
nS
Remark: D = time of one DSP system clock
Ver 0.7
7/13
2007-06-14
ST3010
5. PAD DIAGRAM
Ver 0.7
8/13
2007-06-14
ST3010
6. DEVICE INFORMATION
1.
Substrate: GND
PAD
Symbol
No.
1
TF0
PAD
Symbol
No.
X
Y
1616.23
62.5
31
X
Y
PAD
No.
DPB7
2977.5
2036.55
61
DPB8
2977.5
2136.55
62
Symbol
X
Y
P/S
720
3107.5
RESET
620
3107.5
2
RF0
1716.23
62.5
32
3
TX0
1816.23
62.5
33
DPB9
2977.5
2236.55
63
CMODE0
520
3107.5
62.5
34
DPB10
2977.5
2336.55
64
CMODE1
420
3107.5
OSCXI
320
3107.5
4
RX0
1916.23
5
SCLK0
2016.23
62.5
35
DPB11
2977.5
2436.55
65
6
XREQ
2116.23
62.5
36
DPB12
2977.5
2546.55
66
OSXO
210
3107.5
DPB13
2977.5
2656.55
67
ECLK
100
3107.5
7
CLKO
2216.23
62.5
37
8
SO0
2316.23
62.5
38
DPB14
2977.5
2766.55
68
VREF
62.5
2753.04
DPB15
2940
3107.5
69
VCCOUT
62.5
2643.04
9
TF1
2416.23
62.5
39
10
RF1
2516.23
62.5
40
VSS33
2830
3107.5
70
REGVDD33
62.5
2533.04
VDD33
2720
3107.5
71
REGVSS33
62.5
2433.04
11
TX1
2616.23
62.5
41
12
RX1
2716.23
62.5
42
PWDA
2620
3107.5
72
PLLVSS25
62.5
2257.04
PWD
2520
3107.5
73
PLLVDD25
62.5
2157.04
13
SCLK1
2826.23
62.5
43
14
DPA13
2936.23
62.5
44
D7
2420
3107.5
74
PLLVSS25A
62.5
2057.04
406.55
45
D6
2320
3107.5
75
PLLVDD25A
62.5
1957.04
D5
2220
3107.5
76
DACVSS33A
62.5
1781.04
15
DPA14
2977.5
16
SO1
2977.5
516.55
46
17
VDD25
2977.5
626.55
47
D4
2120
3107.5
77
DACVDD33A
62.5
1681.04
D3
2020
3107.5
78
VCM
62.5
1581.04
18
VSS25
2977.5
736.55
48
19
TEST2
2977.5
836.55
49
SDO
1920
3107.5
79
DACOB
62.5
1481.04
SDI
1820
3107.5
80
DACOB
62.5
1381.04
62.5
1281.04
20
TEST1
2977.5
936.55
50
21
TEST0
2977.5
1036.55
51
SCL
1720
3107.5
81 DACOVSS33A
VDD25
1620
3107.5
82 DACOVSS33A 62.51 1181.04
22
VSS33
2977.5
1136.55
52
23
VDD33
2977.5
1236.55
53
VSS25
1520
3107.5
83 DACOVDD33A 62.5
1081.04
CMD
1420
3107.5
84 DACOVDD33A 62.5
981.04
24
DPB0
2977.5
1336.55
54
25
DPB1
2977.5
1436.55
55
PMODE
1320
3107.5
85
DACO
62.5
881.04
REQ
1220
3107.5
86
DACO
62.5
781.04
26
DPB2
2977.5
1536.55
56
27
DPB3
2977.5
1636.55
57
RDY
1120
3107.5
28
DPB4
2977.5
1736.55
58
WR
1020
3107.5
RD
920
3107.5
CS
820
3107.5
29
DPB5
2977.5
1836.55
59
30
DPB6
2977.5
1936.55
60
Ver 0.7
9/13
2007-06-14
ST3010
7. APPLICATION CIRCUIT
1. ST3010 Part
Figure 7-1
ST3010 Application Circuit Diagram
Note:
1. If any of OSCXI, OSXO, and ECLK is not used, it needs to connect to GND.
2. The cascade resistor and parallel capacitor on CMD, RD, and WR pins can reduce noise interference. In general, resistor is
short and capacitor is open. Please preserve the options on PCB.
Ver 0.7
10/13
2007-06-14
ST3010
2. ADC Part
10K
10K
1.2K
1.5K
2K
Figure 7-2
Note:
Ver 0.7
ADC Application Circuit Diagram
The capacity and inductance in the left down part is to eliminate the record noise.
11/13
2007-06-14
ST3010
3. DAC Part
Figure 7-3
Ver 0.7
DAC Application Circuit Diagram
12/13
2007-06-14
ST3010
8. REVISION
REVISION
DESCRIPTION
PAGE
DATE
0.1
First release
2005/9/16
0.2
Revision: Supporting several different digital audio playback
2005/11/3
0.3
Revision together with programming guide Version 0.1 published
2005/11/30
0.4
Remove serial interface
2005/12/8
0.5
Add some new function
2006/2/22
0.6
Modify application circuit
2006/4/12
0.7
Add ADC/DAC Application Circuit
2006/4/24
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced
without permission from Sitronix. Sitronix Technology Corp. reserves the right to change this document without prior notice and makes no
warranty for any errors which may appear in this document. Sitronix products are not intended for use in life support, critical care, medical, safety
equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense
application, or any governmental procurement to which special terms or provisions may apply.
Ver 0.7
13/13
2007-06-14