ICX428ALB Diagonal 8mm (Type 1/2) CCD Image Sensor for EIA B/W Video Cameras Description The ICX428ALB is an interline CCD solid-state image sensor suitable for EIA B/W video cameras with a diagonal 8mm (Type 1/2) system. Basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically through the adoption of EXview HAD CCDTM technology. This chip features a field period readout system and an electronic shutter with variable charge-storage time. Also, this outline is miniaturized by using original package. This chip is compatible with the pins of the ICX248ALB and has the same drive conditions. EXview HAD CCD TM has differrent spectral characteristics from the curreent CCD. 16 pin DIP (Ceramic) Pin 1 2 V Features • High sensitivity 3 40 H • Low smear Pin 9 • High D range Optical black position • High S/N • High resolution and low dark current (Top View) • Excellent antiblooming characteristics • Continuous variable-speed shutter • Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V) • Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V) • Horizontal register: 5V drive • Maximum package dimensions: φ13.2mm 12 Device Structure • Interline CCD image sensor • Optical size: Diagonal 8mm (Type 1/2) • Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels • Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels • Chip size: 7.40mm (H) × 5.95mm (V) • Unit cell size: 8.4µm (H) × 9.8µm (V) • Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels • Number of dummy bits: Horizontal 22 Vertical 1 (even fields only) • Substrate material: Silicon TM ∗ EXview HAD CCD is a trademark of Sony Corporation. EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01923A41 ICX428ALB USE RESTRICTION NOTICE (December 1, 2003 ver.) This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify this Notice which will be available to you in the latest specifications book for the Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice when you consider using the Products. Use Restrictions • The Products are intended for incorporation into such general electronic equipment as office products, communication products, measurement products, and home electronics products in accordance with the terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time. • You should not use the Products for critical applications which may pose a life- or injury- threatening risk or are highly likely to cause significant property damage in the event of failure of the Products. You should consult your Sony sales representative beforehand when you consider using the Products for such critical applications. In addition, you should not use the Products in weapon or military equipment. • Sony disclaims and does not assume any liability and damages arising out of misuse, improper use, modification, use of the Products for the above-mentioned critical applications, weapon and military equipment, or any deviation from the requirements set forth in this specifications book. Design for Safety • Sony is making continuous efforts to further improve the quality and reliability of the Products; however, failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to ensure the safe design of your products such as component redundancy, anti-conflagration features, and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social damage as a result of such failure. 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You should review those terms and conditions when you consider purchasing and/or using the Products. –2– ICX428ALB VDD VL Vφ1 φSUB Vφ2 Vφ3 Vφ4 8 7 6 5 4 3 2 1 Vertical Register VOUT Block Diagram and Pin Configuration (Top View) Note) Horizontal Register 12 13 14 15 16 φRG VDSUB Hφ1 Hφ2 NC 11 RD 10 GND 9 NC Note) : Photo sensor Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 9 NC 2 Vφ3 Vertical register transfer clock 10 NC 3 Vφ2 Vertical register transfer clock 11 GND GND 4 φSUB Substrate clock 12 RD Reset drain bias 5 Vφ1 Vertical register transfer clock 13 φRG Reset gate clock 6 VL Protective transistor bias 14 VDSUB Substrate bias circuit supply voltage 7 VDD Output circuit supply voltage 15 Hφ1 Horizontal register transfer clock 8 VOUT Signal output 16 Hφ2 Horizontal register transfer clock –3– ICX428ALB Absolute Maximum Ratings Item Ratings Unit –0.3 to +50 V VDD, VRD, VDSUB, VOUT – GND –0.3 to +18 V VDD, VRD, VDSUB, VOUT – φSUB –55 to +10 V Vφ1, Vφ2, Vφ3, Vφ4 – GND –15 to +20 V Vφ1, Vφ2, Vφ3, Vφ4 – φSUB to +10 V Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +17 V Hφ1, Hφ2 – Vφ4 –17 to +17 V φRG – GND –10 to +15 V φRG – φSUB –55 to +10 V VL – φSUB –65 to +0.3 V Pins other than GND and φSUB – VL –0.3 to +30 V Storage temperature –30 to +80 °C Operating temperature –10 to +60 °C Substrate clock φSUB – GND Supply voltage Clock input voltage ∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –4– Remarks ∗1 ICX428ALB Bias Conditions 1 [when used in substrate bias internal generation mode] Item Symbol Min. Typ. Max. Unit Output circuit supply voltage VDD 14.55 15.0 15.45 V Reset drain voltage VRD 14.55 15.0 15.45 V Protective transistor bias VL Substrate bias circuit supply voltage VDSUB 15.45 V Substrate clock φSUB Remarks VRD = VDD ∗1 14.55 15.0 ∗2 ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be used. (When CXD1267AN is used.) ∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. Bias Conditions 2 [when used in substrate bias external adjustment mode] Item Symbol Min. Typ. Max. Unit Remarks Output circuit supply voltage VDD 14.55 15.0 15.45 V Reset drain voltage VRD 14.55 15.0 15.45 V VRD = VDD Protective transistor bias VL ∗3 Substrate bias circuit supply voltage VDSUB ∗4 Substrate voltage adjustment range VSUB 6.0 14.0 V ∗5 Substrate voltage adjustment precision ∆VSUB –3 +3 % ∗5 ∗3 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be used. (When CXD1267AN is used.) ∗4 Connect to GND or leave open. ∗5 The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in substrate bias internal generation mode. VSUB code — one character indication Code and optimal setting correspond to each other as follows. VSUB code E Optimal setting 6.0 f G h J K L m 6.5 7.0 7.5 8.0 8.5 9.0 N P Q R S T DC Characteristics Output circuit supply current Symbol V W 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 <Example> "L" → VSUB = 9.0V Item U Min. IDD –5– Typ. Max. Unit 5.0 10.0 mA Remarks ICX428ALB Clock Voltage Conditions Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Symbol Min. Waveform diagram Remarks VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –9.6 –9.0 –8.5 V 2 VVL = (VVL3 + VVL4)/2 VφV 8.3 9.65 Vp-p 2 VφV = VVHn – VVLn (n = 1 to 4) 0.1 V 2 9.0 | VVH1 – VVH2 | VVH = (VVH1 + VVH2)/2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.5 V 2 High-level coupling VVHL 0.5 V 2 High-level coupling VVLH 0.5 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling VφH 4.75 5.0 VHL –0.05 0 VφRG 4.5 5.0 VRGLH – VRGLL Substrate clock voltage VφSUB 5.25 Vp-p 3 0.05 V 3 V 4 ∗1 VRGL Reset gate clock voltage∗1 Typ. Max. Unit 5.5 Vp-p 4 0.8 4 V 23.0 24.0 25.0 Vp-p Low-level coupling 5 ∗1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications. Item Reset gate clock voltage Symbol Min. Typ. Max. Unit VRGL –0.2 0 VφRG 8.5 9.0 0.2 V 9.5 Vp-p –6– Waveform diagram 4 4 Remarks ICX428ALB Clock Equivalent Circuit Constant Symbol Item Typ. Min. Max. Unit CφV1, CφV3 2700 pF CφV2, CφV4 2700 pF CφV12, CφV34 820 pF CφV23, CφV41 330 pF Capacitance between horizontal transfer clock CφH1 and GND CφH2 100 pF 91 pF Capacitance between horizontal transfer clocks CφHH 47 pF Capacitance between reset gate clock and GND CφRG 11 pF Capacitance between substrate clock and GND CφSUB 680 pF R1, R3 91 Ω R2, R4 100 Ω RGND 68 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vertical transfer clock series resistor Vertical transfer clock ground resistor Vφ2 Vφ1 CφV12 R1 R2 Hφ1 CφV1 CφV23 CφV4 Vφ4 Hφ2 CφHH CφV2 CφV41 R4 Remarks RGND CφV34 CφH1 CφH2 CφV3 R3 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit –7– ICX428ALB Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% VVT φM φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVH1 VVHH VVH VVHH VVHL VVHL VVHL VVL1 VVHH VVHH VVH3 VVH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVHL VVH2 VVHL VVH4 VVLH VVL2VVLH VVLL VVLL VVL4 VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) VVHL –8– VVL ICX428ALB (3) Horizontal transfer clock waveform tr twh tf 90% VφH twl 10% VHL tr (4) Reset gate clock waveform twh tf VRGH twl VφRG Point A RG waveform VRGL + 0.5V VRGLH VRGL VRGLL VRGLm Hφ1 waveform +2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the period twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90% φM VφSUB φM 2 10% VSUB 0% tr twh –9– tf ICX428ALB Clock Switching Characteristics Item Symbol VT Vertical transfer clock Vφ1, Vφ2, Vφ3, Vφ4 Horizontal transfer clock Readout clock During imaging twh 2.3 2.5 φSUB tf 0.5 0.5 20 20 15 5.38 19 Remarks Unit µs During readout 250 ns ∗1 15 During Hφ1 parallel-serial Hφ2 conversion Substrate clock tr Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Hφ Reset gate clock φRG twl 15 0.01 0.01 5.38 0.01 0.01 51 3 3 19 ns ∗2 µs 11 13 1.5 1.8 0.5 ns 0.5 µs ∗1 When vertical transfer clock driver CXD1267AN is used. ∗2 tf ≥ tr – 2ns. Item Symbol Horizontal transfer clock Hφ1, Hφ2 two Min. Typ. 16 20 Max. Unit Remarks ns ∗3 ∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. – 10 – When draining charge ICX428ALB Image Sensor Characteristics (Ta = 25°C) Unit Measurement method 1400 mV 1 5500 mV 2 mV 3 –115 dB 4 20 % 5 Zone 0 and I 25 % 5 Zone 0 to II' Vdt 2 mV 6 Ta = 60°C Dark signal shading ∆Vdt 1 mV 7 Ta = 60°C Flicker F 2 % 8 Lag Lag 0.5 % 9 Item Symbol Min. Typ. Sensitivity1 S1 1120 Sensitivity2 S2 4500 Saturation signal Vsat 1000 Smear Sm Video signal shading SH Dark signal –126 Max. Zone Definition of Video Signal Shading 768 (H) 14 14 12 H 8 V 10 H 8 Zone 0, I 494 (V) 10 Zone II, II' V 10 Ignored region Effective pixel region – 11 – Remarks Ta = 60°C ICX428ALB Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.) 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output or chroma signal output of the measurement system. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.4mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: This indicates the standard imaging condition I with the IR cut filter removed. 3) Standard imaging condition III: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens and the luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. (IR cut filter is not spplicable.) 1. Sensitivity1 Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (VS1) at the center of the screen and substitute the value into the following formula. S1 = VS1 × 250 60 [mV] 2. Sensitivity2 Set to standard imaging condition II. After selecting the electronic shutter mode with a shutter speed of 1/1000s, measure the signal output (VS2) at the center of the screen and substitute the value into the following formula. S2 = VS2 × 1000 [mV] 60 3. Saturation signal Set to standard imaging condition III. After adjusting the luminous intensity to 10 times the intensity with average value of the signal output, 200mV, measure the minimum value of the signal output. – 12 – ICX428ALB 4. Smear Set to standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value VSm [mV] of the signal output and substitute the value into the following formula. Sm = 20 × log VSm × 1 × 500 200 1 10 [dB] (1/10V method conversion value) 5. Video signal shading Set to standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax – Vmin)/200 × 100 [%] 6. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 7. Dark signal shading After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 8. Flicker Set to standard imaging condition III. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then substitute the value into the following formula. Fy = (∆Vf/200) × 100 [%] 9. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) × 100 [%] FLD V1 Light Strobe light timing signal output 200mV Output – 13 – Ylag (lag) CXD1267AN 14 13 12 11 6 7 8 9 10 XV1 XSG1 XV3 XSG2 XV4 RG Hφ2 Hφ1 16 5 XV2 22/20V 17 XSUB 15 18 22/16V 1/35V 0.01 15 2 16 1 Vφ4 Hφ2 4 Vφ3 Hφ1 3 100k 3 4 5 8 9 7 10 6 ICX428 (BOTTOM VIEW) Vφ2 14 VDSUB 19 φSUB 13 φRG 2 VL 20 Vφ1 12 RD – 14 – 3.9k 100 0.01 11 GND 1 VDD NC 15V VOUT NC Drive Circuit 1 (substrate bias internal generation mode) 3.3/20V 1 0.01 [∗A] CCD OUT 1M 3.3/16V –9V ICX428ALB 13 12 11 7 8 9 10 XSG1 XV3 XSG2 XV4 RG Hφ2 Hφ1 14 6 XV1 22/20V 16 5 XV2 15 17 4 XSUB CXD1267AN 18 3 22/16V 1/35V 1/35V 0.01 1/35V 15 2 16 1 14 13 12 3.9k 100 0.01 9 10 8 39k 11 7 6 5 0.1 ICX428 (BOTTOM VIEW) 4 3 100k 27k Vφ4 Hφ2 19 Vφ3 Hφ1 2 56k Vφ2 VDSUB 20 φSUB 1 RD – 15 – φRG 270k Vφ1 GND 0.1 VL NC 15V VDD VOUT NC Drive Circuit 2 (substrate bias external adjustment mode) 3.3/20V 0.1 15k 47k 15k 0.01 [∗A] CCD OUT 1M 3.3/16V –9V ICX428ALB ICX428ALB Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics) 1.0 0.9 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 Wave Length [nm] 800 900 1000 Sensor Readout Clock Timing Chart V1 2.5 V2 Odd Field V3 V4 33.5 1.6 2.5 2.5 2.5 0.2 V1 V2 Even Field V3 V4 Unit: µs – 16 – – 17 – CCD OUT V4 V3 V2 V1 HD BLK VD FLD 493 494 525 1 2 3 4 5 520 Drive Timing Chart (Vertical Sync) 10 2 4 6 1 3 5 15 2 4 6 1 3 5 494 493 1 3 5 2 4 6 1 3 5 2 4 6 ICX428ALB 280 275 270 265 260 20 – 18 – SUB V4 V3 V2 V1 RG H2 H1 BLK HD 20 10 768 1 2 3 5 760 Drive Timing Chart (Horizontal Sync) ICX428ALB 20 10 20 22 1 2 3 1 2 3 10 1 2 3 5 40 30 ICX428ALB Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical shocks. – 19 – – 20 – 1.5 ~ B' 1st. pin Index H GOLD PLATING 42 ALLOY 0.90g AS-B4-01(E) LEAD TREATMENT LEAD MATERIAL PACKAGE MASS DRAWING NUMBER ~ 0.7 ~ Ceramic 1.5 12.35 ± 0.3 12.0 ± 0.15 6.175 V PACKAGE MATERIAL 1 16 ± 1.27 0.6 φ 2 . 13 3 0. 1.5 8 0.3 9 6.175 1.0 B 1.84 PACKAGE STRUCTURE 1.84 4.0 ± 0.2 A 12.0 ± 0.15 0.3 M C 8 9 ~ 7.62 0.25 4.0 ∗ Center of the package : The center is halfway between two pairs of opposite sides, as measured from “B”, “B'”. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom “C” is less than 60µm. 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1˚. 4. The center of the effective image area relative to the center of the package (∗) is (H, V) = (0, 0) ± 0.15mm. 3. The bottom “C” of the package is the height reference. 2. The point “B” of the package is the horizontal reference. The point “B'” of the package is the vertical reference. 1 16 4.0 1. “A” is the center of the effective image area. 2.54 3.29 ± 0.3 16 pin DIP (300mil) 12.35 ± 0.3 Unit: mm ~ Package Outline ICX428ALB Sony Corporation