ICX038DNA
Diagonal 8mm (Type 1/2) CCD Image Sensor for NTSC Color Video Cameras
Description
The ICX038DNA is an interline CCD solid-state
image sensor suitable for NTSC color video cameras
with a diagonal 8mm (Type 1/2) system. Smear,
sensitivity, D-range, S/N and other characteristics
have been greatly improved compared with the
ICX038BNA. High sensitivity and low dark current
are achieved through the adoption of Ye, Cy, Mg and
G complementary color mosaic filters and HAD
(Hole-Accumulation Diode) sensors.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time.
This chip is compatible with and can replace the
ICX038BNA.
20 pin DIP (Cer-DIP)
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Pin 1
2
V
12
Features
3
40
H
Pin 11
• Low smear (–20dB compared with the ICX038BNA)
• High sensitivity (+3.0dB compared with the ICX038BNA)
Optical black position
• High D range (+2.5dB compared with the ICX038BNA)
(Top View)
• High S/N
• High resolution and low dark current
• Excellent antiblooming characteristics
• Ye, Cy, Mg, and G complementary color mosaic filters on chip
• Continuous variable-speed shutter
• Substrate bias:
Adjustment free (external adjustment also possible with 6 to 14V)
• Reset gate pulse:
5Vp-p adjustment free (drive also possible with 0 to 9V)
• Horizontal register:
5V drive
Device Structure
• Interline CCD image sensor
• Image size:
Diagonal 8mm (Type 1/2)
• Number of effective pixels: 768 (H) x 494 (V) approx. 380K pixels
• Total number of pixels:
811 (H) x 508 (V) approx. 410K pixels
• Chip size:
7.95mm (H) x 6.45mm (V)
• Unit cell size:
8.4µm (H) x 9.8µm (V)
• Optical black:
Horizontal (H) direction : Front 3 pixels, rear 40 pixels
Vertical (V) direction
: Front 12 pixels, rear 2 pixels
• Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
• Substrate material:
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95Y13C99
ICX038DNA
VDD
GND
VL
Vφ1
GND
φSUB
Vφ2
Vφ3
Vφ4
10
9
8
7
6
5
4
3
2
1
Vertical Register
VOUT
Block Diagram and Pin Configuration
(Top View)
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Cy
Ye
Cy
Ye
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Note)
Horizontal Register
12
13
14
15
16
17
18
19
20
VSS
GND
GND
RD
φRG
NC
Hφ1
Hφ2
VGG
11
VDSUB
Note)
: Photo sensor
Pin Description
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
Vφ4
Vertical register transfer clock
11
VGG
Output circuit gate bias
2
Vφ3
Vertical register transfer clock
12
VDSUB
Substrate bias circuit supply voltage
3
Vφ2
Vertical register transfer clock
13
VSS
Output circuit source
4
φSUB
Substrate clock
14
GND
GND
5
GND
GND
15
GND
GND
6
Vφ1
Vertical register transfer clock
16
RD
Reset drain bias
7
VL
Protective transistor bias
17
φRG
Reset gate clock
8
GND
GND
18
NC
9
VDD
Output circuit supply voltage
19
Hφ1
Horizontal register transfer clock
10
VOUT
Signal output
20
Hφ2
Horizontal register transfer clock
–2–
ICX038DNA
Absolute Maximum Ratings
Item
Ratings
Unit
–0.3 to +50
V
VDD, VRD, VDSUB, VOUT, VSS – GND
–0.3 to +18
V
VDD, VRD, VDSUB, VOUT, VSS – φSUB
–55 to +10
V
Vφ1, Vφ2, Vφ3, Vφ4 – GND
–15 to +20
V
Vφ1, Vφ2, Vφ3, Vφ4 – φSUB
to +10
V
Voltage difference between vertical clock input pins
to +15
V
Voltage difference between horizontal clock input pins
to +17
V
Hφ1, Hφ2 – Vφ4
–17 to +17
V
φRG, VGG – GND
–10 to +15
V
φRG, VGG – φSUB
–55 to +10
V
VL – φSUB
–65 to +0.3
V
Pins other than GND and φSUB – VL
–0.3 to +30
V
Storage temperature
–30 to +80
°C
Operating temperature
–10 to +60
°C
Substrate clock φSUB – GND
Supply voltage
Clock input voltage
∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–3–
Remarks
∗1
ICX038DNA
Bias Conditions 1 [when used in substrate bias internal generation mode]
Item
Symbol
Min.
Typ.
Max.
Unit
Output circuit supply voltage
VDD
14.55
15.0
15.45
V
Reset drain voltage
VRD
14.55
15.0
15.45
V
Output circuit gate voltage
VGG
1.75
2.0
2.25
V
Output circuit source
VSS
Grounded with 390Ω resistor
Protective transistor bias
VL
∗1
Substrate bias circuit supply voltage
VDSUB
Substrate clock
φSUB
14.55
15.0
∗2
15.45
Remarks
VRD = VDD
V
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Bias Conditions 2 [when used in substrate bias external adjustment mode]
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Output circuit supply voltage
VDD
14.55
15.0
15.45
V
Reset drain voltage
VRD
14.55
15.0
15.45
V
Output circuit gate voltage
VGG
1.75
2.0
2.25
V
Output circuit source
VSS
Protective transistor bias
VL
Substrate bias circuit supply voltage
VDSUB
Substrate voltage adjustment range
VSUB
6.0
14.0
V
∗5
Substrate voltage adjustment precision
∆VSUB
–3
+3
%
∗5
VRD = VDD
Grounded with 390Ω resistor
∗3
∗4
∗3 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗4 Connect to GND or leave open.
∗5 The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a special
code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in
substrate bias internal generation mode.
VSUB code — one character indication
Code and optimal setting correspond to each other as follows.
VSUB code
E
f
G
h
J
K
L
m
N
P
Q
R
S
T
U
V
W
Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
<Example> "L" → VSUB = 9.0V
DC Characteristics
Item
Output circuit supply current
Symbol
IDD
Min.
Typ.
Max.
Unit
5.0
10.0
mA
–4–
Remarks
ICX038DNA
Clock Voltage Conditions
Symbol
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Min. Typ. Max. Unit
Remarks
VVT
14.55 15.0 15.45
V
1
VVH1, VVH2
–0.05
0
0.05
V
2
VVH3, VVH4
–0.2
0
0.05
V
2
VVL1, VVL2,
VVL3, VVL4
–9.6 –9.0
–8.5
V
2
VVL = (VVL3 + VVL4)/2
VφV
8.3
9.65 Vp-p
2
VφV = VVHn – VVLn (n = 1 to 4)
0.1
V
2
9.0
| VVH1 – VVH2 |
VVH = (VVH1 + VVH2)/2
VVH3 – VVH
–0.25
0.1
V
2
VVH4 – VVH
–0.25
0.1
V
2
VVHH
0.5
V
2
High-level coupling
VVHL
0.5
V
2
High-level coupling
VVLH
0.5
V
2
Low-level coupling
VVLL
0.5
V
2
Low-level coupling
VφH
4.75
5.0
5.25 Vp-p
3
VHL
–0.05
0
∗1
0.05
V
3
V
4
5.0
5.5 Vp-p
4
0.8
V
4
25.0
V
5
VRGL
Reset gate clock
voltage∗1
Waveform
diagram
VφRG
4.5
VRGLH – VRGLL
Substrate clock voltage VφSUB
23.0 24.0
Low-level coupling
∗1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Item
Reset gate clock
voltage
Symbol
Min. Typ. Max. Unit
VRGL
–0.2
0
VφRG
8.5
9.0
–5–
0.2
V
9.5 Vp-p
Waveform
diagram
4
4
Remarks
ICX038DNA
Clock Equivalent Circuit Constant
Item
Symbol
Min.
Typ.
Max.
Unit Remarks
CφV1, CφV3
1800
pF
CφV2, CφV4
2200
pF
CφV12, CφV34
450
pF
CφV23, CφV41
270
pF
Capacitance between horizontal transfer clock
and GND
CφH1
64
pF
CφH2
62
pF
Capacitance between horizontal transfer clocks
CφHH
47
pF
Capacitance between reset gate clock and GND
CφRG
8
pF
Capacitance between substrate clock and GND
CφSUB
400
pF
Vertical transfer clock series resistor
R1, R2, R3, R4
68
Ω
Vertical transfer clock ground resistor
RGND
15
Ω
Capacitance between vertical transfer clock
and GND
Capacitance between vertical transfer clocks
Vφ1
Vφ2
CφV12
R1
R2
Hφ1
CφV1
CφV41
CφV23
CφV4
R4
Vφ4
Hφ2
CφHH
CφV2
RGND
CφV34
CφH1
CφH2
CφV3
R3
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
–6–
ICX038DNA
Drive Clock Waveform Conditions
(1) Readout clock waveform
VVT
100%
90%
II
II
φM
φM
2
10%
0%
tr
twh
0V
tf
(2) Vertical transfer clock waveform
Vφ1
Vφ3
VVHH
VVH1
VVHH
VVH
VVHL
VVHL
VVH3
VVHL
VVL1
VVH
VVHH
VVHH
VVHL
VVL3
VVLH
VVLH
VVLL
VVLL
VVL
VVL
Vφ2
Vφ4
VVHH
VVHH
VVH
VVH
VVHH
VVHH
VVHL
VVH2 VVHL
VVHL
VVH4
VVL2
VVHL
VVLH
VVLH
VVLL
VVLL
VVL
VVL4
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
–7–
VVL
ICX038DNA
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
twl
VφH
10%
VHL
(4) Reset gate clock waveform
tr
twh
tf
VRGH
twl
Point A
VφRG
RG waveform
VRGL + 0.5V
VRGLH
VRGL
VRGLL
Hφ1 waveform
+2.5V
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the period twh, then:
VφRG = VRGH – VRGL
–8–
ICX038DNA
(5) Substrate clock waveform
100%
90%
φM
φM
2
VφSUB
10%
0%
VSUB
tr
twh
tf
Clock Switching Characteristics
Item
Symbol
VT
Vertical transfer
clock
Vφ1, Vφ2,
Vφ3, Vφ4
Horizontal
transfer clock
Readout clock
During
imaging
twh
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
2.3 2.5
Hφ
0.5
20
During parallel- Hφ1
serial
Hφ2
conversion
20
15
5.38
Reset gate clock
φRG
11
Substrate clock
φSUB
1.5 1.8
13
Horizontal transfer clock
Symbol
µs
15
250 ns
∗1
ns
∗2
19
15
0.01
0.01
5.38
0.01
0.01
51
3
3
0.5
Hφ1, Hφ2
two
Min.
Typ.
16
20
Max.
19
µs
ns
0.5
Unit
Remarks
ns
∗3
∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
–9–
During
readout
0.5
∗1 When vertical transfer clock driver CXD1267AN is used.
∗2 tf ≥ tr – 2ns.
Item
Unit Remarks
µs
During drain
charge
ICX038DNA
Image Sensor Characteristics
Item
(Ta = 25°C)
Symbol
Min.
Typ.
Sensitivity
S
550
660
Saturation signal
Ysat
800
Smear
Sm
Video signal shading
SHy
Unit
Measurement method
mV
1
mV
2
%
3
20
%
4
Zone 0 and I
25
%
4
Zone 0 to II'
∆Sr
10
%
5
∆Sb
10
%
5
Dark signal
Ydt
2
mV
6
Ta = 60°C
Dark signal shading
∆Ydt
1
mV
7
Ta = 60°C
Flicker Y
Fy
2
%
8
Flicker R-Y
Fcr
5
%
8
Flicker B-Y
Fcb
5
%
8
Line crawl R
Lcr
3
%
9
Line crawl G
Lcg
3
%
9
Line crawl B
Lcb
3
%
9
Line crawl W
Lcw
3
%
9
Lag
Lag
0.5
%
10
Uniformity between video
signal channels
Max.
0.00032 0.00056
Remarks
Ta = 60°C
Zone Definition of Video Signal Shading
768 (H)
14
14
12
V
10
H
8
H
8
Zone 0, I
Zone II, II'
494 (V)
10
Ignored region
Effective pixel region
V
10
Measurement System
[∗Y]
[∗A]
CCD signal output
Y signal output
LPF1
(3dB down 6.3MHz)
CCD
C.D.S
AMP
S
[∗C]
H
LPF2
SH
Chroma signal output
(3dB down 1MHz)
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗Y] , and between [∗A] and [∗C] equals 1.
– 10 –
ICX038DNA
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the
value indicated on the device.)
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output
or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
Cy
Ye
Cy
Ye
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Mg
G
Mg
G
A1
B
A2
As shown in the left figure, fields are read out. The charge is
mixed by pairs such as A1 and A2 in the A field. (pairs such
as B in the B field)
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).
Hreg
Color Coding Diagram
These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} x 1/2
= 1/2 {2B + 3G + 2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} x 1/2
= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:
– (B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)
in alternation. This is also true for the B field.
– 11 –
ICX038DNA
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and
image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard
sensitivity testing luminous intensity.
2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.
S = Ys x
250
[mV]
60
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of the Y signal output, 200mV, measure the minimum value of the Y signal.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula.
Sm =
1
YSm
1
x
x
x 100 [%] (1/10V method conversion value)
10
200
500
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.
SHy = (Ymax – Ymin)/200 x 100 [%]
5. Uniformity between video signal channels
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin
[mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the
following formula.
∆Sr = | (Crmax – Crmin)/200 | x 100 [%]
∆Sb = | (Cbmax – Cbmin)/200 | x 100 [%]
6. Dark signal
Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
– 12 –
ICX038DNA
7. Dark signal shading
After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Ydt = Ydmax – Ydmin [mV]
8. Flicker
1) Fy
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]). Then
substitute the value into the following formula.
Fy = (∆Yf/200) x 100 [%]
2) Fcr, Fcb
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between
fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr, CAb).
Substitute the values into the following formula.
Fci = (∆Ci/CAi) x 100 [%] (i = r, b)
9. Line crawls
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the
following formula.
Lci = (∆Yli/200) x 100 [%] (i = w, r, g, b)
10. Lag
Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following
formula.
Lag = (Ylag/200) x 100 [%]
FLD
V1
Light
Strobe light
timing
Y signal output 200mV
Output
– 13 –
Ylag (lag)
RG
Hφ2
Hφ1
XV4
XSG2
XV3
XSG1
XV1
XV2
CXD1267AN
22/20V
10
9
8
7
6
5
11
12
13
14
15
16
17
4
22/16V
0.01
1/35V
1 2
3
4
6
7
8
ICX038DNA
(BOTTOM VIEW)
5
9
10
3.9k
100
180k
0.01
1/
6.3V
390
20 19 18 17 16 15 14 13 12 11
47/
6.3V
Vφ4
Hφ2
XSUB
Vφ3
Hφ1
19
18
Vφ2
NC
2
3
φSUB
φRG
100k
GND
RD
20
Vφ1
GND
1
VL
GND
VOUT
15V
GND
Vss
VDD
VDSUB
– 14 –
VGG
Drive Circuit 1 (substrate bias internal generation mode)
27k
1M
3.3/16V
0.01
[∗A]
CCD OUT
3.3/20V
1
–9V
ICX038DNA
RG
Hφ2
Hφ1
XV4
XSG2
XV3
XSG1
XV1
XV2
XSUB
CXD1267AN
22/20V
10
9
8
7
11
12
13
14
15
16
5
6
17
4
22/16V
1/35V
0.01
1/35V
1 2
3
100k
4
27k
6
7
8
ICX038DNA
(BOTTOM VIEW)
5
0.1
9
10
39k
270k
3.9k
100
180k
0.01
1/
6.3V
390
20 19 18 17 16 15 14 13 12 11
47/
6.3V
Vφ4
Hφ2
1/35V
Vφ3
Hφ1
19
18
Vφ2
NC
2
3
0.1
56k
φSUB
φRG
20
GND
RD
1
GND
15V
VL
GND
VDD
VDSUB
Vφ1
GND
– 15 –
Vss
VOUT
VGG
Drive Circuit 2 (substrate bias external adjustment mode)
27k
3.3/20V
15k
0.1
47k
15k
0.01
CCD OUT
[∗A]
1M
–9V
3.3/16V
ICX038DNA
ICX038DNA
Spectral Sensitivity Characteristics
(Excludes lens characteristics and light source characteristics)
1.0
Ye
0.8
Cy
Relative Response
G
0.6
0.4
Mg
0.2
0.0
400
450
500
550
600
650
700
Wave Length [nm]
Sensor Readout Clock Timing Chart
V1
2.5
V2
Odd Field
V3
V4
33.5
1.6
2.5 2.5 2.5
0.2
V1
V2
Even Field
V3
V4
Unit : µs
– 16 –
– 17 –
CCD
OUT
V4
V3
V2
V1
HD
BLK
VD
FLD
493
494
525
1
2
3
4
5
520
Drive Timing Chart (Vertical Sync)
10
2 4 6
1 3 5
15
2 4 6
1 3 5
494
493
1 3 5
2 4 6
1 3 5
2 4 6
ICX038DNA
280
275
270
265
260
20
– 18 –
SUB
V4
V3
V2
V1
RG
H2
H1
BLK
HD
20
10
768
1
2
3
5
760
Drive Timing Chart (Horizontal Sync)
ICX038DNA
20
10
20
22
1
2
3
1
2
3
10
1
2
3
5
40
30
ICX038DNA
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
AAAA AAAA AAAA AAAA
AAAA AAAA AAAA AAAA
Upper ceramic
Lower ceramic
39N
29N
29N
0.9Nm
Low melting
point glass
Compressive strength
Shearing strength
Tensile strength
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.
– 19 –
ICX038DNA
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not
to perform the following actions as this may cause cracks.
• Applying repeated bending stress to the outer leads.
• Heating the outer leads for an extended period with a soldering iron.
• Rapidly cooling or heating the package.
• Applying any load or impact to a limited portion of the low melting point glass using tweezers or other
sharp tools.
• Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.
Note that the same cautions also apply when removing soldered products from boards.
e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
– 20 –
– 21 –
3
0.55
~
~
3
11.55
TIN PLATING
42 ALLOY
2.6g
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
0.3
M
1.778
3
14.6
11
10
A
18.0 ± 0.4
H
0.4
V
Cer-DIP
1
20
9.0
PACKAGE MATERIAL
PACKAGE STRUCTURE
B
0.7
7.55
0.4
0.83
15.1 ± 0.3
B'
0.8
0.46
0.7
C
0° to 9°
1.4
10
11
(R0.7)
(1.0)
17.6
φ1.4
1
20
(1.7)
9. The notch and the hole on the bottom must not be used for reference of fixing.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1°.
4. The center of the effective image area, relative to “B” and “B'” is
(H, V) = (9.0, 7.55) ± 0.15mm.
3. The bottom “C” of the package is the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
0.25
20pin DIP (600mil)
1.27
15.24
3.4 ± 0.3
4.0 ± 0.3
(4.0)
Unit: mm
~
Package Outline
ICX038DNA