Oct. 15, 2006 100BASE-LX/1000BASE-LX Spring-Latch SFP Transceiver (For 10km transmission with MCU version) Members of FlexonTM Family Compatible with FDA 21 CFR 1040.10 and 1040.11, Class I Compatible with Telcordia GR-468-CORE RoHS compliance Description Fiberxon FTM-3413C-SLCG SFP transceiver is high performance, cost effective module. It is designed for Gigabit Ethernet for 100BASE-LX/1000BASE-LX Features applications from 0.5m to 10km with SMF. Build-in PHY supporting SGMII Interface Build-in high performance MCU supporting The transceiver consists of two sections: The easier configuration standard Support more link status monitor, such as CRC, FTM-3413C-SLCG is built with SGMII interface. It package counter and Far End Fault Indication can operate as 100BASE-LX or 1000BASE-LX by (FEFI) software configuration or rate select hardware pin. Dual data-rate of 100BASE-LX/1000BASE-LX independently SFP part and the PHY part. operation 1310nm FP laser and PIN photo-detector The optical output can be disabled by a TTL logic 0.5m~10km transmission with SMF high-level input of Tx Disable, and the system also Standard serial ID information Compatible with can disable the module via I2C. Tx Fault is provided SFP MSA to indicate that degradation of the laser. Loss of SFP MSA package with duplex LC connector signal (LOS) output is provided to indicate the loss With Spring-Latch for high density application of an input optical signal of receiver or the link status Very low EMI and excellent ESD protection with partner. The system can also get the LOS(or +3.3V single power supply Link)/Disable/Fault information via I2C register Operating case temperature: 0 to +70°C access. Applications The standard serial ID information Compatible with Switch to Switch interface SFP MSA describes the transceiver’s capabilities, Switched backplane applications standard Router/Server interface information. The host equipment can access this Other optical transmission systems information via the 2-wire serial CMOS EEPROM interfaces, manufacturer and other protocol. For further information, please refer to SFP Standard Multi-Source Agreement (MSA). Compatible with SFP MSA Compatible with IEEE 802.3-2002 Building-in high performance MCU in this module, Compatible with IEEE 802.3ah-2004 Host can more easily configure all functions of Compatible with FCC 47 CFR Part 15, Class B FTM-3413C-SLCG. Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Page 1 of 10 125M/1.25G Spring-Latch SFP Transceiver 10km transmission Preliminary Datasheet Oct. 15, 2006 Regulatory Compliance The transceivers have been tested according to American and European product safety and electromagnetic compatibility regulations (See Table 1). For further information regarding regulatory certification, please refer to FlexonTM regulatory specification and safety guidelines, or contact with Fiberxon, Inc. America sales office listed at the end of the documentation. Table 1 - Regulatory Compliance Feature Standard Electrostatic Discharge MIL-STD-883E (ESD) to the Electrical Pins Method 3015.7 Electrostatic Discharge (ESD) IEC 61000-4-2 to the Duplex LC Receptacle GR-1089-CORE Performance Class 1(>500 V) Compatible with standards FCC Part 15 Class B Electromagnetic Interference (EMI) Immunity EN55022 Class B (CISPR 22B) Compatible with standards VCCI Class B IEC 61000-4-3 Compatible with standards FDA 21CFR 1040.10 and 1040.11 Laser Eye Safety EN60950, EN (IEC) 60825-1,2 Component Recognition Compatible with Class I laser product. TUV Certificate No. 50030043 UL and CSA UL file E223705 Absolute Maximum Ratings Stress in excess of the maximum absolute ratings can cause permanent damage to the module. Table 2 - Absolute Maximum Ratings Parameter Symbol Min. Max. Unit Storage Temperature TS -40 +85 °C Supply Voltage VCC -0.5 3.6 V - 5 95 % Operating Relative Humidity Recommended Operating Conditions Table 3- Recommended Operating Conditions Parameter Symbol Min. Operating Case Temperature TC 0 Power Supply Voltage VCC 3.10 Power Supply Current ICC Date Rate Typical 3.30 1000BASE-LX 1250 100BASE-LX 125 Max. Unit +70 °C 3.50 V 320 mA Notes Mbps Note 1: The max. power supply current after module work stable. Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Page 2 of 10 1 125M/1.25G Spring-Latch SFP Transceiver 10km transmission Preliminary Datasheet Oct. 15, 2006 Optical and Electrical Characteristics Table 4 - Optical and Electrical Characteristics Parameter Symbol Min. Typical Max. Unit 1310 1355 nm Notes Transmitter Centre Wavelength λC 1270 Average Output 1000BASE-LX P0ut -9.5 -3 Power 100BASE-LX P0ut -15 -8 P0ut@TX Disable Asserted Spectral Width 1000BASE-LX (RMS) 100BASE-LX Extinction Ratio 1000BASE-LX (20%～80%) 100BASE-LX Total Jitter at 1000BASE-LX TP2 100BASE-LX Deterministic 1000BASE-LX Jitter at TP2 100BASE-LX Output Optical Eye Input Swing Differential Input Differential Impedance TX Fault 4 7.7 9 dBm 0.26 3 0.481 JT 0.4 0.250 JD 0.305 200 ZIN 80 2 2 dB tr/tf VIN 2 nm ns 3 UI 4 UI 4 Compatible with IEEE 802.3ah-2004 (SGMII Series interface) TX Disable -45 σ EX Rise/Fall Time Data P0ut dBm 100 5 2100 mV 120 Ω Disable 2.0 Vcc Enable Vee Vee+0.8 Fault 2.0 Vcc Normal Vee Vee+0.5 6 V V Receiver Centre Wavelength λC 1260 1310 1570 Receiver 1000BASE-LX -22 Sensitivity 100BASE-LX -28 Receiver 1000BASE-LX -3 Overload 100BASE-LX -8 Return Loss LOS De-Assert LOS Assert 100BASE-LX 1000BASE-LX 100BASE-LX LOSA LOS Hysteresis -29 -35 Total Jitter at 1000BASE-LX TP4 100BASE-LX Deterministic 1000BASE-LX Jitter at TP4 100BASE-LX JT JD Fiberxon Proprietary and Confidential, Do Not Copy or Distribute 8 7 8 dBm dBm -45 0.5 7 dB -23 LOSD dBm dBm 12 1000BASE-LX nm 4.5 0.749 0.51 0.462 0.305 dB UI 4 UI 4 Page 3 of 10 125M/1.25G Spring-Latch SFP Transceiver 10km transmission Preliminary Datasheet Data Output Swing Differential 370 2000 High 2.0 Vcc+0.3 Low Vee Vee+0.5 VOUT (SGMII Series Interface) LOS Oct. 15, 2006 mV 6 V Notes: 2. The optical power is launched into SMF 9/125um. 3. Unfiltered, measured with 8B/10B code for 1.25Gbps and 4B/5B code for 125Mbps 4. Meet the specified maximum output jitter requirements if the specified maximum input jitter is present. 5. Measured with 8B/10B code for 1.25Gbps and 4B/5B code for 125Mbps. 6. PECL logic, internally AC coupled. 7. Measured with 8B/10B code for 1.25Gbps, worst-case extinction ratio, BER ≤1×10-12. 8. Measured with 4B/5B code for 125Mbps, worst-case extinction ratio, BER ≤1×10-10. EEPROM Information The SFP MSA defines a 256-byte memory map in EEPROM describing the transceiver’s capabilities, standard interfaces, manufacturer, and other information, which is accessible over a 2-wire serial interface at the 8-bit address 1010000X (A0h). For the memory contents, please refer to Table 5. Table 5 - EEPROM Serial ID Memory Contents (A0h) Addr. Field Size (Bytes) Name of Field Hex Description 0 1 Identifier 03 SFP 1 1 Ext. Identifier 04 MOD4 2 1 Connector 07 LC 3—10 8 Transceiver 00 00 00 12 00 00 00 00 11 1 Encoding 01 8B10B 12 1 BR, nominal 0D 1.25Gbps 13 1 Reserved 00 14 1 Length (9um)-km 0A 15 1 Length (9um) 64 16 1 Length (50um) 00 17 1 Length (62.5um) 00 18 1 Length (copper) 00 19 1 Reserved 20—35 16 Vendor name 36 1 Reserved 37—39 3 Vendor OUI 40—55 16 Vendor PN 56—59 4 Vendor rev xx xx xx xx 60—61 2 Wavelength 05 1E 62 1 Reserved Transmitter Code 10km 00 46 49 42 45 52 58 4F 4E 20 49 4E 43 2E 20 20 20 “FIBERXON INC. “(ASCⅡ) 00 00 00 00 46 54 4D 2D 33 34 31 33 43 2D 53 4C 43 47 20 20 “FTM-3413C-SLCG” (ASCⅡ) ASCⅡ( “31 30 20 20” means 1.0 revision) 1310nm 00 Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Page 4 of 10 125M/1.25G Spring-Latch SFP Transceiver 10km transmission Preliminary Datasheet 63 1 CC BASE 64—65 2 Options 00 1A 66 1 BR, max 00 67 1 BR, min 00 68—83 16 Vendor SN 84—91 8 92—94 3 Reserved 00 00 00 95 1 CC_EXT xx 96—154 58 Vendor specific 155 1 Reserved 156-247 xx Check sum of bytes 0 - 62 LOS, TX_FAULT and TX_DISABLE xx xx xx xx xx xx xx xx ASCⅡ xx xx xx xx xx xx xx xx Vendor date codexx xx xx xx xx xx 20 20 Oct. 15, 2006 Year(2 bytes), Month(2 bytes), Day (2 bytes) Check sum of bytes 64 - 94 Read only Vendor specific 248 1 Status Module status indication 249 1 CFG0 Work mode configuration 250 1 CFG1 Work mode configuration 251 1 CFG2 Work mode configuration 252 1 Status Module status indication 253 1 Reserved 254 1 PSWL Password entry 255 1 PSWH Password entry Note: The “xx” byte should be filled in according to practical case. For more information, please refer to the related document of SFP Multi-Source Agreement (MSA) and application note of FTM-3413C-SLCG. Easier Configuration Designing-in a high performance MCU in FTM-3413C-SLCG, host can configure Fiberxon’s SGMII series product easily. For FTM-3413C-SLCG, host only need access few registers of A0H via I2C to configure SGMII series module, such as speed-selection, Auto-negotiation, LOS/Link detection, TX disable, FEFI/RFI and CRC counter function support. Host can get inner status via access specific register of FTM-3413C-SLCG. The operation data rate can be configured via hardware pin and I2C bus independently. For more detailed information, please refer to application note of FTM-3413C-SLCG. Recommended Host Board Power Supply Circuit Figure 1 shows the recommended host board power supply circuit. Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Page 5 of 10 125M/1.25G Spring-Latch SFP Transceiver 10km transmission Preliminary Datasheet Oct. 15, 2006 Figure 1, Recommended Host Board Power Supply Circuit Recommended Interface Circuit Figure 2 shows the recommended interface circuit. SGMII Interface Host Board SFP Module VccT 10 KΩ TX Disable TX Fault Z=50Ω 100Ω SGMII/802.3z SerDes MAC Controller 100Ω TD + Laser driver 100Ω Z=50Ω TD - Z=50Ω RD + Z=50Ω RD - Controller PHY IC 100Ω Amplifier Vcc(+3.3V) 6×4.7 K to10KΩ Rate selection LOS MOD-DEF2 MOD-DEF1 MOD-DEF0 MCU Figure 2, Recommended Interface Circuit Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Page 6 of 10 125M/1.25G Spring-Latch SFP Transceiver 10km transmission Preliminary Datasheet Oct. 15, 2006 Pin Definitions Figure 3 below shows the pin numbering of SFP electrical interface. The pin functions are described in Table 6 with some accompanying notes. P in 2 0 T O P V IE W OF BOARD P in 1 1 P in 1 0 B O T T O M V IE W OF BOARD P in 1 Figure 3, Pin View Table 6– Pin Function Definitions Pin No. Name 1 VeeT 2 TX Fault 3 Function Plug Seq. Notes Transmitter Ground 1 Transmitter Fault Indication 3 Note 1 TX Disable Transmitter Disable 3 Note 2 4 MOD-DEF2 Module Definition 2 3 Note 3 5 MOD-DEF1 Module Definition 1 3 Note 3 6 MOD-DEF0 Module Definition 0 3 Note 3 7 Rate Select 3 Note 7 8 LOS Loss of Signal 3 Note 4 9 VeeR Receiver Ground 1 10 VeeR Receiver Ground 1 11 VeeR Receiver Ground 1 12 RD- Inv. Received Data Out 3 Note 5 13 RD+ Received Data Out 3 Note 5 14 VeeR Receiver Ground 1 15 VccR Receiver Power 2 16 VccT Transmitter Power 2 17 VeeT Transmitter Ground 1 18 TD+ Transmit Data In 3 Note 6 19 TD- Inv. Transmit Data In 3 Note 6 20 VeeT Transmitter Ground 1 100Base-LX/1000Base-LX selection Notes: 1. TX Fault is an open collector output, which should be pulled up with a 4.7k~10kΩ resistor on the host Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Page 7 of 10 125M/1.25G Spring-Latch SFP Transceiver 10km transmission Preliminary Datasheet Oct. 15, 2006 board to a voltage between 2.0V and Vcc+0.3V. Logic 0 indicates normal operation; logic 1 indicates a laser fault of some kind. In the low state, the output will be pulled to less than 0.8V. 2. TX Disable is an input that is used to shut down the transmitter optical output. It is pulled up within the module with a 4.7k~10kΩ resistor. Its states are: Low (0~0.8V): Transmitter on (>0.8V, <2.0V): Undefined High (2.0~3.465V): Transmitter Disabled Open: Transmitter Disabled 3. MOD-DEF 0,1,2 are the module definition pins. They should be pulled up with a 4.7k~10kΩ resistor on the host board. The pull-up voltage shall be VccT or VccR. MOD-DEF 0 is grounded by the module to indicate that the module is present MOD-DEF 1 is the clock line of two wire serial interface for serial ID MOD-DEF 2 is the data line of two wire serial interface for serial ID 4. LOS is an open collector output, which should be pulled up with a 4.7k~10kΩ resistor on the host board to a voltage between 2.0V and Vcc+0.3V. Logic 0 indicates normal operation; logic 1 indicates loss of signal. In the low state, the output will be pulled to less than 0.8V. 5. These are the differential receiver output. They are internally AC-coupled 100Ω differential lines which should be terminated with 100Ω (differential) at host with SGMII interface. 6. These are the differential transmitter inputs. They are AC-coupled, differential lines with 100Ω differential termination inside the module. 7. When hardware rate selection has higher priority than software configuration via I2C, this pin can be used to select bit rate by host hardware. SGMII Interface SGMII uses two data signals and two clock signals to convey frame data and link rate information between a 100/1000 PHY and an Ethernet MAC. The data signals operate at 1.25 Gbaud and the clocks operate at 625 MHz (a DDR interface). Due to the speed of operation, each of these signals is realized as a differential pair thus providing signal integrity while minimizing system noise. However, specific implementations may desire to recover clock from the data rather than use the supplied clock, such as in our transceiver design. This operation is allowed. Clearly, SGMII’s 1.25 Gbaud transfer rate is excessive for interfaces operating at 100 Mbps. When these situations occur, the interface “elongates” the frame by replicating each frame byte 10 times for 100 Mbps. This frame elongation takes place “above” the 802.3z PCS layer, thus the start frame delimiter only appears once per frame.The 802.3z PCS layer may remove the first byte of the “elongated” frame. For further information about how to use transceivers with SGMII interface, please refer to the application note of FTM-3413C-SLCG Mechanical Design Diagram The mechanical design diagram is shown in Figure 4. Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Page 8 of 10 125M/1.25G Spring-Latch SFP Transceiver 10km transmission Preliminary Datasheet Oct. 15, 2006 Figure 4, Mechanical Design Diagram of the SFP with Spring- Latch Ordering information FTM 3 4 1 Medium 3 C SL Receptacle C : CL 3 : 1310nm Function 4 : PHY FTM-3413C-SLCG G G : RoHS compliance MCU C: MCU version Package SL: SFP with spring latch Data rate 13: 125M/1.25G Product part Number C Media Data Rate(Mbps) Distance(km) Note Single mode fiber 125/1250 10 MCU version Related SGMII SFP Products Product part Number Media Data Rate(Mbps) Transmission Distance(km) FTM-C012R-LG Cat. 5 Copper 125/1250 0.1 FTM-3413C-SLG Single mode fiber 125/1250 10 FTM-3401C-SL2G Multi-Mode Fiber 125 2 FTM-3401C-SL10G Single mode fiber 125 10 FTM-3413C-SL05G Multi-Mode Fiber 125/1250 0.5 Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Page 9 of 10 125M/1.25G Spring-Latch SFP Transceiver 10km transmission Preliminary Datasheet Oct. 15, 2006 Related Documents For further information, please refer to the following documents: ■ Fiberxon Spring-Latch SFP Installation Guide ■ Fiberxon SFP Application Notes ■ SFP Multi-Source Agreement (MSA) Obtaining Document You can visit our website: http://www.fiberxon.com Or contact with Fiberxon, Inc. America Sales Office listed at the end of documentation to get the latest documents. Revision History Revision Rev. 1a Initiate Review Henry.Xiao Tripper.Huang Approve Walker.Wei Subject Initial datasheet Release Date Oct. 15, 2006 © Copyright Fiberxon Inc. 2006 All Rights Reserved. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change Fiberxon product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Fiberxon or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environment may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN ”AS IS” BASIS. In no event will Fiberxon be liable for damages arising directly from any use of the information contained in this document. Contact U.S.A. Headquarter: 5201 Great America Parkway, Suite 340 Santa Clara, CA 95054 U. S. A. Tel: 408-562-6288 Fax: 408-562-6289 Or visit our website: http://www.fiberxon.com Fiberxon Proprietary and Confidential, Do Not Copy or Distribute Page 10 of 10