Revised January 2003 FIN1104 LVDS 4 Port High Speed Repeater General Description Features This 4 port repeater is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The FIN1104 accepts and outputs LVDS levels with a typical differential output swing of 330 mV which provides low EMI at ultra low power dissipation even at high frequencies. The FIN1104 provides a VBB reference for AC coupling on the inputs. In addition the FIN1104 can directly accept LVPECL, HSTL, and SSTL-2 for translation to LVDS. ■ Greater than 800 Mbps data rate ■ 3.3V power supply operation ■ 3.5 ps maximum random jitter and 135 ps maximum deterministic jitter ■ Wide rail-to-rail common mode range ■ LVDS receiver inputs accept LVPECL, HSTL, and SSTL-2 directly ■ Ultra low power consumption ■ 20 ps typical channel-to-channel skew ■ Power off protection ■ > 7.5 kV HBM ESD Protection ■ Meets or exceeds the TIA/EIA-644-A LVDS standard ■ Available in space saving 24-Lead TSSOP package ■ Open circuit fail safe protection ■ VBB reference output Ordering Code: Order Number FIN1104MTC Package Number Package Description MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pin Descriptions Pin Name Connection Diagram Description RIN1+, RIN2+, RIN3+, RIN4+ Non-inverting LVDS Input RIN1−, RIN2−, RIN3−, RIN4− Inverting LVDS Input DOUT1+, DOUT2+, Non-inverting Driver Output DOUT3+, DOUT4+ DOUT1−, DOUT2−, Inverting Driver Output DOUT3−, DOUT4− EN Driver Enable Pin for All Output EN Inverting Driver Enable Pin for all Outputs VCC Power Supply GND Ground VBB Reference Voltage Output © 2003 Fairchild Semiconductor Corporation DS500656 www.fairchildsemi.com FIN1104 LVDS 4 Port High Speed Repeater January 2002 FIN1104 Function Table Functional Diagram Inputs Outputs EN EN DIN+ DIN− DOUT+ H L H L H L H L L H L H Fail Safe Case DOUT− H L H L X H X X Z Z L X X X Z Z H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +4.6V LVDS DC Input Voltage (VIN) −0.5V to +4.6V LVDS DC Output Voltage (VOUT) −0.5V to +4.6V Driver Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Recommended Operating Conditions Supply Voltage (VCC) Continuous 10 mA Voltage (|VID|) −65°C to +150°C 260°C ESD (Human Body Model) 7500V ESD (Machine Model) (0V + |VID |/2) to (VCC − |VID|/2) Range (VIC) Lead Temperature (TL) (Soldering, 10 seconds) 100 mV to VCC Common Mode Voltage 150°C Max Junction Temperature (TJ) 3.0V to 3.6V Magnitude of Differential −40°C to +85°C Operating Temperature (TA) Note 1: The “Absolute Maximum Ratings”: are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. 400V DC Electrical Characteristics Symbol Parameter Min Test Conditions Typ Max (Note 2) Units VTH Differential Input Threshold HIGH See Figure 1; VIC = +0.05V, +1.2V, or VCC − 0.05V VTL Differential Input Threshold LOW See Figure 1; VIC = +0.05V, +1.2V, or VCC − 0.05V VIH Input HIGH Voltage (EN or EN) 2.0 VCC V VIL Input LOW Voltage (EN or EN) GND 0.8 V VOD Output Differential Voltage 250 330 450 mV ∆VOD VOD Magnitude Change from 25 mV 1.125 1.23 1.375 V 25 mV −3.4 −6 mA ±3.4 ±6 mA ±20 µA Differential LOW-to-HIGH RL = 100 Ω, Driver Enabled, VOS Offset Voltage See Figure 2 ∆VOS Offset Magnitude Change from 100 −100 Differential LOW-to-HIGH IOS Short Circuit Output Current DOUT + = 0V and DOUT− = 0V, Driver Enabled VOD = 0V, Driver Enabled IIN mV mV Input Current (EN, EN, DINx+, DINx−) VIN = 0V to VCC, Other Input = VCC or 0V (for Differential Inputs) IOFF Power Off Input or Output Current VCC = 0V, VIN or VOUT = 0V to 3.6V ±20 µA ICCZ Disabled Power Supply Current Drivers Disabled 5.4 11 mA ICC Power Supply Current Drivers Enabled, Any Valid Input Condition 30.4 41 mA IOZ Disabled Output Leakage Current Driver Disabled, DOUT+ = 0V to 3.6V or ±20 µA VIC Common Mode Voltage Range |VID| = 100 mV to VCC VCC − (|VID|/2) V CIN Input Capacitance DOUT − = 0V to3.6V COUT Output Capacitance VBB Output Reference Voltage 0V + |VID|/2 Enable Input 2.6 LVDS Input 2.1 pF 2.8 VCC = 3.3V, IBB = 0 to −275 µA 1.125 1.2 pF 1.375 V Note 2: All typical values are at TA = 25°C and with VCC = 3.3V. 3 www.fairchildsemi.com FIN1104 Absolute Maximum Ratings(Note 1) FIN1104 AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol tPLHD Parameter Test Conditions Differential Output Propagation Delay LOW-to-HIGH tPHLD Differential Output Propagation Delay HIGH-to-LOW RL = 100 Ω, CL = 5 pF, Min Typ 1.1 1.75 ns 0.75 1.1 1.75 ns 0.29 0.4 0.58 ns 0.29 0.4 0.58 ns 0.2 ns 0.15 ns Differential Output Rise Time (20% to 80%) VID = 200 mV to 450 mV, tTHLD Differential Output Fall Time (80% to 20%) VIC = |V ID|/2 to VCC − (|VID|/2), tSK(P) Pulse Skew |tPLH - tPHL| Duty Cycle = 50%, 0.02 tSK(LH), Channel-to-Channel Skew See Figure 1 and Figure 3 0.02 tSK(HL) (Note 4) tSK(PP) Part-to-Part Skew (Note 5) fMAX Maximum Frequency (Note 6)(Note 7) tPZHD Differential Output Enable Time 0.02 0.5 400 from Z to HIGH tPHZD Differential Output Enable Time from Z to LOW RL = 100 Ω, CL = 5 pF, Differential Output Disable Time See Figure 2 and Figure 3 from HIGH to Z tPLZD Differential Output Disable Time from LOW to Z tDJ tRJ Units 0.75 tTLHD tPZLD Max (Note 3) LVDS Data Jitter, VID = 300 mV, PRBS = 223 - 1, Deterministic VIC = 1.2V at 800 Mbps LVDS Clock Jitter, VID = 300 mV, Random (RMS) VIC = 1.2V at 400 MHz 800 ns MHz 2.2 5 ns 2.5 5 ns 1.8 5 ns 2.1 5 ns 85 135 ps 2.1 3.5 ps Note 3: All typical values are at TA = 25°C and with VCC = 3.3V. Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either Low-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 6: Passing criteria for maximum frequency is the output VOD > 200 mV and the duty cycle is 45% to 55% with all channels switching. Note 7: Output loading is transmission line environment only; CL is < 1 pF of stray test fixture capacitance. FIGURE 1. Differential Receiver Voltage Definitions and Propagation and Transition Time Test Circuit Note A: All LVDS input pulses have frequency = 10 MHz, t R or tF < = 0.5 ns Note B: CL includes all probe and test fixture capacitances FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit FIGURE 2. Differential Driver DC Test Circuit www.fairchildsemi.com 4 FIN1104 FIGURE 4. AC Waveform Note A: All LVTTL input pulses have frequency = 10MHz, tR or tF < = 2 ns Note B: CL includes all probe and jig capacitances FIGURE 5. Differential Driver Enable and Disable Circuit FIGURE 6. Enable and Disable AC Waveforms 5 www.fairchildsemi.com FIN1104 LVDS 4 Port High Speed Repeater 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6