TI TMS320VC5503PGE

TMS320VC5503 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS245C
April 2004 − Revised January 2005
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
This page was intentionally left blank
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS245B device-specific data
sheet to make it an SPRS245C revision.
Scope: Added Section 4.1, Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability; added
Package Addendum, etc.
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
Global:
− moved “Package Thermal Resistance Characteristics” section to Section 6, Mechanical Data
− added Package Addendum
17
Table 2−3, Signal Descriptions:
− HPI.HRDY: changed value of “I/O/Z” column from “O/Z” to “O”
35
Section 3.5.1, External Bus Selection Register (EBSR):
− appended “After reset, the parallel port should be selected to function in either EMIF mode or HPI mode. Dynamic
switching of the parallel port, once configured, is not recommended.” to “The reset value of the parallel port mode bit field
is determined by ...” paragraph
57
Table 3−27, I2C Module Registers:
− 0x3C0B: changed “I2C General-Purpose Register” (I2CGPIO) to “Reserved”
63
Section 4:
− renamed section from “Documentation Support” to “Support”
63
Section 4, Support:
− added Section 4.1, Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability
− added Section 4.1.1, Initialization Requirements for Boundary Scan Test
− added Section 4.1.2, Boundary Scan Description Language (BSDL) Model
63
Added section title “4.2 Documentation Support”
64
Updated Section 4.3, Device and Development-Support Tool Nomenclature
111
Figure 5−32, EHPI Nonmultiplexed Read/Write Timings:
− updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
112
Figure 5−33, EHPI Multiplexed Memory (HPID) Read/Write Timings Without Autoincrement:
− updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
113
Figure 5−34, EHPI Multiplexed Memory (HPID) Read Timings With Autoincrement:
− updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
114
Figure 5−35, EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement:
− updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
115
Figure 5−36, EHPI Multiplexed Register Read/Write Timings:
− updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
119
Section 6, Mechanical Data:
− added new Section 6.1, Package Thermal Resistance Characteristics
− added new Section 6.2, Packaging Information
April 2004 − Revised January 2005
SPRS245C
3
Revision History
4
SPRS245C
April 2004 − Revised January 2005
Contents
Contents
Section
Page
1
TMS320VC5503 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Terminal Assignments for the GHH Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Pin Assignments for the PGE Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
13
15
17
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
On-Chip Read-Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4
Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
DMA Channel Control Register (DMA_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5
Configurable External Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
External Bus Selection Register (EBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2
Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3
Parallel Port Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
General-Purpose Input/Output (GPIO) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
Dedicated General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2
Address Bus General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3
EHPI General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
System Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
Peripheral Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.1
IFR and IER Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.2
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.3
Waking Up From IDLE Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.4
Idling Clock Domain When External Parallel Bus Operating in EHPI Mode . . . . . .
27
28
28
28
29
31
32
32
33
34
34
35
37
38
40
40
41
43
45
46
48
59
60
62
62
62
4
Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability . . . . . . . . . . . . . . . . .
4.1.1
Initialization Requirements for Boundary Scan Test . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2
Boundary Scan Description Language (BSDL) Model . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
TMS320VC5503 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
63
63
63
63
64
64
April 2004 − Revised January 2005
SPRS245C
5
Contents
Section
5
6
6
Page
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
Recommended Operating Conditions for CVDD = 1.2 V (108 MHz) . . . . . . . . . . . . .
5.2.2
Recommended Operating Conditions for CVDD = 1.35 V (144 MHz) . . . . . . . . . . . .
5.2.3
Recommended Operating Conditions for CVDD = 1.6 V (200 MHz) . . . . . . . . . . . . .
5.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CVDD = 1.2 V (108 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CVDD = 1.35 V (144 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CVDD = 1.6 V (200 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1
Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.2
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.3
Clock Generation in Bypass Mode (DPLL Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.4
Clock Generation in Lock Mode (DPLL Synthesis Enabled) . . . . . . . . . . . . . . . . . . .
5.6.5
Real-Time Clock Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
Memory Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
Asynchronous Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2
Synchronous DRAM (SDRAM) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8
Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.1
Power-Up Reset (On-Chip Oscillator Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.2
Power-Up Reset (On-Chip Oscillator Inactive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.3
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
External Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10
Wake-Up From IDLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11
XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12
General-Purpose Input/Output (GPIOx) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13
TIN/TOUT Timings (Timer0 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14
Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.1
McBSP0 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.2
McBSP1 and McBSP2 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.3
McBSP as SPI Master or Slave Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.4
McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15
Enhanced Host-Port Interface (EHPI) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.16
I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
72
72
73
73
74
75
76
77
78
78
81
89
89
90
91
92
92
93
94
95
96
96
98
101
109
110
116
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
119
119
119
SPRS245C
65
65
66
66
67
68
69
69
70
April 2004 − Revised January 2005
Figures
List of Figures
Figure
Page
2−1
2−2
179-Terminal GHH Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144-Pin PGE Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
15
3−1
3−2
Block Diagram of the TMS320VC5503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320VC5503 Memory Map (PGE Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
29
3−3
3−4
TMS320VC5503 Memory Map (GHH Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA_CCR Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
33
3−5
External Bus Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3−6
3−7
Parallel Port Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port (EMIF) Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
39
3−8
3−9
I/O Direction Register (IODIR) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Data Register (IODATA) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
41
3−10
Address/GPIO Enable Register (AGPIOEN) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
3−11
3−12
Address/GPIO Direction Register (AGPIODIR) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address/GPIO Data Register (AGPIODATA) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
42
3−13
3−14
EHPI GPIO Enable Register (EHPIGPIOEN) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI GPIO Direction Register (EHPIGPIODIR) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
3−15
3−16
EHPI GPIO Data Register (EHPIGPIODATA) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Register Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
45
3−17
IFR0 and IER0 Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
3−18
IFR1 and IER1 Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
4−1
Device Nomenclature for the TMS320VC5503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
5−1
5−2
3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
73
5−3
5−4
Bypass Mode Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiply-by-N Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
77
5−5
5−6
Real-Time Clock Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Memory Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
79
5−7
Asynchronous Memory Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
5−8
5−9
Three SDRAM Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Three SDRAM WRT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
83
5−10
5−11
SDRAM ACTV Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDRAM DCAB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
85
5−12
SDRAM REFR Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
5−13
5−14
SDRAM MRS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDRAM Self-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
88
April 2004 − Revised January 2005
SPRS245C
7
Figures
Figure
5−15
5−16
5−17
5−18
5−19
5−20
5−21
5−22
5−23
5−24
5−25
5−26
5−27
5−28
5−29
5−30
5−31
5−32
5−33
5−34
5−35
5−36
5−37
5−38
8
Page
Power-Up Reset (On-Chip Oscillator Active) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Reset (On-Chip Oscillator Inactive) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up From IDLE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output (IOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIN/TOUT Timings When Configured as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIN/TOUT Timings When Configured as Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HINT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI Nonmultiplexed Read/Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI Multiplexed Memory (HPID) Read/Write Timings Without Autoincrement . . . . . . . . . . . . . . . .
EHPI Multiplexed Memory (HPID) Read Timings With Autoincrement . . . . . . . . . . . . . . . . . . . . . . . .
EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement . . . . . . . . . . . . . . . . . . . . . . . .
EHPI Multiplexed Register Read/Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRS245C
89
90
91
92
92
93
94
95
95
100
100
102
104
106
108
109
111
111
112
113
114
115
117
118
April 2004 − Revised January 2005
Tables
List of Tables
Table
Page
2−1
2−2
2−3
Pin Assignments for the GHH Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments for the PGE Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
16
17
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
3−10
3−11
3−12
3−13
3−14
3−15
3−16
3−17
3−18
3−19
3−20
3−21
3−22
3−23
3−24
3−25
3−26
3−27
3−28
3−29
3−30
3−31
3−32
DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320VC5503 Parallel Port Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Direction Register (IODIR) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Data Register (IODATA) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address/GPIO Enable Register (AGPIOEN) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address/GPIO Direction Register (AGPIODIR) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address/GPIO Data Register (AGPIODATA) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI GPIO Enable Register (EHPIGPIOEN) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI GPIO Direction Register (EHPIGPIODIR) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI GPIO Data Register (EHPIGPIODATA) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Idle Control, Status, and System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Serial Port #0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Serial Port #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Serial Port #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFR0 and IER0 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFR1 and IER1 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
31
33
35
37
40
41
41
42
42
43
43
44
45
46
48
48
49
52
53
53
54
55
56
57
57
57
58
58
59
60
61
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
Recommended Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKIN Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended RTC Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Memory Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Memory Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
75
75
76
76
77
78
78
April 2004 − Revised January 2005
SPRS245C
9
Tables
Table
Page
5−9
5−10
5−11
5−12
5−13
5−14
5−15
5−16
5−17
5−18
5−19
5−20
5−21
5−22
5−23
5−24
5−25
5−26
5−27
5−28
5−29
5−30
5−31
5−32
5−33
5−34
5−35
5−36
5−37
5−38
5−39
5−40
Synchronous DRAM Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous DRAM Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Reset (On-Chip Oscillator Active) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics . . . . . . . . . . . . . . . . . . . .
Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up From IDLE Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XF Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIN/TOUT Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIN/TOUT Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP0 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP0 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP1 and McBSP2 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP1 and McBSP2 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .
McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Signals (SDA and SCL) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Signals (SDA and SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
81
89
90
90
91
91
92
92
93
94
94
95
95
96
97
98
99
101
101
103
103
105
105
107
107
109
109
110
110
116
118
6−1
6−2
Thermal Resistance Characteristics (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance Characteristics (Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
119
119
10
SPRS245C
April 2004 − Revised January 2005
Features
TMS320VC5503 Features
D High-Performance, Low-Power, Fixed-Point
D
D
D
D
D
D
TMS320C55x Digital Signal Processor
− 9.26-, 6.95-, 5-ns Instruction Cycle Time
− 108-, 144-, 200-MHz Clock Rate
− One/Two Instruction(s) Executed per
Cycle
− Dual Multipliers [Up to 400 Million
Multiply-Accumulates per Second
(MMACS)]
− Two Arithmetic/Logic Units (ALUs)
− Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write
Buses
32K x 16-Bit On-Chip RAM, Composed of:
− 64K Bytes of Dual-Access RAM (DARAM)
8 Blocks of 4K × 16-Bit
64K Bytes of One-Wait-State On-Chip ROM
(32K × 16-Bit)
8M × 16-Bit Maximum Addressable External
Memory Space (Synchronous DRAM)
16-Bit External Parallel Bus Memory
Supporting Either:
− External Memory Interface (EMIF) With
GPIO Capabilities and Glueless Interface
to:
− Asynchronous Static RAM (SRAM)
− Asynchronous EPROM
− Synchronous DRAM (SDRAM)
− 16-Bit Parallel Enhanced Host-Port
Interface (EHPI) With GPIO Capabilities
Programmable Low-Power Control of Six
Device Functional Domains
On-Chip Scan-Based Emulation Logic
D On-Chip Peripherals
D
D
D
D
D
− Two 20-Bit Timers
− Watchdog Timer
− Six-Channel Direct Memory Access
(DMA) Controller
− Three Multichannel Buffered Serial Ports
(McBSPs)
− Programmable Phase-Locked Loop
Clock Generator
− Seven (LQFP) or Eight (BGA) GeneralPurpose I/O (GPIO) Pins and a GeneralPurpose Output Pin (XF)
− Inter-Integrated Circuit (I2C) Multi-Master
and Slave Interface
− Real-Time Clock (RTC) With Crystal
Input, Separate Clock Domain, Separate
Power Supply
IEEE Std 1149.1† (JTAG) Boundary Scan
Logic
Packages:
− 144-Terminal Low-Profile Quad Flatpack
(LQFP) (PGE Suffix)
− 179-Terminal MicroStar BGA (Ball Grid
Array) (GHH Suffix)
1.2-V Core (108 MHz), 2.7-V – 3.6-V I/Os
1.35-V Core (144 MHz), 2.7-V – 3.6-V I/Os
1.6-V Core (200 MHz), 2.7-V – 3.6-V I/Os
ADVANCE INFORMATION
1
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
April 2004 − Revised January 2005
SPRS245C
11
Introduction
2
Introduction
This section describes the main features of the TMS320VC5503, lists the pin assignments, and describes the
function of each pin. This data manual also provides a detailed description section, electrical specifications,
parameter measurement information, and mechanical data about the available packaging.
NOTE: This data manual is designed to be used in conjunction with theTMS320C55x DSP Functional
Overview (literature number SPRU312), the TMS320C55x DSP CPU Reference Guide (literature
number SPRU371), and the TMS320C55x DSP Peripherals Overview Reference Guide (literature
number SPRU317).
2.1
Description
ADVANCE INFORMATION
The TMS320VC5503 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation
CPU processor core. The C55x DSP architecture achieves high performance and low power through
increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus
structure that is composed of one program bus, three data read buses, two data write buses, and additional
buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data
reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers
per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication
in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of
the ALUs is under instruction set control, providing the ability to optimize parallel activity and power
consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions
for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources,
and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution
of conditional instructions.
The 64K bytes of on-chip memory on TMS320VC5503 is sufficient for many small hand-held appliances,
portable personal appliances, gaming devices, and personal medical care appliances. Many of these
appliances typically require 64K bytes or smaller amount of on-chip memory and need to operate in standby
mode for more than 60% to 70% of the time. For applications that require more than 64K bytes of on-chip
memory but less than 128K bytes of memory, Texas Instruments (TI) offers the TMS320VC5507 device, which
is based on the TMS320C55x DSP core.
The general-purpose input and output functions provide sufficient pins for status, interrupts, and bit I/O for
LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a
microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media
is supported through three McBSPs.
The 5503 peripheral set includes an external memory interface (EMIF) that provides glueless access to
asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as
synchronous DRAM. Additional peripherals include real-time clock, watchdog timer, and I2C multi-master and
slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to
a variety of industry-standard serial devices, and multichannel communication with up to 128 separately
enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host
processor access to 32K bytes of internal memory on the 5503. The HPI can be configured in either
multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The
DMA controller provides data movement for six independent channel contexts without CPU intervention,
providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight
dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also
included.
C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, and XDS510 are trademarks of Texas Instruments.
12
SPRS245C
April 2004 − Revised January 2005
Introduction
The 5503 is supported by the industry’s award-winning eXpressDSP, Code Composer Studio Integrated
Development Environment (IDE), DSP/BIOS, Texas Instruments’ algorithm standard, and the industry’s
largest third-party network. The Code Composer Studio IDE features code generation tools including a
C Compiler and Visual Linker, simulator, RTDX, XDS510 emulation device drivers, and evaluation
modules. The 5503 is also supported by the C55x DSP Library which features more than 50 foundational
software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support
libraries.
2.2
Pin Assignments
Figure 2−1 illustrates the ball locations for the 179-pin ball grid array (BGA) package and is used in conjunction
with Table 2−1 to locate signal names and ball grid numbers.
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core. VSS is the ground for
both the I/O pins and the core. RCVDD and RDVDD are RTC module core and I/O supply, respectively.
ADVANCE INFORMATION
2.2.1 Terminal Assignments for the GHH Package
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 2−1. 179-Terminal GHH Ball Grid Array (Bottom View)
April 2004 − Revised January 2005
SPRS245C
13
Introduction
ADVANCE INFORMATION
Table 2−1. Pin Assignments for the GHH Package
14
BALL #
SIGNAL NAME
BALL #
SIGNAL
NAME
BALL #
SIGNAL
NAME
BALL #
SIGNAL
NAME
A2
VSS
D5
GPIO5
H2
DVDD
L13
D15
A3
GPIO4
D6
DR0
H3
A19
L14
CVDD
A4
DVDD
D7
CLKR1
H4
C4
M1
C10
A5
FSR0
D8
DR1
H5
C5
M2
C13
A6
CVDD
D9
DVDD
H10
DVDD
M3
VSS
A7
FSR1
D10
FSX2
H11
A’[0]
M4
CVDD
A8
DVDD
D11
VSS
H12
RESET
M5
VSS
A9
CLKR2
D12
NC
H13
SDA
M6
A5
A10
DR2
D13
NC
H14
SCL
M7
A1
A11
DX2
D14
NC
J1
C6
M8
A15
A12
RTCINX1
E1
GPIO1
J2
DVDD
M9
D3
A13
RDVDD
E2
GPIO2
J3
C7
M10
D6
A14
RDVDD
E3
DVDD
J4
C8
M11
CVDD
B1
VSS
E4
VSS
J5
CVDD
M12
DVDD
B2
CVDD
E5
VSS
J10
CVDD
M13
VSS
B3
GPIO3
E6
DVDD
J11
CVDD
M14
D12
B4
TIN/TOUT0
E7
DX0
J12
TRST
N1
VSS
B5
CLKR0
E8
FSX1
J13
TCK
N2
VSS
B6
FSX0
E9
DX1
J14
TMS
N3
A13
B7
CVDD
E10
NC
K1
A18
N4
A10
B8
CVDD
E11
NC
K2
C9
N5
A7
B9
VSS
E12
VSS
K3
C11
N6
DVDD
B10
CLKX2
E13
VSS
K4
VSS
N7
CVDD
B11
VSS
E14
XF
K5
VSS
N8
CVDD
B12
RTCINX2
F1
X1
K6
A3
N9
VSS
B13
RDVDD
F2
X2/CLKIN
K7
A2
N10
VSS
B14
VSS
F3
GPIO0
K8
D1
N11
D8
C1
NC
F4
VSS
K9
A14
N12
D11
C2
VSS
F5
CLKOUT
K10
DVDD
N13
DVDD
C3
NC
F10
DVDD
K11
EMU0
N14
VSS
C4
GPIO6
F11
VSS
K12
EMU1/OFF
P1
VSS
C5
VSS
F12
INT4
K13
TDO
P2
VSS
C6
CLKX0
F13
DVDD
K14
TDI
P3
A12
C7
VSS
F14
INT3
L1
CVDD
P4
A9
C8
CLKX1
G1
CVDD
L2
C14
P5
A17
C9
FSR2
G2
C1
L3
C12
P6
A4
C10
CVDD
G3
A20
L4
A11
P7
A16
C11
VSS
G4
C2
L5
A8
P8
DVDD
C12
RCVDD
G5
C0
L6
A6
P9
D2
C13
VSS
G10
INT2
L7
A0
P10
D5
C14
DVDD
G11
CVDD
L8
D0
P11
D7
D1
GPIO7
G12
VSS
L9
D4
P12
D10
D2
DVDD
G13
INT1
L10
D9
P13
DVDD
D3
RSVD2
G14
INT0
L11
D13
P14
DVDD
D4
RSVD1
H1
C3
L12
D14
SPRS245C
April 2004 − Revised January 2005
Introduction
2.2.2 Pin Assignments for the PGE Package
The TMS320VC5503PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−2
and is used in conjunction with Table 2−2 to locate signal names and pin numbers.
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core. VSS is the ground for
both the I/O pins and the core. RCVDD and RDVDD are RTC module core and I/O supply, respectively.
73
109
72
144
37
1
ADVANCE INFORMATION
108
36
Figure 2−2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
April 2004 − Revised January 2005
SPRS245C
15
Introduction
ADVANCE INFORMATION
Table 2−2. Pin Assignments for the PGE Package
16
PIN NO.
SIGNAL NAME
PIN NO.
SIGNAL NAME
PIN NO.
SIGNAL NAME
PIN NO.
SIGNAL NAME
1
VSS
2
NC
37
VSS
38
A13
73
VSS
109
RDVDD
74
D12
110
RCVDD
3
4
RSVD1
39
RSVD2
40
A12
75
D13
111
RTCINX2
A11
76
D14
112
5
DVDD
RTCINX1
41
CVDD
77
D15
113
VSS
6
7
GPIO7
42
A10
78
CVDD
114
VSS
VSS
43
A9
79
EMU0
115
VSS
8
DVDD
44
A8
80
EMU1/OFF
116
DX2
9
GPIO2
45
VSS
81
TDO
117
FSX2
10
GPIO1
46
A7
82
TDI
118
CVDD
CLKX2
11
VSS
47
A6
83
CVDD
119
12
GPIO0
48
A5
84
TRST
120
DR2
13
X2/CLKIN
49
DVDD
85
TCK
121
FSR2
14
X1
50
A4
86
TMS
122
VSS
15
CLKOUT
51
A3
87
CVDD
123
CLKR2
16
C0
52
A2
88
DVDD
124
DX1
17
C1
53
CVDD
89
SDA
125
FSX1
18
CVDD
54
A1
90
SCL
126
DVDD
19
C2
55
A0
91
RESET
127
CLKX1
20
C3
56
DVDD
92
VSS
128
DR1
21
C4
57
D0
93
INT0
129
FSR1
22
C5
58
D1
94
INT1
130
CLKR1
23
C6
59
D2
95
CVDD
131
DX0
24
DVDD
60
VSS
96
INT2
132
CVDD
25
C7
61
D3
97
INT3
133
FSX0
26
C8
62
D4
98
DVDD
134
CLKX0
27
C9
63
D5
99
INT4
135
DR0
28
C11
64
VSS
100
VSS
136
FSR0
29
CVDD
65
D6
101
XF
137
CLKR0
30
CVDD
66
D7
102
VSS
138
VSS
31
C14
67
D8
103
VSS
139
DVDD
32
C12
68
CVDD
104
DVDD
140
TIN/TOUT0
33
VSS
69
D9
105
NC
141
GPIO6
34
C10
70
D10
106
NC
142
GPIO4
35
C13
71
D11
107
DVDD
143
GPIO3
36
VSS
72
DVDD
108
VSS
144
VSS
SPRS245C
April 2004 − Revised January 2005
Introduction
2.3
Signal Descriptions
Table 2−3 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for pin
locations based on package type.
Table 2−3. Signal Descriptions
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
FUNCTION
I/O/Z
A subset of the parallel address bus A13−A0 of the C55x DSP core
bonded to external pins. These pins serve in one of three functions: HPI
address bus (HPI.HA[13:0]), EMIF address bus (EMIF.A[13:0]), or
general-purpose I/O (GPIO.A[13:0]). The initial state of these pins
depends on the GPIO0 pin. See Section 3.5.1 for more information.
BK‡
RESET
CONDITION
A[13:0]
The address bus has a bus holder feature that eliminates passive
component requirement and the power dissipation associated with them.
The bus holders keep the address bus at the previous logic level when the
bus goes into a high-impedance state.
GPIO0 = 1:
HPI address bus. HPI.HA[13:0] is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is 10. This setting enables the
HPI in non-multiplexed mode.
HPI.HA[13:0]
I
HPI.HA[13:0] provides DSP internal memory access to host. In
non-multiplexed mode, these signals are driven by an external host as
address lines.
O/Z
EMIF address bus. EMIF.A[13:0] is selected when the Parallel Port Mode
bit field of the External Bus Selection Register is 01. This setting enables
the full EMIF mode and the EMIF drives the parallel port address bus. The
internal A[14] address is exclusive-ORed with internal A[0] address and
the result is routed to the A[0] pin.
GPIO.A[13:0]
I/O/Z
General-purpose I/O address bus. GPIO.A[13:0] is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is 11.
This setting enables the HPI in multiplexed mode with the Parallel Port
GPIO register controlling the parallel port address bus. GPIO is also
selected when the Parallel Port Mode bit field is 00, enabling the Data
EMIF mode.
EMIF.A′[0]
O/Z
EMIF address bus A′[0]. This pin is not multiplexed with EMIF.A[14] and is
used as the least significant external address pin on the BGA package.
EMIF.A[13:0]
A′[0]
(BGA only)
†
‡
Output,
EMIF.A[13:0]
BK
GPIO0 = 0:
Input,
HPI.HA[13:0]
Output
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
April 2004 − Revised January 2005
SPRS245C
17
ADVANCE INFORMATION
PARALLEL BUS
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
FUNCTION
BK‡
I/O/Z
A subset of the parallel address bus A15−A14 of the C55x DSP core
bonded to external pins. These pins serve in one of two functions: EMIF
address bus (EMIF.A[15:14]), or general-purpose I/O (GPIO.A[15:14]).
The initial state of these pins depends on the GPIO0 pin. See Section 3.5.1
for more information.
RESET
CONDITION
PARALLEL BUS (CONTINUED)
A[15:14]
(BGA only)
The address bus has a bus holder feature that eliminates passive
component requirement and the power dissipation associated with them.
The bus holders keep the address bus at the previous logic level when the
bus goes into a high-impedance state.
ADVANCE INFORMATION
EMIF.A[15:14]
GPIO.A[15:14]
O/Z
EMIF address bus. EMIF.A[15:14] is selected when the Parallel Port Mode
bit field of the External Bus Selection Register is 01. This setting enables
the full EMIF mode and the EMIF drives the parallel port address bus.
I/O/Z
General-purpose I/O address bus. GPIO.A[15:14] is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is 11.
This setting enables the HPI in multiplexed mode with the Parallel Port
GPIO register controlling the parallel port address bus. GPIO is also
selected when the Parallel Port Mode bit field is 00, enabling the Data
EMIF mode.
GPIO0 = 1:
Output,
EMIF.A[15:14]
BK
GPIO0 = 0:
Input,
GPIO.A[15:14]
EMIF address bus. At reset, these address pins are set as output.
A[20:16]
(BGA only)
EMIF.A[20:16]
O/Z
NOTE:
Output
These pins only function as EMIF address pins and they are not
multiplexed for any other function.
A subset of the parallel bidirectional data bus D31−D0 of the C55x DSP
core. These pins serve in one of two functions: EMIF data bus
(EMIF.D[15:0]) or HPI data bus (HPI.HD[15:0]). The initial state of these
pins depends on the GPIO0 pin. See Section 3.5.1 for more information.
D[15:0]
†
‡
18
I/O/Z
The data bus includes bus keepers to reduce the static power dissipation
caused by floating, unused pins. This eliminates the need for external bias
resistors on unused pins. When the data bus is not being driven by the
CPU, the bus keepers keep the pins at the logic level that was most
recently driven. (The data bus keepers are disabled at reset, and can be
enabled/disabled under software control.)
EMIF.D[15:0]
I/O/Z
EMIF data bus. EMIF.D[15:0] is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is 00 or 01.
HPI.HD[15:0]
I/O/Z
HPI data bus. HPI.HD[15:0] is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is 10 or 11.
GPIO0 = 1:
Input,
EMIF.D[15:0]
BK
GPIO0 = 0:
Input,
HPI.HD[15:0]
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
SPRS245C
April 2004 − Revised January 2005
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
FUNCTION
I/O/Z
EMIF asynchronous memory read enable or general-purpose IO8. This
pin serves in one of two functions: EMIF asynchronous memory read
enable (EMIF.ARE) or general-purpose IO8 (GPIO8). The initial state of
this pin depends on the GPIO0 pin. See Section 3.5.1 for more information.
EMIF.ARE
O/Z
Active-low EMIF asynchronous memory read enable. EMIF.ARE is
selected when the Parallel Port Mode bit field of the External Bus Selection
Register is 00 or 01.
GPIO8
I/O/Z
General-purpose IO8. GPIO8 is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is set to 10 or 11.
O/Z
EMIF asynchronous memory output enable or HPI interrupt output. This
pin serves in one of two functions: EMIF asynchronous memory output
enable (EMIF.AOE) or HPI interrupt output (HPI.HINT). The initial state of
this pin depends on the GPIO0 pin. See Section 3.5.1 for more information.
EMIF.AOE
O/Z
Active-low asynchronous memory output enable. EMIF.AOE is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is 00 or 01.
HPI.HINT
O/Z
Active-low HPI interrupt output. HPI.HINT is selected when the Parallel
Port Mode bit field of the External Bus Selection Register is 10 or 11.
I/O/Z
EMIF asynchronous memory write enable or HPI read/write. This pin
serves in one of two functions: EMIF asynchronous memory write enable
(EMIF.AWE) or HPI read/write (HPI.HR/W). The initial state of this pin
depends on the GPIO0 pin. See Section 3.5.1 for more information.
EMIF.AWE
O/Z
Active-low EMIF asynchronous memory write enable. EMIF.AWE is
selected when the Parallel Port Mode bit field of the External Bus Selection
Register is 00 or 01.
HPI.HR/W
I
HPI read/write. HPI.HR/W is selected when the Parallel Port Mode bit field
of the External Bus Selection Register is 10 or 11. HPI.HR/W controls the
direction of the HPI transfer.
I/O/Z
EMIF data ready input or HPI ready output. This pin serves in one of two
functions: EMIF data ready input (EMIF.ARDY) or HPI ready output
(HPI.HRDY). The initial state of this pin depends on the GPIO0 pin. See
Section 3.5.1 for more information.
EMIF.ARDY
I
EMIF data ready input. Used to insert wait states for slow memories.
EMIF.ARDY is selected when the Parallel Port Mode bit field of the
External Bus Selection Register is 00 or 01.
HPI.HRDY
O
HPI ready output. HPI.HRDY is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is 10 or 11.
BK‡
RESET
CONDITION
PARALLEL BUS (CONTINUED)
C1
C2
C3
†
‡
GPIO0 = 1:
Output,
EMIF.ARE
BK
GPIO0 = 0:
Input,
GPIO8
GPIO0 = 1:
Output,
EMIF.AOE
GPIO0 = 0:
Output,
HPI.HINT
GPIO0 = 1:
Output,
EMIF.AWE
BK
GPIO0 = 0:
Input,
HPI.HR/W
GPIO0 = 1:
Input,
EMIF.ARDY
H
GPIO0 = 0:
Output,
HPI.HRDY
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
April 2004 − Revised January 2005
SPRS245C
19
ADVANCE INFORMATION
C0
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
BK‡
FUNCTION
RESET
CONDITION
PARALLEL BUS (CONTINUED)
I/O/Z
EMIF chip select for memory space CE0 or general-purpose IO9. This pin
serves in one of two functions: EMIF chip select for memory space CE0
(EMIF.CE0) or general-purpose IO9 (GPIO9). The initial state of this pin
depends on the GPIO0 pin. See Section 3.5.1 for more information.
EMIF.CE0
O/Z
Active-low EMIF chip select for memory space CE0. EMIF.CE0 is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is set to 00 or 01.
GPIO9
I/O/Z
General-purpose IO9. GPIO9 is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is set to 10 or 11.
I/O/Z
EMIF chip select for memory space CE1 or general-purpose IO10. This pin
serves in one of two functions: EMIF chip-select for memory space CE1
(EMIF.CE1) or general-purpose IO10 (GPIO10). The initial state of this pin
depends on the GPIO0 pin. See Section 3.5.1 for more information.
EMIF.CE1
O/Z
Active-low EMIF chip select for memory space CE1. EMIF.CE1 is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is set to 00 or 01.
GPIO10
I/O/Z
General-purpose IO10. GPIO10 is selected when the Parallel Port Mode
bit field of the External Bus Selection Register is set to 10 or 11.
I/O/Z
EMIF chip select for memory space CE2 or HPI control input 0. This pin
serves in one of two functions: EMIF chip-select for memory space CE2
(EMIF.CE2) or HPI control input 0 (HPI.HCNTL0). The initial state of this
pin depends on the GPIO0 pin. See Section 3.5.1 for more information.
ADVANCE INFORMATION
C4
C5
C6
EMIF.CE2
HPI.HCNTL0
C7
EMIF.CE3
GPIO11
HPI.HCNTL1
†
‡
20
O/Z
Active-low EMIF chip select for memory space CE2. EMIF.CE2 is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is set to 00 or 01.
I
HPI control input 0. This pin, in conjunction with HPI.HCNTL1, selects a
host access to one of the three HPI registers. HPI.HCNTL0 is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is set to 10 or 11.
I/O/Z
EMIF chip select for memory space CE3, general-purpose IO11, or HPI
control input 1. This pin serves in one of three functions: EMIF chip-select
for memory space CE3 (EMIF.CE3), general-purpose IO11 (GPIO11), or
HPI control input 1 (HPI.HCNTL1). The initial state of this pin depends on
the GPIO0 pin. See Section 3.5.1 for more information.
O/Z
Active-low EMIF chip select for memory space CE3. EMIF.CE3 is selected
when the Parallel Port Mode bit field is of the External Bus Selection
Register set to 00 or 01.
I/O/Z
General-purpose IO11. GPIO11 is selected when the Parallel Port Mode
bit field is set to 10.
I
HPI control input 1. This pin, in conjunction with HPI.HCNTL0, selects a
host access to one of the three HPI registers. The HPI.HCNTL1 mode is
selected when the Parallel Port Mode bit field is set to 11.
GPIO0 = 1:
Output,
EMIF.CE0
BK
GPIO0 = 0:
Input,
GPIO9
GPIO0 = 1:
Output,
EMIF.CE1
BK
GPIO0 = 0:
Input,
GPIO10
GPIO0 = 1:
Output,
EMIF.CE2
BK
GPIO0 = 0:
Input,
HPI.HCNTL0
GPIO0 = 1:
Output,
EMIF.CE3
BK
GPIO0 = 0:
Input,
HPI.HCNTL1
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
SPRS245C
April 2004 − Revised January 2005
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
FUNCTION
I/O/Z
EMIF byte enable 0 control or HPI byte identification. This pin serves in one
of two functions: EMIF byte enable 0 control (EMIF.BE0) or HPI byte
identification (HPI.HBE0). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
EMIF.BE0
O/Z
Active-low EMIF byte enable 0 control. EMIF.BE0 is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
HPI.HBE0
I
HPI byte identification. This pin, in conjunction with HPI.HBE1, identifies
the first or second byte of the transfer. HPI.HBE0 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
I/O/Z
EMIF byte enable 1 control or HPI byte identification. This pin serves in one
of two functions: EMIF byte enable 1 control (EMIF.BE1) or HPI byte
identification (HPI.HBE1). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
EMIF.BE1
O/Z
Active-low EMIF byte enable 1 control. EMIF.BE1 is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
HPI.HBE1
I
HPI byte identification. This pin, in conjunction with HPI.HBE0, identifies
the first or second byte of the transfer. HPI.HBE1 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
I/O/Z
EMIF SDRAM row strobe, HPI address strobe, or general-purpose IO12.
This pin serves in one of three functions: EMIF SDRAM row strobe
(EMIF.SDRAS), HPI address strobe (HPI.HAS), or general-purpose IO12
(GPIO12). The initial state of this pin depends on the GPIO0 pin. See
Section 3.5.1 for more information.
BK‡
RESET
CONDITION
PARALLEL BUS (CONTINUED)
C9
C10
O/Z
Active-low EMIF SDRAM row strobe. EMIF.SDRAS is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
HPI.HAS
I
Active-low HPI address strobe. This signal latches the address in the HPIA
register in the HPI Multiplexed mode. HPI.HAS is selected when the
Parallel Port Mode bit field is set to 11.
GPIO12
I/O/Z
General-purpose IO12. GPIO12 is selected when the Parallel Port Mode
bit field is set to 10.
EMIF.SDRAS
†
‡
GPIO0 = 1:
Output,
EMIF.BE0
BK
GPIO0 = 0:
Input,
HPI.HBE0
GPIO0 = 1:
Output,
EMIF.BE1
BK
GPIO0 = 0:
Input,
HPI.HBE1
GPIO0 = 1:
Output,
EMIF.SDRAS
BK
GPIO0 = 0:
Input,
HPI.HAS
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
April 2004 − Revised January 2005
SPRS245C
21
ADVANCE INFORMATION
C8
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
BK‡
FUNCTION
RESET
CONDITION
PARALLEL BUS (CONTINUED)
C11
EMIF.SDCAS
ADVANCE INFORMATION
HPI.HCS
C12
EMIF.SDWE
HPI.HDS1
C13
I
HPI Chip Select Input. HPI.HCS is the select input for the HPI and must be
driven low during accesses. HPI.HCS is selected when the Parallel Port
Mode bit field is set to 10 or 11.
I/O/Z
EMIF SDRAM write enable or HPI Data Strobe 1 input. This pin serves in
one of two functions: EMIF SDRAM write enable (EMIF.SDWE) or HPI
data strobe 1 (HPI.HDS1). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
O/Z
EMIF SDRAM write enable. EMIF. SDWE is selected when the Parallel
Port Mode bit field of the External Bus Selection Register is set to 00 or 01.
I
HPI Data Strobe 1 Input. HPI.HDS1 is driven by the host read or write
strobes to control the transfer. HPI.HDS1 is selected when the Parallel
Port Mode bit field is set to 10 or 11.
I/O/Z
SDRAM A10 address line or general-purpose IO13. This pin serves in one
of two functions: SDRAM A10 address line (EMIF.SDA10) or
general-purpose IO13 (GPIO13). The initial state of this pin depends on
the GPIO0 pin. See Section 3.5.1 for more information.
O/Z
GPIO13
I/O/Z
General-purpose IO13. GPIO13 is selected when the Parallel Port Mode
bit field is set to 10 or 11.
I/O/Z
Memory interface clock for SDRAM, HPI Data Strobe 2 input, or
general-purpose IO14. This pin serves in one of two functions: memory
interface clock for SDRAM (EMIF.CLKMEM) or HPI data strobe 2
(HPI.HDS2). The initial state of this pin depends on the GPIO0 pin. See
Section 3.5.1 for more information.
O/Z
Memory interface clock for SDRAM. EMIF.CLKMEM is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
I
HPI Data Strobe 2 Input. HPI.HDS2 is driven by the host read or write
strobes to control the transfer. HPI.HDS2 is selected when the Parallel
Port Mode bit field is set to 10 or 11.
HPI.HDS2
22
Active-low EMIF SDRAM column strobe. EMIF.SDCAS is selected when
the Parallel Port Mode bit field of the External Bus Selection Register is set
to 00 or 01.
EMIF.SDA10
EMIF.CLKMEM
‡
O/Z
SDRAM A10 address line. Address line/autoprecharge disable for
SDRAM memory. Serves as a row address bit (logically equivalent to A12)
during ACTV commands and also disables the autoprecharging function
of SDRAM during read or write operations. EMIF.SDA10 is selected when
the Parallel Port Mode bit field of the External Bus Selection Register is set
to 00 or 01.
C14
†
I/O/Z
EMIF SDRAM column strobe or HPI chip select input. This pin serves in
one of two functions: EMIF SDRAM column strobe (EMIF.SDCAS) or HPI
chip select input (HPI.HCS). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
GPIO0 = 1:
Output,
EMIF.SDCAS
BK
GPIO0 = 0:
Input,
HPI.HCS
GPIO0 = 1:
Output,
EMIF.SDWE
BK
GPIO0 = 0:
Input,
HPI.HDS1
GPIO0 = 1:
Output,
EMIF.SDA10
BK
GPIO0 = 0:
Input,
GPIO13
GPIO0 = 1:
Output,
EMIF.CLKMEM
BK
GPIO0 = 0:
Input,
HPI.HDS2
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
SPRS245C
April 2004 − Revised January 2005
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
BK‡
RESET
CONDITION
I
Active-low external user interrupt inputs. INT[4:0] are maskable and are
prioritized by the interrupt enable register (IER) and the interrupt mode bit.
H, FS
Input
I
Active-low reset. RESET causes the digital signal processor (DSP) to
terminate execution and forces the program counter to FF8000h. When
RESET is brought to a high level, execution begins at location FF8000h of
program memory. RESET affects various registers and status bits. Use an
external pullup resistor on this pin.
H, FS
Input
I/O/Z†
FUNCTION
INTERRUPT AND RESET PINS
INT[4:0]
RESET
BIT I/O SIGNALS
I/O/Z
GPIO[7:0] (BGA)
EMIF.CKE
(GPIO4)
XF
EMIF.CKE
O/Z
7-bit (LQFP package) or 8-bit (BGA package) Input/Output lines that can
be individually configured as inputs or outputs, and also individually set or
BK
reset when configured as outputs. At reset, these pins are configured as (GPIO5
inputs. After reset, the on-chip bootloader samples GPIO[3:0] to only)
determine the boot mode selected.
H
SDRAM CKE signal. The GPIO4 pin can be configured to serve as (except
SDRAM CKE pin by setting the following bits in the External Bus Selection GPIO5)
Register: CKE SEL = 1 and CKE EN = 1. In default mode, this pin serves as
GPIO4.
Input
Input
(GPIO4)
O/Z
External flag. XF is set high by the BSET XF instruction, set low by BCLR
XF instruction or by loading ST1. XF is used for signaling other processors
in multiprocessor configurations or used as a general-purpose output pin.
XF goes into the high-impedance state when OFF is low, and is set high
following reset.
Output
O/Z
SDRAM CKE signal. The XF pin can be configured to serve as SDRAM
CKE pin by setting the following bits in the External Bus Selection Register:
CKE SEL = 0 and CKE EN = 1. In default mode, this pin serves as XF.
Output
(XF)
O/Z
DSP clock output signal. CLKOUT cycles at the machine-cycle rate of the
CPU. CLKOUT goes into high-impedance state when OFF is low.
OSCILLATOR/CLOCK SIGNALS
CLKOUT
Output
System clock/oscillator input. If the internal oscillator is not being used,
X2/CLKIN functions as the clock input.
X2/CLKIN
I/O
X1
O
†
‡
NOTE: In CLKGEN domain idle (OSC IDLE) mode, this pin becomes
output and is driven low to stop external crystals (if used) from
oscillating or an external clock source from driving the DSP’s
internal logic.
Output pin from the internal system oscillator for the crystal. If the internal
oscillator is not used, X1 should be left unconnected. X1 does not go into
the high-impedance state when OFF is low.
Oscillator
Input
Oscillator
Output
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
April 2004 − Revised January 2005
SPRS245C
23
ADVANCE INFORMATION
GPIO[7:6,4:0] (LQFP)
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
FUNCTION
BK‡
RESET
CONDITION
H
Input
TIMER SIGNALS
TIN/TOUT0
I/O/Z
Timer0 Input/Output. When output, TIN/TOUT0 signals a pulse or a
change of state when the on-chip timer counts down past zero. When
input, TIN/TOUT0 provides the clock source for the internal timer module.
At reset, this pin is configured as an input.
NOTE: Only the Timer0 signal is brought out. The Timer1 signal is
terminated internally and is not available for external use.
REAL-TIME CLOCK
RTCINX1
I
Real-Time Clock Oscillator input
RTCINX2
O
Real-Time Clock Oscillator output
Input
Output
I2C
SDA
ADVANCE INFORMATION
SCL
I/O/Z
I2C (bidirectional) data. At reset, this pin is in high-impedance mode.
H
Hi-Z
I/O/Z
I2C
H
Hi-Z
McBSP0 receive clock. CLKR0 serves as the serial shift clock for the serial
port receiver. At reset, this pin is in high-impedance mode.
H
Hi-Z
McBSP0 receive data
FS
Input
(bidirectional) clock. At reset, this pin is in high-impedance mode.
MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS
CLKR0
DR0
I/O/Z
I
FSR0
I/O/Z
McBSP0 receive frame synchronization. The FSR0 pulse initiates the data
receive process over DR0. At reset, this pin is in high-impedance mode.
CLKX0
I/O/Z
McBSP0 transmit clock. CLKX0 serves as the serial shift clock for the
serial port transmitter. The CLKX0 pin is configured as input after reset.
DX0
O/Z
McBSP0 transmit data. DX0 is placed in the high-impedance state when
not transmitting, when RESET is asserted, or when OFF is low.
Hi-Z
FSX0
I/O/Z
McBSP0 transmit frame synchronization. The FSX0 pulse initiates the
data transmit process over DX0. Configured as an input following reset.
Input
CLKR1
I/Z
McBSP1 receive clock. CLKR1 serves as the serial shift clock for the serial
port receiver.
DR1
I/Z
McBSP1 serial data receive
Input
FSR1
I/Z
McBSP1 receive frame synchronization. The FSR1 pulse initiates the data
receive process over DR1.
Input
DX1
O/Z
McBSP1 serial data transmit. DX1 is placed in the high-impedance state
when not transmitting, when RESET is asserted, or when OFF is low.
BK
Hi-Z
CLKX1
I/O/Z
McBSP1 transmit clock. CLKX1 serves as the serial shift clock for the
serial port transmitter. The CLKX1 pin is configured as input after reset.
H
Input
FSX1
I/O/Z
McBSP1 transmit frame synchronization. The FSX1 pulse initiates the
data transmit process over DX1. Configured as an input following reset.
†
‡
24
Hi-Z
H
H
Input
Input
Input
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
SPRS245C
April 2004 − Revised January 2005
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
FUNCTION
BK‡
RESET
CONDITION
H
Input
MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS (CONTINUED)
CLKR2
I
McBSP2 receive clock. CLKR2 serves as the serial shift clock for the serial
port receiver.
DR2
I
McBSP2 serial data receive
Input
I
McBSP2 receive frame synchronization. The FSR2 pulse initiates the data
receive process over DR2.
Input
DX2
O/Z
McBSP2 serial data transmit. DX2 is placed in the high-impedance state
when not transmitting, when RESET is asserted, or when OFF is low.
BK
Hi-Z
CLKX2
I/O/Z
McBSP2 transmit clock. CLKX2 serves as the serial shift clock for the
serial port transmitter. The CLKX2 pin is configured as input after reset.
H
Input
FSX2
I/O/Z
McBSP2 frame synchronization. The FSX2 pulse initiates the data
transmit process over DX2. FSX2 is configured as an input following reset.
FSR2
Input
TCK
I
IEEE standard 1149.1 test clock. TCK is normally a free-running clock
signal with a 50% duty cycle. The changes on test access port (TAP) of
input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test data register on the rising edge of TCK. Changes
at the TAP output signal (TDO) occur on the falling edge of TCK.
TDI
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is
clocked into the selected register (instruction or data) on a rising edge of
TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected
register (instruction or data) are shifted out of TDO on the falling edge of
TCK. TDO is in the high-impedance state except when the scanning of
data is in progress.
TMS
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device.
This serial control input is clocked into the TAP controller on the rising edge
of TCK.
PU
Input
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE
standard 1149.1 scan system control of the operations of the device. If
TRST is not connected or driven low, the device operates in its functional
mode, and the IEEE standard 1149.1 signals are ignored. This pin has an
internal pulldown.
PD
FS
Input
I/O/Z
Emulator 0 pin. When TRST is driven low, EMU0 must be high for
activation of the OFF condition. When TRST is driven high, EMU0 is used
as an interrupt to or from the emulator system and is defined as I/O by way
of the IEEE standard 1149.1 scan system.
PU
Input
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF
is used as an interrupt to or from the emulator system and is defined as I/O
by way of IEEE standard 1149.1 scan system. When TRST is driven low,
EMU1/OFF is configured as OFF. The EMU1/OFF signal, when
active-low, puts all output drivers into the high-impedance state. Note that
OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF condition, the
following apply: TRST = low, EMU0 = high, EMU1/OFF = low
PU
Input
TRST
EMU0
EMU1/OFF
†
‡
PU
H
Input
PU
Input
ADVANCE INFORMATION
TEST/EMULATION PINS
Hi-Z
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
April 2004 − Revised January 2005
SPRS245C
25
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL
NAME
MULTIPLEXED
SIGNAL NAME
I/O/Z†
BK‡
FUNCTION
RESET
CONDITION
SUPPLY PINS
CVDD
S
Digital Power, + VDD. Dedicated power supply for the core CPU.
DVDD
S
Digital Power, + VDD. Dedicated power supply for the I/O pins.
RDVDD
S
Digital Power, + VDD. Dedicated power supply for the I/O pins of the RTC
module.
RCVDD
S
Digital Power, + VDD. Dedicated power supply for the RTC module
VSS
S
Digital Ground. Dedicated ground for the I/O and core pins.
RESERVED
RSVD1
Reserved. Must be pulled up. Use 10-kΩ resistor.
RSVD2
Reserved. Must be pulled low. Use 10-kΩ resistor.
NC
No connection
ADVANCE INFORMATION
MISCELLANEOUS
†
‡
26
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3−1.
ADVANCE INFORMATION
†
7/8 †
5
†
Number of pins determined by package type.
Figure 3−1. Block Diagram of the TMS320VC5503
April 2004 − Revised January 2005
SPRS245C
27
Functional Overview
3.1
Memory
The 5503 supports a unified memory map (program and data accesses are made to the same physical space).
The total on-chip memory is 128K bytes (32K 16-bit words of RAM and 32K 16-bit words of ROM).
3.1.1 On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the byte address range 000000h−00FFFFh and is composed of eight blocks of
8K bytes each (see Table 3−1). Each DARAM block can perform two accesses per cycle (two reads, two
writes, or a read and a write). DARAM can be accessed by the internal program, data, or DMA buses. The
HPI can only access the first four (32K bytes) DARAM blocks.
ADVANCE INFORMATION
Table 3−1. DARAM Blocks
†
BYTE ADDRESS RANGE
MEMORY BLOCK
000000h − 001FFFh
DARAM 0 (HPI accessible)†
002000h − 003FFFh
DARAM 1 (HPI accessible)
004000h − 005FFFh
DARAM 2 (HPI accessible)
006000h − 007FFFh
DARAM 3 (HPI accessible)
008000h − 009FFFh
DARAM 4
00A000h − 00BFFFh
DARAM 5
00C000h − 00DFFFh
DARAM 6
00E000h − 00FFFFh
DARAM 7
First 192 bytes are reserved for Memory-Mapped Registers (MMRs).
3.1.2 On-Chip Read-Only Memory (ROM)
The one-wait-state ROM is located at the byte address range FF0000h−FFFFFFh, for a total of 64K bytes of
ROM. The ROM address space can be mapped by software to the external memory or to the internal ROM.
The standard 5503 device includes a bootloader program resident in the ROM. When the MPNMC bit field
of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the memory
map, and byte address range FF0000h−FFFFFFh is directed to external memory space. A hardware reset
always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset
instruction does not affect the MPNMC bit. The on-chip ROM can be accessed by the program, data, or DMA
buses. The first 16-bit word access to ROM requires three cycles. Subsequent accesses require two cycles
per 16-bit word.
28
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.1.3 Memory Maps
3.1.3.1
PGE Package Memory Map
The PGE package features 14 address bits representing 16K-byte linear address for asynchronous memories
per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is 4M bytes for
each CE space. The largest SDRAM device that can be used with the 5503 in a PGE package is 128M-bit
SDRAM.
Byte Address
(Hex)†
000000
Memory Blocks
Block Size
MMR (Reserved)
0000C0
DARAM / HPI Access
(32K − 192) Bytes
008000
DARAM‡
32K Bytes
ADVANCE INFORMATION
010000
Reserved
040000
External§ − CE0
16K Bytes − Asynchronous
4M Bytes − 64K Bytes SDRAM¶
External§ − CE1
16K Bytes − Asynchronous
4M Bytes − SDRAM
External§ − CE2
16K Bytes − Asynchronous
4M Bytes − SDRAM
External§ − CE3
16K Bytes − Asynchronous
4M Bytes − SDRAM (MPNMC = 1)
4M Bytes − 64K Bytes if internal ROM selected (MPNMC = 0)
400000
800000
C00000
FF0000
ROM#
(if MPNMC=0)
External§ − CE3
(if MPNMC=1)
64K Bytes
FFFFFF
†
Address shown represents the first byte address in each block.
Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.
§ External memory spaces are selected by the chip-enable signal shown (CE[0:3]). Supported memory types include: asynchronous static
RAM (SRAM) and synchronous DRAM (SDRAM).
¶ The minus 64K bytes consists of 32K-byte DARAM/HPI access and 32K-byte DARAM.
# Read-only memory (ROM): one access every two cycles.
‡
Figure 3−2. TMS320VC5503 Memory Map (PGE Package)
April 2004 − Revised January 2005
SPRS245C
29
Functional Overview
3.1.3.2
GHH Package Memory Map
The GHH package features 21 address bits representing 2M-byte linear address for asynchronous memories
per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is 4M bytes for
each CE space. The largest SDRAM device that can be used with the 5503 in a GHH package is 128M-bit
SDRAM.
Byte Address
(Hex)†
000000
Memory Blocks
Block Size
MMR (Reserved)
0000C0
DARAM / HPI Access
(32K − 192) Bytes
008000
ADVANCE INFORMATION
DARAM‡
32K Bytes
010000
Reserved
040000
External§ − CE0
2M Bytes − Asynchronous
4M Bytes − 64K Bytes SDRAM¶
External§ − CE1
2M Bytes − Asynchronous
4M Bytes − SDRAM
External§ − CE2
2M Bytes − Asynchronous
4M Bytes − SDRAM
External§ − CE3
2M Bytes − Asynchronous
4M Bytes − SDRAM (MPNMC = 1)
4M Bytes − 64K Bytes if internal ROM selected (MPNMC = 0)
400000
800000
C00000
FF0000
ROM#
(if MPNMC=0)
External§ − CE3
(if MPNMC=1)
64K Bytes
FFFFFF
†
Address shown represents the first byte address in each block.
Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.
§ External memory spaces are selected by the chip-enable signal shown (CE[0:3]). Supported memory types include: asynchronous static
RAM (SRAM) and synchronous DRAM (SDRAM).
¶ The minus 64K bytes consists of 32K-byte DARAM/HPI access and 32K-byte DARAM.
# Read-only memory (ROM): one access every two cycles.
‡
Figure 3−3. TMS320VC5503 Memory Map (GHH Package)
30
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.1.4 Boot Configuration
The on-chip bootloader provides a method to transfer application code and tables from an external source to
the on-chip RAM memory at power up. These options include:
•
•
•
•
•
•
Enhanced host-port interface (HPI) in multiplexed or nonmultiplexed mode
External asynchronous memory boot (via the EMIF) from 8-bit-wide or 16-bit-wide memory
Serial port boot (from McBSP0) with 8-bit or 16-bit data length
Serial EPROM boot (from McBSP0) supporting EPROMs with 16-bit or 24-bit address
I2C EEPROM
Direct execution from external 16-bit-wide asynchronous memory
External pins select the boot configuration. The values of GPIO[3:0] are sampled, following reset, upon
execution of the on-chip bootloader code. It is not possible to disable the bootloader at reset because the 5503
always starts execution from the on-chip ROM following a hardware reset. A summary of boot configurations
is shown in Table 3−2. For more information on using the bootloader, see the Using the
TMS320VC5503/VC5507/VC5509/VC5509A Bootloader application report (literature number SPRA375).
GPIO0
GPIO3
GPIO2
GPIO1
0
0
0
0
Reserved
0
0
0
1
Serial (SPI) EPROM Boot (24-bit address) via McBSP0
0
0
1
0
Reserved
0
0
1
1
I2C EEPROM (7-bit address)
0
1
0
0
Reserved
0
1
0
1
HPI – multiplexed mode
0
1
1
0
HPI – nonmultiplexed mode
0
1
1
1
Reserved
1
0
0
0
Execute from 16-bit-wide asynchronous memory (on CE1 space)
1
0
0
1
Serial (SPI) EPROM Boot (16-bit address) via McBSP0
1
0
1
0
8-bit asynchronous memory (on CE1 space)
1
0
1
1
16-bit asynchronous memory (on CE1 space)
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Standard serial boot via McBSP0 (16-bit data)
1
1
1
1
Standard serial boot via McBSP0 (8-bit data)
April 2004 − Revised January 2005
ADVANCE INFORMATION
Table 3−2. Boot Configuration Summary
BOOT MODE PROCESS
SPRS245C
31
Functional Overview
3.2
Peripherals
The 5503 supports the following peripherals:
•
A Configurable Parallel External Interface supporting either:
−
−
•
•
•
•
•
•
•
•
16-bit external memory interface (EMIF) for asynchronous memory and/or SDRAM
16-bit enhanced host-port interface (HPI)
A six-channel direct memory access (DMA) controller
A programmable phase-locked loop clock generator
Two 20-bit timers
Watchdog Timer
Three multichannel buffered serial ports (McBSPs)
Seven (LQFP) or Eight (BGA) configurable general-purpose I/O pins
I2C multi-master and slave interface (I2C compatible except, no fail-safe I/O buffers)
Real-time clock with crystal input, separate clock domain and supply pins
ADVANCE INFORMATION
For detailed information on the C55x DSP peripherals, see the following documents:
•
•
3.3
TMS320C55x DSP Functional Overview (literature number SPRU312)
TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317)
Direct Memory Access (DMA) Controller
The 5503 DMA provides the following features:
•
•
•
•
•
•
•
•
Three standard ports, one for each of the following data resources: DARAM, Peripherals, and External
Memory
Six channels, which allow the DMA controller to track the context of six independent DMA channels
Programmable low/high priority for each DMA channel
One interrupt for each DMA channel
Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected
events.
Programmable address modification for source and destination addresses
Dedicated Idle Domain allows the DMA controller to be placed in a low-power (idle) state under software
control.
Dedicated DMA channel used by the HPI to access internal memory (DARAM)
The 5503 DMA controller allows transfers to be synchronized to selected events. The 5503 supports
15 separate sync events and each channel can be tied to separate sync events independent of the other
channels. Sync events are selected by programming the SYNC field in the channel-specific DMA Channel
Control Register (DMA_CCR).
32
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.3.1 DMA Channel Control Register (DMA_CCR)
The channel control register (DMA_CCR) bit layouts are shown in Figure 3−4.
15
14
13
12
11
10
9
8
DST AMODE
SRC AMODE
END PROG
Reserved
REPEAT
AUTO INIT
R/W, 00
R/W, 00
R/W, 0
R, 0
R/W, 0
R/W, 0
7
6
5
EN
PRIO
FS
4
SYNC
0
R/W, 0
R/W, 0
R/W, 0
R/W, 00000
Figure 3−4. DMA_CCR Bit Locations
The SYNC[4:0] bits specify the event that can initiate the DMA transfer for the corresponding DMA channel.
The five bits allow several configurations as listed in Table 3−3. The bits are set to zero upon reset. For those
synchronization modes with more than one peripheral listed, the Serial Port Mode bit field of the External Bus
Selection Register dictates which peripheral event is actually connected to the DMA input.
Table 3−3. Synchronization Control Function
SYNC FIELD IN
DMA_CCR
00000b
No event synchronized
00001b
McBSP 0 Receive Event (REVT0)
00010b
McBSP 0 Transmit Event (XEVT0)
00011b
Reserved. These bits should always be written with 0.
00100b
Reserved. These bits should always be written with 0.
00101b
McBSP1 Receive Event (REVT1)
00110b
McBSP1 Transmit Event (XEVT1)
00111b
Reserved. These bits should always be written with 0.
01000b
Reserved. These bits should always be written with 0.
01001b
McBSP2 Receive Event (REVT2)
01010b
McBSP2 Transmit Event (XEVT2)
01011b
Reserved. These bits should always be written with 0.
01100b
Reserved. These bits should always be written with 0.
01101b
Timer 0 Interrupt Event
01110b
Timer 1 Interrupt Event
01111b
External Interrupt 0
10000b
External Interrupt 1
10001b
External Interrupt 2
10010b
External Interrupt 3
10011b
External Interrupt 4 / I2C Receive Event (REVTI2C)†
10100b
I2C Transmit Event (XEVTI2C)
Other values
†
SYNCHRONIZATION MODE
Reserved (Do not use these values)
The I2C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the
DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization.
April 2004 − Revised January 2005
SPRS245C
33
ADVANCE INFORMATION
LEGEND: R = Read, W = Write, n = value after reset
Functional Overview
3.4
I2C Interface
The TMS320VC5503 includes an I2C serial port. The I2C port supports:
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Operates at 100 Kbps or 400 Kbps
7-bit addressing mode
Master (transmit/receive) and slave (transmit/receive) modes of operation
Events: DMA, interrupt, or polling
The I2C module clock must be in the range from 7 MHz to 12 MHz. This is necessary for proper operation of
the I2C module. With the I2C module clock in this range, the noise filters on the SDA and SCL pins suppress
noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the DSP clock divided by
a programmable prescaler.
ADVANCE INFORMATION
NOTE: I/O buffers are not fail-safe. The SDA and SCL pins could potentially draw current if the
device is powered down and SDA and SCL are driven by other devices connected to the I2C bus.
3.5
Configurable External Buses
The 5503 offers combinations of configurations for its external parallel port. This allows the system designer
to choose the appropriate media interface for its application without the need of a large-pin-count package.
The External Bus Selection Register controls the routing of the parallel port signals.
34
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.5.1 External Bus Selection Register (EBSR)
The External Bus Selection Register determines the mapping of the 14 (LQFP) or 21 (BGA) address signals,
16 data signals, and 15 control signals of the external parallel port. The External Bus Selection Register is
memory-mapped at port address 0x6C00. Once the bit fields of this register are changed, the routing of the
signals takes place on the next CPU clock cycle.
15
14
13
12
11
10
9
8
CLKOUT
Disable
OSC Disable
HIDL
BKE
SR STAT
HOLD
HOLDA
CKE SEL
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 1
R/W, 0
7
6
5
2
1
0
CKE EN
SR CMD
Reserved
(see NOTE)
Parallel Port
Mode
R/W, 0
R/W, 0
R, 0000
R/W, 01 if GPIO0 = 1
11 if GPIO0 = 0
ADVANCE INFORMATION
The reset value of the parallel port mode bit field is determined by the state of the GPIO0 pin at reset. If GPIO0
is high at reset, the full EMIF mode is enabled and the parallel port mode bit field is set to 01. If GPIO0 is low
at reset, the HPI multiplexed mode is enabled and the parallel port mode bit field is set to 11. After reset, the
parallel port should be selected to function in either EMIF mode or HPI mode. Dynamic switching of the parallel
port, once configured, is not recommended.
LEGEND: R = Read, W = Write, n = value after reset
NOTE: These bits are Reserved and must be kept as 0000 during any writes to EBSR.
Figure 3−5. External Bus Selection Register
Table 3−4. External Bus Selection Register Bit Field Description
BITS
DESCRIPTION
CLKOUT disable.
15
CLKOUT disable = 0:
CLKOUT disable = 1:
CLKOUT enabled
CLKOUT disabled
Oscillator disable. Works with IDLE instruction to put the clock generation domain into IDLE mode.
14
OSC disable = 0:
OSC disable = 1:
Oscillator enabled
Oscillator disabled
Host mode idle bit. (Applicable only if the parallel bus is configured as EHPI.)
13
When the parallel bus is set to EHPI mode, the clock domain is not allowed to go to idle, so a host processor can
access the DSP internal memory. The HIDL bit works around this restriction and allows the DSP to idle the clock
domain and the EHPI. When the clock domain is in idle, a host processor will not be able to access the DSP
memory.
HIDL = 0:
HIDL = 1:
Host access to DSP enabled. Idling EHPI and clock domain is not allowed.
Idles the HPI and the clock domain upon execution of the IDLE instruction when the parallel
port mode is set to 10 or 11 selecting HPI mode. In addition, bit 4 of the Idle Control Register
must be set to 1 prior to the execution of the IDLE instruction.
Bus keeper enable.†
12
BKE = 0:
BKE = 1:
Bus keeper, pullups/pulldowns enabled
Bus keeper, pullups/pulldowns disabled
SDRAM self-refresh status bit.
11
SR STAT = 0: SDRAM self-refresh signal is not asserted.
SR STAT = 1: SDRAM self-refresh signal is asserted
†
Function available when the port or pins configured as input.
April 2004 − Revised January 2005
SPRS245C
35
Functional Overview
Table 3−4. External Bus Selection Register Bit Field Description (Continued)
BITS
DESCRIPTION
EMIF hold
10
HOLD = 0:
HOLD = 1:
DSP drives the external memory bus
Request the external memory bus to be placed in high-impedance so that another device can
drive the memory bus
EMIF hold acknowledge.
HOLDA = 0:
9
HOLDA = 1:
DSP indicates that a hold request on the external memory bus has occured, the EMIF
completed any pending external bus activity, and placed the external memory bus signals in
high-impedance state (address bus, data bus, CE[3:0], AOE, AWE, ARE, SDRAS, SDCAS,
SDWE, SDA10, CLKMEM). Once this bit is cleared, an external device can drive the bus.
No hold acknowledge
SDRAM CKE pin selection bit.
8
CKE SEL = 0: Use XF for SDRAM CKE signal
CKE SEL = 1: Use GPIO.4 for SDRAM CKE signal
SDRAM CKE enable bit.
ADVANCE INFORMATION
7
CKE EN = 0:
CKE EN = 1:
XF or GPIO.4 operates in normal mode
Based on the CKE SEL bit, either XF or GPIO.4 drives the SDRAM CKE pin
SDRAM self-refresh command.
6
5−2
SR CMD = 0: EMIF will not issue a SDRAM self-refresh command
SR CMD = 1: EMIF will issue a SDRAM self-refresh command
Reserved. Must be kept as 0000 during any writes to EBSR.
Parallel port mode. EMIF/HPI/GPIO Mode. Determines the mode of the parallel port.
1−0
†
36
Parallel Port Mode = 00: Data EMIF mode. The 16 EMIF data signals and 13 EMIF control signals are
routed to the corresponding external parallel bus data and control signals. The
14 (LQFP) or 16 (BGA) address bus signals can be used as general-purpose I/O
only.
Parallel Port Mode = 01: Full EMIF mode. The 14 (LQFP) or 21 (BGA) address signals, 16 data signals, and
15 control signals are routed to the corresponding external parallel bus address,
data, and control signals.
Parallel Port Mode = 10: Non-multiplexed HPI mode. The HPI is enabled an its 14 address signals,
16 data signals, and 7 control signals are routed to the corresponding address,
data, control signals of the external parallel bus. Moreover, 8 control signals of the
external parallel bus are used as general-purpose I/O.
Parallel Port Mode = 11: Multiplexed HPI mode. The HPI is enabled and its 16 data signals and
10 control signals are routed to the external parallel bus. In addition, 3 control
signals of the external parallel bus are used as general-purpose I/O. The
14 (LQFP) or 16 (BGA) external parallel port address bus signals are used as
general-purpose I/O.
Function available when the port or pins configured as input.
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.5.2 Parallel Port
•
Full EMIF mode: the EMIF with its 14 (LQFP) or 21 address signals, 16 data signals, and 15 control
signals routed to the corresponding external parallel bus address, data, and control signals.
•
Data EMIF mode: the EMIF with its 16 data signals, and 15 control signals routed to the corresponding
external parallel bus data and control signals. The 14 (LQFP) or 16 (BGA) address bus signals can be
used as general-purpose I/O signals only.
•
Non-multiplexed HPI mode: the HPI is enabled with its 14 address signals, 16 data signals, and
8 control signals routed to the corresponding address, data, and control signals of the external parallel
bus. Moreover, 7 control signals of the external parallel bus are used as general-purpose I/O.
•
Multiplexed HPI mode: the HPI is enabled with its 16 data signals and 10 control signals routed to the
external parallel bus. In addition, 5 control signals of the external parallel bus are used as general-purpose
I/O. The external parallel port’s 14 (LQFP) or 16 (BGA) address signals are used as general-purpose I/O.
Table 3−5. TMS320VC5503 Parallel Port Signal Routing
Pin Signal
Data EMIF (00)†
Full EMIF (01)†
Non-Multiplex HPI (10)†
Multiplex HPI (11)†
Address Bus
A’[0]
A[0]
A[13:1]
N/A
EMIF.A[0] (BGA)
N/A
N/A
GPIO.A[0] (LQFP)
EMIF.A[0] (LQFP)
HPI.HA[0] (LQFP)
GPIO.A[0] (LQFP)
HPI.HA[0] (BGA)
GPIO.A[0] (BGA)
EMIF.A[13:1] (LQFP)
HPI.HA[13:1] (LQFP)
GPIO.A[13:1] (LQFP)
GPIO.A[0] (BGA)
GPIO.A[13:1] (LQFP)
GPIO.A[13:1] (BGA)
EMIF.A[13:1] (BGA)
HPI.HA[13:1] (BGA)
GPIO.A[13:1] (BGA)
A[15:14]
GPIO.A[15:14] (BGA)
EMIF.A[15:14] (BGA)
N/A
GPIO.A[15:14] (BGA)
A[20:16]‡
N/A
EMIF.A[20:16] (BGA)
N/A
N/A
HPI.HD[15:0]
HPI.HD[15:0]
Data Bus
D[15:0]
EMIF.D[15:0]
EMIF.D[15:0]
Control Bus
C0
EMIF.ARE
EMIF.ARE
GPIO8
GPIO8
C1
EMIF.AOE
EMIF.AOE
HPI.HINT
HPI.HINT
C2
EMIF.AWE
EMIF.AWE
HPI.HR/W
HPI.HR/W
C3
EMIF.ARDY
EMIF.ARDY
HPI.HRDY
HPI.HRDY
C4
EMIF.CE0
EMIF.CE0
GPIO9
GPIO9
C5
EMIF.CE1
EMIF.CE1
GPIO10
GPIO10
C6
EMIF.CE2
EMIF.CE2
HPI.HCNTL0
HPI.HCNTL0
C7
EMIF.CE3
EMIF.CE3
GPIO11
HPI.HCNTL1
C8
EMIF.BE0
EMIF.BE0
HPI.HBE0
HPI.HBE0
C9
EMIF.BE1
EMIF.BE1
HPI.HBE1
HPI.HBE1
C10
EMIF.SDRAS
EMIF.SDRAS
GPIO12
HPI.HAS
C11
EMIF.SDCAS
EMIF.SDCAS
HPI.HCS
HPI.HCS
C12
EMIF.SDWE
EMIF.SDWE
HPI.HDS1
HPI.HDS1
C13
EMIF.SDA10
EMIF.SDA10
GPIO13
GPIO13
C14
EMIF.CLKMEM
EMIF.CLKMEM
HPI.HDS2
HPI.HDS2
† Represents the Parallel Port Mode bits of the External Bus Selection Register.
‡ A[20:16] of the BGA package always functions as EMIF address pins and they cannot be reconfigured for any other function.
April 2004 − Revised January 2005
SPRS245C
37
ADVANCE INFORMATION
The parallel port of the 5503 consists of 14 (LQFP) or 21 (BGA) address signals, 16 data signals, and 15 control
signals. Its 14 bits for address allow it to access 16K (LQFP) or 2M bytes of external memory when using the
asynchronous SRAM interface. On the other hand, the SDRAM interface can access the whole external
memory space of 16M bytes. The parallel bus supports four different modes:
Functional Overview
3.5.3 Parallel Port Signal Routing
The 5503 allows access to 16-bit-wide (read and write) or 8-bit-wide (read only) asynchronous memory and
16-bit-wide SDRAM. For 16-bit-wide memories, EMIF.A[0] is kept low and is not used. To provide as many
address pins as possible, the 5503 routes the parallel port signals as shown in Figure 3−6.
Figure 3−6 shows the addition of the A′[0] signal in the BGA package. This pin is used for asynchronous
memory interface only, while the A[0] pin is used with HPI or GPIO. Figure 3−7 summarizes the use of the
parallel port signals for memory interfacing.
EMIF.A[0]
A’[0] (BGA only)
GPIO.A[0]
A[0]
ADVANCE INFORMATION
HPI.HA[0]
EMIF.A[13:1]
HPI.HA[13:1]
A[13:1]
GPIO.A[13:1]
EMIF.A[14]
A[14] (BGA only)
GPIO.A[14]
EMIF.A[15]
A[15] (BGA only)
GPIO.A[15]
EMIF.A[20:16]
A[20:16] (BGA only)
Figure 3−6. Parallel Port Signal Routing
38
SPRS245C
April 2004 − Revised January 2005
Functional Overview
16-Bit-Wide Asynchronous Memory
CEx
CS
CEx
WE
WE
CLKMEM
CLK
RE
RE
SDRAS
RAS
OE
OE
SDCAS
CAS
SDWE
BE[1:0]
WE
BE[1:0]
BE[1:0]
A[13:1]
A[12:0]
A[0]
D[15:0]
5503
BGA
16-Bit
Asynchronous
Memory
A[13]
D[15:0]
A[13]
BA[0]
A[12]
A[11]
SDA10
A[10]
CS
A[10:1]
A[9:0]
WE
WE
D[15:0]
D[15:0]
RE
RE
OE
OE
BE[1:0]
A[13:1]
D[15:0]
BE[1:0]
A[19:13]
16-Bit
Asynchronous
Memory
CEx
A[12:0]
D[15:0]
5503
BGA
8-Bit-Wide Asynchronous Memory
5503
BGA
A[0]
64 MBit or
DQM[H:L] 128 MBit
SDRAM
BA[1]
CEx
A[20:14]
5503
LQFP
5503
LQFP
CS
CS
CLKMEM
CLK
SDRAS
RAS
SDCAS
CAS
SDWE
BE[1:0]
WE
A[14]
64 MBit or
DQM[H:L] 128 MBit
SDRAM
BA[1]
A[13]
BA[0]
CEx
CS
A[12]
A[11]
WE
WE
SDA10
A[10]
RE
RE
A[10:1]
A[9:0]
OE
OE
D[15:0]
D[15:0]
BE[1:0]
BE[1:0]
A[13:0]
A[13:0]
D[7:0]
D[7:0]
CEx
CS
WE
WE
RE
RE
OE
OE
BE[1:0]
BE[1:0]
A[20:14]
A[20:14]
A[13:1]
A[13:1]
A’[0]
D[7:0]
8-Bit
Asynchronous
Memory
ADVANCE INFORMATION
5503
LQFP
16-Bit-Wide SDRAM
8-Bit
Asynchronous
Memory
A[0]
D[7:0]
Figure 3−7. Parallel Port (EMIF) Signal Interface
April 2004 − Revised January 2005
SPRS245C
39
Functional Overview
3.6
General-Purpose Input/Output (GPIO) Ports
3.6.1 Dedicated General-Purpose I/O
The 5503 provides eight dedicated general-purpose input/output pins, GPIO0−GPIO7. Each pin can be
indepedently configured as an input or an output using the I/O Direction Register (IODIR). The I/O Data
Register (IODATA) is used to monitor the logic state of pins configured as inputs and control the logic state
of pins configured as outputs. See Table 3−25 for address information. The description of the IODIR is shown
in Figure 3−8 and Table 3−6. The description of IODATA is shown in Figure 3−9 and Table 3−7.
To configure a GPIO pin as an input, clear the direction bit that corresponds to the pin in IODIR to 0. To read
the logic state of the input pin, read the corresponding bit in IODATA.
To configure a GPIO pin as an output, set the direction bit that corresponds to the pin in IODIR to 1. To control
the logic state of the output pin, write to the corresponding bit in IODATA.
ADVANCE INFORMATION
15
8
7
6
5
4
3
2
1
0
IO4DIR
IO3DIR
IO2DIR
IO1DIR
IO0DIR
R/W−0
R/W−0
R/W−0
R/W−0
R/W−0
Reserved
IO7DIR
IO6DIR
IO5DIR
(BGA)
R−00000000
R/W−0
R/W−0
R/W−0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−8. I/O Direction Register (IODIR) Bit Layout
Table 3−6. I/O Direction Register (IODIR) Bit Functions
†
BIT
NO.
BIT
NAME
RESET
VALUE
15−8
Reserved
0
These bits are reserved and are unaffected by writes.
7−0
IOxDIR†
0
IOx Direction Control Bit. Controls whether IOx operates as an input or an output.
IOxDIR = 0
IOx is configured as an input.
IOxDIR = 1
IOx is configured as an output.
FUNCTION
The GPIO5 pin is available on the BGA package only.
40
SPRS245C
April 2004 − Revised January 2005
Functional Overview
15
8
7
6
5
4
3
2
1
0
Reserved
IO7D
IO6D
IO5D
(BGA)
IO4D
IO3D
IO2D
IO1D
IO0D
R−00000000
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
LEGEND: R = Read, W = Write, pin = value present on the pin (IO7−IO0 default to inputs after reset)
Figure 3−9. I/O Data Register (IODATA) Bit Layout
Table 3−7. I/O Data Register (IODATA) Bit Functions
BIT
NAME
RESET
VALUE
15−8
Reserved
0
7−0
pin†‡
IOxD
FUNCTION
These bits are reserved and are unaffected by writes.
IOx Data Bit.
If IOx is configured as an input (IOxDIR = 0 in IODIR):
IOxD = 0
The signal on the IOx pin is low.
IOxD = 1
The signal on the IOx pin is high.
If IOx is configured as an output (IOxDIR = 1 in IODIR):
IOxD = 0
Drive the signal on the IOx pin low.
IOxD = 1
Drive the signal on the IOx pin high.
†
‡
The GPIO5 pin is available on the BGA package only.
pin = value present on the pin (IO7−IO0 default to inputs after reset)
3.6.2 Address Bus General-Purpose I/O
The 16 address signals, EMIF.A[15−0], can also be individually enabled as GPIO when the Parallel Port Mode
bit field of the External Bus Selection Register is set for Data EMIF (00) or Multiplexed EHPI mode (11). These
pins are controlled by three registers: the enable register, AGPIOEN, determines if the pins serve as GPIO
or address (Figure 3−10); the direction register, AGPIODIR, determines if the GPIO enabled pin is an input
or output (Figure 3−11); and the data register, AGPIODATA, determines the logic states of the pins in
general-purpose I/O mode (Figure 3−12).
15
14
13
12
11
10
9
8
AIOEN15
(BGA)
AIOEN14
(BGA)
AIOEN13
AIOEN12
AIOEN11
AIOEN10
AIOEN9
AIOEN8
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIOEN7
AIOEN6
AIOEN5
AIOEN4
AIOEN3
AIOEN2
AIOEN1
AIOEN0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−10. Address/GPIO Enable Register (AGPIOEN) Bit Layout
Table 3−8. Address/GPIO Enable Register (AGPIOEN) Bit Functions
BIT
NO.
15−0
BIT
NAME
AIOENx
RESET
VALUE
FUNCTION
0
Enable or disable GPIO function of Address Bus of EMIF. AIOEN15 and AIOEN14 are only available in
BGA package.
AIOENx = 0
GPIO function of Ax line is disabled; i.e., Ax has address function.
AIOENx = 1
GPIO function of Ax line is enabled; i.e., Ax has GPIO function.
April 2004 − Revised January 2005
SPRS245C
41
ADVANCE INFORMATION
BIT
NO.
Functional Overview
15
14
13
12
11
10
9
8
AIODIR15
(BGA)
AIODIR14
(BGA)
AIODIR13
AIODIR12
AIODIR11
AIODIR10
AIODIR9
AIODIR8
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIODIR7
AIODIR6
AIODIR5
AIODIR4
AIODIR3
AIODIR2
AIODIR1
AIODIR0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−11. Address/GPIO Direction Register (AGPIODIR) Bit Layout
ADVANCE INFORMATION
Table 3−9. Address/GPIO Direction Register (AGPIODIR) Bit Functions
BIT
NO.
BIT
NAME
15−0
RESET
VALUE
FUNCTION
0
Data direction bits that configure the Address Bus configured as I/O pins as either input or output pins.
AIODIR15 and AIODIR14 are only available in BGA package.
AIODIRx = 0
Configure corresponding pin as an input.
AIODIRx = 1
Configure corresponding pin as an output.
AIODIRx
15
14
13
12
11
10
9
8
AIOD15 (BGA)
AIOD14 (BGA)
AIOD13
AIOD12
AIOD11
AIOD10
AIOD9
AIOD8
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIOD7
AIOD6
AIOD5
AIOD4
AIOD3
AIOD2
AIOD1
AIOD0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−12. Address/GPIO Data Register (AGPIODATA) Bit Layout
Table 3−10. Address/GPIO Data Register (AGPIODATA) Bit Functions
BIT
NO.
15−0
BIT
NAME
AIODx
RESET
VALUE
0
FUNCTION
Data bits that are used to control the level of the Address Bus configured as I/O output pins, and to monitor
the level of the Address Bus configured as I/O input pins. AIOD15 and AIOD14 are only available in BGA
package.
If AIODIRn = 0, then:
AIODx = 0
Corresponding I/O pin is read as a low.
AIODx = 1
Corresponding I/O pin is read as a high.
If AIODIRn = 1, then:
AIODx = 0
Set corresponding I/O pin to low.
AIODx = 1
Set corresponding I/O pin to high.
42
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.6.3 EHPI General-Purpose I/O
Six control lines of the External Parallel Bus can also be set as general-purpose I/O when the Parallel Port
Mode bit field of the External Bus Selection Register is set to Nonmultiplexed EHPI (10) or Multiplexed EHPI
mode (11). These pins are controlled by three registers: the enable register, EHPIGPIOEN, determines if the
pins serve as GPIO or address (Figure 3−13); the direction register, EHPIGPIODIR, determines if the GPIO
enabled pin is an input or output (Figure 3−14); and the data register, EHPIGPIODATA, determines the logic
states of the pins in GPIO mode (Figure 3−15).
15
6
5
4
3
2
1
0
Reserved
GPIOEN13
GPIOEN12
GPIOEN11
GPIOEN10
GPIOEN9
GPIOEN8
R, 0000 0000 00
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Table 3−11. EHPI GPIO Enable Register (EHPIGPIOEN) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
15−6
Reserved
0
Reserved
5−0
GPIOEN13−
GPIOEN8
0
Enable or disable GPIO function of EHPI Control Bus.
GPIOENx = 0 GPIO function of GPIOx line is disabled
GPIOENx = 1 GPIO function of GPIOx line is enabled
15
FUNCTION
6
5
4
3
2
1
0
Reserved
GPIODIR13
GPIODIR12
GPIODIR11
GPIODIR10
GPIODIR9
GPIODIR8
R, 0000 0000 00
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−14. EHPI GPIO Direction Register (EHPIGPIODIR) Bit Layout
Table 3−12. EHPI GPIO Direction Register (EHPIGPIODIR) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
15−6
Reserved
0
Reserved
5−0
GPIODIR13−
GPIODIR8
0
Data direction bits that configure the EHPI Control Bus configured as I/O pins as either input or output
pins.
GPIODIRx = 0 Configure corresponding pin as an input.
GPIODIRx = 1 Configure corresponding pin as an output.
April 2004 − Revised January 2005
FUNCTION
SPRS245C
43
ADVANCE INFORMATION
Figure 3−13. EHPI GPIO Enable Register (EHPIGPIOEN) Bit Layout
Functional Overview
15
6
5
4
3
2
1
0
Reserved
GPIOD13
GPIOD12
GPIOD11
GPIOD10
GPIOD9
GPIOD8
R, 0000 0000 00
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−15. EHPI GPIO Data Register (EHPIGPIODATA) Bit Layout
Table 3−13. EHPI GPIO Data Register (EHPIGPIODATA) Bit Functions
BIT
NAME
RESET
VALUE
15−6
Reserved
0
Reserved
0
Data bits that are used to control the level of the EHPI Control Bus configured as I/O output pins, and to
monitor the level of the EHPI Control Bus configured as I/O input pins.
If GPIODIRn = 0, then:
GPIODx = 0
Corresponding I/O pin is read as a low.
GPIODx = 1
Corresponding I/O pin is read as a high.
ADVANCE INFORMATION
BIT
NO.
5−0
GPIOD13−
GPIOD8
FUNCTION
If GPIODIRn = 1, then:
GPIODx = 0
Set corresponding I/O pin to low.
GPIODx = 1
Set corresponding I/O pin to high.
44
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.7
System Register
The system register (SYSR) provides control over certain device-specific functions. The register is located
at port address 07FDh.
15
8
Reserved
7
3
2
Reserved
0
CLKDIV
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−16. System Register Bit Locations
Table 3−14. System Register Bit Fields
BIT
NUMBER
NAME
15−3
Reserved
CLKDIV
2−0
April 2004 − Revised January 2005
FUNCTION
These bits are reserved and are unaffected by writes.
CLKOUT Divide Factor. Allows the clock present on the CLKOUT pin to be a divided-down version
of the internal CPU clock. This field does not affect the programming of the PLL.
CLKDIV
CLKDIV
CLKDIV
CLKDIV
CLKDIV
CLKDIV
CLKDIV
CLKDIV
000 = CLKOUT represents the CPU clock divided by 1
001 = CLKOUT represents the CPU clock divided by 2
010 = CLKOUT represents the CPU clock divided by 4
011 = CLKOUT represents the CPU clock divided by 6
100 = CLKOUT represents the CPU clock divided by 8
101 = CLKOUT represents the CPU clock divided by 10
110 = CLKOUT represents the CPU clock divided by 12
111 = CLKOUT represents the CPU clock divided by 14
SPRS245C
45
ADVANCE INFORMATION
R/W
Functional Overview
3.8
Memory-Mapped Registers
The 5503 has 78 memory-mapped CPU registers that are mapped in data memory space address 0h to 4Fh.
Table 3−15 provides a list of the CPU memory-mapped registers (MMRs) available. The corresponding
TMS320C54x (C54x) CPU registers are also indicated where applicable.
ADVANCE INFORMATION
Table 3−15. CPU Memory-Mapped Registers
C55x
REGISTER
C54x
REGISTER
WORD ADDRESS
(HEX)
IER0
IMR
00
Interrupt Enable Register 0
[15−0]
IFR0
IFR
01
Interrupt Flag Register 0
[15−0]
ST0_55
−
02
Status Register 0 for C55x
[15−0]
ST1_55
−
03
Status Register 1 for C55x
[15−0]
ST3_55
−
04
Status Register 3 for C55x
[15−0]
−
−
05
Reserved
[15−0]
ST0
ST0
06
Status Register ST0
[15−0]
ST1
ST1
07
Status Register ST1
[15−0]
AC0L
AL
08
Accumulator 0
[15−0]
AC0H
AH
09
AC0G
AG
0A
AC1L
BL
OB
DESCRIPTION
BIT FIELD
[31−16]
[39−32]
Accumulator 1
[15−0]
AC1H
BH
0C
[31−16]
AC1G
BG
0D
[39−32]
T3
TREG
0E
Temporary Register
[15−0]
TRN0
TRN
0F
Transition Register
[15−0]
AR0
AR0
10
Auxiliary Register 0
[15−0]
AR1
AR1
11
Auxiliary Register 1
[15−0]
AR2
AR2
12
Auxiliary Register 2
[15−0]
AR3
AR3
13
Auxiliary Register 3
[15−0]
AR4
AR4
14
Auxiliary Register 4
[15−0]
AR5
AR5
15
Auxiliary Register 5
[15−0]
AR6
AR6
16
Auxiliary Register 6
[15−0]
AR7
AR7
17
Auxiliary Register 7
[15−0]
SP
SP
18
Stack Pointer Register
[15−0]
BK03
BK
19
Circular Buffer Size Register
[15−0]
BRC0
BRC
1A
Block Repeat Counter
[15−0]
RSA0L
RSA
1B
Block Repeat Start Address
[15−0]
REA0L
REA
1C
Block Repeat End Address
[15−0]
PMST
PMST
1D
Processor Mode Status Register
[15−0]
XPC
XPC
1E
Program Counter Extension Register
[7−0]
−
−
1F
Reserved
[15−0]
T0
−
20
Temporary Data Register 0
[15−0]
T1
−
21
Temporary Data Register 1
[15−0]
T2
−
22
Temporary Data Register 2
[15−0]
[15−0]
T3
−
23
Temporary Data Register 3
AC2L
−
24
Accumulator 2
AC2H
−
25
[31−16]
AC2G
−
26
[39−32]
[15−0]
TMS320C54x and C54x are trademarks of Texas Instruments.
46
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−15. CPU Memory-Mapped Registers (Continued)
C54x
REGISTER
WORD ADDRESS
(HEX)
DESCRIPTION
BIT FIELD
CDP
−
27
Coefficient Data Pointer
[15−0]
AC3L
−
28
Accumulator 3
[15−0]
AC3H
−
29
[31−16]
AC3G
−
2A
[39−32]
DPH
−
2B
Extended Data Page Pointer
[6−0]
MDP05
−
2C
Reserved
[6−0]
MDP67
−
2D
Reserved
[6−0]
[15−0]
DP
−
2E
Memory Data Page Start Address
PDP
−
2F
Peripheral Data Page Start Address
[8−0]
BK47
−
30
Circular Buffer Size Register for AR[4−7]
[15−0]
BKC
−
31
Circular Buffer Size Register for CDP
[15−0]
BSA01
−
32
Circular Buffer Start Address Register for AR[0−1]
[15−0]
BSA23
−
33
Circular Buffer Start Address Register for AR[2−3]
[15−0]
BSA45
−
34
Circular Buffer Start Address Register for AR[4−5]
[15−0]
BSA67
−
35
Circular Buffer Start Address Register for AR[6−7]
[15−0]
BSAC
−
36
Circular Buffer Coefficient Start Address Register
[15−0]
BIOS
−
37
Data Page Pointer Storage Location for 128-word Data Table
[15−0]
TRN1
−
38
Transition Register 1
[15−0]
BRC1
−
39
Block Repeat Counter 1
[15−0]
BRS1
−
3A
Block Repeat Save 1
[15−0]
CSR
−
3B
Computed Single Repeat
[15−0]
RSA0H
−
3C
Repeat Start Address 0
[23−16]
RSA0L
−
3D
REA0H
−
3E
REA0L
−
3F
RSA1H
−
40
RSA1L
−
41
REA1H
−
42
REA1L
−
43
RPTC
−
44
Repeat Counter
[15−0]
IER1
−
45
Interrupt Enable Register 1
[15−0]
IFR1
−
46
Interrupt Flag Register 1
[15−0]
DBIER0
−
47
Debug IER0
[15−0]
DBIER1
−
48
Debug IER1
[15−0]
IVPD
−
49
Interrupt Vector Pointer DSP
[15−0]
[15−0]
Repeat End Address 0
[23−16]
[15−0]
Repeat Start Address 1
[23−16]
Repeat End Address 1
[23−16]
[15−0]
[15−0]
IVPH
−
4A
Interrupt Vector Pointer HOST
[15−0]
ST2_55
−
4B
Status Register 2 for C55x
[15−0]
SSP
−
4C
System Stack Pointer
[15−0]
SP
−
4D
User Stack Pointer
[15−0]
SPH
−
4E
Extended Data Page Pointer for the SP and the SSP
[6−0]
CDPH
−
4F
Main Data Page Pointer for the CDP
[6−0]
April 2004 − Revised January 2005
ADVANCE INFORMATION
C55x
REGISTER
SPRS245C
47
Functional Overview
3.9
Peripheral Register Description
Each 5503 device has a set of memory-mapped registers associated with peripherals as listed in Table 3−16
through Table 3−29. Some registers use less than 16 bits. When reading these registers, unused bits are
always read as 0.
NOTE: The CPU access latency to the peripheral memory-mapped registers is 6 CPU cycles.
Following peripheral register update(s), the CPU must wait at least 6 CPU cycles before
attempting to use that peripheral. When more than one peripheral register is updated in a
sequence, the CPU only needs to wait following the final register write. For example, if the
EMIF is being reconfigured, the CPU must wait until the very last EMIF register update takes
effect before trying to access the external memory. The users should consult the respective
peripheral user’s guide to determine if a peripheral requires additional time to initialize itself
to the new configuration after the register updates take effect.
ADVANCE INFORMATION
Table 3−16. Idle Control, Status, and System Registers
WORD ADDRESS
†
REGISTER NAME
DESCRIPTION
RESET VALUE†
0x0001
ICR[7:0]
Idle Control Register
xxxx xxxx 0000 0100
0x0002
ISTR[7:0]
Idle Status Register
xxxx xxxx 0000 0000
0x07FD
SYSR[15:0]
System Register
0000 0000 0000 0000
Hardware reset; x denotes a “don’t care.”
Table 3−17. External Memory Interface Registers
WORD ADDRESS
†
REGISTER NAME
DESCRIPTION
RESET VALUE†
0x0800
EGCR[15:0]
EMIF Global Control Register
xxxx xxxx 0010 xx00
0x0801
EMI_RST
EMIF Global Reset Register
xxxx xxxx xxxx xxxx
0x0802
EMI_BE[13:0]
EMIF Bus Error Status Register
xx00 0000 0000 0000
0x0803
CE0_1[14:0]
EMIF CE0 Space Control Register 1
x010 1111 1111 1111
0x0804
CE0_2[15:0]
EMIF CE0 Space Control Register 2
0100 1111 1111 1111
0x0805
CE0_3[7:0]
EMIF CE0 Space Control Register 3
xxxx xxxx 0000 0000
0x0806
CE1_1[14:0]
EMIF CE1 Space Control Register 1
x010 1111 1111 1111
0x0807
CE1_2[15:0]
EMIF CE1 Space Control Register 2
0100 1111 1111 1111
0x0808
CE1_3[7:0]
EMIF CE1 Space Control Register 3
xxxx xxxx 0000 0000
0x0809
CE2_1[14:0]
EMIF CE2 Space Control Register 1
x010 1111 1111 1111
0x080A
CE2_2[15:0]
EMIF CE2 Space Control Register 2
0101 1111 1111 1111
0x080B
CE2_3[7:0]
EMIF CE2 Space Control Register 3
xxxx xxxx 0000 0000
0x080C
CE3_1[14:0]
EMIF CE3 Space Control Register 1
x010 1111 1111 1111
0x080D
CE3_2[15:0]
EMIF CE3 Space Control Register 2
0101 1111 1111 1111
0x080E
CE3_3[7:0]
EMIF CE3 Space Control Register 3
xxxx xxxx 0000 0000
0x080F
SDC1[15:0]
EMIF SDRAM Control Register 1
1111 1001 0100 1000
0x0810
SDPER[11:0]
EMIF SDRAM Period Register
xxxx 0000 1000 0000
0x0811
SDCNT[11:0]
EMIF SDRAM Counter Register
xxxx 0000 1000 0000
0x0812
INIT
EMIF SDRAM Init Register
xxxx xxxx xxxx xxxx
0x0813
SDC2[9:0]
EMIF SDRAM Control Register 2
xxxx xx11 1111 1111
0x0814
SDC3
EMIF SDRAM Control Register 3
0000 0000 0000 0111
Hardware reset; x denotes a “don’t care.”
48
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−18. DMA Configuration Registers
PORT ADDRESS
(WORD)
REGISTER NAME
DESCRIPTION
RESET VALUE†
GLOBAL REGISTER
0x0E00
DMA_GCR[2:0]
DMA Global Control Register
xxxx xxxx xxxx x000
0x0E02
DMA_GSCR
DMA Software Compatibility Register
0x0E03
DMA_GTCR
DMA Timeout Control Register
0x0C00
DMA_CSDP0
DMA Channel 0 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C01
DMA_CCR0[15:0]
DMA Channel 0 Control Register
0000 0000 0000 0000
0x0C02
DMA_CICR0[5:0]
DMA Channel 0 Interrupt Control Register
xxxx xxxx xx00 0011
0x0C03
DMA_CSR0[6:0]
DMA Channel 0 Status Register
xxxx xxxx xx00 0000
0x0C04
DMA_CSSA_L0
DMA Channel 0 Source Start Address Register
(lower bits)
Undefined
0x0C05
DMA_CSSA_U0
DMA Channel 0 Source Start Address Register
(upper bits)
Undefined
0x0C06
DMA_CDSA_L0
DMA Channel 0 Source Destination Address Register
(lower bits)
Undefined
0x0C07
DMA_CDSA_U0
DMA Channel 0 Source Destination Address Register
(upper bits)
Undefined
0x0C08
DMA_CEN0
DMA Channel 0 Element Number Register
Undefined
0x0C09
DMA_CFN0
DMA Channel 0 Frame Number Register
Undefined
0x0C0A
DMA_CSFI0
DMA Channel 0 Source Frame Index Register
Undefined
0x0C0B
DMA_CSEI0
DMA Channel 0 Source Element Index Register
Undefined
0x0C0C
DMA_CSAC0
DMA Channel 0 Source Address Counter
Undefined
0x0C0D
DMA_CDAC0
DMA Channel 0 Destination Address Counter
Undefined
0x0C0E
DMA_CDEI0
DMA Channel 0 Destination Element Index Register
Undefined
0x0C0F
DMA_CDFI0
DMA Channel 0 Destination Frame Index Register
Undefined
†
ADVANCE INFORMATION
CHANNEL #0 REGISTERS
Hardware reset: x denotes a “don’t care.”
April 2004 − Revised January 2005
SPRS245C
49
Functional Overview
Table 3−18. DMA Configuration Registers (Continued)
PORT ADDRESS
(WORD)
REGISTER NAME
RESET VALUE†
DESCRIPTION
ADVANCE INFORMATION
CHANNEL #1 REGISTERS
0x0C20
DMA_CSDP1
DMA Channel 1 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C21
DMA_CCR1[15:0]
DMA Channel 1 Control Register
0000 0000 0000 0000
0x0C22
DMA_CICR1[5:0]
DMA Channel 1 Interrupt Control Register
xxxx xxxx xx00 0011
0x0C23
DMA_CSR1[6:0]
DMA Channel 1 Status Register
xxxx xxxx xx00 0000
0x0C24
DMA_CSSA_L1
DMA Channel 1 Source Start Address Register
(lower bits)
Undefined
0x0C25
DMA_CSSA_U1
DMA Channel 1 Source Start Address Register
(upper bits)
Undefined
0x0C26
DMA_CDSA_L1
DMA Channel 1 Source Destination Address Register
(lower bits)
Undefined
0x0C27
DMA_CDSA_U1
DMA Channel 1 Source Destination Address Register
(upper bits)
Undefined
0x0C28
DMA_CEN1
DMA Channel 1 Element Number Register
Undefined
0x0C29
DMA_CFN1
DMA Channel 1 Frame Number Register
Undefined
0x0C2A
DMA_CSFI1
DMA Channel 1 Source Frame Index Register
Undefined
0x0C2B
DMA_CSEI1
DMA Channel 1 Source Element Index Register
Undefined
0x0C2C
DMA_CSAC1
DMA Channel 1 Source Address Counter
Undefined
0x0C2D
DMA_CDAC1
DMA Channel 1 Destination Address Counter
Undefined
0x0C2E
DMA_CDEI1
DMA Channel 1 Destination Element Index Register
Undefined
0x0C2F
DMA_CDFI1
DMA Channel 1 Destination Frame Index Register
Undefined
0x0C40
DMA_CSDP2
DMA Channel 2 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C41
DMA_CCR2[15:0]
DMA Channel 2 Control Register
0000 0000 0000 0000
0x0C42
DMA_CICR2[5:0]
DMA Channel 2 Interrupt Control Register
xxxx xxxx xx00 0011
0x0C43
DMA_CSR2[6:0]
DMA Channel 2 Status Register
xxxx xxxx xx00 0000
0x0C44
DMA_CSSA_L2
DMA Channel 2 Source Start Address Register
(lower bits)
Undefined
0x0C45
DMA_CSSA_U2
DMA Channel 2 Source Start Address Register
(upper bits)
Undefined
0x0C46
DMA_CDSA_L2
DMA Channel 2 Source Destination Address Register
(lower bits)
Undefined
0x0C47
DMA_CDSA_U2
DMA Channel 2 Source Destination Address Register
(upper bits)
Undefined
0x0C48
DMA_CEN2
DMA Channel 2 Element Number Register
Undefined
0x0C49
DMA_CFN2
DMA Channel 2 Frame Number Register
Undefined
0x0C4A
DMA_CSFI2
DMA Channel 2 Source Frame Index Register
Undefined
0x0C4B
DMA_CSEI2
DMA Channel 2 Source Element Index Register
Undefined
0x0C4C
DMA_CSAC2
DMA Channel 2 Source Address Counter
Undefined
0x0C4D
DMA_CDAC2
DMA Channel 2 Destination Address Counter
Undefined
0x0C4E
DMA_CDEI2
DMA Channel 2 Destination Element Index Register
Undefined
0x0C4F
DMA_CDFI2
DMA Channel 2 Destination Frame Index Register
Undefined
CHANNEL #2 REGISTERS
†
50
Hardware reset: x denotes a “don’t care.”
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−18. DMA Configuration Registers (Continued)
PORT ADDRESS
(WORD)
REGISTER NAME
DESCRIPTION
RESET VALUE†
DMA_CSDP3
DMA Channel 3 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C61
DMA_CCR3[15:0]
DMA Channel 3 Control Register
0000 0000 0000 0000
0x0C62
DMA_CICR3[5:0]
DMA Channel 3 Interrupt Control Register
xxxx xxxx xx00 0011
0x0C63
DMA_CSR3[6:0]
DMA Channel 3 Status Register
xxxx xxxx xx00 0000
0x0C64
DMA_CSSA_L3
DMA Channel 3 Source Start Address Register
(lower bits)
Undefined
0x0C65
DMA_CSSA_U3
DMA Channel 3 Source Start Address Register
(upper bits)
Undefined
0x0C66
DMA_CDSA_L3
DMA Channel 3 Source Destination Address Register
(lower bits)
Undefined
0x0C67
DMA_CDSA_U3
DMA Channel 3 Source Destination Address Register
(upper bits)
Undefined
0x0C68
DMA_CEN3
DMA Channel 3 Element Number Register
Undefined
0x0C69
DMA_CFN3
DMA Channel 3 Frame Number Register
Undefined
0x0C6A
DMA_CSFI3
DMA Channel 3 Source Frame Index Register
Undefined
0x0C6B
DMA_CSEI3
DMA Channel 3 Source Element Index Register
Undefined
0x0C6C
DMA_CSAC3
DMA Channel 3 Source Address Counter
Undefined
0x0C6D
DMA_CDAC3
DMA Channel 3 Destination Address Counter
Undefined
0x0C6E
DMA_CDEI3
DMA Channel 3 Destination Element Index Register
Undefined
0x0C6F
DMA_CDFI3
DMA Channel 3 Destination Frame Index Register
Undefined
0x0C80
DMA_CSDP4
DMA Channel 4 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C81
DMA_CCR4[15:0]
DMA Channel 4 Control Register
0000 0000 0000 0000
0x0C82
DMA_CICR4[5:0]
DMA Channel 4 Interrupt Control Register
xxxx xxxx xx00 0011
0x0C83
DMA_CSR4[6:0]
DMA Channel 4 Status Register
xxxx xxxx xx00 0000
0x0C84
DMA_CSSA_L4
DMA Channel 4 Source Start Address Register
(lower bits)
Undefined
0x0C85
DMA_CSSA_U4
DMA Channel 4 Source Start Address Register
(upper bits)
Undefined
0x0C86
DMA_CDSA_L4
DMA Channel 4 Source Destination Address Register
(lower bits)
Undefined
0x0C87
DMA_CDSA_U4
DMA Channel 4 Source Destination Address Register
(upper bits)
Undefined
0x0C88
DMA_CEN4
DMA Channel 4 Element Number Register
Undefined
0x0C89
DMA_CFN4
DMA Channel 4 Frame Number Register
Undefined
0x0C8A
DMA_CSFI4
DMA Channel 4 Source Frame Index Register
Undefined
0x0C8B
DMA_CSEI4
DMA Channel 4 Source Element Index Register
Undefined
0x0C8C
DMA_CSAC4
DMA Channel 4 Source Address Counter
Undefined
0x0C8D
DMA_CDAC4
DMA Channel 4 Destination Address Counter
Undefined
0x0C8E
DMA_CDEI4
DMA Channel 4 Destination Element Index Register
Undefined
0x0C8F
DMA_CDFI4
DMA Channel 4 Destination Frame Index Register
Undefined
ADVANCE INFORMATION
CHANNEL #3 REGISTERS
0x0C60
CHANNEL #4 REGISTERS
†
Hardware reset: x denotes a “don’t care.”
April 2004 − Revised January 2005
SPRS245C
51
Functional Overview
Table 3−18. DMA Configuration Registers (Continued)
PORT ADDRESS
(WORD)
REGISTER NAME
RESET VALUE†
DESCRIPTION
ADVANCE INFORMATION
CHANNEL #5 REGISTERS
0x0CA0
DMA_CSDP5
DMA Channel 5 Source Destination
Parameters Register
0000 0000 0000 0000
0x0CA1
DMA_CCR5[15:0]
DMA Channel 5 Control Register
0000 0000 0000 0000
0x0CA2
DMA_CICR5[5:0]
DMA Channel 5 Interrupt Control Register
xxxx xxxx xx00 0011
0x0CA3
DMA_CSR5[6:0]
DMA Channel 5 Status Register
xxxx xxxx xx00 0000
0x0CA4
DMA_CSSA_L5
DMA Channel 5 Source Start Address Register
(lower bits)
Undefined
0x0CA5
DMA_CSSA_U5
DMA Channel 5 Source Start Address Register
(upper bits)
Undefined
0x0CA6
DMA_CDSA_L5
DMA Channel 5 Source Destination Address Register
(lower bits)
Undefined
0x0CA7
DMA_CDSA_U5
DMA Channel 5 Source Destination Address Register
(upper bits)
Undefined
0x0CA8
DMA_CEN5
DMA Channel 5 Element Number Register
Undefined
0x0CA9
DMA_CFN5
DMA Channel 5 Frame Number Register
Undefined
0x0CAA
DMA_CSFI5
DMA Channel 5 Source Frame Index Register
Undefined
0x0CAB
DMA_CSEI5
DMA Channel 5 Source Element Index Register
Undefined
0x0CAC
DMA_CSAC5
DMA Channel 5 Source Address Counter
Undefined
0x0CAD
DMA_CDAC5
DMA Channel 5 Destination Address Counter
Undefined
0x0CAE
DMA_CDEI5
DMA Channel 5 Destination Element Index Register
Undefined
0x0CAF
DMA_CDFI5
DMA Channel 5 Destination Frame Index Register
Undefined
†
Hardware reset: x denotes a “don’t care.”
Table 3−19. Real-Time Clock Registers
WORD ADDRESS
REGISTER NAME
RESET VALUE†
0x1800
RTCSEC
Seconds Register
0000 0000 0000 0000
0x1801
RTCSECA
Seconds Alarm Register
0000 0000 0000 0000
0x1802
RTCMIN
Minutes Register
0000 0000 0000 0000
0x1803
RTCMINA
Minutes Alarm Register
0000 0000 0000 0000
0x1804
RTCHOUR
Hours Register
0000 0000 0000 0000
0x1805
RTCHOURA
Hours Alarm Register
0000 0000 0000 0000
0x1806
RTCDAYW
Day of the Week Register
0000 0000 0000 0000
0x1807
RTCDAYM
Day of the Month (date) Register
0000 0000 0000 0000
0x1808
RTCMONTH
Month Register
0000 0000 0000 0000
0x1809
RTCYEAR
Year Register
0000 0000 0000 0000
0x180A
RTCPINTR
Periodic Interrupt Selection Register
0000 0000 0000 0000
0x180B
RTCINTEN
Interrupt Enable Register
0000 0000 1000 0000
0x180C
RTCINTFL
Interrupt Flag Register
0000 0000 0000 0000
0x180D−0x1BFF
†
DESCRIPTION
Reserved
Hardware reset; x denotes a “don’t care.”
52
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−20. Clock Generator
WORD ADDRESS
0x1C00
†
REGISTER NAME
CLKMD[14:0]
DESCRIPTION
Clock Mode Register
RESET VALUE†
0010 0000 0000 0010 DIV1 mode
Hardware reset; x denotes a “don’t care.”
Table 3−21. Timers
†
REGISTER NAME
DESCRIPTION
RESET VALUE†
0x1000
TIM0[15:0]
Timer Count Register, Timer #0
1111 1111 1111 1111
0x1001
PRD0[15:0]
Period Register, Timer #0
1111 1111 1111 1111
0x1002
TCR0[15:0]
Timer Control Register, Timer #0
0000 0000 0001 0000
0x1003
PRSC0[15:0]
Timer Prescaler Register, Timer #0
xxxx 0000 xxxx 0000
0x2400
TIM1[15:0]
Timer Count Register, Timer #1
1111 1111 1111 1111
0x2401
PRD1[15:0]
Period Register, Timer #1
1111 1111 1111 1111
0x2402
TCR1[15:0]
Timer Control Register, Timer #1
0000 0000 0001 0000
0x2403
PRSC1[15:0]
Timer Prescaler Register, Timer #1
xxxx 0000 xxxx 0000
ADVANCE INFORMATION
WORD ADDRESS
Hardware reset; x denotes a “don’t care.”
April 2004 − Revised January 2005
SPRS245C
53
Functional Overview
Table 3−22. Multichannel Serial Port #0
ADVANCE INFORMATION
PORT ADDRESS
(WORD)
REGISTER NAME
RESET VALUE†
DESCRIPTION
0x2800
DRR2_0[15:0]
Data Receive Register 2, McBSP #0
0000 0000 0000 0000
0x2801
DRR1_0[15:0]
Data Receive Register 1, McBSP #0
0000 0000 0000 0000
0x2802
DXR2_0[15:0]
Data Transmit Register 2, McBSP #0
0000 0000 0000 0000
0x2803
DXR1_0[15:0]
Data Transmit Register 1, McBSP #0
0000 0000 0000 0000
0x2804
SPCR2_0[15:0]
Serial Port Control Register 2, McBSP #0
0000 0000 0000 0000
0x2805
SPCR1_0[15:0]
Serial Port Control Register 1, McBSP #0
0000 0000 0000 0000
0x2806
RCR2_0[15:0]
Receive Control Register 2, McBSP #0
0000 0000 0000 0000
0x2807
RCR1_0[15:0]
Receive Control Register 1, McBSP #0
0000 0000 0000 0000
0x2808
XCR2_0[15:0]
Transmit Control Register 2, McBSP #0
0000 0000 0000 0000
0x2809
XCR1_0[15:0]
Transmit Control Register 1, McBSP #0
0000 0000 0000 0000
0x280A
SRGR2_0[15:0]
Sample Rate Generator Register 2, McBSP #0
0020 0000 0000 0000
0x280B
SRGR1_0[15:0]
Sample Rate Generator Register 1, McBSP #0
0000 0000 0000 0001
0x280C
MCR2_0[15:0]
Multichannel Control Register 2, McBSP #0
0000 0000 0000 0000
0x280D
MCR1_0[15:0]
Multichannel Control Register 1, McBSP #0
0000 0000 0000 0000
0x280E
RCERA_0[15:0]
Receive Channel Enable Register Partition A, McBSP #0
0000 0000 0000 0000
0x280F
RCERB_0[15:0]
Receive Channel Enable Register Partition B, McBSP #0
0000 0000 0000 0000
0x2810
XCERA_0[15:0]
Transmit Channel Enable Register Partition A, McBSP #0
0000 0000 0000 0000
0x2811
XCERB_0[15:0]
Transmit Channel Enable Register Partition B, McBSP #0
0000 0000 0000 0000
0x2812
PCR0[15:0]
Pin Control Register, McBSP #0
0000 0000 0000 0000
0x2813
RCERC_0[15:0]
Receive Channel Enable Register Partition C, McBSP #0
0000 0000 0000 0000
0x2814
RCERD_0[15:0]
Receive Channel Enable Register Partition D, McBSP #0
0000 0000 0000 0000
0x2815
XCERC_0[15:0]
Transmit Channel Enable Register Partition C, McBSP #0
0000 0000 0000 0000
0x2816
XCERD_0[15:0]
Transmit Channel Enable Register Partition D, McBSP #0
0000 0000 0000 0000
0x2817
RCERE_0[15:0]
Receive Channel Enable Register Partition E, McBSP #0
0000 0000 0000 0000
0x2818
RCERF_0[15:0]
Receive Channel Enable Register Partition F, McBSP #0
0000 0000 0000 0000
0x2819
XCERE_0[15:0]
Transmit Channel Enable Register Partition E, McBSP #0
0000 0000 0000 0000
0x281A
XCERF_0[15:0]
Transmit Channel Enable Register Partition F, McBSP #0
0000 0000 0000 0000
0x281B
RCERG_0[15:0]
Receive Channel Enable Register Partition G, McBSP #0
0000 0000 0000 0000
0x281C
RCERH_0[15:0]
Receive Channel Enable Register Partition H, McBSP #0
0000 0000 0000 0000
0x281D
XCERG_0[15:0]
Transmit Channel Enable Register Partition G, McBSP #0
0000 0000 0000 0000
0x281E
XCERH_0[15:0]
Transmit Channel Enable Register Partition H, McBSP #0
0000 0000 0000 0000
†
54
Hardware reset; x denotes a “don’t care.”
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−23. Multichannel Serial Port #1
REGISTER NAME
DESCRIPTION
RESET VALUE†
0x2C00
DRR2_1[15:0]
Data Receive Register 2, McBSP #1
0000 0000 0000 0000
0x2C01
DRR1_1[15:0]
Data Receive Register 1, McBSP #1
0000 0000 0000 0000
0x2C02
DXR2_1[15:0]
Data Transmit Register 2, McBSP #1
0000 0000 0000 0000
0x2C03
DXR1_1[15:0]
Data Transmit Register 1, McBSP #1
0000 0000 0000 0000
0x2C04
SPCR2_1[15:0]
Serial Port Control Register 2, McBSP #1
0000 0000 0000 0000
0x2C05
SPCR1_1[15:0]
Serial Port Control Register 1, McBSP #1
0000 0000 0000 0000
0x2C06
RCR2_1[15:0]
Receive Control Register 2, McBSP #1
0000 0000 0000 0000
0x2C07
RCR1_1[15:0]
Receive Control Register 1, McBSP #1
0000 0000 0000 0000
0x2C08
XCR2_1[15:0]
Transmit Control Register 2, McBSP #1
0000 0000 0000 0000
0x2C09
XCR1_1[15:0]
Transmit Control Register 1, McBSP #1
0000 0000 0000 0000
0x2C0A
SRGR2_1[15:0]
Sample Rate Generator Register 2, McBSP #1
0020 0000 0000 0000
0x2C0B
SRGR1_1[15:0]
Sample Rate Generator Register 1, McBSP #1
0000 0000 0000 0001
0x2C0C
MCR2_1[15:0]
Multichannel Control Register 2, McBSP #1
0000 0000 0000 0000
0x2C0D
MCR1_1[15:0]
Multichannel Control Register 1, McBSP #1
0000 0000 0000 0000
0x2C0E
RCERA_1[15:0]
Receive Channel Enable Register Partition A, McBSP #1
0000 0000 0000 0000
0x2C0F
RCERB_1[15:0]
Receive Channel Enable Register Partition B, McBSP #1
0000 0000 0000 0000
0x2C10
XCERA_1[15:0]
Transmit Channel Enable Register Partition A, McBSP #1
0000 0000 0000 0000
0x2C11
XCERB_1[15:0]
Transmit Channel Enable Register Partition B, McBSP #1
0000 0000 0000 0000
0x2C12
PCR1[15:0]
Pin Control Register, McBSP #1
0000 0000 0000 0000
0x2C13
RCERC_1[15:0]
Receive Channel Enable Register Partition C, McBSP #1
0000 0000 0000 0000
0x2C14
RCERD_1[15:0]
Receive Channel Enable Register Partition D, McBSP #1
0000 0000 0000 0000
0x2C15
XCERC_1[15:0]
Transmit Channel Enable Register Partition C, McBSP #1
0000 0000 0000 0000
0x2C16
XCERD_1[15:0]
Transmit Channel Enable Register Partition D, McBSP #1
0000 0000 0000 0000
0x2C17
RCERE_1[15:0]
Receive Channel Enable Register Partition E, McBSP #1
0000 0000 0000 0000
0x2C18
RCERF_1[15:0]
Receive Channel Enable Register Partition F, McBSP #1
0000 0000 0000 0000
0x2C19
XCERE_1[15:0]
Transmit Channel Enable Register Partition E, McBSP #1
0000 0000 0000 0000
0x2C1A
XCERF_1[15:0]
Transmit Channel Enable Register Partition F, McBSP #1
0000 0000 0000 0000
0x2C1B
RCERG_1[15:0]
Receive Channel Enable Register Partition G, McBSP #1
0000 0000 0000 0000
0x2C1C
RCERH_1[15:0]
Receive Channel Enable Register Partition H, McBSP #1
0000 0000 0000 0000
0x2C1D
XCERG_1[15:0]
Transmit Channel Enable Register Partition G, McBSP #1
0000 0000 0000 0000
0x2C1E
XCERH_1[15:0]
Transmit Channel Enable Register Partition H, McBSP #1
0000 0000 0000 0000
†
ADVANCE INFORMATION
PORT ADDRESS
(WORD)
Hardware reset; x denotes a “don’t care.”
April 2004 − Revised January 2005
SPRS245C
55
Functional Overview
Table 3−24. Multichannel Serial Port #2
ADVANCE INFORMATION
PORT ADDRESS
(WORD)
†
REGISTER NAME
RESET VALUE†
DESCRIPTION
0x3000
DRR2_2[15:0]
Data Receive Register 2, McBSP #2
0000 0000 0000 0000
0x3001
DRR1_2[15:0]
Data Receive Register 1, McBSP #2
0000 0000 0000 0000
0x3002
DXR2_2[15:0]
Data Transmit Register 2, McBSP #2
0000 0000 0000 0000
0x3003
DXR1_2[15:0]
Data Transmit Register 1, McBSP #2
0000 0000 0000 0000
0x3004
SPCR2_2[15:0]
Serial Port Control Register 2, McBSP #2
0000 0000 0000 0000
0x3005
SPCR1_2[15:0]
Serial Port Control Register 1, McBSP #2
0000 0000 0000 0000
0x3006
RCR2_2[15:0]
Receive Control Register 2, McBSP #2
0000 0000 0000 0000
0x3007
RCR1_2[15:0]
Receive Control Register 1, McBSP #2
0000 0000 0000 0000
0x3008
XCR2_2[15:0]
Transmit Control Register 2, McBSP #2
0000 0000 0000 0000
0x3009
XCR1_2[15:0]
Transmit Control Register 1, McBSP #2
0000 0000 0000 0000
0x300A
SRGR2_2[15:0]
Sample Rate Generator Register 2, McBSP #2
0020 0000 0000 0000
0x300B
SRGR1_2[15:0]
Sample Rate Generator Register 1, McBSP #2
0000 0000 0000 0001
0x300C
MCR2_2[15:0]
Multichannel Control Register 2, McBSP #2
0000 0000 0000 0000
0x300D
MCR1_2[15:0]
Multichannel Control Register 1, McBSP #2
0000 0000 0000 0000
0x300E
RCERA_2[15:0]
Receive Channel Enable Register Partition A, McBSP #2
0000 0000 0000 0000
0x300F
RCERB_2[15:0]
Receive Channel Enable Register Partition B, McBSP #2
0000 0000 0000 0000
0x3010
XCERA_2[15:0]
Transmit Channel Enable Register Partition A, McBSP #2
0000 0000 0000 0000
0x3011
XCERB_2[15:0]
Transmit Channel Enable Register Partition B, McBSP #2
0000 0000 0000 0000
0x3012
PCR2[15:0]
Pin Control Register, McBSP #2
0000 0000 0000 0000
0x3013
RCERC_2[15:0]
Receive Channel Enable Register Partition C, McBSP #2
0000 0000 0000 0000
0x3014
RCERD_2[15:0]
Receive Channel Enable Register Partition D, McBSP #2
0000 0000 0000 0000
0x3015
XCERC_2[15:0]
Transmit Channel Enable Register Partition C, McBSP #2
0000 0000 0000 0000
0x3016
XCERD_2[15:0]
Transmit Channel Enable Register Partition D, McBSP #2
0000 0000 0000 0000
0x3017
RCERE_2[15:0]
Receive Channel Enable Register Partition E, McBSP #2
0000 0000 0000 0000
0x3018
RCERF_2[15:0]
Receive Channel Enable Register Partition F, McBSP #2
0000 0000 0000 0000
0x3019
XCERE_2[15:0]
Transmit Channel Enable Register Partition E, McBSP #2
0000 0000 0000 0000
0x301A
XCERF_2[15:0]
Transmit Channel Enable Register Partition F, McBSP #2
0000 0000 0000 0000
0x301B
RCERG_2[15:0]
Receive Channel Enable Register Partition G, McBSP #2
0000 0000 0000 0000
0x301C
RCERH_2[15:0]
Receive Channel Enable Register Partition H, McBSP #2
0000 0000 0000 0000
0x301D
XCERG_2[15:0]
Transmit Channel Enable Register Partition G, McBSP #2
0000 0000 0000 0000
0x301E
XCERH_2[15:0]
Transmit Channel Enable Register Partition H, McBSP #2
0000 0000 0000 0000
Hardware reset; x denotes a “don’t care.”
56
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−25. GPIO
WORD
ADDRESS
REGISTER
NAME
PIN
RESET VALUE†
DESCRIPTION
0x3400
IODIR[7:0]
GPIO[7:0]
General-purpose I/O Direction Register
0000 0000 0000 0000
0x3401
IODATA[7:0]
GPIO[7:0]
General-purpose I/O Data Register
0000 0000 xxxx xxxx
0x4400
AGPIOEN[15:0]
A[15:0]
Address/GPIO Enable Register
0000 0000 0000 0000
0x4401
AGPIODIR[15:0]
A[15:0]
Address/GPIO Direction Register
0000 0000 0000 0000
0x4402
AGPIODATA[15:0]
A[15:0]
Address/GPIO Data Register
xxxx xxxx xxxx xxxx
0x4403
EHPIGPIOEN[5:0]
GPIO[13:8]
EHPI/GPIO Enable Register
0000 0000 0000 0000
0x4404
EHPIGPIODIR[5:0]
GPIO[13:8]
EHPI/GPIO Direction Register
0000 0000 0000 0000
0x4405
EHPIGPIODATA[5:0]
GPIO[13:8]
EHPI/GPIO Data Register
0000 0000 00xx xxxx
†
Hardware reset; x denotes a “don’t care.”
Table 3−26. Device Revision ID
0x3803
‡
REGISTER NAME
Rev ID[4:1]
VALUE‡
DESCRIPTION
Silicon Revision Identification
ADVANCE INFORMATION
WORD ADDRESS
Rev. 1.0: xxxx xxxx xxx0 001x
x denotes a “don’t care.”
Table 3−27. I2C Module Registers
WORD ADDRESS
REGISTER NAME
DESCRIPTION
RESET VALUE†
0x3C00
I2COAR[9:0] §
I2C Own Address Register
0000 0000 0000 0000
0x3C01
I2CIMR
I2C Interrupt Mask Register
0000 0000 0000 0000
0x3C02
I2CSTR
I2C Status Register
0000 0001 0000 0000
0x3C03
I2CCLKL[15:0]
I2C
Clock Divider Low Register
0000 0000 0000 0000
0x3C04
I2CCLKH[15:0]
I2C Clock Divider High Register
0000 0000 0000 0000
0x3C05
I2CCNT[15:0]
I2C Data Count
0000 0000 0000 0000
0x3C06
I2CDRR[7:0]
I2C
0000 0000 0000 0000
0x3C07
I2CSAR[9:0]
I2C Slave Address Register
0000 0011 1111 1111
0x3C08
I2CDXR[7:0]
I2C
0000 0000 0000 0000
0x3C09
I2CMDR[14:0]
I2C Mode Register
0000 0000 0000 0000
0x3C0A
I2CIVR
I2C Interrupt Vector Register
0000 0000 0000 0000
0x3C0B
−
Reserved
0x3C0C
I2CPSC
I2C Prescaler Register
0x3C0D
−
Reserved
0x3C0E
−
Reserved
0x3C0F
I2CMDR2
I2C Mode Register 2
−
I2CRSR
I2C
−
I2CXSR
I2C Transmit Shift Register (not accessible to the CPU)
Data Receive Register
Data Transmit Register
0000 0000 0000 0000
0000 0000 0000 0000
Receive Shift Register (not accessible to the CPU)
†
Hardware reset; x denotes a “don’t care.”
This register must be set by the user. The user may program the I2C’s own address to any value, as long as the value does not conflict with
the I2C addresses of other components connected to the I2C bus.
NOTE: I2C protocol compatible, no fail-safe buffer.
§
April 2004 − Revised January 2005
SPRS245C
57
Functional Overview
Table 3−28. Watchdog Timer Registers
WORD ADDRESS
†
REGISTER NAME
DESCRIPTION
RESET VALUE†
0x4000
WDTIM[15:0]
WD Timer Counter Register
1111 1111 1111 1111
0x4001
WDPRD[15:0]
WD Timer Period Register
1111 1111 1111 1111
0x4002
WDTCR[13:0]
WD Timer Control Register
0000 0011 1100 1111
0x4003
WDTCR2[15:0]
WD Timer Control Register 2
0001 0000 0000 0000
Hardware reset; x denotes a “don’t care.”
Table 3−29. External Bus Selection Register
WORD ADDRESS
0x6C00
†
EBSR[15:0]
DESCRIPTION
External Bus Selection Register
RESET VALUE†
0000 0000 0000 0011‡
Hardware reset; x denotes a “don’t care.”
The reset value is 0000 0000 0000 0001 if GPIO0 = 1; the value is 0000 0000 0000 0011 if GPIO0 = 0.
ADVANCE INFORMATION
‡
REGISTER NAME
58
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.10 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−30.
Table 3−30. Interrupt Table
SOFTWARE
(TRAP)
EQUIVALENT
RELATIVE
LOCATION†
(HEX BYTES)
PRIORITY
FUNCTION
RESET
SINT0
0
0
Reset (hardware and software)
NMI‡
SINT1
8
1
Nonmaskable interrupt
BERR
SINT24
C0
2
Bus Error interrupt
INT0
SINT2
10
3
External interrupt #0
INT1
SINT16
80
4
External interrupt #1
INT2
SINT3
18
5
External interrupt #2
TINT0
SINT4
20
6
Timer #0 interrupt
RINT0
SINT5
28
7
McBSP #0 receive interrupt
XINT0
SINT17
88
8
McBSP #0 transmit interrupt
RINT1
SINT6
30
9
McBSP #1 receive interrupt
XINT1
SINT7
38
10
McBSP #1 transmit interrupt
−
SINT8
40
11
Software interrupt #8
DMAC0
SINT18
90
12
DMA Channel #0 interrupt
DMAC1
SINT9
48
13
DMA Channel #1 interrupt
DSPINT
SINT10
50
14
Interrupt from host
INT3/WDTINT
SINT11
58
15
External interrupt #3 or Watchdog timer interrupt
INT4/RTC§
SINT19
98
16
External interrupt #4 or RTC interrupt
RINT2
SINT12
60
17
McBSP #2 receive interrupt
XINT2
SINT13
68
18
McBSP #2 transmit interrupt
DMAC2
SINT20
A0
19
DMA Channel #2 interrupt
DMAC3
SINT21
A8
20
DMA Channel #3 interrupt
DMAC4
SINT14
70
21
DMA Channel #4 interrupt
DMAC5
SINT15
78
22
DMA Channel #5 interrupt
TINT1
SINT22
B0
23
Timer #1 interrupt
IIC
SINT23
B8
24
I2C interrupt
DLOG
SINT25
C8
25
Data Log interrupt
RTOS
SINT26
D0
26
Real-time Operating System interrupt
−
SINT27
D8
27
Software interrupt #27
−
SINT28
E0
28
Software interrupt #28
−
SINT29
E8
29
Software interrupt #29
−
SINT30
F0
30
Software interrupt #30
−
SINT31
F8
31
Software interrupt #31
ADVANCE INFORMATION
NAME
†
Absolute addresses of the interrupt vector locations are determined by the contents of the IVPD and IVPH registers. Interrupt vectors for
interrupts 0−15 and 24−31 are relative to IVPD. Interrupt vectors for interrupts 16−23 are relative to IVPH.
‡ The NMI pin is internally tied high. However, NMI interrupt vector can be used for SINT1 and Watchdog Timer Interrupt.
§ It is recommended that either the INT4 or RTC interrupt be used. If both INT4 and RTC interrupts are used, one interrupt event can potentially
hold off the other interrupt. For example, if INT4 is asserted first and held low, the RTC interrupt will not be recognized until the INT4 pin is back
to high-logic state again. The INT4 pin must be pulled high if only the RTC interrupt is used.
April 2004 − Revised January 2005
SPRS245C
59
Functional Overview
3.10.1
IFR and IER Registers
The IFR0 (Interrupt Flag Register 0) and IER0 (Interrupt Enable Register 0) bit layouts are shown in
Figure 3−17.
15
14
13
12
11
10
9
8
DMAC5
DMAC4
XINT2
RINT2
INT3/
WDTINT
DSPINT
DMAC1
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
XINT1
RINT1
RINT0
TINT0
INT2
INT0
R/W
R/W
R/W
R/W
R/W
R/W
0
Reserved
LEGEND: R = Read, W = Write, n = value after reset
ADVANCE INFORMATION
Figure 3−17. IFR0 and IER0 Bit Locations
Table 3−31. IFR0 and IER0 Register Bit Fields
BIT
†
FUNCTION
NUMBER
NAME
15
DMAC5
DMA channel 5 interrupt flag/mask bit
14
DMAC4
DMA channel 4 interrupt flag/mask bit
13
XINT2
This bit is used as the McBSP2 transmit interrupt flag/mask bit.
12
RINT2
McBSP2 receive interrupt flag/mask bit.
11
INT3/WDTINT
10
DSPINT
HPI host-to-DSP interrupt flag/mask.
9
DMAC1
DMA channel 1 interrupt flag/mask bit
8
−
This bit is used as either the external user interrupt 3 flag/mask bit, or the watchdog timer interrupt
flag/mask bit.†
Reserved. This bit should always be written with 0.
7
XINT1
This bit is used as the McBSP1 transmit interrupt flag/mask bit.
6
RINT1
McBSP1 receive interrupt flag/mask bit.
5
RINT0
McBSP0 receive interrupt flag bit
4
TINT0
Timer 0 interrupt flag bit
3
INT2
External interrupt 2 flag bit
2
INT0
External interrupt 0 flag bit
1−0
−
Reserved for future expansion. These bits should always be written with 0.
It is possible to have active interrupts simultaneously from both the external INT3 source and the watchdog timer. When an interrupt is detected
in this bit, the watchdog timer status register should be polled to determine if the watchdog timer is the interrupt source.
60
SPRS245C
April 2004 − Revised January 2005
Functional Overview
The IFR1 (Interrupt Flag Register 1) and IER1 (Interrupt Enable Register 1) bit layouts are shown in
Figure 3−18.
15
11
10
9
8
Reserved
RTOS
DLOG
BERR
R/W−00000†
R/W−0
R/W−0
R/W−0
7
6
5
4
3
2
1
0
I2C
TINT1
DMAC3
DMAC2
INT4/RTC
DMAC0
XINT0
INT1
R/W−0
R/W−0
R/W−0
R/W−0
R/W−0
R/W−0
R/W−0
R/W−0
ADVANCE INFORMATION
NOTE: It is possible to have active interrupts simultaneously from both the external interrupt 4
(INT4) and the real-time clock (RTC). When an interrupt is detected in this bit, the real-time
clock status register should be polled to determine if the real-time clock is the source of the
interrupt.
LEGEND: R = Read, W = Write, n = value after reset
† Always write zeros.
Figure 3−18. IFR1 and IER1 Bit Locations
Table 3−32. IFR1 and IER1 Register Bit Fields
BIT
NUMBER
FUNCTION
NAME
15−11
−
10
RTOS
Reserved for future expansion. These bits should always be written with 0.
Real-time operating system interrupt flag/mask bit
9
DLOG
Data log interrupt flag/mask bit
8
BERR
Bus error interrupt flag/mask bit
7
I2C
I2C interrupt flag/mask bit
6
TINT1
5
DMAC3
DMA channel 3 interrupt flag/mask bit
4
DMAC2
DMA channel 2 interrupt flag/mask bit
3
INT4/RTC
2
DMAC0
1
XINT0
0
INT1
April 2004 − Revised January 2005
Timer 1 interrupt flag/mask bit
This bit can be used as either the external user interrupt 4 flag/mask bit, or the real-time clock
interrupt flag/mask bit.
DMA channel 0 interrupt flag/mask bit
McBSP transmit 0 interrupt flag/mask bit
External user interrupt 1 flag/mask bit
SPRS245C
61
Functional Overview
3.10.2
Interrupt Timing
The external interrupts (INT[4:0]) are synchronized to the CPU by way of a two-flip-flop synchronizer. The
interrupt inputs are sampled on falling edges of the CPU clock. A sequence of 1-1-0-0-0 on consecutive cycles
on the interrupt pin is required for an interrupt to be detected. Therefore, the minimum low pulse duration on
the external interrupts on the 5503 is three CPU clock periods.
3.10.3
Waking Up From IDLE Condition
One of the following four events can wake up the CPU from IDLE:
•
Hardware Reset
•
External Interrupt
•
RTC Interrupt
ADVANCE INFORMATION
3.10.3.1 Waking Up From IDLE With Oscillator Disabled
With an external interrupt or an RTC interrupt, the clock generation circuit wakes up the oscillator. In the case
of the interrupt being disabled by clearing the associated bit in the Interrupt Enable Register (IERx), the CPU
is not “woken up”. If the external interrupt serves as the wake-up event, the interrupt line must stay low for a
minimum of 3 CPU cycles after the oscillator is stabilized to wake up the CPU. Otherwise, only the clock
domain will wake up and another external interrupt will be needed to wake up the CPU.
3.10.4
Idling Clock Domain When External Parallel Bus Operating in EHPI Mode
The clock domain cannot be idled when the External Parallel Bus is operating in EHPI mode to ensure host
access to the DSP memory. To work around this restriction, use the HIDL bit of the External Bus Selection
Register (EBSR) with the CLKGENI bit of the Idle Control Register (ICR) to idle the clock domain.
62
SPRS245C
April 2004 − Revised January 2005
Support
4
Support
4.1
Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability
4.1.1 Initialization Requirements for Boundary Scan Test
The TMS320VC5503 uses the JTAG port for boundary scan tests, emulation capability and factory test
purposes. To use boundary scan test, the EMU0 and EMU1/OFF pins must be held HIGH through a rising edge
of the TRST signal prior to the first scan. This operation selects the appropriate TAP control for boundary scan.
If at any time during a boundary scan test a rising edge of TRST occurs when EMU0 or EMU1/OFF are not
high, a factory test mode may be selected preventing boundary scan test from being completed. For this
reason, it is recommended that EMU0 and EMU1/OFF be pulled or driven high at all times during boundary
scan test.
BSDL models are available on the web in the TMS320VC5503 product folder under the “simulation models”
section.
4.2
Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the TMS320C5000 platform of DSPs:
•
•
•
•
•
TMS320C55x DSP Functional Overview (literature number SPRU312)
Device-specific data sheets and data manuals
Complete user’s guides
Development support tools
Hardware and software application reports
TMS320C55x reference documentation includes, but is not limited to, the following:
•
•
•
•
•
•
•
•
•
TMS320C55x DSP CPU Reference Guide (literature number SPRU371)
TMS320C55x DSP Mnemonic Instruction Set Reference Guide (literature number SPRU374)
TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature number SPRU375)
TMS320C55x DSP Programmer’s Guide (literature number SPRU376)
TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317)
TMS320C55x Optimizing C/C++ Compiler User’s Guide (literature number SPRU281)
TMS320C55x Assembly Language Tools User’s Guide (literature number SPRU280)
TMS320C55x DSP Library Programmer’s Reference (literature number SPRU422)
Using the TMS320VC5503/VC5507/VC5509/VC5509A Bootloader application report (literature number
SPRA375)
The reference guides describe in detail the TMS320C55x DSP products currently available and the
hardware and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320 and TMS320C5000 are trademarks of Texas Instruments.
April 2004 − Revised January 2005
SPRS245C
63
ADVANCE INFORMATION
4.1.2 Boundary Scan Description Language (BSDL) Model
Support
4.3
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS320C6412GDK600). Texas Instruments recommends two of three possible prefix designators for
its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS
Fully qualified production device
ADVANCE INFORMATION
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
4.4
TMS320VC5503 Device Nomenclature
TMS 320 VC 5503
PREFIX
TMX =
TMP =
TMS =
SMJ =
SM =
Experimental device
Prototype device
Qualified device
MIL-STD-883C
High Rel (non-883C)
GHH
PACKAGE TYPE†
GHH = 179-terminal plastic BGA
PGE = 144-pin plastic LQFP
DEVICE FAMILY
320 = TMS320 family
DEVICE
55x DSP:
5503
TECHNOLOGY
VC = Dual-Supply CMOS
†
BGA =
LQFP =
Ball Grid Array
Low-Profile Quad Flatpack
Figure 4−1. Device Nomenclature for the TMS320VC5503
64
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320VC5503 DSP.
All electrical and switching characteristics in this data manual are valid over the recommended operating
conditions unless otherwise specified.
5.1
Absolute Maximum Ratings
Supply voltage I/O range, DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.0 V
Supply voltage core range, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 2.0 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.5 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.5 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C
April 2004 − Revised January 2005
SPRS245C
65
ADVANCE INFORMATION
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to VSS. Figure 5−1 provides the test load circuit
values for a 3.3-V I/O.
Electrical Specifications
5.2 Recommended Operating Conditions
5.2.1 Recommended Operating Conditions for CVDD = 1.2 V (108 MHz)
MIN
NOM
MAX
UNIT
Device supply voltage
1.14
1.2
1.26
V
RCVDD
RTC module supply voltage, core
1.14
1.2
1.26
V
RDVDD
RTC module supply voltage, I/O (RTCINX1 and RTCINX2)
1.14
1.2
1.26
V
DVDD
Device supply voltage, I/O (except SDA and SCL)†
2.7
3.3
3.6
V
Core
CVDD
Peripherals
Grounds
VSS
ADVANCE INFORMATION
VIH
VIL
Supply voltage, GND, I/O, and core
High-level input voltage, I/O
Low-level input voltage, I/O
SDA & SCL: VDD related input
levels†
All other inputs
(including hysteresis inputs)
−0.5
0.3 * DVDD
All other inputs
(including hysteresis inputs)
−0.3
0.8
IOH
High-level output current
All outputs
Operating case temperature
†
66
V
SDA &SCL: VDD related input
levels†
Inputs with hysteresis only
TC
DVDD(max) +0.5
DVDD + 0.3
Hysteresis level
Low-level output current
0.7*DVDD
V
2.0
Vhys
IOL
0
V
0.1*DVDD
V
−4
SDA and SCL†
3
All other outputs
4
−40
85
mA
mA
_C
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
Due to the fact that different voltage devices can be connected to the I2C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and
depends on the associated VDD.
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.2.2 Recommended Operating Conditions for CVDD = 1.35 V (144 MHz)
MIN
NOM
MAX
UNIT
Device supply voltage
1.28
1.35
1.42
V
RCVDD
RTC module supply voltage, core
1.28
1.35
1.42
V
RDVDD
RTC module supply voltage, I/O (RTCINX1 and RTCINX2)
1.28
1.35
1.42
V
DVDD
Device supply voltage, I/O (except SDA and SCL)†
2.7
3.3
3.6
V
Core
CVDD
Peripherals
Grounds
Supply voltage, GND, I/O, and core
VIH
High-level input voltage, I/O
VIL
Low-level input voltage, I/O
SDA & SCL: VDD related input
levels†
All other inputs
(including hysteresis inputs)
−0.5
0.3 * DVDD
All other inputs
(including hysteresis inputs)
−0.3
0.8
IOH
High-level output current
All outputs
†
Operating case temperature
V
SDA &SCL: VDD related input
levels†
Inputs with hysteresis only
TC
DVDD(max) +0.5
DVDD + 0.3
Hysteresis level
Low-level output current
0.7*DVDD
V
2.0
Vhys
IOL
0
V
0.1*DVDD
V
−4
SDA and SCL†
3
All other outputs
4
−40
85
mA
mA
_C
I2C
The
pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
Due to the fact that different voltage devices can be connected to the I2C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and
depends on the associated VDD.
April 2004 − Revised January 2005
SPRS245C
67
ADVANCE INFORMATION
VSS
Electrical Specifications
5.2.3 Recommended Operating Conditions for CVDD = 1.6 V (200 MHz)
MIN
NOM
MAX
UNIT
Device supply voltage
1.55
1.6
1.65
V
RCVDD
RTC module supply voltage, core
1.55
1.6
1.65
V
RDVDD
RTC module supply voltage, I/O (RTCINX1 and RTCINX2)
1.55
1.6
1.65
V
DVDD
Device supply voltage, I/O (except SDA and SCL)†
2.7
3.3
3.6
V
Core
CVDD
Peripherals
Grounds
VSS
ADVANCE INFORMATION
VIH
VIL
Supply voltage, GND, I/O, and core
High-level input voltage, I/O
Low-level input voltage, I/O
SDA & SCL: VDD related input
levels†
All other inputs
(including hysteresis inputs)
−0.5
0.3 * DVDD
All other inputs
(including hysteresis inputs)
−0.3
0.8
IOH
High-level output current
All outputs
Operating case temperature
†
68
V
SDA & SCL: VDD related input
levels†
Inputs with hysteresis only
TC
DVDD(max) +0.5
DVDD + 0.3
Hysteresis level
Low-level output current
0.7*DVDD
V
2.0
Vhys
IOL
0
V
0.1*DVDD
V
−4
SDA and SCL†
3
All other outputs
4
−40
85
mA
mA
_C
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
Due to the fact that different voltage devices can be connected to the I2C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and
depends on the associated VDD.
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.3 Electrical Characteristics
5.3.1
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CVDD = 1.2 V (108 MHz) (Unless Otherwise Noted)
VOH
High-level output voltage
VOL
Low-level output voltage
IIZ
II
Input current for outputs in
high-impedance
Input current
TEST CONDITIONS
MIN
TYP
MAX
All outputs
DVDD = 2.7 V−3.6 V,
IOH = MAX
0.75 * DVDD
SDA & SCL†
At 3 mA sink current
0
All other outputs
IOL = MAX
Output-only or
I/O pins with bus
keepers (enabled)
DVDD = MAX,
VO = VSS to DVDD
−300
All other output-only
or I/O pins
DVDD = MAX
VO = VSS to DVDD
−5
5
Input pins with
internal pulldown
(enabled)
DVDD = MAX,
VI = VSS to DVDD
30
300
Input pins with
internal pullup
(enabled)
DVDD = MAX,
VI = VSS to DVDD
−300
−30
X2/CLKIN
DVDD = MAX,
VI = VSS to DVDD
−50
50
All other input-only
pins
DVDD = MAX,
VI = VSS to DVDD
−5
5
UNIT
V
0.4
0.4
V
300
µA
µA
IDDC
CVDD supply current, CPU + internal memory access‡
CVDD = 1.2 V
CPU clock = 108 MHz
TC = 25_C
0.45
mA/
MHz
IDDP
DVDD supply current, pins active§
DVDD = 3.3 V
CPU clock = 108 MHz
TC = 25_C
5.5
mA
IDDC
CVDD supply current, standby¶
Oscillator disabled.
All domains in
low-power state
CVDD = 1.2 V
TC = 25_C
(Nominal Process)
100
µA
IDDP
DVDD supply current, standby
Oscillator disabled.
All domains in
low-power state.
DVDD = 3.3 V
No I/O activity
TC = 25_C
10
µA
Ci
Input capacitance
3
pF
Co
Output capacitance
3
pF
†
I2C
The
pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active.
All other domains are idled.
§ One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load.
¶ In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current
will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
‡
April 2004 − Revised January 2005
SPRS245C
69
ADVANCE INFORMATION
PARAMETER
Electrical Specifications
5.3.2 Electrical Characteristics Over Recommended Operating Case Temperature
Range for CVDD = 1.35 V (144 MHz) (Unless Otherwise Noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
ADVANCE INFORMATION
IIZ
II
Input current for outputs in
high-impedance
Input current
TEST CONDITIONS
MIN
TYP
MAX
All outputs
DVDD = 2.7 V−3.6 V,
IOH = MAX
0.75 * DVDD
SDA & SCL†
At 3 mA sink current
0
All other outputs
IOL = MAX
Output-only or
I/O pins with bus
keepers (enabled)
DVDD = MAX,
VO = VSS to DVDD
−300
All other output-only
or I/O pins
DVDD = MAX
VO = VSS to DVDD
−5
5
Input pins with
internal pulldown
(enabled)
DVDD = MAX,
VI = VSS to DVDD
30
300
Input pins with
internal pullup
(enabled)
DVDD = MAX,
VI = VSS to DVDD
−300
−30
X2/CLKIN
DVDD = MAX,
VI = VSS to DVDD
−50
50
All other input-only
pins
DVDD = MAX,
VI = VSS to DVDD
−5
5
UNIT
V
0.4
0.4
V
300
µA
µA
IDDC
CVDD supply current, CPU + internal memory access‡
CVDD = 1.35 V
CPU clock = 144 MHz
TC = 25_C
0.51
mA/
MHz
IDDP
DVDD supply current, pins active§
DVDD = 3.3 V
CPU clock = 144 MHz
TC = 25_C
5.5
mA
IDDC
CVDD supply current, standby¶
Oscillator disabled.
All domains in
low-power state
CVDD = 1.35 V
TC = 25_C
(Nominal Process)
125
µA
IDDP
DVDD supply current, standby
Oscillator disabled.
All domains in
low-power state.
DVDD = 3.3 V
No I/O activity
TC = 25_C
10
µA
Ci
Input capacitance
3
pF
Co
Output capacitance
3
pF
†
I2C
The
pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active.
All other domains are idled.
§ One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load.
¶ In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current
will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
‡
70
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CVDD = 1.6 V (200 MHz) (Unless Otherwise Noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
IIZ
II
Input current for outputs in
high-impedance
Input current
TEST CONDITIONS
MIN
TYP
MAX
All outputs
DVDD = 2.7 V−3.6 V,
IOH = MAX
0.75 * DVDD
SDA & SCL†
At 3 mA sink current
0
All other outputs
IOL = MAX
Output-only or
I/O pins with bus
keepers (enabled)
DVDD = MAX,
VO = VSS to DVDD
−300
All other output-only
or I/O pins
DVDD = MAX
VO = VSS to DVDD
−5
5
Input pins with
internal pulldown
(enabled)
DVDD = MAX,
VI = VSS to DVDD
30
300
Input pins with
internal pullup
(enabled)
DVDD = MAX,
VI = VSS to DVDD
−300
−30
X2/CLKIN
DVDD = MAX,
VI = VSS to DVDD
−50
50
All other input-only
pins
DVDD = MAX,
VI = VSS to DVDD
−5
5
UNIT
V
0.4
0.4
V
300
µA
µA
IDDC
CVDD supply current, CPU + internal memory access‡
CVDD = 1.6 V
CPU clock = 200 MHz
TC = 25_C
0.60
mA/
MHz
IDDP
DVDD supply current, pins active§
DVDD = 3.3 V
CPU clock = 200 MHz
TC = 25_C
5.5
mA
IDDC
CVDD supply current, standby¶
Oscillator disabled.
All domains in
low-power state
CVDD = 1.6 V
TC = 25_C
(Nominal Process)
150
µA
IDDP
DVDD supply current, standby
Oscillator disabled.
All domains in
low-power state.
DVDD = 3.3 V
No I/O activity
TC = 25_C
10
µA
Ci
Input capacitance
3
pF
Co
Output capacitance
3
pF
†
I2C
The
pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active.
All other domains are idled.
§ One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load.
¶ In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current
will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
‡
April 2004 − Revised January 2005
SPRS245C
71
ADVANCE INFORMATION
5.3.3
Electrical Specifications
Tester Pin Electronics
42 Ω
Data Manual Timing Reference Point
Output
Under
Test
3.5 nH
Transmission Line
Z0 = 50 Ω
(see note)
4.0 pF
Device Pin
(see note)
1.85 pF
ADVANCE INFORMATION
NOTE: The data manual provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data manual timings.
Input requirements in this data manual are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device
pin.
Figure 5−1. 3.3-V Test Load Circuit
5.4
ESD Performance
ESD stress levels were performed in compliance with the following JEDEC standards with the results indicated
below:
•
Charged Device Model (CDM), based on JEDEC Specification JESD22-C101, passed at ±500 V
•
Human Body Model (HBM), based on JEDEC Specification JESD22-A114, passed at ±1500 V
NOTE:
According to industry research publications, ESD-CDM testing results show better correlation
to manufacturing line and field failure rates than ESD-HBM testing. 500-V CDM is commonly
considered as a safe passing level.
5.5
Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
72
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
dis
disable time
Z
High-impedance
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
X
Unknown, changing, or don’t care level
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.6
Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four
or multiplied by one of several values to generate the internal machine cycle.
5.6.1 Internal System Oscillator With External Crystal
The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series
resistance (ESR) specified in Table 5−1. The connection of the required circuit is shown in Figure 5−2. Under
some conditions, all the components shown are not required. The capacitors, C1 and C2, should be chosen
such that the equation below is satisfied. CL in the equation is the load specified for the crystal that is also
specified in Table 5−1.
CL +
C 1C 2
(C 1 ) C 2)
X2/CLKIN
X1
RS
Crystal
C1
C2
Figure 5−2. Internal System Oscillator With External Crystal
Table 5−1. Recommended Crystal Parameters
FREQUENCY RANGE (MHz)
MAX ESR (Ω)
MAX CSHUNT (pF)
RS (Ω)
20
TYP CLOAD (pF)
10
20−15
15−12
7
0
30
16
7
0
12−10
40
16
7
100
10−8
60
18
7
470
8−6
80
18
7
1.5k
6−5
80
18
7
2.2k
Although the recommended ESR presented in Table 5−1 is maximum, theoretically a crystal with a lower
maximum ESR might seem to meet the requirement. It is recommended that crystals which meet the
maximum ESR specification in Table 5−1 are used.
April 2004 − Revised January 2005
SPRS245C
73
ADVANCE INFORMATION
The internal oscillator is always enabled following a device reset. The oscillator requires an external crystal
connected across the X1 and X2/CLKIN pins. If the internal oscillator is not used, an external clock source
must be applied to the X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal oscillator
can be used as a clock source to the PLLs, the crystal oscillation frequency can be multiplied to generate the
CPU clock, if desired.
Electrical Specifications
5.6.2 Layout Considerations
ADVANCE INFORMATION
Since parasitic capacitance, inductance and resistance can be significant in any circuit, good PC board layout
practices should always be observed when planning trace routing to the discrete components used in the
oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close
to the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible
after routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should
be run between these two signal lines. This also helps to minimize stray capacitance between these two
signals.
74
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.6.3 Clock Generation in Bypass Mode (DPLL Disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of one, two, or
four to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock
mode register. The contents of this field only affect clock generation while the device is in bypass mode. In
this mode, the digital phase-locked loop (DPLL) clock synthesis is disabled.
Table 5−2 and Table 5−3 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5−3).
Table 5−2. CLKIN Timing Requirements
†
CVDD = 1.6 V
UNIT
MIN
MAX
MIN
MAX
20
400†
20
400†
ns
C1
tc(CI)
Cycle time, X2/CLKIN
C2
tf(CI)
Fall time, X2/CLKIN
4
4
ns
C3
tr(CI)
Rise time, X2/CLKIN
4
4
ns
C10
tw(CIL)
Pulse duration, CLKIN low
6
6
ns
C11
tw(CIH)
Pulse duration, CLKIN high
6
6
ns
This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. If an external crystal is used, the X2/CLKIN cycle
time is limited by the crystal frequency range listed in Table 5−1.
Table 5−3. CLKOUT Switching Characteristics
NO.
CVDD = 1.2 V
CVDD = 1.35 V
PARAMETER
MIN
CVDD = 1.6 V
TYP
MAX
D*tc(CI)§
1600†
MIN
MAX
D*tc(CI)§
1600†
ns
25
ns
C4
tc(CO)
Cycle time, CLKOUT
20‡
C5
td(CI-CO)
Delay time, X2/CLKIN high to CLKOUT
high/low
5
C6
tf(CO)
Fall time, CLKOUT
C7
tr(CO)
Rise time, CLKOUT
C8
tw(COL)
Pulse duration, CLKOUT low
H−1
H+1
H−1
H+1
ns
C9
tw(COH)
Pulse duration, CLKOUT high
H−1
H+1
H−1
H+1
ns
15
25
20‡
UNIT
TYP
5
15
1
1
1
ns
1
ns
This device utilizes a fully static design and therefore can operate with tc(CO) approaching ∞. If an external crystal is used, the X2/CLKIN cycle
time is limited by the crystal frequency range listed in Table 5−1.
‡ It is recommended that the DPLL synthesised clocking option be used to obtain maximum operating frequency.
§ D = 1/(PLL Bypass Divider)
†
C2
C1
C10
C11
C3
X2/CLKIN
C4
C9
C7
CLKOUT
C5
C6
C8
NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL bypass divide factor chosen for the CLKMD register. The waveform
relationship shown in Figure 5−3 is intended to illustrate the timing parameters based on CLKOUT = 1/2(CLKIN) configuration.
Figure 5−3. Bypass Mode Clock Timings
April 2004 − Revised January 2005
SPRS245C
75
ADVANCE INFORMATION
CVDD = 1.2 V
CVDD = 1.35 V
NO.
Electrical Specifications
5.6.4 Clock Generation in Lock Mode (DPLL Synthesis Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a synthesis factor of
N to generate the internal CPU clock cycle. The synthesis factor is determined by:
N= M
DL
where: M = the multiply factor set in the PLL_MULT field of the clock mode register
DL = the divide factor set in the PLL_DIV field of the clock mode register
Valid values for M are (multiply by) 2 to 31. Valid values for DL are (divide by) 1, 2, 3, and 4.
For detailed information on clock generation configuration, see the TMS320C55x DSP Peripherals Overview
Reference Guide (literature number SPRU317).
ADVANCE INFORMATION
Table 5−4 and Table 5−5 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5−4).
Table 5−4. Multiply-By-N Clock Option Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
†
C1
tc(CI)
Cycle time, X2/CLKIN
C2
tf(CI)
Fall time, X2/CLKIN
DPLL synthesis enabled
CVDD = 1.6 V
UNIT
MIN
MAX
MIN
MAX
20†
400
20†
400
ns
4
ns
4
ns
4
C3
tr(CI)
Rise time, X2/CLKIN
C10
tw(CIL)
Pulse duration, CLKIN low
6
4
6
ns
C11
tw(CIH)
Pulse duration, CLKIN high
6
6
ns
The clock frequency synthesis factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within
the specified range (tc(CO)). If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 5−1.
Table 5−5. Multiply-By-N Clock Option Switching Characteristics
NO.
‡
PARAMETER
CVDD = 1.2 V
MIN
TYP
CVDD = 1.35 V
MAX
MIN
1600
6.95
TYP
CVDD = 1.6 V
MAX
MIN
1600
5
TYP
MAX
UNIT
C4
tc(CO)
Cycle time,
CLKOUT
C6
tf(CO)
Fall time,
CLKOUT
1
1
1
ns
C7
tr(CO)
Rise time,
CLKOUT
1
1
1
ns
C8
tw(COL)
Pulse duration,
CLKOUT low
H−1
H+1
H−1
H+1
H−1
H+1
ns
C9
tw(COH)
Pulse duration,
CLKOUT high
H−1
H+1
H−1
H+1
H−1
H+1
ns
C12
td(CI–CO)
Delay time,
X2/CLKIN high/
low to CLKOUT
high/low
5
25
5
25
5
25
ns
9.26
tc(CI)*N‡
15
tc(CI)*N‡
15
tc(CI)*N‡
15
1600
ns
N = Clock frequency synthesis factor
76
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
C1
C2
C3
C11
C10
X2/CLKIN
C9
C8
C12
C6
C4
CLKOUT
C7
Bypass Mode
NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL multiply and divide factor chosen for the CLKMD register. The waveform
relationship shown in Figure 5−3 is intended to illustrate the timing parameters based on CLKOUT = 1xCLKIN configuration.
Figure 5−4. External Multiply-by-N Clock Timings
The real-time clock module includes an oscillator circuit. The oscillator requires an external 32.768-kHz crystal
connected across the RTCINX1 and RTCINX2 pins. The connection of the required circuit, consisting of the
crystal and two load capacitors, is shown in Figure 5−5. The load capacitors, C1 and C2, should be chosen
such that the equation below is satisfied. CL in the equation is the load specified for the crystal.
CL +
C 1C 2
(C 1 ) C 2)
RTCINX1
RTCINX2
Crystal
32.768 kHz
C1
C2
Figure 5−5. Real-Time Clock Oscillator With External Crystal
NOTE: The RTC can be idled by not supplying its 32-kHz oscillator signal. In order to keep
RTC power dissipation to a minimum when the RTC module is not used, it is recommended
that the RTC module be powered up, the RTC input pin (RTCINX1) be pulled low, and the RTC
output pin (RTCINX2) be left floating.
Table 5−6. Recommended RTC Crystal Parameters
PARAMETER
fo
†
MIN
Frequency of oscillation†
resistance†
ESR
Series
CL
Load capacitance
DL
Crystal drive level
NOM
MAX
32.768
30
UNIT
kHz
60
12.5
kΩ
pF
1
µW
ESR must be 200 kΩ or greater at frequencies other than 32.768kHz. Otherwise, oscillations at overtone frequencies may occur.
April 2004 − Revised January 2005
SPRS245C
77
ADVANCE INFORMATION
5.6.5 Real-Time Clock Oscillator With External Crystal
Electrical Specifications
5.7
Memory Interface Timings
5.7.1 Asynchronous Memory Timings
Table 5−7 and Table 5−8 assume testing over recommended operating conditions (see Figure 5−6 and
Figure 5−7).
Table 5−7. Asynchronous Memory Cycle Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
ADVANCE INFORMATION
†
MAX
CVDD = 1.6 V
MIN
UNIT
MAX
M1
tsu(DV-COH)
Setup time, read data valid before CLKOUT high†
6
5
ns
M2
th(COH-DV)
Hold time, read data valid after CLKOUT high
0
0
ns
10
7
ns
0
0
ns
high†
M3
tsu(ARDY-COH)
Setup time, ARDY valid before CLKOUT
M4
th(COH-ARDY)
Hold time, ARDY valid after CLKOUT high
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Table 5−8. Asynchronous Memory Cycle Switching Characteristics
NO.
PARAMETER
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
UNIT
MIN
MAX
MIN
MAX
M5
td(COH-CEV)
Delay time, CLKOUT high to CEx valid
−2
4
−2
4
ns
M6
td(COH-CEIV)
Delay time, CLKOUT high to CEx invalid
−2
4
−2
4
ns
M7
td(COH-BEV)
Delay time, CLKOUT high to BEx valid
4
ns
M8
td(COH-BEIV)
Delay time, CLKOUT high to BEx invalid
4
−2
−2
M9
td(COH-AV)
Delay time, CLKOUT high to address valid
M10
td(COH-AIV)
Delay time, CLKOUT high to address invalid
−2
M11
td(COH-AOEV)
Delay time, CLKOUT high to AOE valid
−2
4
−2
4
ns
M12
td(COH-AOEIV)
Delay time, CLKOUT high to AOE invalid
−2
4
−2
4
ns
M13
td(COH-AREV)
Delay time, CLKOUT high to ARE valid
−2
4
−2
4
ns
M14
td(COH-AREIV)
Delay time, CLKOUT high to ARE invalid
−2
4
−2
4
ns
M15
td(COH-DV)
Delay time, CLKOUT high to data valid
4
ns
M16
td(COH-DIV)
Delay time, CLKOUT high to data invalid
−2
M17
td(COH-AWEV)
Delay time, CLKOUT high to AWE valid
−2
4
−2
4
ns
M18
td(COH-AWEIV)
Delay time, CLKOUT high to AWE invalid
−2
4
−2
4
ns
78
SPRS245C
4
ns
4
−2
4
ns
ns
−2
ns
April 2004 − Revised January 2005
Electrical Specifications
Setup = 2
Strobe = 5
Not Ready = 2
Extended
Hold = 2
Hold
=1
CLKOUT†
M5
M6
M7
M8
M9
M10
CEx‡
BEx
A[20:0]§
M1
M2
D[15:0]
M11
M12
AOE
M13
ADVANCE INFORMATION
M14
ARE
AWE
M4
M4
M3
M3
ARDY
†
CLKOUT is equal to CPU clock
CEx becomes active depending on the memory address space being accessed
§ A[13:0] for LQFP
‡
Figure 5−6. Asynchronous Memory Read Timings
April 2004 − Revised January 2005
SPRS245C
79
Electrical Specifications
Setup = 2
Strobe = 5
Not Ready = 2
Hold = 1
Extended
Hold = 2
CLKOUT†
M5
M6
M7
M8
M9
M10
CEx‡
BEx
A[20:0]§
M15
M16
D[15:0]
ADVANCE INFORMATION
AOE
ARE
M17
M18
AWE
M4
M3
M4
M3
ARDY
†
CLKOUT is equal to CPU clock
CEx becomes active depending on the memory address space being accessed
§ A[13:0] for LQFP
‡
Figure 5−7. Asynchronous Memory Write Timings
80
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.7.2 Synchronous DRAM (SDRAM) Timings
Table 5−9 and Table 5−10 assume testing over recommended operating conditions (see Figure 5−8 through
Figure 5−14).
Table 5−9. Synchronous DRAM Cycle Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
MAX
CVDD = 1.6 V
MIN
UNIT
MAX
M19
tsu(DV-CLKMEMH)
Setup time, read data valid before CLKMEM high
3
3
ns
M20
th(CLKMEMH-DV)
Hold time, read data valid after CLKMEM high
2
2
ns
9.26†
7.52‡
ns
M21
tc(CLKMEM)
Cycle time, CLKMEM
†
Table 5−10. Synchronous DRAM Cycle Switching Characteristics
NO.
PARAMETER
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
UNIT
MIN
MAX
MIN
MAX
M22
td(CLKMEMH-CEL)
Delay time, CLKMEM high to CEx low
1.2
7
1.2
5
ns
M23
td(CLKMEMH-CEH)
Delay time, CLKMEM high to CEx high
1.2
7
1.2
5
ns
M24
td(CLKMEMH-BEV)
Delay time, CLKMEM high to BEx valid
1.2
7
1.2
5
ns
M25
td(CLKMEMH-BEIV)
Delay time, CLKMEM high to BEx invalid
1.2
7
1.2
5
ns
M26
td(CLKMEMH-AV)
Delay time, CLKMEM high to address valid
1.2
7
1.2
5
ns
M27
td(CLKMEMH-AIV)
Delay time, CLKMEM high to address invalid
1.2
7
1.2
5
ns
M28
td(CLKMEMH-SDCASL)
Delay time, CLKMEM high to SDCAS low
1.2
7
1.2
5
ns
M29
td(CLKMEMH-SDCASH)
Delay time, CLKMEM high to SDCAS high
1.2
7
1.2
5
ns
M30
td(CLKMEMH-DV)
Delay time, CLKMEM high to data valid
1.2
7
1.2
5
ns
M31
td(CLKMEMH-DIV)
Delay time, CLKMEM high to data invalid
1.2
7
1.2
5
ns
M32
td(CLKMEMH-SDWEL)
Delay time, CLKMEM high to SDWE low
1.2
7
1.2
5
ns
M33
td(CLKMEMH-SDWEH)
Delay time, CLKMEM high to SDWE high
1.2
7
1.2
5
ns
M34
td(CLKMEMH-SDA10V)
Delay time, CLKMEM high to SDA10 valid
1.2
7
1.2
5
ns
M35
td(CLKMEMH-SDA10IV)
Delay time, CLKMEM high to SDA10 invalid
1.2
7
1.2
5
ns
M36
td(CLKMEMH-SDRASL)
Delay time, CLKMEM high to SDRAS low
1.2
7
1.2
5
ns
M37
td(CLKMEMH-SDRASH)
Delay time, CLKMEM high to SDRAS high
1.2
7
1.2
5
ns
M38
td(CLKMEMH–CKEL)
Delay time, CLKMEM high to CKE low
1.2
7
1.2
5
ns
M39
td(CLKMEMH–CKEH)
Delay time, CLKMEM high to CKE high
1.2
7
1.2
5
ns
April 2004 − Revised January 2005
SPRS245C
81
ADVANCE INFORMATION
Maximum SDRAM operating frequency = 108 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board
design and the memory chip timing requirement.
‡ Maximum SDRAM operating frequency = 133 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board
design and the memory chip timing requirement.
Electrical Specifications
READ
READ
READ
M21
CLKMEM
M22
M23
M27
CEx†
M24
BEx‡
M26
EMIF.A[13:0]
CA1
CA2
CA3
M19
M20
ADVANCE INFORMATION
D[15:0]
D1
M34
M35
M28
M29
D2
D3
SDA10
SDRAS
SDCAS
SDWE
†
‡
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−8. Three SDRAM Read Commands
82
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
WRITE
WRITE
WRITE
CLKMEM
M22
M23
CEx†
M25
M24
BEx‡
BE1
BE2
BE3
CA2
CA3
M27
M26
EMIF.A[13:0]
CA1
M31
D1
D[15:0]
D2
D3
M34
M35
M28
M29
M32
M33
SDA10
SDRAS
SDCAS
SDWE
†
‡
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−9. Three SDRAM WRT Commands
April 2004 − Revised January 2005
SPRS245C
83
ADVANCE INFORMATION
M30
Electrical Specifications
ACTV
CLKMEM
M22
M23
CEx†
BEx‡
M26
Bank Activate/Row Address
EMIF.A[13:0]
D[15:0]
ADVANCE INFORMATION
M34
SDA10
M36
M37
SDRAS
SDCAS
SDWE
†
‡
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−10. SDRAM ACTV Command
84
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
DCAB
CLKMEM
M22
M23
CEx†
BEx‡
EMIF.A[13:0]
M34
M35
M36
M37
M32
M33
SDA10
SDRAS
SDCAS
SDWE
†
‡
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−11. SDRAM DCAB Command
April 2004 − Revised January 2005
SPRS245C
85
ADVANCE INFORMATION
D[15:0]
Electrical Specifications
REFR
CLKMEM
M22
M23
CEx†
BEx‡
EMIF.A[13:0]
ADVANCE INFORMATION
D[15:0]
SDA10
M36
M37
M28
M29
SDRAS
SDCAS
SDWE
†
‡
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals
remain active until the next access that is not an SDRAM read occurs.
Figure 5−12. SDRAM REFR Command
86
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
MRS
CLKMEM
M22
M23
CEx†
BEx‡
M26
M27
D[15:0]
SDA10
M36
M37
SDRAS
M28
M29
SDCAS
M32
M33
SDWE
†
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
§ Write burst length = 1
Read latency = 3
Burst type = 0 (serial)
Burst length = 1
‡
Figure 5−13. SDRAM MRS Command
April 2004 − Revised January 2005
SPRS245C
87
ADVANCE INFORMATION
MRS Value 0x30§
EMIF.A[13:0]
Electrical Specifications
Enter Self-Refresh
Exit Self-Refresh
CLKMEM
M38
M39
CKE
(XF or GPIO4)
M22
M23
CEx
M36
SDRAS
M28
ADVANCE INFORMATION
SDCAS
SDWE
SDA10
Figure 5−14. SDRAM Self-Refresh Command
88
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.8
Reset Timings
5.8.1 Power-Up Reset (On-Chip Oscillator Active)
Table 5−11 assumes testing over recommended operating conditions (see Figure 5−15).
Table 5−11. Power-Up Reset (On-Chip Oscillator Active) Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
R1
Hold time, RESET low after oscillator stable†
th(SUPSTBL-RSTL)
MAX
3P‡
CVDD = 1.6 V
MIN
UNIT
MAX
3P‡
ns
†
Oscillator stable time depends on the crystal characteristic (i.e., frequency, ESR, etc.) which varies from one crystal manufacturer to another.
Based on the crystal characteristics, the oscillator stable time can be in the range of a few to 10s of ms. A reset circuit with 100 ms or more delay
time will ensure the oscillator stabilized before the RESET goes high.
‡ P = 1/(input clock frequency) in ns. For example, when input clock is 12 MHz, P = 83.33 ns.
ADVANCE INFORMATION
CLKOUT
CVDD
DVDD
R1
RESET
Figure 5−15. Power-Up Reset (On-Chip Oscillator Active) Timings
April 2004 − Revised January 2005
SPRS245C
89
Electrical Specifications
5.8.2 Power-Up Reset (On-Chip Oscillator Inactive)
Table 5−12 and Table 5−13 assume testing over recommended operating conditions (see Figure 5−16).
Table 5−12. Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
R2
†
th(CLKOUTV-RSTL)
Hold time, CLKOUT valid to RESET low
MAX
3P†
CVDD = 1.6 V
MIN
UNIT
MAX
3P†
ns
P = 1/(input clock frequency) in ns. For example, when input clock is 12 MHz, P = 83.33 ns.
Table 5−13. Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics
NO.
CVDD = 1.2 V
CVDD = 1.35 V
PARAMETER
MIN
ADVANCE INFORMATION
R3
td(CLKINV-CLKOUTV)
Delay time, CLKIN valid to CLKOUT valid
MAX
30
CVDD = 1.6 V
MIN
UNIT
MAX
30
ns
X2/CLKIN
R3
CLKOUT
CVDD
DVDD
R2
RESET
Figure 5−16. Power-Up Reset (On-Chip Oscillator Inactive) Timings
90
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.8.3 Warm Reset
Table 5−14 and Table 5−15 assume testing over recommended operating conditions (see Figure 5−17).
Table 5−14. Reset Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
R4
†
tw(RSL)
CVDD = 1.6 V
MAX
MIN
3P†
Pulse width, reset low
UNIT
MAX
3P†
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−15. Reset Switching Characteristics†
PARAMETER
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
MIN
MIN
MAX
UNIT
MAX
R5
td(RSTH-BKV)
Delay time, reset high to BK group valid‡
38P + 15
38P + 15
ns
R6
td(RSTH-HIGHV)
Delay time, reset high to High group valid§
38P + 15
38P + 15
ns
1P + 15
1P + 15
ns
38P + 15
38P + 15
ns
invalid¶
R7
td(RSTL-ZIV)
Delay time, reset low to Z group
R8
td(RSTH-ZV)
Delay time, reset high to Z group valid¶
†
P = 1/CPU clock frequency in ns. For example, when CPU is running at 200 MHz, P = 5 ns.
BK group: Pins with bus keepers, holds previous state during reset. Following low-to-high transition of RESET, these pins go to their post-reset
logic state.
BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, DX1, and DX2
§ High group: Following low-to-high transition of RESET, these pins go to logic-high state.
High group pins: C1[HPI.HINT], XF
¶ Z group: Bidirectional pins which become input or output pins. Following low-to-high transition of RESET, these pins go to high-impedance state.
Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DX0, FSX0, FSX2, CLKX2, FSR2, DR2, CLKR2,
FSX1, CLKX1, FSR1, DR1, CLKR1, A[20:16]
‡
RESET
R5
BK Group†
R6
High Group‡
R7
Z
R8
Group§
†
BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, DX1, and DX2
High group pins: C1[HPI.HINT], XF
§ Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DX0, FSX0, FSX2, CLKX2, FSR2, DR2, CLKR2,
FSX1, CLKX1, FSR1, DR1, CLKR1, A[20:16]
‡
Figure 5−17. Reset Timings
April 2004 − Revised January 2005
SPRS245C
91
ADVANCE INFORMATION
NO.
Electrical Specifications
5.9
External Interrupt Timings
Table 5−16 assumes testing over recommended operating conditions (see Figure 5−18).
Table 5−16. External Interrupt Timing Requirements†
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
†
CVDD = 1.6 V
MAX
MIN
UNIT
MAX
I1
tw(INTL)A
Pulse width, interrupt low, CPU active
3P
3P
ns
I2
tw(INTH)A
Pulse width, interrupt high, CPU active
2P
2P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
I1
ADVANCE INFORMATION
INTn
I2
Figure 5−18. External Interrupt Timings
5.10 Wake-Up From IDLE
Table 5−17 assumes testing over recommended operating conditions (see Figure 5−19).
Table 5−17. Wake-Up From IDLE Switching Characteristics†
NO.
PARAMETER
CVDD = 1.2 V
CVDD = 1.35 V
MIN
ID1
td(WKPEVTL-CLKGEN)
Delay time, wake-up event low to clock
generation enable
(CPU and clock domain idle)
ID2
th(CLKGEN-WKPEVTL)
Hold time, clock generation enable to
wake-up event low
(CPU and clock domain in idle)
ID3
tw(WKPEVTL)
Pulse width, wake-up event low
(for CPU idle only)
TYP
CVDD = 1.6 V
MAX
MIN
1.25‡
TYP
1.25‡
UNIT
MAX
ms
3P§
3P§
ns
3P
3P
ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Estimated data based on 12-MHz crystal used with on-chip oscillator at 25°C. This number will vary based on the actual crystal characteristics
operating condition and the PC board layout and the parasitics.
§ Following the clock generation domain idle, the INTx becomes level-sensitive and stays that way until the low-to-high transition of INTx following
the CPU wake-up. Holding the INTx low longer than minimum requirement will send more than one interrupt to the CPU. The number of interrupts
sent to the CPU depends on the INTx-low time following the CPU wake-up from IDLE.
‡
ID1
X1
ID2
ID3
RESET,
INTx
Figure 5−19. Wake-Up From IDLE Timings
92
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.11 XF Timings
Table 5−18 assumes testing over recommended operating conditions (see Figure 5−20).
Table 5−18. XF Switching Characteristics
NO.
X1
CVDD = 1.2 V
CVDD = 1.35 V
PARAMETER
td(XF)
CVDD = 1.6 V
UNIT
MIN
MAX
MIN
MAX
Delay time, CLKOUT high to XF high
−1
3
−1
3
Delay time, CLKOUT high to XF low
−1
3
−1
3
ns
CLKOUT†
X1
†
ADVANCE INFORMATION
XF
CLKOUT reflects the CPU clock.
Figure 5−20. XF Timings
April 2004 − Revised January 2005
SPRS245C
93
Electrical Specifications
5.12 General-Purpose Input/Output (GPIOx) Timings
Table 5−19 and Table 5−20 assume testing over recommended operating conditions (see Figure 5−21).
Table 5−19. GPIO Pins Configured as Inputs Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
G1
G2
tsu(GPIO-COH)
Setup time, IOx input valid before CLKOUT
high
Hold time, IOx input valid after CLKOUT
high
th(COH-GPIO)
CVDD = 1.6 V
MAX
MIN
GPIO
4
4
AGPIO†
8
8
EHPIGPIO ‡
8
8
GPIO
0
0
AGPIO†
0
0
EHPIGPIO ‡
0
0
UNIT
MAX
ns
ns
†
ADVANCE INFORMATION
AGPIO pins: A[15:0]
‡ EHPIGPIO pins: C13, C10, C7, C5, C4, and C0
Table 5−20. GPIO Pins Configured as Outputs Switching Characteristics
NO.
G3
†
‡
CVDD = 1.2 V
CVDD = 1.35 V
PARAMETER
td(COH-GPIO)
GPIO
Delay time, CLKOUT high to IOx output
AGPIO†
change
EHPIGPIO ‡
CVDD = 1.6 V
UNIT
MIN
MAX
MIN
MAX
0
6
0
6
0
11
0
11
0
13
0
13
ns
AGPIO pins: A[15:0]
EHPIGPIO pins: C13, C10, C7, C5, C4, and C0
CLKOUT†
G1
G2
IOx
Input Mode
G3
IOx
Output Mode
†
CLKOUT reflects the CPU clock.
Figure 5−21. General-Purpose Input/Output (IOx) Signal Timings
94
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.13 TIN/TOUT Timings (Timer0 Only)
Table 5−21 and Table 5−22 assume testing over recommended operating conditions (see Figure 5−22 and
Figure 5−23).
Table 5−21. TIN/TOUT Pins Configured as Inputs Timing Requirements†‡
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
†
‡
MAX
CVDD = 1.6 V
MIN
UNIT
MAX
T4
tw(TIN/TOUTL)
Pulse width, TIN/TOUT low
2P + 1
2P + 1
ns
T5
tw(TIN/TOUTH)
Pulse width, TIN/TOUT high
2P + 1
2P + 1
ns
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.
NO.
CVDD = 1.2 V
CVDD = 1.35 V
PARAMETER
CVDD = 1.6 V
UNIT
MIN
MAX
MIN
MAX
T1
td(COH-TIN/TOUTH)
Delay time, CLKOUT high to TIN/TOUT high
−1
3
−1
3
ns
T2
td(COH-TIN/TOUTL)
Delay time, CLKOUT high to TIN/TOUT low
−1
3
−1
3
ns
T3
tw(TIN/TOUT)
Pulse duration, TIN/TOUT (output)
P−1
P−1
ns
†
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
‡ Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.
§ For proper operation of the TIN/TOUT pin configured as an output, the timer period must be configured for at least 4 cycles.
T5
T4
TIN/TOUT
as Input
Figure 5−22. TIN/TOUT Timings When Configured as Inputs
CLKOUT
T1
T2
T3
TIN/TOUT
as Output
Figure 5−23. TIN/TOUT Timings When Configured as Outputs
April 2004 − Revised January 2005
SPRS245C
95
ADVANCE INFORMATION
Table 5−22. TIN/TOUT Pins Configured as Outputs Switching Characteristics†‡§
Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timings
5.14.1
McBSP0 Timings
Table 5−23 and Table 5−24 assume testing over recommended operating conditions (see Figure 5−24 and
Figure 5−25).
Table 5−23. McBSP0 Timing Requirements†
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
ADVANCE INFORMATION
MC1
tc(CKRX)
Cycle time, CLKR/X
CVDD = 1.6 V
MAX
MIN
UNIT
MAX
CLKR/X ext
2P‡
2P‡
ns
P–1‡
P–1‡
ns
MC2
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
MC3
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
6
6
ns
MC4
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
6
6
ns
MC5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
MC6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
MC7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
MC8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
MC9
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
MC10
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKR int
10
7
CLKR ext
2
2
CLKR int
−3
−3
CLKR ext
1
1
CLKR int
10
7
CLKR ext
2
2
CLKR int
−2
−2
CLKR ext
3
3
CLKX int
13
8
CLKX ext
3
2
CLKX int
−3
−3
CLKX ext
1
1
ns
ns
ns
ns
ns
ns
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡ P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
96
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
Table 5−24. McBSP0 Switching Characteristics†‡
CVDD = 1.2 V
CVDD = 1.35 V
PARAMETER
MIN
CVDD = 1.6 V
MAX
2P
MIN
UNIT
MAX
MC1
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
MC3
tr(CKRX)
Rise time, CLKR/X
CLKR/X int
1
2P
1
ns
ns
MC4
tf(CKRX)
Fall time, CLKR/X
CLKR/X int
1
1
ns
MC11
tw(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D−2§
MC12
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C−2§
MC13
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
MC14
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
tdis(CKXH-DXHZ)
Disable time, DX high-impedance from CLKX high
following last data bit
CLKX int
MC15
CLKX ext
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX int
5
4
CLKX ext
15
9
Delay time, CLKX high to DX
valid¶
CLKX int
4
2
CLKX ext
13
7
CLKX int
2P + 1
2P + 1
CLKX ext
2P + 4
2P + 3
MC16
td(CKXH-DXV)
Only applies to first bit transmitted
when in Data Delay 1 or 2
(XDATDLY = 01b or 10b) modes
Enable time, DX driven from CLKX
high¶
MC17
ten(CKXH-DX)
ten(FXH-DX)
ns
C+2§
C−1§
C+1§
ns
CLKR int
−2
1
−2
1
CLKR ext
4
13
4
8
CLKX int
−2
2
−2
2
CLKX ext
4
15
4
9
0
5
−5
1
10
18
3
11
ns
ns
ns
ns
CLKX int
−1
−3
CLKX ext
6
3
CLKX int
P−1
P−3
CLKX ext
P+6
P+3
DXENA = 0
ns
Only applies to first bit transmitted
when in Data Delay 1 or 2
(XDATDLY= 01b or 10b) modes
Only applies to first bit transmitted
when in Data Delay 0 (XDATDLY=
00b) mode.
Enable time, DX driven from FSX
high¶
MC19
D+1§
DXENA = 1
DXENA = 1
FSX int
DXENA = 0
td(FXH-DXV)
D−1§
DXENA = 0
Delay time, FSX high to DX valid¶
MC18
D+2§
ADVANCE INFORMATION
NO.
DXENA = 1
2
2
FSX ext
13
8
FSX int
2P + 1
2P + 1
FSX ext
2P + 10
2P + 10
FSX int
0
0
FSX ext
8
3
FSX int
P−3
P−3
FSX ext
P+8
P+4
ns
DXENA = 0
ns
Only applies to first bit transmitted
when in Data Delay 0 (XDATDLY=
00b) mode
DXENA = 1
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡ P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
§ T=CLKRX period = (1 + CLKGDV) * P
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA)
and data delay features of the McBSP.
April 2004 − Revised January 2005
SPRS245C
97
Electrical Specifications
5.14.2
McBSP1 and McBSP2 Timings
Table 5−25 and Table 5−26 assume testing over recommended operating conditions (see Figure 5−24 and
Figure 5−25).
Table 5−25. McBSP1 and McBSP2 Timing Requirements†
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
ADVANCE INFORMATION
MC1
tc(CKRX)
Cycle time, CLKR/X
2P‡
ns
P–1‡
ns
CLKR/X ext
MC3
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
MC4
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
MC6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
MC7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
MC8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
MC9
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
MC10
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
UNIT
MAX
P–1‡
Pulse duration, CLKR/X high or CLKR/X low
Setup time, external FSR high before CLKR low
MIN
2P‡
tw(CKRX)
tsu(FRH-CKRL)
MAX
CLKR/X ext
MC2
MC5
CVDD = 1.6 V
6
6
CLKR int
11
7
CLKR ext
3
3
CLKR int
−3
−3
CLKR ext
1
1
CLKR int
11
7
CLKR ext
3
3
CLKR int
−2
−2
CLKR ext
3
3
CLKX int
14
9
CLKX ext
4
3
CLKX int
−3
−3
CLKX ext
1
1
6
ns
6
ns
ns
ns
ns
ns
ns
ns
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡ P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
98
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
Table 5−26. McBSP1 and McBSP2 Switching Characteristics†‡
CVDD = 1.2 V
CVDD = 1.35 V
PARAMETER
MIN
CVDD = 1.6 V
MAX
MIN
2P
UNIT
MAX
MC1
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
MC3
tr(CKRX)
Rise time, CLKR/X
CLKR/X int
2
2
ns
MC4
tf(CKRX)
Fall time, CLKR/X
CLKR/X int
2
2
ns
2§
ns
ns
2§
MC11
tw(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D−
MC12
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C − 2§
MC13
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
MC14
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
MC15
tdis(CKXH-DXHZ)
2
−3
2
3
9
CLKX int
−3
2
−3
2
CLKX ext
4
15
4
9
Disable time, DX high-impedance from CLKX high
following last data bit
CLKX int
−3
3
−5
1
CLKX ext
10
19
3
12
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX int
5
3
CLKX ext
15
9
CLKX int
4
2
CLKX ext
15
9
CLKX int
2P + 1
2P + 1
CLKX ext
2P + 5
2P + 3
valid¶
DXENA = 0
DXENA = 1
−2
−4
CLKX ext
9
4
CLKX int
P−2
P−4
CLKX ext
P+9
P+4
ns
ns
ns
ns
Only applies to first bit transmitted
when in Data Delay 1 or 2
(XDATDLY=01b or 10b) modes
Only applies to first bit transmitted
when
in
Data
Delay
0
(XDATDLY=00b) mode.
Enable time, DX driven from FSX
high¶
ten(FXH-DX)
CLKX int
ns
DXENA = 0
DXENA = 1
FSX int
DXENA = 0
MC19
C + 2§
14
Delay time, FSX high to DX valid¶
td(FXH-DXV)
C − 2§
3
Enable time, DX driven from CLKX
high¶
MC18
D+
C + 2§
−3
td(CKXH-DXV)
ten(CKXH-DX)
D−
2§
CLKR ext
Only applies to first bit transmitted
when in Data Delay 1 or 2
(XDATDLY=01b or 10b) modes
MC17
D+
2§
ns
CLKR int
Delay time, CLKX high to DX
MC16
2P
ADVANCE INFORMATION
NO.
DXENA = 1
3
2
FSX ext
13
8
FSX int
2P + 1
2P + 1
FSX ext
2P + 12
2P + 7
FSX int
1
0
FSX ext
8
4
FSX int
P−1
P−3
FSX ext
P+8
P+5
ns
DXENA = 0
ns
Only applies to first bit transmitted
when
in
Data
Delay
0
(XDATDLY=00b) mode
DXENA = 1
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡ P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
§ T = CLKRX period = (1 + CLKGDV) * P
C = CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA)
and data delay features of the McBSP.
April 2004 − Revised January 2005
SPRS245C
99
Electrical Specifications
MC1
MC2, MC11
MC3
MC2, MC12
CLKR
MC13
MC4
MC13
FSR (Int)
MC5
MC6
FSR (Ext)
MC7
MC8
ADVANCE INFORMATION
DR
(RDATDLY=00b)
Bit (n−1)
(n−2)
MC7
DR
(RDATDLY=01b)
(n−3)
(n−4)
(n−2)
(n−3)
MC8
Bit (n−1)
MC7
MC8
DR
(RDATDLY=10b)
Bit (n−1)
(n−2)
Figure 5−24. McBSP Receive Timings
MC1
MC2, MC11
MC3
MC4
MC2, MC12
CLKX
MC14
MC14
FSX (Int)
MC9
MC10
FSX (Ext)
MC18
MC16
MC19
DX
(XDATDLY=00b)
Bit 0
Bit (n−1)
(n−2)
DX
(XDATDLY=10b)
(n−4)
MC16
MC17
DX
(XDATDLY=01b)
(n−3)
Bit 0
Bit (n−1)
MC15
MC17
(n−2)
(n−3)
MC16
Bit 0
Bit (n−1)
(n−2)
Figure 5−25. McBSP Transmit Timings
100
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.14.3
McBSP as SPI Master or Slave Timings
Table 5−27 to Table 5−34 assume testing over recommended operating conditions (see Figure 5−26 through
Figure 5−29).
Table 5−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)†‡
CVDD = 1.2 V
CVDD = 1.35 V
MASTER
MIN
†
‡
MC23
tsu(DRV-CKXL)
Setup time, DR valid before
CLKX low
MC24
th(CKXL-DRV)
Hold time, DR valid after
CLKX low
MC25
tsu(FXL-CKXH)
Setup time, FSX low before
CLKX high
MC26
tc(CKX)
Cycle time, CLKX
SLAVE
MAX
MIN
MASTER
MAX
MIN
MAX
SLAVE
MIN
UNIT
MAX
15
3 − 6P
10
3 − 6P
ns
0
3 + 6P
0
3 + 6P
ns
5
ns
16P
ns
5
2P
16P
2P
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)†‡
CVDD = 1.2 V
CVDD = 1.35 V
NO.
PARAMETER
MASTER§
CVDD = 1.6 V
MASTER§
SLAVE
MIN
MAX
T−5
MIN
MAX
UNIT
SLAVE
MIN
MAX
MIN
MAX
T+5
T−4
T+4
ns
C−4
C+4
ns
−3
3
C−3
C+1
MC27
td(CKXL-FXL)
Delay time, CLKX low
to FSX low¶
MC28
td(FXL-CKXH)
Delay time, FSX low to
CLKX high#
C−5
C+5
MC29
td(CKXH-DXV)
Delay time, CLKX high
to DX valid
−4
6
MC30
tdis(CKXL-DXHZ)
Disable time, DX highimpedance following
last data bit from CLKX
low
C−4
C+4
MC31
tdis(FXH-DXHZ)
Disable time, DX highimpedance following
last data bit from FSX
high
3P+ 4
3P + 19
3P+ 3
3P + 11
ns
MC32
td(FXL-DXV)
Delay time, FSX low to
DX valid
3P + 4
3P + 18
3P + 4
3P + 10
ns
3P + 3
5P + 15
3P + 3
5P + 8
ns
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
§ T = CLKX period = (1 + CLKGDV) * 2P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
‡
April 2004 − Revised January 2005
SPRS245C
101
ADVANCE INFORMATION
NO.
CVDD = 1.6 V
Electrical Specifications
MC25
LSB
MC26
MSB
CLKX
MC28
MC29
MC27
FSX
MC31
MC30
DX
MC32
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−3)
(n−4)
MC23
MC24
DR
Bit 0
Bit (n−1)
(n−2)
ADVANCE INFORMATION
Figure 5−26. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
102
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
Table 5−29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)†‡
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MASTER
MIN
MC33
tsu(DRV-CKXH)
Setup time, DR valid before
CLKX high
MC34
th(CKXH-DRV)
Hold time, DR valid after CLKX
high
MC25
tsu(FXL-CKXH)
Setup time, FSX low before
CLKX high
MC26
tc(CKX)
Cycle time, CLKX
CVDD = 1.6 V
SLAVE
MAX
MIN
MASTER
MAX
MIN
MAX
SLAVE
MIN
UNIT
MAX
15
3 − 6P
10
3 − 6P
ns
0
3 + 6P
0
3 + 6P
ns
5
ns
16P
ns
5
2P
16P
2P
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
CVDD = 1.2 V
CVDD = 1.35 V
NO.
PARAMETER
MASTER§
CVDD = 1.6 V
MASTER§
SLAVE
MIN
MAX
C−5
MIN
MAX
UNIT
SLAVE
MIN
MAX
MIN
MAX
C+5
C−4
C+4
ns
T−4
T+4
ns
MC27
td(CKXL-FXL)
Delay time, CLKX low to
FSX low¶
MC28
td(FXL-CKXH)
Delay time, FSX low to
CLKX high#
T−5
T+5
MC35
td(CKXL-DXV)
Delay time, CLKX low to
DX valid
−4
6
3P + 3
5P + 15
−3
3
3P + 3
5P + 8
ns
MC30
tdis(CKXL-DXHZ)
Disable time, DX highimpedance
following
last data bit from CLKX
low
−4
4
3P + 4
3P + 19
−3
1
3P + 3
3P + 12
ns
MC32
td(FXL-DXV)
Delay time, FSX low to
DX valid
D−4
D+4
3P + 4
3P + 18
D−3
D+3
3P + 4
3P + 10
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
§ T = CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
‡
April 2004 − Revised January 2005
SPRS245C
103
ADVANCE INFORMATION
Table 5−30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)†‡
Electrical Specifications
MC25
LSB
MC26
MSB
CLKX
MC28
MC35
MC27
FSX
MC32
MC30
DX
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−3)
(n−4)
MC33
MC34
DR
Bit 0
Bit (n−1)
(n−2)
ADVANCE INFORMATION
Figure 5−27. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
104
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
Table 5−31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)†‡
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MASTER
MIN
MC33
tsu(DRV-CKXH)
Setup time, DR valid before CLKX
high
MC34
th(CKXH-DRV)
Hold time, DR valid after CLKX
high
MC36
tsu(FXL-CKXL)
Setup time, FSX low before CLKX
low
MC26
tc(CKX)
Cycle time, CLKX
CVDD = 1.6 V
SLAVE
MAX
MIN
MASTER
MAX
MIN
MAX
SLAVE
MIN
UNIT
MAX
15
3 − 6P
10
3 − 6P
ns
0
3 + 6P
0
3 + 6P
ns
5
ns
16P
ns
5
2P
16P
2P
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
CVDD = 1.2 V
CVDD = 1.35 V
NO.
PARAMETER
MASTER§
CVDD = 1.6 V
MASTER§
SLAVE
MIN
MAX
T−5
MIN
MAX
UNIT
SLAVE
MIN
MAX
MIN
MAX
T+5
T−4
T+4
ns
D−4
D+4
ns
−3
3
D−3
D+1
MC37
td(CKXH-FXL)
Delay time, CLKX high
to FSX low¶
MC38
td(FXL-CKXL)
Delay time, FSX low to
CLKX low#
D−5
D+5
MC35
td(CKXL-DXV)
Delay time, CLKX low to
DX valid
−4
6
MC39
tdis(CKXH-DXHZ)
Disable time, DX highimpedance
following
last data bit from CLKX
high
D−4
D+4
MC31
tdis(FXH-DXHZ)
Disable time, DX highimpedance
following
last data bit from FSX
high
3P + 4
3P +19
3P + 3
3P +11
ns
MC32
td(FXL-DXV)
Delay time, FSX low to
DX valid
3P + 4
3P + 18
3P + 4
3P + 10
ns
3P + 3
5P + 15
3P + 3
5P + 8
ns
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
§ T = CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
‡
April 2004 − Revised January 2005
SPRS245C
105
ADVANCE INFORMATION
Table 5−32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)†‡
Electrical Specifications
MC36
LSB
MSB
MC26
CLKX
MC38
MC35
MC37
FSX
MC31
MC32
MC39
DX
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−3)
(n−4)
MC33
MC34
DR
Bit 0
Bit (n−1)
(n−2)
ADVANCE INFORMATION
Figure 5−28. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
106
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
Table 5−33. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)†‡
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MASTER
MIN
MC23
tsu(DRV-CKXL)
Setup time, DR valid before CLKX
low
MC24
th(CKXL-DRV)
Hold time, DR valid after CLKX
low
MC36
tsu(FXL-CKXL)
Setup time, FSX low before CLKX
low
MC26
tc(CKX)
Cycle time, CLKX
CVDD = 1.6 V
SLAVE
MAX
MIN
MASTER
MAX
MIN
MAX
SLAVE
MIN
UNIT
MAX
15
3 − 6P
10
3 − 6P
ns
0
3 + 6P
0
3 + 6P
ns
5
ns
16P
ns
5
2P
16P
2P
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
CVDD = 1.2 V
CVDD = 1.35 V
NO.
PARAMETER
MASTER§
CVDD = 1.6 V
MASTER§
SLAVE
MIN
MAX
D−5
MIN
MAX
UNIT
SLAVE
MIN
MAX
MIN
MAX
D+5
D−4
D+4
ns
T−4
T+4
ns
MC37
td(CKXH-FXL)
Delay time, CLKX high
to FSX low¶
MC38
td(FXL-CKXL)
Delay time, FSX low to
CLKX low#
T−5
T+5
MC29
td(CKXH-DXV)
Delay time, CLKX high
to DX valid
−4
6
3P + 3
5P + 15
−3
3
3P + 3
5P + 8
ns
MC39
tdis(CKXH-DXHZ)
Disable time, DX highimpedance
following
last data bit from CLKX
high
−4
4
3P + 4
3P + 19
−3
1
3P + 3
3P + 12
ns
MC32
td(FXL-DXV)
Delay time, FSX low to
DX valid
C−4
C+4
3P + 4
3P + 18
C−3
C+3
3P + 4
3P + 10
ns
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
§ T = CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
‡
April 2004 − Revised January 2005
SPRS245C
107
ADVANCE INFORMATION
Table 5−34. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)†‡
Electrical Specifications
MC36
LSB
MSB
MC26
CLKX
MC38
MC29
MC37
FSX
MC32
MC39
DX
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
MC23
MC24
DR
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
ADVANCE INFORMATION
Figure 5−29. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
108
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.14.4
McBSP General-Purpose I/O Timings
Table 5−35 and Table 5−36 assume testing over recommended operating conditions (see Figure 5−30).
Table 5−35. McBSP General-Purpose I/O Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
MIN
†
CVDD = 1.6 V
MAX
MIN
UNIT
MAX
MC20
tsu(MGPIO-COH)
Setup time, MGPIOx input mode before CLKOUT high†
7
7
ns
MC21
th(COH-MGPIO)
Hold time, MGPIOx input mode after CLKOUT high†
0
0
ns
MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.
NO.
MC22
‡
CVDD = 1.2 V
CVDD = 1.35 V
PARAMETER
td(COH-MGPIO)
CVDD = 1.6 V
MIN
MAX
MIN
MAX
0
7
0
7
Delay time, CLKOUT high to MGPIOx output mode‡
UNIT
ns
MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.
MC20
CLKOUT†
MC22
MC21
MGPIO‡
Input Mode
MGPIO§
Output Mode
†
CLKOUT reflects the CPU clock.
MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.
§ MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.
‡
Figure 5−30. McBSP General-Purpose I/O Timings
April 2004 − Revised January 2005
SPRS245C
109
ADVANCE INFORMATION
Table 5−36. McBSP General-Purpose I/O Switching Characteristics
Electrical Specifications
5.15 Enhanced Host-Port Interface (EHPI) Timings
Table 5−37 and Table 5−38 assume testing over recommended operating conditions (see Figure 5−31
through Figure 5−36).
Table 5−37. EHPI Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
NO.
ADVANCE INFORMATION
MIN
†
MAX
CVDD = 1.6 V
MIN
UNIT
MAX
E11
tsu(HASL-HDSL)
Setup time, HAS low before HDS low
4
4
ns
E12
th(HDSL-HASL)
Hold time, HAS low after HDS low
3
3
ns
E13
tsu(HCNTLV-HDSL)
Setup time, (HR/W, HA[13:0], HBE[1:0], HCNTL[1:0]) valid
before HDS low
2
2
ns
E14
th(HDSL-HCNTLIV)
Hold time, (HR/W, HA[13:0], HBE[1:0], HCNTL[1:0]) invalid
after HDS low
4
4
ns
E15
tw(HDSL)
Pulse duration, HDS low
4P†
4P†
ns
4P†
4P†
ns
E16
tw(HDSH)
Pulse duration, HDS high
E17
tsu(HDV-HDSH)
Setup time, HD bus write data valid before HDS high
3
3
ns
E18
th(HDSH-HDIV)
Hold time, HD bus write data invalid after HDS high
4
4
ns
E19
tsu(HCNTLV-HASL)
Setup time, (HR/W, HBE[1:0], HCNTL[1:0]) valid before
HAS low
3
3
ns
E20
th(HASL-HCNTLIV)
Hold time, (HR/W, HBE[1:0], HCNTL[1:0]) valid after HAS low
4
4
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−38. EHPI Switching Characteristics
NO.
†
‡
PARAMETER
E1
ten(HDSL-HDD)M
Enable time, HDS low to HD bus enabled
(memory access)
E2
td(HDSL-HDV)M
Delay time, HDS low to HD bus read data valid
(memory access)
E4
ten(HDSL-HDD)R
Enable time, HDS low to HD enabled
(register access)
E5
td(HDSL-HDV)R
Delay time, HDS low to HD bus read data valid
(register access)
E6
tdis(HDSH-HDIV)
Disable time, HDS high to HD bus read data invalid
E7
td(HDSL-HRDYL)
Delay time, HDS low to HRDY low (during reads)
E8
td(HDV-HRDYH)
Delay time, HD bus valid to HRDY high
(during reads)
E9
td(HDSH-HRDYL)
Delay time, HDS high to HRDY low (during writes)
E10
td(HDSH-HRDYH)
Delay time, HDS high to HRDY high (during writes)
E21
td(COH-HINT)
Delay time, CLKOUT high to HINT high/low
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
UNIT
MIN
MAX
MIN
MAX
6
26
6
19
14P†‡
6
14P†‡
26
6
26
6
26
6
18
2
18
0
ns
19
ns
19
ns
19
ns
15
ns
2
14P†‡
ns
15
14P†‡
11
0
ns
ns
ns
8
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
EHPI latency is dependent on the number of DMA channels active, their priorities and their source/destination ports. The latency shown assumes
no competing CPU or DMA activity to the memory resource being accessed by the EHPI.
110
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
CLKOUT†
E21
HINT
†
CLKOUT reflects the CPU clock.
Figure 5−31. HINT Timings
Read
Write
HCS
E16
E15
E15
HDS
E14
E13
ADVANCE INFORMATION
E14
E13
HR/W
HBE[1:0]
Valid
Valid
HCNTL0
Valid
Valid
HA[13:0]
Valid
Valid
E2
E1
E6
HD[15:0]
(read)
Read Data
E17
HD[15:0]
(write)
E18
Write Data
E10
E7
E8
E9
HRDY
NOTES: A. Any non-multiplexed access with HCNTL0 low will result in HPIC register access. For data read or write, HCNTL0 must stay high
during the EHPI access.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−32. EHPI Nonmultiplexed Read/Write Timings
April 2004 − Revised January 2005
SPRS245C
111
Electrical Specifications
Read
Write
HCS
E11
E12
E12
E11
HAS
E15
E16
E15
HDS
E20
E19
E20
E19
E13
E13
E14
E14
ADVANCE INFORMATION
HR/W
HBE[1:0]
HCNTL[1:0]
Valid
Valid
Valid (11)
Valid (11)
E2
E6
E1
HD[15:0]
(read)
Read Data
E17
HD[15:0]
(write)
E18
Write Data
E10
E7
E8
E9
HRDY
NOTE: The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing
requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−33. EHPI Multiplexed Memory (HPID) Read/Write Timings Without Autoincrement
112
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
HCS
E11
E12
HAS
E15
E16
HDS
E20
E19
E13
E14
HBE[1:0]
HCNTL[1:0]
Valid
Valid
Valid (01)
Valid (01)
E2
E2
E6
E1
HD[15:0]
(read)
E6
E1
Read Data
Read Data
E7
E8
E7
E8
HRDY
HPIA contents
n
n+1
n+2
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. In autoincrement mode, if HBE[1:0] are used to access the data as 8-bit-wide units, the HPIA increments only following each high
byte (HBE1 low) access.
C. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−34. EHPI Multiplexed Memory (HPID) Read Timings With Autoincrement
April 2004 − Revised January 2005
SPRS245C
113
ADVANCE INFORMATION
HR/W
Electrical Specifications
HCS
E12
E11
HAS
E15
E16
HDS
E20
E19
E13
E14
HR/W
ADVANCE INFORMATION
HBE[1:0]
HCNTL[1:0]
Valid
Valid
Valid (01)
Valid (01)
E17
HD[15:0]
(write)
E18
Write Data
Write Data
E10
E10
E9
E9
HRDY
n
HPIA contents
n+1
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−35. EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement
114
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
Read
Write
HCS
E11
E12
E11
E12
HAS
E15
E16
E15
HDS
E20
E19
E13
E19
E20
E13
E14
E14
HBE[1:0]
HCNTL[1:0]
Valid
Valid
Valid (10 or 00)
Valid (10 or 00)
E5
E6
E4
HD[15:0]
(read)
Read Data
E17
HD[15:0]
(write)
E18
Write Data
HRDY
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−36. EHPI Multiplexed Register Read/Write Timings
April 2004 − Revised January 2005
SPRS245C
115
ADVANCE INFORMATION
HR/W
Electrical Specifications
5.16 I2C Timings
Table 5−39 and Table 5−40 assume testing over recommended operating conditions (see Figure 5−37 and
Figure 5−38).
Table 5−39. I2C Signals (SDA and SCL) Timing Requirements
CVDD = 1.2 V
CVDD = 1.35 V
STANDARD
MODE
NO.
MIN
FAST
MODE
MIN
STANDARD
MODE
MAX
MIN
MAX
FAST
MODE
MIN
UNIT
MAX
tc(SCL)
Cycle time, SCL
10
2.5
10
2.5
µs
tsu(SCLH-SDAL)
Setup time, SCL high
before SDA low for a
repeated START condition
4.7
0.6
4.7
0.6
µs
IC3
th(SCLL-SDAL)
Hold time, SCL low after
SDA low for a START and
a repeated START
condition
4
0.6
4
0.6
µs
IC4
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
4.7
1.3
µs
IC5
tw(SCLH)
Pulse duration, SCL high
4
0.6
4
0.6
µs
IC6
tsu(SDA-SCLH)
Setup time, SDA valid
before SCL high
250
100†
250
100†
ns
IC7
th(SDA-SCLL)
Hold time, SDA valid after
SCL low
0‡
0‡
0‡
0‡
IC8
tw(SDAH)
Pulse duration, SDA high
between
STOP
and
START conditions
4.7
1.3
4.7
1.3
IC9
tr(SDA)
Rise time, SDA
IC1
IC2
ADVANCE INFORMATION
MAX
CVDD = 1.6 V
300
1000
20 + 0.1Cb¶
300
ns
300
1000
20 + 0.1Cb¶
300
ns
300
300
20 + 0.1Cb¶
300
ns
300
0.1Cb¶
300
ns
1000
20 +
IC11
tf(SDA)
Fall time, SDA
300
20 +
IC13
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP
condition)
IC14
tw(SP)
Pulse duration, spike
(must be suppressed)
IC15
Cb¶
Capacitive load for each
bus line
µs
0.1Cb¶
0.1Cb¶
0.1Cb¶
Rise time, SCL
Fall time, SCL
µs
20 + 0.1Cb¶
tr(SCL)
tf(SCL)
0.9§
1000
IC10
IC12
0.9§
300
4.0
20 +
300
0.6
0
400
4.0
µs
0.6
50
400
20 +
0
400
50
ns
400
pF
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C-Bus Specification) before the SCL line is released.
‡ A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
§ The maximum t
h(SDA-SCLL) has only to be met if the device does not stretch the LOW period [tw(SCLL)] of the SCL signal.
¶ C = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
b
†
I2C Bus is a trademark of Koninklijke Philips Electronics N.V.
116
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
IC11
IC9
SDA
IC6
IC8
IC14
IC4
IC13
IC5
IC10
SCL
IC1
IC12
IC3
IC2
IC7
IC3
Stop
Start
Repeated
Start
Stop
ADVANCE INFORMATION
Figure 5−37. I2C Receive Timings
April 2004 − Revised January 2005
SPRS245C
117
Electrical Specifications
Table 5−40. I2C Signals (SDA and SCL) Switching Characteristics
CVDD = 1.2 V
CVDD = 1.35 V
NO.
STANDARD
MODE
PARAMETER
MIN
ADVANCE INFORMATION
FAST
MODE
MAX
MIN
STANDARD
MODE
MAX
MIN
MAX
FAST
MODE
MIN
UNIT
MAX
tc(SCL)
Cycle time, SCL
10
2.5
10
2.5
µs
IC17
td(SCLH-SDAL)
Delay time, SCL high to
SDA low for a repeated
START condition
4.7
0.6
4.7
0.6
µs
IC18
td(SDAL-SCLL)
Delay time, SDA low to
SCL low for a START and
a repeated START
condition
4
0.6
4
0.6
µs
IC19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
4.7
1.3
µs
IC20
tw(SCLH)
Pulse duration, SCL high
4
0.6
4
0.6
µs
IC21
td(SDA-SCLH)
Delay time, SDA valid to
SCL high
250
100
250
100
ns
IC22
tv(SCLL-SDAV)
Valid time, SDA valid
after SCL low
0
0
0
0
IC23
tw(SDAH)
Pulse duration, SDA high
between STOP and
START conditions
4.7
1.3
4.7
1.3
IC24
tr(SDA)
Rise time, SDA
IC16
1000
20 + 0.1Cb†
300
ns
300
1000
20 + 0.1Cb†
300
ns
300
300
20 + 0.1Cb†
300
ns
300
0.1Cb†
300
ns
20 +
IC26
tf(SDA)
Fall time, SDA
300
20 +
IC28
td(SCLH-SDAH)
IC29
Cp
Capacitance
I2C pin
300
20 +
4
for each
µs
300
1000
Delay time, SCL high to
SDA high for a STOP
condition
µs
0.1Cb†
0.1Cb†
0.1Cb†
Rise time, SCL
Fall time, SCL
0.9
20 + 0.1Cb†
tr(SCL)
tf(SCL)
0.9
1000
IC25
IC27
†
CVDD = 1.6 V
300
0.6
10
4
10
20 +
µs
0.6
10
10
pF
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
IC26
IC24
SDA
IC21
IC23
IC19
IC28
IC20
IC25
SCL
IC16
IC27
IC18
IC17
IC22
IC18
Stop
Start
Repeated
Start
Stop
Figure 5−38. I2C Transmit Timings
118
SPRS245C
April 2004 − Revised January 2005
Mechanical Data
6
Mechanical Data
6.1
Package Thermal Resistance Characteristics
Table 6−1 and Table 6−2 provide the estimated thermal resistance characteristics for the TMS320VC5503
DSP package types.
PACKAGE
GHH
PGE
RΘJA (°C / W)
BOARD TYPE†
AIRFLOW (LFM)
37.1
High-K
0
35.1
High-K
150
33.7
High-K
250
32.2
High-K
500
70.3
Low-K
0
61.6
Low-K
150
56.5
Low-K
250
49.3
Low-K
500
71.2
High-K
0
61.8
High-K
150
58.9
High-K
250
54.8
High-K
500
103.6
Low-K
0
84.2
Low-K
150
77.8
Low-K
250
69.4
Low-K
500
ADVANCE INFORMATION
Table 6−1. Thermal Resistance Characteristics (Ambient)
†Board
types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area
Array Surface Mount Package Thermal Measurements.
Table 6−2. Thermal Resistance Characteristics (Case)
†
6.2
PACKAGE
RΘJC (°C / W)
BOARD TYPE†
GHH
13.8
2s JEDEC Test Card
PGE
13.8
2s JEDEC Test Card
Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area Array
Surface Mount Package Thermal Measurements.
Packaging Information
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
April 2004 − Revised January 2005
SPRS245C
119
PACKAGE OPTION ADDENDUM
www.ti.com
5-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
TMS320VC5503GHH
TMS320VC5503PGE
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
Package
Type
Package
Drawing
ACTIVE
BGA
GHH
179
160
TBD
SNPB
Level-3-220C-168HR
ACTIVE
LQFP
PGE
144
60
TBD
CU NIPDAU
Level-4-220C-72HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPBG058B – JANUARY 1998 – REVISED MAY 2002
GHH (S–PBGA–N179)
PLASTIC BALL GRID ARRAY
12,10
11,90
10,40 TYP
SQ
0,80
0,40
A1 Corner
0,40
0,80
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08
0,45
0,35
0,10
4173504-3/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGAt configuration.
MicroStar BGA is a trademark of Texas Instruments.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147 / C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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