W25P10, W25P20 AND W25P40
1M-BIT, 2M-BIT AND 4M-BIT
SERIAL FLASH MEMORY WITH 40MHZ SPI
Formally NexFlash NX25P10, NX25P20 and NX25P40
The Winbond W25P10/20/40 are fully compatible with the previous NexFlash
NX25P10/20/40 Serial Flash memories.
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Publication Release Date: November 28, 2005
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W25P10, W25P20 AND W25P40
Table of Contents1.
GENERAL DESCRIPTION ......................................................................................................... 4
2.
FEATURES ................................................................................................................................. 4
3.
PIN CONFIGURATION ............................................................................................................... 5
4.
PIN DESCRIPTION..................................................................................................................... 5
4.1
Package Types ............................................................................................................... 5
4.2
Chip Select (/CS) ............................................................................................................ 5
4.3
Serial Data Output (DO) ................................................................................................. 6
4.4
Write Protect (/WP)......................................................................................................... 6
4.5
HOLD (/HOLD) ............................................................................................................... 6
4.6
Serial Clock (CLK) .......................................................................................................... 6
4.7
Serial Data Input (DI) ...................................................................................................... 6
5.
BLOCK DIAGRAM ...................................................................................................................... 7
6.
FUNCTIONAL DESCRIPTION ................................................................................................... 8
6.1
6.2
SPI OPERATIONS ......................................................................................................... 8
6.1.1
SPI Modes........................................................................................................................8
6.1.2
Hold Function ...................................................................................................................8
WRITE PROTECTION.................................................................................................... 8
6.2.1
7.
Write Protect Features......................................................................................................8
CONTROL AND STATUS REGISTERS..................................................................................... 9
7.1
7.2
STATUS REGISTER ...................................................................................................... 9
7.1.1
BUSY................................................................................................................................9
7.1.2
Write Enable Latch (WEL) ................................................................................................9
7.1.3
Block Protect Bits (BP2, BP1, BP0)................................................................................10
7.1.4
Reserved Bits .................................................................................................................10
7.1.5
Status Register Protect (SRP) ........................................................................................10
7.1.6
Status Register Memory Protection ................................................................................11
INSTRUCTIONS........................................................................................................... 11
7.2.1
Manufacturer and Device Identification...........................................................................12
7.2.2
Instruction Set (1).............................................................................................................12
7.2.3
Write Disable (04h).........................................................................................................13
7.2.4
Write Enable (06h)..........................................................................................................13
7.2.5
Read Status Register (05h) ............................................................................................14
7.2.6
Write Status Register (01h) ............................................................................................15
7.2.7
Read Data (03h) .............................................................................................................16
7.2.8
Fast Read (0Bh) .............................................................................................................17
7.2.9
Page Program (02h) .......................................................................................................18
7.2.10
Sector Erase (D8h).......................................................................................................19
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W25P10, W25P20 AND W25P40
8.
9.
7.2.11
Chip Erase (C7h)..........................................................................................................20
7.2.12
Power-down (B9h) ........................................................................................................21
7.2.13
Release Power-down / Device ID (ABh) .......................................................................22
7.2.14
Read Manufacturer / Device ID (90h) ...........................................................................24
ELECTRICAL CHARACTERISTICS......................................................................................... 25
8.1
Absolute Maximum Ratings (1) .................................................................................... 25
8.2
Operating Ranges......................................................................................................... 25
8.3
8.4
Power-up Timing and Write Inhibit Threshold .............................................................. 26
DC Electrical Characteristics (Preliminary)(1) .............................................................. 27
8.5
AC Measurement Conditions........................................................................................ 28
8.6
AC Electrical Characteristics ........................................................................................ 29
8.7
AC Electrical Characteristics (cont’d) ........................................................................... 30
8.8
Serial Output Timing ..................................................................................................... 31
8.9
Input Timing .................................................................................................................. 31
8.10
Hold Timing................................................................................................................... 31
PACKAGE SPECIFICATION .................................................................................................... 32
9.1
8-Pin SOIC 150-mil (Winbond Package Code SN) (NexFlash Package Code N) ....... 32
10.
ORDERING INFORMATION .................................................................................................... 33
11.
REVISION HISTORY ................................................................................................................ 34
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1. GENERAL DESCRIPTION
The W25P10 (1M-bit), W25P20 (2M-bit) and W25P40 (4M-bit) Serial Flash memories provide a
storage solution for systems with limited space, pins and power. They are ideal for code download
applications as well as storing voice, text and data. The devices operate on a single 2.7V to 3.6V
power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are
offered in space-saving 8-pin SOIC type packages as shown below. Contact Winbond for availability
of alternate packages. As part of a family of Serial Flash products, Winbond also provides a
compatible migration path to 8M/16M/32M-bit densities.
The W25P10/20/40 array is organized into 512/1024/2048 programmable pages of 256-bytes each. A
single byte or, up to 256 bytes, can be programmed at a time using the Page Program instruction.
Pages are grouped into 2/4/8 erasable sectors of 256 pages (64K-byte) each as shown in figure 2.
Both Sector Erase and Chip (full chip) Erase instructions are supported.
The Serial Peripheral Interface (SPI) consists of four pins (Serial Clock, Chip Select, Serial Data In
and Serial Data Out) that support high speed serial data transfers up to 40MHz. A Hold pin, Write
Protect pin and programmable write protect features provide further control flexibility. Additionally, the
device can be queried for manufacturer and device ID. Special customer ID (for copy authentication)
and factory programming is available, contact Winbond for more information.
The Winbond W25P10/20/40 are fully compatible with the previous NexFlash NX25P10/20/40 Serial
Flash memories.
2. FEATURES
• 1M / 2M / 4M-bit Serial Flash Memories
• Programming Features
– Page program up to 256 bytes <2ms
– Sector Erase (64K-byte) 2 seconds
– Chip erase: 3 seconds (25P10/20),
5 seconds (25P40)
– 100,000 erase/write cycles
– Twenty-year data retention
• Family of Serial Flash Memories
– W25P10: 1M-bit/128K-byte (131,072)
– W25P20: 2M-bit/256K-byte (262,144)
– W25P40: 4M-bit/512K-byte (524,288)
– 256-bytes per programmable page
– Migration path to 8M/16M/32M-bit
• Software and Hardware Write Protection
– Write-Protect all or portion of memory
– Enable/Disable protection with /WP pin
• 4-pin SPI Serial Interface
– Clock, Chip Select, Data In, Data Out
– Easily interfaces to popular microcontrollers
– Compatible with SPI Modes 0 and 3
– Bottom Boot organization (standard)
– Optional Hold function for SPI flexibility
• Space Saving Package
– Tiny 8-pin SOIC 150mil
• Ideal for systems with limited pins, space,
and power
– Controller-based serial code-download
– µC systems storing data, text or voice
– Battery-operated and portable products
• Low Power Consumption, Wide
Temperature Range
– Single 2.7 to 3.6V supply
– 4mA active current, 1µA Power-down (typ)
– -40° to +85°C operating range
• Fast and Flexible Serial Data Access
– 40MHz Fast Read, 33MHz Standard Read
– Byte-addressable Read and Program
– Auto-increment Read capability
– Manufacturer and Device ID
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W25P10, W25P20 AND W25P40
3. PIN CONFIGURATION
Figure 1. W25P10, W25P20 and W25P40 Pin Assignments, 8-pin SOIC 150-mil
4. PIN DESCRIPTION
PIN NO.
PIN NAME
I/O
1
/CS
I
Chip Select Input
2
DO
O
Data Output
3
/WP
I
Write Protect Input
4
GND
5
DI
I
Data Input
6
CLK
I
Serial Clock Input
7
/HOLD
I
Hold Input
8
VCC
4.1
FUNCTION
Ground
Power Supply
Package Types
The standard package for the W25P10/20/40 is an 8-pin plastic SOIC with 150-mil body (Winbond
package code SN) (NexFlash package code N). It also allows a package migration path to higher
density Serial Flash devices. The pinout for the package is shown in Figure 1. Package diagrams and
dimensions are illustrated at the end of this data sheet. Optional 8-contact MLP packages may be
available. Please contact Winbond for further MLP package information.
4.2
Chip Select (/CS)
The SPI Chip Select (/CS pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle
is in progress. When /CS is brought low the device will be selected, power consumption will increase
to active levels and instructions can be written to and data read from the device. After power-up, /CS
must transition from high to low before a new instruction will be accepted. The /CS input must track
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W25P10, W25P20 AND W25P40
the VCC supply level at power-up (see “Write Protection” and figure 16). If needed a pull-up resister
on /CS can be used to accomplish this.
4.3
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
4.4
Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is
active low.
4.5
HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought
low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function
can be useful when multiple devices are sharing the same SPI signals. (“See Hold function”)
4.6
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI "Operations")
4.7
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially
written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input
pin.
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W25P10, W25P20 AND W25P40
5. BLOCK DIAGRAM
Figure 2. W25P10, W25P20 and W25P40 Block Diagram
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6. FUNCTIONAL DESCRIPTION
6.1
SPI OPERATIONS
6.1.1 SPI Modes
The W25P10/20/40 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation
Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3
concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the
CLK. Data output on the DO pin is clocked out on the falling edge of CLK.
6.1.2 Hold Function
The /HOLD signal allows the W25P10/20/40 operation to be paused while it is actively selected (when
/CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are
shared with other devices. For example, consider if the page buffer was only partially written when a
priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the
instruction and the data in the buffer so programming can resume where it left off once the bus is
available again.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will
activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition
will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will terminate after the next falling edge of CLK.
During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)
and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the
full duration of the /HOLD operation to avoid resetting the internal logic state of the device.
6.2
WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern the
W25P10/20/40 provides several means to protect data from inadvertent writes.
6.2.1 Write Protect Features
• Device resets when VCC is below threshold.
• Time delay write disable after Power-up.
• Write enable/disable instructions.
• Automatic write disable after program and erase.
• Software write protection using Status Register.
• Hardware write protection using Status Register and /WP pin.
• Write Protection using Power-down instruction.
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W25P10, W25P20 AND W25P40
Upon power-up or at power-down the W25P10/20/40 will maintain a reset condition while VCC is
below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 17). While
reset, all operations are disabled and no instructions are recognized. During power-up and after the
VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time
delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Chip Erase and the Write
Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at
power-up until the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS
can be used to accomplish this.
After power-up the device in automatically placed in a write-disabled state with the Status Register
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page
Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After
completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically
cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP) and Block Protect (BP2, BP1, and BP0) bits. These Status Register
bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the
Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware
control. See Status Register for further information.
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are
ignored except for the Release Power-down instruction.
7. CONTROL AND STATUS REGISTERS
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled, and the state of write protection. The Write
Status Register instruction can be used to configure the devices write protection features. See Figure
3.
7.1
STATUS REGISTER
7.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing
a Page Program, Sector Erase, Chip Erase or Write Status Register instruction. During this time the
device will ignore further instructions except for the Read Status Register instruction (see tW, tPP, tSE
and tCE in AC Characteristics). When the program, erase or write status register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further
instructions.
7.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing
a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A
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write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Chip Erase and Write Status Register.
7.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3,
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array
can be protected from Program and Erase instructions (see Status Register Memory Protection table).
The factory default setting for the Block Protection Bits is 0, none of the array protected. The Block
Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write
Protect (/WP) pin is low. The W25P20 and W25P10 do not use BP2.
7.1.4 Reserved Bits
Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0 for these
bit locations. It is recommended to mask out the reserved bit when testing the Status Register. Doing
this will ensure compatibility with future devices.
7.1.5 Status Register Protect (SRP)
The Status Register Protect (SRP) bit is a non-volatile read/write bit in the status register (S7) that can
be used in conjunction with the Write Protect (/WP) pin to disable writes to the status register. When
the SRP bit is set to a 0 state (factory default) the /WP pin has no control over the status register.
When the SRP pin is set to a 1, the Write Status Register instruction is locked out while the /WP pin is
low. When the /WP pin is high the Write Status Register instruction is allowed.
Figure 3. Status Register Bit Locations
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W25P10, W25P20 AND W25P40
7.1.6
Status Register Memory Protection
STATUS REGISTER(1)
W25P40 (4M-BIT) MEMORY PROTECTION
BP2
BP1
BP0
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
NONE
7
6 and 7
4 thru 7
ALL
NONE
070000h - 07FFFFh
060000h - 07FFFFh
040000h - 07FFFFh
000000h - 07FFFFh
NONE
512K-bit
1M-bit
2M-bit
4M-bit
NONE
Upper 1/8
Upper 1/4
Upper 1/2
ALL
STATUS REGISTER(1)
W25P20 (2M-BIT) MEMORY PROTECTION
BP2
BP1
BP0
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
x
x
x
x
0
0
1
1
0
1
0
1
NONE
3
2 and 3
ALL
NONE
030000h - 03FFFFh
020000h - 03FFFFh
000000h - 03FFFFh
NONE
512K-bit
1M-bit
2M-bit
NONE
Upper 1/4
Upper 1/2
ALL
STATUS REGISTER(1)
W25P10 (1M-BIT) MEMORY PROTECTION
BP2
BP1
BP0
SECTOR(S)
ADDRESSES
DENSITY (KB)
PORTION
x
x
x
0
1
1
x
0
1
NONE
NONE
ALL
NONE
NONE
000000h - 01FFFFh
NONE
NONE
1M-bit
NONE
NONE
ALL
Note:
1. x = don’t care
7.2
INSTRUCTIONS
The instruction set of the W25P10/20/40 consists of twelve basic instructions that are fully controlled
through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the
DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 16. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a
full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects
the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or
when the Status Register is being written, all instructions except for Read Status Register will be
ignored until the program or erase cycle has completed.
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W25P10, W25P20 AND W25P40
7.2.1
Manufacturer and Device Identification
MANUFACTURER ID
(M7-M0)
Winbond Serial Flash
EFH
Device ID
W25P10
W25P20
W25P40
(ID7-ID0)
10h
11h
12h
7.2.2
Instruction Set (1)
INSTRUCTION
NAME
BYTE 1
CODE
Write Enable
Write Disable
Read Status
Register
Write Status
Register
Read Data
06h
04h
BYTE 2(5)
BYTE 3
BYTE 4
BYTE 5
BYTE 6
05h
(S7–S0)(1)
01h
S7–S0
03h
A23–A16
A15–A8
A7–A0
(D7–D0)
(Next byte)
Fast Read
0Bh
A23–A16
A15–A8
A7–A0
dummy
(D7–D0)
Page Program
02h
A23–A16
A15–A8
A7–A0
(D7–D0)
(Next byte)
Sector Erase
Chip Erase
Power-down
Release Powerdown / Device ID
D8h
C7h
B9h
A23–A16
A15–A8
A7–A0(6)
ABh
dummy
dummy
dummy
(ID7-ID0)
90h
dummy
dummy
00h
(M7-M0)
Manufacturer/
Device ID
N-BYTES
(2)
continuous
(Next Byte)
continuous
up to 256
bytes
(3)
(ID7-ID0)
(4)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being
read from the device on the DO pin.
2. The Status Register contents will repeat continuously until /CS terminates the instruction.
3. The Device ID will repeat continuously until /CS terminates the instruction.
4. The Manufacturer ID and Device ID bytes will repeat continuously until /CS terminates the instruction.
5. Unused upper address bits must be set to a 0 for the W25P10.
6. The lowest 16 address bits (A15-A0) must be set to 0.
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W25P10, W25P20 AND W25P40
7.2.3 Write Disable (04h)
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to
a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Chip Erase and Write Status
Register instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction
code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
Figure 4. Write Disable Instruction Sequence Diagram
7.2.4 Write Enable (06h)
The Write Disable instruction (Figure 5) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h”
into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up
and upon completion of the Write Status Register, Page Program, Sector Erase, and Chip Erase
instructions.
Figure 5. Write Enable Instruction Sequence Diagram
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7.2.5 Read Status Register (05h)
The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” into the DI pin on the rising edge of
CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first as shown in figure 6. The Status Register bits are shown in figure 3 and
include the BUSY, WEL, BP2-BP0, and SRP bits (see description of the Status Register earlier in this
data sheet).
The Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 6. The instruction is completed by driving /CS high.
Figure 6. Read Status Register Instruction Sequence Diagram
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W25P10, W25P20 AND W25P40
7.2.6 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable
instruction must previously have been executed for the device to accept the Write Status Register
Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by
driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as
illustrated in figure 7. The Status Register bits are shown in figure 3 and described earlier in this data
sheet.
Only non-volatile Status Register bits SRP, BP2, BP1 and BP0 (bits 7, 4, 3 and 2) can be written to.
All other Status Register bit locations are read-only and will not be affected by the Write Status
Register instruction.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Write Status Register instruction will not be executed. After /CS is driven high, the self-timed
Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While
the Write Status Register cycle is in progress, the Read Status Register instruction may still accessed
to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a
0 when the cycle is finished and ready to accept other instructions again. After the Write Register
cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block Protect bits (BP2, BP1 and BP0) to be set for
protecting all, a portion, or none of the memory from erase and program instructions. Protected areas
become read-only (see Status Register Memory Protection table). The Write Status Register
instruction also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction
with the Write Protect (/WP) pin to disable writes to the status register. When the SRP bit is set to a 0
state (factory default) the /WP pin has no control over the status register. When the SRP pin is set to a
1, the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is
high the Write Status Register instruction is allowed.
Figure 7. Write Status Register Instruction Sequence Diagram
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W25P10, W25P20 AND W25P40
7.2.7 Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory.
The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h”
followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the
rising edge of the CLK pin. After the address is received, the data byte of the addressed memory
location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first.
The address is automatically incremented to the next higher address after each byte of data is shifted
out allowing for a continuous stream of data. This means that the entire memory can be accessed with
a single instruction as long as the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in figure 8. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of
fR (see AC Electrical Characteristics).
Figure 8. Read Data Instruction Sequence Diagram
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W25P10, W25P20 AND W25P40
7.2.8 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding a
“dummy” byte after the 24-bit address as shown in figure 9. The dummy byte allows the devices
internal circuits additional time for setting up the initial address. The dummy byte data value on the DI
pin is a “don’t care”.
Figure 9. Fast Read Instruction Sequence Diagram
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Publication Release Date: November 28, 2005
Revision M
W25P10, W25P20 AND W25P40
7.2.9 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes of data to be programmed at memory
locations previously erased to all 1s (FFh). A Write Enable instruction must be executed before the
device will accept the Page Program Instruction (Status Register bit WEL must equal 1). The
instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a
24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be driven low for
the entire length of the instruction while data is being sent to the device. The Page Program instruction
sequence is shown in figure 10.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the
remaining page length, the addressing will wrap to the beginning of the page. Less than 256 bytes can
be programmed without having any effect on other bytes within the same page. If more than 256 bytes
are sent to the device the addressing will wrap to the beginning of the page and overwrite previously
sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS
is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See
AC Characteristics). While the Page Program cycle is in progress, the Read Status Register
instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during
the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit
in the Status Register is cleared to 0. The Page Program instruction will not be executed if the
addressed page is protected by the Block Protect (BP2, BP1, BP0) bits (see Status Register Memory
Protection table).
Figure 10. Page Program Instruction Sequence Diagram
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W25P10, W25P20 AND W25P40
7.2.10 Sector Erase (D8h)
The Sector Erase instruction sets all memory within a specified sector to the erased state of all 1s
(FFh). A Write Enable instruction must be executed before the device will accept the Erase Sector
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin
low and shifting the instruction code “D8h” followed a 24-bit sector address (A23-A0) (see Figure 2).
The lowest 16 address bits (A15-A0) must be set to 0. The Sector Erase instruction sequence is
shown in figure 11.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector
Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Sector Erase
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector
Erase instruction will not be executed if the addressed page is protected by the Block Protect (BP2,
BP1, BP0) bits (see Status Register Memory Protection table).
Figure 11. Sector Erase Instruction Sequence Diagram
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Publication Release Date: November 28, 2005
Revision M
W25P10, W25P20 AND W25P40
7.2.11 Chip Erase (C7h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “C7h”. The Chip Erase instruction sequence is shown in figure 12.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction
will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed
if any page is protected by the Block Protect (BP2, BP1, BP0) bits (see Status Register Memory
Protection table).
Figure 12. Chip Erase Instruction Sequence Diagram
- 20 -
W25P10, W25P20 AND W25P40
7.2.12 Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC
Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“B9h” as shown in figure 13.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Powerdown instruction will not be executed. After /CS is driven high, the power-down state will entered
within the time duration of tDP (See AC Characteristics). While in the power-down state only the
Release from Power-down / Device ID instruction, which restores the device to normal operation, will
be recognized. All other instructions are ignored. This includes the Read Status Register instruction,
which is always available during normal operation. Ignoring all but one instruction makes the Power
Down state a useful condition for securing maximum write protection. The device always powers-up in
the normal operation with the standby current of ICC1.
Figure 13. Deep Power-down Instruction Sequence Diagram
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Publication Release Date: November 28, 2005
Revision M
W25P10, W25P20 AND W25P40
7.2.13 Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, obtain the devices electronic identification (ID) number
or do both.
When used only to release the device from the power-down state, the instruction is issued by driving
the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in figure 14. After
the time duration of tRES1 (See AC Characteristics) the device will resume normal operation and other
instructions will be accepted. The /CS pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated
by driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The
Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in figure 15. The Device ID values for the W25P10, W25P20, and W25P40 are listed in the
Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction
is completed by driving /CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction
is the same as previously described, and shown in figure 13, except that after /CS is driven high it
must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the
device will resume normal operation and other instructions will be accepted.
If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write
cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on
the current cycle.
Figure 14. Release Power-down Instruction Sequence
- 22 -
W25P10, W25P20 AND W25P40
Figure 15. Release Power-down / Device ID Instruction Sequence Diagram
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Publication Release Date: November 28, 2005
Revision M
W25P10, W25P20 AND W25P40
7.2.14 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device
ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond
(EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first
as shown in figure 16. The Device ID values for the W25P10, W25P20, and W25P40 are listed in the
Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device
ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can
be read continuously, alternating from one to the other. The instruction is completed by driving /CS
high.
Figure 16. Read Manufacturer / Device ID Diagram
- 24 -
W25P10, W25P20 AND W25P40
8. ELECTRICAL CHARACTERISTICS
8.1
Absolute Maximum Ratings (1)
PARAMETERS
SYMBOL
Supply Voltage
VCC
Voltage Applied to Any Pin
VIO
Storage Temperature
TSTG
Lead Temperature
TLEAD
Electrostatic Discharge Voltage
CONDITIONS
RANGE
Relative to Ground
VESD
Human Body
Model(3)
UNIT
–0.6 to +4.0
V
–0.6 to VCC +0.4
V
–65 to +150
°C
See Note 2
°C
–2000 to +2000
V
Notes:
1 This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not
guaranteed. Exposure beyond absolute maximum ratings (listed above) may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive
on restrictions on hazardous substances (RoHS) 2002/95/EU..
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).
8.2
Operating Ranges
PARAMETER
Supply Voltage(1)
Ambient Temperature,
Operating
SYMBOL
VCC
TA
SPEC
CONDITIONS
UNIT
MIN
MAX
FR = 33MHz, fR = 25MHz
2.7
3.6
V
FR = 40MHz, fR = 25MHz
3.0
3.6
V
Industrial
–40
+85
°C
Note:
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming
(erase/write) voltage.
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Publication Release Date: November 28, 2005
Revision M
W25P10, W25P20 AND W25P40
8.3
Power-up Timing and Write Inhibit Threshold
PARAMETER
SPEC
SYMBOL
MIN
UNIT
MAX
VCC (min) to /CS Low
tVSL(1)
10
Time Delay Before Write Instruction
tPUW(1)
1
10
ms
Write Inhibit Threshold Voltage
VWI(1)
1
2
V
Note:
1. These parameters are characterized only.
Figure 17. Power-up Timing and Voltage Levels
- 26 -
µs
W25P10, W25P20 AND W25P40
8.4
DC Electrical Characteristics (Preliminary)(1)
PARAMETER
SYMBOL
SPEC
CONDITIONS
MIN
TYP
UNIT
MAX
Input Capacitance
CIN(2)
VIN = 0V(2)
6
pf
Output Capacitance
Cout(2)
VOUT = 0V(2)
8
pf
Input Leakage
ILI
±2
µA
I/O Leakage
ILO
±2
µA
Standby Current
ICC1
/CS = VCC,
VIN = GND or VCC
25
50
µA
Power-down Current
ICC2
/CS = VCC,
VIN = GND or VCC
<1
5
µA
Current Read Data
1MHz
ICC3
C = 0.1 VCC / 0.9 VCC
DO = Open
4
7
mA
Current Read Data
20MHz
C = 0.1 VCC / 0.9 VCC
DO = Open
10
14
mA
Current Read Data
33MHz
C = 0.1 VCC / 0.9 VCC
DO = Open
14
18
mA
Current Page
Program
ICC4
/CS = VCC
15
20
mA
Current Write Status
Register
ICC5
/CS = VCC
8
20
mA
Current Sector Erase ICC6
/CS = VCC
15
25
mA
Current Chip Erase
ICC7
/CS = VCC
17
25
mA
Input Low Voltage
VIL
–0.5
VCC x0.3
V
Input High Voltage
VIH
VCC x0.7
VCC +0.4
V
Output Low Voltage
VOL
IOL = 1.6 mA
0.4
V
Output High Voltage
VOH
IOH = –100 µA
VCC –0.2
V
Notes:
1. See Preliminary Designation.
2. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V.
- 27 -
Publication Release Date: November 28, 2005
Revision M
W25P10, W25P20 AND W25P40
8.5
AC Measurement Conditions
PARAMETER
SPEC
SYMBOL
UNIT
MIN
MAX
30
30
pF
5
ns
Load Capacitance
CL
Input Rise and Fall Times
TR, TF
Input Pulse Voltages
VIN
0.2 VCC to
0.8 VCC
V
Output Timing Reference Voltages
OUT
0.3 VCC to
0.7 VCC
V
Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 18. AC Measurement I/O Waveform
- 28 -
W25P10, W25P20 AND W25P40
8.6
AC Electrical Characteristics
DESCRIPTION
SYMBOL
SPEC
ALT
MIN
Clock frequency, for Fast Read (0Bh) and all
other instructions except Read Data (03h)
FR
TYP
UNIT
MAX
fC
2.7V-3.6V VCC
3.0V-3.6V VCC
D.C.
D.C.
33
40
MHz
MHz
D.C.
25
MHz
Clock freq. Read Data instruction (03h)
fR
Clock High, Low Time, for Fast Read (0Bh) and
all other instructions except Read Data (03h)
tCLH,
tCLL(1)
11
ns
Clock High, Low Time for Read Data instruction
tCRLH,
tCRLL(1)
11
ns
Clock Rise Time peak to peak
tCLCH(2)
0.1
V/ns
Clock Fall Time peak to peak
tCHCL(2)
0.1
V/ns
/CS Active Setup Time relative to CLK
tSLCH
5
ns
/CS Not Active Hold Time relative to CLK
tCHSL
5
ns
Data In Setup Time
tDVCH
tDSU
2
ns
Data In Hold Time
tCHDX
tDH
5
ns
/CS Active Hold Time relative to CLK
tCHSH
7/5
ns
/CS Not Active Setup Time relative to CLK
tSHCH
5
ns
/CS Deselect Time
tSHSL
tCSH
100
ns
Output Disable Time
tSHQZ(2)
tDIS
Clock Low to Output Valid
tCLQV
tV
Output Hold Time
tCLQX
tHO
/HOLD Active Setup Time relative to CLK
tHLCH
tCSS
(2.7V-3.6V / 3.0V-3.6V)
9
ns
13/9
ns
(2.7V-3.6V / 3.0V-3.6V)
0
ns
6/5
ns
(2.7V-3.6V / 3.0V-3.6V)
Continued – next page
- 29 -
Publication Release Date: November 28, 2005
Revision M
W25P10, W25P20 AND W25P40
8.7
AC Electrical Characteristics (cont’d)
DESCRIPTION
SYMBOL
SPEC
ALT
MIN
TYP
UNIT
MAX
/HOLD Active Hold Time relative to CLK
tCHHH
5
ns
/HOLD Not Active Setup Time relative to CLK
tHHCH
5
ns
/HOLD Not Active Hold Time relative to CLK
tCHHL
5
ns
/HOLD to Output Low-Z
tHHQX(2)
tLZ
9
ns
/HOLD to Output High-Z
tHLQZ(2)
tHZ
9
ns
Write Protect Setup Time Before /CS Low
tWHSL(4)
20
ns
Write Protect Hold Time After /CS High
tSHWL(4)
100
ns
/CS High to Power-down Mode
tDP(2)
3
µs
/CS High to Standby Mode without Electronic
Signature Read
tRES1(2)
3
µs
/CS High to Standby Mode with Electronic
Signature Read
tRES2(2)
1.8
µs
Write Status Register Cycle Time
tW
10
15
ms
Page Program Cycle Time
tPP
2
5
ms
Sector Erase Cycle Time
tSE
0.7
3
s
Chip Erase Cycle Time W25P10 and W25P20
Chip Erase Cycle Time W25P40
tCE
3
5
6
10
s
s
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or
characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set at 1.
- 30 -
W25P10, W25P20 AND W25P40
8.8
8.9
Serial Output Timing
Input Timing
8.10 Hold Timing
- 31 -
Publication Release Date: November 28, 2005
Revision M
W25P10, W25P20 AND W25P40
9. PACKAGE SPECIFICATION
9.1
8-Pin SOIC 150-mil (Winbond Package Code SN)
SYMBOL
A
A1
A2
b
C
D(3)
E
E1(3)
e(2)
L
θ
CP
MILLIMETERS
INCHES
MIN
TYP.
MAX
MIN
1.47
0.10
--0.33
0.19
4.80
5.80
3.80
1.60
--1.45
0.41
0.20
4.85
6.00
3.90
1.27 BSC
0.71
-----
1.72
0.24
--0.50
0.25
4.95
6.19
4.00
0.058
0.004
--0.013
0.0075
0.189
0.228
0.150
1.27
8o
0.10
0.015
0o
---
0.40
0o
---
TYP.
MAX
0.063
0.068
--0.009
0.057
--0.016
0.020
0.008
0.0098
0.191
0.195
0.236
0.244
0.154
0.157
0.050 BSC
0.028
0.050
--8o
--0.004
Notes:
1. Controlling dimensions: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane.
- 32 -
W25P10, W25P20 AND W25P40
10. ORDERING INFORMATION
- 33 -
Publication Release Date: November 28, 2005
Revision M
W25P10, W25P20 AND W25P40
11. REVISION HISTORY
VERSION
DATE
A
04/29/03
B
09/12/03
C
03/09/04
D
03/24/04
E
05/11/04
F
06/16/04
G
11/23/04
H
12/08/04
I
04/04/05
J
05/09/05
K
06/14/05
L
06/28/05
M
11/28/05
PAGE
DESCRIPTION
10, 11, 14, 16,
24
ALL
- 34 -
New Create
Incorporated spiFlash trademark for
W25P10, 20 and 40 product family. Adjusted
data for consistency
Adjusted pages for technical clarity. Updated
Special Options and Ordering Information
MLP metal die pad notification; Under
"Package Types," figure 3 and packaging
information.
Corrected dimensions in Packaging
Information section for 6x5mm MLP. Updated
Characterization information DC & AC
Modified dimensional data in the Packaging
Information for the 6x5mm MLP package
Added FR = 40MHz @ 3.0V to 3.6V VCC.
Added fR = 33MHz @ 3.0V to 3.6V VCC.
Modified tLEAD in Absolute Maximum Ratings
to reference JEDEC Standard information.
Added FR and fR conditions to Operating
Ranges. Updated ICC3 and ICC5 data in DC
Electrical Characteristics. Added 20/33MHz
call outs and updated min, max and typ data
in AC Electrical Characteristics
Updated 8-pin 150-mil SOIC package
information.
Removed 8-contact 6x5 MLP package from
document.
Updated and improved AC Parameters in
Table 7.6 and changed tCHSH, tCLQV and
tHLCH to reference voltage (2.7V-3.6V / 3.0V3.6V) for consistency with other spiFlash
memory data sheets.
Updated Important Notice.
Changed NexFlash part numbers to Winbond
part numbers and updated ordering and
contact information
Updated data sheet to comply with Winbond
standard
Updated FR and fR values in Operating
Ranges Table and AC Characteristics Table.
Updated Read Data (fR) values in Operating
Range and AC Characteristics Tables from
33MHz to 25MHz.
Corrected the pin assignment on table of pin
description of page 5.
W25P10, W25P20 AND W25P40
Preliminary Designation
The “Preliminary” designation on a Winbond data sheet indicates that the product is not fully
characterized. The specifications are subject to change and are not guaranteed. Winbond or an
authorized sales representative should be consulted for current information before using this product.
Trademarks
Winbond and spiFlash are trademarks of Winbond
Electronics Corporation All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property
or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
The Winbond W25P10/20/40 are fully compatible with the previous NexFlash NX25P10/20/40 Serial
Flash memories.
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Publication Release Date: November 28, 2005
Revision M