PRELIMINARY WMS7110/1 NONVOLATILE DIGITAL POTENTIOMETERS WITH UP/DOWN (3-WIRE) INTERFACE, 10KOHM, 50KOHM, 100KOHM RESISTANCE 128 TAPS WITH OPTIONAL OUTPUT BUFFER -1- Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 1. GENERAL DESCRIPTION The WMS711x is a 128 non-volatile linear digital potentiometers available in 10KΩ, 50KΩ and 100KΩ resistance values. The WMS7110/1 can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications. The output of each potentiometer is determined by the wiper position, which varies in linearly between VA and VB terminal according to the content stored in the volatile Tap Register (TR) which is programmed through Up/Down (Increment/Decrement) interface. The channel has one non-volatile memory location (NVMEM0) that can be directly written to by users through the Up/Down interface. Power-on recall is also built in so the content of the NVMEM0 to Tap Register is automatically loaded. B The WMS7110/1 devices pin out the resistor wiper directly. The WMS7111 devices feature an output buffer with 3mA minimum drive capability. All the WMS7110/1 devices are single channel devices offered in 8-pin PDIP, SOIC and MSOP packages. The WMS7110/1 devices operate over a wide operating voltage ranging from 2.7V to 5.5V. 2. FEATURES • Drop-in replacements for many popular parts • Available output buffer for WMS7111 devices • Single linear-taper channel • 128 taps • 10K, 50K and 100K end-to end resistance • VSS to VDD terminal voltages • Non-volatile storage of wiper positions with power-on recall • Data storage and potentiometer control through Up/Down (3-wire) interface • Endurance 100,000 write cycles • Data retention 100 years • Package options: o 8-pin PDIP, SOIC or MSOP • Industrial temperature range: -40° ~ 85°C • Single supply operation 2.7V to 5.5V -2- WMS7110/1 CS U/D Up/Down Serial VA Decoder INC Tap Register 3. BLOCK DIAGRAM VW VB Interface NV Memory VSS NVMEM0 NV Memory Control VDD CS U/D Up/Down Serial VA Decoder INC Tap Register FIGURE 1 – WMS7110 BLOCK DIAGRAM (Rheostat Mode) VW VB Interface NV Memory VSS NVMEM0 NV Memory Control VDD FIGURE 2 – WMS7111 BLOCK DIAGRAM (Divider Mode) -3- Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM .............................................................................................................................. 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 5 6. PIN DESCRIPTION ............................................................................................................................. 6 7. FUNCTIONAL DESCRIPTION............................................................................................................ 7 7.1. Potentiometer and Rheostat Modes ............................................................................................. 7 7.1.1. Rheostat Configuration .......................................................................................................... 7 7.1.2. Potentiometer Configuration .................................................................................................. 7 7.2. Non-Volatile Memory (NVMEM) ................................................................................................... 7 7.3. Serial Data Interface ..................................................................................................................... 8 7.4. Operation Overview ...................................................................................................................... 8 8. TIMING DIAGRAMS............................................................................................................................ 9 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 11 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 12 10.1 Test Circuits ............................................................................................................................... 14 11. TYPICAL APPLICATION CIRCUITS .............................................................................................. 15 11.1. Layout Considerations .............................................................................................................. 17 12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 18 13. ORDERING INFORMATION........................................................................................................... 21 14. VERSION HISTORY ....................................................................................................................... 22 -4- WMS7110/1 5. PIN CONFIGURATION INC 1 8 VDD U/D 2 7 CS VA 3 6 VB VSS 4 5 VW 8-MSOP INC 1 8 VDD U/D 2 7 CS VA 3 6 VB VSS 4 5 VW 8-SOIC INC 1 8 VDD U/D 2 7 CS VA 3 6 VB VSS 4 5 VW 8-PDIP -5- Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 6. PIN DESCRIPTION TABLE 1 – PIN DESCRIPTION Pin Name I/O INC I Description Increment Control. A High-Low transition of INC when CS is low will move the wiper up or down for one increment based on the U/ D input U/ D I Up/Down control Input. High state will cause the wiper to move to the VB terminal, Low state to the VA terminal B VA - High terminal of WinPot VSS - Ground pin, logic ground reference VDD - Power Supply CS I and the device will be in the standby mode. CS LOW enables the part, placing it in the active power mode VB - Low terminal of WinPot Chip Select. When CS is HIGH, the part is deselected B Wiper terminal of WinPot (can be buffered), its position on VW O the resistor array is controlled by the inputs on INC , U/ D , and CS -6- WMS7110/1 7. FUNCTIONAL DESCRIPTION The WMS7110/1, a nonvolatile digitally programmable potentiometers with 128 taps, with or without output buffer, is designed to operate as both a potentiometer or a variable resistor depending upon the output configuration selected. The chip can store up to one 8-bit word in a nonvolatile memory (NVMEM0) in order to set the tap register value when the device is powered up. The WMS7110/1 is controlled by a serial Up-Down (3-wire) interface that allows setting the tap register value as well as storing data in the nonvolatile memory. 7.1. POTENTIOMETER AND RHEOSTAT MODES The WMS7110/1 can operate as either a rheostat or as a potentiometer (voltage divider). When in the potentiometer configuration there are two possible modes. One is done using WMS7110 Winpot device without the output buffer and the other mode is done with WMS7111 WinPot device with the output buffer. 7.1.1. Rheostat Configuration The WMS7110/1 acts as a two terminal resistive element in the rheostat configuration where one terminal can be connected to either the end point pins of the resistor (VA and VB) and the other terminal is the wiper (VW) pin. This configuration controls the resistance between the two terminals and the resistance can be adjusted by sending the corresponding tap register setting to the WMS7110/1 or can also be set by loading a pre-set tap register value from nonvolatile memory NVMEM0 upon power up. B 7.1.2. Potentiometer Configuration In potentiometer configuration an input voltage is applied to either one of the end point pins (VA or VB). The voltage on the wiper pin will be proportional to the voltage difference between VA and VB and the wiper setting. The resistance cannot be directly measured in this configuration. B B 7.2. NON-VOLATILE MEMORY (NVMEM) The WMS7110/1 has one NVMEM position available for storing the potentiometer setting. The NVMEM position can be directly written via the Up/Down interface. The potentiometer is loaded with the value stored in the NVMEM0 on power up. -7- Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 7.3. SERIAL DATA INTERFACE The Up/Down family has a 3-wire Serial Data Interface consisting of CS , INC , U/ D pins. Only UP/DOWN operations can be performed. The key features of this interface include: • Increment/Decrement operations on the tap register (TR) • Direct refresh of tap register (TR) from internal NVMEM • Nonvolatile storage of the present tap register value into the NVMEM and automatic recall at power up • For WMS7111 devices, output buffer amplifier 7.4. OPERATION OVERVIEW The wiper position or the Tap Register(TR) setting can only be changed by the UP/DOWN operation with the combination of CS , U/ D , and INC signals. When CS is low, the part will be activated and the TR setting can be changed by toggling INC , and TR will move up when U/ D is High and move down when U/ D is Low. The TR setting will be stored into the user NVMEM automatically each time CS goes high while INC holds high. Otherwise, if INC is low when CS goes high, the TR setting will not be stored. The NVMEM content will be automatically loaded into TR at Power On. The user NVMEM can be tested through the voltage measurement on the wiper pin after saving TR setting into the NVMEM and reloading into the TR. When the TR setting is already at LOW, further DOWN operations won’t change the setting. Similarly, when TR setting is at HIGH, further UP operations won’t change the setting. When CS is held HIGH, the part will be in Standby mode and the TR setting will not be changed. The operating modes of Up/Down are summarized below. Operation CS U/ D Low High High to Low Wiper toward VA Low Low High to Low Wiper toward VB INC B Low to High x High Store Wiper Position Low to High x Low No Store, Return to Standby x x Standby High Note: x means don’t care -8- WMS7110/1 8. TIMING DIAGRAMS Conditions: VDD = +2.7V to 5.5V, VA = VDD, VB = 0V, T = 25°C B CS tCYC tCI tIL tIC tIH (store) tCPH 90% INC tF tDI 90% 10% tR tID U/D tIW MI [1] VW FIGURE 3 –WMS7110/1 TIMING DIAGRAM Note: [1] MI in the AC Timing diagram (Figure 3) refers to the minimum incremental change in the wiper output due to a change in the wiper position. -9- Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 TABLE 10 – TIMING PARAMETERS PARAMETERS SYMBOL MIN. MAX. CS to INC Setup tCI 100 ns U/ D to INC Setup tDI 50 ns U/ D to INC Hold tID 100 ns INC LOW Period tIL 250 ns INC HIGH Period tIH 250 ns INC Inactive to CS Inactive tIC 1 μs CS Deselect Time (NO STORE) tCPH 100 ns tCPH 15 (2.7V) ms CS Deselect Time (STORE) INC to VW Change tIW 5 UNITS μs μs INC Cycle Time tCYC INC Input Rise and Fall Time tR, tF 500 μs tPU 1 ms 0.2 50 V/ms (13ms (54μs 0-2.7V) 0-2.7V) Power-Up to Wiper Stable VCC Power-Up rate tR VCC - 10 - 1 WMS7110/1 9. ABSOLUTE MAXIMUM RATINGS TABLE 11 – ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)[1] Conditions Values Junction temperature 150ºC Storage temperature -65º to +150ºC Voltage applied to any pad (Vss – 0.3V) to (VDD + 0.3V) VDD – VSS -0.3 to 7.0V TABLE 12 – OPERATING CONDITIONS (PACKAGED PARTS) Conditions [ 1] Values Commercial operating temperature range 0ºC to +70ºC Extended operating temperature -20ºC to +70ºC Industrial operating temperature -40ºC to +85ºC Supply voltage (VDD) +2.7V to +5.5V Ground voltage (VSS) 0V Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions - 11 - Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 10. ELECTRICAL CHARACTERISTICS TABLE 12 – ELECTRICAL CHARACTERISTICS (Packaged parts) PARAMETERS SYMBOL MIN. R TYP. MAX. UNITS -20 +20 % DNL -1 +1 LSB INL -1 +1 LSB CONDITIONDS Rheostat Mode Nominal Resistance Different Non Linearity Integral Non Linearity Tempo [2] [2] 1 Wiper Resistance [2] T=25ºC, VW open ΔRAB/ΔT 300 ppm/°C RW 50 Ω VDD=5V, I=VDD/RTotal 80 Ω VDD=2.7V, I=VDD/RTotal Wiper Current IW -1 1 mA N 8 DNL -1 ±0.2 +1 LSB INL -1 ±0.1 +1 LSB Divider Mode Resolution Different Non Linearity Integral Non Linearity [2] [2] Temperature Coefficient [1] ΔVw/ΔT Bits +20 ppm/°C Code = 80h Full Scale Error VFSE -1 0 LSB Code = Full Scale Zero Scale Error VZSE 0 1 LSB Code = Zero Scale VA,VB,VW VSS VDD V Resistor Terminal Voltage Range Terminal Capacitance [1] Wiper Capacitance B CA, CB 30 pF 30 pF BW10K 1.5 MHz VDD=5V, VB=VSS BW50K 300 KHz Code = 80h BW100K 200 KHz TS 80 B [1] Dynamic Characteristics [1] Bandwidth –3dB Settling Time to 1 LSB Analog Output (Buffer enables) Amp Output Current IOUT Amp Output Resistance Rout Total Harmonic Distortion [1] 100 3 uS mA 1 THD VIH Input Low Voltage VIL Ω IL = 100uA 0.08 % VA=2.5V, VDD=5V, f=1kHz, VIN=1VRMS 0.7VDD V 0.3VDD - 12 - VO=1/2 scale 10 Digital Inputs/Outputs Input High Voltage B V WMS7110/1 PARAMETERS SYMBOL Output Low Voltage MIN. TYP. VOL MAX. UNITS CONDITIONDS 0.4 V IOL=2mA Input Leakage Current ILI -1 +1 uA CS =VDD,Vin=Vss ~ VDD Output Leakage Current ILo -1 +1 uA CS =VDD,Vin=VSS ~ VDD Input Capacitance [1] Output Capacitance [1] CIN 25 pF VDD=5V, fc = 1Mhz COUT 25 pF VDD=5V, fc = 1Mhz Power Requirements Operating Voltage VDD Operating Current IDDR Operating Current 2.7 5.5 V 0.5 1 mA All ops except NVMEM program IDDW 1 2 mA During Non-volatile memory program ISA [3] 0.5 1 mA Buffer is active, NOP, no load ISB [4] 0.1 1 uA Buffer is inactive, Power Down, No load 1 LSB/V Standby Current Power Supply Rejection Ratio PSRR VDD=5V±10%, Code=80H Notes: [1] Not subject to production test. [2] LSB = (VA - VB) / (T- 1); DNL = (Vi+1 - Vi) / LSB; where i = [0, (T -1)] and T = # of taps of the device. B INL = (Vi - i*LSB) / LSB; [3] WMS71x1 only. [4] WMS71x0 only. - 13 - Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 10.1 TEST CIRCUITS VA VW V+ V+ = VDD 1LSB= V+/256 VA VW V+ VB WMS71xx VMS* B VB WMS71xx VMS* B *Assume infinite input impedance *Assume infinite input impedance Potentiometer divider nonlinearity error test circuit (INL, DNL) Power supply sensitivity test circuit (PSS, PSRR) No Connection VA WMS71xx IW VA V+ = VDD ±10% PSRR(dB) = 20LOG( ΔVMS ) ΔVDD VMS PSS(%/%) = Δ ΔVDD WMS71xx VW B VW W VB +5V VOUT VB VMS * B ~ VIN 2.5V DC Offset *Assume infinite input impedance Resistor position nonlinearity error test circuit (Rheostat Operation: R-INL, R-DNL) Capacitance test circuit VMS* VA VW WMS71xx +5V VA IW = VDD /RTotal IW VIN ~ VW VOUT VB B VB B WMS71xx RW = VMS /IW OFFSET GND 2.5V DC *Assume infinite input impedance Gain vs. frequency test circuit Wiper resistance test circuit FIGURE 4 – TEST CIRCUITS - 14 - WMS7110/1 11. TYPICAL APPLICATION CIRCUITS RA RB Vin WMS71XX _ OP AMP VOUT + VOUT = - VIN RA = RB RA RAB(256 − D) , 256 RB = B R AB D 256 RAB = Total resistance of potentiometer D = Wiper setting for WMS71XX FIGURE 5 – PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7110/1 VIN + OP _ AMP RA VOUT RB B WMS71XX VOUT = VIN (1+ RA = RB ) RA RAB(256 − D) R AB D , RB = 256 256 B RAB = Total resistance of potentiometer D = Wiper setting for WMS71XX FIGURE 6 – PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7110/1 - 15 - Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 V+ I = 32mA VREFH VREF = 5.0v WMS71xx GND FIGURE 7 – WMS7110/1 TRIMMING VOLTAGE REFERENCE VDD L1 CHOKE C1 0.1uF CS\ INC\ U/D\ CS\ U/D\ INC\ VSS VDD VA VW VB RF OUT Q1 FILTER RF POWER AMP WMS71xx WINPOT C2 RF Input FIGURE 8 – WMS7110/1 RF AMP CONTROL - 16 - WMS7110/1 11.1. LAYOUT CONSIDERATIONS Use a 0.1μF bypass capacitor as close as possible to the VDD pin. This is recommended for best performance. Often this can be done by placing the surface mount capacitor on the bottom side of the PC board, directly between the VDD and VSS pins. Care should be taken to separate the analog and digital traces. Sensitive traces should not run under the device or close to the bypass capacitors. A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals. DIGITAL CONTROL LINES ANALOG SIGNAL LINE INC VDD U/D CS CAP VA VB VSS VW DIGITAL CONTROL LINE ANALOG SIGNAL LINES FIGURE 9 – WMS7110/1 LAYOUT - 17 - Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 12. PACKAGE DRAWINGS AND DIMENSIONS 8 5 c E HE L 4 1 0.25 D O A Y e SEATING PLANE GAUGE PLANE A1 b Control demensions are in milmeters . SYMBOL A A1 b c E D e HE Y L θ DIMENSION IN MM MAX. MIN. 1.35 1.75 0.10 0.25 0.51 0.33 0.19 0.25 3.80 4.00 4.80 5.00 1.27 BSC 6.20 5.80 0.10 0.40 1.27 0 10 DIMENSION IN INCH MIN. MAX. 0.053 0.069 0.010 0.004 0.013 0.020 0.008 0.010 0.150 0.157 0.188 0.196 0.050 BSC 0.228 0.016 0 0.244 0.004 0.050 10 FIGURE 10: 8L 150MIL SOIC - 18 - WMS7110/1 D 8 5 E1 4 1 B B 1 E S c A1 A A2 B a s e P la n e S e a tin g P la n e L e1 α S ym b o l A A1 A2 B B1 c D E E1 e1 L α e S D im e n s io n in in c h M in Nom D im e n s io n in m m M in Nom 0 .0 1 0 M ax 4 .4 5 0 .1 7 5 0 .2 5 0 .1 2 5 0 .1 3 0 0 .1 3 5 3 .1 8 3 .3 0 3 .4 3 0 .0 1 6 0 .0 1 8 0 .0 2 2 0 .4 1 0 .4 6 0 .5 6 0 .0 5 8 0 .0 6 0 0 .0 6 4 1 .4 7 1 .5 2 1 .6 3 0 .0 0 8 0 .0 1 0 0 .0 1 4 0 .2 0 0 .2 5 0 .3 6 0 .3 6 0 0 .3 8 0 9 .1 4 9 .6 5 7 .3 7 7 .6 2 7 .8 7 0 .2 9 0 0 .3 0 0 0 .3 1 0 0 .2 4 5 0 .2 5 0 0 .2 5 5 6 .2 2 6 .3 5 6 .4 8 0 .0 9 0 0 .1 0 0 0 .1 1 0 2 .2 9 2 .5 4 2 .7 9 0 .1 2 0 0 .1 3 0 0 .1 4 0 3 .0 5 3 .3 0 3 .5 6 15 0 9 .0 2 9 .5 3 0 A M ax 0 .3 3 5 eA 0 .3 5 5 0 .3 7 5 8 .5 1 0 .0 4 5 15 1 .1 4 FIGURE 11: 8L 300MIL PDIP - 19 - Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 FIGURE 12: 8L 3MM MSOP - 20 - WMS7110/1 13. ORDERING INFORMATION Winbond’s WinPot Part Number Description: WMS71 T B RRR P Winbond WinPot Products w/ Up-Down Interface Number Of Taps: 1 = 128 For Up/Down interface: 0 : No buffer 1 : With buffer End-to-end Resistance: 010: 10Kohm 050: 50Kohm 100: 100Kohm Package: S: SOIC P: PDIP M: MSOP Output Buffer End-to-End Resistance SOIC PDIP MSOP NO 10K WMS7110010S WMS7110010P WMS7110010M 50K WMS7110050S WMS7110050P WMS7110050M 100K WMS7110100S WMS7110100P WMS7110100M 10K WMS7111010S WMS7111010P WMS7111010M 50K WMS7111050S WMS7111050P WMS7111050M 100K WMS7111100S WMS7111100P WMS7111100M YES Notes: Part number with white background: Available for sampling and mass production. Part numbers with shaded background: Call factory for availability. For the latest product information, access Winbond’s worldwide website at http://www.winbond-usa.com - 21 - Publication Release Date: April 21, 2005 Revision 1.1 WMS7110/1 14. VERSION HISTORY VERSION DATE DESCRIPTION 1.0 June 2003 Initial issue 1.1 April 2005 Revise disclaim section - 22 - WMS7110/1 Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. The contents of this document are provided “AS IS”, and Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. In no event, shall Winbond be liable for any damages whatsoever (including, without limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if Winbond has been advised of the possibility of such damages. Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and Winbond makes no representation or warranty that such applications shall be suitable for the use specified. The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond. This product incorporates SuperFlash®. This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD® ChipCorder® product specifications. In the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety. This datasheet is subject to change without notice. Copyright© 2005, Winbond Electronics Corporation. All rights reserved. ChipCorder® and ISD® are trademarks of Winbond Electronics Corporation. SuperFlash® is the trademark of Silicon Storage Technology, Inc. All other trademarks are properties of their respective owners. - 23 - Publication Release Date: April 21, 2005 Revision 1.1