AGERE TSOT0410G4

Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Features
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General
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Section overhead (RSOH) and line overhead
(MSOH) termination, and path overhead monitoring
for one SONET STS-192 (SDH STM-64) or four
STS-48 (STM-16) signals.
Supports any valid combination of STS-1 and
concatenated payloads from STS-3c to STS-192c.
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Microprocessor interface configurable to operate
with most commercial microprocessors.
IEEE ® 1149.1 port with memory built-in self-test
(BIST), scan, and boundary scan (JTAG).
Low-power 2.5 V operation with 3.3 V (5 V tolerant)
inputs and outputs.
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EIA ®-644, IEEE 1596.3 compliant LVDS buffers*.
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600-pin LBGA package.
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–40 °C to +85 °C temperature range.
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STS-192/STM-64 (Line Interface)
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Provides a 16-bit (or 4 × 4-bit) wide, 622 MHz differential line interface.
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Synchronizes to the receive data frames and
detects severely errored framing (SEF) and loss of
frame (LOF). Also inserts the framing bytes (A1 and
A2) in the transmit data.
Supports enhanced framing (A1, A1, A2, A2).
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Performs frame-synchronous scrambling and
descrambling of the STS-192/STS-48 data, and
loss of signal (LOS) is detected.
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Extracts the 64-byte or 16-byte section trace message (J0) from the receive data and optionally
stores it in, or compares it to, an internal register
bank. Unstable or mismatched messages are
detected, and path alarm indication signal (AIS)
may be optionally inserted in the drop data.
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Optionally inserts a 64-byte or 16-byte section trace
message or a fixed pattern in the J0 byte of the
transmit data.
Extracts and outputs, on a serial link, all transport
overhead bytes in the receive data and inserts any,
or all, transport overhead bytes in the transmit data
using a corresponding serial input.
Extracts and outputs, on serial links, the section
user channel (F1), orderwire channels (E1, E2),
and data communication channels (D1—D3 and
D4—D12) for the receive data. Inserts corresponding serial input signals into the transmit data.
Extracts, integrates, and stores the automatic protection switch (APS) channel bytes (K1, K2) for the
receive data and detects protection switch failure
alarms. Inserts APS bytes in the transmit data from
internal registers or from add data overhead bytes.
Detects line alarm indication signal (AIS) and
remote defect indication (RDI) based on the K2
byte of the receive data. Inserts line AIS and RDI in
the transmit data. Optionally inserts line RDI automatically due to LOS, LOF, or line AIS defects.
Extracts, integrates, and stores the synchronization
status byte (S1) for the receive data. Inserts the
synchronization status byte into the transmit data
from an internal register or from a value encoded on
the transmit frame synchronous input.
Calculates, detects, and counts section and line
BIP-8 errors (B1, B2) for the receive data, and
inserts BIP-8 in the transmit data. Supports either
bit or block error accumulation of B1 errors (separately provisionable), and bit error accumulation of
B2 errors.
Extracts and counts line remote errors (REI) for the
receive data (M1), and inserts REI in the transmit
data based on B2 errors.
SS bit mode supports SONET (00) or SDH (10) values and defines the value of the SS bits for
unequipped signal insertion. In normal mode,
SS bits can be passed through or overwritten with a
provisioned value. All SS bit provisioning is done at
a STM-16 level affecting all AU-3s.
The B1 error mask can be extracted serially on the
ROHDAT interface, and the B2 error mask can be
extracted serially on the local orderwire, express
orderwire, and orderwire clock pins.
* Refer to LVDS Receiver Buffer Capabilities section on page 169 for additional details.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Table of Contents
Contents
Page
Features ................................................................................................................................................................... 1
General .................................................................................................................................................................. 1
STS-192/STM-64 (Line Interface).......................................................................................................................... 1
Add/Drop (Equipment Interface) .......................................................................................................................... 12
Applications ............................................................................................................................................................ 12
Description.............................................................................................................................................................. 13
Block Diagrams.................................................................................................................................................... 13
Glossary............................................................................................................................................................... 14
Receive Direction Overview................................................................................................................................. 15
Transmit Direction Overview................................................................................................................................ 15
STS-192 Mode Options ....................................................................................................................................... 16
TOH Transparency............................................................................................................................................ 16
Regenerator Loopback...................................................................................................................................... 16
Device Mode Setup.............................................................................................................................................. 16
Pin Information ....................................................................................................................................................... 17
Functional Description ............................................................................................................................................ 47
Receive STS-192 Line Interface .......................................................................................................................... 47
Loss-of-Signal (LOS) Detector .......................................................................................................................... 47
Framer (A1 and A2)........................................................................................................................................... 48
Descrambler ...................................................................................................................................................... 50
Time-Slot Interchanger (TSI)............................................................................................................................. 50
Receive Transport Overhead (TOH) Processor................................................................................................... 52
Receive Overhead Serial Links ......................................................................................................................... 52
Section Trace (J0) ............................................................................................................................................. 53
Section Growth (Z0) .......................................................................................................................................... 54
Section BIP-8 (B1)............................................................................................................................................. 54
Section BIP-8 (B1) Errors Serial Access ........................................................................................................... 54
Local Orderwire (E1) ......................................................................................................................................... 55
Section User Channel (F1)................................................................................................................................ 55
Section Data Communications Channel (D1, D2, and D3) ............................................................................... 55
Line BIP-8 (B2).................................................................................................................................................. 56
Line BIP-8 (B2) Errors Serial Access ................................................................................................................ 58
APS Channel (K1 and K2)................................................................................................................................. 58
Line Data Communication Channel (D4—D12) ................................................................................................ 60
Synchronization Status (S1).............................................................................................................................. 60
STS-192 Line Remote Error Indication (M1) ..................................................................................................... 61
Express Orderwire (E2)..................................................................................................................................... 61
Receive STS Path Processor .............................................................................................................................. 61
1:4 Demultiplex TSI ........................................................................................................................................... 62
Receive Pointer Processor................................................................................................................................ 62
Receive Path Overhead (POH) Processor........................................................................................................ 69
Receive Payload Drop Interface .......................................................................................................................... 76
STS-12 Overhead Insertion and Scrambling..................................................................................................... 77
Drop Interface Output Format ........................................................................................................................... 78
Data Path Parity ................................................................................................................................................ 79
Regenerator Loopback (STS-192 Mode Only) .................................................................................................... 80
Transmit Payload Add Interface........................................................................................................................... 80
STS-12 Framing, Descrambling, and TOH Processing..................................................................................... 81
Transmit Synchronization Buffer ....................................................................................................................... 82
Add Interface Framing (A1 and A2)................................................................................................................... 82
4:1 Time-Slot Multiplex (TSM)........................................................................................................................... 84
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Agere Systems Inc.
Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Table of Contents (continued)
Contents
Page
Transmit Transport Overhead (TOH) Processor.................................................................................................. 84
TOH Transparency............................................................................................................................................ 85
Transmit Overhead Serial Links ........................................................................................................................ 86
Section Trace/Section Growth (J0/Z0) .............................................................................................................. 86
Section BIP-8 (B1)............................................................................................................................................. 87
Local Orderwire (E1) ......................................................................................................................................... 87
Section User Channel (F1)................................................................................................................................ 87
Section Data Communications Channel (D1, D2, and D3) ............................................................................... 88
STS Payload Pointer (H1 and H2) .................................................................................................................... 88
Line BIP-8 (B2).................................................................................................................................................. 89
APS Channel (K1 and K2)................................................................................................................................. 90
Line Data Communication Channel (D4—D12) ................................................................................................ 90
Synchronization Status (S1).............................................................................................................................. 91
STS-192 Line Remote Error Indication (M1) ..................................................................................................... 91
Express Orderwire (E2)..................................................................................................................................... 92
Transmit STS-192 Line Interface ......................................................................................................................... 92
Time-Slot Multiplexer (TSM).............................................................................................................................. 92
Scrambler .......................................................................................................................................................... 92
Data Path Parity ................................................................................................................................................ 92
Microprocessor Interface ........................................................................................................................................ 93
Architecture.......................................................................................................................................................... 93
Transfer Error Acknowledge (TEA_N)............................................................................................................... 93
Interrupt Structure ............................................................................................................................................. 93
Parity Bits .......................................................................................................................................................... 94
Clock Domains .................................................................................................................................................. 94
Persistency Registers .......................................................................................................................................... 96
Register Description............................................................................................................................................. 96
Software Reset .................................................................................................................................................... 96
Device-Level Registers ...................................................................................................................................... 110
Line Terminating Equipment (LTE) Registers.................................................................................................... 115
LTE Common Registers .................................................................................................................................. 115
LTE J0 Access Registers ................................................................................................................................ 117
Signal Degrade/Signal Fail Registers.............................................................................................................. 119
LTE Receive Channel 1, 2, 3, and 4 Registers ............................................................................................... 122
LTE Transmit Common Registers...................................................................................................................... 128
LTE Transmit Channel Registers .................................................................................................................... 130
Equipment (EQPT) Registers ............................................................................................................................ 134
EQPT Common Registers............................................................................................................................... 134
EQPT Receive Drop STS-48 Channel Registers 1—4 ................................................................................... 137
EQPT Transmit Add STS-48 Channel Registers 1—4.................................................................................... 139
Path Overhead (POH) Registers ....................................................................................................................... 144
STS-12, STS-1 Level POH Registers ............................................................................................................. 145
STS-192 Level POH Registers........................................................................................................................ 149
STS-192 Level Path Trace Registers.............................................................................................................. 154
STS-48 Level POH Registers.......................................................................................................................... 155
Absolute Maximum Ratings.................................................................................................................................. 166
Handling Precautions ........................................................................................................................................... 166
Recommended Operating Conditions .................................................................................................................. 166
Electrical Characteristics ...................................................................................................................................... 167
Power Sequencing............................................................................................................................................. 167
Low-Voltage Differential Signal (LVDS) Buffers................................................................................................. 167
Agere Systems Inc.
3
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Table of Contents (continued)
Contents
Page
LVDS Receiver Buffer Capabilities.................................................................................................................. 169
Timing Characteristics .......................................................................................................................................... 172
Receive Data Interface ...................................................................................................................................... 172
Receive STS-48/STS-192 Data ...................................................................................................................... 172
Receive Transport Overhead Interface.............................................................................................................. 173
Receive Local Orderwire ................................................................................................................................. 173
Receive Section User...................................................................................................................................... 173
Receive Express Orderwire............................................................................................................................. 174
Receive Section Data Com ............................................................................................................................. 174
Receive Line Data Com .................................................................................................................................. 174
Receive Overhead Serial Link......................................................................................................................... 175
Transmit Data Interface ..................................................................................................................................... 176
Transmit STS-48/STS-192 Data ..................................................................................................................... 176
Transmit Frame ............................................................................................................................................... 177
Transmit Transport Overhead Interface............................................................................................................. 178
Transmit Local Orderwire ................................................................................................................................ 178
Transmit Section User..................................................................................................................................... 178
Transmit Express Orderwire............................................................................................................................ 178
Transmit Section Data Com ............................................................................................................................ 179
Transmit Line Data Com ................................................................................................................................. 179
Transmit Overhead Serial Link........................................................................................................................ 180
Receive Drop Interface ...................................................................................................................................... 181
Drop Clock, Drop Frame, and Drop Data ........................................................................................................ 181
Receive Drop Section Data Com .................................................................................................................... 182
Transmit Add Interface....................................................................................................................................... 183
Transmit Add Data .......................................................................................................................................... 183
Transmit Add Section Data Com..................................................................................................................... 183
Microprocessor Interface Timing........................................................................................................................ 183
Synchronous Mode ......................................................................................................................................... 183
Asynchronous Mode........................................................................................................................................ 186
Use of a Synchronous Microprocessor with the TSOT0410G4 in Asynchronous Mode ................................. 188
Outline Diagram.................................................................................................................................................... 189
600-Pin LBGA .................................................................................................................................................... 189
Ordering Information............................................................................................................................................. 190
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
List of Figures
Contents
Page
Figure 1. TSOT0410G4 Block Diagram, STS-192 Mode ...................................................................................... 13
Figure 2. TSOT0410G4 Block Diagram, STS-48 Mode ........................................................................................ 14
Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages ............................................................. 35
Figure 4. Framer FSM ........................................................................................................................................... 49
Figure 5. Example of STS-192 SD Detection (10–5 BER) and Clearing (10–6 BER) ............................................. 57
Figure 6. Timing Diagram for RFRM ..................................................................................................................... 60
Figure 7. Pointer Interpreter State Machine .......................................................................................................... 63
Figure 8. STS-12 Data Outputs and Timing .......................................................................................................... 79
Figure 9. TSOT0410G4 Timing Domains .............................................................................................................. 95
Figure 10. Persistency Register Operation ............................................................................................................ 96
Figure 11. Path Register Structure ...................................................................................................................... 144
Figure 12. LVDS Driver and Receiver and Associated Internal Components ..................................................... 168
Figure 13. LVDS Driver and Receiver ................................................................................................................. 168
Figure 14. LVDS Driver ....................................................................................................................................... 168
Figure 15. Receive Data Timing .......................................................................................................................... 172
Figure 16. Receive Data Communication Channels Timing ................................................................................ 173
Figure 17. Receive Overhead Serial Timing ........................................................................................................ 175
Figure 18. Transmit Data Timing ......................................................................................................................... 176
Figure 19. Transmit Frame Timing ...................................................................................................................... 177
Figure 20. Transmit Data Communication Channels Timing ............................................................................... 178
Figure 21. Transmit Overhead Serial Timing ....................................................................................................... 180
Figure 22. Receive Frame Timing (Pointer Processor Bypassed) ...................................................................... 181
Figure 23. Receive Frame Timing (Pointer Processor Active) ............................................................................ 182
Figure 24. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1) ................................................. 184
Figure 25. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1) ................................................. 185
Figure 26. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0) ............................................... 186
Figure 27. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0) ............................................... 187
Agere Systems Inc.
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
List of Tables
Contents
Page
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order....................................................................... 17
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order ..................................................................... 22
Table 3. Pin Descriptions—System Control ........................................................................................................... 26
Table 4. Pin Descriptions—Receive Line Interface ................................................................................................ 27
Table 5. Pin Descriptions—Transmit Line Interface ............................................................................................... 28
Table 6. Pin Descriptions—LVDS Reference, Line Interface ................................................................................. 30
Table 7. Pin Descriptions—Receive Drop Equipment Interface ............................................................................. 31
Table 8. Pin Descriptions—Transmit Add Equipment Interface ............................................................................. 33
Table 9. Pin Descriptions—LVDS Reference, Equipment Interface....................................................................... 35
Table 10. Pin Descriptions—Transport Overhead Interface................................................................................... 36
Table 11. Pin Descriptions—Microprocessor Interface .......................................................................................... 42
Table 12. Pin Descriptions—JTAG Interface.......................................................................................................... 43
Table 13. Pin Descriptions—PLL References ........................................................................................................ 44
Table 14. Pin Descriptions—Power and Ground.................................................................................................... 44
Table 15. Pin Summary .......................................................................................................................................... 46
Table 16. LOS Detector Register Summary ........................................................................................................... 48
Table 17. Framer Register Summary ..................................................................................................................... 50
Table 18. Descrambler Register Summary ............................................................................................................ 50
Table 19. STS-192 Byte Ordering .......................................................................................................................... 51
Table 20. STS-48 Byte Ordering ............................................................................................................................ 51
Table 21. Receive Overhead Serial Links Register Summary ............................................................................... 52
Table 22. J0 Register Summary ............................................................................................................................. 54
Table 23. B1 Register Summary ............................................................................................................................ 55
Table 24. BER Threshold Time and Error Limits for Line SD and SF Detection .................................................... 56
Table 25. B2 Register Summary ............................................................................................................................ 58
Table 26. APS Channel (K1 and K2) Register Summary ....................................................................................... 59
Table 27. Synchronization Status (S1) Register Summary .................................................................................... 61
Table 28. Line REI (M1) Register Summary........................................................................................................... 61
Table 29. STS-12 Byte Ordering ............................................................................................................................ 62
Table 30. Pointer Interpreter Register Summary.................................................................................................... 64
Table 31. Elastic Store Register Summary............................................................................................................. 65
Table 32. Pointer Generator Bypass Register Summary ....................................................................................... 65
Table 33. AIS-P Insertion Conditions ..................................................................................................................... 66
Table 34. Path AIS Insertion Register Summary.................................................................................................... 67
Table 35. Concatenation Register Summary.......................................................................................................... 68
Table 36. Pointer Justification Binning Register Summary..................................................................................... 68
Table 37. J1 Register Summary ............................................................................................................................. 70
Table 38. BER Threshold Time Window and Error Limits for Path SF Detection................................................... 71
Table 39. Time Window Sizes for Path SF Detection............................................................................................. 71
Table 40. B3 Register Summary ............................................................................................................................ 72
Table 41. STS Path Signal Label Assignments...................................................................................................... 73
Table 42. Path Signal Label (C2) Alarm Scenarios ................................................................................................ 74
Table 43. C2 Register Summary ............................................................................................................................ 75
Table 44. RDI-P Codes and Interpretation ............................................................................................................. 76
Table 45. G1 Register Summary ............................................................................................................................ 76
Table 46. Path Alarm Information Encoding........................................................................................................... 77
Table 47. Line Alarm Information Encoding ........................................................................................................... 78
Table 48. Drop Interface Overhead and Scrambling Register Summary ............................................................... 78
Table 49. Timing Enable Bit Definitions.................................................................................................................. 79
Table 50. Receive Data Path Parity Register Summary......................................................................................... 79
Table 51. LTE Transmit Channel Registers—Regenerator Loopback Summary................................................... 80
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Agere Systems Inc.
Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
List of Tables (continued)
Contents
Page
Table 52. Regenerator Loopback Bit Definitions .................................................................................................... 80
Table 53. Path AIS Insertion Encoding................................................................................................................... 81
Table 54. Add Interface Overhead and Scrambling Register Summary................................................................. 82
Table 55. Transmit Synchronization Buffer Register Summary.............................................................................. 82
Table 56. Frame Pulse Provisioning Bit Definitions................................................................................................ 84
Table 57. Transmit Framing Register Summary..................................................................................................... 84
Table 58. LTE Transmit Channel Registers—TOH Transparency Summary ......................................................... 85
Table 59. TOH Transparency Bit Definitions .......................................................................................................... 85
Table 60. Transmit Overhead Serial Links Register Summary .............................................................................. 86
Table 61. Transmit Section Trace (J0) Register Summary .................................................................................... 87
Table 62. Transmit B1 Register Summary ............................................................................................................. 87
Table 63. Transmit STS Payload Pointer Register Summary ................................................................................ 89
Table 64. Transmit B2 Register Summary ............................................................................................................. 89
Table 65. K Byte Select Control Bits ...................................................................................................................... 90
Table 66. Transmit APS Channel (K1K2) Register Summary ................................................................................ 90
Table 67. Transmit Synchronization Status (S1) Register Summary ..................................................................... 91
Table 68. Transmit M1 Register Summary............................................................................................................. 91
Table 69. Transmit Line Scrambler Register Summary.......................................................................................... 92
Table 70. Transmit Data Path Parity Register Summary........................................................................................ 92
Table 71. Register Summary.................................................................................................................................. 97
Table 72. Interrupt Status (RO) ............................................................................................................................ 110
Table 73. Interrupt Status Mask (R/W) ................................................................................................................. 111
Table 74. Chip ID (RO)......................................................................................................................................... 111
Table 75. Chip Vintage (RO) ................................................................................................................................ 111
Table 76. Scratch Pad, Clock Loss Alarm (R/W).................................................................................................. 112
Table 77. Chip-Level Maintenance (R/W) ............................................................................................................ 112
Table 78. Chip Status (RO) .................................................................................................................................. 112
Table 79. Clock Loss Alarm/PM Clock Detection (W1C)...................................................................................... 113
Table 80. Clock Loss Alarm/PM Clock Detection Mask (R/W) ............................................................................. 114
Table 81. Software Chip Reset (WO) ................................................................................................................... 114
Table 82. LTE Interrupt Status (RO)..................................................................................................................... 115
Table 83. LTE Interrupt Status Mask (R/W) ......................................................................................................... 116
Table 84. Section Trace (J0) Access Maintenance (R/W).................................................................................... 117
Table 85. J0 Access Done (W1C) ........................................................................................................................ 118
Table 86. J0 Access Message Start (WO) ........................................................................................................... 118
Table 87. J0 Access Message Buffers 1—32 (R/W) ............................................................................................ 118
Table 88. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–3) (R/W) ................................ 119
Table 89. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–4) (R/W) ................................ 119
Table 90. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–5) (R/W) ................................ 119
Table 91. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–6) (R/W) ................................ 119
Table 92. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–7) (R/W) ................................ 119
Table 93. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–8) (R/W) ................................ 120
Table 94. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–9) (R/W) ................................ 120
Table 95. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–10) (R/W) ............................... 120
Table 96. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–3) (R/W) ................................................... 120
Table 97. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–4) (R/W) ................................................... 120
Table 98. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–5) (R/W) ................................................... 120
Table 99. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–6) (R/W) ................................................... 121
Table 100. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–7) (R/W) ................................................. 121
Table 101. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–8) (R/W) ................................................. 121
Table 102. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–9) (R/W) ................................................. 121
Agere Systems Inc.
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
List of Tables (continued)
Contents
Page
Table 103. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–4) (R/W) ................................................... 121
Table 104. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–5) (R/W) ................................................... 121
Table 105. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–6) (R/W) ................................................... 121
Table 106. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–7) (R/W) ................................................... 122
Table 107. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–8) (R/W) ................................................... 122
Table 108. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–9) (R/W) ................................................... 122
Table 109. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–10) (R/W).................................................. 122
Table 110. LTE Receive Channel 1 Provisioning (R/W)....................................................................................... 122
Table 111. LTE Receive Channel 1 Maintenance (R/W)...................................................................................... 123
Table 112. LTE Receive Channel 1 Loss-of-Signal (LOS) Threshold (R/W)........................................................ 123
Table 113. LTE Receive Channel 1 K Byte Status (RO) ...................................................................................... 123
Table 114. LTE Receive Channel 1 S1 Byte Status (RO) .................................................................................... 123
Table 115. LTE Receive Channel 1 Service-Affecting Interrupt Alarm (W1C) ..................................................... 124
Table 116. LTE Receive Channel 1 Service-Affecting Interrupt Alarm Mask (R/W)............................................. 124
Table 117. LTE Receive Channel 1 Service-Affecting Persistency Alarm (RO)................................................... 124
Table 118. LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C) ............................................... 125
Table 119. LTE Receive Channel 1 Nonservice-Affecting Interrupt Mask (R/W) ................................................. 126
Table 120. LTE Receive Channel 1 Nonservice-Affecting Persistency Alarm (RO)............................................. 127
Table 121. LTE Receive Channel 1 Performance Monitoring (RO) ..................................................................... 127
Table 122. LTE Receive Channel 1 REI-L Performance Monitoring (L) (RO)...................................................... 127
Table 123. LTE Receive Channel 1 REI-L Performance Monitoring (U) (RO) ..................................................... 127
Table 124. LTE Receive Channel 1 CV-L Performance Monitoring (L) (RO)....................................................... 127
Table 125. LTE Receive Channel 1 CV-L Performance Monitoring (U) (RO) ...................................................... 127
Table 126. LTE Receive Channel 1 CV-S Performance Monitoring (RO)............................................................ 128
Table 127. LTE Transmit—Frame Pulse Offset Count (R/W) .............................................................................. 128
Table 128. LTE Transmit—Add Interface Self-Sync Option (R/W)....................................................................... 128
Table 129. LTE Transmit—B1 Corrupt Frame Count (R/W)................................................................................. 128
Table 130. LTE Transmit—B2 Corrupt Frame Count (R/W)................................................................................. 128
Table 131. LTE Transmit—M1 Corrupt Frame Count (R/W) ................................................................................ 129
Table 132. LTE Transmit—TFRM S1 Byte (RO) .................................................................................................. 129
Table 133. LTE Transmit—Interrupt Alarm Register (W1C)................................................................................. 129
Table 134. LTE Transmit—Interrupt Mask Register (R/W)................................................................................... 130
Table 135. LTE Transmit Channel 1 Provisioning (R/W)...................................................................................... 130
Table 136. LTE Transmit Bit Assignment ............................................................................................................. 131
Table 137. LTE Transmit Channel 1 Maintenance (R/W)..................................................................................... 131
Table 138. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #1 (R/W)................................. 131
Table 139. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #2 (R/W)................................. 131
Table 140. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #3 (R/W)................................. 131
Table 141. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #4 (R/W)................................. 132
Table 142. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #1 (R/W) ................................................... 132
Table 143. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #2 (R/W) ................................................... 132
Table 144. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #3 (R/W) ................................................... 132
Table 145. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #4 (R/W) ................................................... 132
Table 146. LTE Transmit Channel 1 K1K2 Byte Insert Values (R/W) .................................................................. 132
Table 147. LTE Transmit Channel 1 S1 Byte Insert Value (R/W) ........................................................................ 132
Table 148. LTE Transmit Channel 1 Interrupt Alarm (W1C) ................................................................................ 133
Table 149. LTE Transmit Channel 1 Interrupt Alarm Mask (R/W)........................................................................ 133
Table 150. EQPT Interrupt Status (RO) ............................................................................................................... 134
Table 151. EQPT Interrupt Mask (R/W) ............................................................................................................... 135
Table 152. Receive Drop Common Service-Affecting Alarm (W1C) .................................................................... 136
Table 153. Receive Drop Common Service-Affecting Alarm Mask (R/W)............................................................ 136
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Agere Systems Inc.
Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
List of Tables (continued)
Contents
Page
Table 154. Receive Drop STS-48 Channel Provisioning Register 1 (R/W).......................................................... 137
Table 155. J0 Trace—STS-12 Channel 1 (R/W) .................................................................................................. 137
Table 156. J0 Trace—STS-12 Channel 2 (R/W) .................................................................................................. 137
Table 157. J0 Trace—STS-12 Channel 3 (R/W) .................................................................................................. 137
Table 158. J0 Trace—STS-12 Channel 4 (R/W) .................................................................................................. 137
Table 159. Receive Drop STS-48 Channel Nonservice-Affecting Alarm (W1C) .................................................. 138
Table 160. Receive Drop STS-48 Channel Nonservice Affecting Alarm Mask (R/W).......................................... 138
Table 161. Transmit Add STS-48 Channel Provisioning (R/W)............................................................................ 139
Table 162. J0 Status Register—1 (RO)................................................................................................................ 139
Table 163. J0 Status Register—2 (RO)................................................................................................................ 139
Table 164. J0 Status Register—3 (RO)................................................................................................................ 139
Table 165. J0 Status Register—4 (RO)................................................................................................................ 139
Table 166. AIS Insert Status Register, STS-12 Channel #1 (RO)........................................................................ 140
Table 167. AIS Insert Status Register, STS-12 Channel #2 (RO)........................................................................ 140
Table 168. AIS Insert Status Register, STS-12 Channel #3 (RO)........................................................................ 141
Table 169. AIS Insert Status Register, STS-12 Channel #4 (RO)........................................................................ 141
Table 170. Transmit Add STS-48 Channel Alarm (W1C)..................................................................................... 142
Table 171. Transmit Add STS-48 Channel Alarm Mask (R/W) ............................................................................ 143
Table 172. STS-12 Pointer Processor Provisioning, STS-1 #1 to STS-1 #12 (R/W) ........................................... 145
Table 173. STS-12 Pointer Processor Maintenance, STS-1 #1 to STS-1 #12 (R/W) .......................................... 145
Table 174. STS-12 Pointer Interpreter PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO) .................. 145
Table 175. STS-12 Pointer Interpreter PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO) ................ 146
Table 176. STS-12 Pointer Generator PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO) .................. 146
Table 177. STS-12 Pointer Generator PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO)................. 146
Table 178. STS-1 #1 Path Overhead Provisioning (R/W) .................................................................................... 146
Table 179. STS-1 #1 Path Overhead Maintenance (R/W) ................................................................................... 146
Table 180. STS-1 #1 Path Overhead Status (RO) ............................................................................................... 147
Table 181. STS-1 #1 Alarm Interrupt Status (W1C) ............................................................................................. 147
Table 182. STS-1 #1 Alarm Interrupt Status Mask (R/W) .................................................................................... 147
Table 183. STS-1 #1 Alarm Persistency (RO)...................................................................................................... 148
Table 184. STS-1 #1 PM Last Second Indicators (RO)........................................................................................ 148
Table 185. STS-1 #1 Last Second CV-P Count (RO) .......................................................................................... 148
Table 186. STS-1 #1 Last Second REI-P Count (RO) ......................................................................................... 148
Table 187. Path Overhead (POH) Interrupt Status (RO)...................................................................................... 149
Table 188. Path Overhead (POH) Interrupt Status Mask (R/W)........................................................................... 149
Table 189. STS-1 Signal Fail Detect Threshold, Window Size Select 0 (R/W) .................................................... 150
Table 190. STS-1 Signal Fail Clear Threshold, Window Size Select 0 (R/W)...................................................... 150
Table 191. STS-1 Signal Fail Detect Threshold, Window Size Select 1 (R/W) .................................................... 150
Table 192. STS-1 Signal Fail Clear Threshold, Window Size Select 1 (R/W)...................................................... 150
Table 193. STS-Nc Signal Fail Detect Threshold, Window Size Select 2 (R/W).................................................. 151
Table 194. STS-Nc Signal Fail Clear Threshold, Window Size Select 2 (R/W) ................................................... 151
Table 195. STS-Nc Signal Fail Detect Threshold, Window Size Select 3 (R/W).................................................. 151
Table 196. STS-Nc Signal Fail Clear Threshold, Window Size Select 3 (R/W) ................................................... 151
Table 197. STS-Nc Signal Fail Detect Threshold, Window Size Select 4 (R/W).................................................. 152
Table 198. STS-Nc Signal Fail Clear Threshold, Window Size Select 4 (R/W) ................................................... 152
Table 199. STS-Nc Signal Fail Detect Threshold, Window Size Select 5 (R/W).................................................. 152
Table 200. STS-Nc Signal Fail Clear Threshold, Window Size Select 5 (R/W) ................................................... 152
Table 201. STS-Nc Signal Fail Detect Threshold, Window Size Select 6 (R/W).................................................. 152
Table 202. STS-Nc Signal Fail Clear Threshold, Window Size Select 6 (R/W) ................................................... 152
Table 203. STS-Nc Signal Fail Detect Threshold, Window Size Select 7 (R/W).................................................. 153
Table 204. STS-Nc Signal Fail Clear Threshold, Window Size Select 7 (R/W) ................................................... 153
Agere Systems Inc.
9
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
List of Tables (continued)
Contents
Page
Table 205. Signal Fail Window Size 0 (R/W)........................................................................................................ 153
Table 206. Signal Fail Window Size 1 (R/W)........................................................................................................ 153
Table 207. Signal Fail Window Size 2 (R/W)........................................................................................................ 153
Table 208. Signal Fail Window Size 3 (R/W)........................................................................................................ 153
Table 209. Path Trace Access Control (R/W) ...................................................................................................... 154
Table 210. Path Trace Access Complete Status (W1C) ...................................................................................... 154
Table 211. Path Trace Access Start..................................................................................................................... 154
Table 212. Path Trace Buffer Word #1—Word #32.............................................................................................. 154
Table 213. STS-1 Channel Interrupt Status, STS-1 #1 to STS-1 #16 (RO) ......................................................... 155
Table 214. STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (R/W) .............................................. 155
Table 215. STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (RO) ....................................................... 157
Table 216. STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (R/W) ............................................ 158
Table 217. STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (RO) ....................................................... 159
Table 218. STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (R/W) ............................................ 160
Table 219. STS-48 Channel Path Trace Control (R/W) ....................................................................................... 161
Table 220. S/W Concatenation Map STS-1 #1 to STS-1 #12 (R/W).................................................................... 161
Table 221. S/W Concatenation Map STS-1 #13 to STS-1 #24 (R/W).................................................................. 161
Table 222. S/W Concatenation Map STS-1 #25 to STS-1 #36 (R/W).................................................................. 162
Table 223. S/W Concatenation Map STS-1 #37 to STS-1 #48 (R/W).................................................................. 162
Table 224. S/W Concatenation Mask STS-1 #1 to STS-1 #12 (R/W) .................................................................. 162
Table 225. S/W Concatenation Mask STS-1 #13 to STS-1 #24 (R/W) ................................................................ 162
Table 226. S/W Concatenation Mask STS-1 #25 to STS-1 #36 (R/W) ................................................................ 162
Table 227. S/W Concatenation Mask STS-1 #37 to STS-1 #48 (R/W) ................................................................ 163
Table 228. Received Concatenation Map STS-1 #1 to STS-1 #12 (RO) ............................................................. 163
Table 229. Received Concatenation Map STS-1 #13 to STS-1 #24 (RO) ........................................................... 163
Table 230. Received Concatenation Map STS-1 #25 to STS-1 #36 (RO) ........................................................... 163
Table 231. Received Concatenation Map STS-1 #37 to STS-1 #48 (RO) ........................................................... 163
Table 232. STS-48 Channel Path Alarms 1 (W1C) .............................................................................................. 164
Table 233. STS-48 Channel Path Alarms 1 Mask (W1C) .................................................................................... 165
Table 234. Absolute Maximum Ratings................................................................................................................ 166
Table 235. Recommended Operating Conditions ................................................................................................ 166
Table 236. Thermal Resistance—Junction to Ambient ........................................................................................ 167
Table 237. LVDS Driver dc Data .......................................................................................................................... 169
Table 238. LVDS Driver ac Data .......................................................................................................................... 169
Table 239. LVDS Driver Reference Data ............................................................................................................. 170
Table 240. LVDS Receiver Data .......................................................................................................................... 170
Table 241. Receive Payload Add Interface .......................................................................................................... 170
Table 242. Receive Payload Drop Interface......................................................................................................... 171
Table 243. LVTTL 3.3 V Logic Interface Characteristics ...................................................................................... 171
Table 244. Receive Data Timing .......................................................................................................................... 172
Table 245. RLCLOW/RSUSER/REXPOW Timing ............................................................................................... 174
Table 246. RSDCC Timing ................................................................................................................................... 174
Table 247. RLDCC Timing ................................................................................................................................... 174
Table 248. Receive Overhead Serial Timing........................................................................................................ 175
Table 249. Transmit Data Timing ......................................................................................................................... 176
Table 250. Transmit Frame Timing ...................................................................................................................... 177
Table 251. TLCLOW/TSUSER/TEXPOW Timing................................................................................................. 178
Table 252. TSDCC Timing ................................................................................................................................... 179
Table 253. TLDCC Timing.................................................................................................................................... 179
Table 254. Transmit Overhead Serial Timing....................................................................................................... 181
Table 255. Drop Frame Timing (Pointer Processor Bypassed)............................................................................ 181
10
Agere Systems Inc.
Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
List of Tables (continued)
Contents
Page
Table 256. Drop Frame Timing (Pointer Processor Active).................................................................................. 182
Table 257. RDDCC Timing................................................................................................................................... 182
Table 258. TADCC Timing ................................................................................................................................... 183
Table 259. TA_N/TEA_N Cycle Termination for Synchronous Write Cycle ......................................................... 184
Table 260. Microprocessor Interface Synchronous Write Cycle Specifications ................................................... 184
Table 261. TA_N/TEA_N Cycle Termination for Synchronous Read Cycle ......................................................... 185
Table 262. Microprocessor Interface Synchronous Read Cycle Specifications ................................................... 185
Table 263. Microprocessor Interface Asynchronous Write Cycle Specifications.................................................. 186
Table 264. TA_N/TEA_N Cycle Termination for Asynchronous Write Cycle ....................................................... 187
Table 265. TA_N/TEA_N Cycle Termination for Asynchronous Read Cycle ....................................................... 187
Table 266. Microprocessor Interface Asynchronous Read Cycle Specifications ................................................. 187
Agere Systems Inc.
11
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Features (continued)
Add/Drop (Equipment Interface)
■
■
■
■
■
■
■
■
■
■
Data Sheet
May 2003
■
■
Provides sixteen 1-bit serial 622 MHz (STS-12 rate)
differential data links at the add and drop interfaces.
Path overhead and SPE timing indication is provided
by the drop interface.
Clock recovery and data skew compensation are
provided at the add interface. Transmit frame
alignment synchronization may be controlled via an
input (TFRM), or may optionally derived from any one
of sixteen add inputs.
■
Interprets the pointer bytes (H1, H2) for each receive
STS and detects loss of pointer (LOP) and path AIS.
Generates new pointer bytes in each drop STS to
adapt the receive data to the drop frequency and
phase. Pointer generation can be bypassed for
synchronous applications.
Optionally inserts path AIS in all drop STS pointer
bytes during LOS, LOF, SEF, or line AIS (MS-AIS)
defects. Optionally inserts path AIS in each drop STS
due to LOP or path AIS defects in the corresponding
receive STS, or under software control.
■
■
Inserts pointer bytes in the transmit data based on
values received in the transport overhead bytes of
the add data. Optionally inserts path AIS in each
transmit STS under control by software, or through
bits in the transport overhead of the add data.
Extracts the 64-byte or 16-byte path trace message
(J1) from up to four selectable receive STS channels
(one per STS-48), and stores it in an internal register
bank. Optionally compares the message to an
expected message stored in the internal register
bank and detects an unstable or mismatched
message.
Calculates, detects, and accumulates path BIP-8
errors (B3) for each receive STS (provisionable
based on bit or block errors). Provides signal fail
detection with provisionable BER.
Outputs path alarm information for each receive STS
in the overhead bytes of the drop data (E1/F1).
Optional TOH transparency capability on the line
interface to/from the TOH on the equipment interface.
Either full TOH transparency, or just line overhead
(MSOH) transparency with section overhead (RSOH)
insertion/extraction, may be selected. In the receive
direction, the section overhead will be used for path
alarm information if section overhead transparency is
not selected. The pointer processor will be
automatically bypassed if any of these options are
selected.
Optional loopback of the receive data and overhead
towards the transmit line interface in STS-192 mode.
The transmit clock is replaced by the receive clock at
the 622 MHz level external to the chip, with the add
interface buffers used to align the data between the
receive and transmit clock domains. The TFRM
signal is replaced by receive frame timing to transfer
from the receive to the transmit clock domains.
Active per-STS-48 transmit line AIS insert controls
during receive LOS, receive LOF, or R_CLK failure
while in regenerator loopback mode.
The add interface self-sync provides the option to use
frame timing being recovered from one of the add
pseudo-STS-12 links as the transmit frame sync
instead of TFRM. The resynchronizing is inhibited if
the selected add pseudo-STS-12 link is out of frame
(OOF).
Applications
■
SONET/SDH add/drop multiplex equipment.
■
SONET/SDH terminal equipment.
■
SONET/SDH digital cross connect equipment.
■
SONET/SDH regenerator equipment.
■
SONET/SDH test equipment.
■
ATM or packet over SONET/SDH equipment.
Extracts and counts path REI for each receive STS
(G1).
Detects path unequipped, payload label mismatch
(PLM), and optionally, payload defect indication (PDI)
in the C2 byte of each receive STS. Optionally inserts
unequipped signal in each transmit STS under
software control.
Detects 1-bit and enhanced path RDI (3-bit) in each
receive STS (G1).
12
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Description
The TSOT0410G4 is used to terminate the transport overhead in a single SONET STS-192 (SDH STM-64) signal
or four SONET STS-48 (SDH STM-16) signals. It monitors the STS path pointers and overhead in the receive data
and provides timing signals for payload mapping devices on the equipment side. The TSOT0410G4 can be
provisioned to support any mix of STS-1 (AU-3) or STS-Nc (AU-4-Xc) payloads from a single STS-192c
(AU-4-64c) channel to 192 STS-1 (AU-3) channels. Block diagrams are shown in Figure 1 and Figure 2.
The TSOT0410G4 is a 2.5 V, 0.25 µm high-density device which is packaged in a 600-pin laminate ball grid array
(LBGA). The I/O circuitry uses a 3.3 V, 0.25 µm technology (5 V tolerant) for LVTTL, and LVDS for high-speed
signals.
The microprocessor interface allows an external processor to access the TSOT0410G4 for configuration and
maintenance. The microprocessor interface is designed to support various 16-bit microprocessors with minimal
glue logic.
The TSOT0410G4 includes an IEEE 1149.1 compliant JTAG port to support boundary scan and memory BIST
testing of the device.
Block Diagrams
MPMODE
PM_CLK
INT_N
TEA_N
TA_N
RW_N
DS_N
TS_N
CS_N
ADDRESS_[15:0]
DATA_[15:0]
PCLK
PARITY_[1:0]
TOH_CLK_[1—4]
TOW_CLK_[1—4]
TSD_CLK_[1—4]
TLD_CLK_[1—4]
TOHEN_[1—4]
TOHFP_[1—4]
TLDCC_[1—4]
TOHDAT_[1—4]_[1:0]
TSUSER_[1—4]
TSDCC_[1—4]
TLCLOW_[1—4]
TEXPOW_[1—4]
Figure 1, below, is a block diagram of the TSOT0410G4 when operating in STS-192 mode (pin AM17,
STS_MODE = 0). Figure 2 on page 14 is a block diagram of the TSOT0410G4 when operating in quad STS-48
mode (pin AM17, STS_MODE = 1). For convenience, two symbol sets are provided for the transmit and receive
line interface pins, based on the mode of the device. Both sets of symbols are included in the pin tables.
TFRM
T_CLK
MICROPROCESSOR INTERFACE
RST_N
TD[15:0]
T_CLKO_1
X4
X4
TRANSMIT
STS-48 TRANSMIT
STS-192 TRANSPORT
OVERHEAD
LINE
PROCESSOR
INTERFACE
HIZ_N
TADCC_[16:1]
TRANSMIT
PAYLOAD
ADD
INTERFACE
TADCK
ADATA_[16:1]
X4
RECEIVE
DROP
ALIGNER
DCTL_[1—4]
TRST_N
JTAG INTERFACE
DRPBYP
ROH_CLK_[1—4]
ROW_CLK_[1—4]
RSD_CLK_[1—4]
RLD_CLK_[1—4]
ROHFP_[1—4]
ROHDAT_[1—4]_[1:0]
RLDCC_[1—4]
RSDCC_[1—4]
RSUSER_[1—4]
RLCLOW_[1—4]
DDATA_[16:1]
RDDCK_[1—4]
R_CLKO_1
REXPOW_[1—4]
D_CLK
RDDCC_[16:1]
RECEIVE
POINTER
PROCESSOR
TMS
RECEIVE PATH
OVERHEAD
PROCESSOR
RECEIVE
PAYLOAD
DROP
INTERFACE
TCK
RECEIVE
STS-48 RECEIVE
STS-192
TRANSPORT OVERHEAD
LINE
PROCESSOR
INTERFACE
DFRM
X4
X4
TDO
RFRM[1—4]
PATH
TRACE
BUFFER
STS PATH
PROCESSING
BLOCK
TDI
R_CLK_1
RD[15:0]
X4
SECTION
TRACE
BUFFER
STS_MODE = 0
5-7952.f (F)
Figure 1. TSOT0410G4 Block Diagram, STS-192 Mode
Agere Systems Inc.
13
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
MPMODE
PM_CLK
INT_N
TEA_N
TA_N
RW_N
DS_N
TS_N
CS_N
ADDRESS_[15:0]
DATA_[15:0]
PCLK
PARITY_[1:0]
TOH_CLK_[1—4]
TOW_CLK_[1—4]
TSD_CLK_[1—4]
TLD_CLK_[1—4]
TOHEN_[1—4]
TOHFP_[1—4]
TLDCC_[1—4]
TOHDAT_[1—4]_[1:0]
TSUSER_[1—4]
TSDCC_[1—4]
TLCLOW_[1—4]
TEXPOW_[1—4]
Description (continued)
TFRM
T_CLK
MICROPROCESSOR INTERFACE
RST_N
TD_1_[3:0]
TD_2_[3:0]
TD_3_[3:0]
TD_4_[3:0]
X4
X4
TRANSMIT
STS-48 TRANSMIT
STS-48
TRANSPORT OVERHEAD
LINE
PROCESSOR
INTERFACE
HIZ_N
TADCC_[16:1]
TRANSMIT
PAYLOAD
ADD
INTERFACE
TADCK
ADATA_[16:1]
T_CLKO_[1—4]
X4
RECEIVE
DROP
ALIGNER
DCTL_[1—4]
TRST_N
JTAG INTERFACE
DRPBYP
ROH_CLK_[1—4]
ROW_CLK_[1—4]
RSD_CLK_[1—4]
RLD_CLK_[1—4]
ROHFP_[1—4]
ROHDAT_[1—4]_[1:0]
RLDCC_[1—4]
RSDCC_[1—4]
RSUSER_[1—4]
RLCLOW_[1—4]
DDATA_[16:1]
RDDCK_[1—4]
R_CLKO_[1—4]
REXPOW_[1—4]
D_CLK
RDDCC_[16:1]
RECEIVE
POINTER
PROCESSOR
TMS
RECEIVE PATH
OVERHEAD
PROCESSOR
RECEIVE
PAYLOAD
DROP
INTERFACE
TDO
RECEIVE
STS-48 RECEIVE
STS-48
TRANSPORT OVERHEAD
LINE
PROCESSOR
INTERFACE
DFRM
X4
X4
TCK
PATH
TRACE
BUFFER
STS PATH
PROCESSING
BLOCK
TDI
R_CLK_[1—4]
RD_1_[3:0]
RD_2_[3:0]
RD_3_[3:0]
RD_4_[3:0]
RFRM[1—4]
X4
SECTION
TRACE
BUFFER
STS_MODE = 1
5-7982.e (F)
Figure 2. TSOT0410G4 Block Diagram, STS-48 Mode
Glossary
This glossary is not intended to list standard SDH or SONET terminology; rather, it is intended to describe terms
that may be specific to this device and/or may be unfamiliar to the reader.
■
■
Persistency Bit—a register bit that indicates the raw alarm has been continuously present since the alarm was
latched in the latched alarm register bit. (See the Persistency Registers section on page 96.)
PM—performance monitoring. Indication of the presence of an alarm or condition during the last second as
indicated by successive rising edges of the PM_CLK input. PM counters count the number of occurrences of a
condition, and 1-bit PM indicates that a condition was present at some time during the last second.
14
Agere Systems Inc.
Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Description (continued)
Receive Direction Overview
In the receive direction, the receive line interface can accept either a single STS-192 (STM-64) signal or four
STS-48 (STM-16) signals, from optical-to-electrical modules, in 16-bit or 4-bit wide serial 622 MHz format. The
receive line interface synchronizes to the frames in each data channel and rotates the data to frame and byte align
it. The data may also be optionally descrambled.
The aligned data is received by the receive transport overhead processor, and the section (regenerator section)
and line (multiplex section) overhead are extracted. Most of the overhead is then either stored internally or provided on external serial outputs, except for the pointer bytes, which are passed to the receive pointer processor.
The receive pointer processor interprets the pointer bytes and provides the SONET payload envelope (SPE) timing
for the receive-path overhead processor and the receive-drop data aligner (pointer processor).
The receive-path overhead processor extracts the path overhead and either stores it internally or processes it for
alarms and performance statistics. The receive-drop data aligner then translates the data from the receive clock
domain to the drop clock domain using a small elastic store and pointer adjustments to the data. The resulting
aligned data is then converted to sixteen 1-bit wide serial 622 MHz streams by the receive payload drop interface
and output along with SPE timing signals for use by a payload mapping device.
Transmit Direction Overview
In the transmit direction, the transmit payload add interface accepts sixteen 1-bit wide serial 622 MHz pseudo*
STS-12 (STM-4) signals and recovers the clock for each. The resulting 16 clocks must be synchronous in frequency, but can be asynchronous in phase. Each clock is used to frame, byte align, descramble, and then write its
associated data stream into a small buffer. The data is then read out of all 16 buffers using transmit clock (T_CLK)
and transmit frame (TFRM) timing.
The converted data is passed along to the transmit transport overhead processor which adds the appropriate section and line overhead. This overhead is either provided by internal configuration registers or external serial inputs,
except for the pointer bytes, which are received in the add data. The resulting valid STS-192 (STM-64) or STS-48
(STM-16) data is then optionally scrambled, converted to one 16-bit wide or four 4-bit wide serial 622 MHz signals,
and output for use by electrical-to-optical modules.
Transmit frame alignment synchronization may optionally be derived from any one of the 16 (selectable) add
inputs. A software provisioning option allows transmit frame alignment synchronization to be provided using the
timing that is being recovered from one of the add pseudo STS-12 links as the transmit frame sync instead of
TFRM.
* The data is formatted as an STS-12 signal; however, most of the transport overhead bytes are either unused or may be used for proprietary
purposes.
Agere Systems Inc.
15
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Description (continued)
STS-192 Mode Options
TOH Transparency
In applications where it is desired, a pass-through capability using software provisioning for the TOH on the line
interface to/from the TOH on the equipment interface is provided for the receive and transmit direction. This feature
is always supported on individual STS-48 channels and will require all four channels to be provisioned in STS-192
mode.
On the receive side, when TOH transparency is enabled, the pointer generators and elastic stores in all path processing blocks are bypassed. In this case, receive timing will be used by the payload drop interface. The receive
direction has the option for full TOH transparency, or just line overhead transparency with section overhead is used
for the normal proprietary drop I/F overhead. When TOH transparency is enabled, the pointer processor (PP) will
be bypassed on a per STS-48 level. See the Receive Pointer Processor section on page 62 for more information
on how this mode effects the device.
The transmit direction has the option for full TOH transparency or just line overhead (MSOH) transparency with
section (RSOH) overhead inserted. If enabled, AIS insertion due to an E1/F1 code in the add TOH will be disabled.
Regenerator Loopback
In applications where the receive data and overhead bytes need to be transmitted towards the transmit line interface, a software regenerator loopback provisioning option is provided. To use this feature, the transmit clock must
be derived from the receive clock at the 622 MHz level external to the device. The add interface buffers align the
data between the receive and transmit clock domains. This mode will only function correctly when the device is in
STS-192 mode. It will not work in STS-48 mode since the four STS-48 streams need to be aligned through the
transmit side. Four received STS-48 streams are unlikely to be aligned to the same clock and frame alignment. The
appropriate per STS-48 transmit line AIS insert control will be active during receive LOS, receive LOF, or R_CLK
failure while in regenerator loopback.
Device Mode Setup
The basic operating mode of the TSOT0410G4 is set using external pins.
The device can operate as a single STS-192 channel or as four separate STS-48 channels. The STS_MODE pin
(AM17) determines which mode is used. Pulling the STS_MODE pin down to VSS selects STS-192 mode.
In applications where no rate adaptation is required or desired, the pointer generators and elastic stores in all path
processing blocks can be bypassed by pulling up the DRPBYP pin (AP11) to VDD. In this case, receive timing will
be used by the payload drop interface. This mode should only be used if the device is in STS-192 mode. See the
Receive Pointer Processor section on page 62 for more information on how this mode affects the device.
The microprocessor interface can be set up to be synchronous by pulling up the MPMODE pin (E14) to VDD, or
asynchronous by pulling down the pin to VSS. See the Microprocessor Interface section on page 93 for more information.
For normal device operation, the TRST_N pin (AP30) should be tied low (to VSS). If TRST_N is high, a TCK clock
must be present.
16
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
VDD
VDD
VSS
VSS
VDD2
VDD2
VSS
VSS
DATA_15
DATA_10
DATA_6
DATA_1
VSS
CS_N
ADDRESS_2
VSS
VDD
VDD
ADDRESS_14
VSS
TLD_CLK_4
TOH_CLK_4
VSS
TSDCC_3
TOHFP_3
TSD_CLK_2
TSDCC_2
VSS
VSS
VDD2
VDD2
VSS
VSS
VDD
VDD
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
VDD
VDD
VSS
VSS
TADCC_14
TADCC_10
TADCC_6
TADCC_2
PARITY_1
DATA_11
DATA_7
DATA_2
TA_N
RW_N
ADDRESS_1
ADDRESS_5
ADDRESS_9
ADDRESS_13
TSUSER_4
TLDCC_4
TSD_CLK_4
TOHFP_4
TOW_CLK_3
TOHDAT_3_0
TLCLOW_2
TEXPOW_2
TOHDAT_2_0
TOH_CLK_2
TSUSER_1
TSD_CLK_1
TOHDAT_1_1
VSS
VSS
VDD
VDD
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
VSS
VSS
VDD
VSS
TADCC_15
TADCC_11
TADCC_7
TADCC_3
PARITY_0
DATA_12
DATA_8
DATA_3
TEA_N
PCLK
ADDRESS_0
ADDRESS_4
ADDRESS_8
ADDRESS_10
ADDRESS_15
TSDCC_4
TOHDAT_4_0
TLCLOW_3
TLD_CLK_3
TOHDAT_3_1
TOW_CLK_2
TSUSER_2
TOHDAT_2_1
TOHFP_2
TLDCC_1
TLD_CLK_1
TOHEN_1
VSS
VDD
VSS
VSS
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
VSS
VSS
VSS
VDD2
TADCC_16
TADCC_12
TADCC_8
TADCC_4
TADCK
DATA_13
DATA_9
DATA_4
INT_N
PM_CLK
DS_N
ADDRESS_3
ADDRESS_7
ADDRESS_12
TEXPOW_4
TOW_CLK_4
TOHEN_4
TSUSER_3
TSD_CLK_3
TOHEN_3
TLD_CLK_2
NC
TOHEN_2
TLCLOW_1
TSDCC_1
TOH_CLK_1
TOHFP_1
VDD2
VSS
VSS
VSS
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
17
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
E1
E2
E3
E4
E5
E6
E7
VDD2
ADATA_16
ADATA_16N
CTAP_ADD4
VDD2
TADCC_13
TADCC_9
F1
F2
F3
F4
F5
F31
F32
VDD2
ADATA_14
ADATA_14N
ADATA_15
ADATA_15N
TFRM
TFRMN
J31
J32
J33
J34
J35
K1
K2
TD12N/TD_4_0N
T_CLKO_3
T_CLKO_3N
TD11/TD_3_3
TD11N/TD_3_3N
ADATA_9
ADATA_9N
N1
N2
N3
N4
N5
N31
N32
E8
E9
TADCC_5
TADCC_1
F33
F34
T_CLKO_4
T_CLKO_4N
K3
K4
NC
ADATA_10
N33
N34
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
DATA_14
VDD
DATA_5
DATA_0
MPMODE
TS_N
VDD2
ADDRESS_6
ADDRESS_11
TLCLOW_4
F35
G1
G2
G3
G4
G5
G31
G32
G33
G34
VDD2
VSS
REXT_ADD
NC
ADATA_13
ADATA_13N
CTAP_TFRM
TD15/TD_4_3
TD15N/TD_4_3N
TD14/TD_4_2
K5
K31
K32
K33
K34
K35
L1
L2
L3
L4
ADATA_10N
NC
TD10/TD_3_2
TD10N/TD_3_2N
TD9/TD_3_1
TD9N/TD_3_1N
ADATA_8
ADATA_8N
NC
CTAP_ADD2
N35
P1
P2
P3
P4
P5
P31
P32
P33
P34
E20
E21
E22
E23
E24
E25
E26
VDD2
TOHDAT_4_1
TEXPOW_3
TLDCC_3
TOH_CLK_3
VDD
TLDCC_2
G35
H1
H2
H3
H4
H5
H31
L5
L31
L32
L33
L34
L35
M1
VDD
VDD
TD8/TD_3_0
TD8N/TD_3_0N
T_CLKO_2
T_CLKO_2N
CTAP_ADD1
P35
R1
R2
R3
R4
R5
R31
E27
E28
NC
TEXPOW_1
H32
H33
M2
M3
ADATA_6
ADATA_6N
R32
R33
E29
E30
TOW_CLK_1
TOHDAT_1_0
H34
H35
VSS
VSS
ADATA_12
ADATA_12N
NC
CTAP_ADD3
TD14N/
TD_4_2N
TD13/TD_4_1
TD13N/
TD_4_1N
TD12/TD_4_0
VSS
M4
M5
ADATA_7
ADATA_7N
R34
R35
E31
E32
E33
E34
E35
VDD2
T_CLK
T_CLKN
CTAP_TCLK
VDD2
J1
J2
J3
J4
J5
NC
ADATA_11
ADATA_11N
VDDA
VSSA
M31
M32
M33
M34
M35
TD7/TD_2_3
TD7N/TD_2_3N
NC
TD6/TD_2_2
TD6N/TD_2_2N
T1
T2
T3
T4
T5
VSS
NC
ADATA_5
ADATA_5N
NC
TD5/TD_2_1
TD5N/
TD_2_1N
TD4/TD_2_0
TD4N/
TD_2_0N
VSS
ADATA_3
ADATA_3N
ADATA_4
NC
ADATA_4N
T_CLKO_1
T_CLKO_1N
TD3/TD_1_3
TD3N/
TD_1_3N
TD2/TD_1_2
ADATA_1
ADATA_1N
NC
ADATA_2
ADATA_2N
TD2N/
TD_1_2N
TD1/TD_1_1
TD1N/
TD_1_1N
TD0/TD_1_0
TD0N/
TD_1_0N
VSS
VDDA
VSSA
NC
VDD2
Note: NC refers to no connect. Do not connect pins so designated.
18
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
T31
T32
T33
T34
T35
U1
U2
VDD2
NC
R_CLKO_1N
R_CLKO_1
VSS
DDATA_1
NC
Y1
Y2
Y3
Y4
Y5
Y31
Y32
VSS
NC
VSSA
VDDA
VDD2
VDD2
CTAP_RCLK1
AC31
AC32
AC33
AC34
AC35
AD1
AD2
R_CLK_2
R_CLK_2N
CTAP_RCLK2
RD3/RD_1_3
VSS
VSSA
VDDA
AG1
AG2
AG3
AG4
AG5
AG31
AG32
U3
U4
U5
U31
U32
U33
U34
U35
V1
V2
V3
NC
DCTL_1
DCTL_1N
NC
RFRM_1N
RFRM_1
R_CLKO_2N
VDD
VDD
DDATA_1N
REXT_DRP1
Y33
RFRM_4
Y34
RFRM_4N
Y35
VSS
AA1
DCTL_2
AA2
DCTL_2N
AA3
DDATA_5
AA4
DDATA_5N
AA5
REXT_DRP2
AA31 RD0N/RD_1_0N
AA32
RD0/RD_1_0
AA33
CTAP_RD1
AD3
DCTL_3
AD4
DCTL_3N
AD5
REXT_DRP3
AD31
RD5/RD_2_1
AD32 RD5N/RD_2_1N
AD33
RD4/RD_2_0
AD34 RD4N/RD_2_0N
AD35
CTAP_RD2
AE1
DDATA_9
AE2
DDATA_9N
AE3
DDATA_10
AG33
AG34
AG35
AH1
AH2
AH3
AH4
AH5
AH31
AH32
AH33
V4
V5
V31
V32
V33
V34
V35
W1
W2
DDATA_2
DDATA_2N
RFRM_2N
RFRM_2
R_CLKO_2
R_CLKO_3N
VDD
VDD
DDATA_3
AA34
R_CLK_1
AA35
R_CLK_1N
AB1
NC
AB2
DDATA_6
AB3
DDATA_6N
AB4
DDATA_7
AB5
DDATA_7N
AB31
RD2/RD_1_2
AB32 RD3N/RD_1_3N
AE4
DDATA_10N
AE5
VDD
AE31
VDD
AE32
RD7/RD_2_3
AE33 RD7N/RD_2_3N
AE34
RD6/RD_2_2
AE35 RD6N/RD_2_2N
AF1
NC
AF2
DDATA_11
AH34
AH35
AJ1
AJ2
AJ3
AJ4
AJ5
AJ31
AJ32
W3
W4
W5
W31
W32
W33
W34
W35
DDATA_3N
DDATA_4
DDATA_4N
RFRM_3
R_CLKO_4N
RFRM_3N
R_CLKO_4
R_CLKO_3
AB33 RD2N/RD_1_2N
AB34
RD1/RD_1_1
AB35 RD1N/RD_1_1N
AC1
VSS
AC2
NC
AC3
DDATA_8
AC4
DDATA_8N
AC5
NC
AF3
DDATA_11N
AF4
DDATA_12
AF5
DDATA_12N
AF31
RD8/RD_3_0
AF32 RD8N/RD_3_0N
AF33
R_CLK_3
AF34
R_CLK_3N
AF35 CTAP_RCLK3
AJ33
AJ34
AJ35
AK1
AK2
AK3
AK4
AK5
NC
DCTL_4
DCTL_4N
DDATA_13
DDATA_13N
RD10/RD_3_2
RD10N/
RD_3_2N
RD9/RD_3_1
RD9N/RD_3_1N
CTAP_RD3
VSS
VSSA
VDDA
DDATA_14
DDATA_14N
CTAP_RCLK4
RD11/RD_3_3
RD11N/
RD_3_3N
NC
VSS
VSS
NC
REXT_DRP4
DDATA_15
DDATA_15N
RD12/RD_4_0
RD12N/
RD_4_0N
R_CLK_4
R_CLK_4N
VSS
VDD2
DDATA_16
DDATA_16N
NC
REF10E
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
19
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)
Pin
Signal Name
AK31
RD14/RD_4_2
AK32 RD14N/RD_4_2N
AK33
RD13/RD_4_1
AK34 RD13N/RD_4_1N
AK35
VDD2
AL1
VDD2
AL2
REF14E
AL3
RESHIE
AL4
RESLOE
AL5
VDD2
AL6
PULLDN
AL7
PULLUP
AL8
NC
AL9
NC
AL10
PULLDN
AL11
VDD
AL12
RDDCC_15
AL13
RDDCC_11
AL14
RDDCC_7
AL15
RDDCC_3
AL16
VDD2
AL17
RSUSER_4
AL18
ROHFP_4
AL19
RLCLOW_4
AL20
VDD2
AL21
ROHDAT_3_1
AL22
REXPOW_3
AL23
ROW_CLK_2
AL24
RLD_CLK_2
AL25
VDD
AL26
ROHFP_1
AL27
RLCLOW_1
AL28
PULLDN
AL29
TDI
AL30
REF10L
Pin
Signal Name
AL31
VDD2
AL32
RD15/RD_4_3
AL33 RD15N/RD_4_3N
AL34
CTAP_RD4
AL35
VDD2
AM1
VSS
AM2
VSS
AM3
VSS
AM4
VDD2
AM5
PULLDN
AM6
PULLDN
AM7
PULLDN
AM8
NC
AM9
NC
AM10
PULLDN
AM11
DFRM
AM12
RDDCC_14
AM13
RDDCC_10
AM14
RDDCC_8
AM15
RDDCC_4
AM16
PULLUP
AM17
STS_MODE
AM18
ROH_CLK_4
AM19
RLDCC_4
AM20
RSD_CLK_3
AM21
ROHFP_3
AM22
RLCLOW_3
AM23
RSDCC_2
AM24
ROHDAT_2_0
AM25
RSUSER_1
AM26
ROH_CLK_1
AM27
RLDCC_1
AM28
PULLDN
AM29
TCK
AM30
TDO
Pin
Signal Name
Pin
Signal Name
AM31
AM32
AM33
AM34
AM35
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
RESLOL
VDD2
VSS
VSS
VSS
VSS
VSS
VDD
VSS
PULLDN
PULLDN
PULLDN
NC
NC
PULLDN
D_CLK
RDDCC_13
RDDCC_9
RDDCC_6
RDDCC_2
PULLUP
RSD_CLK_4
ROHDAT_4_1
RLD_CLK_4
RSUSER_3
ROH_CLK_3
RLDCC_3
RSD_CLK_2
ROHDAT_2_1
REXPOW_2
ROW_CLK_1
RLD_CLK_1
PULLDN
NC
TMS
AN31
AN32
AN33
AN34
AN35
AP1
AP2
AP3
AP4
AP5
AP6
AP7
AP8
AP9
AP10
AP11
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP28
AP29
AP30
RESHIL
VSS
VDD
VSS
VSS
VDD
VDD
VSS
VSS
PULLDN
PULLUP
PULLDN
NC
NC
PULLDN
DRPBYP
RDDCK_4
RDDCK_3
RDDCC_5
RDDCC_1
RST_N
HIZ_N
ROW_CLK_4
ROHDAT_4_0
REXPOW_4
ROW_CLK_3
RLD_CLK_3
RSUSER_2
ROHFP_2
RLCLOW_2
RSDCC_1
ROHDAT_1_0
REXPOW_1
PULLDN
TRST_N
Note: NC refers to no connect. Do not connect pins so designated.
20
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
AP31
AP32
AP33
AP34
AP35
AR1
AR2
AR3
AR4
AR5
REF14L
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VDD2
AR6
AR7
AR8
AR9
AR10
AR11
AR12
AR13
AR14
AR15
VDD2
VSS
VSS
NC
PULLDN
RDDCC_16
RDDCC_12
VSS
RDDCK_2
RDDCK_1
AR16
AR17
AR18
AR19
AR20
AR21
AR22
AR23
AR24
AR25
VSS
RSDCC_4
VDD
VDD
VSS
RSDCC_3
ROHDAT_3_0
VSS
ROH_CLK_2
RLDCC_2
AR26
AR27
AR28
AR29
AR30
AR31
AR32
AR33
AR34
AR35
RSD_CLK_1
ROHDAT_1_1
VSS
VSS
VDD2
VDD2
VSS
VSS
VDD
VDD
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
21
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
R1
ADATA_1
D16
ADDRESS_3
A11
DATA_6
AE2
DDATA_9N
R2
ADATA_1N
C16
ADDRESS_4
B11
DATA_7
AE3
DDATA_10
R4
ADATA_2
B16
ADDRESS_5
C11
DATA_8
AE4
DDATA_10N
R5
ADATA_2N
E17
ADDRESS_6
D11
DATA_9
AF2
DDATA_11
P1
ADATA_3
D17
ADDRESS_7
A10
DATA_10
AF3
DDATA_11N
P2
ADATA_3N
C17
ADDRESS_8
B10
DATA_11
AF4
DDATA_12
P3
ADATA_4
B17
ADDRESS_9
C10
DATA_12
AF5
DDATA_12N
P5
ADATA_4N
C18
ADDRESS_10
D10
DATA_13
AG4
DDATA_13
N3
ADATA_5
E18
ADDRESS_11
E10
DATA_14
AG5
DDATA_13N
N4
ADATA_5N
D18
ADDRESS_12
A9
DATA_15
AH4
DDATA_14
M2
ADATA_6
B18
ADDRESS_13
U4
DCTL_1
AH5
DDATA_14N
M3
ADATA_6N
A19
ADDRESS_14
U5
DCTL_1N
AJ4
DDATA_15
M4
ADATA_7
C19
ADDRESS_15
AA1
DCTL_2
AJ5
DDATA_15N
M5
ADATA_7N
A14
CS_N
AA2
DCTL_2N
AK2
DDATA_16
L1
ADATA_8
M1
CTAP_ADD1
AD3
DCTL_3
AK3
DDATA_16N
L2
ADATA_8N
L4
CTAP_ADD2
AD4
DCTL_3N
AM11
DFRM
K1
ADATA_9
H5
CTAP_ADD3
AG2
DCTL_4
AP11
DRPBYP
K2
ADATA_9N
E4
CTAP_ADD4
AG3
DCTL_4N
D15
DS_N
K4
ADATA_10
Y32
CTAP_RCLK1
U1
DDATA_1
AP17
HIZ_N
K5
ADATA_10N
AC33
CTAP_RCLK2
V2
DDATA_1N
D13
INT_N
J2
ADATA_11
AF35
CTAP_RCLK3
V4
DDATA_2
E14
MPMODE
J3
ADATA_11N
AH31
CTAP_RCLK4
V5
DDATA_2N
D26
NC
H2
ADATA_12
AA33
CTAP_RD1
W2
DDATA_3
E27
NC
H3
ADATA_12N
AD35
CTAP_RD2
W3
DDATA_3N
G3
NC
G4
ADATA_13
AG35
CTAP_RD3
W4
DDATA_4
H4
NC
G5
ADATA_13N
AL34
CTAP_RD4
W5
DDATA_4N
J1
NC
F2
ADATA_14
E34
CTAP_TCLK
AA3
DDATA_5
K3
NC
F3
ADATA_14N
G31
CTAP_TFRM
AA4
DDATA_5N
K31
NC
F4
ADATA_15
AN11
D_CLK
AB2
DDATA_6
L3
NC
F5
ADATA_15N
E13
DATA_0
AB3
DDATA_6N
M33
NC
E2
ADATA_16
A12
DATA_1
AB4
DDATA_7
N2
NC
E3
ADATA_16N
B12
DATA_2
AB5
DDATA_7N
N5
NC
C15
ADDRESS_0
C12
DATA_3
AC3
DDATA_8
P4
NC
B15
ADDRESS_1
D12
DATA_4
AC4
DDATA_8N
R3
NC
A15
ADDRESS_2
E12
DATA_5
AE1
DDATA_9
T4
NC
Note: NC refers to no connect. Do not connect pins so designated.
22
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order (continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
T32
NC
AN5
U2
NC
AN6
U3
NC
U31
Pin
Signal Name
PULLDN
AB33
RD2N/RD_1_2N
AN13
RDDCC_9
PULLDN
AC34
RD3/RD_1_3
AM13
RDDCC_10
AN7
PULLDN
AB32
RD3N/RD_1_3N
AL13
RDDCC_11
NC
AN10
PULLDN
AD33
RD4/RD_2_0
AR12
RDDCC_12
Y2
NC
AN28
PULLDN
AD34
RD4N/RD_2_0N
AN12
RDDCC_13
AB1
NC
AP5
PULLDN
AD31
RD5/RD_2_1
AM12
RDDCC_14
AC2
NC
AP7
PULLDN
AD32
RD5N/RD_2_1N
AL12
RDDCC_15
AC5
NC
AP10
PULLDN
AE34
RD6/RD_2_2
AR11
RDDCC_16
AF1
NC
AP29
PULLDN
AE35
RD6N/RD_2_2N
AR15
RDDCK_1
AG1
NC
AR10
PULLDN
AE32
RD7/RD_2_3
AR14
RDDCK_2
AH34
NC
AL7
PULLUP
AE33
RD7N/RD_2_3N
AP13
RDDCK_3
AJ2
NC
AP6
PULLUP
AF31
RD8/RD_3_0
AP12
RDDCK_4
AK4
NC
AM16
PULLUP
AF32
RD8N/RD_3_0N
AK5
REF10E
AL8
NC
AN16
PULLUP
AG33
RD9/RD_3_1
AL30
REF10L
AL9
NC
AA34
R_CLK_1
AG34
RD9N/RD_3_1N
AL2
REF14E
AM8
NC
AA35
R_CLK_1N
AG31
RD10/RD_3_2
AP31
REF14L
AM9
NC
AC31
R_CLK_2
AL3
RESHIE
AN8
NC
AC32
R_CLK_2N
AN31
RESHIL
AN9
NC
AF33
R_CLK_3
AL4
RESLOE
AN29
NC
AF34
R_CLK_3N
AP8
NC
AJ33
R_CLK_4
AP9
NC
AJ34
AR9
NC
C9
PARITY_0
AG32 RD10N/RD_3_2N
AH32
RD11/RD_3_3
AH33 RD11N/RD_3_3N
AM31
RESLOL
AJ32 RD12N/RD_4_0N
AP28
REXPOW_1
R_CLK_4N
AK33
AN25
REXPOW_2
T34
R_CLKO_1
AK34 RD13N/RD_4_1N
AL22
REXPOW_3
T33
R_CLKO_1N
AK31
AP20
REXPOW_4
B9
PARITY_1
V33
R_CLKO_2
C14
PCLK
U34
R_CLKO_2N
D14
PM_CLK
W35
R_CLKO_3
AL6
PULLDN
V34
AL10
PULLDN
W34
AJ31
RD12/RD_4_0
RD13/RD_4_1
RD14/RD_4_2
AK32 RD14N/RD_4_2N
G2
REXT_ADD
AL32
V3
REXT_DRP1
AL33 RD15N/RD_4_3N
AA5
REXT_DRP2
R_CLKO_3N
AP15
RDDCC_1
AD5
REXT_DRP3
R_CLKO_4
AN15
RDDCC_2
AJ3
REXT_DRP4
RD15/RD_4_3
AL28
PULLDN
W32
R_CLKO_4N
AL15
RDDCC_3
U33
RFRM_1
AM5
PULLDN
AA32
RD0/RD_1_0
AM15
RDDCC_4
U32
RFRM_1N
AM6
PULLDN
AA31
RD0N/RD_1_0N
AP14
RDDCC_5
V32
RFRM_2
AM7
PULLDN
AB34
RD1/RD_1_1
AN14
RDDCC_6
V31
RFRM_2N
AM10
PULLDN
AB35
RD1N/RD_1_1N
AL14
RDDCC_7
W31
RFRM_3
AM28
PULLDN
AB31
RD2/RD_1_2
AM14
RDDCC_8
W33
RFRM_3N
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
23
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order (continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Y33
RFRM_4
AN23
RSD_CLK_2
C6
TADCC_11
H33
TD13N/TD_4_1N
Y34
RFRM_4N
AM20
RSD_CLK_3
D6
TADCC_12
G34
TD14/TD_4_2
AL27
RLCLOW_1
AN17
RSD_CLK_4
E6
TADCC_13
H31
TD14N/TD_4_2N
AP25
RLCLOW_2
AP26
RSDCC_1
B5
TADCC_14
G32
TD15/TD_4_3
AM22
RLCLOW_3
AM23
RSDCC_2
C5
TADCC_15
G33
TD15N/TD_4_3N
AL19
RLCLOW_4
AR21
RSDCC_3
D5
TADCC_16
AL29
TDI
AN27
RLD_CLK_1
AR17
RSDCC_4
D9
TADCK
AM30
TDO
AL24
RLD_CLK_2
AP16
RST_N
AM29
TCK
C13
TEA_N
AP22
RLD_CLK_3
AM25
RSUSER_1
R34
TD0/TD_1_0
E28
TEXPOW_1
AN19
RLD_CLK_4
AP23
RSUSER_2
R35
TD0N/TD_1_0N
B26
TEXPOW_2
AM27
RLDCC_1
AN20
RSUSER_3
R32
TD1/TD_1_1
E22
TEXPOW_3
AR25
RLDCC_2
AL17
RSUSER_4
R33
TD1N/TD_1_1N
D19
TEXPOW_4
AN22
RLDCC_3
B14
RW_N
P35
TD2/TD_1_2
F31
TFRM
AM19
RLDCC_4
AM17
STS_MODE
R31
TD2N/TD_1_2N
F32
TFRMN
AM26
ROH_CLK_1
E32
T_CLK
P33
TD3/TD_1_3
D28
TLCLOW_1
AR24
ROH_CLK_2
E33
T_CLKN
P34
TD3N/TD_1_3N
B25
TLCLOW_2
AN21
ROH_CLK_3
P31
T_CLKO_1
N33
TD4/TD_2_0
C22
TLCLOW_3
AM18
ROH_CLK_4
P32
T_CLKO_1N
N34
TD4N/TD_2_0N
E19
TLCLOW_4
AP27
ROHDAT_1_0
L34
T_CLKO_2
N31
TD5/TD_2_1
C30
TLD_CLK_1
AR27
ROHDAT_1_1
L35
T_CLKO_2N
N32
TD5N/TD_2_1N
D25
TLD_CLK_2
AM24 ROHDAT_2_0
J32
T_CLKO_3
M34
TD6/TD_2_2
C23
TLD_CLK_3
AN24
ROHDAT_2_1
J33
T_CLKO_3N
M35
TD6N/TD_2_2N
A21
TLD_CLK_4
AR22
ROHDAT_3_0
F33
T_CLKO_4
M31
TD7/TD_2_3
C29
TLDCC_1
AL21
ROHDAT_3_1
F34
T_CLKO_4N
M32
TD7N/TD_2_3N
E26
TLDCC_2
AP19
ROHDAT_4_0
B13
TA_N
L32
TD8/TD_3_0
E23
TLDCC_3
AN18
ROHDAT_4_1
E9
TADCC_1
L33
TD8N/TD_3_0N
B20
TLDCC_4
AL26
ROHFP_1
B8
TADCC_2
K34
TD9/TD_3_1
AN30
TMS
AP24
ROHFP_2
C8
TADCC_3
K35
TD9N/TD_3_1N
D30
TOH_CLK_1
AM21
ROHFP_3
D8
TADCC_4
K32
TD10/TD_3_2
B28
TOH_CLK_2
AL18
ROHFP_4
E8
TADCC_5
K33
TD10N/TD_3_2N
E24
TOH_CLK_3
AN26
ROW_CLK_1
B7
TADCC_6
J34
TD11/TD_3_3
A22
TOH_CLK_4
AL23
ROW_CLK_2
C7
TADCC_7
J35
TD11N/TD_3_3N
E30
TOHDAT_1_0
AP21
ROW_CLK_3
D7
TADCC_8
H34
TD12/TD_4_0
B31
TOHDAT_1_1
AP18
ROW_CLK_4
E7
TADCC_9
J31
TD12N/TD_4_0N
B27
TOHDAT_2_0
AR26
RSD_CLK_1
B6
TADCC_10
H32
TD13/TD_4_1
C27
TOHDAT_2_1
Note: NC refers to no connect. Do not connect pins so designated.
24
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order (continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
B24
TOHDAT_3_0
A35
VDD
D4
VDD2
A7
VSS
C24
TOHDAT_3_1
B1
VDD
D32
VDD2
A8
VSS
C21
TOHDAT_4_0
B2
VDD
E1
VDD2
A13
VSS
E21
TOHDAT_4_1
B34
VDD
E5
VDD2
A16
VSS
C31
TOHEN_1
B35
VDD
E16
VDD2
A20
VSS
D27
TOHEN_2
C3
VDD
E20
VDD2
A23
VSS
D24
TOHEN_3
C33
VDD
E31
VDD2
A28
VSS
D21
TOHEN_4
E11
VDD
E35
VDD2
A29
VSS
D31
TOHFP_1
E25
VDD
F1
VDD2
A32
VSS
C28
TOHFP_2
L5
VDD
F35
VDD2
A33
VSS
A25
TOHFP_3
L31
VDD
T5
VDD2
B3
VSS
B22
TOHFP_4
U35
VDD
T31
VDD2
B4
VSS
E29
TOW_CLK_1
V1
VDD
Y5
VDD2
B32
VSS
C25
TOW_CLK_2
V35
VDD
Y31
VDD2
B33
VSS
B23
TOW_CLK_3
W1
VDD
AK1
VDD2
C1
VSS
D20
TOW_CLK_4
AE5
VDD
AK35
VDD2
C2
VSS
AP30
TRST_N
AE31
VDD
AL1
VDD2
C4
VSS
E15
TS_N
AL11
VDD
AL5
VDD2
C32
VSS
B30
TSD_CLK_1
AL25
VDD
AL16
VDD2
C34
VSS
A26
TSD_CLK_2
AN3
VDD
AL20
VDD2
C35
VSS
D23
TSD_CLK_3
AN33
VDD
AL31
VDD2
D1
VSS
B21
TSD_CLK_4
AP1
VDD
AL35
VDD2
D2
VSS
D29
TSDCC_1
AP2
VDD
AM4
VDD2
D3
VSS
A27
TSDCC_2
AP34
VDD
AM32
VDD2
D33
VSS
A24
TSDCC_3
AP35
VDD
AR5
VDD2
D34
VSS
C20
TSDCC_4
AR1
VDD
AR6
VDD2
D35
VSS
B29
TSUSER_1
AR2
VDD
AR30
VDD2
G1
VSS
C26
TSUSER_2
AR18
VDD
AR31
VDD2
G35
VSS
D22
TSUSER_3
AR19
VDD
J4
VDDA
H1
VSS
B19
TSUSER_4
AR34
VDD
T2
VDDA
H35
VSS
A1
VDD
AR35
VDD
Y4
VDDA
N1
VSS
A2
VDD
A5
VDD2
AD2
VDDA
N35
VSS
A17
VDD
A6
VDD2
AH3
VDDA
T1
VSS
A18
VDD
A30
VDD2
A3
VSS
T35
VSS
A34
VDD
A31
VDD2
A4
VSS
Y1
VSS
Note: NC refers to no connect. Do not connect pins so designated.
Agere Systems Inc.
25
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name Order (continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Y35
VSS
AM33
VSS
AP4
VSS
AR23
VSS
AC1
VSS
AM34
VSS
AP32
VSS
AR28
VSS
AC35
VSS
AM35
VSS
AP33
VSS
AR29
VSS
AH1
VSS
AN1
VSS
AR3
VSS
AR32
VSS
AH35
VSS
AN2
VSS
AR4
VSS
AR33
VSS
AJ1
VSS
AN4
VSS
AR7
VSS
J5
VSSA
AJ35
VSS
AN32
VSS
AR8
VSS
T3
VSSA
AM1
VSS
AN34
VSS
AR13
VSS
Y3
VSSA
AM2
VSS
AN35
VSS
AR16
VSS
AD1
VSSA
AM3
VSS
AP3
VSS
AR20
VSS
AH2
VSSA
Note: NC refers to no connect. Do not connect pins so designated.
Table 3. Pin Descriptions—System Control
Symbol
Type1
AP17
HIZ_N
I
u
Global Pin 3-State Control (Active-Low). This input incorporates a Schmitt
trigger. The minimum hysteresis is 0.3 V. Setting this input to 0 causes all
TSOT0410G4 outputs to assume a high-impedance state except for the JTAG
test data output (TDO) pin.
AP16
RST_N
Iu
Asynchronous Chip Reset (Active-Low). This input incorporates a Schmitt
trigger. The minimum hysteresis is 0.3 V. Setting this input to 0 causes an
asynchronous reset of the device. To ensure proper reset, this input should be
held low for a minimum of 26 ns (at least two 77.76 MHz clock cycles).
AM17
STS_MODE
Id
STS Mode Select. See the Device Mode Setup section on page 16 for details.
1 = STS-48.
0 = STS-192.
AP11
DRPBYP
Id
Pointer Generator Bypass Enable. See Pointer Generator Functions on
page 65 for details.
1 = Bypass.
0 = Enable pointer generator.
E14
MPMODE
Iu
Microprocessor Mode. See the Microprocessor Interface section on page 93
for details.
1 = Synchronous mode.
0 = Asynchronous mode.
D14
PM_CLK
I
One Second Performance Monitoring Clock. The performance monitoring
registers are updated on the rising edge of this signal. The internal PM anomaly counters are cleared at the same time. PM_CLK must be high for at least
26 ns, and low for at least 26 ns. The period of the performance monitoring
clock will normally be 1 s, but the minimum period required for proper operation
is 325 ns (during testing and development, for example).
Pin
Name/Description
1. I = input, Id = input with internal pull-down resistor, Iu = input with internal pull-up resistor. The value of all internal pull-up/pull-down resistors is 50 kΩ. All I/Os in Table 3 are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V at their inputs or outputs.
26
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 4. Pin Descriptions—Receive Line Interface
Pin
STS-192
Symbol
STS-48
Symbol
Type 1
Name/Description
AA34
AA35
R_CLK_1
R_CLK_1N
R_CLK_1
R_CLK_1N
I
LVDS
STS_MODE = 1: STS-48 receive channel 1 clock (622 MHz).
STS_MODE = 0: STS-192 receive channel 1 clock (622 MHz).
T34
T33
R_CLKO_1
R_CLKO_1N
R_CLKO_1
R_CLKO_1N
O
LVDS
Receive Clock 1 Loopback.
STS_MODE = 1: STS-48 clock loopback output for channel 1.
STS_MODE = 0: STS-192 clock loopback.
AA32
AA31
RD0
RD0N
RD_1_0
RD_1_0N
I
LVDS
STS_MODE = 1: STS-48 receive channel 1 bit 1 (LSB).
STS_MODE = 0: STS-192 receive channel 1 bit 0 (LSB).
AB34
AB35
RD1
RD1N
RD_1_1
RD_1_1N
I
LVDS
STS_MODE = 1: STS-48 receive channel 1 bit 2.
STS_MODE = 0: STS-192 receive channel 1 bit 1.
AB31
AB33
RD2
RD2N
RD_1_2
RD_1_2N
I
LVDS
STS_MODE = 1: STS-48 receive channel 1 bit 3.
STS_MODE = 0: STS-192 receive channel 1 bit 2.
AC34
AB32
RD3
RD3N
RD_1_3
RD_1_3N
I
LVDS
STS_MODE = 1: STS-48 receive channel 1 bit 4.
STS_MODE = 0: STS-192 receive channel 1 bit 3.
U33
U32
RFRM_1
RFRM_1N
RFRM_1
RFRM_1N
O
LVDS
STS_MODE = 1: STS-48 receive channel 1 frame sync.
STS_MODE = 0: STS-192 receive channel 1 frame sync.
AC31
AC32
R_CLK_2
R_CLK_2N
R_CLK_2
R_CLK_2N
I
LVDS
STS_MODE = 1: STS-48 receive channel 2 clock (622 MHz).
STS_MODE = 0: Not used.
V33
U34
R_CLKO_2
R_CLKO_2N
R_CLKO_2
R_CLKO_2N
O
LVDS
Receive Clock 2 Loopback.
STS_MODE = 1: STS-48 clock loopback output for channel 2.
STS_MODE = 0: Copy of receive clock 1 loopback.
AD33
AD34
RD4
RD4N
RD_2_0
RD_2_0N
I
LVDS
STS_MODE = 1: STS-48 receive channel 2 bit 1 (LSB).
STS_MODE = 0: STS-192 receive channel 1 bit 4.
AD31
AD32
RD5
RD5N
RD_2_1
RD_2_1N
I
LVDS
STS_MODE = 1: STS-48 receive channel 2 bit 2.
STS_MODE = 0: STS-192 receive channel 1 bit 5.
AE34
AE35
RD6
RD6N
RD_2_2
RD_2_2N
I
LVDS
STS_MODE = 1: STS-48 receive channel 2 bit 3.
STS_MODE = 0: STS-192 receive channel 1 bit 6.
AE32
AE33
RD7
RD7N
RD_2_3
RD_2_3N
I
LVDS
STS_MODE = 1: STS-48 receive channel 2 bit 4.
STS_MODE = 0: STS-192 receive channel 1 bit 7.
V32
V31
RFRM_1
RFRM_1N
RFRM_1
RFRM_1N
O
LVDS
STS_MODE = 1: STS-48 receive channel 2 frame sync.
STS_MODE = 0: Not used.
AF33
AF34
R_CLK_3
R_CLK_3N
R_CLK_3
R_CLK_3N
I
LVDS
STS_MODE = 1: STS-48 receive channel 3 clock (622 MHz).
STS_MODE = 0: Not used.
W35
V34
R_CLKO_3
R_CLKO_3N
R_CLKO_3
R_CLKO_3N
O
LVDS
Receive Clock 3 Loopback.
STS_MODE = 1: STS-48 clock loopback output for channel 3.
STS_MODE = 0: Copy of receive clock 1 loopback.
AF31
AF32
RD8
RD8N
RD_3_0
RD_3_0N
I
LVDS
STS_MODE = 1: STS-48 receive channel 3 bit 1 (LSB).
STS_MODE = 0: STS-192 receive channel 1 bit 8.
AG33
AG34
RD9
RD9N
RD_3_1
RD_3_1N
I
LVDS
STS_MODE = 1: STS-48 receive channel 3 bit 2.
STS_MODE = 0: STS-192 receive channel 1 bit 9.
1. I = input, O = output, LVDS = low-voltage differential signal.
Agere Systems Inc.
27
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 4. Pin Descriptions—Receive Line Interface (continued)
Pin
STS-192
Symbol
STS-48
Symbol
Type1
AG31
AG32
RD10
RD10N
RD_3_2
RD_3_2N
I
LVDS
STS_MODE = 1: STS-48 receive channel 3 bit 3.
STS_MODE = 0: STS-192 receive channel 1 bit 10.
AH32
AH33
RD11
RD11N
RD_3_3
RD_3_3N
I
LVDS
STS_MODE = 1: STS-48 receive channel 3 bit 4.
STS_MODE = 0: STS-192 receive channel 1 bit 11.
W31
W33
RFRM_3
RFRM_3N
RFRM_3
RFRM_3N
O
LVDS
STS_MODE = 1: STS-48 receive channel 3 frame sync.
STS_MODE = 0: Not used.
AJ33
AJ34
R_CLK_4
R_CLK_4N
R_CLK_4
R_CLK_4N
I
LVDS
STS_MODE = 1: STS-48 receive channel 4 clock (622 MHz).
STS_MODE = 0: Not used.
W34
W32
R_CLKO_4
R_CLKO_4N
R_CLKO_4
R_CLKO_4N
O
LVDS
Receive Clock 4 Loopback.
STS_MODE = 1: STS-48 clock loopback output for channel 4.
STS_MODE = 0: Copy of receive clock 1 loopback.
AJ31
AJ32
RD12
RD12N
RD_4_0
RD_4_0N
I
LVDS
STS_MODE = 1: STS-48 receive channel 4 bit 1 (LSB).
STS_MODE = 0: STS-192 receive channel 1 bit 12.
AK33
AK34
RD13
RD13N
RD_4_1
RD_4_1N
I
LVDS
STS_MODE = 1: STS-48 receive channel 4 bit 2.
STS_MODE = 0: STS-192 receive channel 1 bit 13.
AK31
AK32
RD14
RD14N
RD_4_2
RD_4_2N
I
LVDS
STS_MODE = 1: STS-48 receive channel 4 bit 3.
STS_MODE = 0: STS-192 receive channel 1 bit 14.
AL32
AL33
RD15
RD15N
RD_4_3
RD_4_3N
I
LVDS
STS_MODE = 1: STS-48 receive channel 4 bit 4.
STS_MODE = 0: STS-192 receive channel 1 bit 15 (MSB).
Y33
Y34
RFRM_4
RFRM_4N
RFRM_4
RFRM_4N
O
LVDS
STS_MODE = 1: STS-48 receive channel 4 frame sync.
STS_MODE = 0: Not used.
Name/Description
1. I = input, O = output, LVDS = low-voltage differential signal.
Table 5. Pin Descriptions—Transmit Line Interface
Pin
STS-192
Symbol
STS-48
Symbol
Type1
Name/Description
E32
E33
T_CLK
T_CLKN
T_CLK
T_CLKN
I
LVDS
Transmit Clock. 622 MHz clock input for all channels. This is
the clock input to the entire transmit section.
F31
F32
TFRM
TFRMN
TFRM
TFRMN
I
LVDS
Transmit Frame Sync. Frame sync input for all channels. This
signal is required for operation of the transmit section. TFRM
must be low for at least 32 T_CLK clock periods and then stay
high for at least 32 more T_CLK periods after the rising edge.
See the Add Interface Framing (A1 and A2) section on
page 82 for details.
P31
P32
T_CLKO_1
T_CLKO_1N
T_CLKO_1
T_CLKO_1N
O
LVDS
Transmit Clock 1 Loopback. Transmit clock output.
STS_MODE = 1: STS-48 clock output for channel 1.
STS_MODE = 0: STS-192 transmit clock output.
R34
R35
TD0
TD0N
TD_1_0
TD_1_0N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 1 bit 1 (LSB).
STS_MODE = 0: STS-192 transmit channel 1 bit 0 (LSB).
1. I = input, O = output, LVDS = low-voltage differential signal.
28
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 5. Pin Descriptions—Transmit Line Interface (continued)
Pin
STS-192
Symbol
STS-48
Symbol
Type1
R32
R33
TD1
TD1N
TD_1_1
TD_1_1N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 1 bit 2.
STS_MODE = 0: STS-192 transmit channel 1 bit 1.
P35
R31
TD2
TD2N
TD_1_2
TD_1_2N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 1 bit 3.
STS_MODE = 0: STS-192 transmit channel 1 bit 2.
P33
P34
TD3
TD3N
TD_1_3
TD_1_3N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 1 bit 4.
STS_MODE = 0: STS-192 transmit channel 1 bit 3.
L34
L35
T_CLKO_2
T_CLKO_2N
T_CLKO_2
T_CLKO_2N
O
LVDS
Transmit Clock 2 Loopback. Transmit clock output.
STS_MODE = 1: STS-48 clock output for channel 2.
STS_MODE = 0: Copy of transmit clock 1 loopback.
N33
N34
TD4
TD4N
TD_2_0
TD_2_0N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 2 bit 1 (LSB).
STS_MODE = 0: STS-192 transmit channel 1 bit 4.
N31
N32
TD5
TD5N
TD_2_1
TD_2_1N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 2 bit 2.
STS_MODE = 0: STS-192 transmit channel 1 bit 5.
M34
M35
TD6
TD6N
TD_2_2
TD_2_2N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 2 bit 3.
STS_MODE = 0: STS-192 transmit channel 1 bit 6.
M31
M32
TD7
TD7N
TD_2_3
TD_2_3N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 2 bit 4.
STS_MODE = 0: STS-192 transmit channel 1 bit 7.
J32
J33
T_CLKO_3
T_CLKO_3N
T_CLKO_3
T_CLKO_3N
O
LVDS
Transmit Clock 3 Loopback. Transmit clock output.
STS_MODE = 1: STS-48 clock output for channel 3.
STS_MODE = 0: Copy of transmit clock 1 loopback.
L32
L33
TD8
TD8N
TD_3_0
TD_3_0N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 3 bit 1 (LSB).
STS_MODE = 0: STS-192 transmit channel 1 bit 8.
K34
K35
TD9
TD9N
TD_3_1
TD_3_1N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 3 bit 2.
STS_MODE = 0: STS-192 transmit channel 1 bit 9.
K32
K33
TD10
TD10N
TD_3_2
TD_3_2N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 3 bit 3.
STS_MODE = 0: STS-192 transmit channel 1 bit 10.
J34
J35
TD11
TD11N
TD_3_3
TD_3_3N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 3 bit 4.
STS_MODE = 0: STS-192 transmit channel 1 bit 11.
F33
F34
T_CLKO_4
T_CLKO_4N
T_CLKO_4
T_CLKO_4N
O
LVDS
Transmit Clock 4 Loopback. Transmit clock output.
STS_MODE = 1: STS-48 clock output for channel 4.
STS_MODE = 0: Copy of transmit clock 1 loopback.
H34
J31
TD12
TD12N
TD_4_0
TD_4_0N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 4 bit 1 (LSB).
STS_MODE = 0: STS-192 transmit channel 1 bit 12.
H32
H33
TD13
TD13N
TD_4_1
TD_4_1N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 4 bit 2.
STS_MODE = 0: STS-192 transmit channel 1 bit 13.
G34
H31
TD14
TD14N
TD_4_2
TD_4_2N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 4 bit 3.
STS_MODE = 0: STS-192 transmit channel 1 bit 14.
G32
G33
TD15
TD15N
TD_4_3
TD_4_3N
O
LVDS
STS_MODE = 1: STS-48 transmit channel 4 bit 4.
STS_MODE = 0: STS-192 transmit channel 1 bit 15 (MSB).
Name/Description
1. O = output, LVDS = low-voltage differential signal.
Agere Systems Inc.
29
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 6. Pin Descriptions—LVDS Reference, Line Interface
Pin
Symbol
Type1
AA33
CTAP_RD1
I
LVDS
Term
Center Tap for RD_1 Inputs. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
AD35
CTAP_RD2
I
LVDS
Term
Center Tap for RD_2 Inputs. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
AG35
CTAP_RD3
I
LVDS
Term
Center Tap for RD_3 Inputs. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
AL34
CTAP_RD4
I
LVDS
Term
Center Tap for RD_4 Inputs. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
Y32
CTAP_RCLK1
I
LVDS
Term
Center Tap for R_CLK_1 Input. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
AC33
CTAP_RCLK2
I
LVDS
Term
Center Tap for R_CLK_2 Input. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
AF35
CTAP_RCLK3
I
LVDS
Term
Center Tap for R_CLK_3 Input. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
AH31
CTAP_RCLK4
I
LVDS
Term
Center Tap for R_CLK_4 Input. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
E34
CTAP_TCLK
I
LVDS
Term
Center Tap for T_CLK Input. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
G31
CTAP_TFRM
I
LVDS
Term
Center Tap for TFRM Input. Provides center-tapped common-mode
termination. This input should be terminated through an external 0.01 µF
capacitor to ground.
AL30
REF10L
I
1.0 V ± 3% reference voltage for line interface I/Os. An example circuit is
shown in Figure 3 on page 35.
AP31
REF14L
I
1.4 V ± 3% reference voltage for line interface I/Os. An example circuit is
shown in Figure 3 on page 35.
AN31
RESHIL
I
Connect a 100 Ω ± 1% resistor between these pins.
AM31
RESLOL
I
Name/Description
1. I = input. I LVDS term = low-voltage differential signal termination pin.
30
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 7. Pin Descriptions—Receive Drop Equipment Interface
Pin
Symbol
Type1
AN11
D_CLK
I/O
DRPBYP = 1: output: receive channel 1 clock (78 MHz).
DRPBYP = 0: input: receive drop clock (78 MHz)—all channels.
AM11
DFRM
I/O
DRPBYP = 1: output: receive channel 1 frame sync.
DRPBYP = 0: input: receive drop frame sync—all channels.
U1
V2
DDATA_1
DDATA_1N
O
LVDS
Receive drop STS-12 channel 1 serial data (622 MHz).
AP15
RDDCC_1
I
Receive drop STS-12 channel 1 section DCC serial link.
V4
V5
DDATA_2
DDATA_2N
O
LVDS
Receive drop STS-12 channel 2 serial data (622 MHz).
AN15
RDDCC_2
I
Receive drop STS-12 channel 2 section DCC serial link.
W2
W3
DDATA_3
DDATA_3N
O
LVDS
Receive drop STS-12 channel 3 serial data (622 MHz).
AL15
RDDCC_3
I
Receive drop STS-12 channel 3 section DCC serial link.
W4
W5
DDATA_4
DDATA_4N
O
LVDS
Receive drop STS-12 channel 4 serial data (622 MHz).
AM15
RDDCC_4
I
Receive drop STS-12 channel 4 section DCC serial link.
U4
U5
DCTL_1
DCTL_1N
O
LVDS
AR15
RDDCK_1
O
AA3
AA4
DDATA_5
DDATA_5N
O
LVDS
Receive drop STS-12 channel 5 serial data (622 MHz).
AP14
RDDCC_5
I
Receive drop STS-12 channel 5 section DCC serial link.
AB2
AB3
DDATA_6
DDATA_6N
O
LVDS
Receive drop STS-12 channel 6 serial data (622 MHz).
AN14
RDDCC_6
I
Receive drop STS-12 channel 6 section DCC serial link.
AB4
AB5
DDATA_7
DDATA_7N
O
LVDS
Receive drop STS-12 channel 7 serial data (622 MHz).
AL14
RDDCC_7
I
Receive drop STS-12 channel 7 section DCC serial link.
AC3
AC4
DDATA_8
DDATA_8N
O
LVDS
Receive drop STS-12 channel 8 serial data (622 MHz).
AM14
RDDCC_8
I
Receive drop STS-12 channel 8 section DCC serial link.
AA1
AA2
DCTL_2
DCTL_2N
O
LVDS
AR14
RDDCK_2
O
Name/Description
Receive drop STS-12 channels 1—4 timing control (622 MHz).
Receive drop STS-12 channels 1—4 section DCC clock.
Receive drop STS-12 channels 5—8 timing control (622 MHz).
Receive drop STS-12 channels 5—8 section DCC clock.
1. I = input, O = output, I/O = bidirectional pin, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
Agere Systems Inc.
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 7. Pin Descriptions—Receive Drop Equipment Interface (continued)
Pin
Symbol
Type1
AE1
AE2
DDATA_9
DDATA_9N
O
LVDS
Receive drop STS-12 channel 9 serial data (622 MHz).
AN13
RDDCC_9
I
Receive drop STS-12 channel 9 section DCC serial link.
AE3
AE4
DDATA_10
DDATA_10N
O
LVDS
Receive drop STS-12 channel 10 serial data (622 MHz).
AM13
RDDCC_10
I
Receive drop STS-12 channel 10 section DCC serial link.
AF2
AF3
DDATA_11
DDATA_11N
O
LVDS
Receive drop STS-12 channel 11 serial data (622 MHz).
AL13
RDDCC_11
I
Receive drop STS-12 channel 11 section DCC serial link.
AF4
AF5
DDATA_12
DDATA_12N
O
LVDS
Receive drop STS-12 channel 12 serial data (622 MHz).
AR12
RDDCC_12
I
Receive drop STS-12 channel 12 section DCC serial link.
AD3
AD4
DCTL_3
DCTL_3N
O
LVDS
AP13
RDDCK_3
O
AG4
AG5
DDATA_13
DDATA_13N
O
LVDS
Receive drop STS-12 channel 13 serial data (622 MHz).
AN12
RDDCC_13
I
Receive drop STS-12 channel 13 section DCC serial link.
AH4
AH5
DDATA_14
DDATA_14N
O
LVDS
Receive drop STS-12 channel 14 serial data (622 MHz).
AM12
RDDCC_14
I
Receive drop STS-12 channel 14 section DCC serial link.
AJ4
AJ5
DDATA_15
DDATA_15N
O
LVDS
Receive drop STS-12 channel 15 serial data (622 MHz).
AL12
RDDCC_15
I
Receive drop STS-12 channel 15 section DCC serial link.
AK2
AK3
DDATA_16
DDATA_16N
O
LVDS
Receive drop STS-12 channel 16 serial data (622 MHz).
AR11
RDDCC_16
I
Receive drop STS-12 channel 16 section DCC serial link.
AG2
AG3
DCTL_4
DCTL_4N
O
LVDS
AP12
RDDCK_4
O
Name/Description
Receive drop STS-12 channels 9—12 timing control (622 MHz).
Receive drop STS-12 channels 9—12 section DCC clock.
Receive drop STS-12 channels 13—16 timing control (622 MHz).
Receive drop STS-12 channels 13—16 section DCC clock.
1. I = input, O = output, I/O = bidirectional pin, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 8. Pin Descriptions—Transmit Add Equipment Interface
Pin
Symbol
Type1
R1
R2
ADATA_1
ADATA_1N
I
LVDS
Transmit add STS-12 channel 1 serial data (622 MHz).
E9
TADCC_1
O
Transmit add STS-12 channel 1 section DCC serial link.
R4
R5
ADATA_2
ADATA_2N
I
LVDS
Transmit add STS-12 channel 2 serial data (622 MHz).
B8
TADCC_2
O
Transmit add STS-12 channel 2 section DCC serial link.
P1
P2
ADATA_3
ADATA_3N
I
LVDS
Transmit add STS-12 channel 3 serial data (622 MHz).
C8
TADCC_3
O
Transmit add STS-12 channel 3 section DCC serial link.
P3
P5
ADATA_4
ADATA_4N
I
LVDS
Transmit add STS-12 channel 4 serial data (622 MHz).
D8
TADCC_4
O
Transmit add STS-12 channel 4 section DCC serial link.
N3
N4
ADATA_5
ADATA_5N
I
LVDS
Transmit add STS-12 channel 5 serial data (622 MHz).
E8
TADCC_5
O
Transmit add STS-12 channel 5 section DCC serial link.
M2
M3
ADATA_6
ADATA_6N
I
LVDS
Transmit add STS-12 channel 6 serial data (622 MHz).
Name/Description
B7
TADCC_6
O
Transmit add STS-12 channel 6 section DCC serial link.
M4
M5
ADATA_7
ADATA_7N
I
LVDS
Transmit add STS-12 channel 7 serial data (622 MHz).
C7
TADCC_7
O
Transmit add STS-12 channel 7 section DCC serial link.
L1
L2
ADATA_8
ADATA_8N
I
LVDS
Transmit add STS-12 channel 8 serial data (622 MHz).
D7
TADCC_8
O
Transmit add STS-12 channel 8 section DCC serial link.
K1
K2
ADATA_9
ADATA_9N
I
LVDS
Transmit add STS-12 channel 9 serial data (622 MHz).
E7
TADCC_9
O
Transmit add STS-12 channel 9 section DCC serial link.
K4
K5
ADATA_10
ADATA_10N
I
LVDS
Transmit add STS-12 channel 10 serial data (622 MHz).
B6
TADCC_10
O
Transmit add STS-12 channel 10 section DCC serial link.
1. I = input, O = output, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
Agere Systems Inc.
33
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 8. Pin Descriptions—Transmit Add Equipment Interface (continued)
Pin
Symbol
Type1
J2
J3
ADATA_11
ADATA_11N
I
LVDS
Transmit add STS-12 channel 11 serial data (622 MHz).
C6
TADCC_11
O
Transmit add STS-12 channel 11 section DCC serial link.
H2
H3
ADATA_12
ADATA_12N
I
LVDS
Transmit add STS-12 channel 12 serial data (622 MHz).
Name/Description
D6
TADCC_12
O
Transmit add STS-12 channel 12 section DCC serial link.
G4
G5
ADATA_13
ADATA_13N
I
LVDS
Transmit add STS-12 channel 13 serial data (622 MHz).
E6
TADCC_13
O
Transmit add STS-12 channel 13 section DCC serial link.
F2
F3
ADATA_14
ADATA_14N
I
LVDS
Transmit add STS-12 channel 14 serial data (622 MHz).
B5
TADCC_14
O
Transmit add STS-12 channel 14 section DCC serial link.
F4
F5
ADATA_15
ADATA_15N
I
LVDS
Transmit add STS-12 channel 15 serial data (622 MHz).
C5
TADCC_15
O
Transmit add STS-12 channel 15 section DCC serial link.
E2
E3
ADATA_16
ADATA_16N
I
LVDS
Transmit add STS-12 channel 16 serial data (622 MHz).
D5
TADCC_16
O
Transmit add STS-12 channel 16 section DCC serial link.
D9
TADCK
O
Transmit add STS-12 section DCC clock—all channels.
1. I = input, O = output, LVDS = low-voltage differential signal. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 9. Pin Descriptions—LVDS Reference, Equipment Interface
Pin
Symbol
Type1
M1
CTAP_ADD1
I
LVDS
Term
Center Tap for ADATA_1 Through ADATA_4 Inputs. Provides center-tapped common-mode termination. This input should be terminated
through an external 0.01 µF capacitor to ground.
L4
CTAP_ADD2
I
LVDS
Term
Center Tap for ADATA_5 Through ADATA_8 Inputs. Provides center-tapped common-mode termination. This input should be terminated
through an external 0.01 µF capacitor to ground.
H5
CTAP_ADD3
I
LVDS
Term
Center Tap for ADATA_9 Through ADATA_12 Inputs. Provides center-tapped common-mode termination. This input should be terminated
through an external 0.01 µF capacitor to ground.
E4
CTAP_ADD4
I
LVDS
Term
Center Tap for ADATA_13 Through ADATA_16 Inputs. Provides center-tapped common-mode termination. This input should be terminated
through an external 0.01 µF capacitor to ground.
AK5
REF10E
I
1.0 V ± 3% reference voltage for equipment interface I/Os. An example circuit is shown in Figure 3.
AL2
REF14E
I
1.4 V ± 3% reference voltage for equipment interface I/Os. An example circuit is shown in Figure 3.
AL3
RESHIE
I
Connect a 100 Ω ± 1% resistor between these pins.
AL4
RESLOE
I
Name/Description
1. I = input. I LVDS term = low-voltage differential signal termination pin.
3.3 V
3.3 V
2.32 kΩ
1%
1.91 kΩ
1%
1 kΩ
1%
1.43 kΩ
1%
LVDSREF10
LVDSREF14
10 nF
10 nF
0622(F)
Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages
Agere Systems Inc.
35
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 10. Pin Descriptions—Transport Overhead Interface
Pin
Symbol
Type1
AP28
REXPOW_1
O
STS_MODE = 1: STS-48 receive channel 1 express orderwire.
STS_MODE = 0: STS-192 receive channel 1 express orderwire.
AL27
RLCLOW_1
O
STS_MODE = 1: STS-48 receive channel 1 local orderwire.
STS_MODE = 0: STS-192 receive channel 1 local orderwire.
AM25
RSUSER_1
O
STS_MODE = 1: STS-48 receive channel 1 section user channel.
STS_MODE = 0: STS-192 receive channel 1 section user channel.
AN26
ROW_CLK_1
O
STS_MODE = 1: STS-48 receive channel 1 orderwire/user clock.
STS_MODE = 0: STS-192 receive channel 1 orderwire/user clock.
AM27
RLDCC_1
O
STS_MODE = 1: STS-48 receive channel 1 line DCC.
STS_MODE = 0: STS-192 receive channel 1 line DCC.
AN27
RLD_CLK_1
O
STS_MODE = 1: STS-48 receive channel 1 line DCC clock.
STS_MODE = 0: STS-192 receive channel 1 line DCC clock.
AP26
RSDCC_1
O
STS_MODE = 1: STS-48 receive channel 1 section DCC.
STS_MODE = 0: STS-192 receive channel 1 section DCC.
AR26
RSD_CLK_1
O
STS_MODE = 1: STS-48 receive channel 1 section DCC clock.
STS_MODE = 0: STS-192 receive channel 1 section DCC clock.
AP27
ROHDAT_1_0
O
STS_MODE = 1: STS-48 receive channel 1 TOH data (LSB).
STS_MODE = 0: Receive STS-1 channel 1—48 TOH data (LSB).
AR27
ROHDAT_1_1
O
STS_MODE = 1: STS-48 receive channel 1 TOH data (MSB).
STS_MODE = 0: Receive STS-1 channel 1—48 TOH data (MSB).
AL26
ROHFP_1
O
STS_MODE = 1: STS-48 receive channel 1 TOH frame pulse.
STS_MODE = 0: Receive STS-1 channel 1—48 TOH frame pulse.
AM26
ROH_CLK_1
O
STS_MODE = 1: STS-48 receive channel 1 TOH clock.
STS_MODE = 0: Receive STS-1 channel 1—48 TOH clock.
E28
TEXPOW_1
I
STS_MODE = 1: STS-48 transmit channel 1 express orderwire.
STS_MODE = 0: STS-192 transmit channel 1 express orderwire.
D28
TLCLOW_1
I
STS_MODE = 1: STS-48 transmit channel 1 local orderwire.
STS_MODE = 0: STS-192 transmit channel 1 local orderwire.
B29
TSUSER_1
I
STS_MODE = 1: STS-48 transmit channel 1 section user channel.
STS_MODE = 0: STS-192 transmit channel 1 section user channel.
E29
TOW_CLK_1
O
STS_MODE = 1: STS-48 transmit channel 1 orderwire/user clock.
STS_MODE = 0: STS-192 transmit channel 1 orderwire/user clock.
C29
TLDCC_1
I
STS_MODE = 1: STS-48 transmit channel 1 line DCC.
STS_MODE = 0: STS-192 transmit channel 1 line DCC.
C30
TLD_CLK_1
O
STS_MODE = 1: STS-48 transmit channel 1 line DCC clock.
STS_MODE = 0: STS-192 transmit channel 1 line DCC clock.
Name/Description
1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
36
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 10. Pin Descriptions—Transport Overhead Interface (continued)
Pin
Symbol
Type1
D29
TSDCC_1
I
STS_MODE = 1: STS-48 transmit channel 1 section DCC.
STS_MODE = 0: STS-192 transmit channel 1 section DCC.
B30
TSD_CLK_1
O
STS_MODE = 1: STS-48 transmit channel 1 section DCC clock.
STS_MODE = 0: STS-192 transmit channel 1 section DCC clock.
E30
TOHDAT_1_0
I
STS_MODE = 1: STS-48 transmit channel 1 TOH data (LSB).
STS_MODE = 0: Transmit STS-1 channel 1—48 TOH data (LSB).
B31
TOHDAT_1_1
I
STS_MODE = 1: STS-48 transmit channel 1 TOH data (MSB).
STS_MODE = 0: Transmit STS-1 channel 1—48 TOH data (MSB).
C31
TOHEN_1
I
STS_MODE = 1: STS-48 transmit channel 1 TOH insert enable.
STS_MODE = 0: Transmit STS-1 channel 1—48 TOH insert enable.
D31
TOHFP_1
O
STS_MODE = 1: STS-48 transmit channel 1 TOH frame pulse.
STS_MODE = 0: Transmit STS-1 channel 1—48 TOH frame pulse.
D30
TOH_CLK_1
O
STS_MODE = 1: STS-48 transmit channel 1 TOH clock.
STS_MODE = 0: Transmit STS-1 channel 1—48 TOH clock.
AN25
REXPOW_2
O
STS_MODE = 1: STS-48 receive channel 2 express orderwire.
STS_MODE = 0: Not used.
AP25
RLCLOW_2
O
STS_MODE = 1: STS-48 receive channel 2 local orderwire.
STS_MODE = 0: Not used.
AP23
RSUSER_2
O
STS_MODE = 1: STS-48 receive channel 2 section user channel.
STS_MODE = 0: Not used.
AL23
ROW_CLK_2
O
STS_MODE = 1: STS-48 receive channel 2 orderwire/user clock.
STS_MODE = 0: Not used.
AR25
RLDCC_2
O
STS_MODE = 1: STS-48 receive channel 2 line DCC.
STS_MODE = 0: Not used.
AL24
RLD_CLK_2
O
STS_MODE = 1: STS-48 receive channel 2 line DCC clock.
STS_MODE = 0: Not used.
AM23
RSDCC_2
O
STS_MODE = 1: STS-48 receive channel 2 section DCC.
STS_MODE = 0: Not used.
AN23
RSD_CLK_2
O
STS_MODE = 1: STS-48 receive channel 2 section DCC clock.
STS_MODE = 0: Not used.
AM24
ROHDAT_2_0
O
STS_MODE = 1: STS-48 receive channel 2 TOH data (LSB).
STS_MODE = 0: Receive STS-1 channel 49—96 TOH data (LSB).
AN24
ROHDAT_2_1
O
STS_MODE = 1: STS-48 receive channel 2 TOH data (MSB).
STS_MODE = 0: Receive STS-1 channel 49—96 TOH data (MSB).
AP24
ROHFP_2
O
STS_MODE = 1: STS-48 receive channel 2 TOH frame pulse.
STS_MODE = 0: Receive STS-1 channel 49—96 TOH frame pulse.
AR24
ROH_CLK_2
O
STS_MODE = 1: STS-48 receive channel 2 TOH clock.
STS_MODE = 0: Receive STS-1 channel 49—96 TOH clock.
Name/Description
1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
Agere Systems Inc.
37
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 10. Pin Descriptions—Transport Overhead Interface (continued)
Pin
Symbol
Type1
B26
TEXPOW_2
I
STS_MODE = 1: STS-48 transmit channel 2 express orderwire.
STS_MODE = 0: Not used.
B25
TLCLOW_2
I
STS_MODE = 1: STS-48 transmit channel 2 local orderwire.
STS_MODE = 0: Not used.
C26
TSUSER_2
I
STS_MODE = 1: STS-48 transmit channel 2 section user channel.
STS_MODE = 0: Not used.
C25
TOW_CLK_2
O
STS_MODE = 1: STS-48 transmit channel 2 orderwire/user clock.
STS_MODE = 0: Not used.
E26
TLDCC_2
I
STS_MODE = 1: STS-48 transmit channel 2 line DCC.
STS_MODE = 0: Not used.
D25
TLD_CLK_2
O
STS_MODE = 1: STS-48 transmit channel 2 line DCC clock.
STS_MODE = 0: Not used.
A27
TSDCC_2
I
STS_MODE = 1: STS-48 transmit channel 2 section DCC.
STS_MODE = 0: Not used.
A26
TSD_CLK_2
O
STS_MODE = 1: STS-48 transmit channel 2 section DCC clock.
STS_MODE = 0: Not used.
B27
TOHDAT_2_0
I
STS_MODE = 1: STS-48 transmit channel 2 TOH data (LSB).
STS_MODE = 0: Transmit STS-1 channel 49—96 TOH data (LSB).
C27
TOHDAT_2_1
I
STS_MODE = 1: STS-48 transmit channel 2 TOH data (MSB).
STS_MODE = 0: Transmit STS-1 channel 49—96 TOH data (MSB).
D27
TOHEN_2
I
STS_MODE = 1: STS-48 transmit channel 2 TOH insert enable.
STS_MODE = 0: Transmit STS-1 channel 49—96 TOH insert enable.
C28
TOHFP_2
O
STS_MODE = 1: STS-48 transmit channel 2 TOH frame pulse.
STS_MODE = 0: Transmit STS-1 channel 49—96 TOH frame pulse.
B28
TOH_CLK_2
O
STS_MODE = 1: STS-48 transmit channel 2 TOH clock.
STS_MODE = 0: Transmit STS-1 channel 49—96 TOH clock.
AL22
REXPOW_3
O
STS_MODE = 1: STS-48 receive channel 3 express orderwire.
STS_MODE = 0: Not used.
AM22
RLCLOW_3
O
STS_MODE = 1: STS-48 receive channel 3 local orderwire.
STS_MODE = 0: Not used.
AN20
RSUSER_3
O
STS_MODE = 1: STS-48 receive channel 3 section user channel.
STS_MODE = 0: Not used.
AP21
ROW_CLK_3
O
STS_MODE = 1: STS-48 receive channel 3 orderwire/user clock.
STS_MODE = 0: Not used.
AN22
RLDCC_3
O
STS_MODE = 1: STS-48 receive channel 3 line DCC.
STS_MODE = 0: Not used.
AP22
RLD_CLK_3
O
STS_MODE = 1: STS-48 receive channel 3 line DCC clock.
STS_MODE = 0: Not used.
Name/Description
1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
38
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 10. Pin Descriptions—Transport Overhead Interface (continued)
Pin
Symbol
Type1
AR21
RSDCC_3
O
STS_MODE = 1: STS-48 receive channel 3 section DCC.
STS_MODE = 0: Not used.
AM20
RSD_CLK_3
O
STS_MODE = 1: STS-48 receive channel 3 section DCC clock.
STS_MODE = 0: Not used.
AR22
ROHDAT_3_0
O
STS_MODE = 1: STS-48 receive channel 3 TOH data (LSB).
STS_MODE = 0: Receive STS-1 channels 97—144 TOH data (LSB).
AL21
ROHDAT_3_1
O
STS_MODE = 1: STS-48 receive channel 3 TOH data (MSB).
STS_MODE = 0: Receive STS-1 channels 97—144 TOH data (MSB).
AM21
ROHFP_3
O
STS_MODE = 1: STS-48 receive channel 3 TOH frame pulse.
STS_MODE = 0: Receive STS-1 channels 97—144 TOH frame pulse.
AN21
ROH_CLK_3
O
STS_MODE = 1: STS-48 receive channel 3 TOH clock.
STS_MODE = 0: Receive STS-1 channels 97—144 TOH clock.
E22
TEXPOW_3
I
STS_MODE = 1: STS-48 transmit channel 3 express orderwire.
STS_MODE = 0: Not used.
C22
TLCLOW_3
I
STS_MODE = 1: STS-48 transmit channel 3 local orderwire.
STS_MODE = 0: Not used.
D22
TSUSER_3
I
STS_MODE = 1: STS-48 transmit channel 3 section user channel.
STS_MODE = 0: Not used.
B23
TOW_CLK_3
O
STS_MODE = 1: STS-48 transmit channel 3 orderwire/user clock.
STS_MODE = 0: Not used.
E23
TLDCC_3
I
STS_MODE = 1: STS-48 transmit channel 3 line DCC.
STS_MODE = 0: Not used.
C23
TLD_CLK_3
O
STS_MODE = 1: STS-48 transmit channel 3 line DCC clock.
STS_MODE = 0: Not used.
A24
TSDCC_3
I
STS_MODE = 1: STS-48 transmit channel 3 section DCC.
STS_MODE = 0: Not used.
D23
TSD_CLK_3
O
STS_MODE = 1: STS-48 transmit channel 3 section DCC clock.
STS_MODE = 0: Not used.
B24
TOHDAT_3_0
I
STS_MODE = 1: STS-48 transmit channel 3 TOH data (LSB).
STS_MODE = 0: Transmit STS-1 channels 97—144 TOH data (LSB).
C24
TOHDAT_3_1
I
STS_MODE = 1: STS-48 transmit channel 3 TOH data (MSB).
STS_MODE = 0: Transmit STS-1 channels 97—144 TOH data (MSB).
D24
TOHEN_3
I
STS_MODE = 1: STS-48 transmit channel 3 TOH insert enable.
STS_MODE = 0: Transmit STS-1 channels 97—144 TOH insert enable.
A25
TOHFP_3
O
STS_MODE = 1: STS-48 transmit channel 3 TOH frame pulse.
STS_MODE = 0: Transmit STS-1 channels 97—144 TOH frame pulse.
Name/Description
1. I = input, O = output. All I/O not explicitly stated with a buffer type 3.3 V TTL.
Agere Systems Inc.
39
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 10. Pin Descriptions—Transport Overhead Interface (continued)
Pin
Symbol
Type1
E24
TOH_CLK_3
O
STS_MODE = 1: STS-48 transmit channel 3 TOH clock.
STS_MODE = 0: Transmit STS-1 channels 97—144 TOH clock.
AP20
REXPOW_4
O
STS_MODE = 1: STS-48 receive channel 4 express orderwire.
STS_MODE = 0: Not used.
AL19
RLCLOW_4
O
STS_MODE = 1: STS-48 receive channel 4 local orderwire.
STS_MODE = 0: Not used.
AL17
RSUSER_4
O
STS_MODE = 1: STS-48 receive channel 4 section user channel.
STS_MODE = 0: Not used.
AP18
ROW_CLK_4
O
STS_MODE = 1: STS-48 receive channel 4 orderwire/user clock.
STS_MODE = 0: Not used.
AM19
RLDCC_4
O
STS_MODE = 1: STS-48 receive channel 4 line DCC.
STS_MODE = 0: Not used.
AN19
RLD_CLK_4
O
STS_MODE = 1: STS-48 receive channel 4 line DCC clock.
STS_MODE = 0: Not used.
AR17
RSDCC_4
O
STS_MODE = 1: STS-48 receive channel 4 section DCC.
STS_MODE = 0: Not used.
AN17
RSD_CLK_4
O
STS_MODE = 1: STS-48 receive channel 4 section DCC clock.
STS_MODE = 0: Not used.
AP19
ROHDAT_4_0
O
STS_MODE = 1: STS-48 receive channel 4 TOH data (LSB).
STS_MODE = 0: Receive STS-1 channels 145—192 TOH data (LSB).
AN18
ROHDAT_4_1
O
STS_MODE = 1: STS-48 receive channel 4 TOH data (MSB).
STS_MODE = 0: Receive STS-1 channels 145—192 TOH data (MSB).
AL18
ROHFP_4
O
STS_MODE = 1: STS-48 receive channel 4 TOH frame pulse.
STS_MODE = 0: Receive STS-1 channels 145—192 TOH frame pulse.
AM18
ROH_CLK_4
O
STS_MODE = 1: STS-48 receive channel 4 TOH clock.
STS_MODE = 0: Receive STS-1 channels 145—192 TOH clock.
D19
TEXPOW_4
I
STS_MODE = 1: STS-48 transmit channel 4 express orderwire.
STS_MODE = 0: Not used.
E19
TLCLOW_4
I
STS_MODE = 1: STS-48 transmit channel 4 local orderwire.
STS_MODE = 0: Not used.
B19
TSUSER_4
I
STS_MODE = 1: STS-48 transmit channel 4 section user channel.
STS_MODE = 0: Not used.
D20
TOW_CLK_4
O
STS_MODE = 1: STS-48 transmit channel 4 orderwire/user clock.
STS_MODE = 0: Not used.
B20
TLDCC_4
I
STS_MODE = 1: STS-48 transmit channel 4 line DCC.
STS_MODE = 0: Not used.
A21
TLD_CLK_4
O
STS_MODE = 1: STS-48 transmit channel 4 line DCC clock.
STS_MODE = 0: Not used.
Name/Description
1. I = input, O = output. All I/O not explicitly stated with a buffer type 3.3 V TTL.
40
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 10. Pin Descriptions—Transport Overhead Interface (continued)
Pin
Symbol
Type1
C20
TSDCC_4
I
STS_MODE = 1: STS-48 transmit channel 4 section DCC.
STS_MODE = 0: Not used.
B21
TSD_CLK_4
O
STS_MODE = 1: STS-48 transmit channel 4 section DCC clock.
STS_MODE = 0: Not used.
C21
TOHDAT_4_0
I
STS_MODE = 1: STS-48 transmit channel 4 TOH data (LSB).
STS_MODE = 0: Transmit STS-1 channels 145—192 TOH data (LSB).
E21
TOHDAT_4_1
I
STS_MODE = 1: STS-48 transmit channel 4 TOH data (MSB).
STS_MODE = 0: Transmit STS-1 channels 145—192 TOH data (MSB).
D21
TOHEN_4
I
STS_MODE = 1: STS-48 transmit channel 4 TOH insert enable.
STS_MODE = 0: Transmit STS-1 channels 145—192 TOH insert enable.
B22
TOHFP_4
O
STS_MODE = 1: STS-48 transmit channel 4 TOH frame pulse.
STS_MODE = 0: Transmit STS-1 channels 145—192 TOH frame pulse.
A22
TOH_CLK_4
O
STS_MODE = 1: STS-48 transmit channel 4 TOH clock.
STS_MODE = 0: Transmit STS-1 channels 145—192 TOH clock.
Name/Description
1. I = input, O = output. All I/O not explicitly stated with a buffer type are 3.3 V TTL.
Agere Systems Inc.
41
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 11. Pin Descriptions—Microprocessor Interface
Pin
Symbol
Type1
Name/Description
C14
PCLK
I
Microprocessor Clock. This clock can operate at up to 78 MHz when the
microprocessor interface is in asynchronous mode (MPMODE = 0). This
clock can operate to a maximum of 40 MHz when the microprocessor interface is in synchronous mode (MPMODE = 1).
A14
CS_N
I
Chip Select (Active-Low). This signal must be low during register access.
E15
TS_N
(AS_N)
I
Transfer Start or Address Strobe (Active-Low).
Transfer start (TS_N) when MPMODE = 1 (synchronous).
Address strobe (AS_N) when MPMODE = 0 (asynchronous).
D15
DS_N
I
Data Strobe (Active-Low). This signal, when used in the asynchronous
mode (MPMODE = 0), indicates that the data is valid for MPU writes.
B14
RW_N
I
Read/Write. This signal is used to indicate a read or write operation.
1 = Read.
0 = Write.
B13
TA_N
O
Data Transfer Acknowledge (Active-Low). This signal goes low to
acknowledge the completion of a data transfer cycle.
C13
TEA_N
O
Transfer Error Acknowledge (Active-Low). This signal goes low to indicate an internal error related to the data transfer cycle. This is used only
when the microprocessor interface is in synchronous mode (MPMODE = 1).
D13
INT_N
O
Interrupt (Active-Low). This signal goes low when the device generates an
unmasked interrupt. The interrupt signal is cleared when the unmasked raw
alarm that generated the interrupt is cleared.
C19
ADDRESS_15
I
A19
ADDRESS_14
I
Address Bus [15:0]. This bus is used to address registers. ADDRESS_15
is the MSB, ADDRESS_0 is the LSB.
B18
ADDRESS_13
I
D18
ADDRESS_12
I
E18
ADDRESS_11
I
C18
ADDRESS_10
I
B17
ADDRESS_9
I
C17
ADDRESS_8
I
D17
ADDRESS_7
I
E17
ADDRESS_6
I
B16
ADDRESS_5
I
C16
ADDRESS_4
I
D16
ADDRESS_3
I
A15
ADDRESS_2
I
B15
ADDRESS_1
I
C15
ADDRESS_0
I
1. I/O = bidirectional pin, I = input, O = output. All I/O not explicitly stated with a buffer type are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V
at their inputs or outputs.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 11. Pin Descriptions—Microprocessor Interface (continued)
Pin
Symbol
Type1
Name/Description
A9
DATA_15
I/O
E10
DATA_14
I/O
Data Bus [15:0]. This bus is a bidirectional data bus for writing and reading software
registers. DATA_15 is the MSB, DATA_0 is the LSB.
D10
DATA_13
I/O
C10
DATA_12
I/O
B10
DATA_11
I/O
A10
DATA_10
I/O
D11
DATA_9
I/O
C11
DATA_8
I/O
B11
DATA_7
I/O
A11
DATA_6
I/O
E12
DATA_5
I/O
D12
DATA_4
I/O
C12
DATA_3
I/O
B12
DATA_2
I/O
A12
DATA_1
I/O
E13
DATA_0
I/O
C9
PARITY_0
I/O
Data Bus Parity—Lower Byte. Odd parity for lower byte [7:0], when MPMODE = 1
(synchronous). Unused when MPMODE = 0 (asynchronous); may be left unconnected if not used.
B9
PARITY_1
I/O
Data Bus Parity—Upper Byte. Odd parity for upper byte [15:8], when MPMODE = 1
(synchronous). Unused when MPMODE = 0 (asynchronous); may be left unconnected if not used.
1. I/O = bidirectional pin, I = input, O = output. All I/O not explicitly stated with a buffer type are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V
at their inputs or outputs.
Table 12. Pin Descriptions—JTAG Interface
Pin
1
Symbol Type
Name/Description
AM29
TCK
Id
AN30
TMS
Id
Test Mode Select. Controls test operations. TMS is sampled on the rising edge of
TCK.
AL29
TDI
Id
Test Data In. TDI is sampled on the rising edge of TCK.
AM30
TDO
O
Test Data Out. This output is updated on the falling edge of TCK. The TDO output is
3-stated except when scanning out test data.
Iu
Test Reset (Active-Low). This signal provides an asynchronous reset for the TAP.
This input should be tied low (to VSS) for normal device operation. If TRST_N is high, a
TCK must be present to ensure that the correct test mode is clocked in on the TMS
input.
AP30 TRST_N
Test Clock. This signal provides timing for test operations.
1. O = output, Id = input with internal pull-down resistor, Iu = input with internal pull-up resistor. The value of all internal pull-up/pull-down
resistors is 50 kΩ. All I/O not explicitly stated with a buffer type are 5 V tolerant, 3.3 V TTL. They will tolerate 5 V at their inputs or outputs.
Agere Systems Inc.
43
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 13. Pin Descriptions—PLL References
Pin
Symbol
Type1
G2
REXT_ADD
I
External PLL Bypass Resistor for Add Interface. Should be externally
connected through a 100 kΩ resistor to analog ground (VSSA).
V3
REXT_DRP1
I
External PLL Bypass Resistor for Drop Interface STS-48 #1. Should be
externally connected through a 100 kΩ resistor to analog ground (VSSA).
AA5
REXT_DRP2
I
External PLL Bypass Resistor for Drop Interface STS-48 #2. Should be
externally connected through a 100 kΩ resistor to analog ground (VSSA).
AD5
REXT_DRP3
I
External PLL Bypass Resistor for Drop Interface STS-48 #3. Should be
externally connected through a 100 kΩ resistor to analog ground (VSSA).
AJ3
REXT_DRP4
I
External PLL Bypass Resistor for Drop Interface STS-48 #4. Should be
externally connected through a 100 kΩ resistor to analog ground (VSSA).
Name/Description
1. I = input. All inputs in Table 13 are 3.3 V TTL.
Table 14. Pin Descriptions—Power and Ground
Pin
Symbol
Type1
A1, A2, A17,
A18, A34, A35,
B1, B2, B34,
B35, C3, C33,
E11, E25, L5,
L31, U35, V1,
V35, W1, AE5,
AE31, AL11,
AL25, AN3,
AN33, AP1, AP2,
AP34, AP35,
AR1, AR2,
AR18, AR19,
AR34, AR35
VDD
P
3.3 V Positive Supply Voltage.
A5, A6, A30,
A31, D4, D32,
E1, E5, E16,
E20, E31, E35,
F1, F35, T5, T31,
Y5, Y31, AK1,
AK35, AL1, AL5,
AL16, AL20,
AL31, AL35,
AM4, AM32,
AR5, AR6,
AR30, AR31
VDD2
P
2.5 V Positive Supply Voltage.
Name/Description
1. P = power, G = ground.
44
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 14. Pin Descriptions—Power and Ground (continued)
Pin
Symbol
Type1
A3, A4, A7,
A8, A13, A16,
A20, A23,
A28, A29,
A32, A33, B3,
B4, B32, B33,
C1, C2, C4,
C32, C34,
C35, D1, D2,
D3, D33, D34,
D35, G1, G35,
H1, H35, N1,
N35, T1, T35,
Y1, Y35, AC1,
AC35, AH1,
AH35, AJ1,
AJ35, AM1,
AM2, AM3,
AM33, AM34,
AM35, AN1,
AN2, AN4,
AN32, AN34,
AN35, AP3,
AP4, AP32,
AP33, AR3,
AR4, AR7,
AR8, AR13,
AR16, AR20,
AR23, AR28,
AR29, AR32,
AR33
VSS
G
Digital Ground.
J4, T2, Y4,
AD2, AH3
VDDA
P
Analog Positive Supply Voltage for PLL Circuits. 3.3 Vdc supply for
PLL circuitry. Each should be connected in such a way that EMI is
decoupled between VDDAs, and to or from VDD. The maximum analog
PLL power is 350 mW for the device.
Name/Description
■
■
J5, T3, Y3,
AD1, AH2
VSSA
G
J4 is the power supply for the add interface PLL.
T2, Y4, AD2, and AH3 are the power supplies for the drop interface
PLLs.
Analog Ground for PLL Circuits. Ground for the PLL circuitry. These
should be connected to VSS in a manner appropriate to minimize EMI
between VSSA pins, and between VSS and VSSA.
■
■
J5 is the analog ground for the add interface PLL.
T3, Y3, AD1, and AH2 are the analog grounds for the drop interface
PLLs.
1. P = power, G = ground.
Agere Systems Inc.
45
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Pin Information (continued)
Table 14. Pin Descriptions—Power and Ground (continued)
Pin
Symbol
Type1
Name/Description
AP6, AL7, AN16,
AM16
PULLUP
—
Manufacturing Test. These pins must be individually pulled up to
VDD2 through 47 kΩ resistors for normal operation.
AM5, AN5, AP5,
AL6, AM6, AN6,
AM7, AN7, AP7,
AL10, AM10,
AN10, AP10,
AR10, AN28,
AM28, AL28,
AP29
PULLDN
—
Manufacturing Test. These pins must be individually pulled
down to VSS through 47 kΩ resistors for normal operation.
AL8, AL9, AM8,
AM9, AN8, AN9,
AP8, AP9, AN29,
AR9, D262, E272,
G32, H42, J12,
K32, K312, L32,
M332, N22, N52,
P42, R32, T42,
T322, U22, U32,
U312, Y22, AB12,
AC22, AC52, AF12,
AG12, AH342,
AJ22, AK42
NC
—
No Connect. Do not connect to these pins.
1. P = power, G = ground.
2. No connect (NC) pins indicated with a footnote (2) are unused. There is no connection between the pin and the die.
Table 15. Pin Summary
Pin Type
Pin Direction
Count
LVDS
Input
Output
Reference
Input
Output
Bidirectional
NC
Other (Manufacturing Test)
Power
Ground
76
96
27
81
93
20
37
20
73
77
Total
600
TTL
46
Agere Systems Inc.
Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Functional Description
Receive STS-192 Line Interface
The receive STS-192 line interface is configured to accept either a single 16-bit wide serial STS-192 stream at
622.08 MHz or four 4-bit wide serial STS-48 streams at 622.08 MHz, and convert them to four STS-48 streams.
The conversion process is essentially the same for both input formats, except that for STS-48 data, each function
is divided into four independent blocks running on separate clocks, while the STS-192 data is processed in one
block and must be passed through a time-slot interchange (TSI) block after the conversion process to demultiplex
its four constituent STS-48 channels.
Regardless of which line format is being used, each input serial stream is first byte and frame aligned by passing it
through a bit rotator to align it. The frame alignment used by the bit rotator is determined by a framer circuit which
monitors the nonaligned word. The data from the bit rotator is then passed to a BIP-8 parity calculator before being
optionally descrambled.
The descrambled data is then either passed directly to one of the STS-48 processing modules when in STS-48
mode, or first passed to a TSI when in STS-192 mode. This TSI reorders the STS-1 slots within the STS-192 to
appear as four STS-48 signals, as required by the STS-48 processing modules.
In STS-192 mode, all 16 data streams are clocked on the positive edge of R_CLK_1. In STS-48 mode, the four
data streams associated with each STS-48 are clocked in on the positive edge of a corresponding clock,
R_CLK_n.
Loss-of-Signal (LOS) Detector
Before the data is optionally descrambled, it is monitored for loss-of-signal (LOS). In STS-192 mode, there is a single LOS detector. In STS-48 mode, there is a separate LOS detector on each STS-48 input. On powerup, an LOS
defect is declared if all zeros data is received continuously for 13.8 µs. This time threshold is provisionable through
the loss-of-signal (LOS) threshold register for each channel, and can be set to any value from 0 µs (i.e., LOS
detection disabled) to 105 µs, with a resolution of 102.88 ns (64 times the period of the 622.08 MHz clock).
The LOS defect is subsequently cleared when two successive valid framing patterns are received with no period of
all zeros exceeding the time threshold. Detection of an LOS defect is indicated by a latched alarm status bit, a persistency bit, and a one second PM bit being set in the corresponding LTE receive channel n registers. In addition,
alarm indication signal (AIS) will be inserted by the framer block in all 48 or 192 STS-1 channels affected.
If an optical transponder is connected to the receive line interface, the most appropriate method to declare LOS is
by monitoring the power level monitor of the received signal from the transponder. In some transponders, the
amplifier gain is high enough to cause the LVDS receive data lines to move above zero, even when there is no
optical input. Should this occur, the TSOT0410G4 might not indicate an LOS defect. This is not a deficiency of the
devices, but is a characteristic of the methods of detecting LOS.
If an optical transponder is used, the LOS detector of the TSOT0410G4 monitors the connection from the transponder to the receive line interface. The LOS detector in the TSOT0410G4 is appropriate for monitoring LOS in
an electrical SONET or SDH system.
Agere Systems Inc.
47
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Note: Register summary tables occur throughout the Functional Description section on page 47, and describe the
first occurrence of registers that are used for a particular function. Refer to the register map (Table 71 on
page 97) for details on other occurrences of similar registers.
Table 16. LOS Detector Register Summary
Function
LOS Detect Time
Latched LOS Alarm
LOS Persistency
LOS One Second PM
Register Name
(First Occurrence)
Register Bits
Qty.1
1st Page3
Addr2
(hex)
LTE Receive Channel 1 Loss-of-Signal
(LOS) Threshold (R/W)
LTE_RX_n_LOS_
THRESHOLD1[9:0]
4
1402
123
LTE Receive Channel 1
Service-Affecting Interrupt Alarm
(W1C)
LOS
4
1405
124
LTE Receive Channel 1
Service-Affecting Persistency Alarm
(RO)
LOS_PER
4
1407
124
LTE Receive Channel 1 Performance
Monitoring (RO)
LOS_PM
4
140B
127
1. Qty. refers to the number of registers that are similar to the one shown in the table. There may be more registers to control different channels, or several registers of similar type used for a particular function.
2. 1st Addr refers to the address (in hex) of the first occurrence of this type of register.
3. Page refers to the relevant page number in this document.
Framer (A1 and A2)
In STS-192 mode, when in frame, the framer outputs byte-aligned and frame-aligned data. In STS-48 mode, framing is performed on four independent channels. Frame timing, parity generation, and AIS insertion are also performed.
Enhanced framing, where every other A1 and A2 byte is inverted to better maintain the dc balance on the optical
line, is also supported in STS-192 mode.
A1A1A1A1 . . . A1A1 = F609F609 . . . F609.
A2A2A2A2 . . . A2A2 = 28D728D7 . . . 28D7.
The STS-192 framer is described below. The STS-48 framer is similar. Enhanced framing is not used when in
STS-48 mode (it is not part of the SONET/SDH specifications). Bit 1 of registers 0x1C00, 0x1D00, 0x1E00, and
0x1F00 should be set to normal mode when the TSOT0410G4 is operating in STS-48 mode.
Framer FSM. The framer FSM is responsible for determining the severely errored framing (SEF) and loss-of-framing (LOF) SONET framing alarms for each channel. The framer FSM is shown in Figure 4 on page 49.
The FSM comes out of reset in the SEF state with the SEF and LOF alarms active. The framing pattern used is the
16-bit word consisting of the last A1 byte, the first A2 byte, plus two additional A1 bytes. The first occurrence of the
framing pattern transfers the FSM to the frame confirm state. Frame timing is also synchronized. Another framing
pattern match coincident with expected frame timing transfers the state to in frame (i.e., it takes two consecutive
valid framing patterns to frame to an incoming signal). Outside the SEF and frame confirm states, the SEF alarm
output is inactive. As shown in the FSM, when in frame, it requires four consecutive framing errors to be transferred
back to the SEF state.
■
■
The LOF alarm is asserted if SEF persists for 24 frames (3 ms).
The LOF alarm is terminated eight frames (1 ms) after the SEF alarm is terminated (i.e., eight frames after the
FSM enters the in-frame state), provided the SEF state is not re-entered (as per SONET objectives).
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
IN
FRAME
FRAMING PATTERN
CONFIRMED
FOUR CONSECUTIVE
FRAMING ERRORS
FRAME
CONFIRM
FRAMING PATTERN
NOT COMFIRMED
FRAMING PATTERN
FOUND
SEF
RESET
5-8401(F).a
Figure 4. Framer FSM
The framing pattern is a subset of the A1A2 STS-N pattern. This design uses the 16-bit A1A2 boundary as the
framing pattern which evaluates to an average SEF defect occurrence time of 31.79 minutes, assuming a Poisson
bit error rate (BER) of 10–3. This is greater than the minimum average SONET requirement of 6 minutes.
The SEF alarm is reported by a latched register bit in the LTE receive nonservice-affecting alarm register for the
respective channel. The LOF alarm is reported by a latched register bit in the LTE receive service-affecting alarm
register for the respective channel. In addition, a persistency bit for LOF exists in the LTE receive service-affecting
persistency register. Detection of LOF and SEF defects are also indicated by the LTE receive last second PM register.
On powerup, detection of an LOF defect causes AIS to be inserted in all affected STS-1 channels by the framer.
During AIS insertion, transport overhead (TOH) processing is disabled. This AIS insertion can be disabled using
the LOF AIS disable control register bit for each channel, or replaced by insertion upon SEF detection using the
SEF AIS disable control bit. Another control bit is the enhanced framing mode. These control bits are part of the
LTE receive provisioning register for the respective channel. The framer is also responsible for sourcing parity with
the framed channels. Parity errors can be forced using the chip-level maintenance register.
Agere Systems Inc.
49
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 17. Framer Register Summary
Function
Enhanced Framing
AIS Insertion on SEF, LOF
LOF Latched Alarm
SEF Latched Alarm
LOF Persistency
LOF, SEF One Second PM
Forcing Parity Errors
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Receive Channel 1
Provisioning (R/W)
LTE Receive Channel 1
Provisioning (R/W)
LTE Receive Channel 1
Service-Affecting Interrupt Alarm
(W1C)
LTE Receive Channel 1
Nonservice-Affecting Interrupt
Alarm (W1C)
LTE Receive Channel 1
Service-Affecting Persistency
Alarm (RO)
LTE Receive Channel 1
Performance Monitoring (RO)
Chip-Level Maintenance (R/W)
ENH_FRMG_CTL_1
4
1400
122
SEF_AIS_DIS_1
LOF_AIS_DIS_1
LOF
4
1400
122
4
1405
124
SEF
4
1408
125
LOF_PER
4
1407
124
LOF_PM
SEF_PM
FRC_PAR_ERR
4
140B
127
1
0005
112
Descrambler
The data from the framer is descrambled using the SONET/SDH standard generator polynomial: 1 + x6 + x7. The
descrambling can be disabled through the DESCRM_DIS bit in the LTE receive channel provisioning register for
each channel.
Table 18. Descrambler Register Summary
Function
Descrambling Control
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Receive Channel 1
Provisioning (R/W)
DESCRM_DIS_1
4
1400
122
Time-Slot Interchanger (TSI)
For STS-192 data, the input stream must be demultiplexed to create four STS-48 data streams for further processing. The TSI reorders the data so that the STS-192 is divided into its four constituent STS-48 data streams.
Table 19 on page 51 shows the order of the bytes belonging to the individual STS-1s, or STS-1, components of an
STS-Nc that comprise the STS-192 as it enters the TSI. Table 20 on page 51 shows the order of bytes after the TSI
(STS-48 byte ordering). In the tables, the bytes arrive starting in the top left of the table, and then down each column. The STS-48 table should be interpreted as four simultaneous data streams, where the bytes are ordered
starting with the top left of each channel, and then down each column.
If the TSOT0410G4 is in STS-48 mode, the data is received on all four channels and the TSI is bypassed.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 19. STS-192 Byte Ordering
Time (Top to Bottom, Then Left to Right) ⇒
1
4
7
10
13
16
19
22
25
28
31
34
37
40
43
46
49
52
55
58
61
64
67
70
73
76
79
82
85
88
91
94
97
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
166
169
172
175
178
181
184
187
190
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
74
77
80
83
86
89
92
95
98
101
104
107
110
113
116
119
122
125
128
131
134
137
140
143
146
149
152
155
158
161
164
167
170
173
176
179
182
185
188
191
3
6
9
12
15
18
21
24
27
30
33
36
39
42
45
48
STS-192
Number
51
54
57
60
63
66
69
72
75
78
81
84
87
90
93
96
99
102
105
108
111
114
117
120
123
126
129
132
135
138
141
144
147
150
153
156
159
162
165
168
171
174
177
180
183
186
189
192
1
Table 20. STS-48 Byte Ordering
Time (Top to Bottom, Then Left to Right for Each STS-48 Channel) ⇒
1
4
7
10
49
52
55
58
97
100
103
106
145
148
151
154
13
16
19
22
61
64
67
70
109
112
115
118
157
160
163
166
25
28
31
34
73
76
79
82
121
124
127
130
169
172
175
178
37
40
43
46
85
88
91
94
133
136
139
142
181
184
187
190
2
5
8
11
50
53
56
59
98
101
104
107
146
149
152
155
14
17
20
23
62
65
68
71
110
113
116
119
158
161
164
167
26
29
32
35
74
77
80
83
122
125
128
131
170
173
176
179
38
41
44
47
86
89
92
95
134
137
140
143
182
185
188
191
3
6
9
12
51
54
57
60
99
102
105
108
147
150
153
156
15
18
21
24
63
66
69
72
111
114
117
120
159
162
165
168
27
30
33
36
75
78
81
84
123
126
129
132
171
174
177
180
STS-48
Number
39
42
45
48
87
90
93
96
135
138
141
144
183
186
189
192
1
2
3
4
Note: STS-12 byte ordering is shown in Table 29 on page 62.
Agere Systems Inc.
51
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Receive Transport Overhead (TOH) Processor
This block is responsible for terminating the transport overhead and is replicated four times. Each block accepts
the frame and byte-aligned data for one STS-48 channel and extracts the transport section and line overhead. The
extracted overhead is then either stored internally, or provided externally on a serial output, and may also be further processed for alarm or performance monitoring purposes.
In STS-48 mode, each channel is synchronized to a separate clock and carries complete transport overhead. In
STS-192 mode, all channels are synchronized to the same clock and only the first STS-48 carries complete transport overhead, while the other channels only carry line BIP-8. The definition and associated storage or processing
of each byte is detailed in the subsections that follow.
All processing of overhead bytes is inhibited while the following alarm defects are detected:
■
LOS (if not disabled)
■
LOF (if AIS insertion is enabled)
■
SEF (if AIS insertion is enabled)
■
Line AIS (only the line overhead bytes are inhibited)
Receive Overhead Serial Links
In addition to the individual storage or external availability of the overhead bytes described below, the full set of
transport overhead bytes for each STS-48 channel (1296 bytes) are serialized and output on the ROHDAT_n_[1:0]
pins. The bytes are sent, MSB first, with each pair of bits output on the positive edge of ROH_CLK_n
(41.472 MHz). The location of the MSB of the first A1 byte is identified by the ROHFP_n output going high.
In STS-48 mode, each pair of ROHDAT_n_[1:0] pins transmits the transport overhead for an STS-48 channel. In
STS-192 mode, the four pairs of ROHDAT_n_[1:0] pins transmit the entire STS-192 overhead (5184 bytes), where
the ROHDAT1 pins transmit STS channels 1 through 48, and the ROHDAT2, ROHDAT3, and ROHDAT4 pins
transmit STS channels 49 through 96, 97 through 144, and 145 through 192, respectively. The timing for this is
described in the Receive Overhead Serial Link section on page 175.
Each interface determines its ROHFP by sampling the Rx frame using a metastable hand-off. Even in 10 Gbits/s
mode, where the RXCLK and ROHCLK are the same, the different delays on the signals in each channel will create the potential for the metastable handlers to sample the channels, ±1 clock cycles, of each other. This is
unavoidable due to the possibility of the four channels being asynchronous. Any external logic that interfaces to
ROHDAT should synchronize to each of the four channels independently using the individual ROHFP signals.
Internally, a memory is used for each channel to buffer the data and transfer it between the internal processing rate
and the external data rate. This allows for the data to be transmitted in a nongapped manner. The operation of the
memory is monitored using parity, and any errors are reported using the ROHDAT parity error alarm bit. This alarm
bit is present in the corresponding LTE receive channel n nonservice affecting interrupt alarm register and is valid
regardless of the mode (STS-48 or STS-192) in which the device is operating.
During AIS insertion due to LOS, LOF, or SEF (provisionable), 0xFF is constantly output for the overhead byte values.
Table 21. Receive Overhead Serial Links Register Summary
Function
Parity Alarm
52
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C)
RX_OH_MEM_PAR_
ERR_1
4
1408
125
Agere Systems Inc.
Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Functional Description (continued)
Section Trace (J0)
The section trace byte is present in the first STS-1 of the STS-48 or STS-192 only. Specified by the J0 message
type control bit, the TOH processor supports extraction of either SONET 64-byte (ASCII, <CR><LF> terminated) or
SDH 16-byte (E.164) section trace messages that are stored in internal memory. Processing of the received message then depends on the J0 message mode control bit. The content of the message is either monitored for a mismatch from a provisioned expected message or monitored for a sustained change (validation) in the received
message.
If the J0 message mode control bit is set to the provisioned mode, then the incoming message is compared against
the software programmed expected message. The expected message is stored in internal memory for each
STS-48 channel. A mismatch is declared if a consistent received message differs from the expected message for
ten consecutive messages. The mismatch clears when four out of five received messages match the expected
message (fixed windowing is used for clearing). This mismatch state is reflected in the J0 message mismatch
alarm bit.
When the J0 message mode control bit is set to the validated mode, the incoming message is monitored for a sustained change. A sustained change is detected when the received message differs from the last stable message
for ten consecutive messages. The new message then becomes the stable message, is stored in internal memory,
and the processor starts checking for a sustained change from this new stable message (i.e., there is no clearing
criteria for a sustained change). The J0 new message alarm bit is set when a sustained change is detected.
Selection of the message type, SONET or SDH format, and the content monitoring mode (provisioned or validated), are provisionable on a per STS-48 channel basis through a corresponding LTE receive channel n maintenance register. The associated alarms for the two modes are reported in the LTE receive channel n
nonservice-affecting interrupt alarm register.
The expected messages for all channels are provisioned through the microprocessor interface using the 64-byte
J0 access message buffer. This message buffer is also used to read the contents of the expected, stable, or
received messages for all channels. Accesses using the data buffer are paged according to direction (transmit and
receive), STS-48 channel, and message type (expected/stable or received) through the use of the section trace
access register. If the J0 message mode is set to the provisioned mode, the expected message is accessible. If the
J0 message mode is set to the validated mode, then the stable message is accessible. Once the section trace
access register is configured, the actual access is triggered by writing a 0x0001 value to the section trace access
start register. The transfer from internal memory to/from the message buffer is performed on the next message
boundary. Completion of the access is indicated by the access done flag being set in the section trace access status register.
Note: To insert J0 into the transmit stream, 0x0020 must be written register 0x1C01 (the enable insertion of provisioned J0 message register). See Table 137 on page 131 for detailed register information.
Internally, a memory is used to store the currently received section trace message as well as the stable or provisioned message. The operation of the memory is monitored using parity, and any errors are reported using the J0
parity error alarm bit.
Agere Systems Inc.
53
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 22. J0 Register Summary
Function
Message Type Control
Message Mode
(Provisioned or
Validated)
Message Mismatch
Latched Alarm
Register Name
(First Occurrence)
Register Bits
Qty.
LTE Receive Channel 1 Maintenance
(R/W)
LTE Receive Channel 1 Maintenance
(R/W)
J_MSG_TYPE_1
4
1401
123
J_MSG_MODE_1
4
1401
123
4
1408
125
4
1408
125
32
1110
118
1
1100
117
1
1102
118
1
1101
118
4
1408
125
LTE Receive Channel 1
J_MSG_MISMATCH_INT
Nonservice-Affecting Interrupt Alarm
_1
(W1C)
J_NEW_MSG_INT_1
New Message Latched
LTE Receive Channel 1
Alarm
Nonservice-Affecting Interrupt Alarm
(W1C)
J0 Access Message Buffer J0 Access Message Buffers 1—32
LTE_J_ACCESS_
(R/W)
BUF_n[15:0]
Message Buffer Access
Section Trace (J0) Access
All bits
Control
Maintenance (R/W)
Message Buffer Access
J0 Access Message Start (WO)
LTE_J_ACCESS_MSG_
Start
START
Message Buffer Access
J0 Access Done (W1C)
J_ACCESS_DONE_
Complete Flag
FLAG
Buffer Parity Error Latched
LTE Receive Channel 1
J_MEM_PARITY_
Alarm
Nonservice-Affecting Interrupt Alarm
ERR_1S
(W1C)
1st Page
Addr
(hex)
Section Growth (Z0)
No receive function has currently been defined for the section growth byte present in the remaining STS-1 locations of the STS-48 or STS-192 J0 byte.
Section BIP-8 (B1)
The section BIP-8 byte is located in the first STS-1 of the STS-48 or STS-192 only, and carries the even parity of the
scrambled data in the previous STS-48 or STS-192 frame. In every frame, the received B1 value is extracted and
compared to the calculated BIP-8 for the previous frame. Errors in the BIP-8 code are tabulated in an internal 16-bit
counter based on either bit or block errors as provisioned for each channel through the B1 BIP mode control bit.
In bit mode (selected by default), each BIP-8 bit in error causes the counter to increment. If block error is selected,
each BIP-8 code in error causes the counter to increment only once. Regardless of which mode is selected, the
value in the counter is transferred to the section coding violation (CV-S) register on the positive edge of PM_CLK,
at which point the counter is cleared. The counter will stop at the maximum value and will not roll over.
Section BIP-8 (B1) Errors Serial Access
The errors detected in section BIP-8 byte are located in the first STS-1 of the STS-48 or STS-192 and can optionally be extracted serially on the local the ROHDAT interface. See the Receive Overhead Serial Links section on
page 52 for details on the ROHDAT interface.
A provisioning bit (B1_ERROR_MASK_EN (bit 7)) is provided in each LTE Rx channel provisioning register as a
B1 error mask enable. When the B1_ERROR_MASK_EN bit is set, the B1 byte in ROHDAT is replaced with the B1
error mask from the previous frame. An error in the Rx B1 BIP-8 code will result in the corresponding bit in the error
mask being set for one frame, with a one-frame delay due to retiming.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
The ROHDAT interface B1 error mask extraction is enabled by provisioning the B1_ERROR_MASK_EN bit in the
LTE Rx channel provisioning registers (0x1400, 0x1500, 0x1600, and 0x1700 respectively). (See Table 110 on
page 122.) The appropriate bit definitions are shown in Table 23. The B1 error mask extract feature is always supported on individual STS-48 channels and will require all four channels to be provisioned in STS-192 mode.
Table 23. B1 Register Summary
Function
B1 Error Bit Enable
Bit Error/Block Error
Control
Last Second Coding
Violations Count
Register Name
(First Occurrence)
Register Bits
LTE Receive Channel 1 Provisioning (R/W) B1_ERROR_MASK_EN
LTE Receive Channel 1 Provisioning (R/W)
B1_BIP_MODE_1
4
4
1st Page
Addr
(hex)
1400 122
1400 122
LTE Receive Channel 1 CV-S Performance
Monitoring (RO)
4
1410
CV_S_REG_1
Qty.
128
Local Orderwire (E1)
The local orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz channel for voice communications between regenerators, hubs, and remote terminals. The byte is extracted from each
frame, buffered, and then output serially, MSB first, on the RLCLOWn pin. During AIS insertion due to LOS, LOF,
or SEF (provisionable), 0x7F is constantly output. The data is clocked out on the positive edge of ROWCKn.
The ROWCKn clock is divided down from the section data communications channel clock, RSDCKn (192 kHz/3),
giving a frequency of 64 kHz and a duty cycle of 33%. In STS-48 mode, each of the four RLCLOW pins transmit
the E1 byte for a channel. In STS-192 mode, only the RLCLOW1 pin transmits the E1 byte, while the other pins
transmit a constant 0x7F serial stream.
Section User Channel (F1)
The section user channel byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz
channel for use by the network provider. The byte is extracted in each frame, buffered, and output serially, MSB
first, on the RSUSERn pin. During AIS insertion due to LOS, LOF, or SEF (provisionable), 0x7F is constantly output. The data is clocked out on the positive edge of ROWCKn.
In STS-48 mode, each of the four RSUSERn pins transmit the F1 byte for a channel. In STS-192 mode, only the
RSUSER1 pin transmits the F1 byte, while the other pins transmit a constant 0x7F serial stream.
Section Data Communications Channel (D1, D2, and D3)
The section data communications channel bytes are located in the first STS-1 of the STS-48 or STS-192 only and
are used as one 192 kHz message-based channel for operations, administration, and maintenance (OA&M) communication. The bytes are extracted from each frame, buffered, and output serially, MSB first, on the RSDCCn pin
in the order that they are received. During AIS insertion due to LOS, LOF, or SEF (provisionable), 0xFF is constantly output. The data is clocked out on the positive edge of RSDCKn.
The RSDCKn clock is divided down from the line data communications channel clock, RLDCKn (576 kHz/3), giving
a frequency of 192 kHz and a duty cycle of 33%. In STS-48 mode, each of the four RSDCC pins transmit the section data communication channel bytes for a channel. In STS-192 mode, only the RSDCC1 pin transmits these
bytes, while the other pins are set high.
Agere Systems Inc.
55
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Line BIP-8 (B2)
The line BIP-8 is located in each STS-1 of the STS-48 or STS-192 and carries the even parity for the line overhead
and SPE data within the previous STS-1 frame. The n line BIP-8 bytes in an STS-N are intended to provide a single
error monitoring facility for the entire STS-N signal. Thus, each TOH processor block is used to check the 48 line
BIP-8 codes, whether in STS-48 or STS-192 mode. Each BIP-8 bit found to be in error causes an internal 22-bit
counter to increment.
The value in the counter is transferred to the line coding violation (CV-L) registers on the positive edge of PM_CLK,
at which point the counter is cleared. The counter will stop at the maximum value and will not roll over. When in
STS-192 mode, a read of the STS-48 channel 1 CV-L register returns the 24-bit sum of the four constituent
STS-48 channel CV-L counts. However, reading channels 2—4 returns the CV-L count for the corresponding
STS-48.
In addition to the CV-L counter, line BIP-8 errors are also tracked in 16-bit signal fail (SF) and signal degrade (SD)
counters. These counters are used to detect SF and SD conditions for protection switching. The BER threshold for
each defect is separately provisionable for each channel over a range of 1 × 10–N values, where N = 3 to 5 for SF
and N = 5 to 9 for SD.
The detection times and error limits used to detect and clear both defects are dependent on the provisioned BER
threshold as shown in Table 24. The values shown in the table are the powerup defaults and are dependent on the
STS mode selected (48 or 192). These values can be changed through the corresponding registers and are common to all channels.
The clearing BER threshold for each defect is always 1/10th of the detection threshold. As can be seen in Table 24,
the range of possible detect thresholds is 1 x 10–3 to 1 x 10–9, which results in clear thresholds of 1 x 10–4 to
1 x 10–10. For example, to detect SD at 1 x 10–5 BER in an STS-192, the detection time is 4 ms and the detect
error limit is 358. The clearing would take place at 1 × 10–6 BER, with a clearing time of 6.5 ms and a clearing error
limit of 77. Figure 5 on page 57 illustrates SD detection and clearing using the default values specified in Table 24.
SD thresholds of 1 x 10–10 to 1 x 10–15 are supported through software.
Table 24. BER Threshold Time and Error Limits for Line SD and SF Detection
BER Threshold
Detect Error Limit
Clear Error Limit
STS-48
STS-192
STS-48
STS-192
STS-48
STS-192
1 × 10–3
4 ms
4 ms
4818
19453
—
—
–4
4 ms
4 ms
862
3543
957
3734
1 × 10–5
4 ms
4 ms
81
358
114
423
1 × 10
–6
31 ms
6.5 ms
62
51
91
77
1 × 10
–7
312.5 ms
65 ms
62
51
91
77
1 × 10
–8
1 × 10
56
Detection Time
2600 ms
650 ms
51
51
77
77
1 × 10–9
21 s
5250 ms
40
40
63
63
1 × 10–10
170 s
41 s
—
—
52
51
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
SD DETECTED
SD ACCUMULATED B2 ERRORS
358
77
SD
4
SD DETECTION WINDOW
6
8
SD CLEARING WINDOW
12.5
CLEARED
19
TIME (MS)
5-8406(F)r.1
Figure 5. Example of STS-192 SD Detection (10–5 BER) and Clearing (10–6 BER)
In STS-192 mode, the thresholds are compared against the sum of the four STS-48 channel SF and SD counts. A
detected SF or SD defect causes a corresponding maskable interrupt status bit to be set in the LTE receive
channel n service-affecting alarm register.
The SD/SF BER control bits in the LTE receive channel n maintenance register select the bit error rate for a particular channel. These control bits then select the detection time, the detect error limit, and the clear error limits for
each channel from the LTE receive common SD/SF registers. The detect error limit and the clear error limit registers contain 16-bit values, while the detection time registers use the lower 15 bits for a value and the upper bit for a
time unit specifier. For the detection time register, the value contained in the lower 15 bits is either specified in
0.5 ms units (upper bit = 0) or in seconds (upper bit = 1). Note that the PM_CLK input to the device is used as the
timing reference when the detection time is expressed in seconds.
A fixed windowing scheme is used for SD/SF detection. The window size is determined by the value in the detection time register for the specified bit error rate. An SD or SF alarm is declared immediately when the accumulated
error count exceeds the value specified in the detect error limit register.
If this error limit is not reached by the end of the window, then the accumulated error count is reset to zero. When
an SD or SF alarm is declared, the accumulated error count resets and clearing begins using the bit error rate
threshold that is 1/10th of the specified value along with the corresponding detection time registers. Clearing of the
SD or SF alarm only occurs at the end of the window when the accumulated error count is less than the value
specified in the clear error limit register.
During AIS insertion due to LOS, LOF, SEF, or line AIS, processing of the B2 byte is inhibited and the internal
SF/SD counters are reset back to zero. Because it takes five frames of line AIS before the actual line AIS alarm is
declared, it is likely that the signal degrade alarm will also be triggered. Once AIS insertion is removed, processing
of the B2 byte is delayed for two frames before it is enabled.
Agere Systems Inc.
57
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 25. B2 Register Summary
Function
Register Name
(First Occurrence)
Register Bits
Last Second Coding Violations
LTE Receive Channel 1 CV-L
CV_L_REG_1_L/
Count
Performance Monitoring (L) (RO)
CV_L_REG_1_U
SD/SF Detection Time
Line Signal Degrade/Signal Fail Bit SD_SF_DETECT_
Error Rate Detection Time
TIME_3
(1 x 10–3) (R/W)
SD_SF_ERR_
SD/SF Detect Error Limit
Line Signal Degrade/Signal Fail
LIMIT_3
Detect Error Limit (1 x 10–3) (R/W)
SD_SF_CLR_ERR_
SD/SF Clear Error Limit
Line Signal Degrade/Signal Fail
LIMIT_3
Clear Error Limit (1 x 10–4) (R/W)
SD/SF Threshold Selection
LTE Receive Channel 1
SD_BER_1/
Maintenance (R/W)
SF_BER_1
SD/SF Latched Alarms
LTE Receive Channel 1
SD_ALARM_1/
Service-Affecting Interrupt Alarm
SF_ALARM_1
(W1C)
Qty.
1st
Addr
(hex)
Page
4
127
8
140E/
140F
1300
7
1310
120
7
1320
121
4
1401
123
4
1405
124
119
Line BIP-8 (B2) Errors Serial Access
The errors detected in the line BIP-8 (B2) byte for each STS-1 can optionally be extracted serially on the local
orderwire (RLCLOWn), express orderwire (REXPOWn), and orderwire clock (OW_CLKn) pins of each STS-48.
This extraction is enabled on a global basis (i.e., all channels) by provisioning the LTE Transmit—B2 Corrupt
Frame Count (R/W) register (on page 128) with a value greater than 806310. The appropriate bit definitions are
shown in Table 130 on page 128, register 1B02. The TOH transparency feature is always supported on individual
STS-48 channels and will require all four channels to be provisioned in STS-192 mode. When enabled, the B2
errors detected in each STS-1 of an STS-48 are output serially on the REXPOWn pin as a byte containing a 1 in
each bit position found in error. These error masks are clocked out on the positive edge of a 78 MHz clock that is
provided on the OW_CLKn pin. Because this frequency is much higher than the bit rate of the B2 bytes, the 48
error masks on each REXPOWn pin are output in a burst fashion once per frame. The presence of this burst is indicated by a continuous logical high on the RLCLOWn pin. The data within the burst follows SONET STS-1 channel
ordering, but with the 48 channels serialized in 4-byte chunks with the LSB (newest data) sent first. In other words,
the STS-1 error masks for each STS-48 are sent LSB first in the following order: 10, 7, 4, 1; 22, 19, 16, 13; 34, 31,
28, 25; 46, 43, 40, 37; 11, 8, 5, 2; 23, 20, 17, 14; 35, 32, 29, 26; 47, 44, 41, 38; 12, 9, 6, 3; 24, 21, 18, 15; 36, 33,
30, 27; 48, 45, 42, 39.
APS Channel (K1 and K2)
The APS channels bytes are located in the first STS-1 of the STS-48 or STS-192 only and are used for automatic
protection switching (APS) signaling to coordinate line level protection switching. In addition, the K2 byte is also
used to carry line AIS (AIS-L) and line RDI (RDI-L) signals.
A new value in either byte is only validated after it has been received N times consecutively, where N is provisionable to 3 or 5 using the K1K2 validate select control bit. When a K1 or K2 byte is validated, the value is stored in
the K byte status register and the K1K2 new byte alarm bit is set. These two alarms are only generated when the
value of the new validated K1 or K2 byte is different from the value of the last validated byte. Validation of the K1
and K2 bytes, and the generation of the alarms, are not affected by the line AIS status.
58
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
The validated K1 and K2 bytes are further processed for the following defects:
■
■
Protection switching byte. This defect occurs when either an inconsistent APS byte or an invalid code is detected.
An inconsistent APS byte occurs when no N consecutive K1 bytes of the last 12 successive frames are identical,
starting with the last frame containing a previously consistent byte. An invalid code occurs when the incoming K1
byte contains an unused code or a code irrelevant for the specific switching operation in three consecutive
frames. An invalid code also occurs when the incoming K1 byte contains an invalid channel number in three
consecutive frames. As invalid code detection requires information not readily available to hardware; it must be
detected by software polling of the validated K1 byte value. An inconsistent APS byte defect is detected by
hardware and will cause a latched alarm status bit to be set in the corresponding LTE receive channel n
nonservice affecting interrupt alarm register. It is cleared when a K1 byte is received and validated. An
inconsistent APS byte defect is neither detected nor terminated during AIS-L defect. Processing of the
inconsistent APS byte defect is also inhibited when the validated K1 byte has a value of 0xFF and bits 6—8 of the
validated K2 byte have a value of 111. This additional feature prevents a change in the inconsistent APS defect
state just before line AIS is declared.
Channel mismatch. This defect occurs when the channel numbers in the transmitted K1 byte (bits 5—8) and the
validated received K2 byte (bits 1—4) are not identical. Detection of a channel mismatch defect causes a latched
alarm status bit to be set in the corresponding LTE receive channel n nonservice-affecting interrupt alarm register.
A channel mismatch defect is neither detected nor terminated during an AIS-L defect. Processing of the channel
mismatch defect is also inhibited when the validated K2 byte has a value of 1111x111 binary. This additional
feature prevents a change in the channel mismatch defect state just before line AIS is declared.
In addition, the currently received K2 byte is processed for the following defects:
■
■
Line AIS (AIS-L). Declared when bits 6—8 of K2 contain 111 for five consecutive frames. Cleared when any other
pattern is received for five consecutive frames. Detection of a line AIS defect is indicated by a latched alarm
status bit, persistency bit, and one second PM bit being set in the registers for the affected channel.
Line RDI (RDI-L). Declared when bits 6—8 of K2 contain 110 (binary) for five consecutive frames. Cleared when
any other pattern is received for five consecutive frames. Detection of a line RDI defect is indicated by a latched
alarm status bit, persistency bit, and one second PM bit being set in the registers for the affected channel.
Table 26. APS Channel (K1 and K2) Register Summary
Function
K1K2 Validation
Length (3 or 5)
Validated K1K2
Storage
New Validated
K1K2 Alarm
Inconsistent APS
Alarm
Channel Mismatch Alarm
AIS-L Latched
Alarm
AIS-L Persistency
Agere Systems Inc.
Register Name
(First Occurrence)
Register Bits
Qty.
Page
4
1st
Addr
(hex)
1400
LTE Receive Channel 1
Provisioning (R/W)
LTE Receive Channel 1 K Byte
Status (RO)
LTE Receive Channel 1
Nonservice-Affecting Interrupt
Alarm (W1C)
LTE Receive Channel 1
Nonservice-Affecting Interrupt
Alarm (W1C)
LTE Receive Channel 1
Nonservice-Affecting Interrupt
Alarm (W1C)
LTE Receive Channel 1
Service-Affecting Interrupt
Alarm (W1C)
LTE Receive Channel 1
Service-Affecting Persistency
Alarm (RO)
K_VALIDATE_LIMIT_SEL_1
RX_K1_VALIDATED_BYTE_1
RX_K2_VALIDATED_BYTE_1
RX_K1_NEW_BYTE_RAW_INT_1
RX_K2_NEW_BYTE_RAW_INT_1
4
1403
123
4
1408
125
INCONSISTENT_APS_ALARM_1
4
1408
125
CHANNEL_MISMATCH_ALARM_1
4
1408
125
RX_LINE_AIS_ALARM_1
4
1405
124
AISL_PER
4
1407
124
122
59
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 26. APS Channel (K1 and K2) Register Summary (continued)
Function
Register Name
(First Occurrence)
Register Bits
Qty.
Last Second AIS-L
PM
RDI-L Latched
Alarm
LTE Receive Channel 1
Performance Monitoring (RO)
LTE Receive Channel 1
Nonservice-Affecting Interrupt
Alarm (W1C)
LTE Receive Channel 1
Nonservice-Affecting
Persistency Alarm (RO)
LTE Receive Channel 1
Performance Monitoring (RO)
RX_LINE_AIS_PM_1
RDI-L Persistency
Last Second
RDI-L PM
Page
4
1st
Addr
(hex)
140B
RX_LINE_RDI_ALARM_1
4
1408
125
RX_LINE_RDI_PER_1
4
140A
127
RX_LINE_RDI_PM_1
4
140B
127
127
Line Data Communication Channel (D4—D12)
The line data communication channel bytes are located in the first STS-1 of the STS-48 or STS-192 only, and are
used as one 576 kHz message-based channel for operations, administration, and maintenance communication
(OA&M). The bytes are extracted from each frame, buffered, and are output serially, MSB first, on the RLDCC_n
pin. During AIS insertion due to LOS, LOF, or SEF (provisionable), 0xFF is constantly output. The data is clocked
out on the positive edge of RLD_CLK_n. The RLD_CLK_n clock is divided down from the internal data clock
(622.08 MHz/1080), giving a frequency of 576 kHz and a duty cycle of roughly 50%.
In STS-48 mode, each of the four RLDCC pins transmit the line data communication channel bytes for that channel. In STS-192 mode, only the RLDCC_1 pin transmits these bytes, while the other pins are set high.
Synchronization Status (S1)
The synchronization status byte is located in the first STS-1 of the STS-48 or STS-192 only, and is used to convey
the synchronization status of a network element. The byte is extracted from each frame. A new value is only validated and stored in the S1 byte after it has been received eight consecutive times. Detection of a new validated
byte is indicated by the latched S1 new byte alarm bit. The alarm is only generated when the value of the new validated byte is different from the value of the last validated byte.
The validated synchronization status byte is also transmitted on the RFRMn pin for each channel when the RFRM
output enable control bit is set high. The byte is serialized MSB first as a repeating 77.76 MHz Manchester
encoded* 16-bit code that is interrupted once per frame by the frame sync pattern 00001111. While the data rate of
the signal is 77.76 MHz, the output pin is driven with 622 MHz low-voltage differential drivers, synchronous to the
corresponding R_CLKO_n clock. When the RFRM output enable control bit is set low (the default value), an 8 kHz
clock is transmitted on the RFRMn pin.
CLK
RFRM
0
1
1
0
0
FRAMING PATTERN
5-8402(F)
Figure 6. Timing Diagram for RFRM
* A logic 0 is encoded as an upward transition at the bit center; a logic 1 is encoded as a downward transition at the bit center. Each Manchester encoded bit requires two clock cycles. The frame sync pattern is not Manchester encoded, and therefore each bit only requires one clock
cycle.
60
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
During AIS insertion due to LOS, LOF, SEF, or line AIS, a constant high signal is transmitted on the RFRMn pin,
regardless of the RFRM output enable control bit.
In STS-48 mode, each of the four RFRMn pins operates according to the functionality specified above. In STS-192
mode, only the RFRM1 pin transmits the validated synchronization status byte or the 8 kHz clock.
Table 27. Synchronization Status (S1) Register Summary
Function
Register Name
(First Occurrence)
Register Bits
Qty.
New Validated S1 Latched
Alarm
LTE Receive Channel 1
Nonservice-Affecting Interrupt
Alarm (W1C)
LTE Receive Channel 1
Provisioning (R/W)
RX_S1_NEW_BYTE_
RAW_INT_1
RX_FRM_EN_1
RFRM Output Enable
Control Bit
Page
4
1st
Addr
(hex)
1408
4
1400
122
125
STS-192 Line Remote Error Indication (M1)
The line remote error indication (REI-L) byte is located in the third STS-1 of the STS-48 or STS-192 only (in order
of appearance in the STS-192 signal), and is used to convey to the far end the number of errors detected using the
line BIP-8 bytes (truncated at 255). The byte is extracted from each frame and the value added to an internal 21-bit
counter. The value in the counter is transferred to the REI-L registers on the positive edge of the PM_CLK input, at
which point the counter is cleared. The counter will stop at the maximum value and will not roll over.
Table 28. Line REI (M1) Register Summary
Function
Last Second REI-L Count
Register Name
(First Occurrence)
Register Bits
Qty.
LTE Receive Channel 1 REI-L
Performance Monitoring (U) (RO)
REI_L_REG_1_U/
REI_L_REG_1_L
4/
4
1st
Addr
(hex)
140D,
140C
Page
127/
127
Express Orderwire (E2)
The express orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz
channel for voice communications between line entities. The byte is extracted from each frame, buffered, and then
output serially, MSB first, on the REXPOW_n pin. During AIS insertion due to LOS, LOF, SEF (provisionable), or
line AIS, 0x7F is constantly output. The data is clocked out on the positive edge of ROW_CLK_n.
In STS-48 mode, each of the four REXPOW pins transmit the E2 byte for a channel. In STS-192 mode, only the
REXPOW_1 pin transmits the E2 byte while the other pins transmit a constant 0x7F serial stream.
Receive STS Path Processor
This block is replicated four times. Each block accepts the data for one STS-48 channel and terminates the
SONET/SDH path layer overhead, without terminating the full path layer (i.e., demapping the payload). It provides
pointer interpretation, path overhead processing, and drop interface alignment (pointer generation) for any mix of
valid STS payloads from 48 channels of STS-1 to one channel of STS-48c, or part of an STS-192c channel. The
exact mix of payloads is determined automatically by hardware by examining the pointer bytes. The received payloads can be optionally compared to a software provisioned map using the software concatenation map registers in
the microprocessor interface. Concatenated payloads must follow the basic position requirement specified in
GR-256-CORE that concatenated payloads start on an STS-3 boundary (STS-1 payloads may start anywhere).
Note that the terminology used is from SONET, although SDH is also supported.
Agere Systems Inc.
61
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
The pointer interpretation, path overhead processing, and drop interface alignment functions are actually grouped
on an STS-12 level. Thus, each path processor block contains four instances of each of these functions along with
a TSI module to convert the input data into four STS-12 channels. Of the path overhead processing functions, however, path trace monitoring is supported on any single STS-1 in each STS-48.
1:4 Demultiplex TSI
In order to demultiplex the STS-48 data stream into four valid STS-12 data streams, the bytes in the STS-48 data
must be reordered. Table 20 on page 51 shows the STS-1 ordering at the input to the four demultiplexers. Table 29
shows the STS-1 ordering after the demultiplexers.
Table 29. STS-12 Byte Ordering
Time (Left to Right for Each STS-12 Channel) ⇒
1
13
25
37
49
61
73
85
97
109
121
133
145
157
169
181
4
16
28
40
52
64
76
88
100
112
124
136
148
160
172
184
7
19
31
43
55
67
79
91
103
115
127
139
151
163
175
187
10
22
34
46
58
70
82
94
106
118
130
142
154
166
178
190
2
14
26
38
50
62
74
86
98
110
122
134
146
158
170
182
5
17
29
41
53
65
77
89
101
113
125
137
149
161
173
185
8
20
32
44
56
68
80
92
104
116
128
140
152
164
176
188
11
23
35
47
59
71
83
95
107
119
131
143
155
167
179
191
3
15
27
39
51
63
75
87
99
111
123
135
147
159
171
183
STS-12
Number
6
18
30
42
54
66
78
90
102
114
126
138
150
162
174
186
9
21
33
45
57
69
81
93
105
117
129
141
153
165
177
189
12
24
36
48
60
72
84
96
108
120
132
144
156
168
180
192
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Receive Pointer Processor
The STS pointer processor is used for phase absorption and frequency synchronization of SONET payload from
one clock domain (the receive or line timing) to another (the drop interface timing). This is accomplished by three
basic functions: pointer interpreter, elastic store, and pointer generator. The pointer interpreter extracts the SONET
synchronous payload envelope (SPE) from the incoming data by interpreting the H1 and H2 pointer bytes of the
line overhead. The SPE is then written to the elastic store. The pointer generator reads the SPE from the elastic
store and regenerates the H1 and H2 pointer bytes. Since the pointer processor does not terminate the path, intermediate performance monitoring is performed (i.e., the path overhead is not modified).
Pointer Interpreter Functions. The STS pointer interpreter interprets the H1 and H2 bytes for each incoming
STS-1. The interpreter has four states: loss of pointer (LOP), alarm indication signal (AIS), normal (NORM), and
concatenation indication (CONC). The state diagram is shown in Figure 7 on page 63.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
3XAIS
CONC
AIS
3XCONC
AI
3X
S
RM
O F
N
D
3X XN
1
8x
IN
VA
LI
D
8xINVALID
NC
3XAIS
3XNORM
3XCONC
3X
CO
8xINVALID
8XNDF
NORM
LOP
3XNORM
5-8400(F)r.1
Figure 7. Pointer Interpreter State Machine
Incoming pointers are categorized into one or more of the following categories:
1. Normal pointer.
2. New data flag (NDF) pointer.
3. Concatenation indicator.
4. AIS pointer.
5. Invalid pointer.
Consecutive (and identical, in the case of normal) pointers in each category are counted and used to determine
state transitions, as shown in Figure 7. When changing states, NORM, CONC, and AIS always take precedence
over LOP (NORM, CONC, and AIS being mutually exclusive) if conditions indicate that two different transitions are
possible.
In NORM state, increments and decrements can be evaluated in either SONET or SDH modes on a per-STS-12
basis. The provisioning is done with the INT_SONET_SDH bit in the STS-12 pointer processor provisioning register, using the following rules:
■
■
In SONET mode, the 8 of 10 rule is used, where eight of the ten I and D bits must be correct for the pointer to be
considered an increment or decrement. Register 0x3000 bit 4 should be set to 1 for this mode.
In SDH mode, the 3 of 5 rule is used, where three of the five I bits and three of the five D bits must be correct for
the pointer to be considered an increment or decrement. Register 0x3000 bit 4 should be set to 0 for this mode.
Also in NORM state, three identical normal pointers with an offset different from the currently validated offset, or a
single NDF pointer with a valid offset will cause the new offset to become the validated offset. The SPE will then be
extracted at the new offset.
Agere Systems Inc.
63
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Classification of invalid pointers depends on the state. In NORM state, any pointer that is not one of the following is
considered invalid:
■
Normal NDF with the offset equal to the currently validated offset.
■
NDF set with a valid offset.
■
AIS pointer (all ones).
■
An increment or decrement where all ten I and D bits are correct.
In AIS state, any pointer that is not an AIS pointer is considered invalid. In CONC state, any pointer that is not a
concatenation indicator or an AIS pointer is considered invalid.
The pointer interpreter provides the following information:
■
■
AIS-P and LOP-P defect indications on a per-STS-1 basis: these are used to create the LOP-P and AIS-P alarms
in the STS-1 channel path alarms register, whose persistency is shown in the AIS_P_PERS and LOP_P_PERS
bits of the STS-1 path alarm persistency register, and the AIS_P_PM and LOP_P_PM alarms in the path
overhead last second bin register.
A per-STS-1 indication of CONC state (RECD_CONC_MAP).
Table 30. Pointer Interpreter Register Summary
Function
SONET/SDH Increment/
Decrement Evaluation Rules
Received Concatenation Map
AIS-P Latched Alarm
AIS-P Persistency
Last Second AIS-P PM
LOP-P Latched Alarm
LOP-P Persistency
Last Second LOP-P PM
Register Name
(First Occurrence)
Register Bits
STS-12 Pointer Processor
INT_SONET_SDH
Provisioning, STS-1 #1 to STS-1
#12 (R/W)
Received Concatenation Map
RECD_CONC_MAP
STS-1 #1 to STS-1 #12 (RO)
STS-1 #1 Alarm Interrupt Status
AIS_P
(W1C)
STS-1 #1 Alarm Persistency (RO)
AIS_P_PERS
STS-1 #1 PM Last Second
AIS
Indicators (RO)
STS-1 #1 Alarm Interrupt Status
LOP_P
(W1C)
STS-1 #1 Alarm Persistency (RO)
LOP_P_PERS
STS-1 #1 PM Last Second
LOP
Indicators (RO)
Qty.
1st
Addr
(hex)
Page
16
3000
145
16
440F
163
192
3013
147
192
192
3015
3016
148
148
192
3013
147
192
192
3015
3016
148
148
Elastic Store Functions. The elastic store provides a 20-byte deep buffer for each STS-1 channel. The receive
SPE bytes for each STS-1 are written into the store along with an indication of SPE phase. The bytes are then read
out of the store using drop interface timing, under control of the pointer generator. If the receive and drop timing is
synchronous, the elastic store will remain half filled with the write and read pointers 180 degrees (10 bytes) apart.
Any difference in the rates, or pointer adjustments on the receive side, will cause the store to fill or empty. A phase
comparator in the elastic store monitors the fill level of the store and generates a pointer adjustment in the pointer
generator whenever the level crosses a minimum or maximum threshold. These thresholds are symmetrical
around the half-fill point in the store and are selected to provide 5 bytes of uncertainty for the transport overhead, a
3-byte window for pointer adjustments, and 2 bytes of dead band. Thus, the elastic store will cause a pointer
adjustment in the pointer generator when the path timing of the incoming STS-1 has drifted more than an average
of ±2 bytes from start-up conditions.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
The integrity of the elastic store is constantly monitored for overflow/underflow conditions. If either of these conditions is detected, the read and write pointers are reset and the ES_OVRUN bit in the corresponding STS-1 channel
path alarms register is set.
Table 31. Elastic Store Register Summary
Function
Elastic Store Overrun Alarm
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
STS-1 #1 Alarm Interrupt Status
(W1C)
ES_OVRUN
192
3013
147
Pointer Generator Functions. The pointer generator monitors the elastic store and produces a new pointer to
align the read data to the frame phase of the drop interface. The base value of the pointer is determined by the offset between the phase of the SPE in the read data and the drop frame indication (DFRM). This value is then modified by the following conditions:
■
■
■
■
■
■
An increment or decrement operation is performed whenever the elastic store indicates the phase difference
between the read and write pointers exceeds a minimum or maximum threshold. No increment or decrement
operation will be performed for three frames following any pointer change operation.
A new pointer value is sent along with an NDF for one frame whenever the SPE phase suddenly changes
position.
A new pointer value is sent along with an NDF for one frame whenever an elastic store overflow or underflow
occurs, causing the read and write pointers to be reset.
An all ones pointer value is sent whenever the pointer interpreter indicates the channel is in LOP or AIS state, or
when AIS insertion is enabled for the channel through the microprocessor interface. If the channel is the head of
a concatenated payload, all STS-1 channels associated with the payload will also have AIS inserted. A new
pointer value is sent along with an NDF for one frame following the termination of the all ones.
An all ones pointer value is sent within 125 µs of the interpreter receiving an all ones pointer (as per SONET
objective O3-99).
Bits 5 and 6 of H1 (the SS-bits in SDH) pass through from the pointer interpreter, except during AIS-P, when they
are set to 11.
The output of the pointer generator is the SPE data and the H1, H2, and H3 bytes for each STS-1 processed. All
other bytes in the SONET frames are defined by the receive payload drop interface.
Pointer Generator Bypass Function. The pointer processor has the ability to bypass the pointer generator for
use in applications where the line timing is passed on (i.e., through timing, in an OC-192 to OC-12 deMUX). This is
achieved by pulling up the DRPBYP pin to VDD. When the pointer generator is bypassed, the output data is taken
from the pointer interpreter instead of from the output of the pointer generator. In this case, receive timing will be
used by the payload drop interface.
Table 32. Pointer Generator Bypass Register Summary
Function
DRPBYP Pin Readback Bit
Agere Systems Inc.
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
Chip Status (RO)
DRPBYP
1
0006
112
65
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Receive TOH Transparency. A passthrough capability using software provisioning for the TOH on the line interface to/from the TOH on the equipment interface is provisioned for the receive direction when the device setup
STS-192 mode. In this case, receive timing will be used by the payload drop interface. The receive direction has
the option for full TOH transparency of just line overhead transparency with section overhead used for the normal
proprietary drop I/F OH. This feature is enabled in software by setting the appropriate bits in the LTE transmit channel 1—4 provisioning (R/W) registers (0x1C00, 0x1D00, 0x1E00, and 0x1F00, respectively). TOH transparency
feature is always supported on individual STS-48 channels and will require all four channels to be provisioned in
STS-192 mode. When this feature is enabled, both the transmit and receive sections will be provisioned to the
same mode (i.e., the function cannot be set up differently in transmit and receive directions). A full description is
found in the TOH Transparency section on page 85.
This feature is available on a per STS-48 level. When TOH transparency is enabled, the PP will be bypassed on a
per STS-48 level. See the Receive Pointer Processor section on page 62 for more information on how this mode
affects the device.
AIS Insertion Functions. The pointer interpreter decides when to insert AIS-P on output data. The conditions
under which AIS-P is inserted are summarized in Table 33. The conditions are provisioned on a per-STS-12 basis
in the STS-N pointer processor control (provisioning) register with the AUTO_AIS_DIS bit.
Table 33. AIS-P Insertion Conditions
Condition
AUTO_AIS_DIS
Bit Value
Output Data
Interpreter AIS-P
0
AIS-P1
1
Flow-Through
Interpreter LOP-P
0
AIS-P1
1
Flow-Through
Software AIS Insert Register
NA
AIS-P1
Receive (line) Clock Lost
NA
AIS-P1
First STS-1 in STS-48/STS-192 Stream
Receives a Valid Concatenation Indicator
NA
AIS-P1
1. AIS-P affects H1, H2, H3, and all SPE bytes.
The flow-through data, as indicated in the table, will be different based on whether the pointer generator is being
bypassed—specifically, the H1, H2, and H3 bytes will be different. If the pointer generator is not bypassed, the H1,
H2, and H3 bytes will be generated by the pointer generator and will be normal pointers with the last known offset.
In pointer generator bypass mode, the H1, H2, and H3 bytes will be the same as those received by the pointer
interpreter, and any downstream equipment will see the same defects as the pointer interpreter.
Note: It is not recommended to set the AUTO_AIS_DIS bit unless in pointer generator bypass mode. This feature
is intended to be used only in the pointer generator bypass mode.
Concatenated STS-1s will follow the AIS insertion of the STS-1 at the head of the concatenation. Changes to concatenated STS-1s will take effect during the pointer bytes (H1, H2, and H3). Thus, when using software AIS insert
on the first STS-1 in the concatenation, it will immediately begin sending AIS-P data and the rest of the concatenation will begin sending AIS-P data after the next pointer (as seen in the pointer interpreter). In addition, AIS-P can
be inserted on any STS-1 within a concatenation individually by writing the appropriate bit in the software AIS insert
register.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 34. Path AIS Insertion Register Summary
Function
Disabling of AIS-P Insertion
on AIS-P and LOP-P
Defects
Software AIS-P Insertion
Control
Register Name
(First Occurrence)
Register Bits
STS-12 Pointer Processor
AUTO_AIS_DIS
Provisioning, STS-1 #1 to STS-1
#12 (R/W)
STS-12 Pointer Processor
PP_CH_SW_AIS_INS_n
Maintenance, STS-1 #1 to STS-1
#12 (R/W)
Qty.
1st
Addr
(hex)
Page
16
3000
145
16
3001
145
Concatenation. Each STS-1 position has its own state machine. When an STS-1 enters the CONC state, indicating receipt of validated concatenation indicators, it begins following all pointer operations indicated by the first
STS-1 in the concatenation. Information is passed between STS-12 pointer processing blocks to facilitate concatenations up to STS-192c. This allows the TSOT0410G4 to automatically adjust to incoming concatenated payloads.
An unsupported concatenation alarm and a concatenation mismatch alarm are created to indicate status of the
received concatenated payloads. The unsupported concatenation alarm is asserted when the received concatenation map from the pointer interpreter contains concatenations that cross an STS-3 boundary, but do not start at an
STS-3 boundary, because the pointer interpreter and pointer generator cannot process such concatenations correctly.
The concatenation mismatch alarm is generated if an STS-1’s concatenation state does not match the provisioned
expect state for that STS-1 and the comparison is enabled. The expect values are provisioned in the software concatenation map registers and the comparisons are enabled (on an STS-1 basis) in the software concatenation
mask registers.
The unsupported concatenation alarms and concatenation mismatch alarms are both reported on an STS-12
basis. In order to find the offending STS-1(s), the corresponding received concatenation map register(s) must be
read and examined. The unsupported concatenation map alarm will be reported in the STS-12 that contains the
first STS-1 of the unsupported concatenation.
In the received concatenation map and the software concatenation map, the first STS-1 in a concatenation is
flagged with 0 and all other STS-1s in the concatenation are flagged with 1s. In the registers, the first STS-1 of the
STS-12 is in the LSB and the STS-1s are in SONET order. Since only 12 STS-1s are reported in each register, the
four most significant bits are ignored. For example, if a read of a received concatenation map register returns
0x0FB6 (binary xxxx 1111 1011 0110), this means that there is an STS-3c starting at the first STS-1 of that particular STS-12, and an STS-3c starting at position 4, and an STS-6c (or larger) starting at position 7. To determine if
the last concatenation is larger than STS-6c, the concatenation map for the next STS-12 must be read.
In order to check the software concatenation map against the received concatenation map, every STS-1 in the
concatenation (including the first) should have the compare enabled with the appropriate compare enable bit.
Agere Systems Inc.
67
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 35. Concatenation Register Summary
Function
Register Name
(First Occurrence)
Register Bits
Concatenation Mismatch
STS-48 Channel Path Alarms 1
CONC_MAP_MMCH_1
Alarm
(W1C)
Unsupported
STS-48 Channel Path Alarms 1 UNSUPP_CONC_MAP_1
Concatenation Alarm
(W1C)
Received Concatenation
Received Concatenation Map
RECD_CONC_MAP
Map
STS-1 #1 to STS-1 #12 (RO)
Software Provisioned
S/W Concatenation Map STS-1
SW_CONC_MAP
Expected Concatenation
#1 to STS-1 #12 (R/W)
Map
Provisioned Concatenation S/W Concatenation Mask STS-1
SW_CONC_MASK
Map Compare Enable
#1 to STS-1 #12 (R/W)
Qty.
1st
Addr
(hex)
Page
4
4413
164
4
4413
164
16
440F
163
16
4406
161
16
440B
162
Pointer Justification (Increment and Decrement) Binning. For performance monitoring purposes, there is a
provision to accumulate last second pointer justifications for one STS-1 in each STS-12 pointer processor. On each
positive edge of the PM_CLK input, the last second counts of received and generated increments and decrements
are transferred to the appropriate registers.
The STS-1 within the STS-12 that will be monitored is provisioned by setting the INT_INC_BIN bits to the SONET
STS-1 number desired in the STS-12 pointer processor control (provisioning) register. Programming this register to
an invalid value will stop accumulation of justification information, but will not clear any justifications already
counted.
All of the justification counters will saturate at a value of 2000 (decimal). This is the maximum number of justifications that can be performed in one second.
Table 36. Pointer Justification Binning Register Summary
Function
Selection of STS-1 within
STS-12 to Monitor
Last Second Increments
Received
Last Second Decrements
Received
Last Second Increments
Generated
Last Second Decrements
Generated
68
Register Name
(First Occurrence)
Register Bits
STS-12 Pointer Processor ProviINT_INC_BIN
sioning, STS-1 #1 to STS-1 #12
(R/W)
STS-12 Pointer Interpreter PM,
PP_CH_INT_INC_PM
Last Second Increments, STS-1
#1 to STS-1 #12 (RO)
STS-12 Pointer Interpreter PM,
PP_CH_INT_DEC_PM
Last Second Decrements, STS-1
#1 to STS-1 #12 (RO)
STS-12 Pointer Generator PM,
PP_CH_GEN_INC_PM
Last Second Increments, STS-1
#1 to STS-1 #12 (RO)
STS-12 Pointer Generator PM, PP_CH_GEN_DEC_PM
Last Second Decrements, STS-1
#1 to STS-1 #12 (RO)
Qty.
1st
Addr
(hex)
Page
16
3000
145
16
3002
145
16
3003
146
16
3004
146
16
3005
146
Agere Systems Inc.
Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Functional Description (continued)
Receive Path Overhead (POH) Processor
This block accepts the payload mapping information, status, and timing from the receive pointer interpreter, and
extracts the path overhead from up to 12 STS channels. The extracted overhead is then stored internally and may
be further processed for alarm or performance monitoring purposes. While an STS channel is in AIS or LOP status, all path overhead processing for the channel is inhibited. The definition and associated storage or processing
of each byte is detailed as follows.
Path Trace (J1). The path trace (J1) byte is the first POH byte of each unconcatenated STS-1 and carries a
repeating message. Path trace messages are 64-bytes long (ASCII, <CR><LF> terminated) in SONET and
16 bytes long (E.164) in SDH systems. The POH processor supports extraction of one path trace message per
STS-48. There are four path trace extraction message buffers. In STS-192 mode, there are four path trace extraction message buffers—one for each of the STS-48 streams contained within the STS-192.
The content of the message is either monitored for a mismatch from a provisioned expected message or monitored
for a sustained change (validation) in the received message. If the message mode control bit is set to the provisioned mode, then the incoming message is compared against the software programmed expected message. The
expected message is stored in internal memory for each STS-48 channel. A mismatch is declared if the received
message differs from this expected message for ten consecutive messages. The mismatch clears when four out of
five received messages match the expected message (fixed windowing is used for clearing). If the message mode
control bit is set to the validated mode, the incoming message is monitored for a sustained change. A sustained
change is detected when the received message differs from the last stable message for ten consecutive messages. The new message then becomes the stable message, is stored in internal memory, and the processor
starts checking for a sustained change from this new stable message (i.e., there is no clearing criteria for a sustained change). The message mismatch state or the new (sustained) message state are reflected by maskable
latched alarm bits in the STS-48 channel path alarms register.
For path trace processing, provisioning of the selected STS-1 within the STS-48, SDH, or SONET message type,
and validated or provisioned message mode is done using the STS-48 channel path trace control register.
The expected messages for the four STS-48 channels are provisioned through the microprocessor interface using
the path trace access control and 64-byte message buffer registers. This message buffer is also used to read the
contents of the expected/stable or received messages from the internal message memories for all channels. The
STS-48 channel and message type (expected/stable or received), and the access type (read/write) are specified
using the path trace access control register. Once this register is configured, the actual access is triggered by writing a 0x0001 value to the path trace access start register. The transfer from internal memory to the message buffer
is performed on the next message boundary. Completion of the access is indicated by the path trace access complete status register.
Internally, for each STS-48 channel, a memory is used to store the currently received path trace message as well
as the stable or provisioned message. The operation of the memory is monitored using parity, and any errors are
reported using the J1 parity error alarm bit.
Agere Systems Inc.
69
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 37. J1 Register Summary
Function
Message Type Select
Message Mode (Provisioned or
Validated)
Message mismatch Latched
Alarm
New Message Latched Alarm
J1 Access Message Buffer
Message Buffer Access
Control
Message Buffer Access Start
Message Buffer Access
Complete Flag
Buffer Parity Error Latched
Alarm
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
STS-48 Channel Path Trace
Control (R/W)
STS-48 Channel Path Trace
Control (R/W)
STS-48 Channel Path Alarms 1
(W1C)
STS-48 Channel Path Alarms 1
(W1C)
Path Trace Buffer Word #1—Word
#32
Path Trace Access Control (R/W)
TYPE_SEL
4
4406
161
MODE_SEL
4
4406
161
J1_MSG_MMCH
4
4413
164
J1_NEW_MSG
4
4413
164
J1_UP_BUFFER
32
4110
154
All Bits
1
4100
154
J1_AXS_START
J1_AXS_DONE
1
1
4102
4101
154
154
J1_BUF_PAR_ERR
4
4413
164
Path Trace Access Start
Path Trace Access Complete
Status (W1C)
STS-48 Channel Path Alarms 1
(W1C)
Path BIP-8 (B3). The path BIP-8 byte carries the even parity of the data in the previous STS SPE frame (783 bytes
for STS-1, M × 783 for STS-Mc). During every frame, the received B3 value is extracted and compared to the calculated BIP-8 for the previous frame. Detected errors are accumulated in an internal 16-bit counter based on either
bit or block errors, as provisioned, per-channel. If bit error mode is enabled for the channel, each BIP-8 bit found to
be in error causes the counter to increment. If block error mode is enabled for the channel, the counter only increments by one, regardless of the number of BIP-8 bits in error, provided that there are one or more bits in error. The
control bit for counting bit or block errors is in the per STS-1 path overhead provisioning register. The value of the
internal counter is transferred to the per STS-1 last second CV-P (path coding violation) count register on the positive edge of the PM clock input, at which point the counter is cleared. The counter will stop at the maximum value
and will not roll over.
In addition to the CV-P counter, path BIP-8 errors are also tracked in a signal fail (SF) counter. Individual STS-1s
have a 9-bit counter. Concatenated payloads have a 14-bit counter. This counter is used to detect SF defects for
protection switching. An SF defect is detected when the error count reaches a selected threshold within a fixed window of time (typically representing a BER of 10–N, where N = 3 to 5), where the error count is cleared at the end of
the time window. The defect is then cleared when the error count within a full time window is less than a threshold,
where both the window and threshold represent a BER that is 1/10th the detection BER.
The time windows and thresholds used are provisionable on a per-channel basis from eight pairs of common registers. Each pair of common registers represents the detection and clearing values for a particular payload type (i.e.,
STS-1, STS-3c, etc.) and BER threshold. Each register includes 2 bits to select one of four common-time windows
and either 9 or 14 bits to select an error threshold. Two of the pairs of registers are reserved for STS-1 payloads
and only support 9-bit thresholds, while the remaining six pairs support STS-Nc payloads. While a channel does
not have an SF defect, the detection register of the pair defines the error threshold and time window.
When a channel detects an SF defect, it switches to the clearing register to define the error threshold and time window. The four common-time windows each support a 16-bit value that represents the time window in 0.5 ms units.
70
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Note that the time windows are continually cycling. Thus, the clearing time window for an STS-1 that has declared
SF does not necessarily start at the exact time that SF is declared. The same can be said for the detect time windows. Also, when a new value is programmed into a time window register, it does not take effect until the end of the
current window.
Essentially, the eight pairs of threshold registers are intended to be used in groups of two, with each group representing two BER thresholds for a particular payload size. Thus, this facility supports separate working and protection channel SF defect BER thresholds for four payload sizes. This concept is demonstrated in Table 38, which
shows the default powerup detection and clearing time windows and error limits for the common threshold registers, along with the payload sizes and BER thresholds they correspond to. Table 39 shows the default powerup
values for the four common-time windows.
Detection of an SF defect for a channel is indicated by the SIG_FAIL bit in the appropriate STS-1 channel path
alarms register and causes a code to be sent in the E1 and F1 overhead bytes for that channel on the drop interface. SD defect detection is not supported in hardware; however, a control bit is provided (SD_INSERT in the path
overhead maintenance STS-1 register) for each channel to force an SD defect code to be sent in the E1 and F1
overhead bytes for that channel on the drop interface.
Table 38. BER Threshold Time Window and Error Limits for Path SF Detection
Payload
Size1
Register
Set
BER
Threshold
Detection
Window
Detection Error
Limit
Clearing
Window
Clearing Error
Limit
STS-1
0
1 × 10–4
1
207
2
275
1
1×
10–5
2
222
3
277
1×
10–4
1
563
2
779
3
1×
10–5
2
690
3
795
4
1 × 10–4
1
931
2
1496
5
1 × 10–5
2
1374
3
1560
6
1×
10–4
1
1309
2
2824
1×
10–5
2
2658
3
3068
STS-3c
STS-6c
STS-12c
2
7
1. Measurements for STS-48c and STS-192c are not realistic. Refer to SONET/SDH specifications for details.
Table 39. Time Window Sizes for Path SF Detection
Time Window
Length (in ms)
Register Value
0
1
2
3
5
50
500
5000
10
100
1000
10000
To set up an SF threshold, select one of the signal fail window size registers for the detect window and write the
appropriate value to it. Select another signal fail window size register for the clear window (if different from the
detect window) and write the appropriate value to it. Next, select a threshold register set (0—7) and write the
detect threshold into the corresponding signal fail detect threshold register, using the two most significant bits of
the register to choose the detect time window as chosen earlier. Then, write the clear threshold into the corresponding signal fail clear threshold register, using the two most significant bits to indicate the clear window as chosen earlier. Finally, for each STS-1 that is to use the new threshold, set the SF_THRESH_SEL bits in the path
overhead maintenance STS-1 register to the number of the register set that has just been set up.
Agere Systems Inc.
71
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
As soon as SF is declared, the counters immediately switch to the clearing window, so it is only at the end of the
current running clear time window that path BIP-8 errors begin to be considered for the clearing of SF. This ensures
that an entire clearing window is used for clearing SF.
Any STS-1 that does not belong to a concatenation has only a 9-bit counter. Thus, if a 14-bit clear threshold that is
greater than 511 is used for such an STS-1, any SF defect is cleared at the end of the current clear time window,
since the clear threshold can never be reached.
To disable SF detection, a window of the smallest possible size (0.5 ms) can be set up and used with a detect
threshold of more than 32, since a maximum of 32 B3 errors can be detected in 0.5 ms.
Table 40. B3 Register Summary
Function
Bit or Block Error Counting
Control
Last Second CV-P
Signal Degrade E1/F1 Code
Insertion Control
Signal Fail Register Set
Selection Control
Signal Fail Detection
Threshold and Window
Select
Signal Fail Clear Threshold
and Window Select
Signal Fail Window Size
Control
Signal Fail Latched Alarm
72
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
STS-1 #1 Path Overhead
CNT_BLK_ERRS
192
Provisioning (R/W)
STS-1 #1 Last Second CV-P
PM_STS1_CVP_CNT
192
Count (RO)
STS-1 #1 Path Overhead
SD_INSERT
192
Maintenance (R/W)
STS-1 #1 Path Overhead
SF_THRESH_SEL
192
Maintenance (R/W)
STS-1 Signal Fail Detect
SF_STS1_DET_THRESH_n 8
Threshold, Window Size
Select 0 (R/W)
STS-1 Signal Fail Clear
SF_STS1_CLR_THRESH_n 8
Threshold, Window Size
Select 0 (R/W)
Signal Fail Window Size 0
SF_WIN_SIZE_0
4
(R/W)
STS-1 #1 Alarm Interrupt
SIG_FAIL
192
Status (W1C)
3010
146
3017
148
3011
146
3011
146
4002
150
4003
150
4012
153
3013
147
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Path Signal Label (C2). The path signal label byte is used to indicate either the type of payload carried in the STS
SPE or the status of the payload. See Table 41 for label assignments.
Table 41. STS Path Signal Label Assignments
Code
(Hex)
Content of the STS SPE
Code
(Hex)
00
01
02
03
04
E1
Unequipped
Equipped—nonspecific payload
VT-structured STS-1 SPE
Locked VT mode
Asynchronous mapping DS3
VT-structured STS-1 SPE with 1 VTx payload defect (STS-1 w/1 VTx PD)
STS-1 with 2 VTx PDs
STS-1 with 3 VTx PDs
STS-1 with 4 VTx PDs
STS-1 with 5 VTx PDs
STS-1 with 6 VTx PDs
STS-1 with 7 VTx PDs
STS-1 with 8 VTx PDs
STS-1 with 9 VTx PDs
STS-1 with 10 VTx PDs
STS-1 with 11 VTx PDs
STS-1 with 12 VTx PDs
STS-1 with 13 VTx PDs
STS-1 with 14 VTx PDs
12
13
14
15
16
EF
Asynchronous mapping for DS4NA
Mapping for ATM
Mapping for DQDB
Asynchronous mapping for FDDI
Mapping for HDLC-PPP (proposed)
STS-1 with 15 VTx PDs
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
STS-1 with 16 VTx PDs
STS-1 with 17 VTx PDs
STS-1 with 18 VTx PDs
STS-1 with 19 VTx PDs
STS-1 with 20 VTx PDs
STS-1 with 21 VTx PDs
STS-1 with 22 VTx PDs
STS-1 with 23 VTx PDs
STS-1 with 24 VTx PDs
STS-1 with 25 VTx PDs
STS-1 with 26 VTx PDs
STS-1 with 27 VTx PDs
VT-structured STS-1 SPE with 28 VT1.5
payload defects, or a nonstructured
STS-1 or STS-Nc SPE with a payload
defect
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
Content of the STS SPE
Of the 256 possible values, only the codes 0x01 to 0x04 and 0x12 to 0x15 are currently defined to identify payload
types, while the codes 0xE1 to 0xFC are defined to indicate payload defects (see Table 41). The valid payload specific codes are, by default, 0x02 to 0xE0, 0xFD, and 0xFE. The codes 0xE1 to 0xFC are used for indicating defects
in the payload. The code 0xFF is a special reserved code due to its appearance in an STS AIS and is treated as a
do not care during any defect detection or clearing.
The C2 byte is extracted each frame and can be accessed from the per STS-1 path C2, RDI status register. The
extracted C2 byte is also validated for five consecutive frames. If the locally provisioned value, configured in the
per STS-1 path overhead provisioning registers, is any equipped value (i.e., not 0x00), the validated signal label is
processed for the following listed defects.
Agere Systems Inc.
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
■
■
■
Payload Label Mismatch (PLM)—Detected if the validated signal label is a valid payload-specific code and does
not match the provisioned expected signal label code in the per STS-1 path overhead provisioning register.
Cleared if the extracted signal label, validated for five consecutive frames, matches the locally provisioned value,
the equipped nonspecific code (0x01), the unequipped code (0x00), or a valid PDI code. If the locally provisioned
value is the equipped nonspecific code, then it matches any equipped code (including PDI). Detection of a PLM
defect is indicated by a maskable latched alarm bit in the per STS-1 channel path alarms register. The PLM alarm
is also followed by a persistency register bit in the per STS-1 path alarm persistency register. Detection of a PLM
defect causes a PLM-specific code to be sent in the E1 and F1 overhead bytes for that STS-channel on the drop
interface.
Path Unequipped (UNEQ)—Detected if the validated signal label matches the unequipped code (0x00). Cleared
if the extracted signal label does not match the unequipped code for five consecutive frames. Detection of an
UNEQ defect is indicated by a maskable latched alarm bit in the per STS-1 channel path alarms register and by a
PM status bit in the per STS-1 path overhead last second bin register. The UNEQ alarm is also represented by a
persistency register bit in the per STS-1 path alarm persistency register. Detection of an UNEQ defect causes a
UNEQ-specific code to be sent in the E1 and F1 overhead bytes for that STS-channel on the drop interface; see
the STS-12 Overhead Insertion and Scrambling section on page 77.
Payload Defect Indication (PDI)—Detected if the validated signal label matches a valid PDI code. Codes 0xE1 to
0xFC are valid if the locally provisioned payload is VT-structured (0x02 or 0x03) or equipped nonspecific (0x01).
Only 0xFC is a valid PDI code for other payload types which are not VT-structured. Cleared if the extracted signal
label does not match a valid PDI code for five consecutive frames. PDI detection can be disabled by a control bit
in the per STS-1 path overhead provisioning register. Detection of a PDI defect causes the PDI code to be sent in
the E1 and F1 overhead bytes for that STS-channel on the drop interface; see the STS-12 Overhead Insertion
and Scrambling section on page 77.
The scenarios presented by different expected and received (validated) signal label codes are presented in
Table 42.
Table 42. Path Signal Label (C2) Alarm Scenarios
All C2 Code
Values
are in Hex
Extracted C2 Byte (Validated Five Consecutive Frames)
00
[Unequipped]
01
[Equipped
Nonsp]
02, 03
[VT-Structur
ed]
Provisioned
C2 Byte
00
04—E0,
FD, FE
E1—FB
[VT PDI]
FC
[PDI]
FF
[AIS]
No Alarms
01
UNEQ-P
MATCH
MATCH
MATCH
PDI-P1
PDI-P1
No Change
02, 03
UNEQ-P
MATCH
MATCH 2/
PLM-P3
PLM-P
PDI-P1
PDI-P1
No Change
04—E0,
FD, FE
UNEQ-P
MATCH
PLM-P
MATCH2/
PLM-P3
PLM-P1
PDI-P1
No Change
E1—FB
FC
Invalid
Provisioning
FF
1. If PDI-P detection is provisioned.
2. If extracted, validated C2 code = provisioned C2 code.
3. If extracted, validated C2 code ≠ provisioned C2 code.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 43. C2 Register Summary
Function
Extracted C2 Byte
Provisioned (Expected) C2
Value
PLM Latched Alarm
PLM Persistency
UNEQ Latched Alarm
UNEQ Persistency
Last Second UNEQ PM
PDI Detection Disable
Register Name
(First Occurrence)
Register Bits
Qty.
1st Page
Addr
(hex)
STS-1 #1 Path Overhead
Status (RO)
STS-1 #1 Path Overhead
Provisioning (R/W)
STS-1 #1 Alarm Interrupt
Status (W1C)
STS-1 #1 Alarm Persistency
(RO)
STS-1 #1 Alarm Interrupt
Status (W1C)
STS-1 #1 Alarm Persistency
(RO)
STS-1 #1 PM Last Second
Indicators (RO)
STS-1 #1 Path Overhead
Provisioning (R/W)
RCV_C2_BYTE
192
3012
147
PROV_STS1_EXP_C2
192
3010
146
PLM_P
192
3013
147
PLM_P_PERS
192
3015
148
UNEQ_P
192
3013
147
UNEQ_P_PERS
192
3015
148
UNEQ
192
3016
148
PDI_EN
192
3010
146
Path Status (G1). The path status byte is used to convey the path termination status and performance back to the
originating STS PTE. This allows the performance of the full-duplex path to be monitored from any single point
along the path. Bits 1 to 4 are used as a remote error indication (formerly far-end block error, or FEBE), while
bits 5—7 are used as a remote defect indication. The G1 byte is extracted from each frame and processed for the
following functions:
■
■
Remote error indication (REI-P). Indicates the count of bit errors detected at the far-end STS PTE using the path
BIP-8. The error count is a binary number from 0 to 8 (values above eight are invalid and are interpreted as zero)
and is accumulated in an internal 16-bit counter based on either bit or block errors as provisioned per channel
through the microprocessor interface. If bit error mode is enabled for the channel, the counter is incremented by
the actual error count. If block error mode is enabled for the channel the counter is only incremented by one, when
the error count is between 1 and 8, regardless of the actual value. The control bit for counting bit or block errors
is in the per STS-1 path overhead provisioning register. The value in the counter accumulates until it is transferred
to the per STS-1 last second REI-P count registers at the positive edge of the PM_CLK input, at which point the
counter is cleared. The counter will stop at the maximum value and will not roll over.
Remote defect indication (RDI-P). Indicates the detection of a defect at the far-end STS PTE. Initially, RDI-P was
defined as a 1-bit value in bit 5, but has since been expanded to a 3-bit enhanced value (ERDI-P). Table 44 on
page 76 shows the valid codes and interpretation for both the 1-bit and enhanced RDI schemes. As can be seen,
bits 6 and 7 are always set to opposite values for ERDI while they are set to the same value for 1-bit RDI. The
POH uses this fact to determine which RDI scheme is being used on a per STS basis. An RDI-P defect is then
detected if a valid defect code for one of the RDI schemes is received for ten consecutive frames. The RDI-P
defect is cleared when the no defects code for that scheme is received for ten consecutive frames. Any validated
RDI-P defect is indicated by a maskable latched alarm bit in the per STS-1 channel path alarms register. Any
validated 3-bit RDI code extracted is stored in the per STS-1 path C2, RDI status register. The RDI alarm is also
followed by a persistency register bit in the per STS-1 path alarm persistency register. In addition, there are 4 PM
status bits to report decoded RDI in the per STS-1 path overhead last second bin register, which are updated at
the positive edge of the PM_CLK input.
Agere Systems Inc.
75
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 44. RDI-P Codes and Interpretation
G1[5:7]
Priority of Enhanced
RDI-P Codes
Trigger
Interpretation
0xx1
Not Applicable
No Defects
No RDI-P Defect
1xx1
Not Applicable
AIS-P, LOP-P
1-bit RDI-P Defect
0012
4
No Defects
No ERDI-P Defects
0102
3
PLM-P, LCD-P
ERDI-P Payload Defect
1012
1
AIS-P, LOP-P
ERDI-P Server Defect
1102
2
UNEQ-P, TIM-P
ERDI-P Connectivity Defect
1. These codes are transmitted by STS PTE that do not support enhanced RDI-P. If enhanced RDI-P is not supported, G1 bits 6
and 7 must be set to the same value, and should be set to 00.
2. These codes are transmitted by STS PTE that support enhanced RDI-P.
Table 45. G1 Register Summary
Function
Bit/Block Error Counting
Selection
Last Second REI-P Count
RDI-P Latched Alarm
Validated 3-bit RDI-P Code
RDI-P Persistency
Last Second RDI-P PM
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
STS-1 #1 Path Overhead
Provisioning (R/W)
STS-1 #1 Last Second REI-P
Count (RO)
STS-1 #1 Alarm Interrupt
Status (W1C)
STS-1 #1 Path Overhead
Status (RO)
STS-1 #1 Alarm Persistency
(RO)
STS-1 #1 PM Last Second
Indicators (RO)
CNT_BLK_ERRS
192
3010
146
PM_STS1_REIP_CNT 192
3018
148
RDI_P
192
3013
147
RCV_RDI_CODE
192
3012
147
RDI_P_PERS
192
3015
148
RDI_ONE_BIT
ERDI_PYLD
ERDI_CONN
ERDI_SRVR
192
3016
148
Receive Payload Drop Interface
This block is replicated four times. Each block accepts four STS-12 data streams from the path processor and converts them to four 1-bit wide STS-12 serial streams at 622 MHz. The data is formatted as an STS-12 signal; however, most of the transport overhead bytes are either unused or are used for proprietary purposes.
Framing, BIP-8 parity, and alarm status are inserted into the TOH bytes of each STS-12, and then the data is
optionally scrambled.
Each STS-12 data stream is output as a 1-bit wide 622 MHz serial stream. The four 1-bit wide serial STS-12 data
streams are output along with a single 1-bit wide control output that carries timing information for all four of the data
outputs.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
STS-12 Overhead Insertion and Scrambling
The payload drop interface uses several of the TOH bytes to pass information to the payload device. All unused
bytes have all zeros inserted in them. After the overhead bytes are inserted, all bytes in the STS-12, except the
framing bytes, are scrambled with the SONET standard 1 + x6 + x7 algorithm, unless scrambling is disabled (for all
STS-12 links) through the scrambling disable bit in the receive drop STS-48 channel n provisioning register. The
bytes used, and their functions, are described as follows:
■
■
■
■
A1 and A2 positions: carry normal STS-12 framing.
J0 position: inserted in the first STS-1 of each STS-12 only, and carries an 8-bit provisionable ID value for the
STS-12. This value is specified in the J0 trace—STS-12 channel n register.
B1 position: inserted in the first STS-1 of each STS-12 only, and carries a BIP-8 calculated for all of the bits in the
previous frame. As per the section BIP definition in GR-253, the BIP-8 is calculated on the scrambled data and
then inserted in B1 for the next frame, before the byte is scrambled. Errors can be inserted in the B1 bytes of all
STS-12 links through the BIP-8 error insertion bit in the receive drop STS-48 channel n provisioning register.
E1 and F1 positions: inserted in each STS-1 and carry path level alarms for that STS channel. Both bytes carry
the same 6-bit value, which encodes the path alarm information, as shown in Table 46.
Table 46. Path Alarm Information Encoding
E1/F1 Value
00111111
11111111
00111110
00111101
00111100—
00100001
00011111
00011110
00000000
■
■
■
Definition
Loss of pointer or path AIS.
Concatenation mismatch or software AIS insertion.
Unequipped signal label.
Signal fail (SF).
PDI code 28 to PDI code 1.
Signal degrade (SD).
Payload label mismatch.
No alarms.
D1, D2, and D3 positions: inserted in the first STS-1 of each STS-12 only and carry a 192 kHz data channel that
is sourced by the RDDCCn (1 to 16) input, and is clocked on the positive edge of RDDCKn (1 to 4).
K1 and K2 positions: inserted in both the first and second STS-1 of each STS-12. The first STS-1 carries the
validated K bytes, while the second STS-1 carries the raw K bytes for the STS-48 or STS-192 that contained the
STS-1 channel. The K bytes are extracted in the receive TOH processing block. See the APS Channel (K1 and
K2) section on page 58.
E2 position: inserted in the first STS-1 of each STS-12 only, and carries line level alarms for the STS-48 or
STS-192 that contained the STS-12 channel. The bit assignments for the E2 byte are shown in Table 47 on
page 78.
Agere Systems Inc.
77
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 47. Line Alarm Information Encoding
E2 Value
00111
00110
00101
00100
00011
00000000
Definition
Loss of Signal
Loss of Frame
Line AIS
Signal Fail (SF)
Signal Degrade (SD)
No Alarms
Table 48. Drop Interface Overhead and Scrambling Register Summary
Function
Scrambling Disable Control
Section Trace (J0) ID Value
B1 Error Insertion
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
Receive Drop STS-48 Channel
Provisioning Register 1 (R/W)
J0 Trace—STS-12 Channel 1
(R/W)
Receive Drop STS-48 Channel
Provisioning Register 1 (R/W)
SCRM_DISABLE
4
2400
137
J0_BYTE_n
16
2401
137
B1_ERROR_INS
4
2400
137
Drop Interface Output Format
Drop Data and Drop Clock. Each STS-12 data stream is output as a 1-bit wide 622 MHz serial stream. The
622 MHz clock is internally generated with a PLL whose reference is the 77.76 MHz D_CLK input (or the R_CLKn
that corresponds to the STS-48 in which the STS-12 belongs, if drop alignment is bypassed).
DCTL Outputs. In addition to the four STS-12 data streams, a 1-bit wide control signal (DCTL_[1—4]) that supplies timing enables for the data streams is output. These timing enables are encoded using a 2-bit vector for each
byte of each STS-12. Thus, there is one byte of timing control for each byte of data from the four STS-12 streams.
This byte of timing control is then scrambled using the standard 1 + x6 + x7 algorithm, passed to a high-speed multiplexer module, and output at 622 MHz synchronized to the STS-12 data as shown in Figure 8 on page 79. The
encoding of the timing enable bits is shown in Table 49 on page 79.
The DCTL_[1—4] outputs may be used by other devices that terminate the SPE path, such as external data
engines. By using the DCTL codes, the SPE can be extracted from the output data without the need for another
pointer interpreter inside the path terminator. The path overhead and payload can be separated as well. These outputs may be left unconnected if not used.
DFRM. The frame alignment is determined by the DFRM input, which is synchronous to the D_CLK input, and is
determined from the rising edge of the DFRM if it remains high for at least four D_CLK edges. Therefore, DFRM
can be an 8 kHz clock or frame pulse meeting the minimum requirement of being high for four D_CLK edges. The
beginning of the first A1 byte on each of the STS-12 outputs occurs approximately nine D_CLK cycles after the rising edge of DFRM.
78
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
STS-12
CHANNEL 1
STS-12 CHANNEL 1 BYTE N
STS-12 CHANNEL 1 BYTE N + 1
...
STS-12
CHANNEL 2
STS-12 CHANNEL 2 BYTE N
STS-12 CHANNEL 2 BYTE N + 1
...
STS-12
CHANNEL 3
STS-12 CHANNEL 3 BYTE N
STS-12 CHANNEL 3 BYTE N + 1
...
STS-12
CHANNEL 4
STS-12 CHANNEL 4 BYTE N
STS-12 CHANNEL 4 BYTE N + 1
...
TIMING
ENABLES
CHANNEL
1
CHANNEL
2
CHANNEL
3
CHANNEL
4
CHANNEL
1
CHANNEL
2
CHANNEL
3
CHANNEL
4
...
CHANNEL
1
5-8407(F)r.1
Figure 8. STS-12 Data Outputs and Timing
Table 49. Timing Enable Bit Definitions
Timing Enable Bits
Definition
00
01
10
11
TOH bytes
SPE bytes
POH bytes
J1 byte
All control bytes follow this format, except the A1, A2, and B1 bytes in the section overhead. The A1 and A2 bytes
carry the standard nonscrambled STS framing, while the B1 byte carries a BIP-8 calculated for all bytes in the previous frame after scrambling. If any STS-1 channel has AIS inserted in it by the path processor, the timing enables
for that channel will always indicate a nominal SPE (i.e., no stuffs) with POH in column 4 and no J1 byte.
Data Path Parity
The receive payload drop interface terminates the internal data path including 1 bit of parity that is added to every
byte of STS-48/STS-192 data through the device. This parity bit is compared to the calculated parity of the data
path, and parity errors are reported in the corresponding bit in the receive drop STS-48 channel nonservice-affecting alarm register.
Table 50. Receive Data Path Parity Register Summary
Function
Data Path Parity Latched
Alarm
Agere Systems Inc.
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
Receive Drop STS-48 Channel
Nonservice-Affecting Alarm (W1C)
RX_DATA_PAR_
ERR_n
4
2405
138
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Regenerator Loopback (STS-192 Mode Only)
This feature is software provisioned to set up a regenerator loopback mode that loops back receive data and overhead towards the transmit line interface. When this feature is enabled, the transmit clock is derived from the
receive clock at the 622 MHz level external to the device. The add interface buffers align the data between the
receive and transmit clock domains. The TFRM signal is replaced by receive frame timing using the new add interface self sync option to transfer from the receive to the transmit clock domains.
The option is enabled in software by setting the appropriate bit, REGEN_LOOPBACK, in the LTE transmit channel
1—4 provisioning (R/W) registers (0x1C00, 0x1D00, 0x1E00, and 0x1F00, respectively). The appropriate bit definitions are shown in Table 52. This mode will only function correctly when the device is in STS-192 mode. It will not
work in STS-48 mode, since the four STS-48 streams need to be aligned through the transmit side. Four received
STS-48 streams are unlikely to be aligned to the same clock and frame alignment.
The REGEN loopback control from channel 1 will enable this mode for all four STS-48 channels when in STS-192
mode. The appropriate per-STS-48 transmit line AIS insert control will be active during receive LOS, receive LOF,
or R_CLK failure while in regenerator loopback.
Table 51. LTE Transmit Channel Registers—Regenerator Loopback Summary
Function
Regenerator
Loopback Enable
Register Name
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Transmit Channel 1
Provisioning (R/W)
REGEN_LOOPBACK
4
1C00
130
Table 52. Regenerator Loopback Bit Definitions
Bit 8
0
1
Definition
Powerup default.
Regenerator loopback—drop data looped back to add side.
Transmit Payload Add Interface
This block is replicated four times. Each block accepts four 1-bit wide STS-12 serial streams at 622 MHz and converts them to STS-48 data. This conversion is performed in three stages.
In the first stage, each STS-12 has framing recovered, is optionally descrambled, and has certain TOH bytes processed.
In the second stage, each STS-12 is passed through a buffer to synchronize the data to the common transmit clock
and frame.
Finally, in the third stage, the four STS-12 data streams are multiplexed into a single STS-48 data stream. This
multiplexing is performed by a time-slot multiplex (TSM) module that reorders the bytes in the STS-12 data streams
to provide a correctly ordered STS-48 data stream.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
STS-12 Framing, Descrambling, and TOH Processing
As the transmit TOH processor overwrites all of the TOH bytes in all STS channels, the payload add interface uses
several of these TOH bytes to receive information from the payload device. The bytes used, and their functions,
are described as follows:
■
■
■
■
A1 and A2 positions: carry normal STS-12 framing. The payload add interface recovers framing for each of the
STS-12 data streams and uses it to frame and byte align the STS-12 data word. In addition to byte alignment, the
frame timing is also used to descramble all bytes in each STS-12, except the framing, using the SONET standard
1 + x6 + x7 algorithm (unless descrambling is disabled for all STS-12 links, through the transmit add STS-48
channel provisioning register). Once in-frame, an out-of-frame (OOF) defect is detected when two consecutive
errored framing sequences are received. The detection of an OOF defect is indicated by a latched alarm status
bit in the transmit add STS-48 channel n alarm register, and causes AIS to be inserted in all affected STS-1
channels.
J0 position: present in the first STS-1 of each STS-12 only, and carries an 8-bit ID value for the STS-12. This
value is extracted and stored in the J0 status register.
B1 position: present in the first STS-1 of each STS-12 only, and carries a BIP-8 calculated for all bits in the
previous frame. As per the section BIP definition in GR-253, the BIP-8 is calculated on the scrambled data, and
then compared to the B1 in the next frame after the byte is descrambled. Any errors detected will cause the BIP-8
error latched alarm status bit to be set in the transmit add STS-48 channel alarm register. Detection of BIP errors
is inhibited while the STS-12 is OOF, and for one frame following reframe.
E1 and F1 positions: present in each STS-1 and carry path AIS insertion control for that STS channel. Both bytes
carry the same value which encodes the path AIS insertion control as shown in Table 53. An AIS insertion request
in either byte will cause AIS to be inserted in that channel and will set a read-only status bit in the AIS insert status
register.
Table 53. Path AIS Insertion Encoding
E1/F1 Value
00111111
00000000
■
■
■
Definition
Path AIS Insertion
No Alarms
D1, D2, and D3 positions: present in the first STS-1 of each STS-12 only, and carries a 192 kHz data channel that
is serialized, and then output, on the TDDCCn (1 to 16) pin on the positive edge of TADCK. While the
STS-12 is OOF, an HDLC abort (0x7F) is continually sent.
K1 and K2 positions: present in both the first and second STS-1 of each STS-12. The first STS-1 carries validated
K bytes, while the second STS-1 carries raw K bytes that can be optionally inserted in the TOH bytes of the
STS-48 or STS-192, that contain that STS-12 channel as their first STS-12 of data. While the STS-12 is OOF, the
K1 values inserted in the TOH bytes are inverted in each frame to cause a downstream APS failure, while the K2
values are held.
E2 position: the transmit add interface does not process the E2 byte.
Agere Systems Inc.
81
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 54. Add Interface Overhead and Scrambling Register Summary
Function
Descrambling Disable
OOF Latched Alarm
Section Trace (J0) ID Value
B1 Error Latched Alarm
E1/F1 AIS Insertion Status
K1K2 Insertion Into Line TOH
Control
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
Transmit Add STS-48 Channel
Provisioning (R/W)
Transmit Add STS-48 Channel
Alarm (W1C)
J0 Status Register—1 (RO)
DESCRM_DISABLE
4
2C00
139
OOF_1
4
2C09
142
J0_BYTE—STS-12
Channel 1
B1_ERROR_1
16
2C01
139
4
2C09
142
AIS_INSERT_n
16
2C05
140
TX_K_BYTES_
SELECT_1
4
1C01
131
Transmit Add STS-48 Channel
Alarm (W1C)
AIS Insert Status Register, STS-12
Channel #1 (RO)
LTE Transmit Channel 1 Maintenance (R/W)
Transmit Synchronization Buffer
Each STS-12 data stream recovers its own clock and possesses a slightly different frame phase. The purpose of
this buffer is to synchronize the STS-12 data to the common transmit clock and frame phase. Note, however, that it
is only intended to compensate for a phase offset between the STS-12 data stream and the transmit timing. It will
not compensate for a frequency offset. Any frequency offset will eventually cause a buffer overflow/underflow,
which is indicated by a latched status bit in the transmit add STS-48 channel alarm register.
The buffer is also only intended to compensate for 75 ns of delay skew between the STS-12 data stream and the
transmit frame phase. Any additional phase offset, which must be common to all STS-12 data streams, can be
compensated using the transmit frame offset feature described in Add Interface Framing (A1 and A2).
Since the detection of a buffer overflow/underflow is asynchronous in nature, the transmit add STS-48 channel provisioning register contains a force add buffer overflow bit which allows testing of the add buffer overflow alarm bit.
Table 55. Transmit Synchronization Buffer Register Summary
Function
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
Force Add Buffer Overflow
Control
Buffer Overflow Latched Alarm
Transmit Add STS-48 Channel
Provisioning (R/W)
Transmit Add STS-48 Channel
Alarm (W1C)
FRC_ADD_BUFFER
_OVRFLW
ADD_12_BUFFER_
OVRFLW_1
4
2C00
139
4
2C09
142
Add Interface Framing (A1 and A2)
The STS framing bytes are present in all STS-1 time slots of the STS-48 or STS-192. When normal framing is
selected, the A1 bytes are set to 0xF6, while the A2 bytes are set to 0x28. If enhanced framing is selected, using
the framing mode control bit, the A1 and A2 bytes contain normal framing in odd STS-1 time slots and the inverse
value in even STS-1 time slots. The add interface framer is a simplified SONET/SDH framer. It frames based on
both the A1/A2 boundary and the repetitive nature of the boundary (that the A1/A2 boundary recurs every
810 × 12 bytes).
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Data Sheet
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Functional Description (continued)
TFRM Framing Signal. The alignment of the generated frame is determined by the TFRM input signal and the
value stored in the Tx frame offset register. The TFRM input provides a common frame reference for all add
STS-12 data streams. The TFRM input is an 8 kHz signal and is sampled with the 622.08 MHz T_CLK. The frame
position is at the rising edge of the TFRM signal when it has been low for at least 32 T_CLK clock periods and then
stays high for at least 32 more (i.e., a 0000 1111 pattern). This transition should be present at approximately the
average position of the start of the first A1 byte in all of the add interface STS-12 serial inputs.
If the TFRM is not aligned to the input data, the frame position can be delayed by the value in the Tx frame offset
register, specified in multiples of 12.86 ns (eight 622.08 MHz clock cycles), which produces the transmit frame timing reference. A value of zero specifies no delay and the maximum value for this register is 9719. This range is
equivalent to advancing the frame timing reference over an entire STS-12 period. This offset is required to align
the transmit frame position with the frame position of the add STS-12 data streams as described in the Transmit
Synchronization Buffer section on page 82.
If the TFRM rising edge should jitter with respect to the 622.08 MHz T_CLK, jitter on the TFRM input can be compensated for up to ±16 T_CLK cycles from the starting position without affecting the generated frame position. This
compensation is enabled with the TX_FRM_DEJITTER_EN bit in the LTE transmit provisioning register. If the
TFRM input drifts more than ±16 T_CLK cycles from its starting position, the transmit frame position is realigned to
the next TFRM frame position (plus any offset added in the offset register), and a TX_FRM_RESYNC alarm is produced.
If the TFRM frame signal is not received at least once every eight frames (i.e., 1 kHz), TFRM synchronization loss
is indicated in the TFRM LOF alarm bit. During TFRM synchronization loss, AIS-P is inserted as described in the
STS Payload Pointer (H1 and H2) section on page 88. While frame synchronization, once established, could be
continued by counting clock cycles, the requirement for the TFRM signal to be provided at least once every eight
frames provides an important check on system function. The TFRM input is a required signal for the transmit side
of the TSOT0410G4. Recovery of TFRM frame sync is described in the Synchronization Status (S1) section on
page 91.
Add Interface Self-Sync Option. The TFRM input can be obtained from the add interface through a self-sync
option to provide a common frame reference for all add STS-12 data streams as an alternate to the TFRM input.
The transmit add synchronization enable option provides for the use of the frame timing from one of the add
pseudo STS-12 links as the transmit frame sync instead of TFRM. This option provides the frame sync from the
add clock domain to the T_CLK clock domain. The option is enabled with the ADD_TX_SYNC (bit 15) in the LTE
transmit common provisioning register. When the self-sync option is enabled, the frame is sampled and then the
add interface free-runs until either the feature is disabled and reenabled, or when the ADD12 (out of frame on used
link) or T_CLK failure alarm is set and clears. Therefore, when changing the ADD12 link, the feature should be disabled and then reenabled after the channel is changed.
The add interface self-sync feature automatically resynchronizes when a buffer overflow/underflow is detected.
This resyncing is inhibited if the selected ADD12 is out-of-frame. The resync function is implemented by resampling the selected ADD12 frame timing and using that to realign the buffer write pointer. The only limit to the resync
property is that it only resamples the frame timing once after an overflow/underflow and there is no guarantee that
the buffer is centered; i.e., if the clock drift continues after the overflow/underflow.
When the ADD_TX_SYNC bit in the LTE transmit common provisioning is set to 1, the frame pulse will be derived
from the add interface input. Bit 0 through bit 3 in the LTE transmit common provisioning register then select which
add channel (1—16) the TFRM will be obtained from. Bits 4—14 are unused in that case. See Table 128 on
page 128.
The preferred method of provisioning the add interface self-sync option is to provision the ADD_TX_SYNC register
with the selected channel first, and then in the next write, provision the ADD_TX_SYNC enable.
Note: The add-sync option should be disabled before the regenerator loopback option is enabled. Enabling
regenerator loopback before the add sync option can cause transmit timing to corrupt overhead bytes.
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STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 56. Frame Pulse Provisioning Bit Definitions
Bit 15
ADD_TX_SYNC
Bit 14
TX_FRM_DEJITTER_EN
0
1
0
0
0
1
Definition
Reset default.
Transmit add synchronization enabled.
TFRM dejitter circuit enable.
Table 57. Transmit Framing Register Summary
Function
Enhanced Framing
Mode Control
Transmit Frame Offset
Control
Transmit Frame Dejitter
Control
Transmit Frame Resynchronization Latched
Alarm
TFRM Synchronization
Loss Latched Alarm
Transmit Add
Synchronization
Enable
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Transmit Channel 1
Provisioning (R/W)
LTE Transmit—Frame
Pulse Offset Count (R/W)
LTE Transmit—Frame
Pulse Offset Count (R/W)
LTE Transmit—Interrupt
Alarm Register (W1C)
TX_FRAMING_MODE_1
4
1C00
130
LTE_TX_FRM_OFFSET_COUNT
1
1B00
128
TX_FRM_DEJITTER_EN
1
1B00
128
TX_FRM_RESYNC
1
1B05
129
TX_FRM_LOF
1
1B05
129
ADD_TX_SYNC
1
1B00
128
LTE Transmit—Interrupt
Alarm Register (W1C)
LTE Transmit—Frame
Pulse Offset Count
4:1 Time-Slot Multiplex (TSM)
In order to multiplex the four STS-12 data streams into a valid STS-48 data stream, the bytes in the STS-12 data
streams must be reordered. This reordering is needed due to the STS-N multiplexing rules, which require an
STS-12 channel to be interleaved in 4-byte chunks.
Transmit Transport Overhead (TOH) Processor
This block is replicated four times. Each block accepts the data for one STS-48 channel from the transmit payload
add interface, and inserts the transport section and line overhead. The inserted overhead is either sourced internally, or provided externally on serial inputs. If sourced internally, the overhead may be from registers in the microprocessor interface, or derived.
In STS-48 mode, each channel carries complete transport overhead. In STS-192 mode, only the first STS-48 channel carries complete transport overhead, while the other channels only carry framing (A1, A2), Z0, and line BIP-8.
In addition, the line overhead bytes can all be overwritten with all ones (along with all of the payload SPE bytes) by
enabling line AIS insertion in the memory map.
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
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Functional Description (continued)
TOH Transparency
The TOH transparency option provides a passthrough capability for the TOH on the line interface to/from the TOH
on the equipment interface. When this feature is enabled, both the transmit and receive sections will be provisioned to the same mode (i.e., the function cannot be set up differently in transmit and receive directions).
The transmit direction has the option for full TOH transparency or just line overhead (MSOH) transparency with
section (RSOH) overhead insertion. The receive direction has the option for full TOH transparency or just line overhead transparency with section overhead used for the normal proprietary drop I/F OH.
This feature is available on a per STS-48 level by setting the TOH transparency enabled bit and the line TOH
transparency only enabled bit of the LTE transmit channel provisioning register. When TOH transparency is appropriately provisioned, the pointer processor will be bypassed on a per STS-48 level. If enabled, AIS insertion due to
an E1/F1 code in the add TOH will be disabled. Enforcing AIS-L from the transmit side does operate even using full
transparency.
During full or line transparency, the only access to the OH bytes is through the TOHDAT interface. The microprocessor-based features that would modify the line or section overhead will not be available. If overhead bytes are
inserted using the TOHDAT interface, a valid B1 must be inserted for full transparency and/or B2 for full or line
transparency.
The option is enabled in software by setting the appropriate bits, TOH_TRANS_EN and LINE_TRANS_ONLY_EN,
in the LTE transmit channel 1—4 provisioning registers (0x1C00, 0x1D00, 0x1E00, and 0x1F00, respectively). The
appropriate bit definitions are shown in Table 58. TOH transparency feature is always supported on individual
STS-48 channels and will require all four channels to be provisioned in STS-192 mode.
Table 58. LTE Transmit Channel Registers—TOH Transparency Summary
Function
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
TOH Transparency
Enabled
Line TOH Transparency
Only Enabled
LTE Transmit Channel 1
Provisioning (R/W)
LTE Transmit Channel 1
Provisioning (R/W)
TOH_TRANS_EN
4
1C00
130
LINE_TRANS_ONLY_EN
4
1C00
130
Table 59. TOH Transparency Bit Definitions
Bit 7
LINE_TRANS_ONLY_EN
Bit 6
TOH_TRANS_EN
Definition
X
0
0
1
1
1
Section and Line Terminated (pointer processor
state dependent on DRPBYP pin).
Full Section and Line Overhead Transparency
(pointer processor is bypassed automatically).
Line Overhead Transparency Section Is Terminated
(pointer processor is bypassed).
Note: X denotes either state.
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STS-192 Overhead and Path Processor
Data Sheet
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Functional Description (continued)
Transmit Overhead Serial Links
In addition to the individual provisioning or external availability of the overhead bytes, the full set of transport overhead bytes for the STS-48 channel (1296 bytes) can be sourced serially using the TOHDAT_n_[1:0] pins. Insertion
must be globally enabled in software, using the TOH data insert control bit, and then enabled on a per-byte basis
by strobing the TOHEN_n pin high during the LSB of the byte to insert (the state of the TOHEN_n is ignored during
the other bits). The bytes are received MSB first, with each pair of bits input on the positive edge of TOH_CLK_n
(41.472 MHz). The location of the MSB bit of the first A1 byte is identified by the TOHFP_n output going high. For
B1 and B2, the value received is actually used as an XOR corruption mask for the internally calculated values.
In STS-48 mode, the TOHDAT_n_[1:0] pins, along with the TOHEN_n pin, capture the transport overhead for that
STS-48 channel. In STS-192 mode, the four pairs of TOHDAT_n_[1:0] pins, along with their respective TOHEN
pins, capture the entire STS-192 overhead (5184 bytes), where the TOHDAT_1 pins capture STS channels
1 through 48, and the TOHDAT_2, TOHDAT_3, and TOHDAT_4 pins capture STS channels 49 through 96,
97 through 144, and 145 through 192, respectively. The timing for this is described in the Transmit Overhead Serial
Link section on page 180.
Internally, a memory is used for each channel to buffer the data and transfer it between the external data rate and
the internal data rate. The operation of the memory is monitored using parity and any errors are reported using the
TOHDAT parity error alarm bit. This alarm bit is present in the LTE transmit channel n interrupt alarm register and is
valid regardless of the mode (STS-48 or STS-192) in which the device is operating.
When enabled, the overhead serial link takes precedence over all other overhead sources, with the exception of
software enabled line or path AIS insertion or path unequipped insertion.
Table 60. Transmit Overhead Serial Links Register Summary
Function
Global TOH Data Insert
Control
TOH Buffer Parity Error
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Transmit Channel 1
Provisioning (R/W)
LTE Transmit Channel 1
Interrupt Alarm (W1C)
TX_TOH_DATA_INSERT_1
4
1C00
130
TX_OH_MEM_PARITY_ERR_1
4
1C0C
133
Section Trace/Section Growth (J0/Z0)
The section trace byte is present in the first STS-1 of the STS-48 or STS-192 only. The TOH processor supports
insertion of either SONET 64-byte (ASCII, <CR><LF> terminated) or SDH 16-byte (E.164) section trace messages. The message is stored in internal memory and should be repeated four times if a 16-byte SDH message is
to be sent. The message is provisioned by software using the section trace access registers (see the Section Trace
(J0) section on page 53 for details). After the message is provisioned, insertion of the message must be enabled
through the J0 Msg insert control bit. If insertion is not enabled, the J0 byte is instead sent as 0x01 for STS-48
mode or 0xCC for STS-192 mode.
The section growth bytes present in the remaining STS-1 locations of the STS-48 or STS-192 are set to the fixed
pattern 0xCC in STS-192 mode, or to an increasing binary count (2 to 48, corresponding to order of appearance) in
STS-48 mode.
Internally, a memory is used to store four section trace messages, one for each channel. The operation of the
memory is monitored using parity, and any errors are reported using the transmit J0 parity error alarm bit that is
reported in the LTE transmit interrupt alarm register.
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Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Table 61. Transmit Section Trace (J0) Register Summary
Function
Section Trace Message
Insert Enable Control
J0 Memory Parity Error
Register Name
(First Occurrence)
Register Bits
LTE Transmit Channel 1 TX_J0_MSG_INSERT_EN_1
Maintenance (R/W)
LTE Transmit—Interrupt TX_J0_MEM_PARITY_ERR
Alarm Register (W1C)
Qty.
1st
Addr
(hex)
Page
4
1C01
131
1
1B05
129
Section BIP-8 (B1)
The section BIP-8 byte is located in the first STS-1 of the STS-48 or STS-192 only, and carries the even parity of
the scrambled data in the previous STS-192 frame. In every frame, the calculated BIP-8 for the previous frame is
inserted in the B1 byte of the current frame prior to scrambling. The B1 value can be fully corrupted (by inverting all
bits) on a per-channel basis, using the B1 corrupt enable control bit. The duration of the corruption is defined in
frames per second, up to a maximum of 8000 frames between rising edges of PM_CLK. The B1 corrupt frame
count register specifies this duration and is shared between the four channels.
Table 62. Transmit B1 Register Summary
Function
B1 Corrupt Enable
B1 Corrupt Duration Control
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Transmit Channel
1 Provisioning (R/W)
LTE Transmit—B1
Corrupt Frame Count
(R/W)
B1_CORRUPT_EN_1
4
1C00
130
LTE_TX_B1_NUM_CORRUPT_
FRAMES
1
1B01
128
Local Orderwire (E1)
The local orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz channel for voice communications between regenerators, hubs, and remote terminals. The byte is input MSB first, on
the TLCLOW_n pin, and is inserted in each frame. The data is clocked in on the positive edge of TOW_CLK_n.
The TOWCKn clock is divided down from the section data communications channel clock, TSDCKn (192 kHz/3),
giving a frequency of 64 kHz and a duty cycle of 33%.
In STS-48 mode, each of the four TLCLOW pins input the E1 byte for that channel. In STS-192 mode, only the
TLCLOW_1 pin inputs the E1 byte, while the other pins are unused.
Section User Channel (F1)
The section user channel byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz
channel for use by the network provider. The byte is input serially, MSB first, on the TSUSERn pin, and is inserted
each frame. The data is clocked in on the positive edge of TOW_CLK_n.
In STS-48 mode, each of the four TSUSER pins input the F1 byte for that channel. In STS-192 mode, only the
TSUSER_1 pin inputs the F1 byte, while the other pins are unused.
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Section Data Communications Channel (D1, D2, and D3)
The section data communications channel bytes are located in the first STS-1 of the STS-48 or STS-192 only, and
are used as one 192 kHz message-based channel for operations, administration, and maintenance communication. The bytes are input serially, MSB first, on the TSDCC_n pin, and are inserted in each frame. The data is
clocked in on the positive edge of TSD_CLK_n.
The TSD_CLK_n clock is divided down from the line data communications channel clock, TLD_CLK_n
(576 kHz/3), giving a frequency of 192 kHz and a duty cycle of 33%.
In STS-48 mode, each of the four TSDCC pins input the section data communication channel bytes for that channel. In STS-192 mode, only the TSDCC_1 pin inputs these bytes, while the other pins are unused.
STS Payload Pointer (H1 and H2)
The STS payload pointer bytes are normally set to the values received at the transmit payload add interface. These
values are overwritten under the following conditions (in order of precedence from highest to lowest):
■
■
■
■
■
Line AIS: enabled using the AIS-L insert control bit.
Unequipped signal insertion: enabled on a per STS-1 channel basis using the UNEQ-P insert enable registers;
overwrites the pointer bytes (H1, H2) for that channel with 0x60 0x00 or 0x68 0x00, based on SS_MODE (see the
SS Bits section below) and the SPE bytes with all zeros.
Software AIS insertion: enabled on a per STS-1 channel basis using the path AIS insert enable registers;
overwrites the pointer bytes for that channel with 0xFF 0xFF (H1 H2) and the SPE bytes with all ones.
TFRM loss of frame sync: overwrites the pointer bytes in all STS-1 channels with 0xFF 0xFF (H1 H2) and all SPE
bytes with all ones (AIS-P).
TOHDAT insertion: enabled on a per STS-48 channel basis using the TOH data insert control bit; overwrites the
pointer bytes with the data serially received on the TOHDAT_n_[1:0] pins if the TOHEN_n pin is high for H1 and
H2.
The pointer bytes are also automatically overwritten with all ones in the transmit payload add interface under the
following conditions:
■
In all STS channels of an STS-12 due to an OOF on that STS-12 data input.
■
For the affected STS channel due to a path AIS insert request received for that STS in the STS-12 overhead.
SS Bits. The SS bits in the STS payload pointer (H1 and H2) are provisioned using SS_MODE (bit 9) and
TX_SS_OVERWRITE_EN (bit 10) in each LTE Tx channel provisioning register. The SS bit mode is set to 0 for
SONET (00) or 1 for SDH (10) and defines the value of the SS bits for unequipped signal insertion. The SS bits
mode also defines the value of the SS bits that are inserted in all of the outgoing H1 bytes for that OC-48 channel if
the Tx SS bit overwrite feature is enabled. The SS bits are passed through untouched if the transmit SS bit overwrite feature is not enabled. The overwrite feature is disabled during AIS (line and path) insertion when TOHDAT
insertion is enabled for that H1 byte or when the incoming H1 byte is 0xFF.
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
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Functional Description (continued)
Table 63. Transmit STS Payload Pointer Register Summary
Function
AIS-L Insert Control
UNEQ-P Insert Control
Software AIS-P Insert
Control
TOH Data Insert Control
Transmit SS Bit Overwrite
Enable Control
SS Bit Mode for
Unequipped Signal
Insertion Control
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Transmit Channel 1
Maintenance (R/W)
LTE Transmit Channel 1
Path Unequipped
(UNEQ-P) Insert Enable
#1 (R/W)
LTE Transmit Channel 1
Path AIS (AIS-P) Insert
Enable #1 (R/W)
LTE Transmit Channel 1
Provisioning (R/W)
LTE Transmit Channel 1
Provisioning (R/W)
LTE Transmit Channel 1
Provisioning (R/W)
TX_LINE_AIS_INSERT_1
4
1C01
131
LTE_TX_1_UNEQ_P_EN_1
16
1C02
131
LTE_TX_1_PATH_AIS_EN_1
16
1C06
132
TX_TOH_DATA_INSERT_1
4
1C00
130
TX_SS_OVERWRITE_EN
4
1C00
130
SS_MODE
4
1C00
130
Line BIP-8 (B2)
The line BIP-8 is located in each STS-1 of the STS-48 or STS-192, and carries the even parity for the line overhead and SPE data in the previous STS-1 frame. Since the B2 byte is calculated for each STS-1, independent of
the other STS-1s, the device mode (STS-48 or STS-192) does not affect the operation of this block. The B2 values
in all STS-1s in an STS-48 channel can be fully corrupted (by inverting all bits) on a per-STS-48 basis using the B2
corrupt enable control bit. The duration of the corruption is defined in frames per second, up to a maximum of
8000 frames between rising edges of PM_CLK. The B2 corrupt frame count register specifies this duration and is
shared between the four channels.
Table 64. Transmit B2 Register Summary
Function
B2 Corrupt Enable
B2 Corrupt Duration
Control
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Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Transmit Channel 1
Provisioning (R/W)
LTE Transmit—B2 Corrupt Frame Count (R/W)
B2_CORRUPT_EN_1
4
1C00
130
LTE_TX_B2_NUM_CORRUPT
_FRAMES
1
1B02
128
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
APS Channel (K1 and K2)
The APS channel bytes are located in the first STS-1 of the STS-48 or STS-192 only, and are used for automatic
protection switching (APS) signaling to coordinate line level protection switching. In addition, the K2 byte is also
used to carry line AIS and line RDI signals. Both bytes are inserted during each frame, normally using either values
stored in the K byte register, or using the raw or validated values received at the transmit payload add interface.
The K byte select bits in the LTE transmit channel n maintenance register determine which source to use. This is
outlined in Table 65.
In addition, the value of bits 6—8 in K2 can optionally be automatically overwritten by 110 (RDI-L) when AIS-L,
LOS, SEF, or LOF (SEF and LOF only if AIS insertion is enabled) are detected for the receive STS-48 or STS-192.
This insertion is controlled by the RDI-L select bit in the LTE transmit channel n maintenance register. When RDI-L
is triggered, it will be inserted for a minimum of 20 consecutive frames, regardless of the length of the receive
defect.
Table 65. K Byte Select Control Bits
K Byte Select Value
(Binary)
00
01
10
11
Source for K1K2 Insertion
LTE transmit channel 1 K1K2 byte insert values register.
Raw K1K2 byte from the transmit payload add interface.
Validated K1K2 byte from the transmit payload add interface.
Invalid. Do not program this value.
Table 66. Transmit APS Channel (K1K2) Register Summary
Function
K1K2 Source Control
K1K2 Software Insert Value
RDI-L Insert Control
Register Name
(First Occurrence)
Register Bits
Qty.
1st Page
Addr
(hex)
LTE Transmit Channel 1
Maintenance (R/W)
LTE Transmit Channel 1
K1K2 Byte Insert Values
(R/W)
LTE Transmit Channel 1
Maintenance (R/W)
TX_K_BYTES_SELECT_1
4
1C01
131
TX_K1_SW_BYTE_1
TX_K2_SW_BYTE_1
4
1C0A
132
RDI_L_SELECT_1
4
1C01
131
Line Data Communication Channel (D4—D12)
The line data communications channel bytes are located in the first STS-1 of the STS-48 or STS-192 only, and are
used as one 576 kHz message-based channel for operations, administration, and maintenance communication
(OA&M). The bytes are input serially, MSB first, on the TLDCCn pin, and are inserted in each frame. The data is
clocked in on the positive edge of TLDCKn.
The TLDCKn clock is divided down from the internal data clock (77.76 MHz/135), giving a frequency of 576 kHz
and a duty cycle of roughly 50%.
In STS-48 mode, each of the four TLDCC pins input the line data communication channel bytes for that channel. In
STS-192 mode, only the TLDCC1 pin is used to input these bytes, while the other pins are not used.
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TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
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Functional Description (continued)
Synchronization Status (S1)
The synchronization status byte is located in the first STS-1 of the STS-48 or STS-192 only, and is used to convey
the synchronization status of a network element. The byte is inserted in each frame using either a value provisioned in the S1 byte control register, or from a value received on the TFRM signal. The S1 byte insert control bit
determines which of these two sources to use.
The data on TFRM is clocked in on the positive edge of T_CLK, MSB first, as a repeating 77.76 MHz Manchester
encoded 16-bit code that is interrupted once per frame by the frame sync pattern 00001111 (at 77.76 MHz). If the
frame sync pattern is not received at least every eight frames (i.e., 1 kHz), a TFRM sync loss is indicated in the
TFRM LOF alarm bit and the value 0x0F is used for S1 if insertion is enabled. During TFRM sync loss, AIS-P is
inserted as described in the STS Payload Pointer (H1 and H2) section on page 88. The 8-bit (16 bits of Manchester) value received is then validated three times before being optionally inserted into the transport overhead as the
S1 byte. This validated value is reflected in the TFRM S1 byte status register and if a value is not validated over
the course of the frame, the TFRM S1 byte invalid alarm bit is set. This alarm bit, along with the TFRM LOF alarm
bit, is found in the LTE transmit interrupt alarm register.
Table 67. Transmit Synchronization Status (S1) Register Summary
Function
S1 Source Control
Provisioned S1 Byte
TFRM S1 Validated
Value
TFRM S1 Byte Invalid
Latched Alarm
Register Name
(First Occurrence)
Register Bits
LTE Transmit Channel 1 S1_BYTE_TX_FRM_INSERT_1
Maintenance (R/W)
LTE Transmit Channel 1
LTE_TX_1_S1_DATA_1
S1 Byte Insert Value
(R/W)
LTE Transmit—TFRM S1 LTE_TX_S1_BYTE_TX_FRM
Byte (RO)
LTE Transmit—Interrupt
TX_FRM_S1_BYTE_INVALID
Alarm Register (W1C)
Qty.
1st
Addr
(hex)
Page
4
1C01
131
4
1C0B
132
1
1B04
129
1
1B05
129
STS-192 Line Remote Error Indication (M1)
The line remote error indication (REI-L) byte is located in the third STS-1 of the STS-48 or STS-192 only (in order
of appearance in the STS-192 signal), and is used to convey to the far end the number of errors detected in the
receive direction using the line BIP-8 bytes. The byte is inserted each frame with a binary value indicating the number of line BIP-8 errors (truncated at 255) detected in the previous receive frame for the entire STS-48 or STS-192.
The value of the byte can be fully corrupted (by setting all bits) on a per-channel basis using the M1 corrupt enable
control bit. The duration of the corruption is defined in frames per second, up to a maximum of 8000 frames
between rising edges of PM_CLK. The M1 corrupt frame count register specifies this duration and is shared
between the four channels.
Table 68. Transmit M1 Register Summary
Function
M1 Corrupt Enable
M1 Corrupt Duration
Control
Agere Systems Inc.
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Transmit Channel 1
Provisioning (R/W)
LTE Transmit—M1 Corrupt Frame Count (R/W)
M1_CORRUPT_EN_1
4
1C00
130
LTE_TX_M1_NUM_CORRUPT_
FRAMES
1
1B03
129
91
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Functional Description (continued)
Express Orderwire (E2)
The express orderwire byte is located in the first STS-1 of the STS-48 or STS-192 only, and provides a 64 kHz
channel for voice communications between line entities. The byte is input serially, MSB first, on the TEXPOW_n pin
and is inserted in each frame. The data is clocked in on the positive edge of TOW_CLK_n.
In STS-48 mode, each of the four TEXPOW pins input the E2 byte for that channel. In STS-192 mode, only the
TEXPOW_1 pin captures the E2 byte, while the other pins are unused.
Transmit STS-192 Line Interface
This block is hardware configured to accept four STS-48 streams and convert them to either a single 16-bit wide
serial STS-192 stream at 622.08 MHz or four 4-bit wide serial STS-48 streams at 622.08 MHz. The conversion process is essentially the same for both output formats, except that for STS-192 mode, the four STS-48 channels
must be passed through a time-slot multiplex (TSM) block first to multiplex them into a STS-192 data stream. The
resulting STS-192, or each of the STS-48 streams, is then optionally scrambled, has section BIP-8 calculated for it,
and is multiplexed up to a 622 MHz signal.
Time-Slot Multiplexer (TSM)
In STS-192 mode, the bytes in the four STS-48 channels need to be combined and reordered to create an
STS-192 data stream. This is performed by the time-slot multiplexer (TSM).
Table 20 on page 51 shows the input ordering to the TSM and Table 19 on page 51 shows the output ordering of
the TSM.
Scrambler
The data stream is normally scrambled using the standard generator polynomial 1 + x6 + x7. The scrambling can
be disabled by the corresponding transmit scrambler disable bit of the LTE transmit channel n provisioning register.
Table 69. Transmit Line Scrambler Register Summary
Function
Scrambler Disable Control
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
LTE Transmit Channel 1
Provisioning (R/W)
SCRM_DIS_1
4
1C00
130
Data Path Parity
The transmit line interface terminates the internal data path, including one bit of parity that is added for every byte
of STS-48/STS-192 data through the device. This parity bit is compared to the calculated parity of the data path
and parity errors are reported using the corresponding bit in the LTE transmit channel n interrupt alarm register.
Table 70. Transmit Data Path Parity Register Summary
Function
Register Name
(First Occurrence)
Register Bits
Qty.
1st
Addr
(hex)
Page
Data Path Parity Error Latched
Alarm
LTE Transmit Channel 1
Interrupt Alarm (W1C)
TX_DATA_PAR_ERR_1
4
1C0C
133
92
Agere Systems Inc.
Data Sheet
May 2003
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Microprocessor Interface
Architecture
The TSOT0410G4 microprocessor interface architecture is configured for glueless interface to two specific microprocessors, the Motorola ® MPC860 and MC68360; however, other processors may also be utilized. Bus transfers
using the MC68360 are asynchronous, while the MPC860 transfers are synchronous to the processor clock.
There is a difference in definition of MSB and LSB of data, address, and parity pins between the TSOT0410G4 and
some microprocessors, such as the Motorola MPC860. For example, the TSOT0410G4 provides Parity_1 and
Parity_0. Parity_1 is the odd parity for the data bus MSB, and parity_0 is the odd parity for the data bus LSB. The
MPC860 DP0 calculates across the data bus MSB, and DP1 across the data bus LSB.
The microprocessor interface operates at the frequency of the microprocessor clock (PCLK) input in synchronous
mode. The state of the MPMODE input signal determines whether bus transfers are synchronous or asynchronous
with respect to PCLK.
The TSOT0410G4 has separate 16-bit wide address and data buses. The microprocessor interface generates an
external processor bus error if an internal data acknowledgement is not received in a predetermined period of time
or on parity errors.
Persistency alarm registers are used in conjunction with interrupt alarm registers to indicate whether alarms are
persistent.
Transfer Error Acknowledge (TEA_N)
The TSOT0410G4 contains a bus time-out counter. When this counter saturates, a bus error is generated to the
external processor through the transfer error acknowledge (TEA_N) signal. This feature must be considered with
respect to the external processor’s ability to generate its own internal bus time-out. TEA_N will be asserted if an
internal data acknowledgement is not received within 32 PCLK periods of the start of the access. This interval is
used since all valid internal accesses to the device will be completed in significantly less than 32 PCLK periods.
TEA_N is also asserted if the calculated parity value does not match the parity generated by the external microprocessor on a data transfer.
Interrupt Structure
The interrupt structure of the TSOT0410G4 is designed to minimize the effort for software/firmware to isolate the
interrupt source. The interrupt structure is comprised of different registers depending on the consolidation level. At
the lowest level (source level) there are two registers. The first is an alarm register (AR). An alarm register is typically of the write 1 clear (W1C) type. The second is an interrupt mask (IM) register of the read/write (RW) type.
An alarm register latches a raw status alarm. This latched alarm may contribute to an interrupt if its corresponding
interrupt mask bit is disabled. Individual latched alarms are consolidated into an interrupt status register (ISR). If
any of the latched alarms that are consolidated into a bit of an ISR are set and unmasked, the ISR bit is set. The
ISR bit may contribute to an interrupt if its corresponding interrupt mask bit is disabled. ISRs may be consolidated
into higher-level ISR in a similar fashion until all alarms are consolidated into the chip-level ISR. The alarm register
that causes an interrupt can be determined by traversing the tree of ISRs, starting at the chip-level ISR, until the
source alarm is found.
The interrupt requests can be selectively disabled on a per-function (per-bit) basis. The interrupt mask register
serves this function. A bit position set to 1 indicates that the status flag in the corresponding bit position will not
contribute to the generation of an interrupt when it is set (status itself is not affected by the interrupt mask). All
interrupts are disabled on RST_N assertion.
Agere Systems Inc.
93
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Parity Bits
There are two parity bits associated with the microprocessor interface. They are only active when the microprocessor interface is in synchronous mode (MPMODE = 1). PARITY_1 is the odd parity bit for the most significant 8 bits
of the data bus (DATA_15 through DATA_8), and PARITY_0 is the odd parity bit for the least significant 8 bits of the
data bus (DATA_7 through DATA_0).
The parity bits may be ignored when the interface is operating in synchronous mode (MPMODE = 1); however,
TEA_N must then be ignored on a write cycle. A TEA_N will never be asserted on a synchronous read cycle since
the interface is presenting the parity on the output pins for the microprocessor interface to check. The parity bit pins
may be left unconnected if not used.
The parity bits are not used by the microprocessor interface when in asynchronous mode (MPMODE = 0), and can
be unconnected.
Clock Domains
There are seven primary clock domains in the TSOT0410G4. Each has a separate clock source, related to the
function of the domain. The microprocessor interface is a distinct clock domain and PCLK is its input clock. It contains the device-level registers. The clock domains are shown in Figure 9 on page 95.
In the event that any domain loses its primary clock source, the microprocessor interface will not be able to access
registers related to those regions until the clock is restored. The domain's clock is necessary internally to transfer
data between that region of the device and the microprocessor interface.
The receive line interface contains four clock domains, each clocked by R_CLK_[1—4], although they are all
clocked by R_CLK_1 in STS-192 mode. The receive payload drop interface is a separate clock domain and is
clocked by D_CLK. The separation between the receive domains is the receive drop aligner block. The transmit
side of the device is an entire clock domain, with T_CLK as its input clock.
The TSOT0410G device monitors RX_CLK_n, TX_CLK, and DRP_CLK to effectively detect loss of R_CLK_n,
T_CLK, and D_CLK. Each clock is monitored by the same logic. P_CLK is divided by eight to produce a test signal
that is less than 1/8th the clocks being monitored. This test signal is sampled using each of the monitored clocks,
and then the sample is XORed with the test signal to generate a difference signal. This difference signal is then
sampled by P_CLK at the end of each half cycle of the test clock. If the monitored clock is still active, the difference
signal should be low by the end of the half cycle and the fail flag will stay low. If the monitored clock fails, the difference signal will be high during one of the half cycles of test signal, causing the fail alarm to strobe high. The status
of RX_CLK_n, TX_CLK, and DRP_CLK are monitored using the clock loss alarm/PM clock detection register,
address 0x7 (see Table 79 on page 113).
94
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
MPMODE
PM_CLK
INT_N
TEA_N
TA_N
RW_N
DS_N
TS_N
CS_N
ADDRESS_[15:0]
DATA_[15:0]
PARITY_[1:0]
PCLK
TOH_CLK_[1—4]
TOW_CLK_[1—4]
TSD_CLK_[1—4]
TLD_CLK_[1—4]
TOHEN_[1—4]
TOHFP_[1—4]
TLDCC_[1—4]
TOHDAT_[1—4]_[1:0]
TSUSER_[1—4]
TSDCC_[1—4]
TLCLOW_[1—4]
TEXPOW_[1—4]
Microprocessor Interface (continued)
TFRM
T_CLK
RST_N
MICROPROCESSOR INTERFACE
HIZ_N
TD_1_[3:0]
TD_2_[3:0]
TD_3_[3:0]
TD_4_[3:0]
X4
TRANSMIT
STS-48 TRANSMIT
STS-192 TRANSPORT
OVERHEAD
LINE
PROCESSOR
INTERFACE
X4
TADCC_[16:1]
TRANSMIT
PAYLOAD
ADD
INTERFACE
TADCK
ADATA_[16:1]
T_CLKO_[1—4]
X4
X4
RECEIVE
STS-48 RECEIVE
STS-192 TRANSPORT
OVERHEAD
LINE
PROCESSOR
INTERFACE
RECEIVE PATH
OVERHEAD
PROCESSOR
DCTL_[1—4]
RDDCK_[1—4]
JTAG INTERFACE
DRPBYP
ROH_CLK_[1—4]
ROW_CLK_[1—4]
RSD_CLK_[1—4]
RLD_CLK_[1—4]
ROHFP_[1—4]
ROHDAT_[1—4]_[1:0]
RLDCC_[1—4]
RSDCC_[1—4]
RSUSER_[1—4]
RLCLOW_[1—4]
DDATA_[16:1]
RDDCC_[16:1]
RECEIVE
POINTER
PROCESSOR
REXPOW_[1—4]
x4 IN STS-48 MODE
D_CLK
RECEIVE
PAYLOAD
DROP
INTERFACE
RECEIVE
DROP
ALIGNER
R_CLKO_[1—4]
x1 IN STS-192 MODE
DFRM
X4
TRST_N
PATH
TRACE
BUFFER
TMS
RD_1_[3:0]
RD_2_[3:0]
RD_3_[3:0]
RD_4_[3:0]
RFRM[1—4]
X4
STS PATH
PROCESSING
BLOCK
TCK
TRACE
BUFFER
TDI
SECTION
TDO
STS_MODE
R_CLK_[1—4]
5-7982(F).b
Note: See text for description of the timing domains.
Figure 9. TSOT0410G4 Timing Domains
Agere Systems Inc.
95
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Persistency Registers
An alarm is persistent if it has been asserted continuously (i.e., the alarm has not been negated from the time it
was asserted to the time it was read by software). An alarm is not persistent if it is negated one or more times from
the point at which it was asserted to the point at which it was read by software.
The persistency register monitors the state of an alarm point, and indicates to software whether the alarm is persistent. The following timing diagram indicates the operation of the persistency register relative to the raw status
alarm, and its corresponding interrupt alarm register. It also describes the software interaction with respect to its
attempt to clear the alarm, and its interpretation.
At the rising edge of the raw alarm point, the corresponding interrupt alarm and persistency alarm register are set.
The falling edge of the raw alarm causes the persistency alarm register to be reset (cleared). Any subsequent
assertion of the raw alarm does not cause the persistency alarm register to be asserted. It remains reset until the
interrupt alarm register is cleared (after the raw alarm is negated, and the interrupt alarm register is cleared). Once
the interrupt alarm register is cleared, its corresponding persistency alarm register reset is released. The persistency register is now able to be set on the next assertion of the raw alarm point.
RAW ALARM
INTERRUPT ALARM REGISTER
PERSISTENCY REGISTER
5-8408(F)
Figure 10. Persistency Register Operation
Register Description
A summary of the available register addresses is provided in Table 71, beginning on page 97. Where two reset values exist, the first refers to STS-48 mode and the second refers to STS-192 mode.
Software Reset
The software reset (writing 0xEAEA to register 0xFF) resets most registers of the TSOT, with the exception of the
device level registers: addresses 0x0 through 0x8. This is by design, since there is a design constraint in resetting
the register that causes the reset. If necessary after a software reset, reconfigure 0x0 through 0x8. These registers
do return to default values after a hardware reset.
Note: The PLLs are not reset by a software reset. Although unlikely, should the need to reset the PLLs arise, a
hardware reset should be asserted (RST_N).
96
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary
Address
(Hex)
0
1
2
3
4
5
6
7
8
9—FE
FF
100—FFF
1000
1001
1100
1101
1102
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
111A
111B
111C
111D
111E
111F
1120
1121
1122
1123
1124
1125
1126
1127
Name
Chip Level Interrupt Status Register
Chip Level Interrupt Status Mask Register
Chip ID Register
Chip Vintage Register
Scratch Pad Register
Chip Level Maintenance Register
Chip Status Register
Clock Loss Alarm Register
Clock Loss Alarm Mask Register
Not Used
Software Chip Reset Register
Not Used
LTE Interrupt Status Register
LTE Interrupt Status Mask Register
Section Trace (J0) Access Maintenance Register
J0 Access Done Register
J0 Access Message Start
J0 Access Message Buffer, Word 1
J0 Access Message Buffer, Word 2
J0 Access Message Buffer, Word 3
J0 Access Message Buffer, Word 4
J0 Access Message Buffer, Word 5
J0 Access Message Buffer, Word 6
J0 Access Message Buffer, Word 7
J0 Access Message Buffer, Word 8
J0 Access Message Buffer, Word 9
J0 Access Message Buffer, Word 10
J0 Access Message Buffer, Word 11
J0 Access Message Buffer, Word 12
J0 Access Message Buffer, Word 13
J0 Access Message Buffer, Word 14
J0 Access Message Buffer, Word 15
J0 Access Message Buffer, Word 16
J0 Access Message Buffer, Word 17
J0 Access Message Buffer, Word 18
J0 Access Message Buffer, Word 19
J0 Access Message Buffer, Word 20
J0 Access Message Buffer, Word 21
J0 Access Message Buffer, Word 22
J0 Access Message Buffer, Word 23
J0 Access Message Buffer, Word 24
Agere Systems Inc.
Bits
Reset
7:0
7:0
15:0
15:0
15:0
0:0
2:0
6:0
6:0
—
15:0
—
13:0
13:0
4:0
0
0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
0x0
0x0
0x1515
0x1
0x0
0x0
—
0x0
0x0
—
0x0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
97
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
98
Name
Bits
Reset
1128
1129
112A
112B
112C
112D
112E
112F
1130—
12FF
1300
1301
1302
1303
1304
1305
J0 Access Message Buffer, Word 25
J0 Access Message Buffer, Word 26
J0 Access Message Buffer, Word 27
J0 Access Message Buffer, Word 28
J0 Access Message Buffer, Word 29
J0 Access Message Buffer, Word 30
J0 Access Message Buffer, Word 31
J0 Access Message Buffer, Word 32
Not Used
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–3)
Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–4)
Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–5)
Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–6)
Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–7)
Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–8)
15:0
15:0
15:0
15:0
15:0
15:0
1306
Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–9)
15:0
1307
Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 × 10–10)
15:0
0x8/0x8
0x8/0x8
0x8/0x8
0x3E/0xD
0x271/0x82
0x1450/
0x514
0x8015/
0x2904
0x80AA/
0x8029
—
1308—
1309
1310
Not Used
—
Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–3)
15:0
1311
Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–4)
15:0
1312
1313
1314
1315
1316
1317—
1319
1320
Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–5)
Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–6)
Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–7)
Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–8)
Line Signal Degrade/Signal Fail Detect Error Limit (1 × 10–9)
Not Used
15:0
15:0
15:0
15:0
15:0
—
Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–4)
15:0
1321
1322
1323
1324
1325
1326
Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–5)
Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–6)
Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–7)
Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–8)
Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–9)
Line Signal Degrade/Signal Fail Clear Error Limit (1 × 10–10)
15:0
15:0
15:0
15:0
15:0
15:0
0x12D2/
0x4BFD
0x35E/
0xDD7
0x51/0x166
0x3E/0x33
0x3E/0x33
0x33/0x33
0x28/0x28
—
0x3BD/
0xE96
0x72/0x1A7
0x5B/0x4D
0x5B/0x4D
0x4D/0x4D
0x3F/0x3F
0x34/0x33
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
1327—
13FF
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
140A
140B
140C
140D
140E
140F
1410
1411—
14FF
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
150A
150B
150C
150D
150E
150F
1510
1511—
15FF
1600
Name
Bits
Reset
—
—
LTE Receive Channel 1 Provisioning Register
LTE Receive Channel 1 Maintenance Register
LTE Receive Channel 1 Loss of Signal (LOS) Threshold
LTE Receive Channel 1 K Byte Status Register
LTE Receive Channel 1 S1 Byte Status Register
LTE Receive Channel 1 Service-Affecting Interrupt Alarm Register
LTE Receive Channel 1 Service-Affecting Interrupt Alarm Mask Register
LTE Receive Channel 1 Service-Affecting Persistency Alarm Register
LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm Register
LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm Mask Register
LTE Receive Channel 1 NSA Persistency Alarm Register
LTE Receive Channel 1 Performance Monitoring Register
LTE Receive Channel 1 REI-L Performance Monitoring Register (L)
LTE Receive Channel 1 REI-L Performance Monitoring Register (U)
LTE Receive Channel 1 CV-L Performance Monitoring Register (L)
LTE Receive Channel 1 CV-L Performance Monitoring Register (U)
LTE Receive Channel 1 CV-S Performance Monitoring Register
Not Used
6:0
6:0
9:0
15:0
7:0
4:0
4:0
2:0
10:0
10:0
5:0
4:0
15:0
4:0
15:0
7:0
15:0
—
0x2
0x20
0x86
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
LTE Receive Channel 2 Provisioning Register
LTE Receive Channel 2 Maintenance Register
LTE Receive Channel 2 Loss of Signal (LOS) Threshold
LTE Receive Channel 2 K Byte Status Register
LTE Receive Channel 2 S1 Byte Status Register
LTE Receive Channel 2 Service-Affecting Interrupt Alarm Register
LTE Receive Channel 2 Service-Affecting Interrupt Alarm Mask Register
LTE Receive Channel 2 Service-Affecting Persistency Alarm Register
LTE Receive Channel 2 Nonservice-Affecting Interrupt Alarm Register
LTE Receive Channel 2 Nonservice-Affecting Interrupt Alarm Mask Register
LTE Receive Channel 2 NSA Persistency Alarm Register
LTE Receive Channel 2 Performance Monitoring Register
LTE Receive Channel 2 REI-L Performance Monitoring Register (L)
LTE Receive Channel 2 REI-L Performance Monitoring Register (U)
LTE Receive Channel 2 CV-L Performance Monitoring Register (L)
LTE Receive Channel 2 CV-L Performance Monitoring Register (U)
LTE Receive Channel 2 CV-S Performance Monitoring Register
Not Used
6:0
6:0
9:0
15:0
7:0
4:0
4:0
2:0
10:0
10:0
5:0
4:0
15:0
4:0
15:0
7:0
15:0
—
0x2
0x20
0x86
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
LTE Receive Channel 3 Provisioning Register
6:0
0x2
Not Used
Agere Systems Inc.
99
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
1601
1602
1603
1604
1605
1606
1607
1608
1609
160A
160B
160C
160D
160E
160F
1610
1611—
16FF
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
170A
170B
170C
170D
170E
170F
1710
1711—
1AFF
1B00
1B01
1B02
1B03
100
Name
Bits
Reset
LTE Receive Channel 3 Maintenance Register
LTE Receive Channel 3 Loss of Signal (LOS) Threshold
LTE Receive Channel 3 K Byte Status Register
LTE Receive Channel 3 S1 Byte Status Register
LTE Receive Channel 3 Service-Affecting Interrupt Alarm Register
LTE Receive Channel 3 Service-Affecting Interrupt Alarm Mask Register
LTE Receive Channel 3 Service-Affecting Persistency Alarm Register
LTE Receive Channel 3 Nonservice-Affecting Interrupt Alarm Register
LTE Receive Channel 3 Nonservice-Affecting Interrupt Alarm Mask Register
LTE Receive Channel 3 NSA Persistency Alarm Register
LTE Receive Channel 3 Performance Monitoring Register
LTE Receive Channel 3 REI-L Performance Monitoring Register (L)
LTE Receive Channel 3 REI-L Performance Monitoring Register (U)
LTE Receive Channel 3 CV-L Performance Monitoring Register (L)
LTE Receive Channel 3 CV-L Performance Monitoring Register (U)
LTE Receive Channel 3 CV-S Performance Monitoring Register
Not Used
6:0
9:0
15:0
7:0
4:0
4:0
2:0
10:0
10:0
5:0
4:0
15:0
4:0
15:0
7:0
15:0
—
0x20
0x86
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
LTE Receive Channel 4 Provisioning Register
LTE Receive Channel 4 Maintenance Register
LTE Receive Channel 4 Loss of Signal (LOS) Threshold
LTE Receive Channel 4 K Byte Status Register
LTE Receive Channel 4 S1 Byte Status Register
LTE Receive Channel 4 Service-Affecting Interrupt Alarm Register
LTE Receive Channel 4 Service-Affecting Interrupt Alarm Mask Register
LTE Receive Channel 4 Service-Affecting Persistency Alarm Register
LTE Receive Channel 4 Nonservice-Affecting Interrupt Alarm Register
LTE Receive Channel 4 Nonservice-Affecting Interrupt Alarm Mask Register
LTE Receive Channel 4 NSA Persistency Alarm Register
LTE Receive Channel 4 Performance Monitoring Register
LTE Receive Channel 4 REI-L Performance Monitoring Register (L)
LTE Receive Channel 4 REI-L Performance Monitoring Register (U)
LTE Receive Channel 4 CV-L Performance Monitoring Register (L)
LTE Receive Channel 4 CV-L Performance Monitoring Register (U)
LTE Receive Channel 4 CV-S Performance Monitoring Register
Not Used
6:0
6:0
9:0
15:0
7:0
4:0
4:0
2:0
10:0
10:0
5:0
4:0
15:0
4:0
15:0
7:0
15:0
—
0x2
0x20
0x86
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
LTE Transmit—Frame Pulse Offset Count
LTE Transmit—B1 Corrupt Frame Count
LTE Transmit—B2 Corrupt Frame Count
LTE Transmit—M1 Corrupt Frame Count
13:0
12:0
12:0
12:0
0x0
0x0
0x0
0x0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
1B04
1B05
1B06
1B07—
1BFF
1C00
1C01
1C02
1C03
1C04
1C05
1C06
1C07
1C08
1C09
1C0A
1C0B
1C0C
1C0D
1C0E—
1CFF
1D00
1D01
1D02
1D03
1D04
1D05
1D06
1D07
1D08
1D09
1D0A
1D0B
1D0C
1D0D
1D0E—
1DFF
1E00
1E01
1E02
1E03
Name
Bits
Reset
LTE Transmit—TFRM S1 Byte
LTE Transmit—Interrupt Alarm Register
LTE Transmit—Interrupt Alarm Mask Register
Not Used
7:0
2:0
2:0
—
0x0
0x0
0x0
—
LTE Transmit Channel 1 Provisioning Register
LTE Transmit Channel 1 Maintenance Register
LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #1
LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #2
LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #3
LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #4
LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #1
LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #2
LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #3
LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #4
LTE Transmit Channel 1 K1K2 Byte Insert Values
LTE Transmit Channel 1 S1 Byte Insert Value
LTE Transmit Channel 1 Interrupt Alarm Register
LTE Transmit Channel 1 Interrupt Alarm Mask Register
Not Used
5:0
5:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
15:0
7:0
1:0
1:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
LTE Transmit Channel 2 Provisioning Register
LTE Transmit Channel 2 Maintenance Register
LTE Transmit Channel 2 Path Unequipped (UNEQ-P) Insert Enable #1
LTE Transmit Channel 2 Path Unequipped (UNEQ-P) Insert Enable #2
LTE Transmit Channel 2 Path Unequipped (UNEQ-P) Insert Enable #3
LTE Transmit Channel 2 Path Unequipped (UNEQ-P) Insert Enable #4
LTE Transmit Channel 2 Path AIS (AIS-P) Insert Enable #1
LTE Transmit Channel 2 Path AIS (AIS-P) Insert Enable #2
LTE Transmit Channel 2 Path AIS (AIS-P) Insert Enable #3
LTE Transmit Channel 2 Path AIS (AIS-P) Insert Enable #4
LTE Transmit Channel 2 K1K2 Byte Insert Values
LTE Transmit Channel 2 S1 Byte Insert Value
LTE Transmit Channel 2 Interrupt Alarm Register
LTE Transmit Channel 2 Interrupt Alarm Mask Register
Not Used
5:0
5:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
15:0
7:0
1:0
1:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
LTE Transmit Channel 3 Provisioning Register
LTE Transmit Channel 3 Maintenance Register
LTE Transmit Channel 3 Path Unequipped (UNEQ-P) Insert Enable #1
LTE Transmit Channel 3 Path Unequipped (UNEQ-P) Insert Enable #2
5:0
5:0
11:0
11:0
0x0
0x0
0x0
0x0
Agere Systems Inc.
101
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
1E04
1E05
1E06
1E07
1E08
1E09
1E0A
1E0B
1E0C
1E0D
1E0E—
1EFF
1F00
1F01
1F02
1F03
1F04
1F05
1F06
1F07
1F08
1F09
1F0A
1F0B
1F0C
1F0D
1F0E—
1FFF
2000
2001
2002
2003
2004—
23FF
2400
2401
2402
2403
2404
2405
2406
102
Name
Bits
Reset
LTE Transmit Channel 3 Path Unequipped (UNEQ-P) Insert Enable #3
LTE Transmit Channel 3 Path Unequipped (UNEQ-P) Insert Enable #4
LTE Transmit Channel 3 Path AIS (AIS-P) Insert Enable #1
LTE Transmit Channel 3 Path AIS (AIS-P) Insert Enable #2
LTE Transmit Channel 3 Path AIS (AIS-P) Insert Enable #3
LTE Transmit Channel 3 Path AIS (AIS-P) Insert Enable #4
LTE Transmit Channel 3 K1K2 Byte Insert Values
LTE Transmit Channel 3 S1 Byte Insert Value
LTE Transmit Channel 3 Interrupt Alarm Register
LTE Transmit Channel 3 Interrupt Alarm Mask Register
Not Used
11:0
11:0
11:0
11:0
11:0
11:0
15:0
7:0
1:0
1:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
LTE Transmit Channel 4 Provisioning Register
LTE Transmit Channel 4 Maintenance Register
LTE Transmit Channel 4 Path Unequipped (UNEQ-P) Insert Enable #1
LTE Transmit Channel 4 Path Unequipped (UNEQ-P) Insert Enable #2
LTE Transmit Channel 4 Path Unequipped (UNEQ-P) Insert Enable #3
LTE Transmit Channel 4 Path Unequipped (UNEQ-P) Insert Enable #4
LTE Transmit Channel 4 Path AIS (AIS-P) Insert Enable #1
LTE Transmit Channel 4 Path AIS (AIS-P) Insert Enable #2
LTE Transmit Channel 4 Path AIS (AIS-P) Insert Enable #3
LTE Transmit Channel 4 Path AIS (AIS-P) Insert Enable #4
LTE Transmit Channel 4 K1K2 Byte Insert Values
LTE Transmit Channel 4 S1 Byte Insert Value
LTE Transmit Channel 4 Interrupt Alarm Register
LTE Transmit Channel 4 Interrupt Alarm Mask Register
Not Used
5:0
5:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
15:0
7:0
1:0
1:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
EQPT Interrupt Status Register
EQPT Interrupt Mask Register
Receive Drop Common Service-Affecting Alarm Register
Receive Drop Common Service-Affecting Alarm Mask Register
Not Used
12:0
12:0
0
0
—
0x0
0x0
0x0
0x0
—
Receive Drop STS-48 Channel Provisioning Register 1
J0 Trace—STS-12 Channel 1
J0 Trace—STS-12 Channel 2
J0 Trace—STS-12 Channel 3
J0 Trace—STS-12 Channel 4
Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 1
Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 1
1:0
7:0
7:0
7:0
7:0
4:0
4:0
0x0
0x1
0x2
0x3
0x4
0x0
0x0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
2407—
24FF
2500
2501
2502
2503
2504
2505
2506
2507—
25FF
2600
2601
2602
2603
2604
2605
2606
2607—
26FF
2700
2701
2702
2703
2704
2705
2706
2707—
27FF
2C00
2C01
2C02
2C03
2C04
2C05
2C06
2C07
2C08
2C09
2C0A
Name
Bits
Reset
Not Used
—
—
Receive Drop STS-48 Channel Provisioning Register 2
J0 Trace—STS-12 Channel 5
J0 Trace—STS-12 Channel 6
J0 Trace—STS-12 Channel 7
J0 Trace—STS-12 Channel 8
Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 2
Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 2
Not Used
1:0
7:0
7:0
7:0
7:0
4:0
4:0
—
0x0
0x5
0x6
0x7
0x8
0x0
0x0
—
Receive Drop STS-48 Channel Provisioning Register 3
J0 Trace—STS-12 Channel 9
J0 Trace—STS-12 Channel 10
J0 Trace—STS-12 Channel 11
J0 Trace—STS-12 Channel 12
Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 3
Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 3
Not Used
1:0
7:0
7:0
7:0
7:0
4:0
4:0
—
0x0
0x9
0x10
0x11
0x12
0x0
0x0
—
Receive Drop STS-48 Channel Provisioning Register 4
J0 Trace—STS-12 Channel 13
J0 Trace—STS-12 Channel 14
J0 Trace—STS-12 Channel 15
J0 Trace—STS-12 Channel 16
Receive Drop STS-48 Channel Nonservice-Affecting Alarm Register 4
Receive Drop STS-48 Channel Nonservice-Affecting Alarm Mask Register 4
Not Used
1:0
7:0
7:0
7:0
7:0
4:0
4:0
—
0x0
0x13
0x14
0x15
0x16
0x0
0x0
—
Transmit Add STS-48 Channel Provisioning Register #1
J0 Status Register—1, STS-48 #1
J0 Status Register—2, STS-48 #1
J0 Status Register—3, STS-48 #1
J0 Status Register—4, STS-48 #1
AIS Insert Status Register, STS-12 Channel #1, STS-48 #1
AIS Insert Status Register, STS-12 Channel #2, STS-48 #1
AIS Insert Status Register, STS-12 Channel #3, STS-48 #1
AIS Insert Status Register, STS-12 Channel #4, STS-48 #1
Transmit Add STS-48 Channel Alarm Register #1
Transmit Add STS-48 Channel Alarm Mask Register #1
1:0
7:0
7:0
7:0
7:0
11:0
11:0
11:0
11:0
14:0
14:0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Agere Systems Inc.
103
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
2C0B—
2CFF
2D00
2D01
2D02
2D03
2D04
2D05
2D06
2D07
2D08
2D09
2D0A
2D0B—
2DFF
2E00
2E01
2E02
2E03
2E04
2E05
2E06
2E07
2E08
2E09
2E0A
2E0B—
2EFF
2F00
2F01
2F02
2F03
2F04
2F05
2F06
2F07
2F08
2F09
2F0A
2F0B—
2FFF
104
Name
Bits
Reset
—
—
Transmit Add STS-48 Channel Provisioning Register #2
J0 Status Register—1, STS-48 #2
J0 Status Register—2, STS-48 #2
J0 Status Register—3, STS-48 #2
J0 Status Register—4, STS-48 #2
AIS Insert Status Register, STS-12 Channel #1, STS-48 #2
AIS Insert Status Register, STS-12 Channel #2, STS-48 #2
AIS Insert Status Register, STS-12 Channel #3, STS-48 #2
AIS Insert Status Register, STS-12 Channel #4, STS-48 #2
Transmit Add STS-48 Channel Alarm Register #2
Transmit Add STS-48 Channel Alarm Mask Register #2
Not Used
1:0
7:0
7:0
7:0
7:0
11:0
11:0
11:0
11:0
14:0
14:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
Transmit Add STS-48 Channel Provisioning Register #3
J0 Status Register—1, STS-48 #3
J0 Status Register—2, STS-48 #3
J0 Status Register—3, STS-48 #3
J0 Status Register—4, STS-48 #3
AIS Insert Status Register, STS-12 Channel #1, STS-48 #3
AIS Insert Status Register, STS-12 Channel #2, STS-48 #3
AIS Insert Status Register, STS-12 Channel #3, STS-48 #3
AIS Insert Status Register, STS-12 Channel #4, STS-48 #3
Transmit Add STS-48 Channel Alarm Register #3
Transmit Add STS-48 Channel Alarm Mask Register #3
Not Used
1:0
7:0
7:0
7:0
7:0
11:0
11:0
11:0
11:0
14:0
14:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
Transmit Add STS-48 Channel Provisioning Register #4
J0 Status Register—1, STS-48 #4
J0 Status Register—2, STS-48 #4
J0 Status Register—3, STS-48 #4
J0 Status Register—4, STS-48 #4
AIS Insert Status Register, STS-12 Channel #1, STS-48 #4
AIS Insert Status Register, STS-12 Channel #2, STS-48 #4
AIS Insert Status Register, STS-12 Channel #3, STS-48 #4
AIS Insert Status Register, STS-12 Channel #4, STS-48 #4
Transmit Add STS-48 Channel Alarm Register #4
Transmit Add STS-48 Channel Alarm Mask Register #4
Not Used
1:0
7:0
7:0
7:0
7:0
11:0
11:0
11:0
11:0
14:0
14:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
Not Used
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
3000
3001
3002
3003
3004
3005
3006—
300F
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
...
3028
...
30C0
...
30C8
3100
...
31C8
...
3F00
...
3FC8
3FC9—
3FFF
4000
4001
4002
Name
Bits
Reset
STS-12 Pointer Processor Provisioning, STS-1 #1 to STS-1 #12
STS-12 Pointer Processor Maintenance, STS-1 #1 to STS-1 #12
STS-12 Pointer Interpreter PM, Last Second Increments, STS-1 #1 to
STS-1 #12
STS-12 Pointer Interpreter PM, Last Second Decrements, STS-1 #1 to
STS-1 #12
STS-12 Pointer Generator PM, Last Second Increments, STS-1 #1 to
STS-1 #12
STS-12 Pointer Generator PM, Last Second Decrements, STS-1 #1 to
STS-1 #12
Not Used
5:0
11:0
10:0
0x11
0x0
0x0
10:0
0x0
10:0
0x0
10:0
0x0
—
—
STS-1 #1 Path Overhead Provisioning
STS-1 #1 Path Overhead Maintenance
STS-1 #1 Path Overhead Status
STS-1 #1 Alarm Interrupt Status
STS-1 #1 Alarm Interrupt Status Mask
STS-1 #1 Alarm Persistency
STS-1 #1 PM Last Second Indicators
STS-1 #1 Last Second CV-P Count
STS-1 #1 Last Second REI-P Count
Not Used
STS-1 #2 Path Overhead Provisioning
...
STS-1 #2 Last Second REI-P Count
...
STS-1 #12 Path Overhead Provisioning
...
STS-1 #12 Last Second REI-P Count
STS-12 Pointer Processor Provisioning, STS-1 #13 to STS-1 #24
...
STS-1 #24 Last Second REI-P Count
...
STS-12 Pointer Processor Provisioning, STS-1 #181 to STS-1 #192
...
STS-1 #192 Last Second REI-P Count
Not Used
15:0
3:0
10:0
6:0
6:0
4:0
6:0
15:0
15:0
—
15:0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
0x0
15:0
0x0
15:0
0x0
15:0
5:0
0x0
0x11
15:0
0x0
5:0
0x11
15:0
—
0x0
—
15:0
15:0
15:0
0x0
0x0
0x40CF
Path Overhead (POH) Interrupt Status Register
Path Overhead (POH) Interrupt Status Mask Register
Path STS-1 Signal Fail Detect Threshold, Window Size Select 0
Agere Systems Inc.
105
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
4003
4004
4005
4006
4007
4008
4009
400A
400B
400C
400D
400E
400F
4010
4011
4012
4013
4014
4015
4016—
46FF
4100
4101
4102
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
411A
411B
411C
411D
411E
411F
4120
106
Name
Bits
Reset
Path STS-1 Signal Fail Clear Threshold, Window Size Select 0
Path STS-1 Signal Fail Detect Threshold, Window Size Select 1
Path STS-1 Signal Fail Clear Threshold, Window Size Select 1
Path STS-Nc Signal Fail Detect Threshold, Window Size Select 2
Path STS-Nc Signal Fail Clear Threshold, Window Size Select 2
Path STS-Nc Signal Fail Detect Threshold, Window Size Select 3
Path STS-Nc Signal Fail Clear Threshold, Window Size Select 3
Path STS-Nc Signal Fail Detect Threshold, Window Size Select 4
Path STS-Nc Signal Fail Clear Threshold, Window Size Select 4
Path STS-Nc Signal Fail Detect Threshold, Window Size Select 5
Path STS-Nc Signal Fail Clear Threshold, Window Size Select 5
Path STS-Nc Signal Fail Detect Threshold, Window Size Select 6
Path STS-Nc Signal Fail Clear Threshold, Window Size Select 6
Path STS-Nc Signal Fail Detect Threshold, Window Size Select 7
Path STS-Nc Signal Fail Clear Threshold, Window Size Select 7
Path Signal Fail Window Size
Path Signal Fail Window Size
Path Signal Fail Window Size
Path Signal Fail Window Size
Not Used
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
—
0x8113
0x80DE
0xC115
0x4233
0x830B
0x82B2
0xC31B
0x43A3
0x85D8
0x855E
0xC618
0x451D
0x8B08
0x8A62
0xCBFC
0xA
0x64
0x3E8
0x2710
—
Path Trace Access Control
Path Trace Access Complete Status
Path Trace Access Start
Path Trace Buffer Word #1
Path Trace Buffer Word #2
Path Trace Buffer Word #3
Path Trace Buffer Word #4
Path Trace Buffer Word #5
Path Trace Buffer Word #6
Path Trace Buffer Word #7
Path Trace Buffer Word #8
Path Trace Buffer Word #9
Path Trace Buffer Word #10
Path Trace Buffer Word #11
Path Trace Buffer Word #12
Path Trace Buffer Word #13
Path Trace Buffer Word #14
Path Trace Buffer Word #15
Path Trace Buffer Word #16
Path Trace Buffer Word #17
3:0
0
0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
4121
4122
4123
4124
4125
4126
4127
4128
4129
412A
412B
412C
412D
412E
412F
4130—
43FF
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
440A
440B
440C
440D
440E
440F
4410
4411
4412
4413
4414
4415—
44FF
Name
Bits
Reset
Path Trace Buffer Word #18
Path Trace Buffer Word #19
Path Trace Buffer Word #20
Path Trace Buffer Word #21
Path Trace Buffer Word #22
Path Trace Buffer Word #23
Path Trace Buffer Word #24
Path Trace Buffer Word #25
Path Trace Buffer Word #26
Path Trace Buffer Word #27
Path Trace Buffer Word #28
Path Trace Buffer Word #29
Path Trace Buffer Word #30
Path Trace Buffer Word #31
Path Trace Buffer Word #32
Not Used
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
STS-1 Channel Interrupt Status, STS-1 #1 to STS-1 #16 (STS-48 #1)
STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #1)
STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #1)
STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #1)
STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #1)
STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #1)
STS-48 #1 Channel Path Trace Control
S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #1)
S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #1)
S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #1)
S/W Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #1)
S/W Concatenation Mask STS-1 #1 to STS-1 #12 (STS-48 #1)
S/W Concatenation Mask STS-1 #13 to STS-1 #24 (STS-48 #1)
S/W Concatenation Mask STS-1 #25 to STS-1 #36 (STS-48 #1)
S/W Concatenation Mask STS-1 #37 to STS-1 #48 (STS-48 #1)
Received Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #1)
Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #1)
Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #1)
Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #1)
STS-48 Channel 1, Path Interrupt Status
STS-48 Channel 1, Path Interrupt Status Mask
Not Used
15:0
15:0
15:0
15:0
15:0
15:0
9:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x200
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
Agere Systems Inc.
107
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
Name
Bits
Reset
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
450A
450B
450C
450D
450E
450F
4510
4511
4512
4513
4514
4515—
45FF
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
460A
460B
460C
460D
460E
460F
4610
4611
STS-1 Channel Interrupt Status, STS-1 #49 to STS-1 #64 (STS-48 #2)
STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #2)
STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #2)
STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #2)
STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #2)
STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #2)
STS-48 #2 Channel Path Trace Control
S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #2)
S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #2)
S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #2)
S/W Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #2)
S/W Concatenation Mask STS-1 #1 to STS-1 #12 (STS-48 #2)
S/W Concatenation Mask STS-1 #13 to STS-1 #24 (STS-48 #2)
S/W Concatenation Mask STS-1 #25 to STS-1 #36 (STS-48 #2)
S/W Concatenation Mask STS-1 #37 to STS-1 #48 (STS-48 #2)
Received Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #2)
Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #2)
Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #2)
Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #2)
STS-48 Channel 2, Path Interrupt Status
STS-48 Channel 2, Path Interrupt Status Mask
Not Used
15:0
15:0
15:0
15:0
15:0
15:0
9:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
—
0x0
0x0
0x0
0x0
0x0
0x0
0x200
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
—
STS-1 Channel Interrupt Status, STS-1 #97 to STS-1 #112 (STS-48 #3)
STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #3)
STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #3)
STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #3)
STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #3)
STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #3)
STS-48 #3 Channel Path Trace Control
S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #3)
S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #3)
S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #3)
S/W Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #3)
S/W Concatenation Mask STS-1 #1 to STS-1 #12 (STS-48 #3)
S/W Concatenation Mask STS-1 #13 to STS-1 #24 (STS-48 #3)
S/W Concatenation Mask STS-1 #25 to STS-1 #36 (STS-48 #3)
S/W Concatenation Mask STS-1 #37 to STS-1 #48 (STS-48 #3)
Received Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #3)
Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #3)
Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #3)
15:0
15:0
15:0
15:0
15:0
15:0
9:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
0x0
0x0
0x0
0x0
0x0
0x0
0x200
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
108
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 71. Register Summary (continued)
Address
(Hex)
4612
4613
4614
4615—
46FF
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
470A
470B
470C
470D
470E
470F
4710
4711
4712
4713
4714
Name
Bits
Reset
Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #3)
STS-48 Channel 3, Path Interrupt Status
STS-48 Channel 3, Path Interrupt Status Mask
Not Used
11:0
11:0
11:0
—
0x0
0x0
0x0
—
STS-1 Channel Interrupt Status, STS-1 #145 to STS-1 #160 (STS-48 #4)
STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (STS-48 #4)
STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (STS-48 #4)
STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (STS-48 #4)
STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (STS-48 #4)
STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (STS-48 #4)
STS-48 #4 Channel Path Trace Control
S/W Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #4)
S/W Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #4)
S/W Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #4)
S/W Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #4)
S/W Concatenation Mask STS-1 #1 to STS-1 #12 (STS-48 #4)
S/W Concatenation Mask STS-1 #13 to STS-1 #24 (STS-48 #4)
S/W Concatenation Mask STS-1 #25 to STS-1 #36 (STS-48 #4)
S/W Concatenation Mask STS-1 #37 to STS-1 #48 (STS-48 #4)
Received Concatenation Map STS-1 #1 to STS-1 #12 (STS-48 #4)
Received Concatenation Map STS-1 #13 to STS-1 #24 (STS-48 #4)
Received Concatenation Map STS-1 #25 to STS-1 #36 (STS-48 #4)
Received Concatenation Map STS-1 #37 to STS-1 #48 (STS-48 #4)
STS-48 Channel 4, Path Interrupt Status
STS-48 Channel 4, Path Interrupt Status Mask
15:0
15:0
15:0
15:0
15:0
15:0
9:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
11:0
0x0
0x0
0x0
0x0
0x0
0x0
0x200
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Agere Systems Inc.
109
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Device-Level Registers
This section gives a brief description of each register bit and its functionality. The abbreviations after each register
indicate if the register is read only (RO), write one clear (W1C), read/write (R/W), or write only (WO).
W1C mode will clear bits to which a 1 is written. Bits written to 0 are not cleared.
Table 72. Interrupt Status (RO)
Address
(Hex)
Bit
Name
0
15:8
7
—
CHIP_EQPT_NSA
6
CHIP_EQPT_SA
5
CHIP_POH_STS48
4
CHIP_POH_STS1
3
CHIP_LTE_NSA
2
CHIP_LTE_SA
1
CHIP_PM_CLK
0
CHIP_CLK_LOSS
110
Description
Reset
Unused.
EQPT Nonservice-Affecting Alarms. Source—register 0x2000, bits 4—7, 9—12. See Table 150 on
page 134.
EQPT Service-Affecting Alarms. Source—register
0x2000, bits 0—3, 8. See Table 150 on page 134.
POH STS-48 Channel Alarms. Source—register
0x4000, bits 12—15. See Table 187 on page 149.
POH STS-1 Channel Alarms. Source—register
0x4000, bits 0—11. See Table 187 on page 149.
LTE Nonservice-Affecting Alarms. Source—register
0x1000, bits 4—7, 9—13. See Table 82 on page 115.
LTE Service-Affecting Alarms. Source—register
0x1000, bits 0—3, 8. See Table 82 on page 115.
PMCLK Positive Edge Detected. Source—register
0x7, bit 6. See Table 79 on page 113.
Clock Loss Alarms. Source—register 0x7, bits 0—5.
See Table 79 on page 113.
0
0
0
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 73. Interrupt Status Mask (R/W)
Address
(Hex)
Bit
Name
1
15:8
7
—
CHIP_EQPT_NSA_M
6
5
4
3
2
1
0
Description
Unused. Program to zero.
EQPT Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
CHIP_EQPT_SA_M EQPT Service-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
CHIP_POH_STS48_M POH STS-48 Channel Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
CHIP_POH_STS1_M POH STS-1 Channel Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
CHIP_LTE_NSA_M
LTE Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
CHIP_LTE_SA_M
LTE Service-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
CHIP_PM_CLK_M
PMCLK Positive Edge Detected Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
CHIP_CLK_LOSS_M Clock Loss Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
0
0
0
0
Table 74. Chip ID (RO)
Address
(Hex)
Bit
Name
2
15:0
CHIP_ID
Description
Reset
Chip Identification Code. Register always reads 0x1515
as 0x1515.
Table 75. Chip Vintage (RO)
Address
(Hex)
Bit
Name
3
15:0
CHIP_VINTAGE
Agere Systems Inc.
Description
Chip Vintage Code. Register always reads as
0x0005.
Reset
0x1
111
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 76. Scratch Pad, Clock Loss Alarm (R/W)
Address
(Hex)
Bit
Name
4
15:0
SCRATCH_PAD
Description
Reset
Scratch Pad Register. Does not impact device
operation.
0
Table 77. Chip-Level Maintenance (R/W)
Address
(Hex)
Bit
Name
5
15:1
0
—
FRC_PAR_ERR
Description
Reset
Unused. Program to zero.
Force Parity Error Alarms (all data paths and
memories).
1 = Forces an internal parity error alarm.
0 = Normal operation.
0
0
Table 78. Chip Status (RO)
Address
(Hex)
Bit
Name
6
15:3
2
—
DRPBYP
1
STS_MODE
0
CHIP_INT
112
Description
Reset
Unused.
State of DRPBYP Pin.
1 = Pointer generator is bypassed.
0 = Pointer generator is enabled.
State of STS_MODE Pin.
1 = STS-48.
0 = STS-192.
Chip Interrupt Activity Status (i.e., inverted
INT_N).
1 = Interrupt pin is asserted.
0 = No interrupt.
0
Pin
State
Pin
State
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 79. Clock Loss Alarm/PM Clock Detection (W1C)
Address
(Hex)
Bit
Name
7
15:7
—
6
PM_CLK
5
D_CLK_FAIL
4
T_CLK_FAIL
3
R_CLK_4_FAIL
2
R_CLK_3_FAIL
1
R_CLK_2_FAIL
0
R_CLK_1_FAIL
Agere Systems Inc.
Description
Unused. May write ones on clear (W1C) if
desired.
PMCLK Strobe Positive Edge Detected
(sampled by PCLK).
1 = PMCLK detected.
0 = PMCLK not detected.
Loss of Clock—D_CLK.
1 = Loss of clock.
0 = D_CLK detected.
Loss of Clock—T_CLK.
1 = Loss of clock.
0 = T_CLK detected.
Loss of Clock—R_CLK_4.
1 = Loss of clock.
0 = R_CLK_4 detected.
Loss of Clock—R_CLK_3.
1 = Loss of clock.
0 = R_CLK_3 detected.
Loss of Clock—R_CLK_2.
1 = Loss of clock.
0 = R_CLK_2 detected.
Loss of Clock—R_CLK_1.
1 = Loss of clock.
0 = R_CLK_1 detected.
Reset
0
0
0
0
0
0
0
0
113
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 80. Clock Loss Alarm/PM Clock Detection Mask (R/W)
Address
(Hex)
Bit
Name
8
15:7
6
—
PM_CLK_M
5
D_CLK_FAIL_M
4
T_CLK_FAIL_M
3
R_CLK_4_FAIL_M
2
R_CLK_3_FAIL_M
1
R_CLK_2_FAIL_M
0
R_CLK_1_FAIL_M
Description
Reset
Unused. Program to zero.
PMCLK Strobe Positive Edge Detected
(sampled by PCLK) Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Loss of Clock—D_CLK Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Loss of Clock—T_CLK Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Loss of Clock—R_CLK_4 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Loss of Clock—R_CLK_3 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Loss of Clock—R_CLK_2 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Loss of Clock—R_CLK_1 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
0
0
0
0
0
0
0
0
Table 81. Software Chip Reset (WO)
Address
(Hex)
Bit
Name
Description
Reset
FF
15:0
CHIP_SW_RESET
Force Hardware Reset to Entire Chip. Write
0xEAEA to initiate reset. Register always
reads as 0x0000. See the Software Reset section on page 96 for details.
0
114
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Line Terminating Equipment (LTE) Registers
The LTE registers are divided into six functional groups as follows:
■
■
■
■
■
■
LTE Common Registers: contains the interrupt status register and the associated mask register that consolidates
the alarms for the LTE.
LTE J0 Access Registers: used to read and provision J0 messages for both the receive and transmit direction.
Signal Degrade/Signal Fail Registers: allows the configuration of the detection time, error limits, and clear error
limit for signal fail and signal degrade detection. These registers are common to all four receive STS-48 channels.
LTE Receive Channel 1, 2, 3, and 4 Registers: provisioning, maintenance, alarm, and status registers for the
individual receive STS-48 channels. In STS-192 mode, only the first channel registers are used (except for the
receive overhead data (ROHDAT) memory parity error alarm, which is valid in all four channels).
LTE Transmit Common Registers: provisioning, maintenance, alarm, and status registers that are shared
between all four transmit STS-48 channels.
LTE Transmit Channel 1, 2, 3, and 4 Registers: provisioning, maintenance, alarm, and status registers for the
individual transmit STS-48 channels. In STS-192 mode, only the first channel registers are used (except for the
transmit overhead data (ROHDAT) memory parity error alarm, which is valid in all four channels).
LTE Common Registers
Table 82. LTE Interrupt Status (RO)
Address
(Hex)
Bit
Name
1000
15:14
—
13
Description
Reset
Unused.
0
LTE_TX_4_NSA
Transmit Channel 4 Nonservice-Affecting
Alarms.
0
12
LTE_TX_3_NSA
Transmit Channel 3 Nonservice-Affecting
Alarms.
0
11
LTE_TX_2_NSA
Transmit Channel 2 Nonservice-Affecting
Alarms.
0
10
LTE_TX_1_NSA
Transmit Channel 1 Nonservice-Affecting
Alarms.
0
9
LTE_TX_COMMON_NSA
Transmit Nonservice-Affecting Alarms.
0
8
LTE_TX_COMMON_SA
Transmit Service-Affecting Alarms.
0
7
LTE_RX_4_NSA
Receive Channel 4 Nonservice-Affecting
Alarms.
0
6
LTE_RX_3_NSA
Receive Channel 3 Nonservice-Affecting
Alarms.
0
5
LTE_RX_2_NSA
Receive Channel 2 Nonservice-Affecting
Alarms.
0
4
LTE_RX_1_NSA
Receive Channel 1 Nonservice-Affecting
Alarms.
0
3
LTE_RX_4_SA
Receive Channel 4 Service-Affecting Alarms.
0
2
LTE_RX_3_SA
Receive Channel 3 Service-Affecting Alarms.
0
1
LTE_RX_2_SA
Receive Channel 2 Service-Affecting Alarms.
0
0
LTE_RX_1_SA
Receive Channel 1 Service-Affecting Alarms.
0
Agere Systems Inc.
115
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 83. LTE Interrupt Status Mask (R/W)
Address
(Hex)
Bit
Name
1001
15:14
13
—
LTE_TX_4_NSA_M
12
11
10
9
8
7
6
5
4
116
Description
Reset
Unused. Program to zero.
Transmit Channel 4 Nonservice-Affecting
Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
LTE_TX_3_NSA_M
Transmit Channel 3 Nonservice-Affecting
Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
LTE_TX_2_NSA_M
Transmit Channel 2 Nonservice-Affecting
Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
LTE_TX_1_NSA_M
Transmit Channel 1 Nonservice-Affecting
Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
LTE_TX_COMMON_NSA_M Transmit Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
LTE_TX_COMMON_SA_M Transmit Service-Affecting Alarms Interrupt
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
LTE_RX_4_NSA_M
Receive Channel 4 Nonservice-Affecting
Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
LTE_RX_3_NSA_M
Receive Channel 3 Nonservice-Affecting
Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
LTE_RX_2_NSA_M
Receive Channel 2 Nonservice-Affecting
Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
LTE_RX_1_NSA_M
Receive Channel 1 Nonservice-Affecting
Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
0
0
0
0
0
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 83. LTE Interrupt Status Mask (R/W) (continued)
Address
(Hex)
Bit
Name
1001
3
LTE_RX_4_SA_M
2
LTE_RX_3_SA_M
1
LTE_RX_2_SA_M
0
LTE_RX_1_SA_M
Description
Receive Channel 4 Service-Affecting Alarms
Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Receive Channel 3 Service-Affecting Alarms
Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Receive Channel 2 Service-Affecting Alarms
Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Receive Channel 1 Service-Affecting Alarms
Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
LTE J0 Access Registers
The J0 access registers are used to read and provision the section trace messages for both the receive and transmit direction. The first step in reading or provisioning a message involves configuring the section trace access
maintenance register for the type of access that is to be performed. If a message write operation is being performed, the message buffer should then be programmed with the desired section trace message to be written to
the selected J0 memory. To start the transfer, write a 0x0001 to the J0 access message start register at which point
the transfer occurs on a non-real-time basis. The J0 access done flag indicates the completion of the message
transfer. If a read operation was specified, the J0 access message buffer now contains the contents of the selected
message.
Note: To insert J0 into the transmit stream, 0x0020 must be written register 0x1C01 (the enable insertion of provisioned J0 message register). See Table 137 on page 131 for detailed register information.
Table 84. Section Trace (J0) Access Maintenance (R/W)
Address
(Hex)
Bit
Name
1100
15:5
4:3
2
—
J_ACCESS_CH_NUM
J_ACCESS_DIR
1
J_ACCESS_MSG_TYPE
0
J_ACCESS_RW
Description
Unused. Program to zero.
J0 Access Channel Number (0 to 3).
J0 Access Direction.
1 = Transmit.
0 = Receive.
Received Message Type.
1 = Provisioned.
0 = Validated.
Message Read/Write.
1 = Write.
0 = Read.
Reset
0
0
0
0
0
Note: When the J_Access_Dir bit is set to 1 (transmit), the J_Access_Msg_Type bit is unused.
Agere Systems Inc.
117
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 85. J0 Access Done (W1C)
Address
(Hex)
Bit
Name
1101
15:1
—
0
J_ACCESS_DONE_FLAG
Description
Reset
Unused. May write ones on clear (W1C) if
desired.
Access Done Flag.
0
0
Note: The J0 access done flag is a write 1 clear (W1C) register, but does not generate an interrupt.
Table 86. J0 Access Message Start (WO)
Address
(Hex)
Bit
1102
15:1
0
Name
Description
—
Unused. Program to zero.
LTE_J_ACCESS_MSG_START Access Started Flag.
Reset
0
0
To start a J0 message transfer, write the value 0x0001 to this register. A read of this register is undefined and
should not be performed.
Table 87. J0 Access Message Buffers 1—32 (R/W)
Address
(Hex)
Bit
Name
1110—112F
15:0
LTE_J_ACCESS_BUF_n
Description
J0 Message Bytes.
Reset
0
The J0 access message buffer is organized as thirty-two 16-bit registers, which allows storage of 1 section trace
message. The beginning of the message should be stored in the lower byte of the first register (i.e., J0 access
message buffer word 1, address 1110, bits 7:0). For SDH messages, only the first eight registers contain the actual
message (i.e., 16 bytes); the other registers are undefined. During a read operation, the contents of the J0 access
message buffer is overwritten with the contents of the desired message.
118
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Signal Degrade/Signal Fail Registers
The SD/SF registers listed below are shared between all four receive STS-48 channels. Selection of the bit rate for
each channel is done using the corresponding LTE receive channel [1—4] maintenance register. The reset value
for the SD/SF registers depends on the state of the STS_MODE pin. In the tables below, the first value in the reset
field indicates the reset value of the register when the device is operating in STS-48 mode, and the second value is
used in STS-192 mode. Both values are given in decimal format.
Table 88. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–3) (R/W)
Address
(Hex)
Bit
Name
1300
15
SD_SF_DETECT_UNIT_3
14:0
SD_SF_DETECT_TIME_3
Description
Reset
Time Unit 0.5 ms(0)/1 s(1).
0/0
–3
Detection Time Value—BER: 1 x 10 .
8/8
Table 89. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–4) (R/W)
Address
(Hex)
Bit
Name
1301
15
SD_SF_DETECT_UNIT_4
14:0
SD_SF_DETECT_TIME_4
Description
Reset
Time Unit 0.5 ms(0)/1 s(1).
0/0
–4
Detection Time Value—BER: 1 x 10 .
8/8
Table 90. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–5) (R/W)
Address
(Hex)
Bit
Name
1302
15
SD_SF_DETECT_UNIT_5
14:0
SD_SF_DETECT_TIME_5
Description
Reset
Time Unit 0.5 ms(0)/1 s(1).
Detection Time Value—BER: 1 x
0/0
10–5.
8/8
Table 91. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–6) (R/W)
Address
(Hex)
1303
Bit
Name
Description
15
SD_SF_DETECT_UNIT_6
Time Unit 0.5 ms(0)/1 s(1).
14:0
SD_SF_DETECT_TIME_6
Detection Time Value—BER: 1 x 10–6.
Reset
0/0
62/13
Table 92. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–7) (R/W)
Address
(Hex)
1304
Bit
Name
Description
15
SD_SF_DETECT_UNIT_7
Time Unit 0.5 ms(0)/1 s(1).
14:0
SD_SF_DETECT_TIME_7
Detection Time Value—BER: 1 x 10–7.
Agere Systems Inc.
Reset
0/0
625/130
119
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 93. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–8) (R/W)
Address
(Hex)
Bit
Name
1305
15
SD_SF_DETECT_UNIT_8
14:0
SD_SF_DETECT_TIME_8
Description
Reset
Time Unit 0.5 ms(0)/1 s(1).
Detection Time Value—BER: 1 x
0/0
10–8
.
5200/1300
Table 94. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–9) (R/W)
Address
(Hex)
Bit
Name
1306
15
SD_SF_DETECT_UNIT_9
14:0
SD_SF_DETECT_TIME_9
Description
Reset
Time Unit 0.5 ms(0)/1 s(1).
1/0
–9
Detection Time Value—BER: 1 x 10 .
21/10500
Table 95. Line Signal Degrade/Signal Fail Bit Error Rate Detection Time (1 x 10–10) (R/W)
Address
(Hex)
Bit
Name
1307
15
SD_SF_DETECT_UNIT_10
14:0
SD_SF_DETECT_TIME_10
Description
Reset
Time Unit 0.5 ms(0)/1 s(1).
Detection Time Value—BER: 1 x
1/1
10–10.
170/41
Table 96. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–3) (R/W)
Address
(Hex)
Bit
Name
1310
15:0
SD_SF_ERR_LIMIT_3
Description
Detect Error Limit—BER: 1 x 10–3.
Reset
4818/19453
Table 97. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–4) (R/W)
Address
(Hex)
Bit
Name
1311
15:0
SD_SF_ERR_LIMIT_4
Description
Detect Error Limit—BER: 1 x 10–4.
Reset
862/3543
Table 98. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–5) (R/W)
Address
(Hex)
Bit
Name
1312
15:0
SD_SF_ERR_LIMIT_5
120
Description
Detect Error Limit—BER: 1 x 10–5.
Reset
81/358
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 99. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–6) (R/W)
Address
(Hex)
Bit
Name
1313
15:0
SD_SF_ERR_LIMIT_6
Description
Detect Error Limit—BER: 1 x 10–6.
Reset
62/51
Table 100. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–7) (R/W)
Address
(Hex)
Bit
Name
1314
15:0
SD_SF_ERR_LIMIT_7
Description
Detect Error Limit—BER: 1 x 10–7.
Reset
62/51
Table 101. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–8) (R/W)
Address
(Hex)
Bit
Name
1315
15:0
SD_SF_ERR_LIMIT_8
Description
Detect Error Limit—BER: 1 x 10–8.
Reset
51/51
Table 102. Line Signal Degrade/Signal Fail Detect Error Limit (1 x 10–9) (R/W)
Address
(Hex)
Bit
Name
1316
15:0
SD_SF_ERR_LIMIT_9
Description
Detect Error Limit—BER: 1 x 10–9.
Reset
40/40
Table 103. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–4) (R/W)
Address
(Hex)
Bit
Name
1320
15:0
SD_SF_CLR_ERR_LIMIT_3
Description
Clear Error Limit—BER: 1 x 10–4.
Reset
957/3734
Table 104. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–5) (R/W)
Address
(Hex)
Bit
Name
1321
15:0
SD_SF_CLR_ERR_LIMIT_4
Description
Clear Error Limit—BER: 1 x 10–5.
Reset
114/423
Table 105. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–6) (R/W)
Address
(Hex)
Bit
Name
1322
15:0
SD_SF_CLR_ERR_LIMIT_5
Agere Systems Inc.
Description
Clear Error Limit—BER: 1 x 10–6.
Reset
91/77
121
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 106. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–7) (R/W)
Address
(Hex)
Bit
Name
1323
15:0
SD_SF_CLR_ERR_LIMIT_6
Description
Reset
Clear Error Limit—BER: 1 x 10–7.
91/77
Table 107. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–8) (R/W)
Address
(Hex)
Bit
Name
1324
15:0
SD_SF_CLR_ERR_LIMIT_7
Description
Reset
Clear Error Limit—BER: 1 x 10–8.
77/77
Table 108. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–9) (R/W)
Address
(Hex)
Bit
Name
1325
15:0
SD_SF_CLR_ERR_LIMIT_8
Description
Reset
Clear Error Limit—BER: 1 x 10–9.
63/63
Table 109. Line Signal Degrade/Signal Fail Clear Error Limit (1 x 10–10) (R/W)
Address
(Hex)
Bit
Name
1326
15:0
SD_SF_CLR_ERR_LIMIT_9
Description
Reset
Clear Error Limit—BER: 1 x 10–10.
52/51
LTE Receive Channel 1, 2, 3, and 4 Registers
■
Base address: 0x1400
■
Channel offset: 0x0100
Table 110. LTE Receive Channel 1 Provisioning (R/W)
Address
(Hex)
1400
Bit
Name
15:8
7
—
B1_ERROR_MASK_EN
6
5
4
3
2
1
0
122
Description
Reset
Unused. Program to zero.
B1 Error Mask Enable.
1 = ROHDAT B1 byte error mask.
0 = ROHDAT B1 byte.
B1_BIP_MODE_1
B1 BIP-8 Mode.
1 = Block error mode.
0 = Bit error mode.
K_VALIDATE_LIMIT_SEL_1 K1K2 Validate Select.
1 = Five consecutive frames.
0 = Three consecutive frames.
RX_FRM_EN_1
RFRM Output Enable.
1 = Validated S1 byte.
0 = 8 kHz signal.
DESCRM_DIS_1
Disable Descrambling LTE Receive Input Signals.
ENH_FRMG_CTL_1
Enable Enhanced Framing.
SEF_AIS_DIS_1
Disable AIS Generation Due to Severely Errored
Frame (SEF).
LOF_AIS_DIS_1
Disable AIS Generation Due to Loss of Frame
(LOF).
0
0
0
0
0
0
0
1
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 111. LTE Receive Channel 1 Maintenance (R/W)
Address
(Hex)
Bit
Name
1401
15:7
6
—
J_MSG_TYPE_1
5
J_MSG_MODE_1
4:2
SD_BER_1
1:0
SF_BER_1
Description
Unused. Program to zero.
J0 Message Type.
1 = SDH.
0 = SONET.
J0 Message Mode.
1 = Validated.
0 = Provisioned.
Signal Degrade Bit Error Rate.
4 = 1 x 10–9.
3 = 1 x 10–8.
2 = 1 x 10–7.
1 = 1 x 10–6.
0 = 1 x 10–5.
Signal Fail Bit Error Rate.
2 = 1 x 10–5.
1 = 1 x 10–4.
0 = 1 x 10–3.
Reset
0
0
1
0
0
Table 112. LTE Receive Channel 1 Loss-of-Signal (LOS) Threshold (R/W)
Address
(Hex)
Bit
1402
15:10
9:0
Name
Description
—
Unused. Program to zero.
LTE_RX_1_LOS_THRESHOLD1 Threshold to Declare LOS (all zeros),
Measured in Multiples of Eight R_CLK_n
Cycles.
Reset
0
0x86
Table 113. LTE Receive Channel 1 K Byte Status (RO)
Address
(Hex)
Bit
Name
1403
15:8
7:0
RX_K1_VALIDATED_BYTE_1
RX_K2_VALIDATED_BYTE_1
Description
K1 Byte—Validated (3/5) K1 Bytes.
K2 Byte—Validated (3/5) K2 Bytes.
Reset
0
0
Table 114. LTE Receive Channel 1 S1 Byte Status (RO)
Address
(Hex)
Bit
Name
1404
15:8
7:0
—
LTE_RX_1_RX_S1_BYTE_1
Agere Systems Inc.
Description
Unused.
S1 Byte—Validated (7) S1 Bytes.
Reset
0
0
123
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 115. LTE Receive Channel 1 Service-Affecting Interrupt Alarm (W1C)
Address
(Hex)
Bit
Name
1405
15:5
—
4
3
2
1
0
SD_ALARM_1
SF_ALARM_1
RX_LINE_AIS_ALARM_1
LOF
LOS
Description
Reset
Unused. May write ones on clear (W1C) if
desired.
Signal Degrade.
Signal Fail.
Line AIS.
Loss of Frame.
Loss of Signal.
0
0
0
0
1
0
Table 116. LTE Receive Channel 1 Service-Affecting Interrupt Alarm Mask (R/W)
Address
(Hex)
Bit
Name
1406
15:5
4
—
SD_ALARM_1_M
3
SF_ALARM_1_M
2
RX_LINE_AIS_ALARM_1_M
1
LOF_M
0
LOS_M
Description
Unused. Program to zero.
Signal Degrade Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Signal Fail Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Line AIS Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Loss of Frame Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Loss of Signal Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
0
Table 117. LTE Receive Channel 1 Service-Affecting Persistency Alarm (RO)
Address
(Hex)
Bit
Name
1407
15:3
2
1
0
—
AISL_PER
LOF_PER
LOS_PER
124
Description
Unused.
Persistent Line AIS Alarm.
Persistent LOF Alarm.
Persistent LOS Alarm.
Reset
0
0
1
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 118. LTE Receive Channel 1 Nonservice-Affecting Interrupt Alarm (W1C)
Address
(Hex)
Bit
Name
Description
Reset
1408
15:11
—
0
10
RX_OH_MEM_PAR_ERR_1
9
8
7
6
5
4
J_MEM_PARITY_ERR_1
RX_S1_NEW_BYTE_RAW_INT_1
RX_K2_NEW_BYTE_RAW_INT_1
RX_K1_NEW_BYTE_RAW_INT_1
INCONSISTENT_APS_ALARM_1
CHANNEL_MISMATCH_ALARM_1
3
2
1
RX_LINE_RDI_ALARM_1
J_NEW_MSG_INT_1
J_MSG_MISMATCH_INT_1
0
SEF
Unused. May write ones on clear (W1C)
if desired.
Receive Overhead Data (ROHDAT)
Memory Parity Error.
J0 Message Buffer Parity Error.
New Validated S1 Byte Received.
New Validated K2 Byte Received.
New Validated K1 Byte Received.
Inconsistent APS Byte Received.
Receive/Transmit K1K2 Byte Channel
Mismatch.
Line Remote Defect Indication (RDI-L).
New Validated J0 Message Received.
Received J0 Message Mismatch (with
expected message).
Severely Errored Frame (SEF).
Agere Systems Inc.
0
0
0
0
0
0
0
0
0
0
1
125
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 119. LTE Receive Channel 1 Nonservice-Affecting Interrupt Mask (R/W)
Address
(Hex)
Bit
1409
15:11
10
9
8
7
6
5
4
3
2
1
0
126
Name
Description
Reset
—
Unused. Program to zero.
RX_OH_MEM_PAR_ERR_1_M Receive Overhead Data (ROHDAT) Memory
Parity Error Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
J_MEM_PARITY_ERR_1_M
J0 Message Buffer Parity Error Interrupt
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
RX_S1_NEW_BYTE_RAW_
New Validated S1 Byte Received Interrupt
INT_1_M
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
RX_K2_NEW_BYTE_RAW_
New Validated K2 Byte Received Interrupt
INT_1_M
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
RX_K1_NEW_BYTE_RAW_
New Validated K1 Byte Received Interrupt
INT_1_M
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
INCONSISTENT_APS_ALARM_ Inconsistent APS Byte Received Interrupt
1_M
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
CHANNEL_MISMATCH_
Receive/Transmit K1K2 Byte Channel MisALARM_1_M
match Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
RX_LINE_RDI_ALARM_1_M Line Remote Defect Indication (RDI-L) Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
J_NEW_MSG_INT_1_M
New Validated J0 Message Received Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
J_MSG_MISMATCH_INT_1_M Received J0 Message Mismatch (with
Expected) Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
SEF_M
Severely Errored Frame (SEF) Interrupt
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
0
0
0
0
0
0
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 120. LTE Receive Channel 1 Nonservice-Affecting Persistency Alarm (RO)
Address
(Hex)
Bit
140A
15:6
5
4
3
2:0
Name
Description
—
Unused.
INCONSISTENT_APS_PER_1 Inconsistent APS Byte Received.
CHANNEL_MISMATCH_PER_1 Receive/Transmit K1K2 Byte Channel
Mismatch.
RX_LINE_RDI_PER_1
Line Remote Defect Indication (RDI-L).
—
Unused.
Reset
0
0
0
0
0
Table 121. LTE Receive Channel 1 Performance Monitoring (RO)
Address
(Hex)
Bit
Name
Description
Reset
140B
15:5
4
—
RX_LINE_RDI_PM_1
0
0
3
SEF_PM
2
1
0
RX_LINE_AIS_PM_1
LOF_PM
LOS_PM
Unused.
Line Remote Defect Indication (RDI-L) Detect
Last Second.
Severely Errored Frame (SEF) Detect Last Second.
Line AIS (AIS-L) Detect Last Second.
Loss of Frame (LOF) Detect Last Second.
Loss of Signal (LOS) Detect Last Second.
0
0
0
0
Table 122. LTE Receive Channel 1 REI-L Performance Monitoring (L) (RO)
Address
(Hex)
Bit
Name
Description
Reset
140C
15:0
REI_L_REG_1_L
Remote Error Indications in Last Second (LSW).
0
Table 123. LTE Receive Channel 1 REI-L Performance Monitoring (U) (RO)
Address
(Hex)
Bit
Name
140D
15:5
4:0
—
REI_L_REG_1_U
Description
Unused.
Remote Error Indications in Last Second
(MSW).
Reset
0
0
Table 124. LTE Receive Channel 1 CV-L Performance Monitoring (L) (RO)
Address
(Hex)
Bit
Name
140E
15:0
CV_L_REG_1_L
Description
Line BIP-8 Errors (B2) Errors in Last Second
(LSW).
Reset
0
Table 125. LTE Receive Channel 1 CV-L Performance Monitoring (U) (RO)
Address
(Hex)
Bit
Name
140F
15:8
7:0
—
CV_L_REG_1_U
Agere Systems Inc.
Description
Unused.
Line BIP-8 Errors (B2) Errors in Last Second
(MSW).
Reset
0
0
127
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 126. LTE Receive Channel 1 CV-S Performance Monitoring (RO)
Address
(Hex)
1410
Bit
Name
15:0
CV_S_REG_1
Description
Reset
Section BIP-8 Errors (B1) in Last Second.
0
LTE Transmit Common Registers
Table 127. LTE Transmit—Frame Pulse Offset Count (R/W)
Address
(Hex)
1B00
Bit
Name
Description
Reset
15
ADD_TX_SYNC
0
14
TX_FRM_DEJITTER_EN
13:0
LTE_TX_FRM_OFFSET_
COUNT
Transmit Add Synchronization Enable
(ADD_TX_SYNC = 0).
TFRM Dejitter Circuit Enable
(bit 15 set to 0).
Frame Pulse Offset Position (in Multiples of
Eight T_CLK Clock Cycles). See the Add
Interface Framing (A1 and A2) section on
page 82 for details.
0
0
Table 128. LTE Transmit—Add Interface Self-Sync Option (R/W)
Address
(Hex)
1B00
Bit
Name
Description
Reset
15
ADD_TX_SYNC
1
14:4
3:0
—
LTE_TX_FRM_ADDCHNL_
SEL
Transmit Add Synchronization Enable
(ADD_TX_SYNC = 1).
Unused (when bit 15 set to 1).
When Bit 15 is Set to 1, Bits 3:0 Select
Transmit Frame Sync Add Channel (1—16).
See the Add Interface Framing (A1 and A2)
section on page 82 for details.
0
0
Table 129. LTE Transmit—B1 Corrupt Frame Count (R/W)
Address
(Hex)
1B01
Bit
15:13
12:0
Name
Description
Reset
—
Unused. Program to zero.
LTE_TX_B1_NUM_CORRUPT_ Number of Frames to Corrupt Inserted
FRAMES
B1 Byte. Used by register 0x1C00. See
Table 135 on page 130.
0
0
Table 130. LTE Transmit—B2 Corrupt Frame Count (R/W)
Address
(Hex)
1B02
Bit
15:13
12:0
Name
Description
Reset
—
Unused. Program to zero.
LTE_TX_B2_NUM_CORRUPT_ Number of Frames to Corrupt Inserted B2
FRAMES
Bytes. Used by register 0x1C00. See
Table 135 on page 130.
0
0
B2 Error Serial Access. Enabled when
value is greater than or equal to 8064(dec).
128
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 131. LTE Transmit—M1 Corrupt Frame Count (R/W)
Address
(Hex)
Bit
1B03
15:13
12:0
Name
Description
—
Unused. Program to zero.
LTE_TX_M1_NUM_CORRUP Number of Frames to Corrupt Inserted M1
T_FRAMES
Byte. Used by register 0x1C00. See Table 135
on page 130.
Reset
0
0
Table 132. LTE Transmit—TFRM S1 Byte (RO)
Address
(Hex)
Bit
1B04
15:8
7:0
Name
Description
—
Unused.
LTE_TX_S1_BYTE_TX_FRM Validated S1 Byte from TFRM Signal. See
the Synchronization Status (S1) section on
page 91 for details.
Reset
0
0
Table 133. LTE Transmit—Interrupt Alarm Register (W1C)
Address
(Hex)
Bit
Name
1B05
15:4
—
3
2
1
0
Agere Systems Inc.
Description
Unused. May write ones on clear (W1C) if
desired.
TX_FRM_RESYNC
TFRM Resynchronization Alarm. Latched
alarm. See the Add Interface Framing (A1 and
A2) section on page 82 for details.
TX_J0_MEM_PARITY_ERR Transmit J0 Memory Parity Error. See the
Section Trace/Section Growth (J0/Z0) section
on page 86 for details.
TX_FRM_S1_BYTE_INVALID Valid S1 Byte Not Received. See the Synchronization Status (S1) section on page 91 for
details.
TX_FRM_LOF
TFRM Loss of Frame. See the Add Interface
Framing (A1 and A2) section on page 82 for
details.
Reset
0
0
0
0
0
129
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 134. LTE Transmit—Interrupt Mask Register (R/W)
Address Bit
(Hex)
1B06
15:4
3
2
1
0
Name
Description
Reset
—
TX_FRM_RESYNC_M
Unused. Program to zero.
TFRM Resynchronization Alarm Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
TX_J0_MEM_PARITY_ERR_M Transmit J0 Memory Parity Error Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
TX_FRM_S1_BYTE_INVALID_M Valid S1 Byte Not Received Error Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
TX_FRM_LOF_M
TFRM Loss of Frame Error Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
0
0
0
0
0
LTE Transmit Channel Registers
■
Base address: 0x1C00
■
Channel offset: 0x0100
Table 135. LTE Transmit Channel 1 Provisioning (R/W)
Address
(Hex)
Bit
Name
1C00
15:11
10
—
TX_SS_OVERWRITE_EN
9
8
7
6
5
4
3
2
1
0
130
Description
Reset
Unused. Program to zero.
Enable Insertion of Defined SS Bits in All of the Outgoing H1 Bytes.
SS_MODE
SS Bit Mode Define SS Bit.
1 = SDH (10).
0 = SONET (00).
REGEN_LOOPBACK
Powerup Default.
LINE_TRANS_ONLY_EN Powerup Default.
TOH_TRANS_EN
Powerup Default.
SCRM_DIS_1
Disable Scrambling on Transmit Data.
M1_CORRUPT_EN_1
Enable Corruption of M1 Byte for N Frames. (The
number of frames (N) is selected in register 0x1B03,
Table 131 on page 129.)
B2_CORRUPT_EN_1
Enable Corruption of B2 Bytes for N Frames. (The
number of frames (N) is selected in register 0x1B02,
Table 130 on page 128.)
B1_CORRUPT_EN_1
Enable Corruption of B1 Byte for N Frames. (The
number of frames (N) is selected in register 0x1B01,
Table 129 on page 128.)
TX_FRAMING_MODE_1
Framing Mode. Enhanced mode is normally used only
when in STS-192 mode.
1 = Enhanced.
0 = Normal.
TX_TOH_DATA_INSERT_1 Enable Transport Overhead Data (TOHDAT) Insertion.
0
0
0
0
0
0
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 136. LTE Transmit Bit Assignment
Bit 7
Bit 6
LINE_TRANS_ONLY_EN TOH_TRANS_EN
X
0
0
1
1
1
Description
Section and line terminated (pointer processor state dependent on DRPBYP pin).
Full section and line overhead transparency (pointer processor bypassed automatically).
Line overhead transparency section is terminated (pointer
processor bypassed).
Note: X indicates either value.
Table 137. LTE Transmit Channel 1 Maintenance (R/W)
Address Bit
(Hex)
1C01
Name
Description
15:6
—
Unused. Program to zero.
5
TX_J0_MSG_INSERT_EN_1 Enable Insertion of Provisioned J0 Message.
4 S1_BYTE_TX_FRM_INSERT_1 Insert Validated S1 Byte from TFRM.
3:2
TX_K_BYTES_SELECT_1
K Byte Select. SW(0)/Raw K Bytes(1)/Validated K
Bytes(2).
1
RDI_L_SELECT_1
Enable RDI-L Insertion. When set to 1, enables
RDI-L when a condition arises to cause RDI-L.
0
TX_LINE_AIS_INSERT_1
Force Line AIS Insertion. Forces AIS_L Insertion
when set to 1.
Reset
0
0
0
0
0
0
Table 138. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #1 (R/W)
Address
(Hex)
Bit
Name
1C02
15:12
11:0
—
LTE_TX_1_UNEQ_P_EN_1
Description
Unused. Program to zero.
Insert UNEQ-P on Specific STS-1 (1 to 12).
Reset
0
0
Table 139. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #2 (R/W)
Address
(Hex)
Bit
Name
Description
Reset
1C03
15:12
11:0
—
LTE_TX_1_UNEQ_P_EN_2
Unused. Program to zero.
Insert UNEQ-P on Specific STS-1 (13 to 24).
0
0
Table 140. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #3 (R/W)
Address
(Hex)
Bit
Name
Description
Reset
1C04
15:12
11:0
—
LTE_TX_1_UNEQ_P_EN_3
Unused. Program to zero.
Insert UNEQ-P on Specific STS-1 (25 to 36).
0
0
Agere Systems Inc.
131
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 141. LTE Transmit Channel 1 Path Unequipped (UNEQ-P) Insert Enable #4 (R/W)
Address
(Hex)
Bit
Name
Description
Reset
1C05
15:12
11:0
—
LTE_TX_1_UNEQ_P_EN_4
Unused. Program to zero.
Insert UNEQ-P on Specific STS-1 (37 to 48).
0
0
Table 142. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #1 (R/W)
Address
(Hex)
Bit
Name
1C06
15:12
11:0
—
LTE_TX_1_PATH_AIS_EN_1
Description
Reset
Unused. Program to zero.
Insert AIS-P on Specific STS-1 (1 to 12).
0
0
Table 143. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #2 (R/W)
Address
(Hex)
Bit
Name
1C07
15:12
11:0
—
LTE_TX_1_PATH_AIS_EN_2
Description
Reset
Unused. Program to zero.
Insert AIS-P on Specific STS-1 (13 to 24).
0
0
Table 144. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #3 (R/W)
Address
(Hex)
Bit
Name
1C08
15:12
11:0
—
LTE_TX_1_PATH_AIS_EN_3
Description
Reset
Unused. Program to zero.
Insert AIS-P on Specific STS-1 (25 to 36).
0
0
Table 145. LTE Transmit Channel 1 Path AIS (AIS-P) Insert Enable #4 (R/W)
Address
(Hex)
Bit
Name
1C09
15:12
11:0
—
LTE_TX_1_PATH_AIS_EN_4
Description
Reset
Unused. Program to zero.
Insert AIS-P on Specific STS-1 (37 to 48).
0
0
Table 146. LTE Transmit Channel 1 K1K2 Byte Insert Values (R/W)
Address
(Hex)
Bit
Name
1C0A
15:8
7:0
TX_K1_SW_BYTE_1
TX_K2_SW_BYTE_1
Description
K1 Byte Value to Insert.
K2 Byte Value to Insert.
Reset
0
0
Table 147. LTE Transmit Channel 1 S1 Byte Insert Value (R/W)
Address
(Hex)
Bit
Name
1C0B
15:8
7:0
—
LTE_TX_1_S1_DATA_1
132
Description
Unused. Program to zero.
S1 Byte Value to Insert.
Reset
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 148. LTE Transmit Channel 1 Interrupt Alarm (W1C)
Address
(Hex)
Bit
Name
1C0C
15:2
—
1
0
Description
Unused. May write ones on clear (W1C) if
desired.
TX_OH_MEM_PARITY_ERR_1 Transport Overhead Data Memory Parity
Error.
TX_DATA_PAR_ERR_1
Transmit Data Path Internal Parity Error.
Reset
0
0
0
Table 149. LTE Transmit Channel 1 Interrupt Alarm Mask (R/W)
Address
(Hex)
Bit
Name
1C0D
15:2
—
1
0
Agere Systems Inc.
Description
Unused. Program to zero.
TX_OH_MEM_PARITY_ERR_1_M Transport Overhead Data Memory Parity
Error Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
TX_DATA_PAR_ERR_1_M
Transmit Data Path Internal Parity Error
Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
133
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Equipment (EQPT) Registers
EQPT Common Registers
Table 150. EQPT Interrupt Status (RO)
Address
(Hex)
Bit
Name
2000
15:13
—
Reset
Unused.
0
12
EQPT_RX_DRP_NSA_4 Receive Drop STS-48 Channel Nonservice-Affecting
Alarms.
0
11
EQPT_RX_DRP_NSA_3 Receive Drop STS-48 Channel Nonservice-Affecting
Alarms.
0
10
EQPT_RX_DRP_NSA_2 Receive Drop STS-48 Channel Nonservice-Affecting
Alarms.
0
9
EQPT_RX_DRP_NSA_1 Receive Drop STS-48 Channel Nonservice-Affecting
Alarms.
0
8
134
Description
EQPT_RX_DRP_SA
Receive Drop Common Service-Affecting Alarms.
0
7
EQPT_TX_ADD_NSA_4 Transmit Add STS-48 Channel 4 Nonservice-Affecting
Alarms.
0
6
EQPT_TX_ADD_NSA_3 Transmit Add STS-48 Channel 3 Nonservice-Affecting
Alarms.
0
5
EQPT_TX_ADD_NSA_2 Transmit Add STS-48 Channel 2 Nonservice-Affecting
Alarms.
0
4
EQPT_TX_ADD_NSA_1 Transmit Add STS-48 Channel 1 Nonservice-Affecting
Alarms.
0
3
EQPT_TX_ADD_SA_4
Transmit Add STS-48 Channel 4 Service-Affecting
Alarms.
0
2
EQPT_TX_ADD_SA_3
Transmit Add STS-48 Channel 3 Service-Affecting
Alarms.
0
1
EQPT_TX_ADD_SA_2
Transmit Add STS-48 Channel 2 Service-Affecting
Alarms.
0
0
EQPT_TX_ADD_SA_1
Transmit Add STS-48 Channel 1 Service-Affecting
Alarms.
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 151. EQPT Interrupt Mask (R/W)
Address
(Hex)
Bit
2001
15:13
12
11
10
9
8
7
6
5
4
3
2
Agere Systems Inc.
Name
Description
—
Unused. Program to zero.
EQPT_RX_DRP_NSA_4_M Receive Drop STS-48 Channel Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_RX_DRP_NSA_3_M Receive Drop STS-48 Channel Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_RX_DRP_NSA_2_M Receive Drop STS-48 Channel Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_RX_DRP_NSA_1_M Receive Drop STS-48 Channel Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_RX_DRP_SA_M
Receive Drop Common Service-Affecting
Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_TX_ADD_NSA_4_M Transmit Add STS-48 Channel 4 Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_TX_ADD_NSA_3_M Transmit Add STS-48 Channel 3 Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_TX_ADD_NSA_2_M Transmit Add STS-48 Channel 2 Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_TX_ADD_NSA_1_M Transmit Add STS-48 Channel 1 Nonservice-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_TX_ADD_SA_4_M Transmit Add STS-48 Channel 4 Service-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
EQPT_TX_ADD_SA_3_M Transmit Add STS-48 Channel 3 Service-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
135
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 151. EQPT Interrupt Mask (R/W) (continued)
Address
(Hex)
Bit
Name
2001
1
EQPT_TX_ADD_SA_2_M
0
EQPT_TX_ADD_SA_1_M
Description
Reset
0
Transmit Add STS-48 Channel 2 Service-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Transmit Add STS-48 Channel 1 Service-Affecting Alarms Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
0
Table 152. Receive Drop Common Service-Affecting Alarm (W1C)
Address
(Hex)
Bit
Name
2002
15:1
—
0
DFRM_LOSS
Description
Reset
Unused. May write ones on clear (W1C) if
desired.
Loss of DFRM Signal.
1 = Loss of DFRM.
0 = DFRM detected.
0
0
Table 153. Receive Drop Common Service-Affecting Alarm Mask (R/W)
Address
(Hex)
Bit
Name
2003
15:1
0
—
DFRM_LOSS_M
136
Description
Unused. Program to zero.
Loss of DFRM Signal Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
EQPT Receive Drop STS-48 Channel Registers 1—4
■
Base address: 0x2400
■
Channel offset: 0x0100
Table 154. Receive Drop STS-48 Channel Provisioning Register 1 (R/W)
Address
(Hex)
Bit
Name
2400
15:2
1
—
B1_ERROR_INS
0
SCRM_DISABLE
Description
Unused. Program to zero.
Insert BIP-8 Error.
1 = Insert a BIP-8 error.
Scrambler Disable.
1 = Disables the receive drop interface scrambler.
0 = Enables the receive drop interface scrambler.
Reset
0
0
0
Table 155. J0 Trace—STS-12 Channel 1 (R/W)
Address
(Hex)
Bit
Name
2401
15:8
7:0
—
J0_BYTE_1
Description
Unused. Program to zero.
J0 Byte for Insert in STS-12 Channel 1.
Reset
0
1
Table 156. J0 Trace—STS-12 Channel 2 (R/W)
Address
(Hex)
Bit
Name
2402
15:8
7:0
—
J0_BYTE_2
Description
Unused. Program to zero.
J0 Byte for Insert in STS-12 Channel 2.
Reset
0
2
Table 157. J0 Trace—STS-12 Channel 3 (R/W)
Address
(Hex)
Bit
Name
2403
15:8
7:0
—
J0_BYTE_3
Description
Unused. Program to zero.
J0 Byte for Insert in STS-12 Channel 3.
Reset
0
3
Table 158. J0 Trace—STS-12 Channel 4 (R/W)
Address
(Hex)
Bit
Name
2404
15:8
7:0
—
J0_BYTE_4
Agere Systems Inc.
Description
Unused. Program to zero.
J0 Byte for Insert in STS-12 Channel 4.
Reset
0
4
137
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 159. Receive Drop STS-48 Channel Nonservice-Affecting Alarm (W1C)
Address
(Hex)
Bit
Name
2405
15:5
—
4
RX_DATA_PAR_ERR_4
3
2
1
0
RX_DATA_PAR_ERR_3
RX_DATA_PAR_ERR_2
RX_DATA_PAR_ERR_1
RX_DATA_PAR_ERR_0
Description
Reset
Unused. May write ones on clear (W1C) if
desired.
Data Path Parity Error Timing Control
Channel.
Data Path Parity Error STS-12 Channel 3.
Data Path Parity Error STS-12 Channel 2.
Data Path Parity Error STS-12 Channel 1.
Data Path Parity Error STS-12 Channel 0.
0
0
0
0
0
0
Table 160. Receive Drop STS-48 Channel Nonservice Affecting Alarm Mask (R/W)
Address
(Hex)
Bit
Name
2406
15:5
4
—
RX_DATA_PAR_ERR_4_M
3
RX_DATA_PAR_ERR_3_M
2
RX_DATA_PAR_ERR_2_M
1
RX_DATA_PAR_ERR_1_M
0
RX_DATA_PAR_ERR_0_M
138
Description
Reset
Unused. Program to zero.
Data Path Parity Error Timing Control
Channel Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Data Path Parity Error STS-12 Channel 3
Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Data Path Parity Error STS-12 Channel 2
Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Data Path Parity Error STS-12 Channel 1
Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Data Path Parity Error STS-12 Channel 0
Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
EQPT Transmit Add STS-48 Channel Registers 1—4
■
Base address: 0x2C00
■
Channel offset: 0x0100
Table 161. Transmit Add STS-48 Channel Provisioning (R/W)
Address
(Hex)
Bit
2C00
15:2
1
0
Name
Description
—
Unused. Program to zero.
FRC_ADD_BUFFER_OVRFLW Force Add Buffer Overflow/Underflow
Alarm in STS-12s.
1 = Force an add buffer overflow/underflow
alarm.
0 = Normal operation.
DESCRM_DISABLE
Descrambler Disable.
1 = Disables the transmit add interface
scrambler.
0 = Enables the transmit add interface scrambler.
Reset
0
0
0
Table 162. J0 Status Register—1 (RO)
Address
(Hex)
Bit
Name
2C01
15:8
7:0
—
J0_BYTE—STS-12 Channel 1
Description
Unused.
J0 Status Byte.
Reset
0
0
Table 163. J0 Status Register—2 (RO)
Address
(Hex)
Bit
Name
2C02
15:8
7:0
—
J0_BYTE—STS-12 Channel 2
Description
Unused.
J0 Status Byte.
Reset
0
0
Table 164. J0 Status Register—3 (RO)
Address
(Hex)
Bit
Name
2C03
15:8
7:0
—
J0_BYTE—STS-12 Channel 3
Description
Unused.
J0 Status Byte.
Reset
0
0
Table 165. J0 Status Register—4 (RO)
Address
(Hex)
Bit
Name
2C04
15:8
7:0
—
J0_BYTE—STS-12 Channel 4
Agere Systems Inc.
Description
Unused.
J0 Status Byte.
Reset
0
0
139
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 166. AIS Insert Status Register, STS-12 Channel #1 (RO)
Address
(Hex)
Bit
Name
2C05
15:12
11
10
9
8
7
6
5
4
3
2
1
0
—
AIS_INSERT11
AIS_INSERT10
AIS_INSERT9
AIS_INSERT8
AIS_INSERT7
AIS_INSERT6
AIS_INSERT5
AIS_INSERT4
AIS_INSERT3
AIS_INSERT2
AIS_INSERT1
AIS_INSERT0
Description
Unused.
STS Channel #12 AIS Insert Status.
STS Channel #11 AIS Insert Status.
STS Channel #10 AIS Insert Status.
STS Channel #9 AIS Insert Status.
STS Channel #8 AIS Insert Status.
STS Channel #7 AIS Insert Status.
STS Channel #6 AIS Insert Status.
STS Channel #5 AIS Insert Status.
STS Channel #4 AIS Insert Status.
STS Channel #3 AIS Insert Status.
STS Channel #2 AIS Insert Status.
STS Channel #1 AIS Insert Status.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 167. AIS Insert Status Register, STS-12 Channel #2 (RO)
Address
(Hex)
Bit
Name
2C06
15:12
11
10
9
8
7
6
5
4
3
2
1
0
—
AIS_INSERT11
AIS_INSERT10
AIS_INSERT9
AIS_INSERT8
AIS_INSERT7
AIS_INSERT6
AIS_INSERT5
AIS_INSERT4
AIS_INSERT3
AIS_INSERT2
AIS_INSERT1
AIS_INSERT0
140
Description
Unused.
STS Channel #12 AIS Insert Status.
STS Channel #11 AIS Insert Status.
STS Channel #10 AIS Insert Status.
STS Channel #9 AIS Insert Status.
STS Channel #8 AIS Insert Status.
STS Channel #7 AIS Insert Status.
STS Channel #6 AIS Insert Status.
STS Channel #5 AIS Insert Status.
STS Channel #4 AIS Insert Status.
STS Channel #3 AIS Insert Status.
STS Channel #2 AIS Insert Status.
STS Channel #1 AIS Insert Status.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 168. AIS Insert Status Register, STS-12 Channel #3 (RO)
Address
(Hex)
Bit
Name
2C07
15:12
11
10
9
8
7
6
5
4
3
2
1
0
—
AIS_INSERT11
AIS_INSERT10
AIS_INSERT9
AIS_INSERT8
AIS_INSERT7
AIS_INSERT6
AIS_INSERT5
AIS_INSERT4
AIS_INSERT3
AIS_INSERT2
AIS_INSERT1
AIS_INSERT0
Description
Unused.
STS Channel #12 AIS Insert Status.
STS Channel #11 AIS Insert Status.
STS Channel #10 AIS Insert Status.
STS Channel #9 AIS Insert Status.
STS Channel #8 AIS Insert Status.
STS Channel #7 AIS Insert Status.
STS Channel #6 AIS Insert Status.
STS Channel #5 AIS Insert Status.
STS Channel #4 AIS Insert Status.
STS Channel #3 AIS Insert Status.
STS Channel #2 AIS Insert Status.
STS Channel #1 AIS Insert Status.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 169. AIS Insert Status Register, STS-12 Channel #4 (RO)
Address
(Hex)
Bit
Name
2C08
15:12
11
10
9
8
7
6
5
4
3
2
1
0
—
AIS_INSERT11
AIS_INSERT10
AIS_INSERT9
AIS_INSERT8
AIS_INSERT7
AIS_INSERT6
AIS_INSERT5
AIS_INSERT4
AIS_INSERT3
AIS_INSERT2
AIS_INSERT1
AIS_INSERT0
Agere Systems Inc.
Description
Unused.
STS Channel #12 AIS Insert Status.
STS Channel #11 AIS Insert Status.
STS Channel #10 AIS Insert Status.
STS Channel #9 AIS Insert Status.
STS Channel #8 AIS Insert Status.
STS Channel #7 AIS Insert Status.
STS Channel #6 AIS Insert Status.
STS Channel #5 AIS Insert Status.
STS Channel #4 AIS Insert Status.
STS Channel #3 AIS Insert Status.
STS Channel #2 AIS Insert Status.
STS Channel #1 AIS Insert Status.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
141
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 170. Transmit Add STS-48 Channel Alarm (W1C)
Address
(Hex)
Bit
Name
2C09
15
—
14
B1_ERROR_4
13
OOF_4
11
—
10
B1_ERROR_3
OOF_3
7
—
6
B1_ERROR_2
OOF_2
3
—
2
B1_ERROR_1
0
142
0
BIP-8 Error STS-12 Channel 4—NSA.
0
0
Unused. May write ones on clear (W1C) if
desired.
0
BIP-8 Error STS-12 Channel 3—NSA.
0
0
Out-of-Frame Alarm STS-12 Channel 3—SA.
0
Unused. May write ones on clear (W1C) if
desired.
0
BIP-8 Error STS-12 Channel 2—NSA.
0
0
Out-of-Frame Alarm STS-12 Channel 2—SA.
0
Unused. May write ones on clear (W1C) if
desired.
0
BIP-8 Error STS-12 Channel 1—NSA.
0
ADD12_BUFFER_OVRFLW_1 Synchronization Buffer Overflow/Underflow
STS-12 Channel 1—NSA.
OOF_1
0
Out-of-Frame Alarm STS-12 Channel 4—SA.
ADD12_BUFFER_OVRFLW_2 Synchronization Buffer Overflow/Underflow
STS-12 Channel 2—NSA.
4
1
Unused. May write ones on clear (W1C) if
desired.
ADD12_BUFFER_OVRFLW_3 Synchronization Buffer Overflow/Underflow
STS-12 Channel 3—NSA.
8
5
Reset
ADD12_BUFFER_OVRFLW_4 Synchronization Buffer Overflow/Underflow
STS-12 Channel 4—NSA.
12
9
Description
Out-of-Frame Alarm STS-12 Channel 1—SA.
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 171. Transmit Add STS-48 Channel Alarm Mask (R/W)
Address
(Hex)
Bit
Name
Description
Reset
2C0A
15
14
—
B1_ERROR_4_M
0
0
13
ADD12_BUFFER_
OVRFLW_4_M
12
OOF_4_M
11
10
—
B1_ERROR_3_M
9
ADD12_BUFFER_
OVRFLW_3_M
8
OOF_3_M
7
6
—
B1_ERROR_2_M
5
ADD12_BUFFER_
OVRFLW_2_M
4
OOF_2_M
3
2
—
B1_ERROR_1_M
1
ADD12_BUFFER_
OVRFLW_1_M
0
OOF_1_M
Unused. Program to zero.
BIP-8 Error STS-12 Channel 4—NSA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Synchronization Buffer Overflow/Underflow STS-12
Channel 4—NSA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Out-of-Frame Alarm STS-12 Channel 4—SA interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Unused. Program to zero.
BIP-8 Error STS-12 Channel 3—NSA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Synchronization Buffer Overflow/Underflow STS-12
Channel 3—NSA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Out-of-Frame Alarm STS-12 Channel 3—SA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Unused. Program to zero.
BIP-8 Error STS-12 Channel 2—NSA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Synchronization Buffer Overflow/Underflow STS-12
Channel 2—NSA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Out-of-Frame Alarm STS-12 Channel 2—SA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Unused. Program to zero.
BIP-8 Error STS-12 Channel 1—NSA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Synchronization Buffer Overflow/Underflow STS-12
Channel 1—NSA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Out-of-Frame Alarm STS-12 Channel 1—SA Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Agere Systems Inc.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
143
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Path Overhead (POH) Registers
Registers pertaining to the path are organized as shown in Figure 11. As can be seen, some functions are performed at the STS-1 level. Registers for these functions are arranged as a group of 12 and then grouped with functions that are performed at the STS-12 level. This group is repeated 16 times in the memory map. Functions that
are performed at the STS-48 level are also grouped together.
In the diagram, the numbers to the top left of each box represent the base address of registers in the first occurrence of that block of registers. The numbers to the bottom right represent the offset to the next occurrence of that
block of registers. Note that register offsets refer to SONET number, not interleave order (i.e., STS-1 number two is
one offset from STS-1 number 1).
For example, to find the base address of the STS-1 level registers for STS-1 number 77, take 0x3010, add six
times 0x0100 (since STS-1 number 77 is in the seventh STS-12), and then add 4 times 0x0010 (since STS-1 number 77 is the fifth STS-1 in the STS-12), and the result is 0x3650.
0X4000
CHIP (STS-192) LEVEL REGISTERS
0X4400
4
STS-48 LEVEL REGISTERS
+0X0100
0X3000
16
STS-12 LEVEL REGISTERS
0X3010
STS-1 LEVEL REGISTERS
12
+0X0010
+0X0100
5-9097(F)r.1
Figure 11. Path Register Structure
144
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
STS-12, STS-1 Level POH Registers
■
Base address: 0x3000
■
STS-12 channel offset: 0x0100
■
STS-1 channel offset: 0x0010
Table 172. STS-12 Pointer Processor Provisioning, STS-1 #1 to STS-1 #12 (R/W)
Address
(Hex)
Bit
Name
3000
15:4
5
—
AUTO_AIS_DIS
Description
Unused. Program to zero.
Disable Automatic AIS Insertion.
Reset
0
0
Note: It is recommended that automatic AIS insertion remain enabled unless in pointer generator bypass mode.
4
INT_SONET_SDH
3:0
INT_INC_BIN
1 = Disable automatic AIS insertion.
0 = Enable automatic AIS insertion.
Pointer Increment/Decrement Standard.
1 = SONET. The 8 of 10 rule will be used. Eight of
the ten I and D bits must be correct for the pointer to
be considered an increment or decrement.
0 = SDH. The 3 of 5 rule is used. Three of the five I
and D bits must be correct for the pointer to be considered an increment or decrement.
STS-1 Increment/Decrement Binning Select.
0
1
Table 173. STS-12 Pointer Processor Maintenance, STS-1 #1 to STS-1 #12 (R/W)
Address
(Hex)
Bit
Name
3001
15:12
11
10:0
—
PP_CH_SW_AIS_INS_12
PP_CH_SW_AIS_INS_11—
PP_CH_SW_AIS_INS_1
Description
Unused. Program to zero.
STS-1 #12 AIS Insert.
STS-1 #11 to STS-1 #1 AIS Insert.
Reset
0
0
0
Table 174. STS-12 Pointer Interpreter PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO)
Address
(Hex)
Bit
Name
3002
15:11
10:0
—
PP_CH_INT_INC_PM
Agere Systems Inc.
Description
Unused.
Last Second Increments on Selected
Pointer Interpreter.
Reset
0
0
145
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 175. STS-12 Pointer Interpreter PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO)
Address
(Hex)
Bit
Name
3003
15:11
10:0
—
PP_CH_INT_DEC_PM
Description
Reset
Unused.
Last Second Decrements on Selected
Pointer Interpreter.
0
0
Table 176. STS-12 Pointer Generator PM, Last Second Increments, STS-1 #1 to STS-1 #12 (RO)
Address
(Hex)
Bit
Name
3004
15:11
10:0
—
PP_CH_GEN_INC_PM
Description
Reset
Unused.
Last Second Increments on Selected
Pointer Generator.
0
0
Table 177. STS-12 Pointer Generator PM, Last Second Decrements, STS-1 #1 to STS-1 #12 (RO)
Address
(Hex)
Bit
Name
3005
15:11
10:0
—
PP_CH_GEN_DEC_PM
Description
Reset
Unused.
Last Second Decrements on Selected
Pointer Generator.
0
0
Table 178. STS-1 #1 Path Overhead Provisioning (R/W)
Address
(Hex)
Bit
Name
3010
15:8
7:2
1
PROV_STS1_EXP_C2
—
CNT_BLK_ERRS
0
PDI_EN
Description
Reset
Expected C2 Byte.
Unused. Program to zero.
Count B3 BIP-8 Errors, and G1 RDI-P and
REI-P Errors.
1 = Block.
0 = Bit.
Enable Payload Defect Indicator.
0
0
0
0
Table 179. STS-1 #1 Path Overhead Maintenance (R/W)
Address
(Hex)
Bit
Name
Description
Reset
3011
15:4
3
2:0
—
SD_INSERT
SF_THRESH_SEL
Unused. Program to zero.
Insert Signal Degrade.
Signal Fail Threshold Select (selects 1 of 8
SF detect/clear register sets at STS-192
level).
0
0
0
146
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 180. STS-1 #1 Path Overhead Status (RO)
Address
(Hex)
Bit
Name
3012
15:11
10:8
—
RCV_RDI_CODE
7:0
RCV_C2_BYTE
Description
Unused.
Received RDI-P Code (currently validated
(raw) RDI-P; may differ from PM register).
Received C2 Byte.
Reset
0
0
0
Table 181. STS-1 #1 Alarm Interrupt Status (W1C)
Address
(Hex)
Bit
Name
3013
15:7
—
6
5
4
3
2
1
0
ES_OVRUN
SIG_FAIL
RDI_P
PLM_P
UNEQ_P
AIS_P
LOP_P
Description
Unused. May write ones on clear (W1C) if
desired.
Elastic Store Overrun/Underrun.
Signal Fail.
Remote Defect Indicator.
Payload Label Mismatch.
Unequipped Received.
AIS Received.
Loss of Pointer.
Reset
0
0
0
0
0
0
0
0
Table 182. STS-1 #1 Alarm Interrupt Status Mask (R/W)
Address
(Hex)
Bit
Name
3014
15:7
6
—
ES_OVRUN_M
5
SIG_FAIL_M
4
RDI_P_M
3
PLM_P_M
2
UNEQ_P_M
1
AIS_P_M
0
LOP_P_M
Agere Systems Inc.
Description
Unused. Program to zero.
Elastic Store Overrun/Underrun Interrupt
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Signal Fail Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Remote Defect Indicator Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Payload Label Mismatch Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Unequipped Received Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
AIS Received Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Loss of Pointer Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
0
0
0
147
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 183. STS-1 #1 Alarm Persistency (RO)
Address
(Hex)
Bit
Name
3015
15:5
4
3
2
1
0
—
RDI_P_PERS
PLM_P_PERS
UNEQ_P_PERS
AIS_P_PERS
LOP_P_PERS
Description
Reset
Unused.
Remote Defect Indicator Persistent.
Payload Label Mismatch Persistent.
Unequipped Received Persistent.
AIS Received Persistent.
Loss of Pointer Persistent.
0
0
0
0
0
0
Table 184. STS-1 #1 PM Last Second Indicators (RO)
Address
(Hex)
Bit
Name
3016
15:7
6
5
4
3
2
1
0
—
RDI_ONE_BIT
ERDI_PYLD
ERDI_CONN
ERDI_SRVR
UNEQ
AIS
LOP
Description
Unused.
1-bit RDI-P Defect.
ERDI-P Payload Defect.
ERDI-P Connectivity Defect.
ERDI-P Server Defect.
UNEQ-P Received.
AIS-P Received.
Loss of Pointer.
Reset
0
0
0
0
0
0
0
0
Table 185. STS-1 #1 Last Second CV-P Count (RO)
Address
(Hex)
Bit
Name
3017
15:0
PM_STS1_CVP_CNT
Description
CV-P Count.
Reset
0
Table 186. STS-1 #1 Last Second REI-P Count (RO)
Address
(Hex)
Bit
Name
3018
15:0
PM_STS1_REIP_CNT
148
Description
REI-P Count.
Reset
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
STS-192 Level POH Registers
■
Base address: 0x4000
Table 187. Path Overhead (POH) Interrupt Status (RO)
Address
(Hex)
Bit
Name
4000
15
14
13
12
11:0
STS48_CH4_ALARMS4
STS48_CH4_ALARMS3
STS48_CH4_ALARMS2
STS48_CH4_ALARMS1
STS1_CH_ALARMS
Description
STS-48 Channel 4 Path Alarms.
STS-48 Channel 3 Path Alarms.
STS-48 Channel 2 Path Alarms.
STS-48 Channel 1 Path Alarms.
STS-1 Channel Alarms (points to registers
consolidating alarms per STS-1).
Reset
0
0
0
0
0
Table 188. Path Overhead (POH) Interrupt Status Mask (R/W)
Address
(Hex)
Bit
4001
15
14
13
12
11:0
Agere Systems Inc.
Name
Description
STS48_CH4_ALARMS4_M STS-48 Channel 4 Path Alarms Interrupt
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS48_CH4_ALARMS3_M STS-48 Channel 3 Path Alarms Interrupt
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS48_CH4_ALARMS2_M STS-48 Channel 2 Path Alarms Interrupt
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS48_CH4_ALARMS1_M STS-48 Channel 1 Path Alarms Interrupt
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS1_CH_ALARMS_M
STS-1 Channel Alarms (points to registers
consolidating alarms per STS-1) Interrupt
Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
149
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 189. STS-1 Signal Fail Detect Threshold, Window Size Select 0 (R/W)
Address
(Hex)
Bit
Name
4002
15:14
SF_STS1_DET_WIN_SEL_0
13:9
8:0
—
SF_STS1_DET_THRESH_0
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Unused. Program to zero.
Detect Threshold.
1
0
CF
Table 190. STS-1 Signal Fail Clear Threshold, Window Size Select 0 (R/W)
Address
(Hex)
Bit
Name
4003
15:14
SF_STS1_CLR_WIN_SEL_0
13:9
8:0
—
SF_STS1_CLR_THRESH_0
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Unused. Program to zero.
Clear Threshold.
2
0
113
Table 191. STS-1 Signal Fail Detect Threshold, Window Size Select 1 (R/W)
Address
(Hex)
Bit
Name
4004
15:14
SF_STS1_DET_WIN_SEL_1
13:9
8:0
—
SF_STS1_DET_THRESH_1
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Unused. Program to zero.
Detect Threshold.
2
0
DE
Table 192. STS-1 Signal Fail Clear Threshold, Window Size Select 1 (R/W)
Address
(Hex)
Bit
Name
4005
15:14
SF_STS1_CLR_WIN_SEL_1
13:9
8:0
—
SF_STS1_CLR_THRESH_1
150
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Unused. Program to zero.
Clear Threshold.
3
0
115
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 193. STS-Nc Signal Fail Detect Threshold, Window Size Select 2 (R/W)
Address
(Hex)
Bit
Name
4006
15:14
SF_STSNC_DET_WIN_SEL_2
13:0
SF_STS1_DET_THRESH_2
Description
Window Size Select (chooses one of four
SF window size registers).
Detect Threshold.
Reset
1
233
Table 194. STS-Nc Signal Fail Clear Threshold, Window Size Select 2 (R/W)
Address
(Hex)
Bit
Name
4007
15:14
SF_STSNC_CLR_WIN_SEL_2
13:0
SF_STS1_CLR_THRESH_2
Description
Window Size Select (chooses one of four
SF window size registers).
Clear Threshold.
Reset
2
30B
Table 195. STS-Nc Signal Fail Detect Threshold, Window Size Select 3 (R/W)
Address
(Hex)
Bit
Name
4008
15:14
SF_STSNC_DET_WIN_SEL_3
13:0
SF_STS1_DET_THRESH_3
Description
Window Size Select (chooses one of four
SF window size registers).
Detect Threshold.
Reset
2
2B2
Table 196. STS-Nc Signal Fail Clear Threshold, Window Size Select 3 (R/W)
Address
(Hex)
Bit
Name
4009
15:14
SF_STSNC_CLR_WIN_SEL_3
13:0
SF_STS1_CLR_THRESH_3
Agere Systems Inc.
Description
Window Size Select (chooses one of four
SF window size registers).
Clear Threshold.
Reset
3
31B
151
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 197. STS-Nc Signal Fail Detect Threshold, Window Size Select 4 (R/W)
Address
(Hex)
Bit
Name
400A
15:14
SF_STSNC_DET_WIN_SEL_4
13:0
SF_STS1_DET_THRESH_4
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Detect Threshold.
1
3A3
Table 198. STS-Nc Signal Fail Clear Threshold, Window Size Select 4 (R/W)
Address
(Hex)
Bit
Name
400B
15:14
SF_STSNC_CLR_WIN_SEL_4
13:0
SF_STS1_CLR_THRESH_4
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Clear Threshold.
2
5D8
Table 199. STS-Nc Signal Fail Detect Threshold, Window Size Select 5 (R/W)
Address
(Hex)
Bit
Name
400C
15:14
SF_STSNC_DET_WIN_SEL_5
13:0
SF_STS1_DET_THRESH_5
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Detect Threshold.
2
55E
Table 200. STS-Nc Signal Fail Clear Threshold, Window Size Select 5 (R/W)
Address
(Hex)
Bit
Name
400D
15:14
SF_STSNC_CLR_WIN_SEL_5
13:0
SF_STS1_CLR_THRESH_5
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Clear Threshold.
3
618
Table 201. STS-Nc Signal Fail Detect Threshold, Window Size Select 6 (R/W)
Address
(Hex)
Bit
Name
400E
15:14
SF_STSNC_DET_WIN_SEL_6
13:0
SF_STS1_DET_THRESH_6
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Detect Threshold.
1
51D
Table 202. STS-Nc Signal Fail Clear Threshold, Window Size Select 6 (R/W)
Address
(Hex)
Bit
Name
400F
15:14
SF_STSNC_CLR_WIN_SEL_6
13:0
SF_STS1_CLR_THRESH_6
152
Description
Reset
Window Size Select (chooses one of four
SF window size registers).
Clear Threshold.
2
B08
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 203. STS-Nc Signal Fail Detect Threshold, Window Size Select 7 (R/W)
Address
(Hex)
Bit
Name
Description
Reset
4010
15:14
SF_STSNC_DET_WIN_SEL_7
2
13:0
SF_STS1_DET_THRESH_7
Window Size Select (chooses one of four SF
window size registers).
Detect Threshold.
A62
Table 204. STS-Nc Signal Fail Clear Threshold, Window Size Select 7 (R/W)
Address
(Hex)
Bit
Name
Description
Reset
4011
15:14
SF_STSNC_CLR_WIN_SEL_7
3
13:0
SF_STS1_CLR_THRESH_7
Window Size Select (chooses one of four SF
window size registers).
Clear Threshold.
BFC
Description
Reset
Table 205. Signal Fail Window Size 0 (R/W)
Address
(Hex)
Bit
Name
4012
15:0
SF_WIN_SIZE_0
Signal Fail Window Size (in 0.5 ms increments).
A
Table 206. Signal Fail Window Size 1 (R/W)
Address
(Hex)
Bit
Name
4013
15:0
SF_WIN_SIZE_1
Description
Signal Fail Window Size (in 0.5 ms increments).
Reset
64
Table 207. Signal Fail Window Size 2 (R/W)
Address
(Hex)
Bit
Name
4014
15:0
SF_WIN_SIZE_2
Description
Signal Fail Window Size (in 0.5 ms increments).
Reset
3E8
Table 208. Signal Fail Window Size 3 (R/W)
Address
(Hex)
Bit
Name
4015
15:0
SF_WIN_SIZE_3
Agere Systems Inc.
Description
Signal Fail Window Size (in 0.5 ms increments).
Reset
2710
153
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
STS-192 Level Path Trace Registers
■
Base address: 0x4100
The operation of the path trace registers is identical to the operation of the section trace registers. Refer to the section trace registers for a description on how to use the path trace registers.
Table 209. Path Trace Access Control (R/W)
Address
(Hex)
Bit
Name
4100
15:4
3:2
—
CH_SEL
1
BUF_MSG_SEL
0
BUF_RNW
Description
Reset
Unused. Program to zero.
STS-48 Channel Select for J1.
3 = Channel 4.
2 = Channel 3.
1 = Channel 2.
0 = Channel 1.
J1 Buffer Message Type Select.
1 = Compare value.
0 = Received message.
J1 Buffer Access Mode.
1 = Write.
0 = Read.
0
0
0
0
Table 210. Path Trace Access Complete Status (W1C)
Address
(Hex)
Bit
Name
4101
15:1
—
0
J1_AXS_DONE
Description
Reset
Unused. May write ones on clear (W1C) if
desired.
J1 Access Done.
0
0
Table 211. Path Trace Access Start
Address
(Hex)
Bit
Name
4102
15:1
—
0
J1_AXS_START
Description
Reset
Unused. May write ones on clear (W1C) if
desired.
Begin J1 Access.
0
0
Table 212. Path Trace Buffer Word #1—Word #32
Address
(Hex)
Bit
Name
4110—412F
15:0
J1_UP_BUFFERn
154
Description
Path Trace Bytes.
Reset
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
STS-48 Level POH Registers
■
Base address: 0x4400
■
STS-48 channel offset: 0x0100
Table 213. STS-1 Channel Interrupt Status, STS-1 #1 to STS-1 #16 (RO)
Address
(Hex)
Bit
Name
4400
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CH_ISR_BIT15
CH_ISR_BIT14
CH_ISR_BIT13
CH_ISR_BIT12
CH_ISR_BIT11
CH_ISR_BIT10
CH_ISR_BIT9
CH_ISR_BIT8
CH_ISR_BIT7
CH_ISR_BIT6
CH_ISR_BIT5
CH_ISR_BIT4
CH_ISR_BIT3
CH_ISR_BIT2
CH_ISR_BIT1
CH_ISR_BIT0
Description
STS-1 #16 Interrupt Alarm.
STS-1 #15 Interrupt Alarm.
STS-1 #14 Interrupt Alarm.
STS-1 #13 Interrupt Alarm.
STS-1 #12 Interrupt Alarm.
STS-1 #11 Interrupt Alarm.
STS-1 #10 Interrupt Alarm.
STS-1 #9 Interrupt Alarm.
STS-1 #8 Interrupt Alarm.
STS-1 #7 Interrupt Alarm.
STS-1 #6 Interrupt Alarm.
STS-1 #5 Interrupt Alarm.
STS-1 #4 Interrupt Alarm.
STS-1 #3 Interrupt Alarm.
STS-1 #2 Interrupt Alarm.
STS-1 #1 Interrupt Alarm.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 214. STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (R/W)
Address
(Hex)
Bit
Name
4401
15
CH_ISR_BIT15_M
14
CH_ISR_BIT14_M
13
CH_ISR_BIT13_M
12
CH_ISR_BIT12_M
11
CH_ISR_BIT11_M
Agere Systems Inc.
Description
STS-1 #16 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #15 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #14 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #13 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #12 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
155
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 214. STS-1 Channel Interrupt Status Mask, STS-1 #1 to STS-1 #16 (R/W) (continued)
Address
(Hex)
Bit
Name
4401
10
CH_ISR_BIT10_M
9
CH_ISR_BIT9_M
8
CH_ISR_BIT8_M
7
CH_ISR_BIT7_M
6
CH_ISR_BIT6_M
5
CH_ISR_BIT5_M
4
CH_ISR_BIT4_M
3
CH_ISR_BIT3_M
2
CH_ISR_BIT2_M
1
CH_ISR_BIT1_M
0
CH_ISR_BIT0_M
156
Description
STS-1 #11 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #10 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #9 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #8 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #7 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #6 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #5 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #4 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #3 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #2 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #1 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 215. STS-1 Channel Interrupt Status, STS-1 #17 to STS-1 #32 (RO)
Address
(Hex)
Bit
Name
4402
15
CH_ISR_BIT15
STS-1 #32 Interrupt Alarm.
0
14
CH_ISR_BIT14
STS-1 #31 Interrupt Alarm.
0
13
CH_ISR_BIT13
STS-1 #30 Interrupt Alarm.
0
12
CH_ISR_BIT12
STS-1 #29 Interrupt Alarm.
0
11
CH_ISR_BIT11
STS-1 #28 Interrupt Alarm.
0
10
CH_ISR_BIT10
STS-1 #27 Interrupt Alarm.
0
9
CH_ISR_BIT9
STS-1 #26 Interrupt Alarm.
0
8
CH_ISR_BIT8
STS-1 #25 Interrupt Alarm.
0
7
CH_ISR_BIT7
STS-1 #24 Interrupt Alarm.
0
6
CH_ISR_BIT6
STS-1 #23 Interrupt Alarm.
0
5
CH_ISR_BIT5
STS-1 #22 Interrupt Alarm.
0
4
CH_ISR_BIT4
STS-1 #21 Interrupt Alarm.
0
3
CH_ISR_BIT3
STS-1 #20 Interrupt Alarm.
0
2
CH_ISR_BIT2
STS-1 #19 Interrupt Alarm.
0
1
CH_ISR_BIT1
STS-1 #18 Interrupt Alarm.
0
0
CH_ISR_BIT0
STS-1 #17 Interrupt Alarm.
0
Agere Systems Inc.
Description
Reset
157
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 216. STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (R/W)
Address
(Hex)
Bit
Name
4403
15
CH_ISR_BIT15_M
14
CH_ISR_BIT14_M
13
CH_ISR_BIT13_M
12
CH_ISR_BIT12_M
11
CH_ISR_BIT11_M
10
CH_ISR_BIT10_M
9
CH_ISR_BIT9_M
8
CH_ISR_BIT8_M
7
CH_ISR_BIT7_M
6
CH_ISR_BIT6_M
5
CH_ISR_BIT5_M
158
Description
STS-1 #32 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #31 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #30 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #29 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #28 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #27 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #26 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #25 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #24 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #23 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #22 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 216. STS-1 Channel Interrupt Status Mask, STS-1 #17 to STS-1 #32 (R/W) (continued)
Address
(Hex)
Bit
Name
4403
4
CH_ISR_BIT4_M
3
CH_ISR_BIT3_M
2
CH_ISR_BIT2_M
1
CH_ISR_BIT1_M
0
CH_ISR_BIT0_M
Description
STS-1 #21 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #20 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #19 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #18 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #17 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
Table 217. STS-1 Channel Interrupt Status, STS-1 #33 to STS-1 #48 (RO)
Address
(Hex)
Bit
Name
4404
15
CH_ISR_BIT15
Description
Reset
STS-1 #48 Interrupt Alarm.
0
14
CH_ISR_BIT14
STS-1 #47 Interrupt Alarm.
0
13
CH_ISR_BIT13
STS-1 #46 Interrupt Alarm.
0
12
CH_ISR_BIT12
STS-1 #45 Interrupt Alarm.
0
11
CH_ISR_BIT11
STS-1 #44 Interrupt Alarm.
0
10
CH_ISR_BIT10
STS-1 #43 Interrupt Alarm.
0
9
CH_ISR_BIT9
STS-1 #42 Interrupt Alarm.
0
8
CH_ISR_BIT8
STS-1 #41 Interrupt Alarm.
0
7
CH_ISR_BIT7
STS-1 #40 Interrupt Alarm.
0
6
CH_ISR_BIT6
STS-1 #39 Interrupt Alarm.
0
5
CH_ISR_BIT5
STS-1 #38 Interrupt Alarm.
0
4
CH_ISR_BIT4
STS-1 #37 Interrupt Alarm.
0
3
CH_ISR_BIT3
STS-1 #36 Interrupt Alarm.
0
2
CH_ISR_BIT2
STS-1 #35 Interrupt Alarm.
0
1
CH_ISR_BIT1
STS-1 #34 Interrupt Alarm.
0
0
CH_ISR_BIT0
STS-1 #33 Interrupt Alarm.
0
Agere Systems Inc.
159
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 218. STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (R/W)
Address
(Hex)
Bit
Name
4405
15
CH_ISR_BIT15_M
14
CH_ISR_BIT14_M
13
CH_ISR_BIT13_M
12
CH_ISR_BIT12_M
11
CH_ISR_BIT11_M
10
CH_ISR_BIT10_M
9
CH_ISR_BIT9_M
8
CH_ISR_BIT8_M
7
CH_ISR_BIT7_M
6
CH_ISR_BIT6_M
5
CH_ISR_BIT5_M
4
CH_ISR_BIT4_M
3
CH_ISR_BIT3_M
2
CH_ISR_BIT2_M
160
Description
STS-1 #48 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #47 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #46 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #45 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #44 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #43 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #42 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #41 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #40 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #39 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #38 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #37 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #36 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #35 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 218. STS-1 Channel Interrupt Status Mask, STS-1 #33 to STS-1 #48 (R/W) (continued)
Address
(Hex)
Bit
Name
4405
1
CH_ISR_BIT1_M
0
CH_ISR_BIT0_M
Description
STS-1 #34 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
STS-1 #33 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Reset
0
0
Table 219. STS-48 Channel Path Trace Control (R/W)
Address
(Hex)
Bit
Name
4406
15:10
9
—
MODE_SEL
8
TYPE_SEL
7:6
5:0
—
STS48_CH_J1_STS_SEL
Description
Unused. Program to zero.
J1 Message Mode Select.
1 = Validated mode.
0 = Provisioned mode.
J1 Message Type Select.
1 = SDH.
0 = SONET.
Unused. Program to zero.
STS-1 # Select for J1 Accumulation (1—48;
other values disable the feature).
Reset
0
0
0
0
0
Table 220. S/W Concatenation Map STS-1 #1 to STS-1 #12 (R/W)
Address
(Hex)
Bit
Name
4407
15:12
11
10:0
—
SW_CONC_MAP_STS12
SW_CONC_MAP_STS11—
SW_CONC_MAP_STS1
Description
Unused. Program to zero.
STS-1 #12 Concatenation Map Bit.
STS-1 #11 to STS-1 #1 Concatenation Map
Bits.
Reset
0
0
0
Table 221. S/W Concatenation Map STS-1 #13 to STS-1 #24 (R/W)
Address
(Hex)
Bit
Name
4408
15:12
11
10:0
—
SW_CONC_MAP_STS24
SW_CONC_MAP_STS23—
SW_CONC_MAP_STS13
Agere Systems Inc.
Description
Unused. Program to zero.
STS-1 #24 Concatenation Map Bit.
STS-1 #23 to STS-1 #13 Concatenation Map
Bits.
Reset
0
0
0
161
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 222. S/W Concatenation Map STS-1 #25 to STS-1 #36 (R/W)
Address
(Hex)
Bit
Name
Description
Reset
4409
15:12
11
10:0
—
SW_CONC_MAP_STS36
SW_CONC_MAP_STS35—
SW_CONC_MAP_STS25
Unused. Program to zero.
STS-1 #36 Concatenation Map Bit.
STS-1 #35 to STS-1 #25 Concatenation Map
Bits.
0
0
0
Table 223. S/W Concatenation Map STS-1 #37 to STS-1 #48 (R/W)
Address
(Hex)
Bit
Name
Description
Reset
440A
15:12
11
10:0
—
SW_CONC_MAP_STS48
SW_CONC_MAP_STS47—
SW_CONC_MAP_STS37
Unused. Program to zero.
STS-1 #48 Concatenation Map Bit.
STS-1 #47 to STS-1 #37 Concatenation Map
Bits.
0
0
0
Table 224. S/W Concatenation Mask STS-1 #1 to STS-1 #12 (R/W)
Address
(Hex)
Bit
Name
Description
Reset
440B
15:12
11
10:0
—
SW_CONC_MASK_STS12
SW_CONC_MASK_STS11—
SW_CONC_MASK_STS1
Unused. Program to zero.
STS-1 #12 Concatenation Mask Bit.
STS-1 #11 to STS-1 #1 Concatenation Mask
Bits.
0
0
0
Table 225. S/W Concatenation Mask STS-1 #13 to STS-1 #24 (R/W)
Address
(Hex)
Bit
Name
440C
15:12
11
10:0
—
SW_CONC_MASK_STS24
SW_CONC_MASK_STS23—
SW_CONC_MASK_STS13
Description
Reset
Unused. Program to zero.
STS-1 #24 Concatenation Mask Bit.
STS-1 #23 to STS-1 #13 Concatenation
Mask Bits.
0
0
0
Table 226. S/W Concatenation Mask STS-1 #25 to STS-1 #36 (R/W)
Address
(Hex)
Bit
Name
440D
15:12
11
10:0
—
SW_CONC_MASK_STS36
SW_CONC_MASK_STS35—
SW_CONC_MASK_STS25
162
Description
Reset
Unused. Program to zero.
STS-1 #36 Concatenation Mask Bit.
STS-1 #35 to STS-1 #25 Concatenation
Mask Bits.
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 227. S/W Concatenation Mask STS-1 #37 to STS-1 #48 (R/W)
Address
(Hex)
Bit
Name
440E
15:12
11
10:0
—
SW_CONC_MASK_STS48
SW_CONC_MASK_STS47—
SW_CONC_MASK_STS37
Description
Unused. Program to zero.
STS-1 #48 Concatenation Mask Bit.
STS-1 #47 to STS-1 #37 Concatenation
Mask Bits.
Reset
0
0
0
Table 228. Received Concatenation Map STS-1 #1 to STS-1 #12 (RO)
Address
(Hex)
Bit
Name
440F
15:12
11
—
RECD_CONC_MAP_STS12
10:0
Description
Unused. Program to zero.
STS-1 #12 Received Concatenation Map
Bit.
RECD_CONC_MAP_STS11— STS-1 #11 to STS-1 #1 Received ConcateRECD_CONC_MAP_STS1 nation Map Bits.
Reset
0
0
0
Table 229. Received Concatenation Map STS-1 #13 to STS-1 #24 (RO)
Address
(Hex)
Bit
Name
4410
15:12
11
—
RECD_CONC_MAP_STS24
10:0
Description
Unused. Program to zero.
STS-1 #24 Received Concatenation Map
Bit.
RECD_CONC_MAP_STS23— STS-1 #23 to STS-1 #13 Received ConcateRECD_CONC_MAP_STS13 nation Map Bits.
Reset
0
0
0
Table 230. Received Concatenation Map STS-1 #25 to STS-1 #36 (RO)
Address
(Hex)
Bit
Name
4411
15:12
11
—
RECD_CONC_MAP_STS36
10:0
Description
Unused. Program to zero.
STS-1 #36 Received Concatenation Map
Bit.
RECD_CONC_MAP_STS35— STS-1 #35 to STS-1 #25 Received ConcateRECD_CONC_MAP_STS25 nation Map Bits.
Reset
0
0
0
Table 231. Received Concatenation Map STS-1 #37 to STS-1 #48 (RO)
Address
(Hex)
Bit
Name
4412
15:12
11
—
RECD_CONC_MAP_STS48
10:0
Agere Systems Inc.
Description
Unused. Program to zero.
STS-1 #48 Received Concatenation Map
Bit.
RECD_CONC_MAP_STS47— STS-1 #47 to STS-1 #37 Received ConcateRECD_CONC_MAP_STS37 nation Map Bits.
Reset
0
0
0
163
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 232. STS-48 Channel Path Alarms 1 (W1C)
Address
(Hex)
Bit
Name
Description
Reset
4413
15:12
—
0
11
CONC_MAP_MMCH_4
10
CONC_MAP_MMCH_3
9
CONC_MAP_MMCH_2
8
CONC_MAP_MMCH_1
7
UNSUPP_CONC_MAP_4
6
UNSUPP_CONC_MAP_3
5
UNSUPP_CONC_MAP_2
4
UNSUPP_CONC_MAP_1
3
—
2
1
0
J1_BUF_PAR_ERR
J1_NEW_MSG
J1_MSG_MMCH
Unused. May write ones on clear (W1C) if
desired.
Concatenation Map Mismatch in
STS-1 #37—STS-1 #48.
Concatenation Map Mismatch in
STS-1 #25—STS-1 #36.
Concatenation Map Mismatch in
STS-1 #13—STS-1 #24.
Concatenation Map Mismatch in
STS-1 #1—STS-1 #12.
Unsupported Concatenation in STS-1 #37—
STS-1 #48.
Unsupported Concatenation in STS-1 #25—
STS-1 #36.
Unsupported Concatenation in STS-1 #13—
STS-1 #24.
Unsupported Concatenation in STS-1 #1—
STS-1 #12.
Unused. May write ones on clear (W1C) if
desired.
J1 Memory Parity Error.
J1 New Validated Message.
J1 Message Mismatch.
164
0
0
0
0
0
0
0
0
0
0
0
0
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Microprocessor Interface (continued)
Table 233. STS-48 Channel Path Alarms 1 Mask (W1C)
Address
(Hex)
Bit
Name
Description
Reset
4414
15:12
—
0
11
CONC_MAP_MMCH_4_M
10
CONC_MAP_MMCH_3_M
9
CONC_MAP_MMCH_2_M
8
CONC_MAP_MMCH_1_M
7
UNSUPP_CONC_MAP_4_M
6
UNSUPP_CONC_MAP_3_M
5
UNSUPP_CONC_MAP_2_M
4
UNSUPP_CONC_MAP_1_M
3
—
2
J1_BUF_PAR_ERR_M
1
J1_NEW_MSG_M
0
J1_MSG_MMCH_M
Unused. May write ones on clear (W1C) if
desired.
Concatenation Map Mismatch in
STS-1 #37—STS-1 #48 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Concatenation Map Mismatch in
STS-1 #25—STS-1 #36 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Concatenation Map Mismatch in
STS-1 #13—STS-1 #24 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Concatenation Map Mismatch in
STS-1 #1—STS-1 #12 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Unsupported Concatenation in STS-1 #37—
STS-1 #48 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Unsupported Concatenation in STS-1 #25—
STS-1 #36 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Unsupported Concatenation in STS-1 #13—
STS-1 #24 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Unsupported Concatenation in STS-1 #1—
STS-1 #12 Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Unused. May write ones on clear (W1C) if
desired.
J1 Memory Parity Error Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
J1 New Validated Message Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
J1 Message Mismatch Interrupt Mask.
1 = Enable interrupt.
0 = Mask interrupt.
Agere Systems Inc.
0
0
0
0
0
0
0
0
0
0
0
0
165
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These
are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of this device specification. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
Table 234. Absolute Maximum Ratings
Parameter
dc Supply Voltage:
3.3 V Power
2.5 V Power
Analog Power
Storage Temperature
Maximum Power Dissipation:
3.3 V Power Supply
2.5 V Power Supply
Symbol
Min
Typ
Max
Unit
VDD
VDD2
VDDA
Tstg
–0.5
–0.5
–0.5
–65
3.3
2.5
3.3
—
3.8
3.0
3.8
125
V
V
V
°C
PD3
PD2
—
—
—
—
6.71
3.5
W
W
1. The maximum power dissipation for the five analog power supply inputs is 350 mW (5 × 70 mW each). This total is included in PD3.
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere Systems Inc. employs a human-body
model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation.
ESD voltage thresholds are dependent on the circuit parameters used in the defined model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is
widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was
obtained by using these circuit parameters.
Device
Model
Voltage
TSOT0410G4
HBM
CDM (corner pins)
CDM (noncorner pins)
TBD
TBD
TBD
Recommended Operating Conditions
Table 235. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Junction Temperature Range
Ambient Operating Temperature Range
3.3 V Power Supply
2.5 V Power Supply
Analog Power Supply
TJ
TA
VDD
VDD2
VDDA
–40
–40
3.135
2.375
3.135
—
—
3.3
2.5
3.3
125
85
3.465
2.625
3.465
°C
°C
V
V
V
166
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Recommended Operating Conditions (continued)
■
The TSOT0410G4 is packaged in a 9-layer LBGA. The heat sink is not grounded in the TSOT0410G4.
■
The thermal resistance junction to case, θJC, of the 600-pin LBGA package is 0.4 °C/W.
■
The thermal resistance junction to ambient (to the nearest 0.5 °C/W), θJA, of the 600-pin LBGA package is given
in Table 236.
Table 236. Thermal Resistance—Junction to Ambient
Air Speed in Linear Feet per Minute (LFPM)
θJA (°C/W)
JEDEC Standard Natural Convection
0
200
500
800
9
8.5
6.5
6
5
Electrical Characteristics
Power Sequencing
The device power may be applied concurrently to both voltage level inputs. If power sequencing is used for other
devices on a board or in a system, it is a preferred that the highest voltage be applied first and removed last.
Low-Voltage Differential Signal (LVDS) Buffers
The LVDS buffers are compliant with the EIA-644 standard. The only exception to compliance with this standard is
associated with the input leakage current. The LVDS input buffers have an input leakage current of 300 µA maximum.
The LVDS buffers are also compliant to the IEEE 1596.3 standard. The only exception to compliance with this
standard is the input termination resistance. The LVDS input buffers have an input termination resistance of
80 Ω—135 Ω.
The LVDS outputs are hot-swap compatible, and can be connected to other vendor’s LVDS I/O buffers. The maximum input current for the Agere LVDS input buffers is 9 mA. Prolonged exposure to higher current levels will have
an impact on long-term reliability.
CML or open collector transmitters cannot be directly connected to the TSOT0410G4 LVDS inputs. This is not possible, since up to four LVDS inputs share one center tap line with one center tap pin. The 10 µm center tap line is
relatively long in the TSOT0410G4; therefore, resistances and capacitances cannot be ignored.
Unused LVDS inputs may be left unconnected. There are internal pull-up resistors (nominal 14 kΩ) that pull open
inputs to greater than 2.75 Vdc (the common mode range is 0 Vdc to 2.4 Vdc). A sense circuit becomes active for
input voltages above 2.75 Vdc and clamps the buffer output to a defined state. Open inputs will not oscillate for this
reason.
For board layout, LVDS traces should be run on controlled-impedance layers, and should be specified as 50 Ω
line-to-ground. The LVDS buffers support point-to-point connections. They are not intended for bused implementations.
Agere Systems Inc.
167
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Electrical Characteristics (continued)
LVDS DRIVER
LVDS RECEIVER
100 Ω
50 Ω
CENTER TAP
50 Ω
EXTERNAL
DEVICE PINS
5-8703(F)
Figure 12. LVDS Driver and Receiver and Associated Internal Components
DRIVER
INTERCONNECT
RECEIVER
VOA
A
AA
VIA
VOB
B
BB
VIB
VGPD
5-8704(F)
Figure 13. LVDS Driver and Receiver
CA
VOA
A
RLOAD
VOB
B
V
VOD = (VOA – VOB)
CB
5-8705(F)
Figure 14. LVDS Driver
168
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Electrical Characteristics (continued)
LVDS Receiver Buffer Capabilities
A disabled or unpowered LVDS receiver can withstand a driving LVDS transmitter over the full range of driver operating range, for an unlimited period of time, without being damaged. Table 237 illustrates LVDS driver dc data,
Table 238 the ac data, and Table 240 on page 170 the LVDS receiver data.
Note: VDD = 3.1 V—3.5 V, 0 °C—125 °C, slow-fast process.
Table 237. LVDS Driver dc Data
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1
Driver Output Voltage High,
VOA or VOB
VOH
RLOAD = 100 Ω ± 1%.
—
—
1.500
Driver Output Voltage Low,
VOA or VOB
VOL
RLOAD = 100 Ω ± 1%.
0.9251
—
—
V
VOD
RLOAD = 100 Ω ± 1%.
0.25
—
0.451
V
—
1.2751
V
Driver Output Differential Voltage VOD = (VOA – VOB)
(with external reference
resistor)
RLOAD = 100 Ω ± 1%,
1.1251
refer to Figure 14 on page 168.
V
Driver Output Offset Voltage
VOS = (VOA + VOB)/2
VOS
Output Impedance, Single-ended
RO
VCM = 1.0 V and 1.4 V.
40
50
60
Ω
RO Mismatch Between
A and B
∆" RO
VCM = 1.0 V and 1.4 V.
—
—
10
%
Change in ∆ VODBetween
0 and 1
∆ VOD
RLOAD = 100 Ω ± 1%.
—
—
25
mV
Change in ∆ VOSBetween
0 and 1
∆ VOS
RLOAD = 100 Ω ± 1%.
—
—
25
mV
ISA, ISB
Driver shorted to ground.
—
—
24
mA
ISAB
Driver shorted together.
—
—
12
mA
IXA, IXB
VDD = 0 V,
VPAD, VPADN = 0 V—3 V.
—
—
30
µA
Output Current
Output Current
Power-off Output Leakage
1. External reference, REF10 = 1.0 V ± 3%, REF14 = 1.4 V ± 3%.
Table 238. LVDS Driver ac Data
Parameter
Symbol
Conditions
Min
Max
Unit
VOD Fall Time, 80% to 20%
tFALL
100
200
ps
VOD Rise Time, 20% to 80%
tRISE
ZLOAD = 100 Ω ± 1%,
CPAD = 3.0 pF, CPADN = 3.0 pF.
ZLOAD = 100 Ω ± 1%,
CPAD = 3.0 pF, CPADN = 3.0 pF.
Any differential pair on package at 50%
point of the transition.
100
200
ps
—
50
ps
Differential Skew tpHLA – tpLHB
ortpHLB – tpLHA
Agere Systems Inc.
tSKEW1
169
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Electrical Characteristics (continued)
Table 239. LVDS Driver Reference Data
Parameter
REF10E, REF10L Voltage Range
REF14E, REF14L Voltage Range
Nominal Input Current—REF10 and
REF14 Reference Inputs
Conditions
Min
Typ
Max
Unit
—
—
—
0.95
1.35
—
1.0
1.4
10
1.05
1.45
—
V
V
µA
Table 240. LVDS Receiver Data
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Receiver input Voltage Range, VIA
or VIB (common mode voltage)
VI
VGPD< 925 mV dc—1 MHz.
0
1.2
2.4
V
Receiver Input Differential Threshold (differential mode voltage)
VIDTH
VGPD< 925 mV 400 MHz.
–100
—
100
mV
Receiver Input Differential
Hysteresis
VHYST
VIDTHH – VIDTHL.
—
—
—1
mV
Receiver Differential Input
Impedance
RIN
With built-in termination, center
tapped.
80
100
135
Ω
1. Buffer will not produce transition when input is open-circuited.
Table 241. Receive Payload Add Interface
Parameter
Conditions
Min
Typ
Max
Unit
Stream of Nontransitional 622 Mbits/s2
—
—
—
60
bits
—
—
100
ps
—
0.4
—
—
UIp-p
—
—
—
—
—
—
—
—
—
0.6
6
60
UIp-p
UIp-p
UIp-p
Input
Data1
Phase Change, Input Signal
Eye Opening4
Over a 200 ns time
interval.3
Jitter
Jitter Tolerance:
250 kHz
25 kHz
2 kHz
1. 622.08 Mbits/s scrambled data stream conforming to SONET STS-12 and SDH STM-4 data format using either a PN7 or PN9 sequence:
— PN7 characteristic is 1 + x6 + x7.
— PN9 characteristic is 1 + x4 + x9.
2. This sequence should not occur more than once per minute.
3. Translates to a frequency change of 500 ppm.
4. A unit interval for 622.08 Mbits/s data is 1.6075 ns.
170
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Electrical Characteristics (continued)
Table 242. Receive Payload Drop Interface
Parameter
Output Jitter, Generated
Conditions
Min
Typ
Max
Unit
250 kHz to 5 MHz.
—
—
0.25
UIp-p
Table 243. LVTTL 3.3 V Logic Interface Characteristics
Parameter
Input Leakage
Input Voltage:
Low
High
Output Voltage:
Low
High
Input Capacitance
Load Capacitance
Agere Systems Inc.
Symbol
Conditions
Min
Typ
Max
Unit
IL
—
—
—
1.0
µA
VILLVTTL
VIHLVTTL
—
—
GND
VDD – 1.0
—
—
1.0
VDD
V
V
VOLLVTTL
VOHLVTTL
CI
CL
–5.0 mA
5.0 mA
—
—
GND
VDD – 1.0
—
—
—
—
2.2
0.4
0.5
VDD
3.0
—
V
V
pF
pF
171
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics
Receive Data Interface
Receive STS-48/STS-192 Data
Figure 15 illustrates the timing for the receive STS-48/STS-192 data stream. Both the clock and data pins are
low-voltage differential signal (LVDS) input buffers. The expected clock rate is 622.08 MHz and the receive data is
clocked on the rising edge of the clock. In STS-48 mode, each channel uses one set of R_CLK_n and RD_n_[3:0]
data pins. In STS-192 mode, only R_CLK_1 is used, along with the 16 RD pins. The timing values for the diagram
are given in Table 244.
t1
P
R_CLK
N
t2
t3
N
RD
P
t4
P
R_CLKO
N
5-9085(F)r.1
Figure 15. Receive Data Timing
Table 244. Receive Data Timing
Symbol
t1
t2
t3
t4
172
Parameter
Clock Period
Data Setup Time Required
Data Hold Time Required
R_CLK to R_CLKO Rising Edge
R_CLK to R_CLKO Falling Edge
Min
Typ
Max
Unit
—
250
250
2.35
2.40
1608
—
—
—
—
—
—
—
5.54
5.61
ps
ps
ps
ns
ns
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Receive Transport Overhead Interface
Figure 16 illustrates the timing for the following receive data communication channel interfaces: local orderwire
(RLCLOW), express orderwire (REXPOW), section user channel (RSUSER), section data com (RSDCC), and line
data com (RLDCC).
Figure 16 is also appropriate to illustrate the timing for the transmit add section data com channel (TADCC and
TADCK). Table 258 on page 183 also references this figure.
t10
t11
DCC CLOCK PIN
t12
DCC DATA PIN
5-9087(F)
Figure 16. Receive Data Communication Channels Timing
Receive Local Orderwire
The receive local orderwire (RLCLOW) pin is timed using the rising edge of the receive orderwire clock
(ROW_CLK) pin. Sampling of the RLCLOW pin is intended to occur at the negative edge of ROW_CLK signal. The
frequency of ROWCK is 64 kHz with a duty cycle of 33%. The timing characteristics for these pins are given in
Table 245 on page 174.
Receive Section User
The receive section user (RSUSER) pin is timed using the rising edge of the receive orderwire clock (ROW_CLK)
pin. Sampling of the RSUSER pin is intended to occur at the negative edge of ROW_CLK signal. The timing characteristics for these pins are given in Table 245.
Agere Systems Inc.
173
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Receive Express Orderwire
The receive express orderwire (REXPOW) pin is timed using the rising edge of the receive orderwire clock
(ROW_CLK) pin. Sampling of the REXPOW pin is intended to occur at the negative edge of ROW_CLK signal. The
timing characteristics for these pins are given in Table 245.
Table 245. RLCLOW/RSUSER/REXPOW Timing
Symbol
t10
t11
t12
Parameter
Clock Period
Clock High Width
Clock to Data Delay
Min
Typ
Max
Unit
—
—
—
15.625
5.21
30
—
—
—
µs
µs
ns
Receive Section Data Com
The receive section data com (RSDCC) pin is timed using the rising edge of the receive section data com clock
(RSDCK) pin. Sampling of the RSDCC pin is intended to occur at the negative edge of RSD_CLK signal. The frequency of RSD_CLK is 192 kHz with a duty cycle of 33%. The timing characteristics for these pins are given in
Table 246. (See Figure 16 on page 173.)
Table 246. RSDCC Timing
Symbol
t10
t11
t12
Parameter
Clock Period
Clock High Width
Clock to Data Delay
Min
Typ
Max
Unit
—
—
—
5.208
1.736
30
—
—
—
µs
µs
ns
Receive Line Data Com
The receive line data com (RLDCC) pin is timed using the rising edge of the receive line data com clock
(RLD_CLK) pin. Sampling of the RLDCC pin is intended to occur at the negative edge of RLD_CLK signal. The frequency of RLD_CLK is 576 kHz with a duty cycle of roughly 50%. The timing characteristics for these pins are
given in Table 247. (See Figure 16 on page 173.)
Table 247. RLDCC Timing
Symbol
t10
t11
t12
174
Parameter
Clock Period
Clock High Width
Clock to Data Delay
Min
Typ
Max
Unit
—
—
—
1.736
0.823
30
—
—
—
µs
µs
ns
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Receive Overhead Serial Link
The ROHDAT_n_[1:0] pins transmit the complete transport overhead data for every received frame. The
ROHDAT_n_ [1:0] pins are timed using the rising edge of the ROH_CLK signal. Sampling of the ROHDAT_n_[1:0]
pins is intended to occur at the positive edge of the ROH_CLK signal.
Since 1296 overhead bytes are transmitted in 125 µs using a 2-bit interface, the average frequency of ROH_CLK
is 41.472 MHz. Internally, this clock is produced using a 155.52 MHz reference, which requires a divide-down factor of 3.75. This is accomplished by producing three 38.88 MHz clock cycles (long clocks), followed by one
51.84 MHz clock cycle (short clock).
The ROHFP pin indicates the frame position by toggling high during the most significant bit of the first A1 byte in
the data stream, as illustrated in Figure 17.
External logic that interfaces to ROHDAT should synchronize to each of the four channels independently using the
ROHFP_[1—4] signals.
Even in 10 Gbits/s mode, where RXCLK and ROHCLK are the same, the different delays on the signals in each
channel will create the potential for the metastability handlers to sample the channels, within ±1 clock cycles, of
each other. This is due to the possibility of the four channels being asynchronous.
The timing characteristics for the receive overhead serial pins are given in Table 248.
t15
t13
t14
t14
ROH_CLK[4—1]
t16
ROHDAT_[4—1]_[1:0]
E2...
A1 [7:6]
A1 [5:4]
A1 [3:2]
MSB
A1 [1:0]
A1 ...
LSB
t17
ROHFP_[4—1]
5-9088.e (F)
Figure 17. Receive Overhead Serial Timing
Table 248. Receive Overhead Serial Timing
Symbol
t13
t14
t15
t16
t17
Parameter
Clock Period (long clock)
Clock High Width
Clock Period (short clock)
Clock to Data Delay
Clock to Frame Pulse Delay
Agere Systems Inc.
Min
Typ
Max
Unit
—
12.8
—
0.9
0.6
25.6
12.9
19.2
—
—
—
13.3
—
8
7
ns
ns
ns
ns
ns
175
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Transmit Data Interface
Transmit STS-48/STS-192 Data
Figure 18 illustrates the timing for the transmit STS-48/STS-192 data stream. Both the clock and data pins are
driven with low-voltage differential signal buffers. T_CLK, being a 622.08 MHz input clock, starts at the transmit
add interface and clocks out the transmit data on the negative edge. The clock is then output on the T_CLKO_N
pin. The timing values for the diagram are given in Table 249.
t23
N
T_CLK
P
t18
N
T_CLKO
P
t19
t20
P
TD
N
t21
t22
5-9089(F)r.2
Figure 18. Transmit Data Timing
Table 249. Transmit Data Timing
Symbol
t18
t19
t20
t21
t22
t23
176
Parameter
Clock Period
Data Delay from Clock Edge
Data Uncertainty
Data Rise Time: 20%—80%
Data Fall Time: 80%—20%
Clock In to Clock Out
Min
Typ
Max
Unit
—
–50
—
100
100
2400
1608
—
250
200
200
200
4600
ps
ps
ps
ps
ps
ps
—
—
—
—
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Transmit Frame
Figure 19 illustrates the timing for the transmit frame (TFRM) signal, which is sampled using a high-speed,
low-voltage differential input buffer on the positive edge of T_CLK. The timing values are given in Table 250.
t24
P
T_CLK
N
t25
t26
N
TFRM
P
5-9090(F)
Figure 19. Transmit Frame Timing
Table 250. Transmit Frame Timing
Symbol
t24
t25
t26
Parameter
Clock Period
Data Setup Time Required
Data Hold Time Required
Agere Systems Inc.
Min
Typ
Max
Unit
—
300
300
1608
—
—
—
—
—
ps
ps
ps
177
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Transmit Transport Overhead Interface
Figure 20 illustrates the timing for the following transmit data communication channel interfaces: local orderwire
(TLCLOW), express orderwire (TEXPOW), section user channel (TSUSER), section data com (TSDCC), and line
data com (TLDCC).
t27
t28
DCC CLOCK PIN
t29
t30
DCC DATA PIN
5-9091(F)
Figure 20. Transmit Data Communication Channels Timing
Transmit Local Orderwire
The transmit local orderwire (TLCLOW) pin is clocked in using the rising edge of the transmit orderwire clock
(TOW_CLK) pin. Generation of the signal feeding the TLCLOW_n pin is intended to occur at the negative edge of
TOW_CLK signal. This clock signal, running at 64 kHz, is an output of the device. The timing characteristics for
these pins are given in Table 251.
Table 251. TLCLOW/TSUSER/TEXPOW Timing
Symbol
t27
t28
t29
t30
Parameter
Clock Period
Clock High Width
Data Setup Time Required
Data Hold Time Required
Min
Typ
Max
Unit
—
—
—
—
15.625
5.21
30
0
—
—
—
—
µs
µs
ns
ns
Transmit Section User
The transmit section user (TSUSER) pin is clocked in using the rising edge of the transmit orderwire clock
(TOW_CLK) pin. Generation of the signal feeding the TSUSER pin is intended to occur at the negative edge of
TOW_CLK signal. The timing characteristics for these pins are given in Table 251.
Transmit Express Orderwire
The transmit express orderwire (TEXPOW) pin is clocked in using the rising edge of the transmit orderwire clock
(TOW_CLK) pin. Generation of the signal feeding the TEXPOW pin is intended to occur at the negative edge of
TOW_CLK signal. The timing characteristics for these pins are given in Table 251.
178
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Transmit Section Data Com
The transmit section data com (TSDCC) pin is clocked in using the rising edge of the transmit section data com
clock (TSD_CLK) pin. Generation of the signal feeding the TSDCC pin is intended to occur at the negative edge of
TSD_CLK signal. This clock signal, running at 192 kHz, is an output of the device. The timing characteristics for
these pins are given in Table 252. (See Figure 20 on page 178.)
Table 252. TSDCC Timing
Symbol
t27
t28
t29
t30
Parameter
Clock Period
Clock High Width
Data Setup Time Required
Data Hold Time Required
Min
Typ
Max
Unit
—
—
—
—
5.208
1.736
30
0
—
—
—
—
µs
µs
ns
ns
Transmit Line Data Com
The transmit line data com (TLDCC) pin is clocked in using the rising edge of the transmit line data com clock
(TLD_CLK) pin. Generation of the signal feeding the TLDCC pin is intended to occur at the negative edge of
TLD_CLK signal. This clock signal, running at 576 kHz, is an output of the device. The timing characteristics for
these pins are given in Table 253. (See Figure 20 on page 178.)
Table 253. TLDCC Timing
Symbol
t27
t28
t29
t30
Parameter
Clock Period
Clock High Width
Data Setup Time Required
Data Hold Time Required
Agere Systems Inc.
Min
Typ
Max
Unit
—
—
—
—
1.736
0.823
30
0
—
—
—
—
µs
µs
ns
ns
179
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Transmit Overhead Serial Link
t33
t31
t32
t32
TOH_CLK
t35
t34
TOHDAT_[1:0]
... E2
A1 [7:6]
A1 [5:4]
A1 [3:2]
MSB
A1 [1:0]
A1...
LSB
t38
TOHFP
t37
t36
TOHEN
5-9092(F)
Figure 21. Transmit Overhead Serial Timing
The TOHDAT_n_[1:0] pins are optionally used to insert transport overhead bytes into the transmit data stream. The
TOHDAT_n_[1:0] pins are sampled internally using the rising edge of the TOH_CLK signal. Generation of the
TOHDAT signal is intended to occur at the positive edge of the TOH_CLK signal. This is possible since there is
zero hold time required on the TOHDAT inputs.
All of the TOH inputs/outputs are synchronous. Internal to TSOT, one TOH clock is generated and routed to all four
TOH_CLK_n pins. The TOH_CLK outputs are redundant copies, and only one has to be used if the TOH_DAT signals are brought to a common device, such as an FPGA. (There will not be any phase jumps between the outputs.)
The skew between the four TOH_CLK outputs is 1 ns maximum.
Since 1296 overhead bytes are received in 125 µs using a 2-bit interface, the average frequency of TOH_CLK is
41.472 MHz. Internally, this clock is produced using a 155.52 MHz reference, which requires a divide-down factor
of 3.75. This is accomplished by producing three 38.88 MHz clock cycles (long clocks), followed by one 51.84 MHz
clock cycle (short clock).
The TOHFP pin indicates the frame position by toggling high during the most significant bit of the first A1 byte in the
data stream, as illustrated in Figure 21. Only one TOHFP frame pulse signal is generated inside the TSOT0410G4,
and it is routed to all four TOHFP_n pins. The TOHFP_n signals are all aligned. Only one is needed if the
TOH_DAT signals are brought to a common device, such as an FPGA.
The timing characteristics for the transmit overhead serial pins are given in Table 254 on page 181.
TOHEN is only sampled on the rising edge of the clock during the least significant bit(s) of the byte; however, it can
be generated for the entire byte time (as indicated by dashed line waveforms in Figure 21).
180
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Table 254. Transmit Overhead Serial Timing
Symbol
Parameter
Min
Typ
Max
Unit
—
25.7
—
ns
10.0
12.9
14.0
ns
19.2
—
ns
t31
Clock Period (long clock)
t32
Clock Low Width
t33
Clock Period (short clock)
—
t34
Data Setup Time Required
8.0
—
—
ns
t35
Data Hold Time Required
0
—
—
ns
t36
TOHEN Setup Time Required
8.5
—
—
ns
t37
TOHEN Hold Time Required
0
—
—
ns
t38
Delay1
0
—
7.0
ns
Clock to Frame Pulse
1. The frame pulse may occur after either a long clock or a short clock.
Receive Drop Interface
Drop Clock, Drop Frame, and Drop Data
The drop clock (D_CLK) and drop frame (DFRM) pins are driven using bidirectional TTL buffers. If the pointer processor is bypassed, the receive clock and receive frame are used for the drop interface and are output on the
D_CLK and DFRM pins.
t5
N
D_CLK
P
t6
N
DFRM
P
5-9086(F)
Figure 22. Receive Frame Timing (Pointer Processor Bypassed)
Table 255. Drop Frame Timing (Pointer Processor Bypassed)
Symbol
Parameter
Min
Typ
Max
Unit
t5
t6
Clock Period
DFRM Delay from Clock Edge
—
0.3
12.86
—
—
1.97
ns
ns
Agere Systems Inc.
181
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
If the pointer processor is not bypassed, D_CLK and DFRM are inputs to the device and are used to clock out the
drop data. The drop clock signal has a frequency of 77.76 MHz, which is multiplexed/divided internally to provide a
622.08 MHz clock for the drop data signals.
t5
N
D_CLK
P
t6
N
DFRM
P
t7
5-9086.a (F)
Figure 23. Receive Frame Timing (Pointer Processor Active)
Table 256. Drop Frame Timing (Pointer Processor Active)
Symbol
t5
t6
t7
Parameter
Clock Period
DFRM Setup Time
DFRM Hold Time Required
Min
Typ
Max
Unit
—
0
3
12.86
—
—
—
—
—
ns
ns
ns
Receive Drop Section Data Com
The receive drop data com (RDDCC) input is provided to allow the D1, D2, and D3 to be used for data transmission
across a backplane, or between devices. Since the section TOH (RSOH) has been previously terminated, these
bytes are no longer used and are available. Use of this input is optional. There is a corresponding output on the
add interface, the TADCC. These outputs would output a similar, proprietary DCC message from another device, or
across a backplane.
The receive drop data com (RDDCC) pin is clocked in using the rising edge of the receive drop section data com
clock (RDDCK) pin. Generation of the signal feeding the RDDCC pin is intended to occur at the negative edge of
RDDCK signal. This clock signal, running at 192 kHz, is an output of the device. In reference to Figure 20 on
page 178, the timing characteristics for these pins are given in Table 257.
Table 257. RDDCC Timing
Symbol
t27
t28
t29
t30
182
Parameter
Clock Period
Clock High Width
Data Setup Time Required
Data Hold Time Required
Min
Typ
Max
Unit
—
2.594
30
—
5.208
—
—
0
—
2.714
—
—
µs
µs
ns
ns
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Transmit Add Interface
Transmit Add Data
The transmit add pins, ADATA[16:1], are asynchronous inputs to the device, and while they do not have a phase
relationship to a clock, they are expected to have the same frequency as T_CLK (622.08 MHz). Furthermore, the
transmit add signals for a STS-48/STS-192 channel are expected to be aligned within 75 ns of each other.
Transmit Add Section Data Com
The transmit add data com (TADCC) output is provided to allow the D1, D2, and D3 to be used for data transmission across a backplane, or between devices. Since the section TOH (RSOH) has not yet been formed and path is
being input at the add interface, these bytes are available. Use of this output is optional. There is a corresponding
input on the add interface, the RDDCC. These inputs would be used to send a similar, proprietary DCC message to
another device, or across a backplane.
The transmit add section data com (TADCC) pins are timed using the rising edge of the transmit add section data
com clock (TADCK) pin. The data is clocked out at the rising edge of TADCK, and the TADCC pins should be read
at the negative edge of TADCK signal. The timing characteristics for these pins are given in Table 258. (See
Figure 16 on page 173.)
Table 258. TADCC Timing
Symbol
t10
t11
t12
Parameter
Clock Period
Clock High Width
Clock to Data Delay
Min
Typ
Max
Unit
—
2.594
30
5.208
—
—
—
2.714
—
µs
µs
ns
Microprocessor Interface Timing
Synchronous Mode
The synchronous microprocessor interface mode is selected when MPMODE = 1. Interface timing for the synchronous mode write cycle is given in Figure 24 on page 184 and in Table 260 on page 184. Interface timing for the
read cycle is given in Figure 25 on page 185 and in Table 262 on page 185.
The parity bits, PARITY_1 and PARITY_0, are optional and may be left unconnected if not used. If unused, TEA_N
should be ignored on a synchronous write.
Agere Systems Inc.
183
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
In synchronous mode, a transfer error (TA_N = 1, TEA_N = 0) will occur if the internal cycle is not terminated in
32 PCLK cycles from the first rising edge of PCLK, where CS_N = 0 and TS_N = 0.
tc
tcycle
INSERTED
WAITSTATES
PCLK
CS_N
t39
TS_N
RW_N
t40
ADDRESS_[15:0]
t41
DATA_[15:0]/PARITY_[1:0]
(INPUT)
TA_N/TEA_N
t43
t42
HIGH Z
t45
t44
HIGH Z
5-9093(F)
Figure 24. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1)
Table 259. TA_N/TEA_N Cycle Termination for Synchronous Write Cycle
TA_N
TEA_N
0
0
1
1
0
1
0
1
Encoding Description
Write data parity error.
Normal cycle termination.
Access to undefined address region—transfer error.
No cycle termination—processor generated time-out.
Table 260. Microprocessor Interface Synchronous Write Cycle Specifications
Symbol
tc
tcycle
t39
t40
t41
t42
t43
t44
t45
184
Parameter
PCLK Period
Bus Transfer Cycle Time
CS_N, TS_N, RW_N Valid to PCLK
ADDRESS, DATA Valid to PCLK
CS_N, TS_N, RW_N, ADDRESS, DATA Hold
PCLK to TA_N/TEA_N 3-State to High
PCLK to TA_N/TEA_N High to Low
PCLK to TA_N/TEA_N Low to High
PCLK to TA_N/TEA_N 3-State
Min
Max
Unit
20
8
4
18
2
3.5
5.5
5
—
—
12
—
—
—
13.5
15
13.5
4
ns
tc
ns
ns
ns
ns
ns
ns
ns
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
tcycle
INSERTED
WAITSTATES
PCLK
CS_N
t39
TS_N
t47
RW_N
t40
ADDRESS_[15:0]
t46
DATA_[15:0]/PARITY_[1:0]
(OUTPUT)
TA_N/TEA_N
t41
t42
HIGH Z
t47
t44
t45
HIGH Z
5-9094(F)
Figure 25. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1)
Table 261. TA_N/TEA_N Cycle Termination for Synchronous Read Cycle
TA_N
TEA_N
0
0
1
1
0
1
0
1
Encoding Description
Not possible during read cycle.
Normal cycle termination.
Access to undefined address region—transfer error.
No cycle termination—processor generated time-out.
Table 262. Microprocessor Interface Synchronous Read Cycle Specifications
Symbol
t46
t47
Parameter
Data Valid to PCLK with TA_N Low
PCLK to DATA 3-State
Agere Systems Inc.
Min
Max
Unit
2
2
3
—
tc
ns
185
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Asynchronous Mode
The asynchronous microprocessor interface mode is selected when MPMODE = 0. Interface timing for the asynchronous mode write cycle is given in Figure 26 and in Table 263 below. Interface timing for the read cycle is given
in Figure 27 on page 187 and in Table 266 on page 187.
In asynchronous mode, the PCLK can be connected to a 77.76 MHz clock. This can be the same source as the
D_CLK input when DRPBYP = 0. If DRPBYP is 1, then the D_CLK output can be used. The microprocessor should
run at no more than half the frequency of PCLK in asynchronous mode. The timing numbers shown assume a
PCLK frequency of 77.76 MHz.
ADDRESS_[15:0]
t50
t48
t49
CS_N
t48
t49
TS_N
t48
t49
DS_N
t51
t52
RW_N
t53
t51
DATA_[15:0]
(INPUT)
t55
TA_N/TEA_N
t57
t54
HIGH Z
t56
HIGH Z
5-9095(F)
Figure 26. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0)
Table 263. Microprocessor Interface Asynchronous Write Cycle Specifications
Symbol
tc
t48
t49
t50
t51
t52
t53
t54
t55
t56
t57
Parameter
PCLK Period
ADDRESS Valid to CS_N/DS_N/TS_N Fall
TA_N Fall to CS_N/DS_N/TS_N Rise
TA_N Fall to DATA/ADDRESS Invalid
RW_N Fall to CS_N/DS_N/TS_N Fall
DS_N Rise to RW_N Rise
DATA Valid to DS_N Fall
CS_N/DS_N/TS_N Fall to TA_N/TEA_N High
CS_N/DS_N/TS_N Fall to TA_N/TEA_N Fall
CS_N/DS_N/TS_N Rise to TA_N/TEA_N Rise
CS_N/DS_N/TS_N Rise to TA_N/TEA_N 3-state
Min
Max
Unit
12.86
0
0
0
0
0
0
4
5
43
42
15
—
—
—
—
—
—
—
351
54
80
ns1
ns
ns
ns
ns
ns
ns
tc
tc
ns
ns
1. This value represents the timing for a transfer error (TA_N = 1, TEA_N = 0). The typical value during normal access would be 9 tc.
186
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Table 264. TA_N/TEA_N Cycle Termination for Asynchronous Write Cycle
TA_N
TEA_N
0
0
1
1
0
1
0
1
Encoding Description
Not possible during asynchronous write cycle.
Normal cycle termination.
Access to undefined address region—transfer error.
No cycle termination—processor generated time-out.
ADDRESS_[15:0]
t48
CS_N
t48
TS_N
t48
DS_N
RW_N
t54
t55
TA_N/TEA_N
t56
HIGH Z
HIGH Z
t58
DATA_[15:0]
t57
t59
HIGH Z
HIGH Z
5-9096(F)
Figure 27. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0)
Table 265. TA_N/TEA_N Cycle Termination for Asynchronous Read Cycle
TA_N
TEA_N
0
0
1
1
0
1
0
1
Encoding Description
Not possible during read cycle.
Normal cycle termination.
Access to undefined address region—transfer error.
No cycle termination—processor generated time-out.
Table 266. Microprocessor Interface Asynchronous Read Cycle Specifications
Symbol
t58
t59
Parameter
TA_N/TEA_N Valid to DATA Valid
CS_N/TS_N/DS_N Rise to DATA 3-State
Agere Systems Inc.
Min
Max
Unit
13
43
15
56
ns
ns
187
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Timing Characteristics (continued)
Use of a Synchronous Microprocessor with the TSOT0410G4 in Asynchronous Mode
The use of a synchronous microprocessor (such as the M860/M8260) to communicate with a TSOT0410G4 configured for asynchronous mode (MPMODE = 0) requires one additional consideration. There is a difference between
the operation of a synchronous processor (e.g., M860/M8260) and the asynchronous processors (e.g., 68360). In
a synchronous processor, the data is latched on the same edge that detects the assertion of TA_N. In an asynchronous processor, the TA_N (DSACK) signal is detected, and the data is latched one clock period later.
In both cases, the TSOT0410G4 meets the timing required by these two different processors. However, a synchronous processor operating with the TSOT0410G4 configured in asynchronous mode will have problems consistently latching the correct data. It will depend on the relationship between the two clocks. As shown in Figure 27 on
page 187, the data is presented on the bus 13 ns—15 ns after TA_N is asserted. If the microprocessor has a rising
edge within this window, it will capture incorrect data.
To operate the TSOT in asynchronous mode with an synchronous processor, add a delay on the TA_N signal from
the TSOT0410G4; otherwise, consider using synchronous mode.
188
Agere Systems Inc.
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Outline Diagram
600-Pin LBGA
Dimensions are in millimeters.
45.00
41.3/42.3
A1 BALL
IDENTIFIER ZONE
41.3/42.3
45.00
ELECTRICALLY ISOLATED
HEAT SPREADER
2.45/3.05
1.45/1.85
1.95/2.35
0.60 ± 0.10
SEATING PLANE
0.20
SOLDER BALL
34 SPACES @ 1.27 = 43.18
A1 BALL
CORNER
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6
4 2
35 33 31 29 27 25 23 21 19 17 15 13 11 9 7
5 3 1
A
C
E
G
0.75 ± 0.15
J
L
N
R
U
W
AA
AC
AE
AG
AJ
AL
AN
AR
B
D
F
H
K
M
P
T
V
Y
34 SPACES
@ 1.27 = 43.18
AB
AD
AF
AH
AK
AM
AP
5-9212.a (F)
Agere Systems Inc.
189
TSOT0410G4 SONET/SDH
STS-192 Overhead and Path Processor
Data Sheet
May 2003
Ordering Information
Device Code
Package
Temperature
Comcode
TSOT0410G14
600-pin LBGA
–40 °C to +85 °C
700017424
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Copyright © 2003 Agere Systems Inc.
All Rights Reserved
May 2003
DS02-252SONT-1 (Replaces DS02-252SONT)