ASAHI KASEI [AK2308LV] AK2308LV SPEECH CODEC for Digital Key telephone FEATURES GENERAL DISCREPTION AK2308LV is an integrated LSI with PCM CODEC, Voice path control, MIC amplifier and Handset driver suitable for PBX/KTS digital key telephone, VoIP Telephone Analog Interface. 2 MIC AMP for the handset and microphone are integrated. Differential driver for the 32ohm speaker and 10k ohm driver for the handset receiver. Path control and volume control via serial CPU I/F 3.3V+/-0.3V single power supply Low noise, low power consumption - PCM CODEC is compliant to ITU G.711 G.712 specification, very low noise, and low power dissipation CODEC. A-law and u-law selectable through Serial I/F register. PCM I/F provides Long/Short frame format. The output is 8bit compressed data along with 16bit linear format. FS must be 8kHz clock that is synchronized with BCLK. - Package 30pin VSOP package Voice path block consists of TX analog inputs, output for handset receiver, output for the hands-free speaker, volume for the TX and RX respectively, and the path control switches. Side tone can be added internally and its volume is controlled through serial CPU I/F. - Package size; 9.7*7.6mm(pin to pin) - Pin pitch; 0.65mm BLOCK DIAGRAM HANDT3 HANDT1 HANDT2 SW1 0dB Amp1 MIC3 PAD 0/-14dB A/D SW2 Amp3 Tx Digital vol +15～-16dB 1dB step Linear ↓ A/μ MIC1 MIC2 Amp2 A/u-law 16bit Linear DAOUT RAI Side Tone Att -12～-57dB 3dB Step +5～+11dB SW5 Amp4 RAO VOL1 PCM I/F CODEC SPI DR FS Rx Analog Vol +12～-12dB 2dB step SW3 DX BCLK D/A 0dB RX Digital vol +15～-16dB 1dB step + Linear ↑ A/μ SPOP 32Ω Amp5 -1 0dB SPON 32Ω -11dB Amp6 PLL PLLCAP SW7 VOL2 HANDI Rx Analog Vol +8～-18dB 2dB step VOL3 +6/0/-6dB Power SW4 10KΩ Amp7 CSN SCLK DATA 0dB -25dB HANDR CPU I/F SW6 VREF RAGND TONEI AVDD AVSS DVDD DVSS MS0227-E-01 2005/12 1 ASAHI KASEI [AK2308LV] PIN ASSIGNMENT PLLCAP AVSS SPON SPOP VDD VSS FS DX BCLK DR DATA SCLK CSN TEST AVDD 1 2 TOP VIEW 3 4 5 6 7 8 9 10 11 12 13 14 15 MS0227-E-01 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TONEI SPI RAO RAI HANDR HANDI DAOUT RAGND VREF HANDT2 HANDT1 HANDT3 MIC3 MIC1 MIC2 2005/12 2 ASAHI KASEI [AK2308LV] PIN CONDITIONS Pin types; DIN: Input DOUT: Output AIN: Analog Input AOUT: Analog Output I/O: Input/ Tri-state output TOUT: Tri-state output AOUT: Analog output PWR: Power supply Table 1 Pin # 21 19 20 26 25 18 16 17 24 27 28 29 4 3 30 11 12 13 Name HANDT2 HANDT3 HANDT1 HANDR HANDI MIC3 MIC2 MIC1 DAOUT RAI RAO SPI SPOP SPON TONEI DATA SCLK CSN 10 8 9 7 DR DX BCLK 6 5 2 15 1 VSS VDD AVSS AVDD 23 22 FS* PLLCAP Type Pin function AIN AIN AOUT AOUT AIN AIN AIN AOUT AOUT AIN AOUT AIN AOUT AOUT AIN Max MIn Cap load Res load Analog input for handset microphone Analog input for handset microphone Amplifier output for handset microphone 20pF Analog output for handset receiver 20pF Analog input for handset receiver Analog input for external microphone Analog input for external microphone Amplifier output for external microphone 20pF Analog output of D/A converter 20pF Amplifier input for level adjustment Amplifier output for level adjustment 20pF Analog input for speaker Analog output of the speaker driver (+) 1000pF between Analog output of the speaker driver (−) Input for the external tone signal Serial data I/O for the internal register I/O 50pF access Serial data clock for the internal register DIN access Chip select negative input for the internal DIN register access DIN RX PCM data serial input TOUT TX PCM data serial output 50pF DIN Bit clock input for the PCM I/F 8KHz frame sync signal input for the DOUT PCM I/F PWR Power supply for the digital block:0V PWR Power supply for the digital block: 3.3V PWR Power supply for the analog block:0V PWR Power supply for the analog block: 3.3V Output to connect the PLL loop filter AOUT capacitance RAGND AOUT Analog ground output for the RX side VREF AOUT Voltage reference output 14 TEST DIN Test pin *FS must be 8kHz clock that is synchronized with BCLK. MS0227-E-01 comment 5kΩ 10kΩ 5kΩ 8kΩ 12kΩ 32Ω 1.0uF external capacitance 1.0uF external capacitance 1.0uF external capacitance Tied to VSS 2005/12 3 ASAHI KASEI [AK2308LV] ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Power Supply Voltages Analog/Digital Power Supply VDD -0.3 6.5 VSS Voltage VSS 0 0 Digital Input Voltage VTD -0.3 VDD+0.3 Analog Input Voltage VTA -0.3 VDD+0.3 Input current (except power supply pins) IIN -10 10 Storage Temperature Tstg -55 125 Warning: Exceeding absolute maximum ratings may cause permanent damage. Normal operation is not guaranteed at these extremes. Units V V V V mA o C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supplies Analog/Digital power supply VDD Ambient Operating Temperature Ta Note) All voltages reference to ground : VSS=0V MS0227-E-01 Min Typ Max 3.0 -10 3.3 3.6 70 Units V C o 2005/12 4 ASAHI KASEI [AK2308LV] FUNCTIONAL DISCRIPTIONS 1. CPU INTERFACE The internal registers can be read/written via serial CPU interface which consists of SCLK, DATA, and CSN pin. 1 word consists of 16bits. The first 3bits are the instruction code which specifies read or write. The following 4bits specify the address. The rest of 8bits are the data stored in the internal registers. Table1-A CPU I/F ADDRESS/DATA STRUCTURE B15 B14 B13 B12 B11 B10 B9 B8 I2 I1 I0 A3 Instruction code (3 bit ) A2 A1 A0 Address (4bit) * B7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 * Data for internal registers (8bit) *)Dummy bit for adjusting the I/O timing when reading register. Table1-B INSTRUCTION CODE I2 I1 I0 1 1 0 1 1 1 Read/Write Read Write No action Others 1-2 Timing of the CPU Interface SCLK and DATA timing in WRITE/READ operation (1) Input data are loaded into the internal shift register at the rising edge of SCLK. (2) The rising edge of SCLK is counted after the falling edge of CSN. (3) When CSN is “L” and more than 16 SCLK pulses: th [WRITE] Data are loaded into the internal register at the rising edge of the SCLK 16 pulse. th [READ] DATA pin becomes an input pin at the falling edge of the SCLK 16 pulse. CSN timing and WRITE/READ CANCELLATION th (1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16 pulse. th (2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16 pulse. SERIAL WRITE/READ ACCESS timing (SERIAL ACCESS MODE) (1) Serial write and read operation will be done by feeding the another 16 SCLK pulse and st data after 1 write or read operation. st nd (2) It is not necessary to make CSN high between 1 operation and 2 operation. MS0227-E-01 2005/12 5 ASAHI KASEI [AK2308LV] WRITE Continuous SCLK Goes up anytime after SCLK 16th pulse and before 32nd pulse CSN SCLK 1 Z DATA 2 1 3 1 4 1 5 0 6 0 Instruction Code 7 0 8 0 9 16 D7 * Z D0 Write data to address”000” Address “0000” 1 2 1 WRITE at the rising edge of SCLK 16th pulse 1 3 4 8 1 9 D7 15 D1 16 D0 Z Write data Instruction Code Burst SCLK SCLK can be stoped at “H” level or “L” level at anytime during the write cycle. After resuming the SCLK, write cycle is retrieved normally. Goes up anytime after SCLK 16th pulse and 32nd pulse CSN SCLK 1 Z DATA 2 1 3 1 4 1 5 0 6 0 Instruction Code 7 0 8 0 9 16 D7 * D0 Write data to address “000” Address ”0000” Z WRITE at the rising edge of SCLK 16th pulse CANCELLATION CSN goes “H” before the rising edge of 16th SCLK pulse CSN SCLK DATA 1 Z 1 2 1 3 1 Instruction Code 4 0 5 0 6 0 Address ”0000” 7 0 8 * 9 D7 16 Z D0 Write data to address”000” Write is not Excuted MS0227-E-01 Z DATA pin: Input mode (Hi-Z) 2005/12 6 ASAHI KASEI [AK2308LV] SERIAL ACCESS Serial access can be done by CSN staying “L” during the serise of write cycle. CSN SCLK DATA 1 Z 1 2 1 3 1 4 0 5 0 6 0 7 0 8 D7 * Address ”0000” Instruction Code 9 16 1 Z D0 1 Write data to Address”000” 2 3 1 1 8 4 1 9 15 16 Z D1 D0 D7 Write data Instruction Code EXCUTE! EXCUTED! READ Continuous SCLK Can be going up at anytime after SCLK 16th pulse and before 32nd pulse CSN SCLK DATA 1 Z 1 2 1 3 0 4 5 A3 A2 Read Instruction 6 7 A1 A0 8 Z 9 D7 16 1 Z D0 1 Read Data Address 2 1 3 1 4 0 Read Instruction 8 9 D7 15 16 D1 D0 Z Read Data Read period until the earlier edge of either CSN rising or SCLK 16th pulse falling Data output starts at the falling edge of SCLK 8th pulse Burst SCLK Can be going up at anytime after SCLK 16th pulse and before 32nd pulse CSN SCLK DATA 1 Z 1 2 1 3 0 Read Instruction 4 5 A3 A2 6 7 A1 A0 Address 8 Z 9 16 D0 D7 Z Read Data Read output starts at the falling edge of SCLK 8th pulse MS0227-E-01 2005/12 7 ASAHI KASEI [AK2308LV] SERIAL ACCESS Serial access can be done by CSN staying “L” during the serise of read cycle CSN SCLK DATA 1 Z 1 2 1 3 0 4 5 0 0 6 7 0 0 Z 9 D7 16 1 Z D0 1 Read data Address ”0000” Read Instruction 8 2 1 3 1 4 8 9 15 16 Z 0 Read Instruction READ EXCUTED! READ EXCUTED! DISCORD OF INSTRUCTION CODE CSN SCLK DATA Z 1 2 3 4 5 I2 I1 I0 IA3 A2 IInstructions except specified 0bb 10b (b=0 or 1) 6 7 8 9 16 Z A1 A0 Address WRITE/READ NOT EXCUTED! Z DATA pin: Input mode (Hi-Z) Register Map Register Type : Read/ Write Add (Hex) 0 1 2 D7 D6 D5 D4 D3 - SW7 - SW6 - SW5 Side Tone SW4 - 3 4 5 6 7–F - - TX_pad •Address “1” ; PCM_0/1 - VOL 3 - - D2 D1 D0 SW3 SW2 SW1 PCM_1 PCM_0 u/A-law Side Tone Attenuator TX Digital Volume RX Digital Volume VOL 1 VOL 2 - - Register Name (Functions) Path Control PCM Control Side Tone Control Side Tone Digital Attenuator Gain TX Voice Path Gain Control RX Digital Volume Control RX Speaker Volume Control RX Handset Volume Control Reserved for test use ---- Selection of the PCM interface Mode(Long/Short frame, AK130 -1,AK130-2, 16bit linear) •Bits with “-” in the flame are for test mode activation. Please fill the data “0” for the normal operation. These bits are for test use so that cannot write the data from CPU interface and read operation, data “0” are read from CPU interface. •Each bit is set as “Default value” written in the following related sections after power on reset. •Explanatory of each bits are described in following pages. MS0227-E-01 2005/12 8 ASAHI KASEI 2. PCM Data Interface [AK2308LV] AK2308LV supports 4 PCM data interface modes. - A/u-Law PCM data mode( Long or Short frame) This mode is for interface of 64kbps PCM data which are compressed /extended by A -law or u-law. Both Long frame and short frame format are acceptable. The PCM data occupies the first time slot of the PCM data bus which is specified by the frame sync signal. Please refer to the format diagram. A -law or u-law is selectable via CPU register. - 16 bit Linear data Mode This mode is for the interface the 16 bit linear PCM data. PCM CODEC of AK2308LV operates at 14 bit accuracy. The 2 bits of the LSB are fixed in the 16 bit data stream. - AK130 B1 Mode This mode provides the PCM data Interface to AK130, the TCM transceiver for PBX/KTS system. PCM data format is 64kbps A-law or u-law data. The timing between data and FS is dif ferent from the A/u-Law PCM data mode written above. In this mode the PCM data are transmitted/received via B1 channel , one of the PCM data channel of the AK130. - AK130 B2 Mode This mode provides the PCM data interface to AK130 B2 channel in th e same manner as AK130 B1 Mode. In every mode, the digital voice data are in and out from DR and DX pin, respectively, and the bit clock and the 8KHz frame sync signal will be fed via BCLK and FS. And FS must be 8kHz clock that is synchronized with BCLK. The order of PCM and linear data is MSB first. Table 2-A Summary of PCM interface modes Mode PCM data format BCLK rate frame signal Time slot A/u-Law PCM data mode 16bit Linear data mode AK130 B1 mode AK130 B2 mode A/u-Law A/u-Law 2.048MHz LF/SF auto select SF only AK130 FS signal AK130 FS signal 1 Time slot 16bit Linear A/u-Law 64K x N (N: 1 to 32) 64K x N (N: 2 to 32) 2.048MHz st first 16 bit after FS signal B1 channel of AK130 B2 channel of AK130 2-1. Selection of the interface mode These four interface modes are selectable through the CPU register which specified below. A/u-Law is also selectable from the same CPU register and it is effective in the A/u -law PCM interface mode and AK130 B1/B2 modes. PCM Control Register Type : Read Write[Address:0001 ADD D7 D6 D5 1 Default 0 0 D2-D0:(PCM_1-0, u/A-law)] D4 D3 D2 D1 PCM_1 PCM_0 - 0 0 0 0 0 D0 u/A law 0 PCM_1、0 ； PCM interface mode select PCM_1 PCM_0 Mode 0 0 A/u-Law PCM data mode 0 1 16bit Linear interface mode 1 0 AK130 B1 mode 1 1 AK130 B2 mode u/A-law ; PCM compress/Extend format select A/u-law Compress/Extend 0 u-law 1 A-law MS0227-E-01 2005/12 9 ASAHI KASEI [AK2308LV] 2-2 Timing and format of the PCM interface 2-2-1 u/A-Law PCM data Mode 8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal. Although there are 32 time slots at maximum in 8kHz frame(when BCK=2.048MHz), PCM data for AK2308LV occupies the first time slot as is indicated in figures below. 2-2-1-a Signals - Frame Sync signal (FS) 8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal clock of the LSI is generated based o n this FS signal. - Bit Clock (BCLK) BCLK defines the PCM data rate. BCLK can be varied from 64kHz to 2.048MHz by 64kHz step. - PCM data output (DX) DX is an output signal of 64Kbps PCM u/A -law data. The data is synchronized to the BCLK which determ ines the data rate. In the period in which the PCM data is not occupied, the DX pin turns to Hi -impedance. In the long frame mode, the th LSB bit turns to Hi-impedance at the faster edge of either FS falling edge or 9 rising edge of BCLK. - PCM data input (DR) DR is an input signal of 64Kbps PCM u/A -law data. The data is clocked by the falling edge of the BCLK and fed into the D/A block. 2-2-1-b LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic selection AK2308LV monitors the duration of the “H” level of FS and automatically selects LF or SF interface format. Period of FS=”H” Interface format More than 2 clocks of BCLK LF 1 clock of BCLK SF 2-2-1-c Frame format of the interface Long Frame format M o r e t h a n 2 c lo c k s 1 2 5 u s (8 K H z ) FS BCLK DX DR 7 D o n ’t c a re 7 6 6 5 5 4 4 3 3 2 2 1 1 0 D o n ’t c a r e 0 Short Frame format 1 2 5 u s (8 K H z ) FS BCLK DX DR 7 D o n ’t c a re 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 D o n ’t c a re Notice FS must be 8kHz clock that is synchronized with BCLK. MS0227-E-01 2005/12 10 ASAHI KASEI [AK2308LV] 2-2-2 16 bit Linear PCM data mode In this mode the 16 bit linear PCM data are interfaced to the outside. This mode is useful to compress/extend the PCM data using much higher compress rate algorithm than u/A -law algorithm by the external DSP. The AK2308LV CODEC operates at 14bit accuracy, thus the least 2 bits are output as fixed value. 2-2-2-a Signals - Frame Sync signal (FS) 8kHz reference signal which is as sa me as in u/A-law PCM data mode. “H” level pulse width of the FS should be 1 clock period as same as in the short frame PCM mode. - Bit Clock (BCLK) BCLK defines the PCM data rate. BCLK can be varied from 128kHz to 2.048MHz by 64kHz step which is different from in the u/A-law PCM data mode. - PCM data output (DX) DX is an output signal of 128Kbps linear PCM data. The data is synchronized to the BCLK which determines the data rate. In the period which the PCM data is not occupied, the DX pin turns to Hi -impedance output. - PCM data input (DR) DR is an input signal of 128Kbps linear PCM data. The data is clocked by the falling edge of the BCLK and fed into the D/A block. 16bti Linear Frame format 125us (8KHz) FS BCLK DX Hi-Z MSB First 1 2 3 12 13 14 DR * MSB First 1 2 3 12 13 14 Hi-Z * * * Hi-Z * 1 1 2-2-3 AK130 B1/B2 Mode These modes are for connecting the PCM interface to AK130, AKM ’s TCM( ping-pong ) transceiver for PBX/KTS system. The PCM data format is A-law or u-law which can be selected by the register. The AK130 B1 mode interfaces the data to B1 channel, one of the B channel which AK130 provides, and the AK130 B2 mode interfaces the data to B2 channel. 2-2-3-a Signals - Frame Sync signal (FS) ___ Please feed the FS signal which is generated by AK130.( F0o , pin#3 ) - Bit Clock (BCLK) BCLK defines the PCM data rate. Please use 2.048MHz clock which is generated by AK130.( E2o,pin#5 ) - PCM data output (DX) DX is an output signal of 128Kbps linear PCM data. Please connect to the PCM data input pin of AK130. ( DSTi,pin#11 ) - PCM data input (DR) DR is an input signal of 128Kbps linear PCM data. The data is clocked by the falling edge of the BCLK and fed into the D/A block. Please connect to the PCM data output pin of AK130. ( DSTo,pin#6 ) MS0227-E-01 2005/12 11 ASAHI KASEI [AK2308LV] AK130 B1 Mode 244ns 125us(8kHz) FS BCLK 16CLK 8CLK MSB First Hi-Z DX DR * * * 7 * * * 7 6 2 MSB First 6 1 Hi-Z 0 1 0 * * * * Note)*：Don't care AK130 B2 Mode 244ns 125us(8kHz) FS BCLK 24CLK 8CLK MSB First Hi-Z DX DR * * * 7 * * * 7 6 MSB First 6 2 1 1 Hi-Z 0 0 * * * * Note)*：Don't care MS0227-E-01 2005/12 12 ASAHI KASEI 3. Path and Gain Controls [AK2308LV] The voice path gain of both RX and TX side, and the tone path gain are controlled from the CPU registers. 3-1. Voice Path control switches; AK2308LV has 7 analog switches to control the RX, TX analog path and Tone path. These switches are controlled from following “Path Control” register. Path Control Register Type : Read Write[Address:0000 D6-D0:(SW7-SW1)] ADD D7 D6 D5 D4 D3 D2 0 SW7 SW6 SW5 SW4 SW3 Default 0 0 0 0 0 0 D1 SW2 0 D0 SW1 0 Table3-a Switch function SW Name SW7 SW6 SW5 SW4 SW3 Function Speaker Tone enable 2 Handset Tone select Speaker Tone enable 1 RX Voice path enable for Handset RX speaker path enable SW2 SW1 TX MIC path enable TX Handset path enable Polarity 1: Tone output ON 0: Tone output OFF 1: Tone output ON 0: Tone output OFF 1: Tone output ON 0: Tone output OFF 1: Voice path ON 0: Voice path OFF 1: Speaker path ON 0: Speaker path OFF 1: MIC path ON 0: MIC path OFF 1: Handset path ON 0: Handset path OFF Tone Path When the tone signal is applied, please input the tone signal first, and then turn on the switches (SW7~5). Also when you want to stop the tone signal, please turn off the switches before stopping the tone signal. This is to prevent the pop noise when tone is turned off & on. SW5 Vol 1 SPOP SW7 -1 TONEI -11dB SPON SW6 -25dB HANDR Notice Please do not turn on the SW5 and SW7 simultaneously. MS0227-E-01 2005/12 13 ASAHI KASEI [AK2308LV] 3-2 Voice path gain Controls AK2308LV provides the RX and TX voice gain control functions both in analog domain and in digital domain. These gain can be controlled from following five registers. 3-2-1. RX voice path gain controls RX side voice path has three gain control blocks. These gain stages are controlled through following three registers, “RX Digital Volume Control”, “RX Handset Volume Control” and “RX Speaker Control”. RX Digital Volume Control Register Type : Read Write[Address:0100 D4-D0(VRX4-VRX0)] ADD D7 D6 D5 D4 D3 D2 D1 4 VRX4 VRX3 VRX2 VRX1 Default 0 0 0 0 0 0 0 D0 VRX0 0 VRX[4-0]; RX side digital volume from +15dB to –16dB by 1dB step. VRX4 VRX3 VRX2 VRX1 VRX0 RX digital Attenuator Comment 0 0 0 0 0 -16dB default 0 0 0 0 1 -15dB 0 0 0 1 0 -14dB 0 0 0 1 1 -13dB 0 0 1 0 0 -12dB 0 0 1 0 1 -11dB 0 0 1 1 0 -10dB 0 0 1 1 1 -9dB 0 1 0 0 0 -8dB 0 1 0 0 1 -7dB 0 1 0 1 0 -6dB 0 1 0 1 1 -5dB 0 1 1 0 0 -4dB 0 1 1 0 1 -3dB 0 1 1 1 0 -2dB 0 1 1 1 1 -1dB 1 0 0 0 0 0dB 1 0 0 0 1 +1dB 1 0 0 1 0 +2dB 1 0 0 1 1 +3dB 1 0 1 0 0 +4dB 1 0 1 0 1 +5dB 1 0 1 1 0 +6dB 1 0 1 1 1 +7dB 1 1 0 0 0 +8dB 1 1 0 0 1 +9dB 1 1 0 1 0 +10dB 1 1 0 1 1 +11dB 1 1 1 0 0 +12dB 1 1 1 0 1 +13dB 1 1 1 1 0 +14dB 1 1 1 1 1 +15dB MS0227-E-01 2005/12 14 ASAHI KASEI [AK2308LV] RX Handset Volume Control ( Vol 2 ), RX Handset Volume Control ( Vol 3) Register Type : Read Write [Address:0111 D4-D0(V2_3-V2_0)] ADD D7 D6 D5 D4 D3 D2 D1 6 V3_1 V3_0 V2_3 V2_2 V2_1 default 0 0 0 0 0 0 0 D0 V2_0 0 V2_[3-0]; Analog volume for the RX side handset output ( precise). The gain is variable from +8dB to –18dB by 2 dB step. The total gain control is done with V3_[1:0]. V2_3 V2_2 V2_1 V2_0 VOL2 Comment 0 0 0 0 -18dB defult 0 0 0 1 -16dB 0 0 1 0 -14dB 0 0 1 1 -12dB 0 1 0 0 -10dB 0 1 0 1 -8dB 0 1 1 0 -6dB 0 1 1 1 -4dB 1 0 0 0 -2dB 1 0 0 1 0dB 1 0 1 0 +2dB 1 0 1 1 +4dB 1 1 0 0 +6dB 1 1 0 1 +8dB 1 1 1 0 Forbidden 1 1 1 1 Forbidden V3_[1-0]; Analog volume for the RX side handset output (coarse). The gain is variable from +6dB to –6dB by 6 dB step. V3_1 V3_0 VOL3 Comment 0 0 -6dB defult 0 1 0dB 1 0 +6dB 1 1 Forbidden MS0227-E-01 2005/12 15 ASAHI KASEI [AK2308LV] RX Speaker Volume Control ( Vol 1 ) Register Type : Read Write [Address:0101 D3-D0(V1_3-V1_0)] ADD D7 D6 D5 D4 D3 D2 5 V1_3 V!_2 default 0 0 0 0 0 0 D1 V1_1 0 D0 V1_0 0 V1_[3-0]; Analog volume for the RX Speaker output. The gain is variable from +12dB to –12dB by 2 dB step. V1_3 V1_2 V1_1 V1_0 VOL1 Comment 0 0 0 0 -12dB defult 0 0 0 1 -10dB 0 0 1 0 -8dB 0 0 1 1 -6dB 0 1 0 0 -4dB 0 1 0 1 -2dB 0 1 1 0 0dB 0 1 1 1 +2dB 1 0 0 0 +4dB 1 0 0 1 +6dB 1 0 1 0 +8dB 1 0 1 1 +10dB 1 1 0 0 +12dB 1 1 0 1 Forbidden 1 1 1 0 Forbidden 1 1 1 1 Forbidden MS0227-E-01 2005/12 16 ASAHI KASEI [AK2308LV] 3-2-2. TX voice path gain controls TX side voice path has two gain control blocks. One is a analog volume and the other is a digital attenuator after D/A converter. These voice path gains are controlled through the following register. TX Voice Path Gain Control (TX digital Attenuator, VOL 1) Register Type : Read Write[Address:0010 D5-D0: (TX_pad, VTX4-VTX0)] ADD D7 D6 D5 D4 D3 D2 D1 3 Tx_pad VTX4 VTX3 VTX2 VTX1 default 0 0 1 0 0 0 0 D0 VTX0 0 VTX[4-0]; The digital attenuator for TX side voice path. The gain variation is from +15dB to –16dB by 1dB step. VTX4 VTX3 VTX2 VTX1 VTX0 TX digital Attenuator Comment 0 0 0 0 0 -16dB default 0 0 0 0 1 -15dB 0 0 0 1 0 -14dB 0 0 0 1 1 -13dB 0 0 1 0 0 -12dB 0 0 1 0 1 -11dB 0 0 1 1 0 -10dB 0 0 1 1 1 -9dB 0 1 0 0 0 -8dB 0 1 0 0 1 -7dB 0 1 0 1 0 -6dB 0 1 0 1 1 -5dB 0 1 1 0 0 -4dB 0 1 1 0 1 -3dB 0 1 1 1 0 -2dB 0 1 1 1 1 -1dB 1 0 0 0 0 0dB 1 0 0 0 1 +1dB 1 0 0 1 0 +2dB 1 0 0 1 1 +3dB 1 0 1 0 0 +4dB 1 0 1 0 1 +5dB 1 0 1 1 0 +6dB 1 0 1 1 1 +7dB 1 1 0 0 0 +8dB 1 1 0 0 1 +9dB 1 1 0 1 0 +10dB 1 1 0 1 1 +11dB 1 1 1 0 0 +12dB 1 1 1 0 1 +13dB 1 1 1 1 0 +14dB 1 1 1 1 1 +15dB TX_pad: The digital attenuator for TX side voice path. The gain variation is 0dB or –14dB TX_pad 0 1 Comment TX digital pad 0dB -14dB default MS0227-E-01 2005/12 17 ASAHI KASEI [AK2308LV] 3-2-3. Side Tone path gain controls AK2308LV provides the side tone pass from TX to RX in digital domain. The activation of this pass is set through “Side Tone” bit and the side tone attenuation is controlled through “Side Tone digital attenuator gain” register. Side Tone Control, Side Tone digital attenuator gain Register Type : Read Write[Address:0010 D4-D0:(Side_Tone, Side Tone digital attenuator gain)] ADD D7 D6 D5 D4 D3 D2 D1 D0 2 Side VSD_3 VSD_2 VSD_1 VSD_0 Tone default 0 0 0 0 1 1 Side Tone; A pass enable of the side tone from TX to RX. Name Porarity Side Tone 0 OFF 1 ON 1 1 Comment default VSD_[3-0]; Side tone digital Attenuator. The gain variation range is from –12dB to –57dB. VSD_3 VSD_2 VSD_1 VSD_0 Side Tone digital Attenuator gain 0 0 0 0 -12dB 0 0 0 1 -15dB 0 0 1 0 -18dB 0 0 1 1 -21dB 0 1 0 0 -24dB 0 1 0 1 -27dB 0 1 1 0 -30dB 0 1 1 1 -33dB 1 0 0 0 -36dB 1 0 0 1 -39dB 1 0 1 0 -42dB 1 0 1 1 -45dB 1 1 0 0 -48dB 1 1 0 1 -51dB 1 1 1 0 -54dB 1 1 1 1 -57dB MS0227-E-01 Comment default 2005/12 18 ASAHI KASEI [AK2308LV] 4. Power on Reset Power on Reset AK2308LV automatically generates the internal reset pulse wh ich resets all the circuit that is necessary to start the initialization after the power on reset. The CPU registers are set to the default value. After the internal reset pulse is generated, CODEC starts the initialization procedure by being fed FS signa l, and it takes 150ms(typ.), 330ms(max) to complete the initialization after the detection of power on. Power up slope to enable the Power-on Reset When the power-up slope is no longer than 50ms(=5tau:tau is time constant), Power On Reset works normally. When the slope is longer than 50ms, Power On Reset may not be activated and no internal registers are initialized. In this case all registers must be written through CPU interface. NOTE) For the stable operation after power up, we recommend to write all register value through CPU interface in any case after the power up. Recommended start up procedure The following start up procedure is recommended when AK2308LV is going to power up. Power up Wait 200ms - FS=”L” - BCLK=”L” During this stage, FS and BCLK must be tied to “L” not to receive or transmit the data from/to the external devices. *In case of VDD rising time =50ms(=5tau) Write data to the internal register through serial I/F - Write data to the internal register before CODEC starts working. Supply FS and BCLK - CODEC Initialization starts. Wait 250ms (min:130ms) - CODEC Initialization complete. CODEC starts working MS0227-E-01 2005/12 19 ASAHI KASEI [AK2308LV] ELECTRICAL CHARACTERISTICS o Unless otherwise noted, guaranteed for VDD=+3.3V+/-0.3V(AK2308LV), Ta = –10 ~ +85 C, FS=8kHz. ♦DC Characteristics Parameter Power Consumption Symbol Conditions * Note1) Idd BCLK=2048kHz Output High Voltage (CMOS level) Output Low Voltage (CMOS level) Input High Voltage1 (CMOS level) Input Low Voltage1 (CMOS level) Analog Ground (RAGND) Output Voltage Input Leakage Current Output Leakage Current VOH VOL IOH=-1.6mA Min Typ Max - 17 26 VDD-0.5 0.4 0.7VDD Ii Io Maximum output current ±100µA 1.4 -10 -10 Tri-state mode V V VIL1 VRG mA V IOL=1.0mA VIH1 Units 1.5 0.3VDD V 1.6 V +10 +10 µA µA *Note1) All the output pins are unloaded. 1020Hz@0dBm0 sine wave from HANDT1,2, and A to A loop -backed to HANDR. All the volume gains are set to 0dB. The handset mic and receiver paths are only active. MS0227-E-01 2005/12 20 ASAHI KASEI [AK2308LV] ♦AC Characteristics Note) Otherwise specified, Ta=-10℃～+70 degree, VDD=3.3V +/- 0.3V(AK2308LV), VSS=0V, FS=8kHz are assumed. All the timing parameters are measured at VOH=VDD-0.5, VOL=0.4V. PCM Interface u/A-law mode（Long Frame ,Short Frame） & Linear PCM mode Items FS frequency BCLK frequency Note1) Clock width Falling/rising time Output delay Pin Name FS BCLK Parm. FFS FBCLK Conditions - MIN - TYP 8 64×N MAX - Unit kHz kHz BCLK FS,BCLK,DR DX DX WP TD TDX TDX2 Cl=50pF Cl=50pF 100 10 - 40 60 60 ns ns ns ns FS TFSS - 100 - - ns DR TDRS - 100 - - ns ns Setup time Hold time FS Low level width FS TFSH - 100 - - DR TDRH - 100 - - ns FS TWLFS - 1 - - BCLK Note1）Short Frame, Long Frame:64 x N kHz (N=1 to 32), Linear mode:64 x N kHz(N=2 to 32) AK130 B1ch/B2ch mode Items FS frequency Clock frequency Pulse width Falling/Rising time Output delay Setup time Pin Name FS BCLK BCLK FS,BCLK,DR DX DX FS Parm. FFS FBCLK WP TD TDX TDX2 TFSS Conditions CL=50pF CL=50pF - MIN - TYP 8 MAX - - 2.048 244 - 10 100 - 40 60 60 - Unit kHz kHz ns ns ns ns ns DR TDRS - 100 - - ns FS TFSH - 100 - - ns DR TDRH - 100 - - ns Hold time u/A-law PCM mode（Short Frame） & Linear PCM mode FFS TFSH TFSS TFSH TFSS FS WP WP BCLK FBCLK TDX TDX TDX2 DX TDRS TDRH DR MS0227-E-01 2005/12 21 ASAHI KASEI [AK2308LV] u/A law PCM mode（Long Frame） FFS FWLFS TFSH TFSS TFSH FS BCLK TDX TDX TDX TDX2 DX TDRS TDRH DR AK130 B1ch/B2ch mode FFS TFSH TFSS TFSH TFSS FS WP WP BCLK FBCLK TDX TDX TDX2 DX TDRS TDRH DR MS0227-E-01 2005/12 22 ASAHI KASEI [AK2308LV] CPU I/F Items SCLK pulse width* Falling/rising time Output delay Pin Name SCLK CSN,SCLK DATA DATA Parm. WPS TD TDA TDA2 Conditions CL=15pF CL=15pF MIN 60 - TYP - MAX 40 150 150 Unit ns ns ns Ns CSN TCSS - 60 - - ns DATA TDAS - 60 - - ns CSN TCSH - 60 - - ns DATA TDAH - 60 - - ns Setup time Hold time Note) ex; maximum SCLK=5. 0MHz(@50% duty), 4.34MHz(@40/60% duty) Data write cycle TCSH TCSH TCSS TCSS CSN WPS WPS SCLK FSCLK TDAS TDAH DATA Data read cycle TCSH TCSS CSN WPS TDA2 WPS SCLK FSCLK TDA TDAS TDA TDA TDAH DATA Instruction code, Address write Data read MS0227-E-01 2005/12 23 ASAHI KASEI [AK2308LV] ♦CODEC Absolute Gain (AK2308LV:VDD=3.3V +/-0.3V ) Parameter Conditions HANDT3 to DX 1020Hz 0dBm0 Analog Input Level MIC3 to DX input 1020Hz dBm0 input Absolute Transmit Gain u/A-law Maximum input level Analog Output Level Absolute Receive Gain Min Units Vrms -1.5 - +1.5 dB 0.145 Vrms 0.482 DR to DAOUT 1020Hz 0dBm0 input -1.5 Maximum Overload Level DR to DAOUT +3.14dBm0 input - Vrms +1.5 0.694 Gain Tracking Parameter Conditions Transmit Gain Tracking Error Reference Level: -51dBm0 ~-46dBm0 ( A to D ) -10dBm0 -46dBm0 ~-36dBm0 HANDT3 to DX, MIC3 to DX 1020Hz Tone -36dBm0 ~ 0dBm0 Receive Gain Tracking Error Reference Level: -51dBm0 ~-46dBm0 ( D to A ) -10dBm0 -46dBm0 ~-36dBm0 DR to DAOUT 1020Hz Tone -36dBm0 ~ 0dBm0 The characteristics from MIC3 to DR path is guaranteed by the design. HANDT3 to DX MIC3 to DX Receive Frequency Response ( D to A ) DR to DAOUT Max 0.101 3.17dBm0(u-law) 3.14dBm0(A-law) Frequency Response Parameter Transmit Frequency Response ( A to D ) Typ Conditions Relative to: 0.06kHz 0dBm0@1020Hz 0.2kHz 0.3 ~3.0kHz 3.4kHz 3.78kHz Relative to: 0.3K ~3.0kHz 0dBm0@1020Hz 3.4kHz 3.78kHz Distortion Parameter Conditions Transmit Signal to Distortion 1020Hz Tone -36dBm0 ~-41dBm0 ( D to A ) -26dBm0 ~-36dBm0 HANDT3 to DX 0dBm0 ~-26dBm0 MIC3 to DX Receive Signal to Distortion 1020Hz Tone -36dBm0 ~-41dBm0 ( A to D ) -26dBm0 ~-36dBm0 DR to DAOUT 0dBm0 ~-26dBm0 Note) C-message Weighted for u-Law, Psophometric Weighted for A-Law MS0227-E-01 dB Vrms Min -0.9 -0.6 -0.4 -0.9 -0.6 -0.4 Typ - Max 0.9 0.6 0.4 0.9 0.6 0.4 Min 24 0 -0.3 0 6.5 -0.3 0 6.5 Typ - Max 2.5 0.3 0.8 0.3 0.8 - Min 24 29 35 Typ - Max - 24 29 35 - - Units dB dB Units dB dB Units dB dB 2005/12 24 ASAHI KASEI [AK2308LV] Noise Parameter Conditions Min Typ Max Units 1) Idle Channel Noise u-law, C-message 8 16 dBrnC0 AtoD HANDT1,2 to DX A-law, Psophometric -82 -74 dBm0p MIC2 to DX 2) Idle Channel Noise u-law, C-message 2 9 dBrnC0 DtoA A-law, Psophometric -88 -81 dBm0p DR to DAOUT 2) Idle Channel Noise u-law, C-message 3 10 dBrnC0 DtoA A-law, Psophometric -87 -80 dBm0p DR to HANDR DR to SPOP/SPON Note 1) Analog Input = Analog Ground. The gain of Handset MIC and MIC input is assumed as +25dB. SCLK is not supplied. Note 2) Digital Input(DR) = +0 Code Interchannel Crosstalk Parameter Transmit to Receive HANDT3 to DAOUT MIC3 to DAOUT Receive to Transmit DX to DR Conditions 0dBm0@HANDT4, Idle PCM code@DR 0dBm0 code@DR, HANDT4 = 0 Vrms Min - Typ -70 Max - - -70 - Min typ -1.0 0 +1.0*) dB -1.0 0 +1.0*) -1.5 0 +1.5 -1.0 0 +1.0 Units dB dB ♦Voice Path RX voice path Volume Parameter Step margin Volume Conditions VOL1 1020Hz 0dBm0 input at DR +12to-12dB Relative to: 0dB VOL2 1020Hz 0dBm0 input at DR +8to-12dB Relative to: 0dB -14to-18dB VOL3 1020Hz 0dBm0 input at DR +6/0/-6dB Relative to: 0dB max Unit dB dB *)Monotonus increase/decrease is guaranteed RX Amp for Handset receiver Parameter SINAD HANDI to HANDR Gain error Gain error TONEI to HANDR (-25dB gain) Signal attenuation HANDI to of speaker mute HANDR TONEI to HANDR Conditions 1.0Vp-p@1020Hz input (0 to 30kHz) 1.0Vp-p@1020Hz input (0 to 30kHz) MIN 40 -1.5 -2 TYP 0 0 MAX 2.0Vp-p@1020Hz input SW4: 0 to 1 1.0Vp-p@1020Hz input SW6:0 to 1 60 - - 40 - - MS0227-E-01 Unit dB +1.5 +2 2005/12 25 ASAHI KASEI RX Amp for Speaker output Parameter SINAD SPI to SPOP/SPOP Gain error Gain error TONEI to SPOP/SPON Signal attenuation SPI to of speaker mute SPOP/SPON TONEI to SPOP/SPON [AK2308LV] Conditions 1.0Vp-p@1020Hz input (0 to 30kHz) 1.0Vp-p@1020Hz input (0 to 30kHz) 2.0Vp-p@1020Hz input SW3: 0 to 1 1.0Vp-p@1020Hz input SW5:0 to 1, SW7: 0 to 1 MIN 40 -1.5 -1.5 TYP 0 0 MAX 60 - - 60 - - Conditions 0.564Vp-p@1020Hz input, +11dB setting (0 to 30kHz) Invert amplifier MIN 40 -1.5 5 TYP 0 0 MAX Conditions 0.023Vp-p@1020Hz input, +25dB setting (0 to 30kHz) Invert amplifier MIN 40 -1.5 0 TYP 0 0 MAX MIN 60 TYP - MAX - 60 - - MIN 7 7 1 52 70 70 TYP 10 10 75 100 100 MAX 15 15 113 150 150 Unit dB +1.5 +1.5 RX Amp SINAD Gain error gain Parameter RAI to RAO TX Amp for Handset / MIC Amp Parameter SINAD HANDT2 to HANDT1, Gain error MIC2 to MIC1 gain TX path switching summing amplifier characteristics Parameter Conditions Signal attenuation HANDT3 to DX 1020Hz@0dBm0 input of path switching SW1: 0 to 1 MIC3 to DX 1020Hz@0dBm0 input SW2: 0 to 1 Input impedance Parameter Input impedance HANDT3 MIC3 RAI SPI HANDI TONEI Conditions MS0227-E-01 Unit dB +1.5 11 Unit dB +1.5 25 Unit dB Unit kΩ kΩ MΩ kΩ kΩ kΩ 2005/12 26 ASAHI KASEI [AK2308LV] APPLICATION CIRCUIT EXAMPLE l Transmit side pins 1uF 1uF MIC3 MIC1 20kΩ 100pF 10uF HANDT1 20kΩ MIC2 10uF 1.2kΩ l HANDT3 100pF HANDT2 1.2kΩ Receive side pins DAOUT 1uF 20kΩ RAIN 1uF 35k～71kΩ Speaker equivalent circuit 15Ω SPOP RAO 1uF 0.1mH 2kΩ 50pF SPI 15Ω HANDI SPON Handset equivalent circuit 1uF HANDR 10kΩ Tone input 1uF MS0227-E-01 TONEI 2005/12 27 ASAHI KASEI l [AK2308LV] Analog Ground, PLLCAP PLLCAP 0.22uF RAGND 1uF VREF 1uF Please place the capacitor closer to the pins. l Power Supplies VDD 10uF 0.1uF VSS AVDD 10uF 0.1uF AVSS Please adjust capacitors in response to the noise environment on the power source. MS0227-E-01 2005/12 28 ASAHI KASEI [AK2308LV] PACKAGE 30pin VSOP Marking (1) Pin#1 indicator (2) Date code: XXXXXXX (7digit) (3) Marketing code: AK2308LV (4) AKM Logo AK2308LV AK2308LV AKM AK2308LV XXXXXXX 1pin Date code & Lot# MS0227-E-01 2005/12 29 ASAHI KASEI [AK2308LV] Package dimensions 30pin VSOP (Unit: mm) 0.3TYP 16 1 A 7.6±0.3 5.6±0.2 30 15 0.22±0.1 0.13 M 0.65 Detail A +0.1 0.1 -0.05 0.45±0.2 9.7±0.2 1.6MAX 1.2±0.2 10.2MAX +0.1 0.15 -0.05 MS0227-E-01 2005/12 30 ASAHI KASEI [AK2308LV] IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0227-E-01 2005/12 31