ASAHI KASEI [AK2306/LV] AK2306/2306LV Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER FEATURE GENERAL DESCRIPTION AK2306 is a dual PCM CODEC-Filter most suitable for ISDN Terminal Adapter. - Dual It includes Selectable A-law/u-law function, Internal Gain Adjustment from +6dB to –18dB by 1dB step control, Selectable 16Hz/20Hz Ring Tone Generator for SLIC. All of these functions are controlled by the internal register accessed through the serial interface. PCM interface of AK2306 accepts Long Frame, Short Frame clock formats and GCI format. 64 x N kHz(128k-4096kHz) clock input is available for PCM interface. AK2306 and AK2306LV are pin-compatible, but different products which power supply voltage are 5.0V and 3.3V,respectively. PCM CODEC and Filtering systems for ISDN Terminal Adapter - Selectable Ring Tone Generator for SLIC 16Hz or 20Hz tone is available. - Independent functions on each channel controlled by the internal register - Power Down Mode - Mute - Gain Adjustment: +6 to -18dB (1dB step) - Selectable PCM Data Interface Timing: Long Frame / Short Frame/GCI - Variable PCM Data Rate: 64k x N [Hz] (128k - 4.096MHz) - OP Amp for External Gain Adjustment - A-law/u-law Register Selectable - Serial Interface to access the internal register - Power on Reset - Single Power Supply Voltage - +5.0V ± 5% (AK2306) - +3.3V ± 0.3V (AK2306LV) - Low Power Consumption PACKAGE - 24pinSSOP 8 .2 x 7.9 mm (0.65mm pin pitch) <MS0093-E-07> 1 2012/01 ASAHI KASEI [AK2306/LV] CONTENTS ITEMS PAGE - BLOCK DIAGRAM….…………..……………………… 3 - PIN ASSIGNMENT….……………………………..…… 4 - PIN CONDITION……...………………………………… 5 - PIN FUNCTION…….…………………………………… 6 - CIRCUIT DESCRIPTION….….……………………...… 8 - FUNCTIONAL DESCRIPTION…….…..……………… 9 - PCM INTERFACE……….…………………….... 9 LONGFRAME/SHORTFRAME/GCI - MUTE…………………………………….……… 12 - GAIN ADJUSTMENT….…..…………………… 13 - RING TONE GENERATOR .......................... 14 - RESET 15 ....................................................... - POWER DOWN……..……………………..…… 16 - SERIAL INTERFACE………….………….…… 18 - REGISTER……….……………………………………… 22 - ABSOLUTE MAXIMUM RATINGS……..…………..… 25 - RECOMMENDED OPERATING CONDITIONS…….. 25 - ELECTRICAL CHARACTERISTICS……..………...… 25 - APPLICATION CIRCUIT EXAMPLE…..…………...… 34 - PACKAGE INFORMATION……..…………………..… 36 <MS0093-E-07> 2 2012/01 ASAHI KASEI [AK2306/LV] BLOCK DIAGRAM GST0 VFTP0 VFTN0 VR0 VFR0 GSR0 GST1 VFTP1 VFTN1 VR1 VFR1 GSR1 GA0T AAF0 GA0R SMF0 DX DR FS BCLK GA1T AAF1 GA1R SMF1 CODEC AMPT1 CH1 FS1 AMPR1 RING TONE GENERATOR BGREF Power on Reset Register 3 A/u_SEL Internal Register PWDN Mut1 Mut0 TXVlm1 TXVlm0 RXVlm1 PLL VDD VSS <MS0093-E-07> FS0 AMPR0 RXVlm0 LPC PCM I/F CH0 TNOUT VREF CODEC AMPT0 Serial I/F SCLK DATA CSN 2012/01 ASAHI KASEI [AK2306/LV] PIN ASSIGNMENT VFTP1 VFTN1 GST1 GSR1 VFR1 VR1 VDD FS BCLK DX DR TNOUT <MS0093-E-07> 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 4 VREF VFTP0 VFTN0 GST0 GSR0 VFR0 VSS VR0 LPC CSN DATA SCLK 2012/01 ASAHI KASEI [AK2306/LV] PIN CONDITION Pin# Name I/O Pin type AC load (MAX.) DC load (MIN.) Outout status (Power down mode) Output status (Reset) Remarks VFTP1 Analog VFTN1 Analog GST1 50pF Analog Hi-Z Hi-Z 10kΩ(*1) GSR1 50pF O Analog Hi-Z Hi-Z 10kΩ (*1) VFR1 I Analog VR1 50pF O Analog Hi-Z Hi-Z 10kΩ VDD FS I TTL/CMOS(*3) BCLK I TTL/CMOS(*3) DX 15pF O CMOS Hi-Z Hi-Z DR I TTL/CMOS(*3) TNOUT 15pF O CMOS L L SCLK I TTL/CMOS(*3) DATA 15pF I/O TTL/CMOS(*3) Input Input CSN I TTL/CMOS(*3) LPC O Analog 0.22uF (*2) VSS VR0 50pF O Analog Hi-Z Hi-Z 10kΩ VFR0 I Analog GSR0 50pF O Analog Hi-Z Hi-Z 10kΩ (*1) GST0 50pF I Analog Hi-Z Hi-Z 10kΩ (*1) VFTN0 O Analog VFTP0 O Analog VREF O Analog 1.0 uF (*2) *1) DC load(MIN.) includes a feedback resistance of input/output op-amp. *2)External capacitance should be connected to VSS. *3)TTL level is applied only for the input level of AK2306. Output level for both AK2306 and AK2306LV,and the input level of AK2306LV are CMOS level. <MS0093-E-07> 5 2012/01 ASAHI KASEI [AK2306/LV] PIN FUNCTION Pin# Name 1 VFTP1 I/O I 2 VFTN1 I 3 GST1 O 4 GSR1 O 5 VFR1 I 6 VR1 O 22 VFTN0 I 23 VFTP0 I 21 GST0 O 17 VR0 O 19 VFR0 I 20 GSR0 O 10 DX O 11 DR I 8 FS I 9 BCLK I <MS0093-E-07> Function Positive analog input of the transmit OPamp(AMPT1) for channel 1. Transmit gain is defined by the ratio of R2/R1. R1 is the external input resister connected to this pin. R2 is the external feedback resister connected between this pin and GST1. Negative analog input of the transmit OPamp(AMPT1) for channel 1. Output of the transmit OPamp(AMPT1) for channel 1. The external feedback resister is connected between this pin and VFTP1. Output of the receive OPamp(AMPR1) for channel 1. Negative analog input of the receive OPamp(AMTR1) for channel 1. Receive gain is defined by the ratio of R4/R3. R3 is the external input resister connected to this pin. R4 is the external feedback resister connected between this pin and VR1. Analog Output equivalent to the received PCM data for channel 1. Output gain is adjusted by the GA1R. Negative analog input of the transmit OPamp(AMPT0) for channel 0. Transmit gain is defined by the ratio of R2/R1. R1 is the external input resister connected to this pin. R2 is the external feedback resister connected between this pin and GST0. Positive analog input of the transmit OPamp(AMPT0) for channel 0. Output of the transmit OPamp(AMPT0) for channel 0. The external feedback resister is connected between this pin and VFTP0. Analog Output equivalent to the received PCM data for channel 0. Output gain is adjusted by the GA0R Negative analog input of the receive OPamp(AMTR0) for channel 0. Receive gain is defined by the ratio of R4/R3. R3 is the external input resister connected to this pin. R4 is the external feedback resister connected between this pin and VR0. Output of the receive OPamp(AMPR0) for channel 0. Serial output of PCM data. The channel 1 data is output following the channel 0 data. The PCM data rate is synchronized with BCLK. This output remains in the high impedance state except for the period of transmitting PCM data. Serial input of PCM data. The channel 1 data is received following the channel 0 data. The PCM data rate is synchronized with BCLK. Frame sync input. This clock is input for the internal PLL which gerenates the internal system clocks. FS must be 8kHz clock which is synchronized with BCLK. Bit clock of PCM data interface. This clock defines the input/output timing of DX and DR. The frequency of BCLK should be 64 x N kHz(128k – 4096kHz). 6 2012/01 ASAHI KASEI Pin# Name 12 TNOUT [AK2306/LV] I/O O Function Ring Tone output pin. 16Hz or 20Hz tone is selected by the internal register. Data input of serial interface. 14 DATA I/O 13 SCLK I Clock input of serial interface. 15 CSN I Read and write enable of serial interface. 16 LPC O 24 VREF O 7 VDD - 18 VSS - Pin for PLL loop filter. External capacitance(Min 0.22uF) should be connected between this pin and VSS. Analog ground output. External capacitance(1.0 uF) should be connected between this pin and VSS. Positive supply voltage. +5V(AK2306) or +3.3V(AL2306LV) supply. Ground. <MS0093-E-07> 7 2012/01 ASAHI KASEI [AK2306/LV] CIRCUIT DESCRIPTION Block AMPT0,1 AMPR0,1 AAF A/D D/A SMF BGREF RING TONE GENERATOR GA0T/R GA1T/R GATN SERIAL I/F PLL PCM I/F <MS0093-E-07> Function Op-amp for input gain adjustment. This op-amp has differential inputs. Adjusting the gain with external resistors. The resistor larger than 10kΩ is recommended for the feedback resistor. <NOTE> AMPT0(1) becomes automatically power down, when CODEC ch0(1) is power down. Op-amp for output gain adjustment. This op-amp is used as an inverting amplifier. Adjusting the gain with external resistors. The resistor larger than 10kΩ is recommended for the feedback resistor. Integrated anti-aliasing filter which prevents signals around the sampling rate from folding back into the voice band. AAF is a 2nd order RC low-pass filter. Converts analog signal to 8bit PCM data according to the companding schemes of ITU recommendation G.711; A-law or u-law. The band limiting filter is also integrated. The selection of companding schemes is set by ALAWN register as follows: "H": u-Law "L": A-Law Expands 8bit PCM data according to A-law or u-law. The selection of companding schemes is set by ALAWN register as follows: "H": u-Law "L": A-Law Extracts the inband signal from D/A output. It also corrects the sinx/x effect of D/A output. Provides the stable analog ground voltage using an on-chip band-gap reference circuit which is temperature compensated. The output voltage is 2.4V for +5V operation(AK2306) or 1.5V for +3.3V operation(AK2306LV). Generates two kinds of tone; 16Hz or 20Hz. Tone selection and Tone ON/OFF is controlled by the registers. Gain selects of analog I/O signals. It is posibble to select gain from +6dB to -18dB (1dB/step). Gain is defined by the internal register. Interface to the internal register by using SCLK, DATA, and CSN pins. PLL generates system clock of AK2306. Reference clock is FS (8KHz). More than 0.22uF of an external capacitance should be connected between LPC and VSS. PCM data rate is available for 64xN(N = 2 to 64)kHz which synchronizes with BCLK. Two kinds of data format (Long Frame, Short Frame) are available. Each data format is automatically detected. PCM data stream, which includes ch0 and ch1 data, is output through DX pin and input through DR pin. Ch1 PCM data stream always follows ch0 PCM data stream. 8 2012/01 ASAHI KASEI [AK2306/LV] FUNCTIONAL DESCRIPTION PCM Data Interface AK2306 supports the following 3 PCM data formats - Long Frame Sync(LF) - Short Frame Sync(SF) - GCI PCM data of both channels are multiplexed and interfaced through the common pins(DR,DX).The first 8bit is defined as B1 channel and the seconds 8bit is defined as B2 channel in the PCM data stream. The order of PCM data is MSB first in each channel. Selection of the interface mode The GCI and ordinary PCM interface(LF,SF) are selectable through the CPU register as following table. LF and SF is automatically selected by AK2306 by means of detecting the length of 8KHz frame signal. Register for PCM Interface mode select (Address:101 Bit:0) PCMIF PCM Interface 0 LF or SF 1 GCI Comments LF/SF are selected automatically ∗ Default on power-on reset =LF/SF mode(PCMIF=0). LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic LF/SF selection AK2306 monitors the duration of the “H” level of FS and automatically selects LF or SF interface format. period of FS=”H” Interface format more than 2 clocks of BCK LF 1 clock of BCK SF Timing of the interface 8 bits PCM data is accommodated in 1 frame( 1 25us ) defined by 8kHz frame sync signal. Although there are 64 time slots at maximum in 8kHz frame(when BCK=4.096MHz), PCM data for AK2306 occupy first and second time slot for channel 0 and channel 1,respectively as is indicated in figures of next page. - Frame Sync signal (FS) 8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal clock of the LSI is generated based on this FS signal. - Bit Clock (BCLK) BCLK defines the PCM data rate. BCLK can be varied from 128kHz to 4.096MHz by 64kHz step. - Position of the Ch0,Ch1 PCM data in the DX/DR data flow B1 and B2 channel of the PCM data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B register. <MS0093-E-07> 9 2012/01 ASAHI KASEI [AK2306/LV] CH0,1selection (Address:100 Bit:5) SEL2B CH0 CH1 0 B1 B2 1 B2 B1 Remarks Default on Reset <2ch Multiplexed> LongFrame FS BCLK B1 ch DX DR Don’t care B2 ch 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SEL2B=0 SEL2B=1 => => B1-CHANNEL (CH0) B1-CHANNEL (CH1) Don’t care B2-CHANNEL (CH1) B2-CHANNEL (CH0) ShortFrame FS BCLK B2 ch B1 ch DX DR Don’t care SEL2B=0 SEL2B=1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 => => B1-CHANNEL (CH0) B1-CHANNEL (CH1) Don’t care B2-CHANNEL (CH1) B2-CHANNEL (CH0) <Non Multiplex> Not supported ! Important Notice Please don’t stop feeding FS and BCLK except Full power down mode. Internal PLL does free running when either FS or BCLK is not provided. In this case, the frequency of Ring Tone output is not guaranteed. <MS0093-E-07> 10 2012/01 ASAHI KASEI [AK2306/LV] GCI ( General Circuit Interface ) GCI format is used for ISDN applicat ion. The data format and clocking is showed as Fig X. timing of the interface 8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal. Although there are 32 time slots at maximum in 8kHz frame(when BCK=4.096MHz), PCM data on GCI occupy first and second time slot for channel 0 and channel 1,respectively. Frame Sync signal (FS) 8kHz reference signal. This signal indicated the timing and the frame position of 8kHz GCI. All the internal clock of the LSI is generated based on this FS signal. High level duration of the FS is 1 clock period of BCLK. Bit Clock (BCLK) BCLK defines the GCI data rate. The bit rate of GCI data is half of BCLK. BCLK can be varied from 512kHz to 4.096MHz by 128kHz step. Position of the Ch0,Ch1 GCI data in the DX/DR data flow B1 and B2 channel of the GCI data channel are assigned to Analog Ch0 and Ch1 as is defined by SEL2B register as same way as PCM interface. CH0,1selection( Address:100 Bit:5) SEL2B CH0 CH1 0 B1 B2 1 B2 B1 Remarks Default on Reset <2ch Multiplex> FS BCLK B1 ch DX DR Don’t care B2 ch 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SEL2B=0 SEL2B=1 => => B1-CHANNEL (CH0) B1-CHANNEL (CH1) Don’t care B2-CHANNEL (CH1) B2-CHANNEL (CH0) <Non Multiplex> Not supported ! Important Notice Please don’t stop feeding FS and BCLK except Full power down mode. Internal PLL does free running when either FS or BCLK is not provided. In this case, the frequency of Ring Tone output is not guaranteed. <MS0093-E-07> 11 2012/01 ASAHI KASEI [AK2306/LV] MUTE The output on each channel can be muted independently through the CPU register as shown in the table. Mute register( Address:100 Bit:5,4 ) MTCH0,1 Operation DX pin VRX pin 0 Normal PCM data output CODEC analog output 1 Mute High-Impedance(* 1) AGND* (*1) MTCH0 and MTCH1 are the mute control bit for CH0 and CH1,respectively. B1 and B2 channel muted by MTCH0/1 is defined by SEL2B bit shown in the PCM Interface section. <EXAMPLE> LF Mode CH0 mute (MTCH=1, MTCH1=0, SEL2B=0) FS0 BCLK DX Don’t care DR 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 B1-CHANNEL(CH0) <SEL2B=”0”> Don’t care B2-CHANNEL(CH1) <SEL2B=”0”> VRX0 : CODEC CH0 analog output is always at AGND level. VRX1 : CODEC CH1 analog output is the signal converted from the PCM data of CH1 input through DR pin. GCI mode CH0 mute (MTCH0=1, MTCH1=0, SEL2B=0) FS0 BCLK DX Don’t care DR 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 B1-CHANNEL(CH0) <SEL2B=”0”> Don’t care B2-CHANNEL(CH1) <SEL2B=”0”> VRX0 : CODEC CH0 analog output is always at AGND level. VRX1 : CODEC CH1 analog output is the signal converted from the PCM data of CH1 input through DR pin. <MS0093-E-07> 12 2012/01 ASAHI KASEI [AK2306/LV] GAIN ADJUSTMENT Analog input/output gain can be adjusted at the range from +6dB to –18dB by 1.0dB step through CPU register. VR Register( Address:011 –000 Bit:4 –0) GanT4 GanR4 GanT3 GanR3 GAnT2 GAnR2 GAnT1 GAnR1 GAnT0 GAnR0 Gain [dB] 0 0 0 0 0 +6 0 0 0 0 1 +5 0 0 0 1 0 +4 0 0 0 1 1 +3 0 0 1 0 0 +2 0 0 1 0 1 +1 0 0 1 1 0 0 0 0 1 1 1 -1 0 1 0 0 0 -2 0 1 0 0 1 -3 0 1 0 1 0 -4 0 1 0 1 1 -5 0 1 1 0 0 -6 0 1 1 0 1 -7 0 1 1 1 0 -8 0 1 1 1 1 -9 1 0 0 0 0 -10 1 0 0 0 1 -11 1 0 0 1 0 -12 1 0 0 1 1 -13 1 0 1 0 0 -14 1 0 1 0 1 -15 1 0 1 1 0 -16 1 0 1 1 1 -17 1 1 --- --- --- -18 <MS0093-E-07> 13 Remarks Default 2012/01 ASAHI KASEI [AK2306/LV] RING TONE GENERATOR Ring tone generator generates two kinds of ring tone, 16Hz and 20Hz. The frequency of the tone can be selected by CPU register. Tone frequency selection Tone Selection register (Address: 101, Bit: 3) TNFQ Tone Frequency Remarks 0 16Hz Default 1 20Hz Tone output enable Tone output can be enabled/disabled through CPU register. RING TONEGEN Enable (Address: 100, Bit: 2) PDTN RING TONE GENERATOR Remarks 1 Power Down* Default 0 Tone output enabled * When Power down is selected, TNOUT pin output is fixed to “L” level. <MS0093-E-07> 14 2012/01 ASAHI KASEI [AK2306/LV] RESET Power on Reset AK2306 automatically generates the internal reset pulse which resets all the circuit that is necessary to start the initialization after the power on reset. The CPU registers are set to the default value. After the internal reset pulse is generated, CODEC Ch0/Ch1 starts the initialization procedure by being fed FS signal, and it takes 180ms( typ.), 350ms(max) to complete the initialization after the detectio n of power on. Power up slope to enable the Power-on Reset When power-up slope is no longer than 50ms(=5tau:tau is time constant), Power On Reset works normally. When the time is longer than 50ms, Power On Reset is not activated and no internal registers are initialized. In this case all registers must be written through CPU interface. NOTE) For stable operation after power up, we recommend to write all register value through CPU interface after power up. Recommended start up procedure The following start up procedure is recommended when AK2306/LV is going to power up. Power up Wait 200ms *In case of VDD rising time =50ms(=5tau) Write data to the internal register through serial I/F - FS=”L” - BCLK=”L” When 1stFS and BCLK are set to “L”, CODEC ch0,ch1 dose not interface with external devices. - Write data to the internal register before CODEC starts working. Supply FS and BCLK - CODEC Initialization starts. Wait 130ms - CODEC Initialization complete. CODEC starts working <MS0093-E-07> 15 2012/01 ASAHI KASEI POWER [AK2306/LV] DOWN Power consumption is reduced in the power down mode. In the power down mode, the current fed to analog circuits and the clock for digital circuits, are stopped, and the relating circuits hold its status. There are two power down modes. - Power down for all circuits - Power down by block * In the power down mode, the output pins of corresponding blocks turn to Hi-Z except TNOUT pin.(See page 5) POWER DOWN MODE SETTING 2 power down modes Mode Circuits Registers All circuit All PD CODEC CH0 PDCH0 CODEC CH1 PDCH1 RING TONEGEN PDTN Block Operation for “0”/”1” ”0” : Normal ”1” : Power down ”0” : Normal ”1” : Power down Note - CPU Registers are not reset. - Serial I/F is available. - No need to supply FS, BCLK. - Keep supplying FS, even when CODEC CH0,1 are in power down mode (see page10,11). - When CODEC CHn(n=0,1) is in power down mode, the functions below are active: (1) AMPTn(n=0,1) Input/Output (2) TNOUT Output Please refer next page table in deltail. CANCELLATION OF POWER DOWN : CODEC When power down mode for CODEC CH0/CH1 is cleared, the CODEC circuitry starts to be initialized. It takes 130mS(typ.). When full circuit power down mode for CODEC is cleared, AK2306/LV starts the same wake up sequence as one at power on. It takes 250ms(Typ) Wake up time for Tone generator is 125us(Typ). <MS0093-E-07> 16 2012/01 ASAHI KASEI POWER DOWN BLOCK Channel 1 Channel 0 REGISTER [AK2306/LV] ALL BLOCK PD CODEC CH0 CODEC CH1 CODEC CH0&1 RING TONEGEN PDCH0 PDCH1 PDCH0 PDCH1 PDTN AMPT0 OFF GA0T OFF OFF OFF AAF0 OFF OFF OFF CODEC CH0 OFF OFF OFF SMF0 OFF OFF OFF GA0R OFF AMPR0 OFF AMPT1 OFF GA1T OFF OFF OFF AAF1 OFF OFF OFF CODEC CH1 OFF OFF OFF SMF1 OFF OFF OFF GA1R OFF AMPR1 OFF PCM I/F RING TONEGEN OFF OFF OFF PLL OFF BGREF OFF OFF SERIAL I/F <MS0093-E-07> 17 2012/01 ASAHI KASEI [AK2306/LV] SERIAL INTERFACE The internal registers can be read/written with SCLK, DATA, and CSN pins. 1word consists of 16bits. The first 4bits are the instruction code which specifies read/write. The following 3bits specify the address. The rest of 8bits are for setting registers. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 I3 I2 I1 I0 A2 A1 A0 * D7 D6 D5 D4 D3 D2 D1 D0 Instruction code (4bit) Address (3bit) Data for internal registers (8bit) * *)Dummy bit for adjusting the I/O timing when reading register. INSTRUCTION CODEC I3 I2 I1 I0 1 1 1 0 1 1 1 1 Read/Write Read Write No action Other codes SCLK and WRITE/READ (1) Input data are loaded into the internal shift register at the rising edge of SCLK. (2) The rising edge of SCLK is counted after the falling edge of CSN. (3) When CSN is “L” and more than 16 SCLK pulses: [WRITE] Data are loaded into the internal register at the rising edge of the SCLK 16th pulse. [READ] DATA pin is switched to an input pin at the falling edge of the SCLK 16th pulse. CSN and WRITE / READ CANCELLATION th (1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16 pulse. th (2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16 pulse. SERIAL WRITE / READ (SERIAL ACCESS) (1) CSN must go up to “H” before the next access in successive access. (2) When the next access is going to be done , if CSN remains to be “L”, successive access can not be done. <MS0093-E-07> 18 2012/01 ASAHI KASEI [AK2306/LV] WRITE Continuous SCLK Goes up anytime after SCLK 16th pulse Must goes up once CSN SCLK 1 Z DATA 2 1 3 1 4 1 5 1 6 0 Instruction Code 7 0 8 0 9 D7 * Z D0 Write data to address”000” Address “000” 1 16 2 1 WRITE at the rising edge of SCLK 16th pulse 1 3 1 4 8 1 9 D7 15 D1 16 D0 Z Write data Instruction Code Burst SCLK SCLK can be stop at “H” level or “L” level at anytime during the write cycle. A fter resuming the SCLK, write cycle is retrieved normally. Goes up anytime after SCLK 16th pulse Must go up once CSN SCLK 1 Z DATA 2 1 3 1 4 1 5 1 6 0 Instruction Code 7 0 8 0 9 16 D7 * D0 Write data to address “000” Address ”000” Z WRITE at the rising edge of SCLK 16th pulse CANCELLATION CSN goes “H” before the rising edge of 16th SCLK pulse CSN SCLK DATA 1 Z 1 2 1 3 1 Instruction Code <MS0093-E-07> 4 1 5 0 6 0 Address ”000” 7 0 8 * 9 D7 16 Z D0 Write data to address”000” Write is not Excuted 19 Z DATA pin: Input mode (Hi-Z) 2012/01 ASAHI KASEI [AK2306/LV] SERIAL ACCESS Serial access with CSN staying “L” during the serise of write cycle. CSN SCLK DATA 1 Z 2 1 1 3 1 4 1 Instruction Code 5 0 6 7 0 0 8 D7 * Address ”000” 9 1 16 Z D0 2 1 Write data to Address”000” 3 1 4 1 8 1 9 15 D1 D7 16 Z D0 Write data Instruction Code EXCUTE! NOT EXCUTED! READ CONTINOUS SCLK Can be going up at anytime after SCLK 16th pulse Must go up once CSN SCLK DATA 1 Z 2 1 1 3 1 4 0 Read Instruction 5 6 7 A2 A1 A0 8 Z 9 D7 16 1 Z D0 1 1 3 1 4 0 Read Instruction Read Data Address 2 8 9 D7 15 16 D1 D0 Z Read Data Read period until the earlier edge of either CSN rising or SCLK 16th pulse falling Data output starts at the falling edge of SCLK 8th pulse Burst SCLK Can be going up at anytime after SCLK 16th pulse Must go up once CSN SCLK DATA 1 Z 2 1 1 3 1 Read Instruction 4 0 5 6 7 A2 A1 A0 Address 9 8 Z 16 D0 D7 Z Read Data Read output starts at the falling edge of SCLK 8th pulse <MS0093-E-07> 20 2012/01 ASAHI KASEI [AK2306/LV] SERIAL ACCESS Serial access with CSN staying “L” during the serise of read cycle. CSN SCLK DATA 1 Z 1 2 1 3 1 4 0 Read Instruction 5 0 6 0 7 0 8 Z 9 D7 16 1 Z D0 1 3 1 4 8 9 15 16 Z 0 Read Instruction Read data Address ”000” 1 2 READ EXCUTED! READ NOT EXCUTED! DISCORD OF INSTRUCTION CODE CSN SCLK DATA Z 1 2 3 4 5 I3 I2 I1 I0 A2 IInstructions except specified 0bbb 10bb 110b (b=0 or 1) <MS0093-E-07> 6 7 8 9 16 Z A1 A0 Address WRITE/READ NOT EXCUTED! Z 21 DATA pin: Input mode (Hi-Z) 2012/01 ASAHI KASEI [AK2306/LV] REGISTER MAP Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A2 A1 A0 * D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 * 0 0 - GA0R4 GA0R3 GA0R2 GA0R1 GA0R0 0 0 1 * 0 0 - GA1R4 GA1R3 GA1R2 GA1R1 GA1R0 0 1 0 * 0 0 - GA0T4 GA0T3 GA0T2 GA0T1 GA0T0 0 1 1 * 0 0 - GA1T4 GA1T3 GA1T2 GA1T1 GA1T0 1 0 0 * 0 0 MTCH1 MTCH0 PD PDTN PDCH1 PDCH0 1 0 1 * 0 0 0 0 TNFQ ALAWN SEL2B PCMIF 1 1 0 * Reserved 1 1 1 * Reserved *)Dummy Bit Note) All registers except address(000 - 011), Bit5(D5) can be read/write. Note) Please write “all 0’s” for address(000 - 100), Bit7,6(D7,D6) and address(101), Bit7,6,5,4(D7 - D4) for normal operation. Note) Address(000 - 011),Bit5(D5) can not be write and “0” data will be output when it is accessed to rea d. INITIALIZATION OF REGISTERS The registers are initialized at POWER ON RESET only. Power on reset may not be excuted due to the difference of power up time constant. Thus it is highly recommended that all the register (address(000 – 101) ) are to be written at the time of the power up and after the abnormal circumstances happens such as micro interrupt of the power line or mal operation due to lightning. REGISTER FUNCTION Address 000 001 Bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 <MS0093-E-07> Name GA0R0 GA0R1 GA0R2 GA0R3 GA0R4 0 0 GA1R0 GA1R1 GA1R2 GA1R3 GA1R4 0 0 Default 0 1 1 0 0 Function Receive gain adjustment on ch0 +6 to –18dB by 1.0dB step 0 0 0 1 1 0 0 Test mode Please write all “0”. Receive gain adjustment on ch1 +6 to –18dB by 1.0dB step 0 0 Test mode Please write all “0”. Refer 00000: +6dB 11xxx: -18dB 00000: +6dB 11xxx: -18dB 22 2012/01 ASAHI KASEI Address 010 011 100 101 110 [AK2306/LV] Bit 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 Name GA0T0 GA0T1 GA0T2 GA0T3 GA0T4 0 0 GA1T0 GA1T1 GA1T2 GA1T3 GA1T4 0 0 PDCH0 PDCH1 Default 0 1 1 0 0 Function Transmit gain adjustment on ch0 +6 to –18dB by 1.0dB step 0 0 0 1 1 0 0 Test mode Please write all “0”. Transmit gain adjustment on ch1 +6 to –18dB by 1.0dB step 0 0 0 0 2 PDTN 1 3 PD 0 4 5 6 7 MTDX0 MTDX1 0 0 0 0 0 0 0 PCMIF 0 1 SEL2B 0 2 ALAWN 1 3 TNFQ 0 4 5 6 7 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Test mode Please write all “0”. CODEC CH0,1 Power down control 0: Power ON 1: Power OFF RING TONEGEN Power down control 0: Power ON 1: Power OFF Full Power down 0: Power ON 1: Power OFF Mute control: VR0.VR1,DX pin 0: Normal output 1: Mute Test mode Please write all “0”. PCM Interface select 0: LF/SF 1: GCI PCM data channel select 0: CH0 -> B1 1: CH1 -> B1 A/u-law select 0: A-law 1: u-law Tone frequency select 0: 16Hz 1: 20Hz Test mode Please write all “0”. <MS0093-E-07> Refer 00000: +6dB 11xxx: -18dB 00000: +6dB 11xxx: -18dB Reserved 23 2012/01 ASAHI KASEI Address 111 Bit [AK2306/LV] Name 0 1 2 3 4 5 6 7 <MS0093-E-07> Default 0 0 0 0 0 0 0 0 Function Reserved 24 Refer 2012/01 ASAHI KASEI [AK2306/LV] ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Power Supply Voltages Analog/Digital Power Supply VDD -0.3 6.5 VSS Voltage VSS -0.1 0.1 Digital Input Voltage VTD -0.3 VDD+0.3 Analog Input Voltage VTA -0.3 VDD+0.3 Input current (except power supply pins) IIN -10 10 Storage Temperature Tstg -55 125 Warning: Exceeding absolute maximum ratings may cause permanent damage. Normal operation is not guaranteed at these extremes. Units V V V V mA o C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supplies Analog/Digital power supply( AK2306 ) VDD Power Supplies Analog/Digital power supply( AK2306 LV) VDD Ambient Operating Temperature Ta Frame Sync Frequency FS Note) All voltages reference to ground : VSS=0V Min Typ Max Units 4.75 5.0 5.25 V 3.0 -40 3.3 3.6 85 V o C kHz 8 ELECTRICAL CHARACTERISTICS Unless otherwise noted, guaranteed for VDD=+5V +/– 5%(AK2306), VDD=+3.3V+/-0.3V(AK2306LV), o Ta = –40 ~ +85 C, FS=8kHz. DC Characteristics Parameter Power Consumption BCLK=2048kHz Output High Voltage (CMOS level) Output Low Voltage (CMOS level) Input High Voltage1 (CMOS level) Input High Voltage2 (TTL level) Input Low Voltage1 (CMOS level) Input Low Voltage2 (TTL level) Input Leakage Current Input Capacitance Output Leakage Current Power Consump.@PD <MS0093-E-07> Symbol Conditions PDD1 PDCH0,1 PDDT0,1=0,0 All output unloaded PDD2 PDCH0,1 PDDT0,1=1,0 All output unloaded VOH IOH=-1.6mA VOL Min Typ Max 65 mW 35 0.8VDD V IOL=1.6mA 0.4 VIH1 VIH2 V 2.4 V VIL2 -10 -10 - 25 V 0.7VDD VIL1 Ii Ci Io Tri-state mode PDDd Units 2.5 0.3VDD V 0.8 V +10 5 +10 - uA pF uA mW 2012/01 ASAHI KASEI CODEC [AK2306/LV] Absolute Gain ( AK2306: VDD=5.0V +/-5%, AK2306LV VDD=3.3V +/-0.3V ) Parameter Conditions Min Analog Input Level Input: AK2306 0dBm0@1020Hz AK2306LV Absolute Transmit Gain -0.6 Analog Output Level Input: AK2306 0dBm0@1020Hz AK2306LV Absolute Receive Gain -0.6 Maximum Overload Level +3.14dBm0 AK2306 AK2306LV Gain Tracking Parameter Transmit Gain Tracking Error Receive Gain Tracking Error Frequency Response Parameter Transmit Frequency Response Receive Frequency Response Distortion Parameter Transmit Signal to Distortion Receive Signal to Distortion Max Units Vrms 0.6 dB Vrms 0.6 dB Vrms Conditions Reference Level: -55dBm0 ~-50dBm0 -10dBm0 -50dBm0 ~-40dBm0 1020Hz Tone -40dBm0 ~ 3dBm0 Reference Level: -55dBm0 ~-50dBm0 -10dBm0 -50dBm0 ~-40dBm0 1020Hz Tone -40dBm0 ~ 3dBm0 Min -1.2 -0.4 -0.2 -1.2 -0.4 -0.2 Typ - Max 1.2 0.4 0.2 1.2 0.4 0.2 Conditions Relative to: 0.05kHz 0dBm0@1020Hz 0.06kHz 0.2kHz 0.3 ~3.0kHz 3.4kHz 4.0kHz Relative to: 0 ~3.0kHz 0dBm0@1020Hz 3.4kHz 4.0kHz Min -1.8 -0.15 -0.8 -0.15 -0.8 - Typ - Max -30 -26 0 0.15 0 -14 0.15 0 -14 Min 25 30 36 25 30 36 - Typ - Max -46 - -46 dB - -42 dB Conditions -40dBm0 ~-45dBm0 -30dBm0 ~-40dBm0 0dBm0 ~-30dBm0 1020Hz Tone -40dBm0 ~-45dBm0 -30dBm0 ~-40dBm0 0dBm0 ~-30dBm0 1020Hz Tone Single Frequency Distortion Transmit Single Frequency Distortion Receive Intermodulation Distortion -6dBm@860Hz,1380Hz Note) C-message Weighted for u-Law, Psophometric Weighted for A-Law <MS0093-E-07> Typ 0.849 0.531 0.849 0.531 1.219 0.762 26 Units dB dB Units dB dB Units dB dB dB 2012/01 ASAHI KASEI Envelope delay Distortion Parameter Transmit Delay, Absolute Transmit Delay, Relative Relative to f=1600Hz Receive Delay, Absolute Receive Delay, Relative Relative to f=1600Hz [AK2306/LV] Conditions f =1600Hz f =500Hz ~600Hz f =600Hz ~1000Hz f =1000Hz ~2600Hz f =2600Hz ~2800Hz f =2800Hz ~3000Hz f =1600Hz f =500Hz ~1000Hz f =1000Hz ~1600Hz f =1600Hz ~2600Hz f =2600Hz ~2800Hz f =2800Hz ~3000Hz Min - Typ - Units us - Max 560 220 145 75 105 155 450 90 125 175 Typ 5 -85 5 -85 - Max 10 -80 10 -80 -53 Units dBrnC0 dBm0p dBrnC0 dBm0p dBm0 -40 -30 - us us us Noise Parameter 1) Idle Channel Noise A!D 2) Idle Channel Noise D!A Noise, Single Frequency Conditions u-law, C-message A-law, Psophometric u-law, C-message A-law, Psophometric VFXIN = 0 Vrms, DR = DX f=0 ~100kHz PSRR, Transmit AVDD=DVDD=5V±100mVop f=0 ~50kHz PSRR, Receive AVDD=DVDD=5V±100mVop f=0 ~50kHz Spurious Out-of-Band Signal 0dBm0, 4.6 ~7.6kHz 3) at VRX Output 0.3 ~3.4kHz 7.6 ~8.4kHz PCM CODE 8.4 ~100kHz Note 1) Analog Input = Analog Ground Note 2) Digital Input(DR) = +0 Code Note 3) Not tested in production Test. Parameters guaranteed by design. Interchannel Crosstalk Parameter Transmit to Receive Receive to Transmit Transmit to Transmit Receive to Receive Conditions 0dBm0@VFXIN, Idle PCM code 0dBm0 code level, VFXIN = 0 Vrms 0dBm0@VFXIN, Idle PCM code 0dBm0 code level, VFXIN = 0 Vrms Min 40 - - dB 40 - - dB - - -30 -40 -32 dB Min - Typ - Max -75 -75 -75 -75 Units dB dB dB dB Min 10 - Typ 3.6 2.25 Max 50 - Units kohm pF Analog Interface Transmit Amplifier Parameter Load Resistance Load Capacitance VDD=5V Output voltage Swing VDD=3.3V <MS0093-E-07> Conditions 27 Vp-p 2012/01 ASAHI KASEI [AK2306/LV] Analog Interface Receive Output Parameter Output voltage(AGND level) Load Resistance Load Capacitance Output voltage Swing (AK2306 : VDD 5.0V±5%, AK2306LV : VDD 3.3V±0.3V) Conditions Min Typ Max AK2306 2.3 2.4 2.5 +0 PCM code input AK2306LV 1.5 10 50 AK2306 3.6 AK2306LV 2.25 - Units V kohm pF Vp-p Analog Interface Receive Output Amplifier Parameter Input Resistance Load Resistance Load Capacitance Conditions AK2306 AK2306LV Output Voltage Swing Min 10 10 - Typ 3.6 2.25 Max 50 - Units M ohm k ohm pF Vp-p VOLUME ( GA0T,GA0R,GA1T,GA1R) Parameter Step margin Pin Conditions Min Relative to: 0dB typ -1.0 max Unit +1.0*) dB *)Monotonus increase/decrease is guranteed RING TONE GENERATOR Parameter Signal frequency 16Hz/20Hz Tone Duty <MS0093-E-07> Conditions Min typ max No Jitter on FS 8KHz frame signal -5% 16/20 +5% Hz No Jitter on FS 8KHz frame signal 49 50 51 % 28 Unit 2012/01 ASAHI KASEI [AK2306/LV] PCM INTERFACE ( Long Frame, Short Frame, GCI ) o Unless otherwise noted, the specification applies for TA = -40 to +85 C, VDD = 5V±5%/3.3V±0.3V,VSS = 0V and FS= 8kHz. All timing parameters are measured at VOH = 0.8VDD and VOL =0.4V. Parameter Symbol Min Typ Max Units Ref Fig FS Frequency 1/tPF - 8 - kHz BCLK Frequency 1/tPB 128 4096 kHz BCLK Pulse Width High tWBH 80 ns BCLK Pulse Width Low tWBL 80 ns Rising Time: (BCLK,FS,DX,DR) tR 40 ns Falling Time: (BCLK,FS,DX,DR) tF 40 ns Hold Time: BCLK Low to FS High tHBF 40 ns Setup Time: FS High to BCLK Low tSFB 70 ns Setup Time: DR to BCLK Low tSDB 40 ns Hold Time: BCLK Low to DR tHBD 40 ns Delay Time: BCLK High to DX valid Note1) tDBD 60 Fig1 Fig2 Fig3 ns Long Frame nd Hold Time: 2 period of BCLK Low to FS Low tHBFL Delay Time: FS or BCLK High, whichever is later,to DX valid Note1) Delay Time: BCLK Low to DX High-Z Note1) 40 tDZFL ns 60 ns 60 ns Fig1 tDZCL 10 tWFSL 1 BCL K Hold Time: BCLK Low to FS Low tHBFS 40 ns Setup Time: FS Low to BCLK Low tSFBS 40 ns Delay Time: BCLK Low to DX High-Z Note1) tDZCS 10 60 ns BCLK Frequency 1/tPBG 512 4096 kHz Delay Time: Second BCLK Low to DX High-Z tDZCG 10 60 ns Setup Time: DR to Second BCLK High tSDBG 40 ns Hold Time: Second BCLK High to DR tHBDG 40 ns FS Pulse Width Low Short Frame Fig2 GCI Fig3 Note1) Measured with 15pF Load capacitance and driving two LSTTLs <MS0093-E-07> 29 2012/01 ASAHI KASEI [AK2306/LV] tF tR tWBL tWB tPB BCLK tSFB tHBFL FS tHBF tDZFL tDZCL tDBD DX MSB DR 2 MS B 2 3 4 tSDB tHBD 3 4 5 6 7 8 5 6 7 8 FS tPF tWFSL Fig1 PCM Interface Timing < Long Frame > tF tR tWBL tWBH tPB BCLK tSFB tHBFS FS tHBF tSFBS tDBD tDBD tDZCS DX MS B 2 3 4 tSDB DR MS B Fig2 <MS0093-E-07> 2 3 6 7 8 tHBD 4 PCM Interface Timing 30 5 5 6 7 8 < Short Frame > 2012/01 ASAHI KASEI [AK2306/LV] FS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tPB tWBH BCLK tDBD DX MS B 2 3 4 MS B 2 5 6 7 6 7 8 MS B 2 3 4 5 6 7 MS B 2 3 4 5 6 7 8 tHBD tSDB DR tWBL tDZCG 3 4 5 8 8 BCLK tSFB tHBF tWFSL FS tHBF tDZFL DX 1 2 Fig3 <MS0093-E-07> 3 PCM Interface Timing < GCI > 31 2012/01 ASAHI KASEI [AK2306/LV] SERIAL INTERFACE Parameter Symbol SCLK Frequency Min 1/tPSCLK Typ Max 4 Units Ref fig MHz SCLK Pulse Width High tWSH 40 ns SCLK Pulse Width Low tWSL 40 ns CSN Pulse Width Low tWCL 16 SCL K Hold Time: SCLK High to CSN Low tHCS 80 ns Setup Time: CSN Low to SCLK High tSCS 40 ns Rising Time: CSN,SCLK tR 100 ns Falling Time: CSN,SCLK tF 100 ns Fig4 W R I T E Setup Time: DATA to SCLK High tSDC 40 ns Hold Time: SCLK High to DATA tHDC 40 ns Hold Time: SCLK Low to CSN High tHCS2 0 ns Delay Time: SCLK Low to DATA pin drive tDDD 0 ns Delay Time: SCLK Low to DATA valid tDVD Delay Time: SCLK Low to DATA High-Z tDZSD Delay Time: CSN High to DATA High-Z CSN Pulse Width High Fig4 R E A D <MS0093-E-07> 32 Fig5 60 ns 0 60 ns tDZCD 0 60 ns tWCH 40 Fig6 ns 2012/01 ASAHI KASEI [AK2306/LV] tWCL CSN tWSH tHCS tF tPSCLK tWSL tR tHCS SCLK tHDC tSC DATA tSD I3 I2 I0 A2 A0 * D7 D6 - D1 D0 Fig4 Serial Interface Timing <WRITE> tWCL CSN tWSH tHCS tF tPSCLK tWSL tR tHCS2 SCLK tHDC tSC tDVD tSD tDDD Z DATA I3 I2 I0 A2 A0 D7 Fig5 Serial Interface Timing D6 D1 D0 <READ> tWCH CSN SCLK tDZSD DATA D1 D0 tDZCD Z I1 I0 D0 Z Fig6 Serial Interface Timing <READ> <MS0093-E-07> 33 2012/01 ASAHI KASEI [AK2306/LV] APPLICATION CIRCUIT EXAMPLE Analog input circuit(AMPT0,1) AK2306/LV has an op-amp at analog input of each channel. Each op-amp can be used as a gain adjustment. Op-amp can be used as an inverting amplifier or differential input buffer with AMPRn as VREF buffer . Feedback resistor must be 10k ohm or larger. Single End buffer AK2306 GSXn R2 (n=0,1) C1 R1 VFXn C2 AMPTn C1=0.47uF C2=30pF R1=R2=33kohm BGREF more than 1.0uF Differential buffer C2 GSXn R2 C1 R1 (n=0,1) VFXn AMPTn R1 R2 C1=0.47uF C2=30pF R1=R2=33kohm C2 AMPRn BGREF ! Important Notice Please use AMPRn as a AGND buffer to avoid a cross talk between TX and RX, channel1 and channel2 when TX input is composed as a differential input. <MS0093-E-07> 34 2012/01 ASAHI KASEI [AK2306/LV] Analog output circuit(AMPR0,1) AK2306/LV has an op-amp at analog output stage of each channel to consist in an inverting amplifier for a gain adjustment of 0dBm0 level. Feedback resistor must be 10kohm or larger. AK2306 BGREF GSRn (n=0,1) R1 VFRn R1=R2=33kohm R2 VRn GAnR ! Important Notice When AMPRn are used as a AGND buffer, they can not be used for a gain adjustment. Analog ground stabilization capacitor An external capacitor of more than 1.0uF should be connected between VREF and VSS to stabilize analog ground (VREF). AK2306/LV C + VREF PLL Loop filter capcitor An external capacitor of more than 0.22uF should be connected between LPC and VSS. AK2306/LV C + LPC Power Supply To attenuate the power supply noise, connect capacitors between VDD and VSS, as shown below. AK2306/LV VDD C1 + C2 VSS <MS0093-E-07> C1=C3=0.1uF C2=C4=10uF 35 2012/01 ASAHI KASEI [AK2306/LV] PACKAGE INFORMATION - 24pin SSOP Marking XXXXX: Date Code Identifier AK2306 AKM AK2306VM XXXXX AK2306L AKM AK2306LVM XXXXX <MS0093-E-07> 36 2012/01 ASAHI KASEI [AK2306/LV] PACKAGE SIZE 24pin SSOP (Unit: mm) 8.20 2.10MAX 24 13 5.30 7.90±0.20 A 12 1 0.30±0.10 0.65±0.08 0.22±0.05 0.13 M 0.10±0.10 0.60±0.15 Detail A Seating Plane | 0.10 NOTE: Dimension "*" does not include mold flash. <MS0093-E-07> 37 0-8° 2012/01 ASAHI KASEI [AK2306/LV] REVISION HISTORY Date (Y/M/D) 11/10/20 Revision 06 Reason Specification Change Page 1, 36, 37 12/01/25 07 Error Correction 36 Contents Package Change: (24pin VSOP) → (24pin SSOP) Marking diagrams were changed. Package drawing was changed. PACKAGE INFORMATION Marking diagrams were changed IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <MS0093-E-07> 38 2012/01