AKM AK4532_04

ASAHI KASEI
[AK4532]
AK4532
Internet/Network/General Purpose Multimedia Audio CODEC
General Description
The AK4532 is a low-cost high-quality 16-Bit CODEC designed specifically for Internet Boxes,
Network PCs, and to interface with audio/video controller ICs for standard PC applications. AKM’s
AK4532 serial interface mode simplifies the design process on existing and new audio projects. The
converters can have a range of 4 to 50 kHz. For voice mail applications, an internal 26 dB microphone
preamp has been added and because of the internal input mixer, music or other sounds can easily be
mixed with voice.
Features
•
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•
•
•
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•
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2ch Audio CODEC
2ch stereo including 1ch mono recording mixer with L/R, R/L, L/L and R/R switching
2ch stereo playback mixer
Mic input with 26 dB optional gain
High Jitter Tolerance
Interface compatible with AKM’s AK4531
Sampling Rate: 4 kHz to 50 kHz
3-wire Serial Interface for Mixer Control
5 V operation, can connect to 3.3 V Digital Controller.
Low power consumption - 150 mW
Power down mode
Small low profile package - 24 pin VSOP.
Block Diagram
0178-E-02
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2004/12
ASAHI KASEI
[AK4532]
Ordering Guide
AK4532
AKD4532
from -10°C to +70°C
Evaluation Board
24pin VSOP(0.65mm pitch)
Pin Layout
0178-E-02
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2004/12
ASAHI KASEI
[AK4532]
Pin and Function
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pin Name
AGND
VA
MIC/AUXR
AUXL
LINER
LINEL
PD
MCLK
LRCK
SCLK
SDI
SDO
DGND
VD
CS
CCLK
CDATA
CMODE
LOUT
ROUT
VRAD
I/O
I
I
I
I
I
I
I
I
I
O
I
I
I
I
O
O
I
22
AINFL
-
23
AINFR
-
24
VCOM
-
Function
Analog Ground
Analog Power - 5V
Mic or Right Aux Line Level Input
Left Aux Line Level Input
Right Line Level Input
Left Line Level Input
Power down and Reset
Master Clock for CODEC
Left Right Clock for CODEC
Serial Clock for CODEC
Serial Data In
Serial Data Out
Digital Ground
Digital Power - 5V
Chip Select
Control Port Clock
Control Port Data
MCLK select (L:256fs, H:384fs)
Left Analog Out
Right Analog Out
A/D Reference
Connect to AGND with 0.1uF and 4.7uF capacitors
L channel Antialias Filter Pin
Connect to AGND with 1.0nF capacitor
R channel Antialias Filter Pin
Connect to AGND with 1.0nF capacitor
Voltage Common Output Pin
Connect to AGND with 0.1uF and 4.7uF capacitors.
Note: 1. No load current may be taken from the VCOM, VRAD pins for the external circuits.
2. All digital input pins should not be left floating.
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ASAHI KASEI
[AK4532]
ABSOLUTE MAXIMUM RATINGS
AGND, DGND = 0 V
Parameter
Power Supplies:
Analog
Digital
Input Current, Any Pin except Supplies
Analog Input Voltage Range
Digital Input Voltage
Ambient Temperature
Storage Temperature
Symbol
VA
VD
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-0.3
-10
-65
max
6.0
6.0 or VA+0.3
+/- 10
6.0 or VA+0.3
6.0 or VA+0.3
70
150
Units
V
V
mA
V
V
°C
°C
Note: 1. All voltages with respect to ground.
2. Max value is higher voltage of 6.0 or VA+0.3V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
Operating Specifications are not guarantee at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND = 0 V, Note 1)
Parameter
Power Supplies
Analog
Digital
Symbol
VA
VD
min
4.5
4.5
typ
5.0
5.0
max
5.5
VA
units
V
V
Note 1: All voltages with respect to ground.
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ASAHI KASEI
[AK4532]
ANALOG CHARACTERISTICS
(Ta=25 °C; VA, VD = 5.0V; fs = 44.1kHz; Signal Frequency = 1 kHz; MCLK=256fs; BCLK = 64 fs;
LRCK = fs, Gain, ATT and Mixer switches are defualt setting. Measurement frequency bandwidth is
10Hz to 20kHz, unless otherwise noted.)
Parameter
min
typ
max
units
measured via LineL and LineR
A/D
Resolution
16
Bits
S/(N+D)
-0.5 dB Input
74
80
dB
S/N
A-weighted
84
90
dB
Dynamic Range
-60 dB Input,
84
90
dB
A-weighted
Interchannel Isolation
(Note 1)
68
76
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
100
ppm/°
C
Offset Error
(Note 2)
+/- 1
LSB
Input Voltage
(Note 4)
2.50
2.70
2.90 Vpp
Mixer Input Resistance
30
60
100
kΩ
measured via LOUT and ROUT
D/A
Resolution
16
Bits
S/(N+D)
75
83
dB
S/N
A-weighted
83
87
dB
Dynamic Range
-60 dB Input,
83
87
dB
A-weighted
Interchannel Isolation
(Note 1)
80
100
dB
Interchannel Gain Mismatch
0.2
0.7
dB
ppm/°C
Gain Drift
100
Output Voltage
(Note 4)
2.85
3.05
3.35 Vpp
Load Resistance
10
kΩ
Out-of-Band Noise
BW < 100 kHz
-81
dB
MIC Amp
Gain
Input Resistance
Mixer Gain Control
Step Size
Gain Control Range
Master Volume
Step Size
Attenuation Control Range
For 26dB setting
32 Steps
(Note 3)
32 Steps
(Note 3)
24
15
26
25
0
-50
2
0
-62
2
28
40
dB
kΩ
12
dB
dB
0
dB
dB
Power Supplies
Normal Operation
Power-Down Mode
VA
VD
Power Dissipation
VA
VD
Power Dissipation
27
3
150
10
10
100
40
5
225
200
mA
mA
mW
uA
uA
uW
Note: 1. Crosstalk between channels on the same A/D or D/A.
2. Internal HPF removes offset
3. Minimum spec applies to ≥ -40dB setting.
4. Input and Output voltage scale with VA.
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ASAHI KASEI
[AK4532]
FILTER CHARACTERISTICS
(Ta=25 °C; VA, VD = 5.0V ± 10%; fs = 44.1 kHz)
Parameter
Symbol
A/D Digital Filter
(Decimation LPF)
PB
Passband (Note 1)
+/- 0.1 dB
-0.5 dB
-1.2 dB
-6.7 dB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay Distortion
Delta GD
Group Delay (Note 2)
GD
A/D Digital Filter (HPF)
Frequency Response
-3 dB
FR
(Note 1)
-0.5 dB
-0.1 dB
D/A Digital Filter
Passband (Note 1)
+/- 0.1 dB
PB
-6.0 dB
Stopband
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay (Note 2)
GD
D/A Digital Filter
+ Analog Filter
Frequency Response
0 to 20 kHz
FR
min
typ
max
Units
16.5
19.0
20.0
22.05
16.1
kHz
kHz
kHz
kHz
kHz
dB
dB
uS
1/fs
6.85
19.6
44.9
Hz
Hz
Hz
0
0
0
0
26.0
+/- 0.1
68
0
0
0
26.1
18.0
22.05
14.4
kHz
kHz
kHz
dB
dB
1/fs
+/- 1.0
dB
+/- 0.1
65
Note: 1. The passband and stopband frequencies scale with fs.
2. The calculating delay time which occurred by digital filtering. This time is from the input of
analog signal to setting the 16bit data of both channels to the output register of ADC.
For DAC, this time is from setting 16bit data of both channels on input register to the output of
analog signal.
DIGITAL CHARACTERISTICS
(Ta=25 °C; VA, VD = 5.0V±10%)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-80uA)
Low-Level Output Voltage (Iout=80uA)
Input Leakage Current
0178-E-02
Symbol
VIH
VIL
VOH
VOL
Iin
6
min
2.2
VD-0.4
-
typ
-
max
0.8
0.4
+/-10
Units
V
V
V
V
uA
2004/12
ASAHI KASEI
[AK4532]
SWITCHING CHARACTERISTICS
(Ta=25 °C; VA, VD = 5.0V ± 10%, CL = 20pF)
Parameter
Symbol
min
typ
max
Units
11.2896
12.800 MHz
1.024
fCLK
Master Clock Timing (CMODE=L)
16.9344
19.2
MHz
1.536
fCLK
(CMODE=H)
ns
31.25
fCLKL
Pulse Width Low
(CMODE=L)
ns
23
fCLKL
(CMODE=H)
ns
31.25
fCLKH
Pulse Width High
(CMODE=L)
ns
23
fCLKH
(CMODE=H)
LRCK Frequency (Note 1)
fs
4
44.1
50
kHz
Duty Cycle
45
55
%
Serial Interface Timing
ns
312.5
tSCK
SCLK Period
ns
100
tSCKL
SCLK Pulse Width Low
ns
100
tSCKH
SCLK Pulse Width High
ns
50
LRCK Edge to SCLK “rising edge” (Note 2) tLRS
ns
50
SCLK “rising edge” to LRCK edge (Note 2) tSLR
ns
50
tSDH
SDI Hold Time
ns
50
tSDS
SDI Setup Time
ns
70
tLRS
LRCK to SDO(MSB)
ns
70
tSSD
SCLK “rising edge” to SDO
Control Interface Timing
ns
200 (Note 4)
CCLK Period
tCCK
ns
80
CCLK Pulse Width Low
tCCKL
ns
80
CCLK Pulse Width High
tCCKH
ns
50
CDATA Hold Time
tCDS
ns
50
CDATA Setup Time
tCDH
ns
150 (Note 4)
tCSW
CS High Level Time
ns
50 (Note 4)
tCSS
CS “falling edge” to CCLK “rising” time
ns
50
tCSH
CCLK “rising time” to CS “rising” time
Reset Timing
tPD
150
ns
PD Pulse Width
tPDS
516
1/fs
PD “rising edge” to SDO delay (Note 3)
Note: 1. If the duty of LRCK changes larger than 5% from 50%, the AK4532 is reset by the internal
phase detecting circuit automatically.
2. SCLK rising edge must not occur at the same time as LRCK edge.
3. These cycles are the number of LRCK rising from PD rising.
4. fs ≥ 19.6kHz.
In the case of fs <19.6kHz, these three parameters must meet a relationship of
(tCSW + tCSS + 7 × tCCK) > 1/(32 × fs) in addition to these specifications.
For example, when tCCK=200ns and tCSS=50ns at fs=8kHz, tCSW(min) is 2457ns.
When tCSW=150ns and tCSS=50ns fs=8kHz, tCCK(min) is 530ns.
0178-E-02
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ASAHI KASEI
[AK4532]
Audio Data Formats
The data format of ADC and DAC are MSB first & MSB justified with 16bit. The SCLK needs 32fs or
more than 32fs in a LRCK cycle.
Lch
LRCK
Rch
SCLK
=64fs
SDO
16Bit
15141312
1 0
Don't Care
15141312
1 0
Don't Care
1514
SDI
16Bit
15141312
1 0
Don't Care
15141312
1 0
Don't Care
1514
SDO,SDI - 15:MSB,0:LSB
Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
1/fs
VIH
VIL
LRCK
tSCK
VIH
VIL
SCLK
tSCKH
tSCKL
Clock Timing
VIH
VIL
LRCK
tSLR
tLRS
VIH
VIL
SCLK
tLRS
tSSD
VIH
VIL
SDO
tSDS
tSDH
VIH
VIL
SDI
Serial Audio Interface Timing
0178-E-02
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2004/12
ASAHI KASEI
[AK4532]
tCSW
VIH
VIL
CS
tCSS
tCCK
VIH
VIL
CCLK
tCDS
CDATA
tCCKH
tCDH
A7
A6
tCCKL
A5
VIH
VIL
Control Data Interface Timing 1
VIH
VIL
CS
tCSH
VIH
VIL
CCLK
CDATA
D2
D1
VIH
VIL
D0
Control Data Interface Timing2
tPD
PD
VIL
Power down and Reset Timing
0178-E-02
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2004/12
ASAHI KASEI
[AK4532]
OPERATION OVERVIW
1. CONTROL REGISTER MAP
Addr Register Name
D7
D6
00
Master Volume Lch
MUTE
01
Master Volume Rch
MUTE
02
Voice Volume Lch
MUTE
03
Voice Volume Rch
MUTE
08
Line Volume Lch
MUTE
09
Line Volume Rch
MUTE
0A
AUX Volume Lch
MUTE
0B
AUX Volume Rch
MUTE
10
Output Mixer SW 1
11
Output Mixer SW 2
12
Lch Input Mixer SW 1
13
Rch Input Mixer SW 1
14
Lch Input Mixer SW 2
15
Rch Input Mixer SW 2
16
Reset and Power Down
19
MIC Amp Gain
Note: ATT* is data bits for the attenuation level.
GAI* is data bits for the gain level.
D5
D4
ATT4
ATT4
GAI4
GAI4
GAI4
GAI4
GAI4
GAI4
LineL
AUXR
LineL
LineL
AUXL
AUXL
AUXL
D3
ATT3
ATT3
GAI3
GAI3
GAI3
GAI3
GAI3
GAI3
LineR
VoiceL
LineR
LineR
AUXR
AUXR
D2
ATT2
ATT2
GAI2
GAI2
GAI2
GAI2
GAI2
GAI2
D1
ATT1
ATT1
GAI1
GAI1
GAI1
GAI1
GAI1
GAI1
VoiceR
VoiceL
VoiceR
PD
2. WRITE Timing of Control Register
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDATA
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A7-A0:
D7-D0:
Address
Control Data
3. Control Register Definitions
Addr
00
01
Register Name
Master Volume Lch
Master Volume Rch
MUTE
ATT4:0
Initial
0178-E-02
D7
MUTE
MUTE
D6
RST
MGAIN
IMPORTANT: There is the compatibility between the AK4531 and AK4532. But the input mixer
functions of those device has some different implication in the application, receptively.
And the other address of control register except those described in the above table and “1A” are
“do not care”. Address “1A” for testing shall be strictly prohibited to access.
Be ware that the three MSB address bits(A7, A6, A5) are ignored by AK4532. Writing to address
“20” register will update the address “00” register for instance.
0
D0
ATT0
ATT0
GAI0
GAI0
GAI0
GAI0
GAI0
GAI0
MIC
D5
D4
ATT4
ATT4
D3
ATT3
ATT3
D2
ATT2
ATT2
D1
ATT1
ATT1
D0
ATT0
ATT0
1:
0:
MUTE
No MUTE
32 levels with 2 dB step
00000: 0dB
11111: -62 dB
“0000 0000”(No MUTE & 0dB)
10
2004/12
ASAHI KASEI
Addr
02
03
08
09
0A
0B
Register Name
Voice Volume Lch
Voice Volume Rch
Line Volume Lch
Line Volume Rch
AUX Volume Lch
AUX Volume Rch
MUTE
D7
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
D6
D5
D4
GAI4
GAI4
GAI4
GAI4
GAI4
GAI4
D3
GAI3
GAI3
GAI3
GAI3
GAI3
GAI3
D2
GAI2
GAI2
GAI2
GAI2
GAI2
GAI2
D1
GAI1
GAI1
GAI1
GAI1
GAI1
GAI1
D0
GAI0
GAI0
GAI0
GAI0
GAI0
GAI0
1:
0:
MUTE
No MUTE
32 levels with 2 dB step
00000: 12dB
00110: 0 dB
11111: -50 dB
“0000 0110”(No MUTE & 0dB)
ATT4:0
Initial
Addr
10
11
12
13
14
15
[AK4532]
Register Name
Output Mixer SW 1
Output Mixer SW 2
Lch Input Mixer SW 1
Rch Input Mixer SW 1
Lch Input Mixer SW 2
Rch Input Mixer SW 2
D7
D6
D5
AUXL
D4
LineL
AUXR
LineL
LineL
AUXL
AUXL
D3
LineR
VoiceL
LineR
LineR
AUXR
AUXR
D2
D1
VoiceR
VoiceL
VoiceR
ON/OFF of Mixer Switches
0:
OFF
1:
ON
Initial
“000X XX00”
XXX=000: Addr=10,14,15 (All:OFF)
XXX=011: Addr=11(Output Mixer Voice R&L:ON)
XXX=100: Addr=12(Lch Input Mixer Line L :ON)
XXX=010: Addr=13(Rch Input Mixer Line R :ON)
Addr
16
19
Register Name
Reset and Power Down
MIC Amp Gain
D7
D6
D5
D4
D3
D2
D1
PD
D0
RST
MGAIN
RST initializes the contents of all registers except PD and RST registers. When PD pin goes low, RST
register becomes
“1”.
1: Normal Operation
0: Initialize
PD register enables the power down. When PD pin goes low, PD register becomes “1”.
1: Normal Operation
0: Power Down
MGAIN selects the gain of MIC amp. The initial state is “0”.
0: Bypass (0dB)
1: 26 dB
Try to avoid pops and clicks when activating or inactivating this function.
0178-E-02
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D0
MIC
ASAHI KASEI
[AK4532]
4. Explanation of each sequence
4.1. Reset & Power down
Power Supply
PD pin
PD(register)
RST(register)
Internal State
INIT1
Write to register
Inhibit(1)
INITA
Normal
PD
INITA
Normal
INIT2
Normal PD+INIT2
Inhibit(2)
INITA
Normal
Inhibit(2
External clock
MCLK,LRCK,SCLK
The clocks may be stopped.
• INIT1:
• INIT2:
• INITA:
• PD:
Initializing all registers. The AK4532 exists in the power down state.
Initializing all registers except PD , RST registers.
Initializing the analog section. Initializing period is 516/fs.
Power down state. All analog outputs are floating.
In case of RST register = “0”, initializing all registers except PD , RST registers.
• Inhibit(1): Inhibits writing to all registers.
• Inhibit(2): Inhibits writing to all registers except for PD , RST registers.
• The AK4532 operates with the external clocks(MCLK, LRCK, SCLK) during initializing the
analog section.
Figure 1. Reset & Power Down Sequence
4.2. PD pin operation
“H”: Normal operation
“L”: Initializing mode 1(INIT1 in Figure 1)
• Initializing all registers.
• Inhibits writing to all registers.
• The initialization of the analog section starts at rising edge of PD pin.
• SDO pin stays “L” during the initializing periods of 516/fs.
• Going into power down state.
4.3. RST register operation
“1”: Normal operation
“0”: Initializing mode 2(INIT2 in Figure 1)
• Initializing all registers except PD , RST registers.
• Inhibits writing to all registers except PD , RST registers.
• RST register goes “1” when PD pin goes “L”.
• The analog section is not initialized.
4.4. PD register operation
“1”: Normal operation
“0”: Power down
• The contents of all registers are held.
• PD resister goes “1” when PD pin goes “L”.
• All analog outputs(LOUT, ROUT) go floating.
• The initialization of the analog section starts at the rising edge of PD resister.
• SDO pin stays “L” during the initializing period of 516/fs.
4.5. SDO output pin operation
0178-E-02
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ASAHI KASEI
[AK4532]
SDO output is the 16bit data of ADC and goes “L”(0000H) in the following cases.
• PD pin = “L”
• During initializing the analog section(516/fs).
• RST register = “0”
• PD register = “0”
4.6. Analog output pin(LOUT, ROUT) operation
These outputs are floating in the following case.
• PD pin = “L”
• PD register = “0”
5. System Clock
The external clocks which are required to operate the AK4532 are MCLK, LRCK and SCLK. MCLK
should be synchronized with LRCK but the phase is free of care. As the AK4532 includes the phase
detect circuit for LRCK, the AK4532 is reset automatically when the synchronization is out of
phase by changing the clock frequencies. Therefore, the reset is not required except only upon
power-up.
All external clocks should always be present whenever the AK4532 is in normal operation mode. If these
clocks are not provided, the AK4532 may draw excessive current and do not possibly operate
properly because the device utilizes the dynamic logic internally. If the external clocks are not
present, the AK4532 should be in the power down mode.
5.
Digital High Pass Filter
The ADC of the AK4532 has a digital high pass filter for DC offset cancel. The cut-off frequency of
the HPF is 6.85Hz at fs=44.1kHz and the frequency response at 20Hz is -0.5dB. It also scales with
sampling rate(fs).
0178-E-02
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ASAHI KASEI
[AK4532]
System Design
Figure 2 shows the system connection diagram. An evaluation board is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
4.7u
+
0.1u
+
0.1u
10
VA
VRAD
21
+
0.1u
8
9
Controller
&
Synth.
10
VCOM
PD
MCLK
+
15
4.7u
LRCK
SDI
12
SDO
18
CMODE
16
4.7u
24
0.1u
SCLK
11
17
+5V
Analog
2
14
VD
7
4.7u
AINFL 22
AINFR 23
AK4532
MIC/AUXR
AUXL
LineR
LineL
CDATA
CCLK
CS
LOUT
ROUT
DGND
13
AGND
3
4
5
6
19
20
Lch
Analog
Out
Rch
Analog
Out
1
Figure 2. Typical Connection Diagram
1. Grounding and power supply decoupling
The AK4532 requires careful attention to power supply and grounding arrangements. VD should be
supplied from analog power supply. Analog ground and digital ground should be connected
together near to where the supplies are brought onto the printed circuit board. Decoupling
capacitors should be as near to the AK4532 as possible, with the small value ceramic capacitor
being the nearest.
2. On-chip voltage reference
The on-chip voltage references are output on the VRAD and VCOM pins for decouping .
The VRAD is used as the reference of A/D conversion. The VCOM is a signal ground of this chip. An
electrolytic capacitor less than 10uF in parallel with a 0.1uF ceramic capacitor attached to these
pins eliminates the effects of high frequency noise. Especially, the small value ceramic capacitors
should be as near to the AK4532 as possible. No load current may be drawn from the VRAD and
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ASAHI KASEI
[AK4532]
VCOM pins. All signals, especially clocks, should be kept away from the VRAD and VCOM pins
in order to avoid unwanted coupling into the chip.
3. Analog Inputs
The mixer input and the ADC inputs are single-ended and internally biased to the VCOM voltage with
60kΩ(typ) resistance. The input signal range is typically 2.83Vpp(1Vrms). Figure 3 is an example
for 2Vrms line-level input circuit. The ADC output data format is 2’s complement. The AK4532
accepts input voltages from AGND to VA. The output code is 7FFFH for input above a positive full
scale and 8000H for input below a negative full scale. The ideal code is 0000H with no input signal.
The DC offset is canceled by the internal HPF.
AK4532
Analog
Input
2Vrms
5.1k
0.47u
LINE/AUX
5.1k
Figure 3. 2Vrms Line-level Input
The AK4532 samples the analog inputs at 64fs. The digital filter rejects all noise higher than the stop
band. However, the filter will not reject frequencies right around 64fs(and multiples of 64fs). Most
audio signals do not have significant energy at 64fs. As a result, two 1nF capacitors are necessary
for AINFR and AINFL.
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The output signal
range is typically 2.83Vpp(1Vrms). The DAC input data format is 2’s complement. The output
voltage is a positive full scale for 7FFFH and a negative full scale for 8000H. The ideal output is
VCOM voltage for 0000H. The internal switched-capacitor filter and continuous-time filter almost
remove the noise generated by the delta-sigma modulator of DAC beyond the audio passband,
especially low sampling rate. The noise floor level is almost constant and the audible noise level is
-83dB(typ) at 8kHz sampling.
5.
Other information
5.1 Clock change
The clock change or LRCK phase shift should be done while muting the DAC output by the master
volume or voice volume to avoid the click noise by out-of-synchronization.
ADC may output digital code at the clock change, or LRCK phase shift may produce incomplete or
destroyed 16bit data. Then some attention is required carefully.
5.2 Offset on mixer inputs
When the mixer gain is set to +12dB, the output has pretty large offset even if the inputs are no signal.
Therefore, large click noise may occur when the gain level is changed quickly.
5.3 Click noise on the analog outputs
The click noise of about -50dB occurs from the analog outputs(LOUT, ROUT) at the power on/off or the
transition of PD register. The analog outputs should be muted externally if the click noise
influences systems application.
0178-E-02
15
2004/12
ASAHI KASEI
[AK4532]
Package
● 24pin VSOP
(Unit: mm)
*7.8 ±0.15
1.25 ±0.2
* 5.6±0.2
7.6±0.2
13
24
A
12
1
0.22 ±0.1
0.15 ±0.05
0.65
0.1
0.5 ±0 .2
Detail A
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0 ~10゚
■Package & Lead frame materiel
Package molding compound : Epoxy
Lead frame material
:Cu
Lead frame surface treatment : Solder plate
0178-E-02
16
2004/12
ASAHI KASEI
[AK4532]
Marking
AK4532VF
AAXXXX
1)
2)
3)
4)
5)
6)
Pin #1 indication
AA: LOT#
Date Code: XXXX(4 digits)
Marketing Code: AK4532-VF
Country of Origin
Asahi Kasei Logo
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd.
(AKM) sales office or authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in
any safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy,
or other fields, in which its failure to function or perform may reasonably be
expected to result in loss of life or in significant injury or damage to person or
property.
b. A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet
very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.
0178-E-02
17
2004/12