ASAHI KASEI [AK4531A] AK4531A Audio CODEC with 13ch Mixer & 18bit DAC General Description The AK4531A is a two channel 16bit AUDIO Hi-Fi CODEC (ADC and DAC) with a sampling rate of 4kHz to 50kHz and includes a 2 channel 18bit DAC designed to work together with an extra sound source. Each converter can also operate by independent sampling rates. Its internal recording and playback mixer has 5 channel stereo and 3 channel mono with L/R, R/L, L/L and R/R switching. The AK4531A also has an internal 30dB microphone amplifier. Its master clock is 256 times of fs and an internal PLL can also automatically generates 256fs for master clock from fs. The sampling ADC has an enhanced dual bit delta sigma modulator. Both the 16bit and 18bit DAC have low outband noise and high jitter tolerance due to a switched capacitor filter(SCF) and a continuous time filter(CTF). The AK4531A corresponds to a 3.3V digital interface, performing with a low power dissipation of 315mW. The package is a low profile 44pin LQFP. Features □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 2ch Audio CODEC with low outband noise DAC 2ch 18bit Extra Audio DAC Standard Serial Interface for CODEC & DAC CODEC & DAC Dynamic Range: 87dB High Jitter Tolerance 5ch stereo & 3ch mono recording mixer with L/R, R/L, L/L and R/R switching 5ch stereo & 3ch mono playback mixer Input PGA with 32levels & 2dB step 30dB microphone amplifier 3-wire Serial Interface for Mixer Control Sampling Rate: 4kHz ∼ 50kHz Independent Sampling Rates for Each Converter Master Clock: 256fs On chip PLL for deriving 256fs master clock from fs clock Corresponding to a 3.3V digital interface Low Power Dissipation: 315mW Low Profile Package: 44pin LQFP AK4531 Pin Compatible M0003-E-01 1998/12 -1- ASAHI KASEI [AK4531A] M0003-E-00 1998/2 -2- ASAHI KASEI [AK4531A] ■ Ordering Guide AK4531A-VQ AKD4531 -10 ∼ +70 ℃ Evaluation Board 44pin LQFP(0.8mm pitch) ■ Pin Layout M0003-E-01 1998/12 -3- ASAHI KASEI [AK4531A] PIN/FUNCTION No. Pin Name I/O Function Analog Inputs/Outputs : 16pin 39 CDL I Lch #1 Line Level Input Pin 38 CDR I Rch #1 Line Level Input Pin 37 LineL I Lch #2 Line Level Input Pin 36 LineR I Rch #2 Line Level Input Pin 35 AUXL I Lch #3 Line Level Input Pin 34 AUXR I Rch #3 Line Level Input Pin 40 MONO1 I Mono #1 Input Pin 41 MONO2 I Mono #2 Input Pin 44 MIC I MIC Input Pin 28 LOUT O Lch Line Level Output Pin 27 ROUT O Rch Line Level Output Pin 26 MOUT O Mono Output Pin 33 AINL I Lch ADC Input Pin 30 AINR I Rch ADC Input Pin 24 AOUTL O Lch DAC Output Pin 23 AOUTR O Rch DAC Output Pin Serial Audio Interface : 9pin 2 MCLK1 I Extra DAC Master Clock 3 LRCK1 I Extra DAC L/R Clock 4 BCLK1 I Extra DAC Bit Clock 5 SDI1 I Extra Data Input 6 MCLK2 I CODEC Master Clock 7 LRCK2 I CODEC L/R Clock 8 BCLK2 I CODEC Bit Clock 9 SDI2 I CODEC-DAC Data Input 10 SDO O CODEC-ADC Data Output Serial Control Data Interface : 3pin 12 CS I Chip Select 13 CCLK I Control Interface Clock 14 CDATA I Control Data M0003-E-01 1998/12 -4- ASAHI KASEI No. Pin Name Miscellaneous : 11pin [AK4531A] I/O 1 11 29 RST BUSY VRAD I O O 25 VRDA1 O 22 VRDA2 O 21 VCOM O 43 MAMP O 42 32 MONO3 AINFL I O 31 AINFR O 20 LOOPF O Power Supplies : 5pin 18 VA 19 AGND 16 VD 17 VT 15 DGND - Function Reset Pin Status Output ADC Voltage Reference Pin Connected to AGND with 0.1uF and 4.7uF CODEC-DAC Voltage Reference Pin Connected to AGND with 0.1uF and 4.7uF Extra-DAC Voltage Reference Pin Connected to AGND with 0.1uF and 4.7uF Voltage Common Output Pin Connected to AGND with 0.1uF and 4.7uF MIC Amp Output Pin Connected to MONO3 with 1uF capacitor. MONO #3 Input Pin Lch Antialias Filter Pin Connected to AGND with 1.0nF capacitor. Rch Antialias Filter Pin Connected to AGND with 1.0nF capacitor. Loop Filter Pin Connected to AGND with 0.1uF capacitor. capacitors. capacitors. capacitors. capacitors. Analog Power Supply Pin, 5V Analog Ground Pin Digital Power Supply Pin, 5V Output Buffer Power Supply Pin, 3.3V Digital Ground Pin Note: No load current may be taken from the VCOM, VRAD, VRDA1, VRDA2 pins for the external circuits. All digital input pins except pull-down pins should not be left floating. M0003-E-01 1998/12 -5- ASAHI KASEI [AK4531A] ABSOLUTE MAXIMUM RATINGS (AGND,DGND=0V; Note 1) Parameter Power Supplies: Analog Digital (Note 2) Output Buffer Input Current, Any Pin Except Supplies Analog Input Voltage (Note 2) Digital Input Voltage (Note 2) Ambient Temperature (power applied) Storage Temperature Symbol VA VD VT IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -0.3 -10 -65 max 6.0 6.0/VA+0.3 VD ± 10 6.0/VA+0.3 6.0/VA+0.3 70 150 Units V V V mA V V ℃ ℃ Note: 1. All voltages with respect to ground. 2. Max value is higher voltage of 6.0V or VA+0.3V. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND,DGND=0V; Note 1) Parameter Power Supplies: Analog Digital Output Buffer Symbol VA VD VT min 4.5 4.5 3.0 typ 5.0 5.0 3.3 max 5.5 VA VD Units V V V Note: 1. All voltages with respect to ground. M0003-E-01 1998/12 -6- ASAHI KASEI [AK4531A] ANALOG CHARACTERISTICS (Ta=25 ℃ ; VA,VD=5.0V; VT=3.3V; fs=44.1kHz; Signal Frequency=1kHz; CSEL2,1="1,1", MCLK=256fs, BCLK=64fs, LRCK=fs The same clocks are supplied to CODEC-ADC,CODEC-DAC & Extra-DAC. Measurement frequency=10Hz ∼ 20kHz; unless otherwise specified) Parameter min typ max CODEC-ADC: Measured via AINL/AINR Resolution 16 S/(N+D) (-0.5dB Input) 74 82 S/N (A-Weighted) 83 88 Dynamic Range (-60dB Input, A-Weighted) 83 88 Interchannel Isolation (Note 3) 78 70 Interchannel Gain Mismatch 0.1 0.3 Gain Drift 100 Offset Error (Note 4) ±1 Input Voltage 2.60 2.88 3.16 Input Resistance 45 75 105 Power Supply Rejection 50 CODEC-DAC: Measured via AOUTL/AOUTR Resolution 16 S/(N+D) 74 83 S/N (A-Weighted) 83 88 Dynamic Range (-60dB Input, A-Weighted) 83 88 Interchannel Isolation (Note 3) 80 90 Interchannel Gain Mismatch 0.1 0.5 Gain Drift 100 Output Voltage 2.60 2.88 3.16 Load Resistance 10 Out-of-Band Noise (BW ≦ 100kHz) -83 Power Supply Rejection 50 Extra-DAC: Reference data Resolution 18 S/(N+D) 83 S/N (A-Weighted) 88 Dynamic Range (-60dB Input, A-Weighted) 88 Interchannel Isolation (Note 3) 90 Interchannel Gain Mismatch 0.1 Gain Drift 100 Output Voltage 2.88 Power Supply Rejection 50 Units Bits dB dB dB dB dB ppm/℃ LSB Vpp kΩ dB Bits dB dB dB dB dB ppm/℃ Vpp kΩ dB dB Bits dB dB dB dB dB ppm/℃ Vpp dB Note: 3. Crosstalk between channels on the same A/D or D/A. 4. Internal HPF removes offset. M0003-E-01 1998/12 -7- ASAHI KASEI Parameter Mic Amp Gain Input Resistance Mixer Input Input Resistance (CD,Line,AUX) Input Resistance (MONO1,MONO2,MONO3) Mixer Gain Control: 32 steps Step Size Gain Control Range Line Output: LOUT/ROUT/MOUT Load Resistance Master Volume: 32 steps Step Size Attenuation Control Range Mono Volume: 8 steps Step Size Attenuation Control Range Power Supplies Power Supply Current Normal Operation (PD bit="1") VA VD+VT Power-Down-Mode (PD bit="0") VA VD+VT Power Dissipation Normal Operation Power-Down-Mode [AK4531A] min typ max Units 28 30 30 50 32 80 dB kΩ 30 10 50 - 80 80 kΩ kΩ 0 -50 2 12 dB dB kΩ 5 0 -62 2 0 -28 4 50 13 0 dB dB 0 dB dB 75 20 mA mA 10 10 315 100 M0003-E-01 uA uA 475 mW uW 1998/12 -8- ASAHI KASEI [AK4531A] FILTER CHARACTERISTICS (Ta=25 ℃ ; VA,VD=5.0V ± 10%; VT=3.0 ∼ 5.5V; fs=44.1kHz) Parameter Symbol min CODEC-ADC Digital Filter(Decimation LPF): Passband PB 0 ± 0.1dB (Note 5) -0.5dB 0 -1.2dB 0 -6.7dB 0 Stopband SB 26.0 Passband Ripple PR Stopband Attenuation SA 68 Group Delay Distortion GD △ Group Delay (Note 6) GD CODEC-ADC Digital Filter(HPF): Frequency Response -3dB (Note 5) FR -0.5dB -0.1dB CODEC-DAC Digital Filter: Passband PB 0 ± 0.1dB (Note 5) -6.0dB 0 Stopband SB 26.1 Passband Ripple PR Stopband Attenuation SA 65 Group Delay (Note 6) GD CODEC-DAC Digital Filter+Analog Filter: Frequency Response 0 ∼ 20.0kHz FR Extra-DAC Digital Filter: Passband PB 0 ± 0.1dB (Note 5) -6.0dB 0 Stopband SB 26.0 Passband Ripple PR Stopband Attenuation SA 57 Group Delay (Note 6) GD Extra-DAC Digital Filter+Analog Filter: Frequency Response 0 ∼ 20.0kHz FR typ max 16.5 19.0 20.0 22.05 Units 16.1 kHz kHz kHz kHz kHz dB dB us 1/fs 6.85 19.6 44.9 Hz Hz Hz ± 0.1 0 18.0 22.05 14.4 kHz kHz kHz dB dB 1/fs ± 1.0 dB ± 0.1 18.0 22.05 14.4 kHz kHz kHz dB dB 1/fs ± 1.0 dB ± 0.02 Notes: 5. The Passband and stopband frequencies scale with fs. 6. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 16bit data of both channels to the output register for ADC. For DAC, this time is from setting the 16/18bit data of both channels on input register to the output of analog signal. M0003-E-01 1998/12 -9- ASAHI KASEI [AK4531A] DIGITAL CHARACTERISTICS (Ta=25 ℃ ; VA,VD=5.0V ± 10%; VT=3.0 ∼ 5.5V) Parameter Symbol High-Level Input Voltage VIH Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-80uA) VOH Low-Level Output Voltage (Iout=80uA) VOL Input Leakage Current Iin min 2.0 VT-0.4 - typ - max 0.8 0.4 ± 10 Units V V V V uA SWITCHING CHARACTERISTICS (Ta=25 ℃ ; VA,VD=5.0V ± 10%; VT=3.0 ∼ 5.5V; CL ＝ Parameter Symbol Master Clock Timing (Note 7) fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Frequency (Note 8) fs Duty Cycle Serial Interface Timing (Note 9) BCLK Period tBCK BCLK Pulse Width Low tBCKL Pulse Width High tBCKH LRCK Edge to BCLK " ↑ " (Note 10) tLRB BCLK " ↑ " to LRCK Edge (Note 10) tBLR SDI Hold Time tSDH SDI Setup Time tSDS LRCK to SDO(MSB) tLRS BCLK " ↑ " to SDO tBSD Control Interface Timing CCLK Period tCCK CCLK Pulse Width Low tCCKL Pulse Width High tCCKH CDATA Hold Time tCDS CDATA Setup Time tCDH CS High Level Time tCSW CS "↓ " to CCLK " ↑ " tCSS CCLK " ↑ " to " CS " ↑ " tCSH Reset Timing RST Pulse Width tRTW RST " ↑ " to SDO delay (Note 11) tRSD 20pF) min 1.024 31.25 31.25 4 45 typ 11.2896 max 12.800 44.1 50 55 Unit MHz ns ns kHz ％ 70 70 ns ns ns ns ns ns ns ns ns 312.5 100 100 50 50 50 50 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns 150 516 ns 1/fs Notes: 7. Master clock means MCLK1 and MCLK2. 8. LRCK means LRCK1 and LRCK2. If the duty of LRCK changes larger than 5% from 50%, the AK4531A is reset by the internal phase detecting circuit automatically. Extra-DAC should operate at fs ≧ 16kHz for practical use. 9. Timing relation is specified between LRCK1 and BCLK1, or LRCK2 and BCLK2. 10. BCLK rising edge must not occur at the same time as LRCK edge. 11. These cycles are the number of LRCK rising from RST rising. M0003-E-01 1998/12 - 10 - ASAHI KASEI [AK4531A] ■ Audio Data Formats The data format of CODEC-ADC/DAC is MSB first & MSB justified with 16bit. The BCLK needs 32fs or more than 32fs cycles. The data format of Extra-DAC is MSB first & MSB justified with 18bit. In this case, BCLK needs 36fs or more than 36fs cycles. ■ Timing Diagram Clock Timing Serial Audio Interface Timing M0003-E-01 1998/12 - 11 - ASAHI KASEI [AK4531A] Control Data Interface Timing 1 Control Data Interface Timing 2 Reset Timing M0003-E-01 1998/12 - 12 - ASAHI KASEI [AK4531A] OPERATION OVERVIEW 1. Control Register Map Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 Register Name Master Volume Lch Master Volume Rch Voice Volume Lch Voice Volume Rch FM Volume Lch FM Volume Rch CD Audio Volume Lch CD Audio Volume Rch Line Volume Lch Line Volume Rch AUX Volume Lch AUX Volume Rch Mono1 volume Mono2 volume MIC volume Mono-out Volume Output Mixer SW 1 Output Mixer SW 2 Lch Input Mixer SW 1 Rch Input Mixer SW 1 Lch Input Mixer SW 2 Rch Input Mixer SW 2 Reset & Power Down Clock Select AD Input Select MIC Amp Gain D7 MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE TMIC TMIC D6 D5 D4 ATT4 ATT4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 D3 ATT3 ATT3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 D2 ATT2 ATT2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 ATT2 FML FMR LineL LineR CDL AUXL AUXR VoiceL VoiceR FML FMR LineL LineR CDL FML FMR LineL LineR CDL TMono1 TMono2 AUXL AUXR VoiceL TMono1 TMono2 AUXL AUXR VoiceR D1 ATT1 ATT1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 ATT1 CDR Mono2 CDR CDR Mono2 Mono2 PD CSEL2 D0 ATT0 ATT0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 ATT0 MIC Mono1 MIC MIC Mono1 Mono1 RST CSEL1 ADSEL MGAIN Notes. ATT * is data bits for the attenuation level. GAI * is data bits for the gain level. 2. WRITE Timing of Control Register M0003-E-01 1998/12 - 13 - ASAHI KASEI [AK4531A] 3. Control Register Definitions Addr Register Name 00 Master Volume Lch 01 Master Volume Rch D7 MUTE MUTE MUTE 1:Mute. ATT4:0 32 levels with 2dB step 00000: 0dB 11111: -62dB Initial Addr 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E D7 MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE 1: Mute. GAI4:0 32 levels with 2dB step 00000: +12dB 00110: 0dB 11111: -50dB Initial "1000 0110" (Mute & 0dB). Addr Register Name 0F Mono-out Volume ATT2:0 Initial D5 D4 ATT4 ATT4 D3 ATT3 ATT3 D2 ATT2 ATT2 D1 ATT1 ATT1 D0 ATT0 ATT0 D6 D5 D4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 GAI4 D3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 GAI3 D2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 GAI2 D1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 GAI1 D0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 GAI0 D6 D5 D4 D3 D2 ATT2 D1 ATT1 D0 ATT0 "1000 0000" (Mute & 0dB). Register Name Voice Volume Lch Voice Volume Rch FM Volume Lch FM Volume Rch CD Audio Volume Lch CD Audio Volume Rch Line Volume Lch Line Volume Rch AUX Volume Lch AUX Volume Rch Mono1 volume Mono2 volume MIC volume MUTE D6 D7 MUTE 1:Mute. 8 levels with 4dB step 000: 0dB 111: -28dB "1000 0000" (Mute & 0dB). M0003-E-01 1998/12 - 14 - ASAHI KASEI Addr 10 11 12 13 14 15 [AK4531A] Register Name Output Mixer SW 1 Output Mixer SW 2 Lch Input Mixer SW 1 Rch Input Mixer SW 1 Lch Input Mixer SW 2 Rch Input Mixer SW 2 D7 TMIC TMIC D6 FML D5 D4 FMR LineL AUXL AUXR FML FMR LineL FML FMR LineL TMono1 TMono2 AUXL TMono1 TMono2 AUXL D3 D2 D1 D0 LineR CDL CDR MIC VoiceL VoiceR Mono2 Mono1 LineR CDL CDR MIC LineR CDL CDR MIC AUXR VoiceL Mono2 Mono1 AUXR VoiceR Mono2 Mono1 ON/OFF of Mixer Switches 0: OFF 1: ON Initial "0000 0000" (All OFF). Addr Register Name 16 17 18 19 D7 D6 D5 D4 D3 Reset & Power Down Clock Select AD Input Select MIC Amp Gain RST D2 D1 D0 PD RST CSEL2 CSEL1 ADSEL MGAIN initializes the contents of all registers. When RST pin goes "L", this register becomes "1". 1: Normal Operation 0: Initialize PD Enables the power down. When RST pin goes "L", this register becomes "1". 1: Normal Operation 0: Power down CSEL2,1 Selects the clocks for codec in two systems （① -MCLK1,LRCK1,BCLK1; ② -MCLK2,LRCK2,BCLK2 ） . The clocks for Extra-DAC always connect to system ① . The following is the clock select table. Please refer to the block diagram about each signal name. The initial state is "1,1". Clock Select CSEL2 CSEL1 0 0 1 1 0 1 0 1 CODEC-ADC CLK3 LR3 BCK3 PLL MCLK1 MCLK2 MCLK1 LRCK2 LRCK1 LRCK2 LRCK1 BCLK2 BCLK1 BCLK2 BCLK1 CODEC-DAC CLK2 LR2 BCK2 PLL PLL MCLK2 MCLK1 LRCK2 LRCK2 LRCK2 LRCK1 BCLK2 BCLK2 BCLK2 BCLK1 * In the PLL mode, the master clock(256fs) is supplied by the PLL circuit based on LRCK2. ADSEL MGAIN Selects the input source to ADC. The initial state is "0". 0: output from Input Mixer 1: AINL/AINR inputs Selects the gain of MIC amp. The initial state is "0". 0: 0dB 1: 30dB M0003-E-01 1998/12 - 15 - ASAHI KASEI [AK4531A] 4. Explanation of each sequence 4.1. Reset & Power down · · · · · · · INIT1: Initializing all registers. INIT2: Initializing all registers except for PD,RST registers. INITA: Initializing the analog section. Initializing period is 516/fs. PD: Power down state. All analog outputs are floating. The contents of all registers are hold. Inhibit(1): Inhibits writing to all registers. Inhibit(2): Inhibits writing to all registers except for PD,RST registers. The AK4531A operates by the external clocks(MCLK1,LRCK1,BCLK1) during initializing the analog section. Figure 1. Reset & Power Down Sequence 4.2. RST pin operation "H": Normal operation "L": Initializing mode 1 (INIT1 in Figure 1) ・ Initializing all registers. ・ Inhibits writing to all registers. ・ BUSY output goes "H". ・ The initialization of the analog section starts from "↑ " of RST pin. ・ SDO pin stays "L" and BUSY pin holds "H" during the initializing period of 516/fs. 4.3. RST register operation "1": Normal Operation "0": Initializing mode 2 (INIT2 in Figure 1) ・ Initializing all registers except for PD,RST registers. ・ Inhibits writing to all registers except for PD,RST registers. ・ BUSY output goes "H". ・ RST register goes "1" when RST pin goes "L". ・ The analog section is not initialized. M0003-E-01 1998/12 - 16 - ASAHI KASEI [AK4531A] 4.4. PD register operation "1": Normal Operation "0": Power down ・ The contents of all registers are hold. ・ BUSY output goes "H". ・ PD register goes "1" when RST pin goes "L". ・ All analog outputs(LOUT,ROUT,MOUT,AOUTL,AOUTR,MAMP) go floating. ・ The initialization of the analog section starts when PD register returns to "1". ・ SDO pin stays "L" and BUSY pin holds "H" during the initializing period of 516/fs. 4.5. BUSY output pin operation BUSY output goes "H" in the following cases. ・ RST pin="L" ・ During initializing the analog section. ・ RST register="0" ・ PD register="0" ・ During PLL unlock. But this is valid only when PLL clock is selected by CSEL registers. i.e. CSEL2,1=(0,0) or (0,1). 4.6. SDO output pin operation SDO output is the 16bit data of ADC and goes "L"(0000H) in the following cases. ・ RST pin="L" ・ During initializing the analog section. ・ RST register="0" ・ PD register="0" ・ During PLL unlock. But this is valid only when PLL clock is selected as ADC clock by CSEL registers. i.e. CSEL2,1=(0,0). 4.7. CODEC-DAC analog output pins(AOUTL,AOUTR) operation These outputs are muted internally and VCOM voltage is output in the following cases. ・ RST pin="L" ・ During initializing the analog section. ・ RST register="0" ・ During PLL unlock. But this is valid only when PLL clock is selected as ADC clock by CSEL registers. i.e. CSEL2,1=(0,0) or (0,1). These outputs are floating in the following case. ・ PD register="0" 4.8. Extra-DAC analog outputs operation It is impossible to observe externally due to the internal signal. These outputs are muted internally and VCOM voltage is output in the following cases. ・ RST pin="L" ・ During initializing the analog section. ・ RST register="0" These outputs are floating in the following case. ・ PD register="0" M0003-E-01 1998/12 - 17 - ASAHI KASEI [AK4531A] 5. System clock The external clocks which are required to operate the AK4531A are MCLK, LRCK, BCLK except for PLL mode. MCLK should be synchronized with LRCK but the phase is free of care. As the AK4531A includes the phase detect circuit for LRCK, the AK4531A is reset automatically when the synchronization is out of phase by changing the clock frequencies. Therefore, the reset is not required except only upon power-up. All external clocks should always be present whenever the AK4531A is in normal operation mode. If these clocks are not provided, the AK4531A may draw excess current and do not possibly operate properly because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4531A should be in the power-down mode. 6. PLL lock speed The AK4531A has a PLL to generate the CODEC master clock. The lock in time from 4kHz to 50kHz is about 100ms. 7. Digital High Pass Filter The ADC of the AK4531A has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 6.85Hz at fs=44.1kHz and the frequency response at 20Hz is -0.5dB. It also scales with sampling rate(fs). M0003-E-01 1998/12 - 18 - ASAHI KASEI [AK4531A] SYSTEM DESIGN Figure 2,3 show the system connection diagram. An evaluation board is available which demonstrates the optimum layout, power supply arrangements and measurement results. Figure 2. Typical Connection Diagram(VT=3.3V) M0003-E-01 1998/12 - 19 - ASAHI KASEI [AK4531A] Figure 3. Typical Connection Diagram (VT=5V) 1. Grounding and Power Supply Decoupling The AK4531A requires careful attention to power supply and grounding arrangements. VD should be supplied from analog power supply. Analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4531A as possible, with the small value ceramic capacitor being the nearest. 2. On-chip voltage reference The on-chip voltage references are output on the VRAD,VRDA1,VRDA2 and VCOM pins for decoupling. The VRAD,VRDA1,VRDA2 pins are used as the reference of A/D and D/A conversion. The VCOM is a signal ground of this chip. An electrolytic capacitor less than10uF in parallel with a 0.1uF ceramic capacitor attached to these pins eliminates the effects of high frequency noise. Especially, the small value ceramic capacitors should be as near to the AK4531A as possible. No load current may be drawn from the VRAD,VRDA1,VRDA2 and VCOM pins. All signals, especially clocks, should be kept away from the VRAD,VRDA1,VRDA2 and VCOM pins in order to avoid unwanted coupling into the modulators. M0003-E-01 1998/12 - 20 - ASAHI KASEI [AK4531A] 3. Analog Inputs The mixer inputs and the ADC input are single-ended and internally biased to the VCOM voltage with 50k Ω (typ) resistance. The input signal range is typically 2.88Vpp(1Vrms). Figure 4 is an example for 2Vrms line-level input circuit. The ADC output data format is 2's complement. The AK4531A accepts input voltages from AGND to VA. The output code is 7FFFH for input above a positive full scale and 8000H for input below a negative full scale. The ideal code is 0000H with no input signal. The DC offset is cancelled by the internal HPF. Figure 4. 2Vrms Line level Input The AK4531A samples the analog inputs at 64fs. The digital filter rejects all noise higher than the stop band. However, the filter will not reject frequencies right around 64fs(and multiples of 64fs). Most audio signals do not have significant energy at 64fs. 4. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The output signal range is typically 2.80Vpp(1Vrms). The DAC input data format is 2's complement. The output voltage is a positive full scale for 7FFFH and a negative full scale for 8000H in the case of CODEC-DAC. The ideal output is VCOM voltage for 0000H. The internal switched-capacitor filter and continuous-time filter almost remove the noise generated by the delta-sigma modulator of DAC beyond the audio passband, especially low sampling rate. In case of CODEC-DAC, the noise floor level is almost constant and the audible noise level is -83dB(typ) at 8kHz sampling. However, Extra-DAC should be operated at fs ≧ 16kHz. 5. Other information 5.1. Clock change The clock change should be done after muting the DAC output by the master volume to avoid the click noise by out-of-synchronization. 5.2. Offset on mixer inputs When the mixer gain is set to +12dB, the output has pretty large offset even if the inputs are no signal. Therefore, large click noise may occur when the gain level is changed quickly. 5.3. Click noise on the analog outputs. The click noise of about -50dB occurs from the analog outputs(LOUT,ROUT,MOUT,AOUT) at the power on/off or the transition of PD register. The analog outputs should be muted externally if the click noise influences system application. M0003-E-01 1998/12 - 21 - ASAHI KASEI [AK4531A] PACKAGE ■ Package & Lead frame material Package molding compound ： Lead frame material ： Lead frame surface treatment: Epoxy Cu Solder plate M0003-E-01 1998/12 - 22 - ASAHI KASEI [AK4531A] MARKING 1) 2) 3) 4) 5) Pin #1 indication Date Code : XXXXXXX(7 digits) Marketing Code : AK4531A-VQ Country of Origin Asahi Kasei Logo M0003-E-01 1998/12 - 23 -