ASAHI KASEI [AKD4125-A] AKD4125-A AK4125 Evaluation Board Rev.1 GENERAL DESCRIPTION The AKD4125-A is an evaluation board for AK4125, the digital sample rate converter. The AKD4125-A has the digital audio interface and can achieve the interface with digital audio system via opt-connector. Ordering guide AKD4125-A --- AK4125 Evaluation Board FUNCTION • DIR/DIT with optical input/output • 10pin Header for AKM AD/DA evaluation board 5V Opt In GND AK4114 AK4114 Opt Out Regulator COAX 10pin Header COAX AK4125 DSP Data 10pin Header DSP Data Figure 1. AKD4125-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM078701> 2006/04 -1- ASAHI KASEI [AKD4125-A] Operation sequence 1) Set up the power supply lines. [VCC] (red) = +5V (for regulator) [DGND] (black) = 0V Each supply line should be distributed from the power supply unit. The regulator can be supplied 3.3V to all circuits. 2) Set up the evaluation mode, jumper pins. (See the followings.) 3) Power on. The AK4125 should be reset once bringing SW1 (PDN) “L” upon power-up. Evaluation mode (1) Setting for Input port (1) When using DIR function of AK4114 (U3) When using PORT1 (DIR) or J1 (COAX), nothing should be connected to PORT2 (INPUT). JP2 IBICK JP3 SDTI JP4 ILRCK • SW3 setting (See Table 1) Upper-side is “H” and lower-side is “L”. The audio interface format of the AK4114 is fixed to 24bit, MSB justified. IDIF2-0 and PLL2-0 of SW3 should be used by default setting. SW3 No. 1 2 3 4 5 6 7 Name DITH PLL2 PLL1 PLL0 IDIF0 IDIF1 IDIF2 ON (“H”) Dither ON OFF (“L”) Dither OFF PLL Mode Setting Fixed to default AK4125 Audio I/F Format Setting Fixed to default Default L H L H L H L Table 1. SW3 Setting <KM078701> 2006/04 -2- ASAHI KASEI [AKD4125-A] (2) All clocks are fed through the 10pin port When using PORT2 (INPUT), nothing should be connected to J1 (COAX) and PORT1 (DIR). JP2 IBICK JP3 SDTI JP4 ILRCK • SW3 setting (See Table 2) Upper-side is “H” and lower-side is “L”. SW3 No. 1 2 3 4 5 6 7 Name DITH PLL2 PLL1 PLL0 IDIF0 IDIF1 IDIF2 ON (“H”) Dither ON OFF (“L”) Dither OFF PLL Mode Setting Refer to Table 3 AK4125 Audio I/F Format Setting Refer to Table 4 Default L H L H L H L Table 2. SW3 Setting Mode PLL2 PLL1 PLL0 ILRCK Freq IBICK Freq IMCLK 0 L L L 1 L L H 8k ∼ 96kHz 8k ∼ 216kHz 16k ∼ 216kHz (Note 1) Depending on IDIF2-0 Not needed. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Master / Slave Slave IMCLK = DVSS IBICK = Input ILRCK = Input Master IMCLK = Input IBICK = Output ILRCK = Output L L H H H H L L L L H H H H H L H H Reserved L L 32fsi (Note 3) Not L H 64fsi 8k ∼ 216kHz needed. (Note 2) H L 128fsi 64fsi H H L L 128fs 8k ∼ 216kHz L H 256fs 8k ∼ 108kHz H L 512fs 8k ∼ 54kHz H H 128fs 8k ∼ 216kHz 64fs L L 192fs 8k ∼ 216kHz L H 384fs 8k ∼ 108kHz H L 768fs 8k ∼ 54kHz H H 192fs 8k ∼ 216kHz Table 3. PLL Setting (Input PORT) SMUTE (Note 4) Manual Semi-Auto Manual Semi-Auto Manual Semi-Auto Manual Semi-Auto Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter” in the datasheet. 470Ω, 0.22µF and 1nF are implemented on the evaluation board. Note 2. The IBCIK must be continuous except when the clocks are changed. Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I2S Compatible. Note 4. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode in the datasheet. <KM078701> 2006/04 -3- ASAHI KASEI [AKD4125-A] Mode 0 1 2 IDIF2 L L L IDIF1 L L H IDIF0 L H L SDTI Format 16bit, LSB justified 20bit, LSB justified 24/20bit, MSB justified 3 L H H 24/16bit, I2S Compatible 4 5 6 7 H H H H L L H H L H L H 24bit, LSB justified 24bit, MSB justified 24bit, I2S Compatible ILRCK IBICK Input Input Output Output IBICK Freq ≥ 32fsi ≥ 40fsi ≥ 48fsi ≥ 48fsi or 32fsi ≥ 48fsi 64fs 64fs Master / Slave Slave Master Reserved Table 4. Input Audio Interface Format (Input PORT) (2) Setting for Output port (1) When using DIT function of AK4114 (U4) When using PORT4 (DIT) or J2 (TX), nothing should be connected to PORT3 (OUTPUT). When BICK and LRCK frequencies are changed, the value of X’tal (X1) frequency should be changed. JP6 OBICK JP7 OLRCK • SW4 setting (See Table 5) Upper-side is “H” and lower-side is “L”. The audio interface format of the AK4114 is fixed to 24bit, MSB justified. ODIF2-0, CMODE2-0 and OBIT1-0 of SW3 should be used by default setting. SW4 No. 1 2 3 4 5 6 7 Name ODIF1 ODIF0 CMODE2 CMODE1 CMODE0 OBIT1 OBIT0 ON (“H”) OFF (“L”) AK4125 Output Audio I/F Format Setting Fixed to default AK4125 Mode Setting Fixed to default AK4125 Output bit Length Setting Fixed to default Table 5. SW4 Setting <KM078701> Default H L H L L H H 2006/04 -4- ASAHI KASEI [AKD4125-A] (2) All clocks are fed through the 10pin port When using PORT3 (OUTPUT), nothing should be connected to J2 (TX) and PORT4 (DIT). JP6 OBICK JP7 OLRCK • SW4 setting (See Table 6) Upper-side is “H” and lower-side is “L”. SW4 No. 1 2 3 4 5 6 7 Name ODIF1 ODIF0 CMODE2 CMODE1 CMODE0 OBIT1 OBIT0 ON (“H”) OFF (“L”) AK4125 Output Audio I/F Format Setting Refer to Table 7 AK4125 Mode Setting Refer to Table 8 AK4125 Output bit Length Setting Refer to Table 9 Table 6. SW4 Setting Default H L H L L H H Mode ODIF1 ODIF0 SDTO Format 0 L L LSB justified 1 L H (Reserved) 2 H L MSB justified 3 H H I2S Compatible Table 7. Output Audio Interface Format 1 (Output PORT) Mode 0 1 2 3 4 5 6 7 CMODE2 CMODE1 CMODE0 Master / Slave OMCLK L L L Master 256fso L L H Master 384fso L H L Master 512fso L H H Master 768fso H L L Slave Not used. Set to DVSS. H L H Master 128fso H H L Master 192fso H H H Master (Bypass) Not used. Set to DVSS. Table 8. Master/Slave Control (Output PORT) fso 8k ∼ 108kHz 8k ∼ 108kHz 8k ∼ 54kHz 8k ∼ 54kHz 8k ∼ 216kHz 8k ∼ 216kHz 8k ∼ 216kHz 8k ∼ 216kHz Mode OBIT1 OBIT0 SDTO Output 0 L L 16bit 1 L H 18bit 2 H L 20bit 3 H H 24bit Table 9. Output Audio Interface Format 2 (Output PORT) <KM078701> 2006/04 -5- ASAHI KASEI [AKD4125-A] Other jumper pins set up 1. JP1 (RX) : Select of RX input COAX: COAX input. RX: Optical input. <Default> 2. JP5 (CKSO) : AK4114 BICK and LRCK setting H: BICK: 2.048MHz ∼ 12.288MHz, LRCK: 32kHz ∼ 192kHz L: BICK: 2.048MHz ∼ 6.144MHz, LRCK: 32kHz ∼ 96kHz <Default> When BICK and LRCK frequencies are changed, the value of X’tal (X1) frequency should be changed. 3. JP8 (TX) : Select of TX output BNC: BNC connector (J2) output. OPT: Optical (PORT4) output. <Default> The function of the toggle SW Upper-side is “H” and lower-side is “L”. [SW1] (PDN): Resets the AK4125 and the AK4114. Keep “H” during normal operation. The AK4125 and the AK4114 should be resets once bringing “L” upon power-up. [SW2] (SMUTE): Soft mute of AK4125 Indication for LED [LED1] (UNLOCK): Monitor UNLOCK pin of the AK4125. LED turns on when unlock occurs. [LED2] (ERF): Monitor INT0 pin of the AK4114 (U3). LED turns on when unlock or parity error occurs. <KM078701> 2006/04 -6- ASAHI KASEI [AKD4125-A] MEASUREMENT RESULTS [Measurement condition] • Measurement unit • Power Supply • Band width • Temperature : Audio Precision, System Two Cascade : AVDD = DVDD = 3.3V : 10Hz ∼ FSO/2 : Room [Measurement Result] SRC Characteristics THD+N (Input = 1kHz, 0dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz Worst Case (FSO/FSI = 44.1kHz/8kHz) Dynamic Range (Input = 1kHz, −60dBFS) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz Worst Case (FSO/FSI = 192kHz/192kHz) Dynamic Range (Input = 1kHz, −60dBFS, A-weighted) FSO/FSI = 44.1kHz/48kHz <KM078701> Result Unit 130.2 124.9 130.6 124.3 116.7 dB dB dB dB dB 136.2 136.4 136.1 132.3 132.2 dB dB dB dB dB 139.6 dB 2006/04 -7- ASAHI KASEI [AKD4125-A] [Plot] AK4125 THD+N vs Input Level (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,fin=1KHz -120 -122 -124 -126 -128 -130 -132 d B F S -134 -136 -138 -140 -142 -144 -146 -148 -150 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Fig 1. THD+N vs. Input Level AK4125 THD+N vs Input Frequency (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input Level=0dBFS -80 -85 -90 -95 -100 -105 -110 d B F S -115 -120 -125 -130 -135 -140 -145 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Fig 2. THD+N vs. Input Frequency (Input = 0dBFS) <KM078701> 2006/04 -8- ASAHI KASEI [AKD4125-A] AK4125 THD+N vs Input Frequency (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input Level=-60dBFS -100 -105 -110 -115 -120 -125 -130 d B F S -135 -140 -145 -150 -155 -160 -165 -170 -175 -180 20 50 100 200 500 1k 2k 5k 10k 20k Hz Fig 3. THD+N vs. Input Frequency (Input = −60dBFS) AK4125 Linearity (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,fin=1KHz +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Fig 4. Linearity <KM078701> 2006/04 -9- ASAHI KASEI [AKD4125-A] AK4125 Frequency_Response (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input=0dBFS +1 +0.5 -0 -0.5 -1 -1.5 -2 d B F S -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k Hz Fig 5. Frequency Response AK4125 FFT Plot (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input=0dBFS,fin=1KHz +0 -10 -20 -30 -40 -50 -60 -70 -80 d B F S -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 20 50 100 200 500 1k 2k 5k 10k 20k Hz Fig 6. FFT Plot (Input = 0dBFS) <KM078701> 2006/04 - 10 - ASAHI KASEI [AKD4125-A] AK4125 FFT Plot (fsi=48KHz,fso=44.1KHz) AVDD=DVDD=3.3V,Input=-60dBFS,fin=1KHz +0 -10 -20 -30 -40 -50 -60 -70 -80 d B F S -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 20 50 100 200 500 1k 2k 5k 10k 20k Hz Fig 7. FFT Plot (Input = −60dBFS) AK4125 Frequency_Response (Blue:fsi=48KHz, Red:fsi=96KHz, Green:fsi=192KHz) AVDD=DVDD=3.3V,fso=48KHz +1 +0.5 -0 -0.5 fsi=192kHz -1 -1.5 fsi=96kHz -2 -2.5 d B F S fsi=48kHz -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k Hz Fig 8. Frequency Response <KM078701> 2006/04 - 11 - ASAHI KASEI [AKD4125-A] AK4125 Frequency_Response (Yellow:fsi=44.1KHz, Blue:fsi=48KHz, Red:fsi=96KHz,Green:fsi=192KHz) AVDD=DVDD=3.3V,fso=44.1KHz +1 +0.5 -0 fsi=44.1kHz -0.5 fsi=192kHz -1 -1.5 fsi=96kHz -2 -2.5 d B F S fsi=48kHz -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k Hz Fig 9. Frequency Response <KM078701> 2006/04 - 12 - ASAHI KASEI [AKD4125-A] Revision History Date (YY/MM/DD) 05/06/30 Manual Revision KM078700 Board Revision 0 06/04/18 KM078701 1 Reason Contents First Edition Circuit Change Condenser C24, C25: Value Change: openÆ5p IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM078701> 2006/04 - 13 - A B C D E E 1 D1 HSU119 R1 10k E 1 1 H 3 L C1 0.1u SW1 ATE1D-2M3 2 3 U1A 74HC14 4 PDN REG U1B 74HC14 VCC T1 TA48M33F 2 OUT PDN C5 1n C7 0.22u REG GND 2 REG For 74HC14 x 1 REG IN U2 C2 0.1u 1 FILT AVDD 30 2 AVSS DVSS 29 3 PDN DVDD 28 4 SMUTE OMCLK 27 R2 470 C8 0.1u C3 C4 0.1u 47u + C6 0.1u + C9 10u C10 0.1u 2 D 1 D2 HSU119 R3 10k R4 51 5 1 H 3 L C11 0.1u 6 9 U1C 74HC14 8 OMCLK U1D 74HC14 R5 51 5 DITHER OLRCK 26 OLRCK R6 51 2 SW2 ATE1D-2M3 D SMUTE 6 PLL2 OBICK 25 OBICK R7 51 R8 51 7 ILRCK 24 ILRCK SDTO IBICK ODIF1 9 SDTI ODIF0 22 10 IDIF0 CMODE2 21 IDIF1 CMODE1 12 IDIF2 CMODE0 19 13 PLL0 IMCLK 18 14 PLL1 OBIT1 17 15 UNLOCK OBIT0 16 SDTO R9 51 8 IBICK C 23 C R10 51 SDTI 11 REG DITH PLL2 PLL1 PLL0 IDIF0 IDIF1 IDIF2 B RP1 M8-1-473 REG R11 51 SW3 DSS107 1 2 3 4 5 6 7 20 14 13 12 11 10 9 8 INPUT SW4 DSS107 IMCLK 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ODIF1 ODIF0 CMODE2 CMODE1 CMODE0 OBIT1 OBIT0 B OUTPUT RP2 M8-1-473 11 7 6 5 4 3 2 1 AK4125 7 6 5 4 3 2 1 10 U1E 74HC14 47K LED1 SML-210JT REG 1 R12 1k 47K 2 UNLOCK A A Title Size A3 Date: A B C D AKD4125-A Document Number Rev AK4125 Tuesday, April 18, 2006 Sheet E 1 1 of 3 A RX(COAX) B J1 BNC-R-PC C D E C12 0.1u R13 75 E E DIF2 DIF1 DIF0 PORT1 TORX141 VCC 3 GND OUT 2 1 C13 0.1u COAX JP1 RX H HIF3G-50P-2.54DSA (3x1) OPT 1 4 C 5 H H CM1 CM0 L L Setting 128fs, 192kHz Setting PLL=ON, RX Mode D 2 ERF 37 INT1 AVDD R 38 R16 1k 39 40 VCOM 41 AVSS 42 RX0 43 NC 44 RX1 45 TEST1 46 RX2 47 NC 48 RX3 3 LED2 SML-210JT R15 18k C16 0.47u + 2 Setting 24bit, MSB justified C15 0.1u D 1 L OCKS0 OCKS1 C14 10u R14 470 U3 L + RX(OPT) REG L1 47u IPS0 U1F 74HC14 INT0 NC OCKS0 DIF0 OCKS1 TEST2 CM1 DIF1 CM0 36 13 12 35 34 33 C R17 100 32 IMCLK 6 7 AK4114 NC PDN DIF2 XTI IPS1 XTO P/SN DAUX XTL0 MCKO2 31 30 PDN R18 100 PORT2 A1-10PA-2.54DSA IBICK R19 100 8 9 29 R20 100 28 1 2 3 4 5 10 9 8 7 6 INPUT SDTI B 10 IMCLK IBICK ILRCK SDTI ILRCK R21 220k 27 R22 220k R23 220k B R24 220k JP2 HIF3G-50P-2.54DSA (2x1) IBICK 11 XTL1 12 VIN BICK 26 SDTO 25 LRCK 24 MCKO1 23 22 DVSS DVDD 21 VOUT 20 UOUT 19 BOUT COUT 18 JP4 HIF3G-50P-2.54DSA (2x1) ILRCK C20 10u + A C18 0.1u A + C19 10u 17 TX1 16 TX0 15 C17 0.1u 14 13 TVDD DVSS JP3 HIF3G-50P-2.54DSA (2x1) SDTI Title Size A3 Date: A B C D AKD4125-A Document Number Rev INPUT Tuesday, April 18, 2006 1 Sheet E 2 of 3 A B C D E REG + E Setting DIF2 DIF1 DIF0 C21 10u H L L E 24bit, MSB justified C22 0.1u OCKS1 1 IPS0 2 37 INT1 R AVDD 39 40 VCOM 41 AVSS 42 RX0 43 NC 44 RX1 45 TEST1 46 RX2 RX3 NC 48 47 + U4 38 C23 0.47u INT0 36 NC OCKS0 35 3 DIF0 OCKS1 34 4 TEST2 CM1 33 Setting OCKS0 L L 256fs, 96kHz H H 128fs, 192kHz CM1 CM0 L H Setting PLL=OFF, X'tal Mode H D D JP5 HIF3G-50P-2.54DSA (3x1) CKSO R25 100 L OMCLK R26 100 5 DIF1 R27 100 32 CM0 PORT3 A1-10PA-2.54DSA OBICK OMCLK OBICK OLRCK SDTO OLRCK 7 C AK4114 NC 31 PDN C24 5p DIF2 30 XTI R28 100 PDN R29 220k IPS1 XTO 29 9 P/SN DAUX 28 XTL0 MCKO2 11 XTL1 BICK 26 12 VIN SDTO 25 OUTPUT R30 220k R31 220k R32 220k C 2 X1 HC-49/U 11.2896MHz 8 10 9 8 7 6 SDTO 1 6 1 2 3 4 5 C25 5p 10 27 PORT4 TOTX141 TX(OPT) IN VCC GND 1 C31 0.1u LRCK 24 MCKO1 23 22 DVSS DVDD B JP7 HIF3G-50P-2.54DSA (2x1) OLRCK + OPT 3 2 C27 0.1u C29 10u + C28 10u 21 20 VOUT UOUT 19 COUT 18 BOUT 17 TX0 TX1 16 C26 0.1u 15 13 B 14 TVDD DVSS JP6 HIF3G-50P-2.54DSA (2x1) OBICK BNC JP8 TX C30 0.1u R33 240 HIF3G-50P-2.54DSA (3x1) T2 DA-02F J2 BNC-R-PC TX(BNC) R34 150 1:1 A A Title Size A3 Date: A B C D AKD4125-A Document Number Rev OUTPUT Tuesday, April 18, 2006 Sheet E 1 3 of 3