ASAHI KASEI [AK4388] AK4388 192kHz 24-Bit 2ch ∆Σ DAC GENERAL DESCRIPTION The AK4388 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator, the AK4388 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4388 integrates a combination of SCF and CTF filters increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate make this part ideal for a wide range of applications including DVD-Audio. The AK4388 is offered in a space saving 16pin TSSOP package. FEATURES Sampling Rate Ranging from 8kHz to 192kHz 128 times Oversampling (Normal Speed Mode) 64 times Oversampling (Double Speed Mode) 32 times Oversampling (Quad Speed Mode) 24-Bit 8 times FIR Digital Filter SCF with High Tolerance to Clock Jitter Single Ended Output Buffer Digital de-emphasis Soft mute 2 I/F format: 24-Bit MSB justified, 24/16-Bit LSB justified or I S Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode) 256fs or 384fs (Double Speed Mode) 128fs, 192fs (Quad Speed Mode) THD+N: -90dB Dynamic Range: 106dB Power supply: 4.5 to 5.5V Very Small Package: 16pin TSSOP (6.4mm x 5.0mm) AK4384 Parallel Mode Compatible MCLK VDD DEM SMUTE ACKS DIF0 DIF1 LRCK BICK SDTI Control Port De-emphasis Control VSS Clock Divider VCOM DZF Audio Data Interface 8X Interpolator ∆Σ Modulator SCF LPF AOUTL 8X Interpolator ∆Σ Modulator SCF LPF AOUTR RSTN MS0485-E-01 2006/07 -1- ASAHI KASEI [AK4388] Ordering Guide -20 ∼ +85°C 16pin TSSOP (0.65mm pitch) -40 ∼ +85°C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4388 AK4388ET AK4388VT AKD4388 Pin Layout MCLK 1 16 DZF BICK 2 15 DEM SDTI 3 14 VDD LRCK 4 13 VSS RSTN 5 12 VCOM SMUTE 6 11 AOUTL ACKS 7 10 AOUTR DIF0 8 9 DIF1 Top View Compatibility with AK4384 1. Function Functions THD+N Output Voltage Slow Roll-Off Filter Mode Setting DEM in Parallel control Audio Format in Parallel control AK4384 -94dB 3.4Vpp Available Serial/Parallel Not Available 24-Bit I2S 24-Bit MSB justified Zero Data Detect Pin 2. Pin Configuration AK4388 AK4384 MCLK MCLK BICK BICK SDTI SDTI LRCK LRCK RSTN PDN SMUTE SMUTE/CSN ACKS ACKS/CCLK DIF0 DIF0/CDTI 2 pins Pin# 1 2 3 4 5 6 7 8 Pin# 16 15 14 13 12 11 10 9 AK4388 -90dB 3.2Vpp Not Available Parallel Available 24/16-Bit I2 S 24-Bit MSB justified 24/16-Bit LSB justified 1 pin AK4384 AK4388 DZFL DZF DZFR DEM (pd) VDD VDD VSS VSS VCOM VCOM AOUTL AOUTL AOUTR AOUTR P/S (pu) DIF1 (pu) Different points from AK4384 * pu: Pull-up, pd: Pull-down MS0485-E-01 2006/07 -2- ASAHI KASEI [AK4388] PIN/FUNCTION No. 1 Pin Name MCLK I/O I 2 3 4 5 BICK SDTI LRCK RSTN I I I I 6 SMUTE I 7 ACKS I 8 9 10 11 12 DIF0 DIF1 AOUTR AOUTL VCOM I I O O O 13 14 VSS VDD - 15 DEM I Function Master Clock Input Pin An external TTL clock should be input on this pin. Audio Serial Data Clock Pin Audio Serial Data Input Pin L/R Clock Pin Reset Mode Pin When at “L”, the AK4388 is in the power-down mode and is held in reset. The AK4388 must be reset once upon power-up. Soft Mute Pin “H”: Enable, “L”: Disable Auto Setting Mode Pin “L”: Manual Setting Mode, “H”: Auto Setting Mode Audio Data Interface Format Pin Audio Data Interface Format Pin (Internal pull-up pin) Rch Analog Output Pin Lch Analog Output Pin Common Voltage Pin, VDD/2 Normally connected to VSS with a 10µF electrolytic cap. Ground Pin Power Supply Pin De-emphasis Mode Pin (Internal pull-down pin) When at “H”, the de-emphasis filter is available. 16 DZF O Zero Input Detect Pin Note: All input pins except pull-up and pull-down pins should not be left floating. ABSOLUTE MAXIMUM RATINGS (VSS=0V; Note 1) Parameter Symbol min Power Supply VDD -0.3 Input Current (any pins except for supplies) IIN Input Voltage VIND -0.3 Ambient Operating Temperature AK4388ET Ta -20 AK4388VT Ta -40 Storage Temperature Tstg -65 Note: 1. All voltages with respect to ground. max 6.0 ±10 VDD+0.3 85 85 150 Units V mA V °C °C °C WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Power Supply Symbol VDD min 4.5 typ 5.0 max 5.5 Units V *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0485-E-01 2006/07 -3- ASAHI KASEI [AK4388] ANALOG CHARACTERISTICS (Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 3) THD+N fs=44.1kHz 0dBFS –90 –80 dB BW=20kHz –60dBFS –42 dB fs=96kHz 0dBFS –90 dB BW=40kHz –60dBFS –39 dB fs=192kHz 0dBFS –85 dB BW=40kHz –60dBFS –39 dB Dynamic Range (-60dBFS with A-weighted) (Note 4) 98 106 dB S/N (A-weighted) (Note 5) 98 106 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy Gain Drift 100 ppm/°C Output Voltage (Note 6) 2.95 3.20 3.45 Vpp Load Resistance (Note 7) 5 kΩ Load Capacitance 25 pF Power Supplies Power Supply Current (VDD) 16 mA Normal Operation (RSTN pin = “H”, fs ≤ 96kHz) 18 27 mA Normal Operation (RSTN pin = “H”, fs = 192kHz) 60 160 µA Power-Down Mode (RSTN pin = “L”) (Note 8) Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual. 4. 100dB at 16bit data. 5. S/N does not depend on input bit length. 6. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, AOUT (typ.@0dB) = 3.20Vpp × VDD/5. 7. For AC-load. 8. DIF1 pin is tied to VDD and the other all digital inputs including clock pins (MCLK, BICK and LRCK) are tied to VSS. MS0485-E-01 2006/07 -4- ASAHI KASEI [AK4388] FILTER CHARACTERISTICS (Ta = 25°C; VDD = 4.5 ∼ 5.5V; fs = 44.1kHz) Parameter Symbol min typ max Units Digital filter (DEM = OFF) PB 0 20.0 kHz Passband ±0.05dB (Note 9) 22.05 kHz –6.0dB Stopband (Note 9) SB 24.1 kHz dB Passband Ripple PR ± 0.02 Stopband Attenuation SA 54 dB Group Delay (Note 10) GD 19.3 1/fs De-emphasis Filter (DEM = ON) De-emphasis Error fs = 32kHz –1.5/0 dB (Relative to 0Hz) fs = 44.1kHz –0.2/+0.2 dB fs = 48kHz 0/+0.6 dB Digital Filter + LPF (DEM = OFF) Frequency Response 20.0kHz fs=44.1kHz FR dB ±0.2 40.0kHz fs=96kHz FR dB ±0.3 80.0kHz fs=192kHz FR dB +0.1/-0.6 Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs. 10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. MS0485-E-01 2006/07 -5- ASAHI KASEI [AK4388] DC CHARACTERISTICS (Ta=25°C; VDD=4.5 ∼ 5.5V) Parameter Symbol min typ max Units High-Level Input Voltage VIH 2.2 V Low-Level Input Voltage VIL 0.8 V High-Level Output Voltage (Iout=-80µA) VOH VDD-0.4 V Low-Level Output Voltage (Iout=80µA) VOL 0.4 V Input Leakage Current (Note 11) Iin µA ± 10 Note: 11. Except DIF1 and DEM pins. DIF1 pin has internal pull-up device, DEM pin has internal pull-down device, nominally 100kΩ. SWITCHING CHARACTERISTICS (Ta=25°C; VDD=4.5 ∼ 5.5V; CL=20pF) Parameter Symbol min typ fCLK 2.048 11.2896 Master Clock Frequency Duty Cycle dCLK 40 LRCK Frequency Normal Speed Mode fsn 8 Double Speed Mode fsd 32 Quad Speed Mode fsq 120 Duty Cycle Duty 45 Audio Interface Timing BICK Period Normal Speed Mode tBCK 1/128fs Double/Quad Speed Mode tBCK 1/64fs BICK Pulse Width Low tBCKL 30 Pulse Width High tBCKH 30 tBLR 20 BICK “↑” to LRCK Edge (Note 12) tLRB 20 LRCK Edge to BICK “↑” (Note 12) tSDH 20 SDTI Hold Time tSDS 20 SDTI Setup Time Reset Timing RSTN Pulse Width (Note 13) tRST 150 Notes: 12. BICK rising edge must not occur at the same time as LRCK edge. 13. The AK4388 can be reset by bringing RSTN pin = “L”. MS0485-E-01 max 36.864 60 Units MHz % 48 96 192 55 kHz kHz kHz % ns ns ns ns ns ns ns ns ns 2006/07 -6- ASAHI KASEI [AK4388] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Serial Interface Timing tRSTN RSTN VIL Power-down Timing MS0485-E-01 2006/07 -7- ASAHI KASEI [AK4388] OPERATION OVERVIEW System Clock The external clocks, which are required to operate the AK4388, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS pin = “L”, Normal Speed Mode), the frequency of MCLK is set automatically (Table 1). After exiting reset (RSTN pin= “↑”), the AK4388 is in Auto Setting Mode. In Auto Setting Mode (ACKS pin = “H”), as MCLK frequency is detected automatically (Table 2), and the internal master clock becomes the appropriate frequency (Table 3). All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4388 is in the normal operation mode (RSTN pin = ”H”). If these clocks are not provided, the AK4388 may draw excess current and may fall into unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4388 should be reset by RSTN pin = “L” after threse clocks are provided. If the external clocks are not present, the AK4388 should be in the power-down mode (RSTN pin = “L”). After exiting reset at power-up etc., the AK4388 is in the power-down mode until MCLK and LRCK are input. LRCK fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920MHz 11.2896MHz 12.2880MHz MCLK 512fs 16.3840MHz 22.5792MHz 24.5760MHz 384fs 12.2880MHz 16.9344MHz 18.4320MHz 768fs 24.5760MHz 33.8688MHz 36.8640MHz 1152fs 36.8640MHz N/A N/A BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz Table 1. System Clock Example (Manual Setting Mode, ACKS pin = “L”, Normal Speed Mode) MCLK 1152fs 512fs 256fs 128fs 768fs 384fs 192fs Mode Normal Normal Double Quad Sampling Rate 8kHz~32kHz 8kHz~48kHz 32kHz~96kHz 120kHz~192kHz Table 2. Sampling Speed (Auto Setting Mode, ACKS pin = “H”) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 192fs 33.8688 36.8640 256fs 8.1920 11.2896 12.2880 22.5792 24.5760 - MCLK (MHz) 384fs 512fs 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 33.8688 36.8640 - 768fs 24.5760 33.8688 36.8640 - 1152fs 36.8640 - Table 3. System Clock Example (Auto Setting Mode, ACKS pin = “H”) When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (Table 2). But, when the sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs. ACKS pin L H H MCLK 256fs/384fs/512fs/768fs 256fs/384fs 512fs/768fs DR,S/N 106dB 103dB 106dB Table 4. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz) MS0485-E-01 2006/07 -8- ASAHI KASEI [AK4388] Audio Serial Interface Format Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-1 as shown in Table 5 can select four serial data modes. DIF1 pin is internal pull-up pin. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 0 1 DIF1 L L DIF0 L H SDTI Format 16bit MSB justified 24bit MSB justified BICK ≥32fs ≥48fs 2 H L 24bit LSB justified 3 H H 16/24bit I2S Compatible Figure Figure 1 Figure 2 ≥48fs Figure 3 ≥48fs or 32fs Figure 4 Table 5. Audio Data Formats LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 14 6 1 0 5 14 3 4 15 2 16 17 1 15 0 31 0 14 6 5 14 1 4 15 3 16 2 17 1 0 31 15 14 0 1 0 1 BICK (64fs) SDTI Mode 0 Don’t care 15 14 0 Don’t care 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDTI Mode 1 Don’t care 23 22 21 20 19 0 Don’t care 23 22 21 20 19 0 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1 Timing MS0485-E-01 2006/07 -9- ASAHI KASEI [AK4388] LRCK 0 1 2 23 22 30 24 31 0 2 1 22 23 24 30 31 0 1 BICK (64fs) SDTI Mode 2 23 22 1 0 23 Don’t care 22 1 0 Don’t care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing LRCK 0 1 2 3 23 25 24 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI Mode 3 23 22 1 0 23 Don’t care 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing De-emphasis Filter A digital de-emphasis filter is built-in (tc = 50/15µs). DEM pin is internal pull-down pin. The digital de-emphasis filter is enabled by setting DEM pin “H”. Refer to the section of “FILTER CHARACTERISTICS” regarding the gain error when the de-emphasis filter is enabled. DEM pin De-emphasis Filter 1 0 ON OFF Default Table 6. De-emphasis Filter Control MS0485-E-01 2006/07 - 10 - ASAHI KASEI [AK4388] Zero Detection When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”. DZF pin immediately goes to “L” if input data of both channels are not zero after going DZF “H”(Figure 5). Soft Mute Operation Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by -∞ during 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit ATT Level (1) (1) (3) Attenuation -∞ GD (2) GD AOUT DZF pin (4) 8192/fs Notes: (1) 1020LRCK cycles (1020/fs) at input data is attenuated to -∞. (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”. Figure 5. Soft Mute and Zero Detection MS0485-E-01 2006/07 - 11 - ASAHI KASEI [AK4388] System Reset The AK4388 must be reset once by bringing RSTN pin = “L” upon power-up. The AK4388 is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4388 is in the power-down mode until LRCK are input. Power ON/OFF timing AK4388 is placed in the power-down mode by bringing RSTN pin “L” and the registers are initialized. The analog outputs go to VCOM (VDD/2). Since some click noise occurs at the edge of the RSTN signal, the analog output should be muted externally if the click noise influences system application. Power RSTN pin Internal State DAC In (Digital) Normal Operation (2) “0”data (2) “0”data GD (1) (3) DAC Out (Analog) Reset GD (3) (4) Clock In Don’t care Don’t care MCLK,LRCK,BICK (6) DZF External Mute (5) Mute ON Mute ON Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are VCOM (VDD/2) in power-down mode. (3) Click noise occurs at the edge of RSTN signal. This noise is output even if “0” data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (RSTN pin = “L”). (5) Mute the analog output externally if the click noise (3) influences the system application. The timing example is shown in this figure. (6) DZF pins are “L” in the power-down mode (RSTB pin = “L”). Figure 6. Power-down/up Sequence Example MS0485-E-01 2006/07 - 12 - ASAHI KASEI [AK4388] SYSTEM DESIGN Figure 7 shows the system connection diagram. An evaluation board (AKD4388) is available in order to allow an easy study on the layout of a surrounding circuit. Master Clock 1 MCLK DZF 16 64fs 2 BICK DEM 15 24bit Audio Data 3 SDTI VDD 14 fs Reset & Power down Optional External Mute Circuits 0.1u VSS 13 VCOM 12 SMUTE AOUTL 11 7 ACKS AOUTR 10 8 DIF0 DIF1 9 4 LRCK 5 RSTN 6 AK4388 + + 10u Analog Supply 5V 10u Lch Out Mode Setting Digital Ground Rch Out Analog Ground Figure 7. Typical Connection Diagram Notes: - LRCK = fs, BICK = 64fs. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins except DIF1 and DEM pins should not be left floating. MS0485-E-01 2006/07 - 13 - ASAHI KASEI [AK4388] 1. Grounding and Power Supply Decoupling VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to VDD as possible. The differential Voltage between VDD and VSS pins set the analog output range. 2. Analog Outputs The analog outputs are single-ended and centered around the VCOM voltage. The output signal range is typically 3.20Vpp (typ@VDD=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV. Figure 8 shows an example of the external LPF with 3.20Vpp (1.13Vrms) output. Figure 9 shows an example of the external LPF with 2Vrms output. AK4388 10u 220 Analog Out AOUT 3.2Vpp (1.13Vrms) 2.2nF 22k fc=328.8kHz, g=-0.064dB at 40kHz Figure 8. External 1st order LPF Circuit Example (simple) 390p 3.9k 3.3k +Vop AK4388 10u 2.7k Analog Out 3.9k AOUT 22k 390p -Vop 5.93Vpp (2.09Vrms) fc=125.8kHz, Q=0.752, g=0.058dB at 40kHz Figure 9. External 2nd order LPF Circuit Example (using op-amp with dual power supplies) MS0485-E-01 2006/07 - 14 - ASAHI KASEI [AK4388] PACKAGE 16pin TSSOP (Unit: mm) *5.0±0.1 9 A 8 1 0.13 M 6.4±0.2 *4.4±0.1 16 1.05±0.05 0.22±0.1 0.17±0.05 0.65 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0485-E-01 2006/07 - 15 - ASAHI KASEI [AK4388] MARKING (AK4388ET) AKM 4388ET XXYYY 1) 2) 3) 4) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4388ET Asahi Kasei Logo MS0485-E-01 2006/07 - 16 - ASAHI KASEI [AK4388] MARKING (AK4388VT) AKM 4388VT XXYYY 1) Pin #1 indication 2) Data Code : XXYYY(5 digits) XX: Lot# YYY: Date Code 3) Marketing Code : 4388VT 4) Asahi Kasei Logo MS0485-E-01 2006/07 - 17 - ASAHI KASEI Date (YY/MM/DD) 06/04/24 06/07/28 [AK4388] Revision 00 00 Reason First edition Error Correction Page Contents 12 Figure 6 DZF1/DZF2 Æ DZF “(6) DZF pins are “L” in the power-down mode (RSTB pin = “L”).” was added. Figure 8 fc=154kHz, g=0.284dB at 40kHz Æ fc=328.8kHz, g=-0.064dB at 40kHz 14 IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or dev ices or systems containing them, may require an export license or other official approv al under the law and regulations of the country of export pertaining to customs and tariff s, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any saf ety, life support, or other hazard related dev ice or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representativ e Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for lif e support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the saf ety or effectiveness of the device or system containing it, and which must therefore meet v ery high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the abov e content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0485-E-01 2006/07 - 18 -