[AK4386] AK4386 100dB 96kHz 24-Bit 2ch ΔΣ DAC GENERAL DESCRIPTION The AK4386 is a 24bit low voltage & low power stereo DAC. The AK4386 uses the Advanced Multi-Bit ΔΣ architecture, this architecture achieves DR=100dB at 3V operation. The AK4386 integrates a combination of SCF and CTF filters increasing performance for systems with excessive clock jitter. The AK4386 is suitable for the portable audio system like MP3 and the home audio systems like STB and TV, etc as low power and small package. The AK4386 is offered in a space saving 16pin TSSOP package. FEATURES Sampling Rate: 8kHz ∼ 96kHz 24-Bit 8 times FIR Digital Filter SCF with high tolerance to clock jitter Single-ended output buffer Digital de-emphasis for 44.1kHz sampling I/F Format: 24-Bit MSB justified, 16/24-Bit LSB justified, I2S Compatible Master Clock: 512/768/1024/1536fs for Half Speed (8kHz ∼ 24kHz) 256/384/512/768fs for Normal Speed (8kHz ∼ 48kHz) 128/192/256/384fs for Double Speed (48kHz ∼ 96kHz) CMOS Input Level THD+N: −86dB DR, S/N: 100dB(@VDD=3.0V) Power Supply: 2.2 to 3.6V Ta = −20 ∼ 85°C (ET), −40 ∼ 85°C (VT) 16pin TSSOP TEST PDN DEM MCLK VDD De-emphasis Control DFS1 VSS Clock Divider VCOM DFS0 LRCK BICK SDTI Audio Data Interface DIF1 8X Interpolator ΔΣ Modulator SCF CTF LOUT 8X Interpolator ΔΣ Modulator SCF CTF ROUT DIF0 MS0280-E-01 2008/10 -1- [AK4386] ■ Ordering Guide AK4386ET AK4386VT AKD4386 −20 ∼ +85°C 16pin TSSOP (0.65mm pitch) −40 ∼ +85°C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4386 ■ Pin Layout MCLK 1 16 TEST BICK 2 15 DIF1 SDTI 3 14 VDD LRCK 4 13 VSS PDN 5 12 VCOM DFS0 6 11 LOUT DFS1 7 10 ROUT DEM 8 9 DIF0 Top View MS0280-E-01 2008/10 -2- [AK4386] PIN/FUNCTION No. Pin Name 1 MCLK 2 BICK 3 SDTI 4 LRCK I/O I I I I 5 PDN I 6 7 DFS0 DFS1 I I 8 DEM I 9 10 11 DIF0 ROUT LOUT I O O 12 VCOM O 13 14 15 VSS VDD DIF1 I 16 TEST I Function Master Clock Input Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Input Channel Clock Pin Full Power Down Mode Pin “L” : Power down, “H” : Power up Sampling Speed Select 0 Pin Sampling Speed Select 1 Pin De-emphasis Filter Enable Pin “L” : OFF, “H” : ON (De-emphasis of fs=44.1kHz is enable.) Audio Interface Format 0 Pin Rch Analog Output Pin Lch Analog Output Pin Common Voltage Output Pin, 0.55 × VDD Normally connected to VSS with a 4.7μF (min. 1μF, max. 10μF) electrolytic capacitor. Ground Pin Power Supply Pin, 2.2 ∼ 3.6V Audio Interface Format 1 Pin TEST Pin This pin should be connected to VDD. Note: All digital input pins should not be left floating. ■ Handling of Unused Pin The unused output pins should be processed appropriately as below. Classification Analog Pin Name LOUT, ROUT MS0280-E-01 Setting This pin should be open. 2008/10 -3- [AK4386] ABSOLUTE MAXIMUM RATINGS (VSS=0V; Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Powered applied) AK4386ET AK4386VT Storage Temperature Symbol VDD IIN VIND Ta Ta Tstg min −0.3 −0.3 −20 −40 −65 max 4.6 ±10 VDD+0.3 85 85 150 Units V mA V °C °C °C Note 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Power Supply Symbol VDD min 2.2 typ 3.0 max 3.6 Units V Note 1. All voltages with respect to ground. WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0280-E-01 2008/10 -4- [AK4386] ANALOG CHARACTERISTICS (Ta=25°C; VDD=3.0V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 20Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units Dynamic Characteristics: Resolution 24 Bits 0dBFS THD+N fs=44.1kHz −86 −76 dB −60dBFS BW=20kHz −37 dB 0dBFS fs=96kHz −84 dB −60dBFS BW=40kHz −34 dB DR (−60dBFS with A-weighted) 92 100 dB S/N (A-weighted) 92 100 dB Interchannel Isolation 80 100 dB DC Accuracy: Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 100 ppm/°C Output Voltage (Note 2) 1.85 2.0 2.15 Vpp Load Resistance (Note 3) 10 kΩ Load Capacitance 25 pF Power Supplies Power Supply Current mA 9 6 Normal Operation (PDN pin = “H”, fs=44.1kHz) mA 10 6.5 Normal Operation (PDN pin = “H”, fs=96kHz) mA 2.5 1.5 Power Save mode (PDN pin = “H”, MCLK Stop) μA 50 10 Full Power-down mode (PDN pin = “L”) (Note 4) Note 2. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, Vout = 0.67 × VDD (typ). Note 3. For AC-load. Note 4. All digital input pins are fixed to VDD or VSS. MS0280-E-01 2008/10 -5- [AK4386] FILTER CHARACTERISTICS (Ta=25°C; VDD=2.2 ∼ 3.6V; fs=44.1kHz; DEM=OFF) Parameter Symbol min DAC Digital Filter: Passband (Note 5) ±0.05dB PB 0 −6.0dB Stopband (Note 5) SB 24.1 Passband Ripple PR Stopband Attenuation SA 64 Group Delay (Note 6) GD Digital Filter + SCF + CTF: FR Frequency Response 0 ∼ 20kHz ∼ 40kHz (Note 7) typ max Units 22.05 20.0 - 24.0 - kHz kHz kHz dB dB 1/fs ±0.5 ±1.0 - dB dB ±0.01 Note 5. The passband and stopband frequencies scale with fs (system sampling rate). Note 6. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. Note 7. At fs=96kHz. DC CHARACTERISTICS (Ta=25°C; VDD=2.2 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Symbol VIH VIL Iin MS0280-E-01 min 70%VDD - typ - max 30%VDD ±10 Units V V μA 2008/10 -6- [AK4386] SWITCHING CHARACTERISTICS (Ta=25°C; VDD=2.2 ∼ 3.6V) Parameter Master Clock Frequency Half Speed Mode (512/768/1024/1536fs) Normal Speed Mode (256/384/512/768fs) Double Speed Mode (128/192/256/384fs) Duty Cycle LRCK Frequency Half Speed Mode (DFS1-0 = “10”) Normal Speed Mode (DFS1-0 = “00”) Double Speed Mode (DFS1-0 = “01”) Duty Cycle Audio Interface Timing BICK Period Half Speed Mode Normal Speed Mode Double Speed Mode BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge LRCK Edge to BICK “↑” SDTI Hold Time SDTI Setup Time Power-Down & Reset Timing PDN Pulse Width (Note 8) (Note 8) (Note 9) Symbol min fCLK fCLK fCLK dCLK typ max Units 4.096 2.048 6.144 40 36.864 36.864 36.864 60 MHz MHz MHz % fsh fsn fsd dCLK 8 8 48 45 24 48 96 55 kHz kHz kHz % tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/128fs 1/64fs 70 70 40 40 40 40 ns ns ns ns ns ns ns ns ns tPD 4×C ms Note 8. BICK rising edge must not occur at the same time as LRCK edge. Note 9. The AK4386 can be reset by bringing PDN pin = “L”. The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4 × C. When C = 4.7μF, tPD is 19ms(min). The value of the capacitor (C) connected with VCOM pin should be 1μF ≤ C ≤ 10μF. When the states of DIF1-0 pins change, the AK4386 should be reset by PDN pin. MS0280-E-01 2008/10 -7- [AK4386] ■ Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Audio Interface Timing tPD PDN VIL Power Down & Reset Timing MS0280-E-01 2008/10 -8- [AK4386] OPERATION OVERVIEW ■ System Clock The external clocks, which are required to operate the AK4386, are MCLK, BICK and LRCK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 pins (Table 1). The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 pin = DFS0 pin = “H”) (Table 2). The AK4386 is automatically placed in the power save mode when MCLK stops in the normal operation mode (PDN pin = “H”), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4386 is powered up. After exiting reset at power-up etc., the AK4386 is in the power-down mode until MCLK and LRCK are input. When the states of DIF1-0 pins change in the normal operation mode, the AK4386 should be reset by PDN pin. Mode Normal Speed Double Speed Half Speed Auto DFS1 L L H H DFS0 fs L 8 ∼ 48kHz H 48 ∼ 96kHz L 8 ∼ 24kHz H 8 ∼ 96kHz Table 1. System Clock Example MCLK Frequency 512/768fs 128/192/256/384fs 1024/1536fs Sampling Speed Mode Normal Speed Double Speed Half Speed Table 2. Auto Mode MCLK Frequency 256/384/512/768fs 128/192/256/384fs 512/768/1024/1536fs Table 2 fs 8 ∼ 48kHz 48 ∼ 96kHz 8 ∼ 24kHz ■ Audio Interface Format Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 pins as shown in Table 3 can select four serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode 3 can be used for 16bit I2S Compatible format by zeroing the unused LSBs at BICK ≥ 48fs or BICK = 32fs. Mode 0 1 2 3 DIF1 L L H H DIF0 SDTI Format L 16bit, LSB justified H 24bit, LSB justified L 24bit, MSB justified H 16/24bit, I2S Compatible Table 3. Audio Interface Format MS0280-E-01 BICK ≥ 32fs ≥ 48fs ≥ 48fs ≥ 48fs or 32fs Figure Figure 1 Figure 2 Figure 3 Figure 4 2008/10 -9- [AK4386] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 0 1 2 3 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1 BICK(64fs) SDTI(i) Don't Care 15 14 13 12 1 0 Don't Care 15 14 13 12 2 1 0 SDTI-15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 2 8 9 24 31 0 1 2 8 9 24 31 0 1 BICK(64fs) SDTI(i) Don't Care 23 1 0 8 Don't Care 8 23 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1 Timing LRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing LRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing MS0280-E-01 2008/10 - 10 - [AK4386] ■ De-emphasis Filter The AK4386 includes the digital de-emphasis filter (tc=50/15μs) by IIR filter. This filter corresponds to 44.1kHz sampling. The de-emphasis filter is enabled by setting DEM pin “H”. In case of Half speed and Double speed mode, the digital de-emphasis filter is always off. Mode DFS1 pin DFS0 pin DEM pin De-emphasis Filter L L L OFF Normal Speed L L H ON Double Speed L H * OFF Half Speed H L * OFF H H L OFF Auto H H H ON (Note) Table 4. De-emephasis Filter (*: Don’t care) Note. The digital de-emphasis filter corresponds to 44.1kHz sampling. In case of Half speed and Double speed mode, the digital de-emphasis filter is always off. ■ Power-down The AK4386 is placed in the power-down mode by bringing PDN pin = “L”. and the digital filter is reset at the same time. This reset should always be done after power up. When PDN pin = “L”, DAC outputs go to Hi-Z. Also, the internal power down is automatically done when MCLK stops during operating (PDN pin =“H”), and the analog outputs go to the VCOM voltage. MCLK pin should be fixed to “H” or “L” when MCLK stops. Mode 0 1 2 PDN pin L H MCLK DAC Output Don’t care Hi-Z Supplied Normal Output Not Supplied VCOM Voltage Table 5. Power down mode MS0280-E-01 State Full Power Down Normal Power Save 2008/10 - 11 - [AK4386] (1) Power down by PDN pin PDN Internal State (1) Normal Operation Power-down D/A In (Digital) “0” data GD (2) GD (4) D/A Out (Analog) Clock In (3) (2) (4) (5) Don’t care MCLK, BICK, LRCK External MUTE Normal Operation (6) Mute ON Notes: (1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7μF is attached between VCOM pin and VSS.) (2) The analog output corresponding to digital input has the group delay (GD). (3) When PDN pin = “L”, the analog output is Hi-Z. (4) Click noise occurs in 3 ∼ 4LRCK at both edges (↑ ↓) of PDN signal. This noise is output even if “0” data is input. (5) The external clocks (MCLK, BICK and LRCK) can be stopped in the power down mode (PDN pin = “L”). (6) Please mute the analog output externally if the click noise (4) influences system application. The timing example is shown in this figure. Figure 5. Power-down/up sequence example 1 MS0280-E-01 2008/10 - 12 - [AK4386] (2) Power save by MCLK stop (PDN pin = “H”) PDN pin (1) Internal State Power-down D/A In (Digital) Power-down Normal Operation (2) GD (4) Hi-Z VCOM (2) (4) (4) Clock In (5) MCLK Stop MCLK, BICK, LRCK External MUTE Normal Operation (3) GD D/A Out (Analog) Power-save (5) (6) (6) Notes: (1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7μF is attached between VCOM pin and VSS.) (2) The analog output corresponding to digital input has the group delay (GD). (3) The digital data can be stopped. The click noise after MCLK is input again by inputting the “0” data to this section can be reduced. (4) Click noise occurs in 3 ∼ 4LRCK at both edges (↑ ↓) of PDN signal, MCLK inputs and MCLK stops. This noise is output even if “0” data is input. (5) The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop). (6) Please mute the analog output externally if the click noise (4) influences system application. The timing example is shown in this figure. Figure 6. Power-down/up sequence example 2 MS0280-E-01 2008/10 - 13 - [AK4386] SYSTEM DESIGN Figure 7 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Master Clock 1 MCLK TEST 64fs 2 BICK DIF1 15 24bit Audio Data 3 SDTI VDD 14 fs Reset & Power down Mode Setting Digital Ground 16 0.1u + 10u VSS 13 PDN VCOM 12 6 DFS0 LOUT 11 Lch Out 7 DFS1 ROUT 10 Rch Out 8 DEM DIF0 9 4 LRCK 5 AK4386 Analog Supply 2.2 to 3.6V 4.7u + (C) Analog Ground Note: - VSS of the AK4386 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - When AOUT drive some capacitive load, some resistor should be added in series between AOUT and capacitive load. - The value of the capacitor connected to VCOM pin should be 1μF ≤ C ≤ 10μF. - All digital input pins should not be left floating. Figure 7. Typical Connection Diagram 1. Grounding and Power Supply Decoupling The AK4386 requires careful attention to power supply and grounding arrangements. VDD is usually supplied from the analog supply in the system. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4386 as possible, with the small value ceramic capacitor being the closest. 2. Voltage Reference The differential Voltage between VDD and VSS sets the analog output range. VCOM is used as a common voltage of the analog signal. VCOM pin is a signal ground of this chip. An electrolytic capacitor about 4.7μF should be attached between VCOM pin and VSS. No load current may be drawn from VCOM pin. Especially, the ceramic capacitor should be connected to this pin as near as possible. 3. Analog Outputs The analog outputs are single-ended and centered around the VCOM voltage (0.55 × VDD). The output signal range is typically 2.0Vpp (typ@VDD=3.0V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage (0.55 × VDD) for 000000H (@24bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV. MS0280-E-01 2008/10 - 14 - [AK4386] PACKAGE 16pin TSSOP (Unit: mm) 5.0 16 1.10max 9 4.4 6.4±0.2 A 1 0.22±0.1 8 0.17±0.05 0.65 0.1±0.1 0.5±0.2 Detail A Seating Plane 0.10 0∼10° ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0280-E-01 2008/10 - 15 - [AK4386] MARKING (AK4386ET) AKM 4386ET XXYYY 1) 2) 3) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4386ET MS0280-E-01 2008/10 - 16 - [AK4386] MARKING (AK4386VT) AKM 4386VT XXYYY 4) 5) 6) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4386VT MS0280-E-01 2008/10 - 17 - [AK4386] REVISION HISTORY Date (YY/MM/DD) 03/12/01 08/10/23 Revision 00 01 Reason First edition Spec Addition Page Contents The AK4386ET was added. VT and ET datasheets were combined together. IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0280-E-01 2008/10 - 18 -