AKM AKD4730

ASAHI KASEI
[AKD4730-100W]
AKD4730-100W
AK4730-100W Evaluation Board Rev.4
GENERAL DESCRIPTION
The AKD4730-100W is the evaluation board of AK4730, which is one chip modulator built in two channel
PWM Modulators and Pre-Drivers of MOSFETs for Class-D Amplifier. It has the interface of the
evaluation board of AKM’s ADC, it is possible to evaluate it easily. The AKD4730 also has the digital
audio interface and can achieve the interface with digital audio systems via opt-connector.
„ Ordering guide
AKD4730-100W
--- AK4730-100W Evaluation Board
(Cable for connecting with printer port of IBM-AT compatible PC
and control software are packed with this.) This control software can’t operate
on Windows NT.
FUNCTION
† MOSFET drivers is built in
† Compatible with 2 types of interface
- The optical input
- Direct interface with AC3 decoder by 10pin header
† 10pin header for serial control interface
12V
GND
48V
Output power
100W/ 8ohm
Regulator
5V
DIR
Opt In
Lch
AK4114
10pin Header A/D
E-Bridge
Data
AK4730
Rch
10pin Header Control
Data
E-Bridge
AKM recommend MOSFETs of IRF9Z34N, IRFZ24N in International Rectifier products for E-Bridge.
The inductance for LPF is TRTT14-J026 of TDK’s product.
Figure 1. AKD4730-100W Block Diagram
<KM074904>
2005/07
-1-
ASAHI KASEI
[AKD4730-100W]
„ Operation sequence
1) Set up the power supply lines (Please refer the wiring of “ set up other jumper ”)
Terminal
Name
Color
Vp
Red
Supply
Voltage
48V
+12V
Orange
12V
GND
Black
0V
Items
Note
VP1, 2,3 pins of AK4730
Should be connected
MVDD pin of AK4730, the
Should be connected
regulator and so on.
All GND of AK4730
Should be connected
Table 1. Wiring of the power supply
Please wire the power supply carefully. (Divide wiring from each power supply)
2) Setup of each clocks to AK4730
The input method of the clocks to AK4730 has two kinds of methods. One method is from the mounted
AK4114, another is from the external inputs. These setting is selected by the jumpers of JP1(MCLK),
JP2(BICK), JP3(LRCK), JP4(SDATA).
(see the following Figures)
JP1
MCLK
JP3
BICK
JP4
SDATA
JP2
LRCK
EXT DIR
EXT DIR
EXT DIR
EXT DIR
Figure 2 Clocks input from AK4114
JP1
MCLK
JP3
BICK
JP4
SDATA
JP2
LRCK
EXT DIR
EXT DIR
EXT DIR
EXT DIR
Figure 3. Clock input from the external
3) The connections of the outputs
Analog signals are outputted to J1(Lch hot), J2(Lch cold), J6(Rch hot), J7(Rch cold). Connect each terminal
to speakers or the measurement equipment.
<KM074904>
2005/07
-2-
ASAHI KASEI
[AKD4730-100W]
Setup sequence
1, SW1 is the switch for power-off of
AK4730, AK4114. SW1 should be
switched on off-side at the time of power
supply on.
Turn on SW1 after power on.
SW1
OFF⇔ON
2, Next, write the control registers.
PORT3
Control cable
<KM074904>
Connect a control cable and a power
supply as the figure.
2005/07
-3-
ASAHI KASEI
[AKD4730-100W]
„ Setup of the DIP switch
[S2]: Setup of AK4730
No.
Pin
1
CAD1
2
3
CAD0
I2C
OFF
ON
Set the chip address up.
Default is “00”
4-wire Serial
Don’t turn it on.
Table 2. Setup of S2
Default
OFF
OFF
OFF
[S1]: Setup of AK4114
No.
Pin
1
NC
2
CM0
3
OCKS1
4
OCKS0
5
DIF0
6
7
DIF1
DIF2
OFF
ON
It isn't connected.
PLL mode
X’tal mode
Setting of MCLK output
Default is “00”(256fs)
Setting of Audio interface
Default is “101”(I2S)
Default
OFF
OFF
OFF
OFF
ON
OFF
ON
Table 3. Setup of S1
„ The function of toggle SW
[SW1](4730_PDN): Resets AK4730, AK4114. Leave SW to “H” during normal operation.
„ The indication content of LED
LED is turned on when each pin output is “H”.
[LE1] (INT1): it is the output of INT0 pin of AK4114 (the detection of AUTO DTSCD, AUDION)
[LE2] (INT0): it is the output of INT1 pin of AK4114 (the detection of UNLOCK, PAR)
<KM074904>
2005/07
-4-
ASAHI KASEI
[AKD4730-100W]
„ Serial Control
AKD4730-100W can be controlled through the printer port (a parallel port) of the IBM-AT interchange machine.
Connect PORT3 and a PC with 10 line flat cable of packing together.
10 pin Connector
10
9
Connect
PC
RED
2
10 wire flat cable
PORT3
UP-I/F
1
10 pin Header
Figure 4. The connection of 10 line flat cable
<KM074904>
2005/07
-5-
ASAHI KASEI
[AKD4730-100W]
AKD4730-100W Control Program operation manual
„ Set-up of evaluation board and control software
2
This evaluation board does not correspond to I C control.
1. Set up the AKD4730-100W according to above mentioned setting.
2. Connect IBM-AT compatible PC with AKD4730-100W by 10-line type flat cable (packed with AKD4730). Take
care of the direction of 10pin header. (Please install the driver in the CD-ROM-disk when this control software is used
on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control
software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on
Windows NT.)
3. Insert the CD-ROM-disk labeled “AKD4730-100W Evaluation Kit” into the CD-ROM-disk drive.
4. Access the CD-ROM-disk drive and double-click the icon of “akd4730_3.exe” to set up the control program.
5. Then please evaluate according to the followings.
„ Operation flow
Keep the following flow.
1. Start a control program in accordance with the above.
2. Next, it should input and output data properly, and evaluate it.
„ Explanation of each buttons
1. [Write default] :
2. [All write] :
3. [All Read] :
4. [F1] :
5. [F2] :
6. [Volume] :
7. [Read] :
8. [Write] :
initialize the registers of AK4730
The setting data of all registers on PC display is written to the AK4730 at the same time.
The setting data of all registers of the AK4730 is read out at same time.
Dialog to write data by keyboard operation.
Dialog to evaluate ATTL/ATTR
Volume and Tone can be changed by the slider buttons
The setting data of each register is read
The setting data of each register is written. “ON”/”OFF” at each bit are set up by click.
If you want to write the input data to AK4730, click “OK” button. If not, click “Cancel” button.
„ The indication of the data
The inputted data is indicated at the register map. Red character means “H” and “1”, Blue character means “L” and “0”.
The blank part is the part which is not defined by the datasheet.
<KM074904>
2005/07
-6-
ASAHI KASEI
[AKD4730-100W]
„ Explanation of each dialog
1. [Function1 Dialog] :
Address Box:
Data Box:
Dialog to write data by keyboard operation
Input register address in 2 figures of hexadecimal.
Input register data in 2 figures of hexadecimal.
If you want to write the input data to AK4730, click “OK” button. If not, click “Cancel” button.
2. [Function2 Dialog] :
Dialog to evaluate ATTL/ATTR
This dialog corresponds to only addr=02H, 03H
Address Box: Input register address in 2 figures of hexadecimal.
Start Data Box: Input start data in 2 figures of hexadecimal.
End Data Box: Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to AK4730 by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example]
Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example]
Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK4730, click “OK” button. If not, click “Cancel” button.
3. [Volume Dialog] : Dialog to write the data by the mouse operation
This dialog corresponds to only addr=02H, 03H, 04H, 05H
4. [Write Dialog] : Dialog to write data by the mouse operation
There are dialogs corresponding to each register.
Click the “Write” button corresponding to each register to set up the dialog. If you check the check box, data becomes
“H” or “1”. If not, “L” or “0”.
If you want to write the input data to AK4730, click “OK” button. If not, click “Cancel” button.
<KM074904>
2005/07
-7-
ASAHI KASEI
[AKD4730-100W]
„ Attention on the operation
In the case that the function of “Output-Short Protection” is used
Write “1” to PW bit after PROT bit was written “1”.
In the case that the function of “Adaptive Dead-Time Control” is used
Write “1” to ADTC bit after PW bit was written “1”.
If you set up Function1 or Function2 dialog, input data to all boxes. Attention dialog is indicated if you input data or
address that is not specified in the datasheet or you click “OK” button before you input data. In that case set up the dialog
and input data once more again. These operations does not need if you click “Cancel” button or check the check box.
<KM074904>
2005/07
-8-
ASAHI KASEI
[AKD4730-100W]
„ AK4730 register map
Addr Register Name
PW
00H
& Mode
Vol. Gain
01H
Control
Lch
02H
Volume
Rch
03H
Volume
TONE-Bass
04H
Control
TONE- Treble
05H
Control
Dead Time
06H
Lch 1
Dead Time
07H
Lch 2
Dead Time
08H
Rch 1
Dead Time
09H
Rch 2
Dead Time
0AH
Lch Status 1
Dead Time
0BH
Lch Status 2
Dead Time
0CH
Rch Status 1
Dead Time
0DH
Rch Status 2
D7
D6
D5
D4
D3
D2
D1
D0
DEM1
DEM0
DIF2
DIF1
DIF0
DFS1
DFS0
PW
0
SCALE1
SCALE0
GAIN2
GAIN1
GAIN0
SMUTER
SMUTEL
L7
L6
L5
L4
L3
L2
L1
L0
R7
R6
R5
R4
R3
R2
R1
R0
TFS
TLIM
TONE
B4
B3
B2
B1
B0
0
0
0
T4
T3
T2
T1
T0
0
DR1L2
DR1L1
DR1L0
0
DF1L2
DF1L1
DF1L0
0
DR2L2
DR2L1
DR2L0
0
DF2L2
DF2L1
DF2L0
0
DR1R2
DR1R1
DR1R0
0
DF1R2
DF1R1
DF1R0
0
DR2R2
DR2R1
DR2R0
0
DF2R2
DF2R1
DF2R0
0
DR1LO2
DR1LO1
DR1LO0
0
DF1LO2
DF1LO1
DF1LO0
0
DR2LO2
DR2LO1
DR2LO0
0
DF2LO2
DF2LO1
DF2LO0
0
DR1RO2
DR1RO1
DR1RO0
0
DF1RO2
DF1RO1
DF1RO0
0
DR2RO2
DR2RO1
DR2RO0
0
DF2RO2
DF2RO1
DF2RO0
0EH
Option
0
0
0
0
FIR
ADTC
PROT
PSRON
0FH
Protection
Status
0
0
0
0
0
0
0
OVRL
Note: When PDN pin is “L”, it is impossible to write the data to all registers. It is initialized.
Do not write the data to Addr.10H~1FH.
• The setting of the registers of Red character as the above Addr.“06H~09H” is recommended to
Dead-Time (for MOSFET Array SLA5097) on the AKD4730-100W evaluation board.
• When the function of ADTC is evaluated, set up the power supply (Vp) to 48V.
<KM074904>
2005/07
-9-
ASAHI KASEI
[AKD4730-100W]
„ Plots
[Measurement condition]
• Measurement unit : Audio Precision, System two, Cascade
• MCLK
: 256fs
• BICK
: 64fs
• fs
: 48kHz, 44.1kHz
• BW
: 10Hz∼20kHz
• Bit
: 24bit
• Power Supply
: AVDD=DVDD=TVDD=PVDD=5V, MVDD=12V, VP=48V(VP1=VP2=VP3 <28V)
• Interface
: AK4114
• Temperature
: Room
• Load
: 8Ω
Figure 5. THD+N vs Input Level (fin=1kHz)
Figure 6. FFT (Noise floor)
Figure 7. Linearity (fin=1kHz)
Figure 8. Triangle –80dBFS input
Figure 8. Tone control FR
<KM074904>
2005/07
- 10 -
ASAHI KASEI
[AKD4730-100W]
AKM
AK4730 Vp=48V
THD+N vs Input level
+0
-10
-20
-30
-40
-50
d
B
r
-60
-70
A
-80
-90
-100
-110
-120
-130
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 5. THD+N vs Input Level (fin=1kHz)
AKM
AK4730 Vp=48V
Out of band noise
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 6. FFT (Out of band noise)
FFT points=16384, Avg=8, Window=Equiripple
<KM074904>
2005/07
- 11 -
ASAHI KASEI
[AKD4730-100W]
AKM
AK4730 VP=48V
Linearity
05/18/04 20:26:58
+0
-10
-20
-30
-40
-50
d
B
r
-60
A
-80
-70
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
AK4730_lin.at2c
Figure 7. Linearity (fin=1kHz)
AKM
AK4730 VP=48V
-80dBFS Triangle Wave
05/18/04 20:02:01
5m
4m
3m
2m
1m
V
0
-1m
-2m
-3m
-4m
-5m
0
10m
20m
30m
40m
50m
60m
70m
80m
90m
100m
110m
120m
sec
AK4730_tri.at2c
Figure 8. Triangle –80dBFS input
<KM074904>
2005/07
- 12 -
ASAHI KASEI
[AKD4730-100W]
AKM
AK4730 Vp=48V, fs=44.1kHz
+12
+10
+8
+6
+4
d
B
r
A
+2
+0
-2
-4
-6
-8
-10
-12
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 9. Tone control FR
<KM074904>
2005/07
- 13 -
ASAHI KASEI
[AKD4730-100W]
Revision History
Date
(YY/MM/DD)
04/05/20
Manual
Revision
KM074900
04/12/14
KM074901
Board
Reason
Revision
0
First Edition
1
Circuit Change
Contents
Additions and changes of parts number due to changes of
parts of npn transistors of Output Lch and Output Rch
from 2 in 1 package to discrete. Added parts number Q33,
Q34, Q35, Q36, Q37, Q38 due to this changes.
Defined new parts number.
Changes of parts number:
Output Lch
: Output Rch
Q2A Æ Q2
:
Q18A Æ Q18
Q2B Æ Q33
: Q18B Æ Q36
Q4A Æ Q4
: Q20A Æ Q20
Q4B Æ Q34
: Q20B Æ Q37
Q8A Æ Q8
: Q24A Æ Q24
Q8B Æ Q35
: Q24B Æ Q38
Changes of parameters of circuit around AK4730:
C23, C25 : 10u Æ 47u
R4, R11 : 1M Æ 1.2M
05/01/25
KM074902
3
Board Revision Change
05/04/04
KM074903
3
05/07/19
KM074904
4
Control Software Version
Change
Control Software File Name
Change
Board Revision Change
Parts ID Change
<KM074904>
Changes of parameters of circuit around Output Lch and
Output Rch:
C87, C132 : 0.33u Æ 0.1u
R69, R92 : 200 Æ 51
Rev.A Æ Rev.3
Ver.1.0 Æ Ver.3.0
akd4730.exe Æ akd4730_3.exe
Rev.3 Æ Rev.4
Inductance for LPF: Parts ID Change
RLF12560-100M7R5 Æ TRTT14-J026
2005/07
- 14 -
ASAHI KASEI
[AKD4730-100W]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or
use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or
other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with
the express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any
and all claims arising from the use of said product in the absence of such notification.
<KM074904>
2005/07
- 15 -
4
S1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
3
2
4114_3.3V
C1
10u
4114_SETTING
RP1
C2
CM0
OCKS1
OCKS0
DIF0_DIR
DIF1_DIR
DIF2_DIR
INT1
RX0
0.1u
7
6
5
4
3
2
1
D
1
+
CM0
OCKS1
OCKS0
DIF0
DIF1
DIF2
4114_3.3V
5
D
C3
0.47u
R1
18k
R2
D1
DIODE
PDN
1
IPS0
1
1
H
L
2
38
37
INT1
R
AVDD
39
40
VCOM
41
AVSS
42
RX0
43
NC
44
RX1
45
INT0
36
INT0
NC
OCKS0
35
OCKS0
3
DIF0
OCKS1
34
OCKS1
4
TEST2
CM1
33
5
DIF1
CM0
32
CM0
PDN
31
PDN
XTI
30
10k
U2A
TEST1
46
2
DIR_VD
RX2
RX3
NC
48
U1
47
47k
U2B
2
3
4
74HCT14
74HCT14
C4
0.1u
SW1
DIF0_DIR
1
DIR_PDN
C
4114_3.3V
DIF1_DIR
L1
PORT1
GND
VCC
GND
5
OUT
TORX141
NC
7
DIF2
C7
C5
0.1u
C6
+
10u
DIF2_DIR
TORX
5p
AK4114
2
6
6
X1
RX0
R3
8
29
12.2880MHz
1
5
4
3
2
1
2
6
C
10u
IPS1
XTO
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
MCKO2
XTL1
BICK
26
4114_BICK
25
4114_SDTO
470
C8
5p
11
R5
10u
LE2
8
74HCT14
1k
LRCK
24
MCKO1
23
22
C14
10u
INT0
5V
4114_LRCK
U2D
INT1
4114_3.3V
1k
DIR_VD
74HCT14
+
C13
9
DVSS
DVDD
21
VOUT
20
UOUT
19
COUT
18
BOUT
17
TX1
16
6
DIR_VD
R6
A
1
4114_3.3V
C15
C16
0.1u
47u
OUT
GND
T1
LP2950A
0
3
IN
A
DIR_VD
C17
+
+
47u
2
INT0
C12
0.1u
0.1u
LE1
+
R4
U2C
5
B
C11
4114_3.3V
INT1
TX0
47u
15
C10
13
0.1u
+
SDTO
14
C9
VIN
TVDD
B
12
DVSS
for 74HCT14
DIR_VD
C18
0.1u
Title
AK4114
Size
A3
Date:
5
4
3
2
Document Number
Rev
3
AKD4730-100W
Tuesday, January 25, 2005
Sheet
1
1
of
5
3
5V
1
R12
10k
10u
C20
47u
R10
82k
R13
R11
1.2M
2
10k
R15
+ C21
47u
C24
2
10k
C22
C25
47u
R16
20k
VP: max 48V
VP
10k
C23
47u
NC
C26
0.1u
R19
R21
+ C27
D
0.1u
2
D
R9
10k
C19
2
+
R17
VRLO
0
1
R14
1.2M
5V
R7
VRRO
R8
10k
1
1
5V
5V
2
1
4
+
5
R20
10u
10k R18
C28
R22
10n
10k
10k
10k
R25
51k
51k
C29
10n
C30
100p
R23
220K
R24
220K
R26
1.2K
R27
1.2K
C31
100p
5V
C33
0.01u
R28
82k
C32
0.01u
VRRI
C34
1n
VRLI
C35
2.2u
R29
56k
1
C37
60
BVSS2
0.1u
2
3
R31 51k
Q2L
4
C39
C
0.0022u
R32 51k
Q1L
5
R33 51k
ADPTHR
LGATE1L
Q1L
MGATE1L
Q2R
HGATE1L
Q1R
HGATE2L
OVRL
MGATE2L
6
C41 0.0022u
TP1
TP
56
TP2
TP
55
TP3
TP
54
TP4
TP
53
TP5
TP
52
TP7
TP
R34 51k
7
Q1R
C42 0.0022u
R35
8
13k
TP6 TP
9
C43
0.47u
10
R
LGATE2L
VBG12V
U3
MVSS
FLT
AK4730
MVDD
R36 15k
C44
R37
57
C40 0.0022u
Q2R
330p
11
0
5V
1
12
C45 +
MVDD
PVDD
MVSS
2
0.1u
14
TP10
TP
TP11
49
C48
0.1u
17
18
JP1
0
BVSS1
LGATE1R
MCKO
MGATE1R
CDTO
HGATE1R
DVSS
HGATE2R
DVDD
MGATE2R
MCLK
LGATE2R
47
TP8
TP
46
TP9
TP
45
TP12
TP
44
TP13
TP
43
TP14
TP
42
TP15
TP
R39
EXT
DIR
19
L2L
L1R
M1R
H1R
H2R
M2R
B
L2R
EXT
TP19 TP16
TP20 TP17
TP21
TP18
TP
TP
TP
TP
TP
TP
BVSS2
MVDD
41
MVSS
40
39
38
TSTL2
TSTM2
37
TSTL1
TSTH2
36
35
34
TSTH1
33
DVSS
32
NC
31
CAD0
DVDD
30
29
SCL
CAD1
28
27
SDA
26
I2C
CSN
25
24
23
21
PORT2
10
9
8
7
6
22
100
LRCK
PDN
LRCK
BICK
R40
EXT
DIR
SDTI
20
TSTM1
100
MCLK
JP2
1
2
3
4
5
M2L
12V
1
+
R38
C47
100u
5V
MCLK
BICK
LRCK
DATA
H2L
48
2
16
4114_LRCK
H1L
50
port3
MCKO2
C
M1L
51
TP
15
B
L1L
C46
13
10u
PVSS
470u
58
MVSS
Q2L
C38
59
MVDD
ADPTLR
+
2
62
61
12V
VP1
VP2
64
63
VP3
65
ADPTLL
66
PROTLL
ADPTHL
67
PROTL
69
68
PROTHL
70
VREFLI
71
CAPL
72
AVSS
VREFLO
74
73
CAPFF2
CAPFF1
76
75
AVDD
78
77
CAPR
VREFRO
PROTLR
VREFRI
1
PROTR
80
79
C36
NC
PROTHR
R30
20k
C49
0.1u
R41
C50
C51
100
1
+
JP3
EXT
DIR
4114_BICK
2
BICK
0.1u
JP4
4114_SDTO
EXT
DIR
C52
100
PDN
1
U4
74HCT157
2
3
5
6
11
10
5V
10
8
6
4
2
uP-I/F
R46
10k
10k
14
13
CSN
CCLK/SCL
CDTI/SDA
SDA_ACK
R47
470
R49
470
R48
470
1
15
SDA_ACK
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
I2C
4
CSN
SDA
SCL
100u
CAD1 CAD0
CSN
7
12V
R43
0
SCL
RP2
9
12
3
2
1
SDA_ACK
CAD1
CAD0
I2C
CAD1
CAD0
I2C
A
5V
47k
A/B
G
3
2
1
A
PORT3
9
7
5
3
1
R45
10k
2
+
DATA
R44
470u
R42
port3
S2
5V
4730_SETTING
I2C
4
5
6
R50
1.8k
Title
U5A
1
2
AK4730
SDA
Size
A2
5V
74LS07
Date:
5
4
3
2
Document Number
Rev
AKD4730-100W
Tuesday, January 25, 2005
1
Sheet
3
2
of
5
5
4
3
2
12V
L2L
H1L
C53
C56
NC
C54
12V
C62
NC
NC
C58
C59
NC
C63
NC
NC
C61
NC
NC
R51
C64
L1L
C55
NC
C57
R54
M1L
NC
NC
C60
D
12V
H2L
12V
M2L
1
12V
12V
R52
NC
R53
D
R55
R56
NC
NC
NC
NC
NC
NC
R61
0
Q1
Q7
Q9
Q8
NC
NC
Q35
NC
NC
VP
R57
0
R62
0
NC
VP
R58
0
Q2
NC
Q33
NC
C65
100n
C71
R66
510
0.02u
CD3
1
2
NC
Q5
NC
NC
C69
0.02u
R63
510
C70
0.02u
C74
CD1
10K
1
D-1
NC
NC
2
D-2
0.1u
0.1u
1
R64
510
0.1u
C73
10K
1
Q6
Q34
NC
100n
0.1u
C
C76
1u
1u
2
NC
2
C75
CD2
2
1
NC
1
C
D-3
D-4
1
Q4
NC
R68
0.02u
CD4
2
Q3
C68
R67
C72
R60
0
C66
C67
R65
510
R59
0
1SMA5923
1SMA5923
2
2
1
NC
NC
Q10
IRFZ24N
C77
0.1u
C78
0.1u
Q11
IRF9Z34N
Q12
IRF9Z34N
Q13
IRFZ24N
C79
1u
C80
1u
C81
0.1u
C82
0.1u
B
B
VRLI
R69
5V
1
51
Q14
IRFZ24N
VRLO
+
C83
0.1u
Q16
IRLR3105
C84
2200u
Q15
IRFZ24N
2
R70
100
R71
R72
Q2L
Q1L
100k
100k
J1
OUTPUT_connector
J2
OUTPUT_connector
R100
51k
51k
C87
1
1
R101
L2
A
1
L3
0.1u
2
1
10u
A
2
10u
C88
C89
0.47u
0.47u
Title
Output_Lch
Size
A3
Date:
5
4
3
2
Document Number
Rev
3
AKD4730-100W
Tuesday, January 25, 2005
Sheet
1
3
of
5
5
4
3
2
12V
12V
12V
L2R
H1R
C98
C101
NC
C99
12V
NC
NC
C103
C109
C104
NC
C108
NC
C100
NC
C106
NC
NC
R74
R77
L1R
NC
C102
C107
M1R
NC
NC
C105
D
12V
H2R
12V
M2R
1
R75
NC
D
R76
R78
R79
NC
NC
NC
NC
NC
NC
R84
0
Q17
Q23
Q25
Q24
NC
NC
Q38
NC
NC
VP
R80
0
R85
0
VP
R81
0
Q18
NC
NC
Q19
Q36
NC
R89
510
CD7
1
C
2
NC
0.1u
0.1u
C118
C119
C114
0.02u
R86
510
C115
0.02u
CD5
10K
1
1
D-5
NC
2
D-6
0.1u
0.1u
1
D-8
1
C113
R91
10K
CD8
2
NC
100n
C112
R90
C117
0.02u
Q22
Q37
NC
NC
C111
100n
C116
0.02u
R83
0
Q21
Q20
NC
NC
C110
R88
510
R82
0
C120
CD6
2
2
NC
2
1
NC
C
1
C121
D-7
1SMA5923
1SMA5923
2
1
1u
1u
2
R87
510
NC
NC
Q26
C122
0.1u
C123
0.1u
C124
1u
IRFZ24N
Q27
Q28
IRF9Z34N
IRF9Z34N
Q29
C125
1u
IRFZ24N
C126
0.1u
C127
0.1u
B
B
VRRI
R92
5V
1
51
Q30
IRFZ24N
VRRO
+
C128
0.1u
Q32
IRLR3105
C129
2200u
Q31
IRFZ24N
2
R93
100
R94
R95
Q2R
Q1R
100k
100k
J6
OUTPUT_connector
J7
OUTPUT_connector
R102
51k
51k
A
C132
1
1
R103
L4
1
A
L5
0.1u
2
1
10u
2
10u
C133
C134
0.47u
0.47u
Title
Output_Rch
Size
A3
Date:
5
4
3
2
Document Number
Rev
3
AKD4730-100W
Tuesday, January 25, 2005
Sheet
1
4
of
5
5
4
1
D
1
D
2
J4
+12V_connector
1
J3
V+_connector
3
VP: max 48V
12V
R73
1
1
1
+
C90
100u
C91
0.1u
C
2
C97
0.1u
2
C92
47u
2
1
1
+
C96
0.1u
2
C95
470u
2
+
C94
0.1u
2
C93
2200u
1
1
+
2
1
0
C
5V
2
1
U6
NJM78M05A
I G O 3
2
VP
J5
GND_connector
B
B
1
A
A
Title
Size
A4
Date:
5
4
3
2
Document Number
Power Supplies
Rev
3
AKD4730-100W
Tuesday, January 25, 2005
Sheet
5
1
of
5