OKI MSM7630

E2F0005-29-12
¡ Semiconductor
MSM7630
¡ Semiconductor
This version: Jan.
1999
MSM7630
Previous version: Mar. 1998
Universal Speech Processor
GENERAL DESCRIPTION
The MSM7630 is a speech processor LSI device with internal D/A converter. It is optimized for
speech output applications such as text-to-speech conversion.
FEATURES
• Parallel and serial interfaces
• Single 3.3V power supply
• 5V interface available
• Internal 16-bit x 16-bit to 32-bit multiplier (2-clock data throughput)
• 26 VAX MIPS performance at 40 MHz operation (when using ordinary ROM/SRAM)
• Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK)(Product name: MSM7630GS-BK)
1/95
¡ Semiconductor
MSM7630
CLK
MCLKA
PLL
TSTM
EXINT
TST
DAC
TMR
RST
STBY
SCLK
TXD
RXD
DSR
DTR
CTS
RTS
DRAMC
RAS
CAS0,1
WE
PIO
PD7-0
PSTB
PACK
PCS
PIOA
POBF
PIBF
MPY
REG
DAO1
SG
CPU
A23-0
D31-16
WR0,1
RD
ROM
SRAM
Local Bus
BLOCK DIAGRAM
TMR
TMR
SIO
2/95
¡ Semiconductor
MSM7630
,
A19
TSTM2
TSTM1
VDD
EXTINT
A23
A22
A21
A20
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DAO1
TEST0
SG
VDD
VDD
GND
GND
XO
CLK
CLKA
UPORT
PIN CONFIGURATION (TOP VIEW)
D23
D22
D21
VDD
D20
D19
D18
D17
D16
PD7
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
GND
A17
A16
A15
A14
A13
A12
VDD
A11
A10
A9
A8
A7
A6
A5
GND
A4
A3
A2
A1
A0
CAS1
CAS0
VDD
WE
SCLK
RXD
RAS
TXD
DTR
AS
ROM
VDD
SRAM
D31
D30
D29
D28
D27
GND
D26
D25
D24
80
79
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
RST
RD
STBY
WR1
WR0
PD6
GND
PD5
PD4
PD3
PD2
PD1
PD0
PIOA
VDD
PCS
PACK
PIBF
PSTB
POBF
DSR
RTS
GND
CTS
GND
100-Pin Plastic QFP
3/95
¡ Semiconductor
MSM7630
PIN DESCRIPTIONS
Symbol
Type
D31-16
I/O
16-bit data bus. 8-bit devices are accessed through D31-24.
A23-0
O
24-bit address bus. DRAM addresses are output from A13-0.
ROM
O
SRAM
O
RD
O
WR0,1
O
RAS
O
CAS0,1
O
WE
O
Write enable. WE is active during writes to DRAM space as the DRAM write signal.
AS
O
Address strobe.
Description
ROM select signal. ROM indicates that ROM space is assigned to the specified address.
It is used as a chip select signal.
SRAM select signal. SRAM indicates that SRAM space is assigned to the specified address.
It is used as a chip select signal.
Read signal. RD is active during both 8-bit and 16-bit reads.
Write signals. WR0 corresponds to writes from D31-24, and WR1 corresponds to
writes from D23-16.
Row address strobe. RAS is active during both 8-bit and 16-bit reads.
Column address strobe. CAS0 corresponds to accesses from D31-24, and CAS1
corresponds to accesses from D23-16.
TXD
O
Serial data output.
RXD
I
Serial data input.
DTR
O
Control signal indicating SIO can transmit and receive.
DSR
I
Input signal indicating that modem is in operable state.
RTS
O
SIO transmit request signal.
CTS
I
Input signal indicating that modem can transmit.
SCLK
O
Synchronous transfer clock output.
PD7-0
I/O
Parallel port data input/output.
PACK
I
Parallel port read signal. Set high for Centronics interface.
PSTB
I
Parallel port write signal. Strobe signal for Centronics interface.
PCS
I
Parallel port chip select signal.
PIOA
I
POBF
3-state
PIBF
3-state
UPORT
O
TEST0
I
Connects with SG.
DAO1
O
D/A converter output.
SG
I
Signal ground. Connects with TEST0.
CLK
I
Clock input signal.
Parallel port address signal. Selects data or status during an access.
Output port buffer full. Indicates that data has been set in the output buffer.
Input port buffer full. Indicates that there is data in the input buffer.
Busy output signal for Centronics interface.
General flag output signal.
XO
O
Clock signal. Inverse of CLK.
CLKA
O
Internal clock signal.
RST
I
Reset input.
STBY
I
Standby signal. STBY suspends operation and places the MSM7630 in a standby state.
EXTINT
I
External interrupt signal.
TSTM2,1
I
Test mode select input signal.
4/95
¡ Semiconductor
MSM7630
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Ta = 25°C
Rating
Unit
–0.3 to +4.5
V
Power Supply Voltage
VDD
Input Voltage
VIN
Ta = 25°C
–0.3 to +5.5
V
Storage Temperature
TSTG
—
–55 to +125
°C
Unit
(excluding TEST0)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Conditon
Range
Power Supply Voltage
VDD
—
3.0 to 3.6
V
Operating Temperature
Top
—
–40 to +85
°C
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 3.0 to 3.6 V, Ta = –40 to +85°C)
VIH
Condition
Excluding CLK
Min.
2.2
Typ.
—
Max.
—
Unit
"H" Input Voltage
"L" Input Voltage
VIL
Excluding CLK
—
—
0.8
V
"H" Input Voltage
VIH
CLK
0.8 ¥ VDD
—
—
V
"L" Input Voltage
VIL
CLK
—
—
0.2 ¥ VDD
V
"H" Output Voltage
VOH
IOH = –4 mA
2.4
—
—
V
"L" Output Voltage
VOL
IOL = 4 mA
—
—
0.4
V
Input Leakage Current
ILI
0 £ VIN £ VDD
–10
—
+10
mA
Output Leakage Current
ILO
0 £ VOUT £ VDD
–10
—
+10
mA
—
—
120
mA
—
1.5
mA
Parameter
Symbol
VDD = 3.6 V,
V
Dynamic Supply Current
IDO
Static Supply Current
IDS
—
—
D/A Output Relative Accuracy
VDAE
No load
—
—
10
mV
D/A Output Impedance
RDA
—
12
20
28
kW
fOPE = 20 MHz
5/95
¡ Semiconductor
MSM7630
AC Characteristics
(VDD = 3.0 to 3.6 V, TOPE = –40 to +85°C)
Condition
—
Min.
25
Typ.
—
Max.
50
Unit
tOSC
tW_CLKL
—
13
—
—
ns
tW_CLKH
—
8
—
—
ns
Operating Period
tCYC
—
25
—
50
ns
CLKA Delay Time
tCLK
—
—
—
12
ns
Parameter
Source Oscillation Period
Input Clock Low-Level
Symbol
ns
Minimum Width
Input Clock High-Level
Minimum Width
tXO
—
—
—
7
ns
tW_RST
—
1024
—
—
tCYC
A Delay Time
tA
—
—
—
22
ns
D Setup Time
tS_D
—
2
—
—
ns
D Hold Time
tH_D
—
6
—
—
ns
D Delay Time
tD
—
—
—
25
ns
RD Delay Time
tRD
—
—
—
20
ns
tWR
Falling
—
—
22
ns
Rising
—
—
22 + 0.5 tCYC
ns
—
—
20
ns
2
—
—
ns
XO Delay Time
Required RST Time
WR Delay Time
UPORT Delay Time
tUPORT
—
EXINT Setup Time
tS_EXINT
—
6/95
¡ Semiconductor
MSM7630
ROM, SRAM Access
(VDD = 3.0 to 3.6 V, TOPE = –40 to +85°C)
Parameter
RD Pulse Width
Symbol
tW_RD
Condition
ROM, SRAM
Min.
2
Typ.
—
Max.
11
Unit
1.5
—
10.5
tCYC
—
1
—
tCYC
—
2
—
tCYC
—
1
—
tCYC
—
1
—
tCYC
tCYC
3t to 12t Access
WR Pulse Width
tW_WR
SRAM
3t to 12t Access
A to RD Time
tW_ARD
ROM, SRAM
3t, 4t Access
ROM, SRAM
5t to 12t Access
A to WR Time
tW_AWR
SRAM
3t to 12t Access
WR to SRAM Time
tW_WRSRAM
SRAM
3t to 12t Access
ROM Delay Time
tROM
—
—
—
20 + 0.5 tCYC
ns
SRAM Delay Time
tSRAM
—
—
—
20 + 0.5 tCYC
ns
tW_ROM
ROM
3
—
12
tCYC
3
—
12
tCYC
—
0
—
tCYC
—
1
—
tCYC
ROM Pulse Width
3t to 12t Access
SRAM Pulse Width
tW_SRAM
SRAM
3t to 12t Access
WR to D Time
tW_WRD
SRAM
3t Access
SRAM
4t to 12t Access
7/95
¡ Semiconductor
MSM7630
DRAM Access
(VDD = 3.0 to 3.6 V, TOPE = –40 to +85°C)
Parameter
Symbol
Min.
—
Typ.
—
Max.
18
Unit
3
—
Note 1
tCYC
RAS Delay Time
tRAS
Condition
—
RAS Pulse Width
tW_RAS
—
A to RAS Time
tW_ARAS
—
1
—
—
tCYC
CAS Delay Time
tCAS
2nt access falling
—
—
18 + 0.5 tCYC
ns
Normal
—
—
18
ns
Normal
1.5
—
2
tCYC
ns
edge
CAS Pulse Width
tW_CAS
Refresh
4
—
5
tCYC
tW_ACAS
—
0.5
—
1
ns
RAS to CAS Time
tW_RASCAS
—
1.5
—
2
tCYC
WE to CAS Time
tW_WECAS
—
1.5
—
2
tCYC
A to CAS Time
WE Delay Time
tWE
—
—
—
20
ns
WE Pulse Width
tW_WE
—
3
—
Note 1
tCYC
A to WE Time
tW_AWE
—
—
1
—
tCYC
Required Precharge Time
tW_PREC
—
1
—
Note 2
tCYC
tW_CASRAS
—
—
1
—
tCYC
tW_EDO
Hyper Mode
—
—
1
tCYC
CAS to RAS Time
CAS to D Time
General Device Access
(VDD = 3.0 to 3.6 V, TOPE = –40 to +85°C)
Parameter
AS Delay Time
Symbol
tAS
Condition
—
Min.
—
Typ.
—
Max.
18
Unit
ns
8/95
¡ Semiconductor
MSM7630
When DS bit = 0
(VDD = 3.0 to 3.6 V, TOPE = –40 to +85°C)
Parameter
AS Pulse Width
Symbol
tW_AS
Condition
4t to 7t Access
Min.
2
Typ.
—
Max.
5
Unit
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
2
—
5
tCYC
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
2
—
5
tCYC
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
—
0
—
tCYC
—
0
—
tCYC
tCYC
(X bit = 0)
8t to 14t Access
(X bit = 1)
A to AS Time
tW_AAS
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
RD Pulse Width
tW_RD
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
A to RD Time
tW_ARD
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
WR Pulse Width
tW_WR
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
A to WR Time
tW_AWR
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
D to WR Time
tW_DWR
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
9/95
¡ Semiconductor
MSM7630
When DS bit = 1
(VDD = 3.0 to 3.6 V, TOPE = –40 to +85°C)
Parameter
AS Pulse Width
Symbol
tW_AS
Condition
4t to 7t Access
Min.
2
Typ.
—
Max.
5
Unit
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
2
—
5
tCYC
6
—
12
tCYC
—
1
—
tCYC
—
1
—
tCYC
2
—
5
tCYC
6
—
12
tCYC
—
2
—
tCYC
—
3
—
tCYC
—
1
—
tCYC
—
2
—
tCYC
tCYC
(X bit = 0)
Note 3
8t to 14t Access
(X bit = 1)
A to AS Time
tW_AAS
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
RD Pulse Width
tW_RD
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
A to RD Time
tW_ARD
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
WR Pulse Width
tW_WR
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
A to WR Time
tW_AWR
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
D to WR Time
tW_DWR
4t to 7t Access
(X bit = 0)
8t to 14t Access
(X bit = 1)
10/95
¡ Semiconductor
MSM7630
Serial Interface
(VDD = 3.0 to 3.6 V, TOPE = –40 to +85°C)
Min.
—
Typ.
—
Max.
20
Unit
tRTS
Condition
—
tW_RXD
—
1/bps
—
—
s
RXD Setup Time
tS_RXD
—
0.5/bps
—
—
s
RXD Hold Time
tH_RXD
—
0.5/bps
—
—
s
CTS Setup Time
tS_CTS
—
0
—
—
ns
CTS Hold Time
tH_CTS
—
0
—
—
ns
TXD Delay Time
tTXD
—
—
—
20
ns
TXD Pulse Width
tW_TXD
—
1/bps
—
—
s
DTR Delay Time
tDTR
—
—
—
20
ns
SCLK Delay Time
tSCLK
—
—
—
20
ns
SCLK Pulse Width
tW_SCLK
—
1/bps
—
—
s
Symbol
Min.
—
Typ.
—
Max.
22
Unit
Parameter
RTS Delay Time
Required RXD Time
Symbol
ns
Parallel Interface
(VDD = 3.0 to 3.6 V, TOPE = –40 to +85°C)
Parameter
PACK to PD Delay Time
tPACK
Condition
—
PACK to PD Hi Z Delay Time
tPRDZ
—
—
—
22
ns
PCS Setup Time for PSTB/PACK
tS_PCS
—
0
—
—
ns
PCS Hold Time for PSTB/PACK
tH_PCS
—
0
—
—
ns
ns
PIOA Setup Time for PSTB/PACK
tS_PIOA
—
0
—
—
ns
PIOA Hold Time for PSTB/PACK
tH_PIOA
—
3
—
—
ns
Required PACK Time
tW_PACK
—
30 + tCYC
—
—
ns
Required PSTB Time
tW_PSTB
—
30 + 2 tCYC
—
—
ns
tS_PD
—
–tCYC
—
—
ns
tH_PD
—
8
—
—
ns
PD Setup Time for PSTB
PD Hold Time for PSTB
Note 1
Note 2
Note 3
Note 4
According to DRAM configuration
By the DRAM access timing
In the case of writing, increased by 1 clock when X bit = 0 and by 2 clocks when X bit
= 1.
Flash memory access timing is the same with the SRAM timing.
11/95
¡ Semiconductor
MSM7630
TIMING DIAGRAM
Clock And Reset
tW_CLKL tW_CLKH
tOSC
CLK
tXO
XO
tCYC
tCLKA
CLKA
tW_RST
RST
12/95
¡ Semiconductor
MSM7630
ROM Read
CLK
tCLKA
CLKA
tA
tA
A
tS_D
tH_D
D
tW_ARD
tW_ROM
tROM
tROM
ROM
tRD
tW_RD
tRD
RD
3tt/4tt Access
CLK
tCLKA
CLKA
tA
tA
A
tS_D
tH_D
D
tW_ARD
tW_ROM
tROM
tROM
ROM
tRD
tW_RD
tRD
RD
5tt/6tt/8tt/10tt/12tt Access
13/95
¡ Semiconductor
MSM7630
SRAM Read
CLK
tCLKA
CLKA
tA
tA
A
tS_D
tH_D
D
tW_ARD
tW_SRAM
tSRAM
tSRAM
SRAM
tRD
tRD
tW_RD
RD
3tt/4tt Access
CLK
tCLKA
CLKA
tA
tA
A
tS_D
tH_D
D
tW_ARD
tW_SRAM
tSRAM
tSRAM
SRAM
tRD
tW_RD
tRD
RD
5tt/6tt /8tt /10tt/12tt Access
14/95
¡ Semiconductor
MSM7630
SRAM Write
CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AWR
tW_SRAM
tSRAM
tSRAM
SRAM
tWR
tW_WRSRAM
tWR
WR
tW_WR
3tt Access
CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AWR
tW_WRD
tW_SRAM
tSRAM
tSRAM
SRAM
tWR
WR
tWR
tW_WR
tW_WRSRAM
4tt/5tt/6tt/8tt/10tt/12tt Access
15/95
¡ Semiconductor
MSM7630
DRAM Read
tOSC
CLK
CLKA
tA
tA
A
row address
column address
tS_D
tH_D
D
tW_ARAS
tW_RAS
tW_PREC
tRAS
tRAS
RAS
tCAS
CAS
tW_ACAS
tW_CAS
tCAS
tW_RASCAS
WE
2ntt Access (Fast Page Mode)
tOSC
CLK
CLKA
tA
A
tA
row address
column address
tS_D
column address
tH_D
tH_D
tS_D
D
tW_ARAS
tW_RAS
tW_PREC
tRAS
tRAS
RAS
CAS
tW_ACAS
tW_CAS
tCAS
tCAS
tCAS
tW_RASCAS
WE
2ntt Access (Fast Page Mode)
16/95
¡ Semiconductor
MSM7630
tOSC
CLK
CLKA
tA
tA
row address
A
column address
tS_D
tH_D
D
tW_ARAS
tW_RAS
tW_PREC
tRAS
tRAS
RAS
tW_ACAS
tW_CAS
tCAS
CAS
tCAS
tW_RASCAS
WE
3ntt Access (Fast Page Mode)
tOSC
CLK
CLKA
tA
tA
row address
A
column address
tS_D
column address
tS_D
tH_D
tH_D
D
tW_ARAS
tW_RAS
tW_PREC
tRAS
tRAS
RAS
CAS
tW_ACAS
tCAS
tW_CAS
tW_CAS
tCAS
tCAS
tCAS
tW_RASCAS
WE
3ntt Access (Fast Page Mode)
17/95
¡ Semiconductor
MSM7630
tOSC
CLK
CLKA
tA
tA
tA
row address
A
column address
tS_D
tH_D
D
tW_PREC
tW_ARAS
tW_RAS
tRAS
tRAS
tW_ACAS
RAS
tW_EDO
tW_CAS
tCAS
CAS
tCAS
tW_RASCAS
WE
3ntt Access (Hyperpage Mode)
tOSC
CLK
CLKA
tA
tA
tA
row address
A
tA
column address
column address
tH_D
tS_D
D
tW_PREC
tW_ARAS
tS_D
tH_D
tW_RAS
tRAS
tRAS
RAS
CAS
tW_ACAS
tCAS
tW_CAS
tW_CAS
tCAS
tCAS
tW_EDO
tCAS
tW_RASCAS
WE
3ntt Access (Hyperpage Mode)
18/95
¡ Semiconductor
MSM7630
DRAM Write
tOSC
CLK
CLKA
tA
tA
row address
A
column address
tD
tD
D
tW_ARAS
tW_RAS
tW_PREC
tRAS
tRAS
RAS
tW_RASCAS
CAS
tW_AWE
tW_ACAS
tW_CAS
tWE
WE
tCAS
tCAS
tW_WECAS
tW_WE
tWE
2ntt Access (Fast Page Mode)
tOSC
CLK
CLKA
tA
tA
row address
A
column address
tD
column address
tD
tD
D
tW_ARAS
tW_RAS
tW_PREC
tRAS
RAS
tW_RASCAS
CAS
WE
tW_AWE
tW_WECAS
tWE
tW_CAS
tW_ACAS
tCAS
tCAS
tW_WE
tW_CAS
tCAS
tWE
2ntt Access (Fast Page Mode)
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¡ Semiconductor
MSM7630
tOSC
CLK
CLKA
tA
A
tA
row address
column address
tD
D
tD
tW_ARAS
tW_RAS
tW_PREC
tRAS
RAS
tW_AWE
CAS
tRAS
tW_ACAS
tW_RASCAS
tW_WECAS
tW_CAS
tCAS
tCAS
tWE
tWE
WE
3ntt Access (Fast Page Mode/Hyperpage Mode)
tOSC
CLK
CLKA
tA
row address
A
D
column address
column address
tD
tD
tW_ARAS
tD
tW_PREC
tW_RAS
tRAS
tRAS
RAS
CAS
WE
tW_AWE
tW_ACAS
tW_RASCAS
tW_CAS
tWE
tW_CAS
tCAS
tW_CAS
tCAS
tCAS
tW_WE
tCAS
tWE
3ntt Access (Fast Page Mode/Hyperpage Mode)
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¡ Semiconductor
MSM7630
DRAM Refresh
tOSC
CLK
CLKA
A
ignore
ignore
D
tW_RAS
tRAS
RAS
tRAS
tW_CASRAS
tCAS
tW_CAS
tCAS
CAS
WE
2ntt CAS-Before-RAS Refresh
tOSC
CLK
CLKA
A
ignore
ignore
D
tW_RAS
tRAS
RAS
tRAS
tW_CASRAS
tCAS
tW_CAS
tCAS
CAS
WE
3ntt CAS-Before-RAS Refresh
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MSM7630
tOSC
CLK
CLKA
A
ignore
ignore
D
tW_RAS
tRAS
RAS
tRAS
tW_CASRAS
tCAS
tW_CAS
tCAS
CAS
WE
CAS-Before-RAS Self-Refresh
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MSM7630
General Device Access
CLK
tCLKA
CLKA
tA
tA
A
tS_D
tH_D
D
tW_AAS
tW_AS
tAS
AS
tW_AAS
tAS
tW_ARD
tRD
RD
tW_RD
tRD
Bus Read
CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AAS
tW_AS
tAS
AS
WR
tW_AAS
tAS
tW_AWR
tWR
tW_WR
tWR
Bus Write (When DS bit in the SCR register is "0")
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MSM7630
CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AAS
tW_AAS
tW_AS
tAS
AS
tAS
tW_AWR
tW_DWR
WR
tWR
tWR
tW_WR
Bus Write (When DS bit is "1" and X bit is "0" in the SCR register)
CLK
tCLKA
CLKA
tA
tA
A
tD
tD
D
tW_AAS
tW_AS
tW_AAS
tAS
AS
WR
tAS
tW_AWR
tWR
tW_WR
tWR
tW_DWR
Bus Write (When DS bit is "1" and X bit is "1" in the SCR register)
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MSM7630
Parallel Interface
tOSC
CLK
tCLKA
CLKA
tS_PCS
tH_PCS
tS_PCS
tH_PCS
tS_PCS
tH_PCS
tS_PIOA
tH_PIOA
tS_PIOA
tH_PIOA
tS_PIOA
tH_PIOA
PCS
PIOA
tW_PACK
tW_PACK
PACK
tW_PSTB
PSTB
tPACK
tPRDZ
tS_PD
tH_PD
PD
tPACK
tPRDZ
tPACK
tPRDZ
PIBF
POBF
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CLK
tCLKA
CLKA
tS_RXD
RXD
tH_RXD
tS_RXD
Start_bit (= 0)
bit 0
tW_RXD
tRTS
tH_RXD
tS_RXD
bit 1
bit 6
tH_RXD
bit 7
tW_RXD
tW_RXD
tS_RXD
tH_RXD
¡ Semiconductor
Serial Interface
tOSC
Stop_bit (= 1)
tW_RXD
tRTS
RTS
tOSC
CLK
tCLKA
CLKA
tTXD
Start_bit (= 0)
TXD
tH_CTS
tW_TXD
tTXD
bit 0
tW_TXD
tTXD
bit 1
bit 6
bit 7
tW_TXD
tTXD
Stop_bit (= 1)
tW_TXD
tTXD
MSM7630
26/95
CTS
tS_CTS
tTXD
¡ Semiconductor
MSM7630
CLK
tCLKA
CLKA
tSCLK
tW_SCLK
tSCLK
tW_SCLK
tSCLK
SCLK
Synchronous Transfer Output
General Port Output
CLK
tCLKA
CLKA
tUPORT
tUPORT
UPORT
General Port Output
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MSM7630
Standby Operation
CLK
XO
CLKA
tW_RST
RST*
tRSTSTBY_H
tRSTSTBY_S
STBY
CPU Operation
tSTBYCLKA
Operating
Suspend
Process
Suspend
Resume Process
Operating
RAS
CAS
Maintain the pin level on the STBY signal until the CPU has completed its suspend process and clock
signal CLKA has stopped.
After the STBY signal is released, the CPU will not resume until oscillation has stabilized (1024 tCYC).
* The RST signal is not necessary for self-refresh DRAM.
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MSM7630
Interrupt Process
CLK
XO
CLKA
EXTINT
The external interrupt signal EXTINT requests an interrupt to the CPU. The pin level on EXTINT
must be maintained until the CPU accepts the interrupt. Also, be sure to clear the interrupt source
within the interrupt routine.
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MSM7630
FUNCTIONAL DESCRIPTION
CPU Core
1. Features
The SCP (Speech Control Processor) uses a CPU core with an Oki-original 32-bit RISC architecture.
2. Register Configuration
The CPU core registers are configured as 32 words for general registers, 7 words for privileged
registers, and 1 word for a special register.
General Registers
Privileged Registers
%r0 (link)
%PSR
%r1 (pre-PC)
%VBA
%r2 (pre-nPC)
%prPSR
%r3 (long-immed.)
%IRR
%r4
%BPA
%r5
%PC
%nPC
Special Register
%NOP
%r30
%r31
2.1 General Registers
The general registers are a set of 32 registers with 32-bit width. Of these registers %r0 to %r3 can be
used as general registers, but they do have special functions pre-assigned by the system. Registers
%r4 to %r31 can be used freely. Contents are undefined after reset.
bit 31
0
GR
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¡ Semiconductor
%r0:
MSM7630
%r1:
Link register (stores subroutine return address). Also stores %PC+4 during bl instruction
execution.
Stores value of %PC when an exception, interrupt, or trap is accepted.
%r2:
Stores value of %nPC when an exception, interrupt, or trap is accepted.
%r3:
Stores the immediate value of SETLI (Set Long Immediate) instructions.
2.2 Privileged Registers
Reads are allowed at any processor level (Processor Level: 0 = user mode, 1 or above = supervisor
mode), but write accesses are allowed only when the processor level is supervisor mode. The
privileged registers are configured as 7 words, and are used primarily for processor control. If the
processor attempts a write access to a privileged register while in user mode, then the instruction will
not be executed and a privileged instruction exception will be issued.
2.2.1 PSR (Processor Status Register)
This register sets and displays the state of the processor.
bit 31
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
VER
M M
I I N
E E
0 0 0 0 0 F F 0 0 0 0 0 V C N Z 0 C C O 0 0 B M
U U
P L P
P
32 16
0
PL
• bit[31:28] VER: Version (read-only)
Indicates the CPU core version. Currently fixed to "3".
• bit[22] MFU32 (read-only)
Indicates whether the 32-bit multiplier unit is present ("1") or not ("0"). This is "0" for the MSM7630.
• bit[21] MFU16 (read-only)
Indicates whether the 16-bit multiplier unit is present ("1") or not ("0"). This is "1" for the MSM7630.
• bit[15] V: Overflow (read-only)
Indicates that execution of an addition or subtraction instruction resulted in an arithmetic
overflow.
• bit[14] C: Carry (read-only)
Indicates that execution of an addition or subtraction instruction resulted in an arithmetic carry or
borrow.
• bit[13] N: Negative (read-only)
Indicates that execution of an addition or subtraction instruction resulted in a negative value
(bit[31] is "1").
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MSM7630
• bit[12] Z: Zero (read-only)
Indicates that execution of an addition or subtraction instruction resulted in a zero value (bit[31:0]
are all "0").
• bit[10] ICP: Instruction Cache Purge (read/write)
Invalidates all instruction cache entries. Writing "1" to this bit purges the contents of the instruction
cache. After this process (after one cycle) this bit is automatically cleared to "0" by hardware. The
instruction cache is purged during reset.
• bit[9] ICL: Instruction Cache Lock (read/write)
Freezes all instruction cache entries. After "1" is written to this bit, instruction cache contents are
frozen and then instruction execution continues. This bit will be "1" after reset.
• bit[8] NOP: Non-Operation (read-only)
When set to "1", forces the next instruction to a NOP regardless of the instruction. There is no way
to directly set this bit to "1". This bit will be "0" after reset.
• bit [5] EBP: Breakpoint Trap Enable (read/write)
Enables breaks. If this bit is set to "1", then a trap will occur when the value of the instruction
execution address (%PC) equals the value of the breakpoint address (%BPA). The instruction that
generated the break will not be executed. This bit will be "0" after reset.
• bit[4] EM: Master Enable (read/write)
Disables all exceptions, interrupts, and traps. This bit automatically becomes "0" at the point when
the processor accepts an exception, interrupt, or trap. While this bit is "0", further exceptions,
interrupts or traps will not be accepted, with instruction execution continuing in the normal
instruction sequence. An instruction must be used to return this bit to "1". It will be "0" after reset.
• bit[3:0] PL: Processor Level (read/write)
Sets and provides the processor’s instruction execution level. Processor levels are 0-15. An external
interrupt will be accepted if its level has a higher priority than the processor level at that time.
External interrupt levels are 1-16, so when PL is 0 all external interrupts will be accepted, and when
PL is 1 external interrupts of level 2 and above will be accepted. When an external interrupt is
accepted, the processor level will become the same as the external interrupt level. For example, if
PL is 5 and a level 7 external interrupt is accepted, then PL will transition to 7 at that point. When
PL is restored to its previous state, its saved value in %prPSR will be restored to %PSR.
Alternatively PL can be set to its previous value explicitly by an instruction in the interrupt process
routine. However, %PSR is a privileged register, so writes are only permitted in supervisor mode.
PL will be set to 15 after reset.
32/95
¡ Semiconductor
MSM7630
2.2.2 VBA: Vector Base Address (read/write)
This read/write register sets the leading address of the dispatch table (vector table) to exception,
interrupt, and trap process routines.
bit 31
12 11
VBA
0
0 0 0 0 0 0 0 0 0 0 0 0
The dispatch table is 256 entries of 4K bytes size, with 16 bytes (4 instructions) save for each entry’s
dispatch routine. Entry points are generated by an OR operation with this register, so they are set
at 4K-byte boundaries. As a result, only the upper 20 bits of an argument will be written to the VBA
register (the lower 12 bits will be ignored).
Entry_point = VBA[31:12] ÍÍ(vector_number << 4)
This register is undefined after reset.
2.2.3 prPSR: Pre-Processor Status Register (read/write)
This read/write register saves the value of %PSR at the time an exception, interrupt, or trap is
accepted. In order to accept overlapping exceptions, interrupts, and traps, the value of %prPSR must
be pushed on a stack and then EM of %PSR must be set to "1".
bit 31
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
VER
p
M M
p p p p
I
F
F
0 0 0 0 0
0 0 0 0 0
0 C
U U
V C N Z
P
32 16
p
I
C
L
p
p
N
E p
O 0 0 B E
P
P M
0
pPL
The upper 16 bits of %prPSR are always identical to %PSR. Refer to the descriptions of the same bit
positions in %PSR for an explanation of %prPSR bits.
2.2.4 IRR: Interrupt Request Register (read-only)
This register indicates whether there is an interrupt request at each of the 16 levels of external
interrupts. It is read-only, and shows interrupt requests regardless of PL (processor level). The IRR
value will continue until an interrupt source is released.
bit 31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I I I I I I
N
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M R R R R R R
Q Q Q Q Q Q
I 15 14 13 12 11 10
I
R
Q
9
I
R
Q
8
I
R
Q
7
I
R
Q
6
I
R
Q
5
I
R
Q
4
I
R
Q
3
I
R
Q
2
I
R
Q
1
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¡ Semiconductor
MSM7630
The MSM7630 uses only 6 interrupts of the 16 interrupt levels.
bit 31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 0
Q
11
I
I
I
I
R 0 R 0 R 0 R 0 0
Q
Q
Q
Q
9
7
5
3
2.2.5 BPA: Breakpoint Address (read/write)
This read/write register sets and shows the instruction address (byte address) where a breakpoint
trap occurred. The lowest 2 bits will always be "0". When EBP of %PSR is "1", a trap will be generated
immediately before execution of the instruction at the breakpoint set by this register. This register
will be undefined after reset.
bit 31
2 1 0
BPA
0 0
2.2.6 PC: Program Counter (read-only)
This read-only register provides the instruction address (byte address) in the execution phase. Its
lowest 2 bits will always be "0".
bit 31
2 1 0
PC
0 0
2.2.7 nPC: Next Program Counter (read-only)
This read-only register provides the instruction address (byte address) in the instruction decode
phase. Its lowest 2 bits will always be "0".
bit 31
2 1 0
nPC
0 0
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¡ Semiconductor
MSM7630
2.3 Special Registers
These are not privileged registers, but they are special registers used for specific functions.
2.3.1 NOP: Non-Operation (read/write)
When this register is specified as a destination register, execution results will not be stored anywhere.
When specified as a source register, it will read as an undefined value.
bit 31
0
NOP
3. Data Formats
There are two data format types: one for internal processor core calculations and one for memory
accesses.
3.1 Internal Data Format
The CPU core handles all data as 32 bits (word format). Therefore, when the format of data stored
in memory is byte (8 bits) or half-word (16 bits) it must be used internally as 32-bit data through a
signed load instruction or unsigned load instruction. Similarly when internal core processing results
are stored to memory, a store instruction corresponding to the data format in memory must be
executed. Also, bit addresses specified for bit test instructions and bit manipulation instructions are
shown in the diagram below.
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
35/95
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MSM7630
3.2 Memory Data Format
The following memory data formats are supported: byte (8 bits), half-word (16 bits), and word (32
bits). Memory addresses are always byte addresses regardless of data format. However, half-word
accesses must be on 16-bit boundaries (least significant bit is "0"), and word accesses must be on 32bit boundaries (least significant 2 bits are "00"). If a load or store instruction execution attempts a
memory access that violates these boundaries, then a data address invalid exception will occur.
Memory addressing is big-endian. The diagrams below show memory data formats for byte data
access, half-word data access, and word data access.
Byte Data Access
bit 31
24 23
16 15
8 7
0
byte
byte
byte
byte
n
n+1
n+2
n+3
Address
Half-Word Data Access
bit 31
Address
16 15
0
half word
half word
n
n+1
Word Data Access
bit 31
0
word
Address
n
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¡ Semiconductor
MSM7630
3.3 Memory Addressing Modes
Memory addresses are byte addresses, so memory addressing is performed with three types of load
instructions and two types of store instructions. Swap instructions have the same memory
addressing as store instructions.
3.3.1 Load Instruction Addressing
1. Base + Index
The effective address (EA) is obtained by adding the values of any two general registers %r0-31
specified.
EA = [reg_S1 + reg_S2]
2. Base + Displacement
The effective address (EA) is obtained by adding the value of any general register %r0-31 specified
and a displacement given by the instruction’s immediate value field.
EA = [reg_S1] + offS
3.3.2 Store Instruction Addressing
1. Base + Displacement
The effective address (EA) is obtained by adding the value of any general register %r0-31 specified
and a displacement given by the instruction’s immediate value field.
EA = [reg_S1] + offS
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¡ Semiconductor
MSM7630
4. Instruction Set
All instructions are fixed 32-bit length.
Category
Unconditional branch
Conditional branch
Instruction
b{,x}?
Function
Unconditional branch
bl{,x}?
Unconditional branch to subroutine
bt{,x/t} S1,?
Conditional Branch
bf{,x/t} S1,?
Conditional Branch
jlr {,x} S2,D*
Conditional branch to subroutine
jlrt {,x/t} S1,S2,D*
Conditional branch to subroutine
jlrf {,x/t} S1,S2,D*
Conditional branch to subroutine
rt S2
Return from subroutine
Bit test
btst1 S1,S2/immU,D
Bit test
btst0 S1,S2/immU,D
Bit test
Comparison
cmpeq S1,S2/immS,D
Comparison [=]
cmple S1,S2/immS,D
Comparison [signed: £]
cmplt S1,S2/immS,D
Comparison [signed: <]
cmpls S1,S2/immS,D
Comparison [unsigned: £]
cmpc S1,S2/immS,D
Comparison [unsigned: <]
cmpne S1,S2/immS,D
cmpgt S1,S2/immS,D
Comparison [π]
Comparison [signed: >]
cmpge S1,S2/immS,D
Comparison [signed: ≥]
cmphi S1,S2/immS,D
Comparison [unsigned: >]
cmpnc S1,S2/immS,D
Comparison [unsigned: ≥]
Trap
trap vct
Transfer to trap toutine
Arithmetic/logical operation
add S1,S2/immS9,D
Add
sub S1,S2/immS9,D
Subtract
adc S1,S2/immS9,D
Add with carry
sbc S1,S2/immS9,D
Subtract with carry
Extend
Shift
Bit manipulation
and S1,S2/immS9,D
Logical AND
or S1,S2/immS9,D
Logical OR
xor S1,S2/immS9,D
Exclusive OR
sbr S1,S2/immS12,D
Subtract
extu S1,S2/immU,D
MSB extend
ext S1,S2/immU,D
MSB extend
sl S1,S2/immS,D
Logical shift
rot S1,S2/immS,D
Logical rotate
slr S1,S2/immS,D
Logical shift
sar S1,S2/immS,D
Arithmetic shift
brst S1,S2/immU,D
Set bit to "0"
bset S1,S2/immU,D
Set bit to "1"
bnot S1,S2/immU,D
Invert bit
brst %psr,4/5,%psr
Set bit to "0"
brst %psr,4/5,%psr
Set bit to "1"
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¡ Semiconductor
Category
Register-register move
MSM7630
Instruction
mov S,D
Function
Move
movh S1,D'
Move upper bits
seti imm17S,D
Store immediate value
setih const16,D'
Store immediate value to upper 16 bits
setli const25
Store immediate value left-shifted 7 bits to %r3
sb S2/immS,[S1+offS]
Byte store
shw S2/immS,[S1+offS]
Half-word store
sw S2/immS,[S1+offS]
Word store
Swap
swap S2,[S1+offS]
Swap
Load
lb [S1+offS],D'
Byte load
lhw [S1+offS],D'
Half-word load
lw [S1+offS],D'
Word load
mul0 S1,S2/immS,D'
Signed multiply
mul16 S1,S2/immS,D'
Signed multiply
mul32 S1,S2/immS,D'
Signed multiply
mulu0 S1,S2/immS,D'
Unsigned multiply
mulu16 S1,S2/immS,D'
Unsigned multiply
mulu32 S1,S2/immS,D'
Unsigned multiply
Store immediate value
Store
Multiplication
Multiply instructions need two clocks for execution time.
The MSM7630 can only use the mul0 and mulu0 instructions of the multiplication instructions.
39/95
¡ Semiconductor
MSM7630
5. Exceptions, Traps, and Interrupts
The CPU core of SCP provides error exceptions, traps, external interrupts, and software traps (by
trap instructions). Each type has a corresponding interrupt priority level and instruction dispatch
address.
Source
Vector Branch Address Priority Synchronous/Asynchronous
Number
System reset
(Sense)
0x00000000
0
Asynchronous (level)
CPU reset (INIT)
0
VBA+0x000
1
Asynchronous (edge)
Instruction access exception
1
VBA+0x010
2
Synchronous
Instruction address invalid exception
2
VBA+0x020
3
Synchronous
Reserved instruction exception
3
VBA+0x030
4
Synchronous
Privileged instruction exception
4
VBA+0x040
5
Synchronous
Data address invalid exception
5
VBA+0x050
8
Asynchronous (edge)
Data access exception
6
VBA+0x060
9
Asynchronous (edge)
Reserved
7
VBA+0x070
Breakpoint trap
8
VBA+0x080
6
Synchronous
Reserved
9
VBA+0x090
to 32
to VBA+0x200
External interrupt 1
33
VBA+0x210
25
Asynchronous (level)
External interrupt 2
34
VBA+0x220
24
Asynchronous (level)
External interrupt 3
35
VBA+0x230
23
Asynchronous (level)
External interrupt 4
36
VBA+0x240
22
Asynchronous (level)
External interrupt 5
37
VBA+0x250
21
Asynchronous (level)
External interrupt 6
38
VBA+0x260
20
Asynchronous (level)
External interrupt 7
39
VBA+0x270
19
Asynchronous (level)
External interrupt 8
40
VBA+0x280
18
Asynchronous (level)
External interrupt 9
41
VBA+0x290
17
Asynchronous (level)
External interrupt 10
42
VBA+0x2a0
16
Asynchronous (level)
External interrupt 11
43
VBA+0x2b0
15
Asynchronous (level)
External interrupt 12
44
VBA+0x2c0
14
Asynchronous (level)
External interrupt 13
45
VBA+0x2d0
13
Asynchronous (level)
External interrupt 14
46
VBA+0x2e0
12
Asynchronous (level)
External interrupt 15
47
VBA+0x2f0
11
Asynchronous (level)
External interrupt 16 (NMI)
48
VBA+0x300
10
Asynchronous (edge)
0
VBA+0x000
7
Synchronous
to 255
to VBA+0xff0
TRAP instruction
The system reset vector is at absolute address 0. All others are ORed with VBA as the base address.
Synchronous detection is acceptance of a request within an instruction cycle.
Asynchronous detection is acceptance of a request between instruction cycles or at any point in time
after.
40/95
¡ Semiconductor
MSM7630
5.1 RST: System Reset
A system reset resets all states under all circumstances.
Type: Asynchronous hardware reset after RST pin level detection.
Vector address: Absolute address 0 (0x00000000).
Conditions: Non-maskable (unconditional)
PL after interrupt transition: 15
5.2 IAE: Instruction Access Exception
An instruction access exception is generated when an instruction is fetched from an undefined
memory space. If the instruction is converted to a NOP by delayed instruction control (x-bit
manipulation), then no exception will be generated.
Type: Instruction-synchronous exception caused by memory access error during instruction fetch.
Vector number/address: Vector number = 1 / VBA+0x010
Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit).
Saved address: Address of the instruction that caused the exception.
PL after interrupt transition: 15
5.3 IAIE: Instruction Address Invalid Exception
An instruction address invalid exception is generated when a register indirect branch instruction
attempts an instruction fetch at an address that is not on a word boundary. If the instruction is
converted to a NOP by delayed instruction control (x-bit manipulation), then no exception will be
generated.
Type: Instruction-synchronous exception caused by an illegal JLR or RT instruction.
Vector number/address: Vector number = 2 / VBA+0x020
Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit).
Saved address: Address of the instruction that caused the exception.
PL after interrupt transition: 15
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MSM7630
5.4 PIE: Privileged Instruction Exception
A privileged instruction exception is generated when an action that can only be performed in
supervisor mode attempted in user mode: (a) in user mode a privileged register is specified as a
destination, or (b) in user mode a number 64 or below is specified for a TRAP instruction vector. If
the instruction is converted to a NOP by delayed instruction control (x-bit manipulation), then no
exception will be generated.
Type: Instruction-synchronous exception caused by an illegal privileged instruction.
Vector number/address: Vector number = 4 / VBA+0x040
Conditions: Non-maskable (unconditional). Invalidated by delayed instruction control (x-bit).
Saved address: Address of the instruction that caused the exception.
PL after interrupt transition: 15
5.5 DAIE: Data Address Invalid Exception
A data address invalid exception is generated when a memory access instruction attempts to access
a memory address not on a word boundary.
Type: Asynchronous exception caused by an illegal memory access instruction.
Vector number/address: Vector number = 5 / VBA+0x050
Conditions: EM == 1. However, exception must be maintained until accepted.
Saved address: Address being executed when the exception was accepted.
PL after interrupt transition: 15
5.6 DAE: Data Access Exception
A data access exception is generated when data is accessed in an undefined memory space.
Type: Asynchronous exception caused by a memory access instruction error.
Vector number/address: Vector number = 6 / VBA+0x060
Conditions: EM == 1. However, exception must be maintained until accepted.
Saved address: Address being executed when the exception was accepted.
PL after interrupt transition: 15
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MSM7630
5.7 BPT: Breakpoint Trap
A breakpoint trap is generated when the instruction execution address matches the address pointed
to by the %BPA register. However, the EBP bit in the %PSR register must be enabled. The instruction
at the address that causes the trap will not be executed. The trap will be generated even if the
instruction is converted to a NOP by delayed instruction control (x-bit manipulation).
Type: Instruction-synchronous trap caused by hardware.
Vector number/address: Vector number = 8 / VBA+0x080
Conditions: EM == 1 && EBP == 1. Not invalidated by delayed instruction control (x-bit).
Saved address: Address pointed to by the %BPA register.
PL after interrupt transition: 15
5.8 EINT: External Interrupt 1-15
External interrupts are generated by inputs. However, an external interrupt will be accepted only
when its level has higher priority than the current processor level. When an external interrupt is
accepted, the processor level becomes the same as its level.
Type: Asynchronous interrupt when level on INT1-INT15 pins is detected.
Vector number/address: Vector number = 33-47 / VBA+0x210-0x2f0
Conditions: EM == 1 && PL < external_interrupt_number
Saved address: Address being executed when the interrupt was accepted.
PL after interrupt transition: External interrupt number
The MSM7630 assigns interrupt levels as follows. It does not use other interrupts (including NMI).
Priority
Interrupt Number
User Block/TMR2
Interrupt Source
1
INT11
External pin (EXTINT)
2
INT9
Serial I/O
3
INT7
Parallel I/O
4
INT5
TMR1
5
INT3
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MSM7630
5.9 Return From Interrupt
In order to return from an interrupt process caused by an exception, external interrupt, or software
trap, the pipeline at the time of the interrupt must be regenerated before execution.
There are two types of returns: (1) re-execution of an instruction that was in its execution phase at
the time an exception, external interrupt, or asynchronous trap caused an interrupt, and (2) reexecution of the instruction after the instruction that was in its execution phase at the time a software
trap caused an interrupt. However, if breakpoints are supported by software traps then case (1)
applies.
The return sequence from an interface process is described below.
Also, an rt instruction must not be executed while the EM bit of %PSR is 1 (the state permitting
overlapping interrupts). If an interrupt occurred during the rt instruction in such a case, then the
contents of %PSR would be corrupted.
1. Resume from interrupted instruction
·
·
brst
jlr
%psr, 4, %psr
%r1, %nop
rt
%r2
; EM-bit reset
; delay slot, branch %r1 (old %PC),
; return address not saved
; return to %r2 (old %nPC), %prPSR move to %PSR
2. Return from instruction after interrupt
·
·
add
brst
jlr
rt
%r2, 4, %r1
%psr, 4, %psr
%r2, %nop
%r1
; %r2+4 (old %nPC+4)Æ%r1
; EM-bit reset
; delay slot, branch %r2 (old %nPC), return address not saved
; return to %r1 (old %nPC+4), %prPSR move to %PSR
In this case the pNOP bit of %prPSR must be cleared in advance of rt instruction execution. If the
pNOP bit of %prPSR is set and then the rt instruction is executed, then the instruction at the return
point would not be executed.
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MSM7630
Bus Interface Unit
1. Features
The SCP’s bus interface unit (BIU) manages address space and outputs control signals that enable
optimal memory access. This allows ROM, SRAM, DRAM and other general devices to be accessed.
2. Address Space
The address space that can be directly accessed by load/store instructions is 4 gigabytes. The BIU
manages this address space by dividing it into several.
0x00000000
ROM
256 MB
SRAM
256 MB
DRAM
256 MB
0x0FFFFFFF
0x10000000
0x1FFFFFFF
0x20000000
External
0x2FFFFFFF
0x30000000
Reserved
0x3FFFFFFF
0x40000000
General devices
1 GB
4 GB
0x7FFFFFFF
0x80000000
Reserved
0xBFFFFFFF
0xC0000000
Internal ROM
256 MB
0xCFFFFFFF
Internal
0xD0000000
Internal RAM
256 MB
Registers
512 MB
0xDFFFFFFF
0xE0000000
0xFFFFFFFF
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MSM7630
2.1 ROM Space
ROM space is assigned to 0x00000000-0x0FFFFFFF. When this space is accessed the ROM signal goes
"L".
2.2 SRAM Space
SRAM space is assigned to 0x10000000-0x1FFFFFFF. When this space is accessed the SRAM signal
goes "L".
2.3 DRAM Space
DRAM space is assigned to 0x20000000-0x2FFFFFFF. When this space is accessed the DRAM
controller outputs a signal required for DRAM access.
2.4 General Device Space
General device space is assigned to 0x40000000-0x7FFFFFFF. When this space is accessed the AS
signal goes "L". This space is used to access general devices external to the MSM7630.
2.5 Internal ROM Space
Internal ROM space is assigned to 0xC0000000-0xCFFFFFFF. It is used to access internal ROM.
This space is not used by the MSM7630. Accesses to this space will cause instruction access
exceptions or data access exceptions.
2.6 Internal RAM Space
Internal RAM space is assigned to 0xD0000000-0xDFFFFFFF. It is used to access internal RAM.
This space is not used by the MSM7630. Access to this will cause instruction access exceptions or data
access exceptions.
2.7 Register Space
Register space is assigned to 0xE0000000-0xFFFFFFFF. Within this space, 0xF8000000-0xFFFFFFFF
is assigned for standard I/O and system registers.
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0xF8000000
MSM7630
TMR
0xF8FFFFFF
0xF9000000
0xF9FFFFFF
0xFA000000
SIO
0xFAFFFFFF
0xFB000000
0xFBFFFFFF
0xFC000000
PIO
BSR
0xFF000000
BEA
0xFF000004
ECR
0xFF000008
SCR
0xFF00000C
0xFCFFFFFF
0xFD000000
0xFF000010
0xFDFFFFFF
0xFE000000
0xFF000018
0xFF000014
0xFF00001C
0xFEFFFFFF
0xFF000000
0xFF000020
0xFFFFFFFF
0xFF00003F
DRAMC
0xFF000040
0xFF00005F
System Registers
0xFF000080
Test Circuit
0xFF0000FF
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MSM7630
3. Registers
This is a register group used for bus control.
3.1 BEA: Bus Error Address
This register provides the address at the time a bus error occurred.
bit 31
0
BEA
3.2 BSR: Bus Status Register
This register provides bus status information.
bit 31
19 18 17 16 15 14
C
XSP S 0
P
12 11
ST
8 7 6
PEB
0
4 3 2 1 0
BES
0 0 H R
• bit[18:17] XSP: Sleep (read/write)
When the STBY signal is "L", these bits either stop the clock without CPU intervention (XSP = 00)
or stop the clock after waiting for the CPU suspend process (XSP = 11).
• bit[16] CSP: CPU Sleep (read/write)
This bit indicates whether the CPU core is operating or suspended. Writing "1" will stop the CPU
core’s clock.
• bit[14:12] ST: Status (read-only)
These bits save the status signals when an access by the CPU core causes a bus error.
• bit[11:8] PEB: Parity Error Byte (read-only)
These bits provide the byte position when a parity error occurs.
• bit[6:4] BES: Bus Error Status (read-only)
These bits provide the source of a bus error.
BES = 000
BES = 001
BES = 010
BES = 100
No error
BIU register privilege violation
Parity error
Invalid space access
These bits will be "000" after reset.
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MSM7630
• bit[1] H: Hold (read/write)
This bit sets whether or not bus rights will be passed upon a CPU core bus rights request. This bit
will be "0" after reset.
3.3 ECR: Extra Configuration Register
This register sets bus operation.
bit 31
4 3 2 1 0
11 10 9 8 7 6
O A 0 P
M
X X
BM
A O A D
V V V
• bit[10] OX: Internal ROM (read-only)
This bit indicates whether or not internal ROM will be accessed in 2 clocks.
MSM7630 does not use this bit.
• bit[9] AX: Internal RAM (read-only)
This bit indicates whether or not internal RAM will be accessed in 2 clocks.
MSM7630 does not use this bit.
• bit[7] PM: Parity Mode (read/write)
This bit sets parity.
PM = 0
PM = 1
Even parity
Odd parity
This bit will be "0" after reset.
MSM7630 does not use parity checking, so it ignores this field.
• bit[3] A: All Internal ROM (read/write)
This bit sets whether or not internal ROM will be accessed instead of external ROM.
MSM7630 has no internal ROM, so this bit is always "0".
• bit[2] OV: Internal ROM Valid (read-only)
This bit shows whether internal ROM is enabled or disabled.
This bit is "0" for MSM7630.
• bit[1] AV: Internal RAM Valid (read-only)
This bit shows whether internal RAM is enabled or disabled.
This bit is "0" for MSM7630.
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MSM7630
3.4 SCR: Space Configuration Register
This register sets ROM space, SRAM space, and general device space.
bit 31
26 25 24 23
A A
C D
21 20
ARW
18 17 16 15 14 13 12
AWW
AS
O O
0 C D
10 9 8 7 6 5 4 3 2 1 0
ORW
OS
D P S X
WT
S C D
SZ
• bit[25] AC: SRAM Parity Check (read/write)
This bit sets parity checking of SRAM space. It will be "0" after reset.
AC = 0
AC = 1
Ignore parity checks.
Generate a bus error if a parity error is detected.
• bit[24] AD: SRAM Dummy Cycle (read/write)
This bit sets whether or not SRAM space may be accessed continuously after ROM space or DRAM
space has been read.
AD = 0
AD = 1
Continuous access allowed.
Open an interval of at least one clock.
This bit will be "1" after reset.
• bit[23:21] ARW: SRAM Read Wait (read/write)
These bits set the wait count when SRAM space is accessed by a read.
ARW = 000
ARW = 001
ARW = 010
ARW = 011
ARW = 100
ARW = 101
ARW = 110
ARW = 111
2t access (1 wait)
3t access (2 waits)
4t access (3 waits)
5t access (4 waits)
6t access (5 waits)
8t access (7 waits)
10t access (9 waits)
12t access (11 waits)
These bits will be "111" after reset.
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MSM7630
• bit[20:18] AWW: SRAM Write Wait (read/write)
These bits set the wait count when SRAM space is accessed by a write.
AWW = 000
AWW = 001
AWW = 010
AWW = 011
AWW = 100
AWW = 101
AWW = 110
AWW = 111
2t access (1 wait)
3t access (2 waits)
4t access (3 waits)
5t access (4 waits)
6t access (5 waits)
8t access (7 waits)
10t access (9 waits)
12t access (11 waits)
These bits will be "111" after reset.
• bit[17:16] AS: SRAM Device Size (read/write)
These bits set the device size of SRAM space.
AS = 00
AS = 01
AS = 10
AS = 11
No SRAM (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
These bits will be "00" after reset. When this field is "00", attempting to access SRAM space will
cause an instruction access exception or data access exception.
• bit[14] OC: ROM Parity Check (read/write)
This bit sets parity checking for ROM space. It will be "0" after reset.
OC = 0
OC = 1
Ignore parity errors.
Generate a bus error if a parity error is detected.
This bit will be "0" for the MSM7630.
• bit[13] OD: ROM Dummy Cycle (read/write)
This bit sets whether or not a ROM space access will immediately follow an SRAM space or DRAM
space read.
OD = 0
OD = 1
Consecutive access enabled.
Force an interval of at least one clock.
This bit will be "1" after reset.
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MSM7630
• bit[12:10] ORW: ROM Read Wait (read/write)
These bits set the wait count when ROM space is accessed by a read.
ORW = 000
ORW = 001
ORW = 010
ORW = 011
ORW = 100
ORW = 101
ORW = 110
ORW = 111
2t access (1 wait)
3t access (2 waits)
4t access (3 waits)
5t access (4 waits)
6t access (5 waits)
8t access (7 waits)
10t access (9 waits)
12t access (11 waits)
These bits will be "111" after reset.
• bit[9:8] OS: ROM Device Size (read/write)
These bits set the device size of ROM space.
OS = 00
OS = 01
OS = 10
OS = 11
No ROM (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
When this field is "00", attempting to access ROM space will cause an instruction access exception
or data access exception.
• bit[7] DS: Other Data Setup (read/write)
This bit sets whether or not the data setup time to the write strobe signal WR is guaranteed during
writes to general device space.
DS = 0
DS = 1
Not guaranteed.
Guaranteed.
This bit will be "1" after reset.
• bit[6] PC: Other Parity Check (read/ write)
This bit sets parity checking for general device space. It will be "0" after reset.
PC = 0
PC = 1
Ignore parity errors.
Generate a bus error if a parity error is detected.
This bit will be "0" for the MSM7630.
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MSM7630
• bit[5] SD: Other Dummy Cycle (read/write)
This bit sets whether or not a general device space access will immediately follow an SRAM space
or DRAM space read.
SD = 0
SD = 1
Consecutive access enabled.
Force an interval of at least one clock.
This bit will be "1" after reset.
• bit[4] X: External Bus Clock Unit (read/write)
This bit sets the operating clock unit for general device space.
X=0
X=1
Use 1 clock as the unit.
Use 2 clocks as the unit.
This bit will be "0" after reset.
• bit[3:2] WT: Other Wait (read/write)
These bits set the wait count when general device space is accessed.
WT = 00
WT = 01
WT = 10
WT = 11
4t access
5t access
6t access
7t access
These bits will be "11" after reset.
• bit[1:0] SZ: Other Device Size (read/write)
These bits set the device size of general device space.
SZ = 00
SZ = 01
SZ = 10
SZ = 11
No general device (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
These bits will be "11" after reset. When this field is "00", attempting to access general device space
will cause an instruction access exception or data access exception.
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MSM7630
3.5 DRAM: DRAM Configuration Register
This register sets DRAM space.
bit 31
29 28 27 26 25 24 23 22 21 20
0 0 0
E
DT M TP
D
P MD
18 17 16 15
RA
CS
13 12 11 10 9
CA
SZ
R
F
M
0
RFC
After this register has been written, DRAM must not be accessed until the DRAM is operating
properly. Refer to the data sheet of the DRAM used to obtain the required conditions for proper
DRAM operation.
• bit[28:27] DT: Device Type (read/write)
These bits set the DRAM device type.
DT = 00
DT = 01
Fast page mode
Hyperpage mode (EDO DRAM)
These bits will be "00" after reset.
• bit[26] PR: Parity Check (read/write)
This bit sets parity checking for DRAM space. It will be "0" after reset.
PR = 0
PR = 1
Ignore parity errors.
Generate a bus error if a parity error is detected.
This bit will be "0" for the MSM7630.
• bit[25:24] TP: Type (read/write)
This bit sets the DRAM’s RAS signal and byte position control signal.
TP = 00
TP = 01
TP = 10
TP = 11
1 RAS mode, byte position CAS control
2 RAS mode, byte position CAS control
1 RAS mode, byte position WE control
2 RAS mode, byte position WE control
These bits will be "00" after reset.
• bit[23] DP: Data Priority (read/write)
This bit sets the priority of processing when data access is requested by a load/store instruction
during a one-line instruction cache read from DRAM due to an instruction cache miss.
DP = 0
DP = 1
Give priority to the instruction cache read from DRAM.
Give priority to the data access.
This bit will be "0" after reset.
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MSM7630
• bit[22:21] MD: Mode (read/write)
These bits set the number of clocks for a DRAM access.
MD = 01
MD = 10
2n clock access
3n clock access
These bits will be "10" after reset.
• bit[20:18] RA: Row Address (read/write)
These bits set the most significant bit position of the row address.
RA = 000
RA = 001
RA = 010
RA = 011
RA = 100
RA = 101
RA = 110
A17
A18
A19
A20
A21
A22
A23
These bits will be "000" after reset.
• bit[17:16] RS: Row Shift (read/write)
These bits set how many bits to shift the row address to output it as a DRAM address.
RS = 00
RS = 01
RS = 10
RS = 11
8-bit shift
9-bit shift
10-bit shift
11-bit shift
These bits will be "00" after reset.
• bit[15:13] CA: Column Address (read/write)
These bits set the most significant bit position of the column address.
CA = 000
CA = 001
CA = 010
CA = 011
CA = 100
A08
A09
A10
A11
A12
These bits will be "000" after reset.
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MSM7630
• bit[12:11] SZ: Device Size (read/write)
These bits set the device size of DRAM space.
SZ = 00
SZ = 01
SZ = 10
SZ = 11
No DRAM (space is invalid)
8-bit wide device
16-bit wide device
32-bit wide device
These bits will be "00" after reset. When this field is "00", attempting to access DRAM space will
cause an instruction access exception or data access exception.
• bit[10] RFM: Refresh Mode (read/write)
This bit sets the refresh operation mode.
RFM = 0
RFM = 1
CAS-before-RAS refresh
CAS-before-RAS self-refresh
This bit will be "0" after reset.
• bit[9:0] RFC: Refresh Counter (read/write)
These bits set the initial value of the refresh counter. It should be set as an integer value obtained
by:
[(refresh period) ÷ (clock period) ÷ 16] – 1
These bits will be "0000000000" after reset.
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MSM7630
4. ROM Access
The MSM7630 interface with ROM is shown below.
Axx
Axx
ROM
ROM
RD
CS
OE
Dxx
Data
External Bus
MSM7630
The ROM signal will become "0" when the address signal and specified ROM space match. Refer to
the timing diagram for basic timing of ROM accesses.
5. SRAM Access
The MSM7630 interface with SRAM is shown below.
Axx
Axx
SRAM
WE
RD
CS
WE
OE
SRAM
Dxx
Data
MSM7630
External Bus
The SRAM signal will become "0" when the address signal and specified SRAM space match. Refer
to the timing diagram for basic timing of SRAM accesses.
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MSM7630
6. DRAM Access
There are two MSM7630 interfaces with DRAM: one when byte position is specified by CAS, and one
when byte position is specified by WE. This is set by the DRAM register’s TP field.
An interface example when byte position is specified by CAS is shown below.
Axx
Axx
RAS
CAS [0 : 1]
WE
RAS
CAS
WE
DRAM
Dxx
Data
External Bus
MSM7630
An interface example when byte position is specified by WE is shown below.
Axx
Axx
RAS
WE
CAS [0 : 1]
RAS
CAS
WE
DRAM
Dxx
Data
MSM7630
External Bus
Refer to the timing chart for basic timing of DRAM accesses.
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MSM7630
The table below shows how address signals are connected for different DRAM configurations.
Configuration
Row
CA
RS
RA
256K ¥ 8
17-09
08-00
A[08:00]
000
01
000
256K ¥ 16
18-10
09-01
A[09:01]
001
01
001
18-09
08-01
A[09:01]
000
00
001
19-11
10-02
A[10:02]
010
01
010
19-10
09-02
A[11:02]
001
00
010
512K ¥ 8
18-09
08-00
A[09:00]
000
01
001
512K ¥ 16
19-10
09-01
A[10:01]
001
01
010
512K ¥ 32
20-11
10-02
A[11:02]
010
01
011
1M ¥ 8
19-10
09-00
A[09:00]
001
10
010
1M ¥ 16
20-11
10-01
A[10:01]
010
10
011
20-10
09-01
A[11:01]
001
01
011
20-09
08-01
A[12:01]
000
00
011
21-12
11-02
A[11:02]
011
10
100
21-11
10-02
A[12:02]
010
01
100
21-10
09-02
A[13:02]
001
00
100
20-10
09-00
A[10:00]
001
10
011
20-09
08-00
A[11:00]
000
01
011
21-11
10-01
A[11:01]
010
10
100
21-10
09-01
A[12:01]
001
01
100
22-12
11-02
A[12:02]
011
10
101
22-11
10-02
A[13:02]
010
01
101
21-11
10-00
A[10:00]
010
11
100
21-10
09-00
A[11:00]
001
10
100
22-12
11-01
A[11:01]
011
11
101
22-11
10-01
A[12:01]
010
10
101
23-13
12-02
A[12:02]
100
11
110
23-12
11-02
A[13:02]
011
10
110
256K ¥ 32
1M ¥ 32
2M ¥ 8
2M ¥ 16
2M ¥ 32
4M ¥ 8
4M ¥ 16
4M ¥ 32
Column Address lines
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MSM7630
Serial Interface
1. Features
The serial interface (SIO) performs both clock synchronized and start-stop transfers.
2. SIO Functions
2.1 Port Configuration
• Independent transmit and receive circuits
• Double buffer configuration for receive buffer
Because the transmit and receive circuits are independent, start-stop transfers are all full-duplex
communication.
2.2 Transfer Methods
• Start-stop transfer
Data length:
Transfer sequence:
Stop bits:
Parity bit:
Flag bit:
7 bits or 8 bits selectable
LSB first
1 bit or 2 bits selectable
No parity, even parity, or odd parity selectable
Enables inter-processor communication using the serial port.
However, cannot be used together with parity bit.
• Clock synchronized transfer
Data length:
Transfer sequence:
8 bits fixed
LSB first
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¡ Semiconductor
,
,
MSM7630
The chart below shows the data format with start-stop transfers.
7N1
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
1
7N2
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
1
1
7F1
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
Flag
1
7P1
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
Parity
1
7F2
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
Flag
1
1
7P2
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
Parity
1
1
8N1(*)
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
1
8N2
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
1
1
8F1
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Flag
1
8P1
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Parity
1
8F2
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Flag
1
1
8P2
1
0
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Parity
1
1
Stop bits
1 : 1 Stop Bit, 2 : 2 Stop Bits
Flag/parity
Data size
N : Non, F : Flag, P : Parity
7 : 7 bits, 8 : 8 bits
(*) After reset the format will be 8 bits, no parity, 1 stop bit.
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2.3 Baud Rate
• Internal baud rate generator
• Clock synchronized transfers
B = f/(8 ¥ n ¥ (256 – P))
where
B:
f:
n:
P:
baud rate (bps)
processor (SCP) clock frequency (Hz)
baud rate parameter
One of 1, 2, 4, 8, 16, 32, and 64. Selected by SBR’s SBRP field.
(Refer to the register description.)
baud rate adjustment value (0 £ P £ 255)
Set by SBR’s SBRV field. (Refer to the register description.)
At a processor (SCP) clock of 20 MHz, the maximum transfer rate is 2.5 Mbps. At 40 MHz, the
maximum transfer rate is 5 Mbps.
• Start-stop transfers
B = f/(16 ¥ n ¥ (256 – SBR))
where
B:
f:
n:
baud rate (bps)
processor (SCP) clock frequency (Hz)
baud rate parameter
One of 1, 2, 4, 8, 16, 32, and 64. Selected by SBR’s SBRP field.
(Refer to the register description.)
SBR : baud rate adjustment value (0 £ SBR £ 255)
Set by SBR’s SBRV field. (Refer to the register description.)
2.4 Error Detection
• Parity errors (start-stop transfers)
A parity error will be detected when a parity bit generated from received data does not match the
received parity bit.
• Framing errors (start-stop transfers)
A framing error will be detected when a received stop bit is "0". When 2 stop bits have been selected,
only the first bit received will be checked.
• Overrun errors (start-stop and clock synchronized transfers)
An overrun error will be detected when the next receive frame's stop bit is detected before the
receive buffer has been read.
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2.5 Interrupts
The SIO is the source of the following interrupts.
• Interrupts
- Receive error interrupt
A receive error interrupt will be generated whenever a parity error, framing error, or overrun
error is detected.
- Receive buffer full interrupt
A receive buffer full interrupt will be generated whenever the valid receive data has been
transferred to the receive buffer.
- Transmit buffer empty interrupt
A transmit buffer empty interrupt will be generated whenever the transmit buffer becomes
empty.
- Transmit end interrupt
A transmit end interrupt will be generated whenever an SIO data transfer ends.
- Modem status interrupt
A modem status interrupt will be generated whenever a change in a modem control input signal
(CTS, DSR) is detected.
• Interrupt enable/disable
Each interrupt source can be independently enabled or disabled. Also, all interrupts can be
disabled at once.
• Interrupt requests
Whenever any of the five interrupts above is enabled and its conditions are fulfilled, the CPU will
get an SIO interrupt request.
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3. SIO Registers
These registers control SIO.
3.1 SIB: SIO Input Buffer
This register holds data that has been input externally. It is undefined after reset.
bit 7
0
SIB
3.2 SOB: SIO Output Buffer
This register holds data to be output externally. It is undefined after reset.
bit 7
0
SOB
3.3 SSTS: SIO Status Register
This register provides SIO status.
bit 15
11 10 9 8 7 6 5 4 3 2 1 0
S
0 0 0 0 0 O
V
E
S
F
R
E
S
S S
P 0 M O
T
S S
E
I T
S
I
S
T
S
E
R
I
S
R
X
I
S
T
X
I
S
T
E
I
• bit[10] SOVE
0 : No overrun error
1 : Overrun error generated
This bit can only be written with "0". It will be "0" after reset.
• bit[9] SFRE
0 : No framing error
1 : Framing error generated
This bit can only be written with "0". It will be "0" after reset.
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• bit[8] SPTE
0 : No parity error
1 : Parity error generated
This bit can only be written with "0". It will be "0" after reset.
• bit[6] SMSI
0 : No modem status interrupt
1 : Modem status interrupt requested
This bit is read-only. It will be "0" after reset.
• bit[5] SOST
0 : Transmit buffer full
1 : Transmit buffer empty
This bit can only be written with "0". It will be "1" after reset.
• bit[4] SIST
0 : Receive buffer empty
1 : Receive buffer full
This bit can only be written with "0". It will be "0" after reset.
• bit[3] SERI
0 : No receive error interrupt
1 : Receive error interrupt requested
This bit is read-only. It will be "0" after reset.
• bit[2] SRXI
0 : No receive buffer full interrupt
1 : Receive buffer full interrupt requested
This bit is read-only. It will be "0" after reset.
• bit[1] STXI
0 : No transmit buffer empty interrupt
1 : Transmit buffer empty interrupt requested
This bit is read-only. It will be "0" after reset.
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• bit[0] STEI
0 : No transmit end interrupt
1 : Transmit end interrupt requested
This bit can only be written with "0". It will be "0" after reset.
3.4 SCMD: SIO Command Register
bit 15 14 13 12 11 10
S S S
S S
E R
R T 0 I R
X
E I I
E E
N E E
N N
9
S
T
X
I
E
8 7 6 5 4
S
S S S
T
E 0 M F F
O B B
I
D M
E
3 2 1 0
S
F
L
S
P
T
Y
S
S
T
P
• bit[15] SREN
0 : Data receive disabled
1 : Data receive enabled
This bit will be "0" after reset.
• bit[14] STEN
0 : Data transmit disabled
1 : Data transmit enabled
This bit will be "0" after reset.
• bit[12] SIEN
0 : Interrupts disabled
1 : Interrupts enabled
This bit will be "0" after reset.
• bit[11] SERIE
0 : Receive error interrupts disabled
1 : Receive error interrupts enabled
This bit will be "0" after reset.
• bit[10] SRXIE
0 : Receive buffer full interrupts disabled
1 : Receive buffer full interrupts enabled
This bit will be "0" after reset.
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• bit[9] STXIE
0 : Transmit buffer empty interrupts disabled
1 : Transmit buffer empty interrupts enabled
This bit will be "0" after reset.
• bit[8] STEIE
0 : Transmit end interrupts disabled
1 : Transmit end interrupts enabled
This bit will be "0" after reset.
• bit[6] SMOD
0 : Start-stop transfer mode
1 : Clock synchronized transfer mode
This bit will be "0" after reset.
• bit[5] SFBM
0 : Clear flag bit mode
1 : Set flag bit mode
This bit will be "0" after reset.
• bit[4] SFB
0 : Flag bit value set to "0"
1 : Flag bit value set to "1"
This bit will be "0" after reset.
• bit[3] SFL
0 : Transfer data length is 8 bits
1 : Transfer data length is 7 bits
This bit will be "0" after reset.
• bit[2:1] SPTY
00 : No parity
10 : Even parity
11 : Odd parity
These bits will be "00" after reset.
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• bit[0] SSTP
0 : 1 stop bit
1 : 2 stop bits
This bit will be "0" after reset.
3.5 SBR: Baud Rate Adjustment Register
This register sets values that adjust the baud rate.
bit 15
11 10
0 0 0 0 0
8 7
SBRP
0
SBRV
• bit[10:8] SBRP
000 :
001 :
010 :
011 :
100 :
101 :
110 :
Baud rate parameter n = 1
Baud rate parameter n = 2
Baud rate parameter n = 4
Baud rate parameter n = 8
Baud rate parameter n = 16
Baud rate parameter n = 32
Baud rate parameter n = 64
These bits will be undefined after reset.
• bit[7:0] SBRV
These bits are the baud rate adjustment value. They will be undefined after reset.
3.6 MSTS: Modem Status Register
This register provides the states of modem signals.
bit 15
12 11 10 9
D
0 0 0 0 C
T
S
4 3 2 1 0
D
C D
D 0 0 0 0 0 0 T S 0 0
S
S R
R
• bit[11] DCTS
0 : CTS signal has not changed
1 : CTS signal has changed
This bit is read-only. It will be "0" after reset.
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• bit[10] DDSR
0 : DSR signal has not changed
1 : DSR signal has changed
This bit is read-only. It will be "0" after reset.
• bit[3] CTS
0 : CTS input signal value = "0"
1 : CTS input signal value = "1"
This bit is read-only. It will be the CTS pin input value after reset.
• bit[2] DSR
0 : DSR input signal value = "0"
1 : DSR input signal value = "1"
This bit is read-only. It will be the DSR pin input value after reset.
3.7 MCMD: Modem Command Register
This register enables/disables modem status interrupts and auto-enable mode, and controls RTS
and DTR output signals.
bit 15
10 9 8 7
D
0 0 0 0 0 0 C
T
S
2 1 0
D
C D
D 0 0 0 0 0 0 T S
S
S R
R
• bit[9] SMSIE
0 : Disables modem status interrupts
1 : Enables modem status interrupts
This bit will be "0" after reset.
• bit[8] SAEN
0 : Disables auto-enable mode
1 : Enables auto-enable mode
This bit will be "0" after reset.
• bit[1] RTS
0 : Output RTS signal "0"
1 : Output RTS signal "1"
This bit will be "0" after reset.
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• bit[0] DTR
0 : Output DTR signal "0"
1 : Output DTR signal "1"
This bit will be "0" after reset.
3.8 SCNT: SIO Control Register
This register controls SIO.
bit 15
0
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S
T
P
• bit[0] CSTP
0 : Enable SIO clock supply
1 : Disable SIO clock supply
This bit will be "0" after reset.
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4. SIO Register Addresses
SIO register addresses for the MSM7630 are shown below.
0xFA000000
SIO Input Buffer
0xFA000004
SIO Output Buffer
0xFA000008
Baud Rate Adjustment Register
0xFA00000C
SIO Status Register
0xFA000010
SIO Command Register
0xFA000014
Modem Status Register
0xFA000018
Modem Command Register
0xFA00001C
SIO Control Register
5. SIO Operation
There are two methods of SIO operation: start-stop transfers where communication is performed
synchronized to characters, and clock synchronized transfers where communication is performed
synchronized to the clock.
5.1 Clock Synchronized Transfers
Clock synchronized transfer mode is selected by setting the SCMD (Command Register) SMOD bit
to "1". In this mode 8-bit data will be input/output synchronized to the clock output from the SCLK
pin.
With clock synchronized transfers, transfer data is only 8 bits, so parity bits and flag bits cannot be
added. The SCMD (Command Register) SFBM bit, SFL bit, and SPTY bits will be set to "0", "0", and
"00" respectively.
5.1.1 Clock Synchronized Transfer Baud Rate
B=
f
8 ¥ n ¥ (256 – P)
where
B : baud rate
f : SCP clock frequency
n : baud rate parameter (set by SBR register’s SBRP bit)
P : baud rate adjustment value (set by SBR register’s SBRV bit)
Set SBR (Baud Rate Adjustment Register) to achieve the required baud rate.
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5.1.2 Clock Synchronized Transmit Operation
1) Verify that the SSTS (Status Register) SOST bit is "1", and then write the data to be transferred to
the transmit buffer SOB.
2) Write "0" to SOST to indicate that SOB has valid data.
3) If using SIO interrupts, set the SCMD (Command Register) SIEN bit to "1". If using the transmit
buffer empty interrupt, write "1" to the SCMD STXIE bit. If using the transmit end interrupt, write
"1" to the SCMD STEIE bit.
4) If the MCMD (Modem Command Register) SAEN bit is "0", then setting the SCMD (Command
Register) STEN bit to "1" will start the transfer. If the MCMD SAEN bit is "1", then the transfer will
start when the SCMD STEN bit is "1" and the CTS input is "1".
5) SOB (Transmit Buffer) data will be transferred LSB first from the TXD output. Also, a synchronous
clock will be transmitted from the SCLK pin. Data on the TXD output will change synchronous
to the falling edge of SCLK. The receiving device should sample TXD data on the rising edge of
SCLK.
6) When the next data can be written to the transmit buffer, the SSTS (Status Register) SOST bit will
change from "0" to "1". If the SCMD (Command Register) STXIE and SIEN bits are "1" at this time,
then the SSTS STXI bit will become "1" and an interrupt request to the CPU will be generated.
7) For continuous transfers, after the SSTS (Status Register) SOST bit becomes "1" write new data to
SOB (Transmit Buffer) and write "0" to the SOST bit.
8) If there is no more data to be transmitted, then write "0" to the SCMD (Command Register) STXIE
bit. This will disable interrupt requests from SIO.
9) When transfer of the eighth bit of data ends, the SSTS (Status Register) SOST bit will become "1"
(transmit buffer SOB is empty), SCLK will stop, and the transmit operation will end. If the
SCMD’s STEIE and SIEN bits are "1" at this time, then the SSTS’s STEI bit will become "1" and an
interrupt request to the CPU will be generated. This interrupt can be released by writing "0" to the
SSTS’s STEI bit or the SCMD’s STEIE bit.
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5.1.3 Clock Synchronized Receive Operation
1) The receive operation will begin if the MCMD’s SAEN bit is "0" (auto-enable mode disabled) and
the SCMD’s SREN bit is "1" (data receive enabled).
2) When the receive operation begins, a synchronous clock will be output from SCLK.
3) If using SIO interrupts, set SCMD’s SIEN bit to "1". If using the receive buffer full interrupt, set
SCMD’s SRXIE bit to "1".
4) The transmitting device should input the data to be transferred on RXD on the falling edge of
SCLK, LSB first. The SIO will sample RXD data on SCLK’s rising edge, shifting it into the Receive
Shift Register.
5) When the eighth bit of data has been received, the receive shift register’s data is transferred to SIB.
However, it will not be transferred to SIB if an overrun error occurs.
6) After data has transferred from the receive shift register to the receive buffer SIB, SIST will change
from "0" to "1", indicating that there is valid data in the receive buffer SIB. If SCMD’s SRXI bit and
SIEN bit are both "1" at this time, an interrupt request to the CPU will be generated.
7) To continue receiving data, read the SIB data after SIS becomes "1", and then write "0" to SIST.
8) To end the receive operation, write "0" to SCMD’s SREN bit. At the time "0" is written to SREN,
data currently being received will be transferred to SIB and the receive operation will end.
9) When SSTS’s SIST bit is "1" and the SIO enters the state in which data is ready to be transferred
from the receive shift register to the receive buffer, the SIO will assume that an overrun error
(receipt of further data before the value of the receive buffer SIB is read) has occurred. SSTS’s SOVE
bit will then be set to "1". In this case the receive shift register value will not be transferred to the
receive buffer SIB. If SCMD’s SERIE bit and SIEN bit are "1", then SSTS's SERI bit will be set to "1"
and an interrupt request to the CPU will be generated. To release the interrupt, write "0" to SSTS’s
SOVE bit or to SCMD’s SERIE or SIEN bit.
5.2 Start-Stop Transfers
Start-stop transfer mode is selected by setting the SCMD (Command Register) SMOD bit to "0". In
this mode data is output LSB first from TXD, and input LSB first from RXD.
5.2.1 Start-Stop Transfer Baud Rate
B=
f
16 ¥ n ¥ (256 – P)
where
B : baud rate
f : SCP clock frequency
n : baud rate parameter (set by SBR register’s SBRP bit)
P : baud rate adjustment value (set by SBR register’s SBRV bit)
Set SBR (Baud Rate Adjustment Register) to achieve the required baud rate.
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5.2.2 Start-Stop Transmit Operation
1) Verify that the SSTS (Status Register) SOST bit is "1", and then write the data to be transferred to
the transmit buffer SOB. Next write "0" to SOST to indicate that SOB has valid data.
2) If the MCMD (Modem Command Register) SAEN bit is "0", then setting the SCMD (Command
Register) STEN bit to "1" will start the transfer. If the MCMD SAEN bit is "1", then the transfer will
start when the SCMD STEN bit is "1" and the CTS input is "1".
3) For start-stop transmit operation, a start bit "0" will be output from TXD. Then the data written
in SOB will be output LSB first. If SCMD’s SFL bit is "0", then 8 bits of data will be output. If the
SFL bit is "1", then 7 bits will be output.
4) When SCMD (Command Register) SFBM bit is "0", a parity bit will be output after the SOB data.
The parity will be even if the SPTY field is "10", and odd if the SPTY field is "11". If SCMD’s SFBM
bit is "1" and SPTY is "00", then the value set in SCMD’s SFB bit will be output after the SOB data.
If SCMD’s SFBM bit is "0" and the SPTY field is "0", then neither a parity bit nor flag bit will be
output after SOB data.
5) Finally, one stop bit will be output if the SCMD (Command Register) SSTP bit is "0", or two stop
bits will be output if the SSTP bit is "1". This will end the transfer of one frame of data.
6) When the next data can be written to the transmit buffer, the SSTS (Status Register) SOST bit will
change from "0" to "1". If the SCMD (Command Register) STXIE and SIEN bits are "1" at this time,
then the SSTS STXI bit will become "1" and an interrupt request to the CPU will be generated.
7) For continuous transfers, after the SSTS (Status Register) SOST bit becomes "1" write new data to
SOB (Transmit Buffer) and write "0" to the SOST bit. This will disable interrupt requests from SIO.
8) If there is no more data to be transmitted, then write "0" to the SCMD (Command Register) STXIE
bit. The will disable interrupt requests from SIO.
9) When transfer of the stop bit ends, the transmit operation will end if the SOST bit is "1". If the
SCMD's STEIE and SIEN bits are "1" at this time, then the SSTS's STEI bit will become "1" and an
interrupt request to the CPU will be generated. This interrupt can be released by writing "0" to
the SSTS's STEI bit or the SCMD's STEIE or SINT bit.
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5.2.3 Start-Stop Receive Operation
1) The receive operation can begin if the MCMD’s SAEN bit is "0" and the SCMD’s SREN bit is "1".
2) If using SIO interrupts, set SCMD’s SIEN bit to "1". If using the receive buffer full interrupt, set
SCMD’s SRXIE bit to "1". If using the receive error interrupt, set SCMD’s SERIE bit to "1".
3) The SIO receive operation will start when a falling edge is detected on RXD. The first bit of data
is received as the start bit. If the received value is "1", then it will not be recognized as a start bit,
the receive operation will be suspended, and the device will wait for another RXD falling edge to
be detected. If the received value is "0", then data will continue to be received.
4) When the start bit is received, receive of data will start. If SCMD’s SFL bit is "0", then 8 bits of data
will be input serially into the receive shift register. If the SFL bit is "1", then 7 bits of data will be
input.
5) When SCMD (Command Register) SFBM bit is "0", a parity bit will be received after the data. The
parity will be even if the SPTY field is "10", and odd if the SPTY field is "11". If SCMD’s SFBM bit
is "1" and SPTY is "00", one flag bit will be received. If SCMD’s SFBM bit is "0" and the SPTY field
is "00", then neither a parity bit nor flag bit will be received.
6) Finally one stop bit will be received. Even if SCMD’s SSTP bit is "1", only the first stop bit will be
received.
7) When all bits have been received, the data input in the receive shift register will be transferred to
the receive buffer SIB. However, if either of the following two conditions applies, then data will
not be transferred to SIB, and SIB will retain its previous value.
1. SCMD’s SFBM bit is "1", its SPTY field is "00", and the received flag bit does not match SCMD’s
SFB bit.
2. An overrun error occurred.
8) When data has been transferred from the receive shift register to the receive buffer SIB, SSTS’s SIST
will change from "0" to "1". If SCMD’s SRXIE and SIEN bits are both "1", then SSTS’s SRXI bit will
become "1" and an interrupt request to the CPU will be generated. To release the interrupt, write
"0" to SSTS’s SIST bit or to SCMD’s SRXIE or SIEN bit.
9) When SSTS’s SIST bit is "1" and the SIO enters the state in which data is ready to be transferred
from the receive shift register to the receive buffer, the SIO will assume that an overrun error
(receipt of further data before the value of the receive buffer is read) has occurred. SSTS’s SOVE
bit will then be set to "1".
10) If the received stop bit is "0", then it will be considered indication of a framing error. SSTS’s SFRE
bit will then be set to "1".
11) When SCMD’s SPTY field is "10" or "11", a mismatch between parity generated from the receive
data and the parity bit will be considered a parity error. SSTS’s SPTE bit will then be set to "1".
12) If one or more of the SOVE, SFRE, and SPTE bits are "1" and the SCMD' s SERIE and SIEN bits
are "1", then SSTS's SERI bit will be set to "1" and an interrupt request to the CPU will be generated.
13) To release the interrupt for any error, write "0" to all of SSTS’s SOVE, SFRE, and SPTE bits, or write
"0" to SCMD’s SERIE or SIEN bits.
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Parallel Interface
1. Features
The parallel interface (PIO) inputs and outputs 8-bit wide parallel data. It has three data transfer
methods: software control mode where input/output is specified with 1-bit ports, handshake
control mode through strobe/acknowledge signals and flags indicating buffer status, and bus
control mode through read/write signals.
2. PIO Functions
2.1 PIO Data Size
• 8 bits
2.2 PIO Control Modes
• Software control mode
In software control mode, the PIO controls input and output of bits in accordance with the value
written in the direction register. If a direction register bit is "0", then the corresponding pin level will
be an input. If "1", then the value in the corresponding output buffer will be output to the pin.
• Handshake control mode
In handshake control mode, the PIO inputs external data through a handshake using a strobe signal
(PSTB) and input buffer full signal (PIBF). It outputs data externally through a handshake using an
output buffer full signal (POBF) and acknowledge signal (PACK).
• Bus control mode
In bus control mode, the PIO controls data input/output with a chip select signal (PCS), flag/buffer
select signal (PIOA), read signal (PACK), and write signal (PSTB).
2.3 PIO Interrupts
Interrupts to the CPU core are available when handshake control mode or bus control mode is
selected.
• Input buffer full interrupts
When PCMD’s PIEN bit is "1", writing "0" to the PIIE bit will disable input buffer full interrupts, and
writing "1" will enable them. When the PIEN bit is "0", input buffer full interrupts will be disabled
regardless of the value of the PIIE bit.
If input buffer full interrupts are enabled, then one will be generated whenever the input buffer is
written from an external device.
To release input buffer full interrupts, write "0" to the status register PSTS’s PIST bit, to the command
register PCMD’s PIIE bit, or to PCMD’s PIEN bit.
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• Output buffer empty interrupts
When PCMD’s POEN bit is "1", writing "0" to the POIE bit will disable output buffer empty interrupts,
and writing "1" will enable them. When the POEN bit is "0", output buffer empty interrupts will be
disabled regardless of the value of the POIE bit.
If output buffer empty interrupts are enabled, then one will be generated whenever the output buffer
is read by an external device.
To release output buffer empty interrupts, write "0" to the status register PSTS’s POST bit, to the
command register PCMD’s POIE bit, or to PCMD’s POEN bit.
3. PIO Registers
These registers control the PIO.
3.1 PIB: PIO Input Buffer
This buffer saves data input from an external device. It will be undefined after reset.
bit 7
0
PIB
3.2 POB: PIO Output Buffer
This buffer saves data to be output to an external device. It will be undefined after reset.
bit 7
0
POB
3.3 PDIR: PIO Direction Register
This register specifies under software control whether each parallel port bit is input or output. It will
be "00000000" after reset.
bit 7
0
PDIR
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3.4 PSTS: PIO Status Register
This register provides the PIO status.
bit 7 6 5 4 3 2 1 0
0 0
P
I
N
T
I
P
I
N
T
O
P
A
C
K
P
O
S
T
P
S
T
B
P
I
S
T
• bit[5] PINTI
0 : No input buffer full interrupt
1 : Input buffer full interrupt occurred
This bit will be "0" after reset.
• bit[4] PINTO
0 : No output buffer empty interrupts
1 : Output buffer empty interrupt occurred
This bit will be "0" after reset.
• bit[3] PACK
0 : No acknowledge
1 : Acknowledge
This bit will be undefined after reset.
• bit[2] POST
0 : Output buffer full
1 : Output buffer empty
This bit can only be written with "0". It will be "1" after reset.
• bit[1] PSTB
0 : No strobe
1 : Strobe
This bit will be undefined after reset.
• bit[0] PIST
0 : Input buffer empty
1 : Input buffer full
This bit can only be written with "0". It will be "0" after reset.
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MSM7630
3.5 PCMD: PIO Command Register
This register specifies the parallel port mode and specifies whether interrupts are enabled or
disabled. It will be "00000000" after reset.
bit 7 6 5 4 3 2 1 0
P
M
O
D
P
O
E
N
P
P P
I 0 0 O I
E
I I
N
E E
• bit[7:6] PMOD
00 : Bus control mode
01 : Handshake control mode
1x : Software control mode
• bit[5] POEN
0 : Output operation disabled
1 : Output operation enabled
• bit[4] PIEN
0 : Input operation disabled
1 : Input operation enabled
• bit[1] POIE
0 : Output buffer empty interrupts disabled
1 : Output buffer empty interrupts enabled
• bit[0] PIIE
0 : Input buffer full interrupts disabled
1 : Input buffer full interrupts enabled
4. PIO Register Addresses
For the MSM7630, PIO register addresses are listed below.
0xFB000000
PIO Input Buffer
0xFB000004
PIO Output Buffer
0xFB000008
PIO Direction Register
0xFB00000C
PIO Status Register
0xFB000010
PIO Command Register
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¡ Semiconductor
MSM7630
5. PIO Operation
5.1 Software Control Mode
In software control mode data input/output and control signals are all controlled by software.
5.1.1 Data Input from External Device
1) Write "1x" to the PCMD (Command Register) PMOD bits ("x" indicates that either "0" or "1" is
acceptable).
2) Read the input buffer PIB to read the parallel port’s pin levels at that time.
5.1.2 Data Output to External Device
1) Write "1x" to the PCMD (Command Register) PMOD bits ("x" indicates that either "0" or "1" is
acceptable).
2) Write a value to the output buffer POB.
3) Write "1" to the bits in PDIR (Direction Register) that correspond to parallel port pins that will be
outputs. This starts to drive the parallel port for data to be output.
4) If "0" is written to any bits in PDIR, then the corresponding parallel port pins will stop being
driven.
5.2 Handshake Control Mode
In handshake control mode data input is controlled by handshake using a strobe (PSTB), input buffer
full (PIBF), acknowledge (PACK), and output buffer full (POBF) for input/output.
5.2.1 Data Input from External Device
(A) SCP operation
1) Write "01" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s PIEN bit to
enable input operation.
2) When data is written to the input buffer PIB from the external device, the PSTS (Status Register)
PIST bit will become "1" to indicate that there is valid data in PIB. When PSTS’s PIST bit becomes
"1", the input buffer full output (PIBF) will become "1".
3) If PSTS’s PIST bit is "1" and input buffer full interrupts have been enabled (PCMD’s PIIE bit is "1"),
then a PIO interrupt to the CPU core will be generated.
4) The CPU core verifies that PSTS’s PIST bit is "1" in the PIO interrupt vector process routine and
reads the input buffer PIB. It then writes "0" to PSTS’s PIST bit to release the interrupt.
5) When PSTS’s PIST bit becomes "0", the input buffer full output (PIBF) also becomes "0".
6) Repeat the operation from step 2).
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MSM7630
(B) External operation
1) Verify that the input buffer full output (PIBF) is "0".
2) Drive the parallel input/output bus (PD[7:0]) with input data.
3) Set the strobe input (PSTB) to "1". This writes the data to the input buffer PIB.
4) When the input buffer full output (PIBF) becomes "1", stop driving the parallel input/output bus
and set the strobe input (PSTB) to "0".
5) Repeat the operation from step 1).
5.2.2 Data Output to External Device
(A) SCP operation
1) Write "01" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s POEN bit to
enable output operation.
2) Verify that the PSTS (Status Register) POST bit is "1", indicating that the output buffer POB is
empty.
3) Write data to the output buffer POB.
4) Write "0" to PSTS’s POST bit. When POST becomes "0", the output buffer full output (POBF) will
become "1".
5) If PSTS’s POST bit is "1" and output buffer full interrupts have been enabled (PCMD’s POIE bit
is "1"), then a PIO interrupt to the CPU core will be generated. This interrupt will be released by
writing "0" to PSTS’s POST bit or writing "0" to PCMD’s POIE bit.
6) Write data to the output buffer POB and repeat the operation from step 4).
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¡ Semiconductor
MSM7630
(B) External operation
1) Verify that the output buffer full output (POBF) is "1".
2) Set the acknowledge input (PACK) to "1". When the acknowledge input is set to "1", the PIO will
output the value of the output buffer (POB) to the parallel input/output bus (PD[7:0]).
3) Verify that the output buffer full output (POBF) is "0".
4) Read the value on the input/output bus.
5) Set the acknowledge input (PACK) to "0". When the acknowledge input becomes "0", the PIO will
stop driving the input/output bus.
6) Repeat the operation from step 1).
5.3 Bus Control Mode
In bus control mode data input/output is controlled externally by the chip select input (PCS), flag/
buffer select input (PIOA), read input (PACK), and write input (PSTB).
(A) SCP operation
1) Write "00" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s PIEN bit to
enable input operation.
2) When an external device writes data to the input buffer PIB, the PSTS (Status Register) PIST bit
will become "1", indicating that there is valid data in the input buffer PIB.
3) If PCMD’s PIIE bit is "1", then a PIO interrupt to the CPU core will be generated.
4) The CPU core verifies that PSTS’s PIST bit is "1" in the PIO interrupt vector process routine and
reads the input buffer PIB. It then writes "0" to PSTS’s PIST bit to release the interrupt.
5) Repeat the operation from step 2).
(B) External operation
1) Read the input buffer full output (PIBF).
Chip select input
Flag/buffer select input
Read input
Write input
PCS
PIOA
PACK
PSTB
0
0
0
1
2) Verify that the input buffer full output (PIBF) is "0".
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MSM7630
3) Write data to the input buffer (PIB).
Chip select input
Flag/buffer select input
Read input
Write input
Input/output bus
PCS
PIOA
PACK
PSTB
PD[7:0]
0
1
1
0
Write data
4) Repeat the operation from step 1).
5.3.2 Data Output to External Device
(A) SCP operation
1) Write "00" to the PCMD (Command Register) PMOD bits. Also write "1" to PCMD’s POEN bit to
enable output operation.
2) Verify that the PSTS (Status Register) POST bit is "1", indicating that the output buffer POB is
empty.
3) Write data to the output buffer POB.
4) Write "0" to PSTS’s POST bit. When POST is "0", the output buffer full output (POBF) will become
"1".
5) When POST becomes "1" and PCMD’s POIE bit is "1", then a PIO interrupt to the CPU core will
be generated. This interrupt will be released by writing "0" to PSTS’s POST bit or by writing "0"
to PCMD’s POIE bit.
6) Repeat the operation from step 3).
(B) External operation
1) Read the output buffer full output (POBF).
Chip select input
Flag/buffer select input
Read input
Write input
PCS
PIOA
PACK
PSTB
0
0
0
1
2) Verify that the output buffer full output (POBF) is "1".
3) Read the output buffer (POB).
Chip select input
Flag/buffer select input
Read input
Write input
Input/output bus
PCS
PIOA
PACK
PSTB
PD[7:0]
0
1
0
1
Read data
4) When the output buffer is read, PSTS's POST bit will become "1".
5) Repeat the operation from step 1).
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¡ Semiconductor
MSM7630
Timer Unit
1. Features
The timer unit (TMR) is a 16-bit programmable timer. It has two modes: an interval timer mode
which requests interrupts to the CPU core, and a clock division mode which generates a 50% duty,
frequency divided clock.
2. TMR Functions
2.1 Counter
• 16-bit up counter
2.2 Counter Clock Period
•
•
•
•
F (SCP operating frequency ¥ 1)
4F (SCP operating frequency ¥ 4)
16F (SCP operating frequency ¥ 16)
64F (SCP operating frequency ¥ 64)
2.3 Interval Timer Interrupts
When the counter overflows (counter value changes from 0xFFFF to 0x0000), it will request an
interrupt to the CPU core.
2.4 Divided Clock Generation
When the counter overflows (counter value changes from 0xFFFF to 0x0000), it will invert the value
currently being output.
3. TMR Registers
3.1 TIR: Timer Initial Value Register
This register saves the counter’s initial value. When this register is written, the same value will be
written to the Timer Value Register (TCR). This register will be undefined after reset.
bit 15
0
TIR
3.2 TCR: Timer Value Register
This register provides the counter’s current value. It will be undefined after reset.
bit 15
0
TCR
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¡ Semiconductor
MSM7630
3.3 TSTS: Timer Status Register
This register provides TMR status.
bit 7
1 0
T T
0 0 0 0 0 0 D C
A A
T
• bit[1] TDAT
0 : No timer interrupt request occurred (interval timer mode)
Divided clock output is "0" (divided clock mode)
1 : Timer interrupt request occurred (interval timer mode)
Divided clock output is "1" (divided clock mode)
• bit[0] TCA
0 : Timer counter operation is suspended
1 : Timer counter is operating
3.4 TCMR: Command Register
This register sets TMR operation.
bit 7 6 5 4 3 2 1 0
T
T
C 0 M
O
G
D
T
C 0 0
A
I
T
C
S
• bit[7] TCG
0 : Disable timer counter operation
1 : Enable timer counter operation
This bit will be "0" after reset.
• bit[5] TMOD
0 : Interval timer mode
1 : Divided clock mode
This bit will be "0" after reset.
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¡ Semiconductor
MSM7630
• bit[4] TCAI
0 : Disable auto-initialization of timer value register
1 : Enable auto-initialization of timer value register
This bit will be "0" after reset.
• bit[1:0] TCS
00 :
01 :
10 :
11 :
Count clock F
Count clock 4 F
Count clock 16 F
Count clock 64 F
These bits will be "00" after reset.
4. TMR Register Addresses
The MSM7630 has two timers. The register addresses for each are listed below.
TMR1
TMR2
Timer Initial Value Register
0xF8000000
Timer Value Register
0xF8000004
Timer Status Register
0xF8000008
Timer Command Register
0xF800000C
Timer Initial Value Register
0xF8000010
Timer Value Register
0xF8000014
Timer Status Register
0xF8000018
Timer Command Register
0xF800001C
5. TMR Operation
5.1 Interval Timer Mode
In interval timer mode counting begins from the value set in the Timer Initial Value Register, and a
timer interrupt is generated to the CPU when the counter overflows.
1) Set the TCMR (Command Register) TCG bit to "0", disabling counting.
2) Set TCMR’s TCS bits to select the counter’s increment clock.
3) Set TCMR’s TMOD bit to "0", setting interval timer mode as the operating mode.
4) To generate periodic interrupts set TCMR’s TCAI bit to "1", which will set the counter to be loaded
with the value of the Timer Initial Value Register each time the counter overflows. For a one-shot
interrupt set the TCAI bit to "0".
5) Set the timer’s initial value in the Timer Initial Value Register TIR. Writing to this register will
simultaneously write the same value to the Timer Value Register TCR.
6) Write "1" to TCMR’s TCG bit to start counting. An interrupt will be generated when the counter
overflows.
7) To release the interrupt set the TSTS (Status Register) TDAT bit to "0" in software.
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MSM7630
5.2 Divided Clock Mode
In divided clock mode counting begins from the value set in the Timer Initial Value Register, and the
divided clock output value inverts when the counter overflows.
1) Set the TCMR (Command Register) TCG bit to "0", disabling counting.
2) Set TCMR’s TCS bits to select the counter’s increment clock.
3) Set TCMR’s TMOD bit to "1", setting divided clock mode as the operating mode.
4) To generate a periodic divided clock set TCMR’s TCAI bit to "1", which will set the counter to be
loaded with the value of the Timer Initial Value Register each time the counter overflows. For a
one-shot divided clock set the TCAI bit to "0".
5) Set the timer’s initial value in the Timer Initial Value Register TIR. Writing to this register will
simultaneously write the same value to the Timer Value Register TCR.
6) Write "1" to TCMR’s TCG bit to start counting and generating a divided clock.
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¡ Semiconductor
MSM7630
Speech Data Registers
1. Features
This is a register group and control circuit used for speech output.
2. Speech Data Registers Functions
2.1 Speech Output Registers
These are 12-bit registers that store speech output data. There are two registers and one output
register configured to operate at the speech sampling frequency.
Use of two registers reduces the frequency of interrupt generation during waveform output, which
lightens the CPU load. The output stage is provided in the register, which corrects the inaccuracies
in the sampling frequencies that are caused by interrupts.
Interrupt to
DATA
CLK
12-bit REG
DATA
D
WR
CPU
TMR2 output
12-bit REG
1
1/2
12-bit REG
DAC
The two registers are in parallel, continuously written with D/A conversion data. The output
register reads the data from the two registers alternately in every sampling cycle.
The output level registers' clock is generated by TMR2. This clock is multiplied by 1/2 to output
interrupt signals. The interrupt signals are used to write the waveform output data to the speech
output registers.
Note the following when the MSM7576 mode (described later) is not used when using the speech
output registers :
– The TMR2 must be set to the divided clock mode.
– To write data to DAC1 and DAC2, write to DAC2 first, then DAC1.
– Do not clear the status register of the TMR2. If it is cleared by an interrupt routine, the sampling
frequency for the speech output will change.
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MSM7630
TMR2 output
0xxxxx
DAREGO
0x0000
0x0001
0x0002
DAREG1
0x0001
0x0003
DAREG2
0x0000
0x0002
Interrupt to
CPU
2.2 MSM7576 Mode
This mode forces operation to be the same as MSM7576 operation. Interrupt signals from TMR2 are
output directly as interrupts to the CPU.
DATA
CLK
TMR2 output
Interrupt to CPU
12-bit REG
DAC
3. Speech Data Registers Details
3.1 DAC1: Speech Output Register 1
This register stores speech output data. It will be "000000000000" after reset.
bit 15
12 11
0 0 0 0
0
DAC1
3.2 DAC2: Speech Output Register 2
This register stores speech output data. It will be "000000000000" after reset.
bit 15
12 11
0 0 0 0
0
DAC2
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¡ Semiconductor
MSM7630
3.3 DACO: D/A Conversion Register
This register stores data to be input to the D/A converter. It will be "000000000000" after reset.
bit 15
12 11
0
0 0 0 0
DACO
3.4 USTAT: Status Register
This register indicates whether or not the speech output registers/circuits have generated an
interrupt to the CPU.
Writing "0" to this register releases the interrupt from the speech output registers/circuits. In
MSM7576 mode USTAT will become "0" when the TMR2 interrupt is released.
bit 7
1 0
U
S
0 0 0 0 0 0 0 T
A
T
3.5 UPORT: General Register
This is a general register. It will be "0" after reset.
bit 7
1 0
U
P
0 0 0 0 0 0 0 O
R
T
3.6 MODE7576: MSM7576 Mode Select Register
This register sets MSM7576 mode. It will be "0" after reset.
bit 7
1 0
M
0 0 0 0 0 0 0 O
D
E
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¡ Semiconductor
MSM7630
4. Speech Output Registers Address Configuration
The addresses used by the speech output registers/circuits are assigned at 0x80000000. Accesses to
this space will be 3t access.
Speech Output Register 1
0x80000000
Speech Output Register 2
0x80000004
D/A Conversion Register
0x80000008
Status Register
0x8000000C
General Register
0x80000010
MSM7576 Mode Select Register
0x80000020
Speech Output
1. Output Waveform from DAO1
The speech output pin directly outputs the output of the DA converter.
The output waveform from DAO1 will be a staircase synchronized to the sampling frequency.
Maximum output amplitude will be (4095/4096 ¥ VDD).
2. Output Filter
Because the output from DAO1 is a staircase described above, add a low-pass filter. The diagram
below shows a reference circuit for a Butterworth low-pass filter.
1200p
2
3
–
+
1
R
15
R
R
8
1k
1000p
300p
2200p
0.1µ
–
14 +
4
11
R
16
R
13
–
12 +
10
–
7
5 +
9
220p
6
1k
MC14573P
Butterworth low-pass filter
R = 47k, f = 4.8 kHz (95 model: for 12 kHz sampling)
R = 36k, f = 6.4 kHz (96 model: for 16 kHz sampling)
R = 27k, f = 9.6 kHz (97 model: for 22 kHz sampling)
91/95
¡ Semiconductor
MSM7630
Oscillation Circuit
There are two methods to generate the MSM7630 system clock: adding an external crystal oscillator
or supplying an external clock.
1. Crystal Oscillator
The diagram below shows a connection example for a crystal oscillator.
MSM7630
22 pF
CLK
Crystal
1 MW
22 pF
XO
GND
2. External Clock
The diagram below shows an example using an external clock.
MSM7630
CLK
External Clock
Open
XO
The external clock is input on the CLK pin. Leave the XO pin open.
92/95
2
20 MHz
STBY
RST
3
VCC
+3.3 V
A +3.3 V
–
+
1
5
1k
A
MSM7630
R
12
220p
1k
100p
A
A
15 –
+
14
10
8
+
RCA Jack
16
13
A
A
A
Butterworth low-pass filter
R = 47k, f = 4.8 kHz (95 model: for 12 kHz sampling)
VCC
SCLK
TXD
RXD
DSR
DTR
CTS
RTS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
POBF
PIBF
PSTB
PACK
PCS
PIOA
13
7
A
A
99
98
1
2
17
32
48
64
79
94
95
100
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AVDD
RST
STBY
UPORT
CLK
XO
CLKA
EXTINT
DAO1
TEST0
SG
AGND
GND
GND
GND
GND
GND
GND
GND
GND
10
24
40
56
72
87
96
97
3
5
90
92
93
91
96
1000p
R
4
–
+
MC14573
R = 36k, f = 6.4 kHz (96 model: for 16 kHz sampling)
54
51
53
46
50
49
47
30
31
33
34
35
36
37
38
45
43
44
42
41
39
R = 27k, f = 9.6 kHz (97 model: for 22 kHz sampling)
PD<7 : 0>
IOW
IOR
PCS
PA0
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
WR1
WR0
RD
SRAM
ROM
WE
RAS
CAS1
CAS0
AS
TSTM1
TSTM2
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
6
R
11 –
VCC
12
13
14
15
16
18
19
20
21
22
23
25
26
27
28
29
6
7
4
11
9
55
52
58
57
8
88
89
85
84
83
82
81
80
78
77
76
75
74
73
71
70
69
68
67
66
65
63
62
61
60
59
R
8
A
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R
A +5 V
2200p
A
¡ Semiconductor
0.1µ
1200p
SYSTEM CONFIGURATION EXAMPLE
22p
1M
Parallel Interface Application Example
22p
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D26
D25
D24
Pull-up/down 10k
(when the bus capacitance is 100 pF)*
MSM27C1602
D15
A19
D14
A18
D13
A17
D12
A16
D11
A15
D10
A14
D9
A13
D8
A12
D7
A11
D6
A10
D5
A9
D4
A8
D3
A7
D2
A6
D1
A5
D0
A4
A3
A2
BYTE
A1
OE
A0
CE
16Mb ROM (x16)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
VCC
A9
A8
A7
A6
A5
A4
A3
A2
A1
MSM514260ZS
D15
D14
D13
D12
A8
D11
A7
D10
A6
A5
D9
A4
D8
A3
D7
A2
D6
A1
D5
A0
D4
D3
RAS
D2
UCAS
D1
LCAS
D0
WE
OE
4Mb DRAM (x16)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MSM29C401
A18
I/O7
A17
I/O6
A16
I/O5
A15
I/O4
A14
I/O3
A13
I/O2
A12
I/O1
A11
I/O0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
WE
OE
CE
4Mb Flash ROM (x8)
D31
D30
D29
D28
D27
D26
D25
D24
* Determine the value of each resistor
so that the bus will stabilize within 18 ms.
Text-to-Speech Conversion System Configuration Example
(Parallel Interface Application)
MSM7630
93/95
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
0.1µ
STBY
RST
3
VCC
+3.3 V
A +3.3 V
–
+
1
5
1k
A
MSM7630
SCLK
TXD
RXD
DSR
DTR
CTS
RTS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
POBF
PIBF
PSTB
PACK
PCS
PIOA
54
51
53
46
50
49
47
30
31
33
34
35
36
37
38
45
43
44
42
41
39
13
7
R
12
220p
1k
A
A
15 –
+
14
10
8
+
300p
A
A
RCA Jack
16
13
A
A
A
MAX232
Butterworth low-pass filter
R = 47k, f = 4.8 kHz (95 model: for 12 kHz sampling)
R = 36k, f = 6.4 kHz (96 model: for 16 kHz sampling)
R = 27k, f = 9.6 kHz (97 model: for 22 kHz sampling)
99
98
1
2
17
32
48
64
79
94
95
100
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AVDD
RST
STBY
UPORT
CLK
XO
CLKA
EXTINT
DAO1
TEST0
SG
AGND
GND
GND
GND
GND
GND
GND
GND
GND
10
24
40
56
72
87
96
97
3
5
90
92
93
91
86
1000p
R
4
–
+
MC14573
T1IN
R1OUT
C1+
1µ
1µ
C1–
C2+
C2–
R2OUT
T2IN
T1OUT
R1IN
VCC
V+
V–
GND
R2IN
T2OUT
DIN8P
1
2
3
4
5
6
7
8
VCC
1µ
1µ
VCC
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
WR1
WR0
RD
SRAM
ROM
WE
RAS
CAS1
CAS0
AS
TSTM1
TSTM2
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
6
R
A +5 V
11 –
VCC
VCC
VCC
12
13
14
15
16
18
19
20
21
22
23
25
26
27
28
29
6
7
4
11
9
55
52
58
57
8
88
89
85
84
83
82
81
80
78
77
76
75
74
73
71
70
69
68
67
66
65
63
62
61
60
59
R
8
A
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R
2200p
A
1200p
2
20 MHz
¡ Semiconductor
22p
1M
Serial Interface Application Example
22p
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D26
D25
D24
Pull-up/down 10k
(when the bus capacitance is 100 pF)*
MSM27C1602
D15
A19
D14
A18
D13
A17
D12
A16
D11
A15
D10
A14
D9
A13
D8
A12
D7
A11
D6
A10
D5
A9
D4
A8
D3
A7
D2
A6
D1
A5
D0
A4
A3
A2
BYTE
A1
OE
A0
CE
16Mb ROM (x16)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
VCC
A9
A8
A7
A6
A5
A4
A3
A2
A1
MSM514260ZS
D15
D14
D13
D12
A8
D11
A7
D10
A6
A5
D9
A4
D8
A3
D7
A2
D6
A1
D5
A0
D4
D3
RAS
D2
UCAS
D1
LCAS
D0
WE
OE
4Mb DRAM (x16)
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MSM29C401
A18
I/O7
A17
I/O6
A16
I/O5
A15
I/O4
A14
I/O3
A13
I/O2
A12
I/O1
A11
I/O0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
WE
OE
CE
4Mb Flash ROM (x8)
D31
D30
D29
D28
D27
D26
D25
D24
2400 bps
4800 bps
9600 bps 19200 bps
* Determine the value of each resistor
so that the bus will stabilize within 18 ms.
Text-to-Speech Conversion System Configuration Example
(Serial Interface Application)
MSM7630
94/95
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
¡ Semiconductor
MSM7630
PACKAGE DIMENSIONS
(Unit : mm)
QFP100-P-1420-0.65-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.29 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
95/95