ALLEGRO A3946KLB

Data Sheet
29319.150b
3946
Half-Bridge Power MOSFET Controller
A3946KLB SOIC
Scale 1:1
VREG
1
16 VBB
CP2
2
15 VREF
CP1
3
14 DT
PGND
4
13 LGND
GL
5
12 RESET
S
6
11
GH
7
10 IN1
BOOT
8
9
IN2
~FAULT
A3946KLP TSSOP with Exposed Thermal Pad
Scale 1:1
VREG
1
16 VBB
CP2
2
15 VREF
CP1
3
14 DT
PGND
4
13 LGND
GL
5
12 RESET
S
6
11 IN2
GH
7
10 IN1
BOOT
8
9 ~FAULT
The A3946 is designed specifically for applications that require
high power unidirectional dc motors, three-phase brushless dc motors, or
other inductive loads. The A3946 provides two high-current gate drive
outputs that are capable of driving a wide range of power N-channel
MOSFETs. The high-side gate driver switches an N-channel MOSFET
that controls current to the load, while the low-side gate driver switches
an N-channel MOSFET as a synchronous rectifier.
A bootstrap capacitor provides the above-battery supply voltage
required for N-channel MOSFETs. An internal charge pump for the
high side allows for dc (100% duty cycle) operation of the half-bridge.
The A3946 is available in a choice of two power packages: a
16-lead SOIC with internally fused leads (part number suffix LB), and
a 16-lead TSSOP with exposed thermal pad (suffix LP). Both packages
have a lead (Pb) free version, with 100% matte tin plated leadframes
(suffix -T).
FEATURES
On-chip charge pump for 7 V minimum input supply voltage
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB ............................. 60 V
Logic Inputs ..................................–0.3 V to 6.5 V
Pin S……. .........................................–4 V to 60 V
Pin GH ...........................................–4 V to 75 V
Pin BOOT….. ................................–0.6 V to 75 V
Pin DT ........................................................ VREF
Pin VREG ......................................–0.6 V to 15 V
Package Thermal Resistance, RJA
High-current gate drive for driving a wide range of
N-channel MOSFETs
Bootstrapped gate drive with charge pump for 100% duty cycle
Overtemperature protection
Undervoltage protection
–40ºC to 135ºC ambient operation
Selection Guide
Part Number
Pb-free
A3946KLB..................................... 48°C/W
1
A3946KLB
A3946KLB..................................... 38°C/W
2
A3946KLB-T
Yes
A3946KLBTR
–
A3946KLP ..................................... 44°C/W1
A3946KLP ..................................... 34°C/W2
Operating Temperature Range, TA .. –40°C to +135°C
Junction Temperature, TJ...........................+150°C
Storage Temperature Range, TS ....-55°C to +150°C
Notes:
1. Measured on a two-sided PCB with 3 in.2 of
2 oz. copper.
2. Measured on JEDEC standard High-K board.
A3946KLBTR-T
A3946KLP
–
Yes
–
A3946KLP-T
Yes
A3946KLPTR
–
A3946KLPTR-T
Yes
Packing
Package
47 pieces/tube
16-pin SOIC with internally
fused leads
1000 pieces/reel
96 pieces/tube
16-pin TSSOP with exposed
thermal pad
4000 pieces/reel
3946
Half-Bridge Power MOSFET Controller
Functional Block Diagram
+VBAT
C1
0.47 uF, X7R
V rated to VBAT
C2
0.47 uF, X7R
V rated to VBAT
P
VBB
CP2
VREF
10
kΩ
L
VREG
Charge
Pump
+5 Vref
0.1 uF
X7R
10 V
CP1
L
CREG
ILIM
P
P
Charge
Pump
BOOT
~FAULT
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
CBOOT
L
VREF
DT
RDEAD
Turn-On
Delay
IN1
P
Control
Logic
L
RGATE
GH
High Side
Driver
S
VREG
L
IN2
RGATE
GL
Low Side
Driver
PGND
L
P
RESET
LGND
L
L
P
Control Logic Table
IN1
IN2
X
X
0
0
0
1
1
1
DT Pin
RESET
GH
GL
Function
X
0
Z
Z
Sleep mode
RDEAD - LGND
1
L
H
Low-side FET ON following dead time
RDEAD - LGND
1
L
L
All OFF
0
RDEAD - LGND
1
L
L
All OFF
1
RDEAD - LGND
1
H
L
High-side FET ON following dead time
0
0
VREF
1
L
L
All OFF
0
1
VREF
1
L
H
Low-side FET ON
1
0
VREF
1
H
L
High-side FET ON
1
1
VREF
1
H
H
CAUTION: High-side and low-side FETs ON
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
3946
Half-Bridge Power MOSFET Controller
ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Limits
Min.
Typ.
Max.
Units
–
–
3
6
mA
–
10
μA
VBB > 7.75 V, Ireg = 0 mA to 15 mA
12.0
13
13.5
V
VBB = 7 V to 7.75 V, Ireg = 0 mA to 15 mA
11.0
–
13.5
V
–
62.5
–
kHz
4.5
–
5.5
V
60
100
ns
40
80
ns
4
3
–
–
–
–
Ω
Tj = 135°C
–
–
–
–
–
–
RESET = High, Outputs Low
VBB Quiescent Current
IVBB
VREG Output Voltage
VREG
Charge Pump Frequency
FCP
CP1, CP2
VREF Output Voltage
VREF
IREF ≤ 4 mA, CREF = 0.1 μF
RESET = Low
Gate Output Drive
Turn On Time
trise
CLOAD = 3300 pF, 20% to 80%
Turn Off Time
tfall
CLOAD = 3300 pF, 80% to 20%
Pullup On Resistance
Pulldown On Resistance
RDSUP
RDSDOWN
Tj = 25°C
Tj = 135°C
Tj = 25°C
6
2
Ω
Ω
Ω
Short Circuit Current –
Source
–
tpw < 10 μs
800
–
–
mA
Short Circuit Current –
Sink
–
tpw < 10 μs
1000
–
–
mA
VREG – 1.5
–
–
V
VREG – 0.2
–
–
200
350
500
ns
Rdead = 100 kΩ
5
6
7
μs
Logic input to unloaded GH, GL. DT = VREF
–
–
150
ns
GH Output Voltage
VGH
GL Output Voltage
VGL
tpw < 10 μs, Bootstrap Capacitor fully charged
–
V
Timing
Dead Time (Delay from
Turn Off to Turn On)
Propagation Delay
tDEAD
tPD
Rdead = 5 kΩ
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3
3946
Half-Bridge Power MOSFET Controller
ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
Limits
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
9.1
9.6
V
Protection
VREG Undervoltage
VREGON
VREG increasing
8.6
VREG Undervoltage
VREGOFF
VREG decreasing
7.8
8.3
8.8
V
BOOT Undervoltage
VBSON
VBOOT increasing
8
8.75
9.5
V
BOOT Undervoltage
VBSOFF
VBOOT decreasing
7.25
8.0
8.75
V
Thermal Shutdown Temperature
TJTSD
Temperature increasing
170
ΔTJ
Recovery = TJTSD – ΔTJ
15
–
–
°C
Thermal Shutdown Hysteresis
–
–
IIN(1)
IN1 VIN / IN2 VIN = 2.0 V
40
100
μA
IIN(0)
IN1 VIN / IN2 VIN = 0.8 V
–
–
–
16
40
μA
–
–
–
–
–
–
–
1
μA
–
–
V
0.8
V
300
mV
400
mV
1
μA
°C
Logic
Input Current
RESET pin only
Logic Input Voltage
VIN(1)
VIN(0)
Logic Input Hysteresis
Fault Output
IN1 / IN2 logic high
2.0
RESET logic high
2.2
Logic low
–
All digital inputs
Vol
I = 1 mA, fault asserted
Voh
V=5V
–
100
–
–
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V
4
3946
Half-Bridge Power MOSFET Controller
Functional Description
VREG. A 13 V output from the on-chip charge pump, used
to power the low-side gate drive circuit directly, provides the
current to charge the bootstrap capacitors for the high-side
gate drive.
The VREG capacitor, CREG, must supply the instantaneous
current to the gate of the low-side MOSFET. A 10 μF, 25 V
capacitor should be adequate. This capacitor can be either
electrolytic or ceramic (X7R).
Diagnostics and Protection. The fault output pin,
~FAULT, goes low (i.e., FAULT = 1) when the RESET line
is high and any of the following conditions are present:
• Undervoltage conditions on VREG (UVREG) or on the
internal logic supply VREF (UVREF). These conditions
set a latched fault.
• A junction temperature > 170°C (OVERTEMP). This condition sets a latched fault.
• An undervoltage on the stored charge of the BOOT capacitor (UVBOOT). This condition does NOT set a latched
fault.
An overtemperature event signals a latched fault, but does
not disable any output drivers, regulators, or logic inputs.
The user must turn off the A3946 (e.g., force the RESET line
low) to prevent damage.
The power FETs are protected from inadequate gate drive
voltage by undervoltage detectors. Either of the regulator
undervoltage faults (UVREG or UVREF) disable both output
drivers until both voltages have been restored. The high-side
driver is also disabled during a UVBOOT fault condition.
Under many operating conditions, both the high-side (GH)
and low-side (GL) drivers may be off, allowing the BOOT
capacitor to discharge (or never become charged) and create
a UVBOOT fault condition, which in turn inhibits the highside driver and creates a FAULT = 1. This fault is NOT
latched. To remove this fault, momentarily turn on GL to
charge the BOOT capacitor.
Latched faults may be cleared by a low pulse, 1 to 10 μs
wide, on the RESET line. Throughout that pulse (despite
a possible UVBOOT), FAULT = 0; also the fault latch is
cleared immediately, and remains cleared. If the power is
restored (no UVREG or UVREF), and if no OVERTEMP
fault exists, then the latched fault remains cleared when the
RESET line returns to high. However, FAULT = 1 may still
occur because a UVBOOT fault condition may still exist.
Charge Pump. The A3946 is designed to accommodate
a wide range of power supply voltages. The charge pump
output, VREG, is regulated to 13 V nominal.
In all modes, this regulator is current-limited. When VBB
< 8 V, the charge pump operates as a voltage doubler. When
8 V < VBB< 15 V, the charge pump operates as a voltage
doubler/PWM, current-controlled, voltage regulator. When
VBB>15 V, the charge pump operates as a PWM, current-controlled, voltage regulator. Efficiency shifts, from 80% at VBB=
7 V, to 20% at VBB = 50 V.
CAUTION. Although simple paralleling of VREG supplies
from several A3946s may appear to work correctly, such a
configuration is NOT recommended. There is no assurance
that one of the regulators will not dominate, taking on all of
the load and back-biasing the other regulators. (For example,
this could occur if a particular regulator has an internal reference voltage that is higher that those of the other regulators,
which would force it to regulate at the highest voltage.)
Sleep Mode/Power Up. In Sleep Mode, all circuits are
disabled in order to draw minimum current from VBB. When
powering up and leaving Sleep Mode (the RESET line is
high), the gate drive outputs stay disabled and a fault remains
asserted until VREF and VREG pass their undervoltage
thresholds. When powering up, before starting the first bootstrap charge cycle, wait until t = CREG ⁄ 4 (where CREG is in
μF, and t is in ns) to allow the charge pump to stabilize.
When powered-up (not in Sleep Mode), if the RESET line
is low for > 10 μs, the A3946 may start to enter Sleep Mode
(VREF < 4 V). In that case, ~FAULT = 1 as long as the RESET
line remains low.
If the RESET line is open, the A3946 should go into Sleep
Mode. However, to ensure that this occurs, the RESET line
must be grounded.
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3946
Half-Bridge Power MOSFET Controller
Dead Time. The analog input pin DT sets the delay to turn
on the high- or low-side gate outputs. When instructed to
turn off, the gate outputs change after an short internal propagation delay (90 ns typical). The dead time controls the time
between this turn-off and the turn-on of the appropriate gate.
The duration, tDEAD, can be adjusted within the range 350 ns
to 6000 ns using the following formula:
tDEAD = 50 + (RDEAD ⁄ 16.7 )
where tDEAD is in ns, and RDEAD is in Ω, and should be in the
range 5 kΩ < RDEAD < 100 kΩ.
Do not ground the DT pin. If the DT pin is left open, dead
time defaults to 12 μs.
Control Logic. Two different methods of control are
possible with the A3946. When a resistor is connected from
DT to ground, a single-pin PWM scheme is utilized by shorting IN1 with IN2. If a very slow turn-on is required (greater
than 6 μs), the two input pins can be hooked-up individually
to allow the dead times to be as long as needed.
The dead time circuit can be disabled by tying the DT pin
to VREF. This disables the turn-on delay and allows direct
control of each MOSFET gate via two control lines. This is
shown in the Control Logic table, on page 2.
Top-Off Charge Pump. An internal charge pump allows
100% duty cycle operation of the high-side MOSFET. This is
a low-current trickle charge pump, and is only operated after
a high-side has been signaled to turn on. A small amount
of bias current (< 200 μA) is drawn from the BOOT pin
to operate the floating high-side circuit. The charge pump
simply provides enough drive to ensure that the gate voltage
does not droop due to this bias supply current. The charge
required for initial turn-on of the high-side gate must be supplied by bootstrap capacitor charge cycles. This is described
in the section Application Information.
VREF. VREF is used for the internal logic circuitry and
is not intended as an external power supply. However,
the VREF pin can source up to 4 mA of current. A 0.1 μF
capacitor is needed for decoupling.
Fault Response Table
Fault Mode
No Fault
BOOT Capacitor Undervoltage
Thermal Shutdown
Sleep
5
3
~FAULT
VREG
VREF
GH1
GL1
1
1
ON
ON
(IL)
(IL)
1
0
ON
ON
0
(IL)
3
1
0
ON
ON
0
0
4
1
0
OFF
ON
0
0
1
0
ON
ON
(IL)
(IL)
0
1
OFF
OFF
High Z
High Z
VREG Undervoltage
VREF Undervoltage
RESET
2
(IL) indicates that the state is determined by the input logic.
2
This fault occurs whenever there is an undervoltage on the BOOT capacitor. This fault is not latched.
3
These faults are latched. Clear by pulsing RESET = 0.
4
Unspecified VREF undervoltage threshold < 4 V.
5
During power supply undervoltage conditions, GH and GL are instructed to be 0 (low). However, with VREG < 4 V, the outputs start to become high impedance (High Z). Refer to the section Sleep Mode/Power Up.
1
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6
3946
Half-Bridge Power MOSFET Controller
Application Information
Bootstrap Capacitor Selection. CBOOT must be correctly selected to ensure proper operation of the device. If
too large, time is wasted charging the capacitor, with the
result being a limit on the maximum duty cycle and PWM
frequency. If the capacitor is too small, the voltage drop can
be too large at the time the charge is transferred from the
CBOOT to the MOSFET gate.
To keep the voltage drop small:
At power-up and when the drivers have been disabled for
a long time, the bootstrap capacitor can be completely
discharged. In this case, Delta_v can be considered to be the
full high-side drive voltage, 12 V. Otherwise, Delta_v is the
amount of voltage dropped during the charge transfer, which
should be 400 mV or less. The capacitor is charged whenever
the S pin is pulled low, via a GL PWM cycle, and current
flows from VREG through the internal bootstrap diode
circuit to CBOOT.
QBOOT >> QGATE
where a factor in the range of 10 to 20 is reasonable. Using
20 as the factor:
and
QBOOT = CBOOT × VBOOT = QGATE × 20
CBOOT = QGATE × 20 / VBOOT
The voltage drop on the BOOT pin, as the MOSFET is being
turned on, can be approximated by:
Power Dissipation. For high ambient temperature
applications, there may be little margin for on-chip power
consumption. Careful attention should be paid to ensure that
the operating conditions allow the A3946 to remain in a safe
range of junction temperature.
The power consumed by the A3946 can be estimated as:
P_total = Pd_bias + Pd_cpump + Pd_switching_loss
where:
Delta_v = QGATE / CBOOT
For example, given a gate charge, QGATE, of 160 nC, and the
typical BOOT pin voltage of 12 V, the value of the Boot
capacitor, CBOOT, can be determined by:
Pd_bias = VBB × IVBB , typically 3 mA,
and
Pd_cpump = (2VBB – VREG) IAVE, for VBB < 15 V, or
CBOOT = (160 nC × 20) / 12 V ≈ 0.266 μF
Pd_cpump = (VBB – VREG) IAVE, for VBB > 15 V,
Therefore, a 0.22 μF ceramic (X7R) capacitor can be chosen
for the Boot capacitor.
in either case, where
In that case, the voltage drop on the BOOT pin, when the
high-side MOSFET is turned on, is:
and
IAVE = QGATE × 2 × fPWM
Pd_switching_loss = QGATE
Delta_v = 160 nC / 0.22 μF = 0.73 V
Bootstrap Charging. It is good practice to ensure that the
high-side bootstrap capacitor is completely charged before a
high-side PWM cycle is requested.
× VREG × 2 × fPWM Ratio,
where
Ratio = 10 Ω / (RGATE + 10 Ω).
The time required to charge the capacitor can be approximated by:
tCHARGE = CBOOT (Delta_v / 100 mA)
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3946
Half-Bridge Power MOSFET Controller
Application Block Diagrams
+VBAT
C1
0.47 μF
C2
10 μF
P
CP2
VREF
VREF
VREG
Charge
Pump
+5 Vref
10
kΩ
CP1
0.1 uF
ILIM
L
L
P
P
Charge
Pump
BOOT
~FAULT
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
CBOOT
0.47 μF
IRF2807
L
DT
RDEAD
15.8 kΩ
GH
High Side
Driver
Turn-On
Delay
RGATE
IN1
Control
Logic
S
VREG
Forward
IRF2807
L
IN
P
33 Ω
200
kΩ
L
IN
CREG
10 μF
IN2
GL
Low Side
Driver
Brake
RGATE
33 Ω
PGND
External
+5 V
L
RESET
M
LGND
P
L
L
DC
Motor
P
Diagram A. Dependent drivers. Unidirectional motor control with braking and dead time. TDEAD = 1 μs; QTOTAL = 160 nC.
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115 Northeast Cutoff, Box 15036
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3946
Half-Bridge Power MOSFET Controller
+VBAT
P
C1
0.47 μF
C2
10 μF
CP2
VREF
VREF
CP1
0.1 uF
10
kΩ
L
L
VREG
Charge
Pump
+5 Vref
P
CREG
P 10 μF
ILIM
P
Charge
Pump
BOOT
~FAULT
M
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
CBOOT
IRF2807
L
VREF
DT
GH RGATE
High Side
Driver
Turn-On
Delay
33 Ω
200
kΩ
DC Motor #1
IN1
Forward
Control
Logic
Slow
Decay
DC Motor #2
Forward
S
VREG
L
IRF2807
IN2
RGATE
GL
Slow
Decay
External
+5 V
DC Motor #2
0.47 μF
Low Side
Driver
33 Ω
PGND
L
RESET
M
LGND
P
L
L
200
kΩ
DC Motor #1
P
Diagram B. Independent drivers. One high-side drive and one low-side drive.
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
9
3946
Half-Bridge Power MOSFET Controller
+VBAT
C1
0.47 μF
C2
10 μF
P
P
CP2
VREF
VREF
CP1
0.1 uF
10
kΩ
ILIM
L
L
VREG
Charge
Pump
+5 Vref
P
P
Charge
Pump
DC Motor
#1
Bootstrap
UVLO
DT
Turn-On
Delay
RGATE
GH
High Side
Driver
33 Ω
200
kΩ
DC Motor #1
IN1
Forward
Control
Logic
Slow
Decay
S
P
VREG
DC Motor #2
Forward
IRF2807
L
IN2
RGATE
GL
Low Side
Driver
Slow
Decay
33 Ω
PGND
External
+5 V
DC Motor
#2
IRF2807
L
VREF
M
M
BOOT
~FAULT
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
CREG
10 μF
L
RESET
P
200
kΩ
LGND
L
L
P
Diagram C. Independent drivers. Two low-side drives.
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115 Northeast Cutoff, Box 15036
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10
3946
Half-Bridge Power MOSFET Controller
Pin Name
VREG
Pin Description
SOIC-16
(A3946KLB)
TSSOP-16
(A3946KLP)
Gate drive supply.
1
1
CP2
Charge pump capacitor, positive side. When not using the charge
pump, leave this pin open.
2
2
CP1
Charge pump capacitor, negative side. When not using the charge
pump, leave this pin open.
3
3
External ground. Internally connected to the power ground.
4
4
Low-side gate drive output for external MOSFET driver. External
series gate resistor can be used to control slew rate seen at the
power driver gate, thereby controlling the di/dt and dv/dt of the S
pin output.
5
5
S
Directly connected to the load terminal. The pin is also connected
to the negative side of the bootstrap capacitor and negative supply
connection for the floating high-side drive.
6
6
GH
High-side gate drive output for N-channel MOSFET driver. External
series gate resistor can be used to control slew rate seen at the
power driver gate, thereby controlling the di/dt and dv/dt of the S
pin output.
7
7
BOOT
High-side connection for bootstrap capacitor, positive supply for the
high-side gate drive.
8
8
Diagnostic output, open drain. Low during a fault condition.
9
9
IN1
Logic control.
10
10
IN2
Logic control.
11
11
RESET
Logic control input. When RESET = 0, the chip is in a very low
power sleep mode.
12
12
LGND*
External ground. Internally connected to the logic ground.
13
13
Dead Time. Connecting a resistor to GND sets the turn-on delay
to prevent shoot-through. Forcing this input high disables the dead
time circuit and changes the logic truth table.
14
14
5 V internal reference decoupling terminal.
15
15
Supply Input.
16
16
PGND*
GL
~FAULT
DT
VREF
VBB
*In the LB package, the PGND pin (4) and LGND pin (13) grounds are internally connected by the leadframe. In the LP package, however,
the PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally.
In the LP package, the exposed thermal pad is not connected to any pin, but should be externally connected to ground, to reduce noise
pickup by the pad.
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
11
3946
Half-Bridge Power MOSFET Controller
A3946KLB SOIC
.406 10.31
.398 10.11
8º
0º
16
.011 0.28
.009 0.23
.299 7.59
.291 7.39
.040 1.02
.020 0.51
.414 10.52
.398 10.11
1
.020 0.51
.014 0.36
2
.104 2.64
.096 2.44
.050 1.27
BSC
.026 0.66
REF
.012 0.30
.004 0.10
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
Webbed lead frame. Leads 4 and 13 are joined together within the device package.
A3946KLP TSSOP with Exposed Thermal Pad
5.1
4.9
0.201
0.193
8º
0º
16
0.20 0.008
0.09 0.004
4.5 0.177
4.3 0.169
A
6.6 0.260
6.2 0.244
3 0.118
BSC
1 0.039
REF
1
2
3 0.118
BSC
.75
.45
0.030
0.018
.25 0.010
BSC
Seating Plane
Gauge Plane
.30
.19
0.012
0.007
1.20 0.047
MAX
.65 .026
BSC
.15 0.006
.00 0.000
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
A Exposed thermal pad (bottom surface)
NOTES:
1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 49 devices or add “TR” to part number for tape and reel.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
12
3946
Half-Bridge Power MOSFET Controller
The products described here are manufactured under one or
more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical components in life-support devices or systems without express written
approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights
of third parties which may result from its use.
Copyright©2003, 2004 AllegroMicrosystems, Inc.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
13