CGS100P2530 PECL-TTL 1 to 10 Minimum Skew Clock Driver CGS100P2531 PECL-TTL 2 to 10 Minimum Skew Clock Driver General Description Features These minimum skew clock drivers are designed for Clock Generation & Support (CGS) applications, particularly for ECL to TTL clock tree distribution schemes. The ’2530 and ’2531 are single supply devices with guaranteed minimum output skew across the outputs of a given device. Skew parameters are also provided as a means to measure duty cycle requirements as those found in high speed clocking systems. The ’2530 is a minimum skew clock driver with one input driving ten outputs and the ’2531 is a selectable two input to 10 outputs, specifically designed for signal generation and clock distribution applications. Y Y Y Y Y Y Y Y Y Logic Symbols PECL-TTL version of National’s CGS74B2528 TTL clock drivers Clock Generation & Support (CGS) devices ideal for ECL and TTL clock trees with CGS 100311 1-to-10 or 2-to-10 low skew clock distribution 500 ps pin-to-pin output skew Specification for transition skew to meet duty cycle requirements 28-pin PCC to minimize high speed switching noise and for low dynamic power consumption Current sourcing 48 mA and current sinking of 64 mA Low dynamic power consumption above 20 MHz Guaranteed 4 kV ESD protection Connection Diagrams ’2530 Pin Assignment for LCC TL/F/10983 – 1 ’2531 TL/F/10983 – 3 TL/F/10983 – 2 TL/F/10983 – 4 C1995 National Semiconductor Corporation TL/F/10983 RRD-B30M115/Printed in U. S. A. CGS100P2530 PECL-TTL 1 to 10 Minimum Skew Clock Driver CGS100P2531 PECL-TTL 2 to 10 Minimum Skew Clock Driver September 1995 Pin Description Functional Description On the multiplexed clock device, the SEL pin is used to determine which CLKn will have an active effect on the outputs of the circuit. When SEL e 1, the CLK1 input is selected and when SEL e 0, the CLK0 input is selected. The nonselected CLKn input will not have any effect on the logical output level of the circuit. The output pins act as a single entity and will follow the state of the CLK, CLK1/CLK0 pins when either the multiplexed (’2531) or the straight (’2530) clock distribution chip is selected. Pin Names Description CLK CLK0, CLK1 O0 –O9 SEL PECL Differential Clock Input (’2530) PECL Differential Clock Input (’2531) TTL Outputs PECL Clock Select (’2531) Truth Tables ’2530 Inputs ’2531 Outputs Inputs Outputs CLK CLK O0 – O9 CLK0 CLK0 CLK1 CLK1 SEL O0 –O9 L H L H L H VBB H L L H VBB VBB X L H U U L* H* VBB L H L H L H X X X X X X H L L H VBB VBB X X X X X X X X X X X X L H L H L H X X X X X X H L L H VBB VBB L L L L L L H H H H H H L H U U L* H* L H U U L* H* Le He Xe Ue * e Low Logic Level High Logic Level Don’t Care Undefined Single Ended Operation ’2530 ’2531 TL/F/10983–5 TL/F/10983 – 6 2 Absolute Maximum Ratings (Note) Voltage Applied to Output (with VCC e 0V) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Maximum Junction Temperature Plastic VCC Pin Potential to Ground Pin ESD Last Passing Voltage (Min) 150§ C 2000V Recommended Operating Conditions b 0.5V to a 7.0V b 0.5V to a 7.0V TTL Input Voltage (Note 1) TTL Input Current (Note 1) VBB Output Current ECL Input Potential to GND Pin b 0.5V to VCC Twice the Rated IOL (mA) Current Applied to Output in Low State (Max) b 30 mA to a 5.0 mA Operating Free Air Temperature Range b 5.0 mA to a 1.0 mA Supply Voltage b 0.5V to VCC a 0.5V Note: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Typical iJA 0 LFM Airflow 225 LFM 500 LFM b 40§ C to a 85§ C 4.5V to 5.5V Note 1: Either voltage limit or current limit is sufficient to protect inputs. 69§ C/W 53§ C/W 45§ C/W DC Electrical Characteristics Over recommended operating conditions unless specified otherwise. All typical values are measured at VCC e 5V, TA e 25§ C. Symbol VOH Parameter Conditions High Level Output Voltage 2.4 IOH e 48 mA, VCC e 4.5V 2.0 VOL Low Level Output Voltage VCC e 4.5V, IOL e 64 mA VBB Output Reference Voltage IVBB e b1 mA VDIFF Input Voltage Differential Required for Full Output Swing VCM Common Mode Voltage High Level VIH Input High Voltage V 0.55 V VCC b 1.26 V 150 mV V Guarantee HIGH Signal for All Inputs VCC b 1.165 VCC b 0.87 V VCC b 1.83 VCC b 1.475 Guarantee LOW Signal for All Inputs Low Level Input Current VIN e VIL (min) IIH High Level Input Current VIN e VIH (max) ICBO Input Leakage Current VIN e 0 ICCH Supply Current VCC e 5.5V 0.50 V mA 50 b 10 mA mA 30 ’2531 mA 33 Output Current Drive VCC e 5.5V, VO e 2.25V Supply Current VCC e 5.5V ’2530 Units VCC b 0.4 Input Low Voltage ICCL Max VCC b 1.6 IIL IOS Typ 0.375 VCC b 1.38 VIL ’2530 Min IOH e b3 mA, VCC e 4.5V b 50 b 150 72 ’2531 75 3 mA mA AC Electrical Characteristics Over recommended operating conditions unless specified otherwise. All typical values are measured at VCC e 5V, TA e 25§ C. CGS100P Symbol VCC e 4.5V to 5.5V TA e b40§ C to a 85§ C CL e 50 pF RL e 500X Parameter Min Typ Units Max fMAX Frequency Maximum 70 MHz tPLH Low-to-High Propagation Delay CLKn to On (’2530) 3.4 5.0 7.0 ns tPHL High-to-Low Propagation Delay CLKn to On (’2530) 3.4 5.0 7.0 ns tPLH, tPHL Propagation Delay CLKn to On (’2531) 4.0 4.0 5.0 5.0 8.0 8.0 ns tPLH, tPHL Propagation Delay SEL to On (’2531) 5.0 5.0 5.0 5.0 10.0 10.0 ns Extended AC Electrical Characteristics Over recommended operating conditions unless specified otherwise. All typical values are measured at VCC e 5V, TA e 25§ C. CGS100P Symbol VCC e 4.5V to 5.5V TA e b40§ C to a 85§ C CL e 50 pF RL e 500X Parameter Min Units Typ Max tOSHL Maximum Skew Common Edge Output-to-Output Variation (Note 2) 150 500 ps tOSLH Maximum Skew Common Edge Output-to-Output Variation (Note 2) 150 500 ps tPS Maximum Skew Pin (Signal) Transition Variation (Note 2) 0.6 1.1 ns trise, tfall Rise/Fall Time (from 0.8V/2.0V to 2.0V/0.8V) 1.0 1.5 ns Note 2: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH) or in opposite directions both HL and LH (tOST). tOSHL and tOSLH are characterized and guaranteed by design @ 1 MHz. See Figures A and B of Parameter Measurement Information. 4 Timing Diagrams TL/F/10983 – 13 TL/F/10983 – 14 Test Circuit RL is 500X CL is 50 pF for all prop delays and skew measurements. TL/F/10983 – 15 Note 3: Refer to Test Philosophy and Definitions section for skew specifications. Note 4: Load capacitance includes the test jig. Ordering Information (contact NSC Marketing for specific date of availability) CGS 100 P 253x V Family Clock Generation & Support Packaging V-PCC Operating Temperature Range 100 e F 100K Device Type 2530 2531 Technology P e P-ECL 5 CGS100P2530 PECL-TTL 1 to 10 Minimum Skew Clock Driver CGS100P2531 PECL-TTL 2 to 10 Minimum Skew Clock Driver Physical Dimensions inches (millimeters) 28-Lead Plastic Chip Carrier (PCC) NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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