ALTERA FLEX6000

FLEX 6000
Programmable Logic
Device Family
®
March 2001, ver. 4.1
Data Sheet
%
Typical gates (1)
10,000
16,000
16,000
24,000
Logic elements (LEs)
880
1,320
1,320
1,960
Maximum I/O pins
102
204
171
218
3.3 V
5.0 V
3.3 V
3.3 V
Supply voltage (V CCINT)
Altera Corporation
1
FLEX 6000 Programmable Logic Device Family Data Sheet
EPF6010A
71
102
EPF6016
EPF6016A
EPF6024A
2
81
81
117
171
117
171
117
171
199
204
199
218
171
219
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
16-bit loadable counter
16
172
153
133
MHz
16-bit accumulator
16
172
153
133
MHz
24-bit accumulator
24
136
123
108
MHz
16-to-1 multiplexer (pin-to-pin) (1)
10
12.1
13.4
16.6
ns
592
84
67
58
MHz
16
16 multiplier with a 4-stage pipeline
Altera Corporation
3
FLEX 6000 Programmable Logic Device Family Data Sheet
8-bit, 16-tap parallel finite impulse response
(FIR) filter
599
94
80
72
MSPS
8-bit, 512-point fast Fourier transform (FFT)
function
1,182
75
63
89
53
109
43
S
MHz
universal asynchronous
receiver/transmitter (UART)
487
36
30
25
MHz
PCI bus target with zero wait states
609
56
49
42
MHz
4
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FLEX 6000 Programmable Logic Device Family Data Sheet
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5
FLEX 6000 Programmable Logic Device Family Data Sheet
6
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FLEX 6000 Programmable Logic Device Family Data Sheet
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7
FLEX 6000 Programmable Logic Device Family Data Sheet
Dedicated Inputs
4
LE 1
LABCTRL1/
SYNCLR
LABCTRL2
CLK1/SYNLOAD
8
CLK2
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
data1
data2
data3
data4
Look-Up
Table
(LUT)
Carry-In
Cascade-In
Carry
Chain
Cascade
Chain
D
PRN
Q
LE-Out
CLRN
labctrl1
labctrl2
Chip-Wide Reset
Clear/ Preset
Logic
Clock
Select
labctrl3
labctrl4
Carry-Out
Altera Corporation
Cascade-Out
9
FLEX 6000 Programmable Logic Device Family Data Sheet
10
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Carry-In
a1
LUT
s1
Register
b1
Carry Chain
LE 2
a2
LUT
Register
s2
b2
Carry Chain
LE 3
an
LUT
Register
sn
bn
Carry Chain
LE n + 1
LUT
Register
Carry-Out
Carry Chain
LE n + 2
Altera Corporation
11
FLEX 6000 Programmable Logic Device Family Data Sheet
12
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
LE 2
LE 2
d[3..0]
LUT
d[7..4]
LUT
d[(4 -1)..4( -1)]
LUT
d[3..0]
LUT
d[7..4]
LUT
d[(4 -1)..4( -1)]
LUT
LE 3
LE 3
LE + 1
Altera Corporation
LE
+1
13
FLEX 6000 Programmable Logic Device Family Data Sheet
Cascade-In
Carry-In
LE-Out
data1
data2
D
4-Input
LUT
data3
data4
PRN
Q
CLRN
Cascade-Out
Carry-In
Cascade-In
LE-Out
data1
data2
PRN
D
Q
3-Input
LUT
CLRN
3-Input
LUT
Cascade-Out
Carry-Out
Cascade-In
Carry-In
data1
data2
LAB-Wide
Synchronous
Load
3-Input
LUT
LAB-Wide Synchronous
Clear
D
PRN
Q
LE-Out
data3 (data)
CLRN
3-Input
LUT
Carry-Out
14
Cascade-Out
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FLEX 6000 Programmable Logic Device Family Data Sheet
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15
FLEX 6000 Programmable Logic Device Family Data Sheet
16
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
D
Q
CLRN
labctrl1 or
labctrl2
Chip-Wide Reset
D
PRN
Q
labctrl1 or
labctrl2
Chip-Wide Reset
Altera Corporation
17
FLEX 6000 Programmable Logic Device Family Data Sheet
2
2
5
5
22
10
5
5
22
10
2
2
20
5
5
20
5
5
5
5
5
5
10
10
To/From
Adjacent
LAB
5
10
10
10
5
10
10
10
LE 1
through
LE 5
5
10
10
5
10
5
10
18
LE 1
through
LE 5
LE 6
through
LE 10
10
5
10
LE 6
through
LE 10
10
10
To/From
Adjacent
LAB
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FLEX 6000 Programmable Logic Device Family Data Sheet
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19
FLEX 6000 Programmable Logic Device Family Data Sheet
LE
LE
20
From Adjacent
Local Interconnect
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FLEX 6000 Programmable Logic Device Family Data Sheet
Altera Corporation
EPF6010A
4
144
22
20
EPF6016
EPF6016A
6
144
22
20
EPF6024A
7
186
28
30
21
FLEX 6000 Programmable Logic Device Family Data Sheet
4
LAB C1
LAB D1
22
LAB
(Repeated
Across
Device)
LAB C22
LAB D22
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
To Row or Column Interconnect
Delay
Chip-Wide Output Enable
From LAB Local Interconnect
From LAB Local Interconnect
Slew-Rate
Control
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23
FLEX 6000 Programmable Logic Device Family Data Sheet
IOE
LAB
IOE
24
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FLEX 6000 Programmable Logic Device Family Data Sheet
IOE
IOE
LAB
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25
FLEX 6000 Programmable Logic Device Family Data Sheet
Printed Circuit Board
Designed for 256-Pin FineLine BGA Package
100-Pin
FineLine
BGA
100-Pin FineLine BGA Package
(Reduced I/O Count or
Logic Requirements)
256-Pin
FineLine
BGA
256-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
EPF6016A
EPF6024A
26
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Altera Corporation
3.3
2.5
3.3
3.3
5.0
3.3
5.0
5.0
(1)
27
FLEX 6000 Programmable Logic Device Family Data Sheet
SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test result at the input pins.
BYPASS
Places the 1-bit bypass register between the
and
pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation.
28
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
EPF6010A
522
EPF6016
621
EPF6016A
522
EPF6024A
666
TMS
TDI
t JCP
t JCH
t JCL
t JPSU
t JPH
TCK
tJPZX
t JPXZ
t JPCO
TDO
tJSSU
Signal
to Be
Captured
Signal
to Be
Driven
Altera Corporation
tJSZX
tJSH
tJSCO
tJSXZ
29
FLEX 6000 Programmable Logic Device Family Data Sheet
tJCP
clock period
100
ns
tJCH
clock high time
50
ns
tJCL
clock low time
50
ns
ns
tJPSU
JTAG port setup time
20
tJPH
JTAG port hold time
45
tJPCO
JTAG port clock-to-output
25
ns
tJPZX
JTAG port high impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high impedance
25
ns
ns
tJSSU
Capture register setup time
20
tJSH
Capture register hold time
45
ns
tJSCO
Update register clock-to-output
35
ns
tJSZX
Update register high impedance to valid
output
35
ns
tJSXZ
Update register valid output to high
impedance
35
ns
ns
%
464
(703
[521
VCC
)
Device
Output
250
(8.06 k )
[481
To Test
System
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
30
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
–2.0
7.0
V
–2.0
7.0
V
–25
25
mA
–65
150
°C
–65
135
°C
135
°C
4.75 (4.50)
5.25 (5.50)
V
Supply voltage for output buffers, (3), (4)
5.0-V operation
4.75 (4.50)
5.25 (5.50)
V
Supply voltage for output buffers, (3), (4)
3.3-V operation
3.00 (3.00)
3.60 (3.60)
V
–0.5
V CCINT + 0.5
V
0
V CCIO
V
0
85
°C
–40
100
°C
V CC
Supply voltage
VI
DC input voltage
With respect to ground (2)
I OUT
DC output current, per pin
T STG
Storage temperature
No bias
T AMB
Ambient temperature
Under bias
TJ
Junction temperature
PQFP, TQFP, and BGA packages
V CCINT
Supply voltage for internal logic
and input buffers
(3), (4)
V CCIO
VI
Input voltage
VO
Output voltage
TJ
Operating temperature
tR
Input rise time
40
ns
tF
Input fall time
40
ns
For commercial use
For industrial use
Altera Corporation
31
FLEX 6000 Programmable Logic Device Family Data Sheet
V IH
High-level input voltage
2.0
V CCINT + 0.5
V
V IL
Low-level input voltage
–0.5
0.8
V
V OH
5.0-V high-level TTL output
voltage
I OH = –8 mA DC, V CCIO = 4.75 V (7)
2.4
V
3.3-V high-level TTL output
voltage
I OH = –8 mA DC, V CCIO = 3.00 V (7)
2.4
V
3.3-V high-level CMOS output
voltage
I OH = –0.1 mA DC, V CCIO = 3.00 V (7)
V CCIO – 0.2
V
5.0-V low-level TTL output
voltage
I OL = 8 mA DC, V CCIO = 4.75 V (8)
0.45
V
3.3-V low-level TTL output
voltage
I OL = 8 mA DC, V CCIO = 3.00 V (8)
0.45
V
3.3-V low-level CMOS output
voltage
I OL = 0.1 mA DC, V CCIO = 3.00 V (8)
0.2
V
II
Input pin leakage current
V I = V CC or ground (8)
–10
10
µA
I OZ
Tri-stated I/O pin leakage current V O = V CC or ground (8)
–40
40
µA
I CC0
V CC supply current (standby)
5
mA
C IN
Input capacitance for I/O pin
V IN = 0 V, f = 1.0 MHz
8
pF
CINCLK
Input capacitance for dedicated input V IN = 0 V, f = 1.0 MHz
12
pF
C OUT
Output capacitance
8
pF
V OL
32
V I = ground, no load
V OUT = 0 V, f = 1.0 MHz
0.5
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
V CC
Supply voltage
VI
DC input voltage
With respect to ground (2)
–0.5
4.6
V
–2.0
5.75
V
mA
I OUT
DC output current, per pin
–25
25
T STG
Storage temperature
No bias
–65
150
°C
T AMB
Ambient temperature
Under bias
–65
135
°C
TJ
Junction temperature
PQFP, PLCC, and BGA packages
135
°C
V CCINT
Supply voltage for internal logic and (3), (4)
input buffers
3.00 (3.00)
3.60 (3.60)
V
V CCIO
Supply voltage for output buffers,
3.3-V operation
(3), (4)
3.00 (3.00)
3.60 (3.60)
V
Supply voltage for output buffers,
2.5-V operation
(3), (4)
2.30 (2.30)
2.70 (2.70)
V
VI
Input voltage
VO
Output voltage
TJ
Operating temperature
For commercial use
For industrial use
–0.5
5.75
V
0
V CCIO
V
0
85
°C
–40
100
°C
tR
Input rise time
40
ns
tF
Input fall time
40
ns
Altera Corporation
33
FLEX 6000 Programmable Logic Device Family Data Sheet
V IH
High-level input voltage
1.7
5.75
V
V IL
Low-level input voltage
–0.5
0.8
V
V OH
3.3-V high-level TTL output
voltage
I OH = –8 mA DC, V CCIO = 3.00 V (7)
3.3-V high-level CMOS output
voltage
2.5-V high-level output voltage
V OL
2.4
V
I OH = –0.1 mA DC, V CCIO = 3.00 V (7)
V CCIO – 0.2
V
I OH = –100 µA DC, V CCIO = 2.30 V (7)
2.1
V
I OH = –1 mA DC, V CCIO = 2.30 V (7)
2.0
V
I OH = –2 mA DC, V CCIO = 2.30 V (7)
1.7
V
3.3-V low-level TTL output
voltage
I OL = 8 mA DC, V CCIO = 3.00 V (8)
0.45
V
3.3-V low-level CMOS output
voltage
I OL = 0.1 mA DC, V CCIO = 3.00 V (8)
0.2
V
2.5-V low-level output voltage
I OL = 100 µA DC, V CCIO = 2.30 V (8)
0.2
V
I OL = 1 mA DC, V CCIO = 2.30 V (8)
0.4
V
I OL = 2 mA DC, V CCIO = 2.30 V (8)
0.7
V
10
µA
Input pin leakage current
I OZ
Tri-stated I/O pin leakage current V O = 5.3 V to ground (8)
I CC0
V CC supply current (standby)
C IN
Input capacitance for I/O pin
V IN = 0 V, f = 1.0 MHz
8
pF
CINCLK
Input capacitance for dedicated input V IN = 0 V, f = 1.0 MHz
12
pF
C OUT
Output capacitance
8
pF
34
V I = 5.3 V to ground (8)
–10
II
V I = ground, no load
V OUT = 0 V, f = 1.0 MHz
–10
0.5
10
µA
5
mA
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
EPF6010A
EPF6016A
EPF6010A
EPF6016A
VCCINT = 3.3 V
VCCIO = 3.3 V
Room Temperature
100
75
Typical IO
Output
Current (mA)
VCCINT = 3.3 V
VCCIO = 2.5 V
Room Temperature
100
75
Typical IO
Output
Current (mA)
IOL
50
IOL
50
IOH
IOH
25
25
1
2
3
4
5
1
VO Output Voltage (V)
2
EPF6016
4
5
EPF6016
150
150
IOL
IOL
120
120
90
Typical IO
Output
Current (mA)
90
Typical IO
Output
Current (mA)
VCCINT = 5.0 V
VCCIO = 5.0 V
Room Temperature
60
1
2
VCCINT = 5.0 V
VCCIO = 3.3 V
Room Temperature
60
IOH
IOH
30
30
3
4
1
5
2
3 3.3
4
5
VO Output Voltage (V)
VO Output Voltage (V)
EPF6024A
EPF6024A
100
100
VCCINT = 3.3 V
VCCIO = 3.3 V
Room Temperature
75
Typical IO
Output
Current (mA)
VCCINT = 3.3 V
VCCIO = 2.5 V
Room Temperature
75
Typical IO
Output
Current (mA)
IOL
50
IOL
50
25
25
IOH
1
2
3
IOH
4
VO Output Voltage (V)
Altera Corporation
3
VO Output Voltage (V)
5
1
2
3
4
5
VO Output Voltage (V)
35
FLEX 6000 Programmable Logic Device Family Data Sheet
36
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Carry-In from
Previous LE
Cascade-In from
Previous LE
LE
Carry-out to Carry-out to
Next LE in Next LE in
Same LAB Next LAB
Cascade-out Cascade-out
to Next LE in to Next LE in
Same LAB
Next LAB
I/O Pin
IOE
Altera Corporation
37
FLEX 6000 Programmable Logic Device Family Data Sheet
tREG_TO_REG
LUT delay for LE register feedback in carry chain
tCASC_TO_REG
Cascade-in to register delay
tCARRY_TO_REG
Carry-in to register delay
tDATA_TO_REG
LE input to register delay
tCASC_TO_OUT
Cascade-in to LE output delay
tCARRY_TO_OUT
Carry-in to LE output delay
tDATA_TO_OUT
LE input to LE output delay
tREG_TO_OUT
Register output to LE output delay
tSU
LE register setup time before clock; LE register recovery time after
asynchronous clear
tH
LE register hold time after clock
tCO
LE register clock-to-output delay
tCLR
LE register clear delay
tC
LE register control signal delay
tLD_CLR
Synchronous load or clear delay in counter mode
tCARRY_TO_CARRY Carry-in to carry-out delay
tREG_TO_CARRY
Register output to carry-out delay
tDATA_TO_CARRY
LE input to carry-out delay
tCARRY_TO_CASC
Carry-in to cascade-out delay
tCASC_TO_CASC
Cascade-in to cascade-out delay
tREG_TO_CASC
Register-out to cascade-out delay
tDATA_TO_CASC
LE input to cascade-out delay
tCH
LE register clock high time
tCL
LE register clock low time
38
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
tOD1
Output buffer and pad delay, slow slew rate = off, VCCIO = VCCINT
C1 = 35 pF (2)
tOD2
Output buffer and pad delay, slow slew rate = off, VCCIO = low voltage
C1 = 35 pF (3)
tOD3
Output buffer and pad delay, slow slew rate = on
C1 = 35 pF (4)
tXZ
Output buffer disable delay
C1 = 5 pF
tZX1
Output buffer enable delay, slow slew rate = off, VCCIO = VCCINT
C1 = 35 pF (2)
tZX2
Output buffer enable delay, slow slew rate = off, VCCIO = low voltage
C1 = 35 pF (3)
tZX3
IOE output buffer enable delay, slow slew rate = on
C1 = 35 pF (4)
tIOE
Output enable control delay
tIN
Input pad and buffer to FastTrack Interconnect delay
tIN_DELAY
Input pad and buffer to FastTrack Interconnect delay with additional delay
turned on
tLOCAL
LAB local interconnect delay
tROW
Row interconnect routing delay
(5)
tCOL
Column interconnect routing delay
(5)
tDIN_D
Dedicated input to LE data delay
(5)
tDIN_C
Dedicated input to LE control delay
tLEGLOBAL
LE output to LE control via internally-generated global signal delay
tLABCARRY
Routing delay for the carry-out of an LE driving the carry-in signal of a
different LE in a different LAB
tLABCASC
Routing delay for the cascade-out signal of an LE driving the cascade-in
signal of a different LE in a different LAB
t1
Register-to-register test pattern
(6)
tDRR
Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local
interconnects
(7)
Altera Corporation
(5)
39
FLEX 6000 Programmable Logic Device Family Data Sheet
tINSU
Setup time with global clock at LE register
(8)
tINH
Hold time with global clock at LE register
(8)
tOUTCO
Clock-to-output delay with global clock with LE register using FastFLEX I/O
pin
(8)
%
%
%
%
REG_TO_REG
1.2
1.3
1.7
ns
CASC_TO_REG
0.9
1.0
1.2
ns
CARRY_TO_REG
0.9
1.0
1.2
ns
DATA_TO_REG
1.1
1.2
1.5
ns
CASC_TO_OUT
1.3
1.4
1.8
ns
CARRY_TO_OUT
1.6
1.8
2.3
ns
DATA_TO_OUT
1.7
2.0
2.5
ns
0.5
ns
0.4
REG_TO_OUT
0.4
SU
0.9
1.0
1.3
ns
H
1.4
1.7
2.1
ns
40
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
CO
0.3
0.4
0.4
ns
CLR
0.4
0.4
0.5
ns
C
1.8
2.1
2.6
ns
LD_CLR
1.8
2.1
2.6
ns
CARRY_TO_CARRY
0.1
0.1
0.1
ns
REG_TO_CARRY
1.6
1.9
2.3
ns
DATA_TO_CARRY
2.1
2.5
3.0
ns
CARRY_TO_CASC
1.0
1.1
1.4
ns
CASC_TO_CASC
0.5
0.6
0.7
ns
REG_TO_CASC
1.4
1.7
2.1
ns
DATA_TO_CASC
1.1
1.2
1.5
ns
CH
2.5
3.0
3.5
ns
CL
2.5
3.0
3.5
ns
OD1
1.9
2.2
2.7
ns
OD2
4.1
4.8
5.8
ns
OD3
5.8
6.8
8.3
ns
XZ
1.4
1.7
2.1
ns
XZ1
1.4
1.7
2.1
ns
XZ2
3.6
4.3
5.2
ns
XZ3
5.3
6.3
7.7
ns
IOE
0.5
0.6
0.7
ns
IN
3.6
4.1
5.1
ns
IN_DELAY
4.8
5.4
6.7
ns
Altera Corporation
41
FLEX 6000 Programmable Logic Device Family Data Sheet
LOCAL
0.7
0.7
1.0
ns
ROW
2.9
3.2
3.2
ns
COL
1.2
1.3
1.4
ns
DIN_D
5.4
5.7
6.4
ns
DIN_C
4.3
5.0
6.1
ns
LEGLOBAL
2.6
3.0
3.7
ns
LABCARRY
0.7
0.8
0.9
ns
LABCASC
1.3
1.4
1.8
ns
t1
EPF6010A
37.6
43.6
53.7
ns
EPF6016A
38.0
44.0
54.1
ns
tINSU
2.1 (1)
2.4 (1)
3.3 (1)
tINH
0.2 (2)
0.3 (2)
0.1 (2)
tOUTCO
2.0
42
7.1
2.0
8.2
2.0
ns
ns
10.1
ns
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
tREG_TO_REG
2.2
2.8
ns
tCASC_TO_REG
0.9
1.2
ns
tCARRY_TO_REG
1.6
2.1
ns
tDATA_TO_REG
2.4
3.0
ns
tCASC_TO_OUT
1.3
1.7
ns
tCARRY_TO_OUT
2.4
3.0
ns
tDATA_TO_OUT
2.7
3.4
ns
tREG_TO_OUT
0.3
0.5
ns
tSU
1.1
1.6
tH
1.8
2.3
ns
ns
tCO
0.3
0.4
ns
tCLR
0.5
0.6
ns
tC
1.2
1.5
ns
tLD_CLR
1.2
1.5
ns
tCARRY_TO_CARRY
0.2
0.4
ns
tREG_TO_CARRY
0.8
1.1
ns
tDATA_TO_CARRY
1.7
2.2
ns
tCARRY_TO_CASC
1.7
2.2
ns
tCASC_TO_CASC
0.9
1.2
ns
tREG_TO_CASC
1.6
2.0
ns
tDATA_TO_CASC
1.7
2.1
ns
tCH
4.0
4.0
ns
tCL
4.0
4.0
ns
tOD1
2.3
2.8
ns
tOD2
4.6
5.1
ns
Altera Corporation
43
FLEX 6000 Programmable Logic Device Family Data Sheet
tOD3
4.7
5.2
tXZ
2.3
2.8
ns
tZX1
2.3
2.8
ns
tZX2
4.6
5.1
ns
tZX3
4.7
5.2
ns
tIOE
0.5
0.6
ns
tIN
3.3
4.0
ns
tIN_DELAY
4.6
5.6
ns
tLOCAL
0.8
1.0
ns
tROW
2.9
3.3
ns
tCOL
2.3
2.5
ns
tDIN_D
4.9
6.0
ns
tDIN_C
4.8
6.0
ns
tLEGLOBAL
3.1
3.9
ns
tLABCARRY
0.4
0.5
ns
tLABCASC
0.8
1.0
ns
t1
53.0
65.0
ns
tDRR
16.0
20.0
ns
44
ns
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
tINSU
3.2
4.1
ns
tINH
0.0
0.0
ns
tOUTCO
2.0
7.9
2.0
9.9
ns
tREG_TO_REG
1.2
1.3
1.6
tCASC_TO_REG
0.7
0.8
1.0
ns
ns
tCARRY_TO_REG
1.6
1.8
2.2
ns
tDATA_TO_REG
1.3
1.4
1.7
ns
tCASC_TO_OUT
1.2
1.3
1.6
ns
tCARRY_TO_OUT
2.0
2.2
2.6
ns
tDATA_TO_OUT
1.8
2.1
2.6
ns
tREG_TO_OUT
0.3
0.3
0.4
ns
tSU
0.9
1.0
1.2
ns
tH
1.3
1.4
1.7
ns
tCO
0.2
0.3
0.3
ns
tCLR
0.3
0.3
0.4
ns
tC
1.9
2.1
2.5
ns
tLD_CLR
1.9
2.1
2.5
ns
tCARRY_TO_CARRY
0.2
0.2
0.3
ns
tREG_TO_CARRY
1.4
1.6
1.9
ns
tDATA_TO_CARRY
1.3
1.4
1.7
ns
tCARRY_TO_CASC
1.1
1.2
1.4
ns
tCASC_TO_CASC
0.7
0.8
1.0
ns
tREG_TO_CASC
1.4
1.6
1.9
ns
tDATA_TO_CASC
1.0
1.1
1.3
ns
tCH
2.5
3.0
3.5
ns
tCL
2.5
3.0
3.5
ns
Altera Corporation
45
FLEX 6000 Programmable Logic Device Family Data Sheet
tOD1
1.9
2.1
2.5
ns
tOD2
4.0
4.4
5.3
ns
tOD3
7.0
7.8
9.3
ns
tXZ
4.3
4.8
5.8
ns
tXZ1
4.3
4.8
5.8
ns
tXZ2
6.4
7.1
8.6
ns
tXZ3
9.4
10.5
12.6
ns
tIOE
0.5
0.6
0.7
ns
tIN
3.3
3.7
4.4
ns
tIN_DELAY
5.3
5.9
7.0
ns
tLOCAL
0.8
0.8
1.1
ns
tROW
3.0
3.1
3.3
ns
tCOL
3.0
3.2
3.4
ns
tDIN_D
5.4
5.6
6.2
ns
tDIN_C
4.6
5.1
6.1
ns
tLEGLOBAL
3.1
3.5
4.3
ns
tLABCARRY
0.6
0.7
0.8
ns
tLABCASC
0.3
0.3
0.4
ns
45.0
50.0
60.0
ns
46
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
tINSU
2.0 (1)
2.2 (1)
2.6 (1)
tINH
0.2 (2)
0.2 (2)
0.3 (2)
tOUTCO
2.0
7.4
2.0
8.2
2.0
ns
ns
9.9
ns
----------------------------
Altera Corporation
EPF6010A
14
EPF6016
88
EPF6016A
14
EPF6024A
14
47
FLEX 6000 Programmable Logic Device Family Data Sheet
48
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
1000
200
800
150
ICC Supply
Current
100
(mA)
ICC Supply
Current
(mA)
600
400
50
200
0
50
0
100
Frequency (MHz)
30
60
Frequency (MHz)
250
400
200
300
ICC Supply 150
Current
(mA)
ICC Supply
Current
(mA)
100
200
100
50
0
50
Frequency (MHz)
Altera Corporation
100
0
50
100
Frequency (MHz)
49
FLEX 6000 Programmable Logic Device Family Data Sheet
Configuration device
EPC1 or EPC1441 configuration device
Passive serial (PS)
BitBlaster TM, ByteBlasterMVTM, or MasterBlaster TM
download cables, or serial data source
Passive serial asynchronous BitBlaster, ByteBlasterMV, or MasterBlaster
(PSA)
download cables, or serial data source
50
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Altera Corporation
51
FLEX 6000 Programmable Logic Device Family Data Sheet
®
52
Altera Corporation
Printed on Recycled Paper.