AMCC S5933

S5933
32-Bit PCI “MatchMaker”
February 12, 1997 Revised October 1998
FEATURES
APPLICATIONS
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PCI 2.1 Compliant Master/Slave Device
Full 132 Mbytes/sec Transfer Rate
PCI Bus Operation DC to 33 Mhz
8/16/32 Bit Add-On User Bus
Four Definable Pass-Thru Regions
Two 32 Byte FIFOs
Sync/Async Add-On Bus Operation
Mail Box Registers w/Byte Level Status
Direct Mail Box Data Strobe/Interrupts
Big/Little Endian Conversions
Direct PCI & Add-On Interrupt Pins
Boot Loading from nvRAM or Byte Wide
Optional Expansion BIOS/POST Code
160 Pin PQFP
High Speed Networking
Digital Video Applications
I/O Communications Ports
High Speed Data Input/Output
Multimedia Communications
Memory Interfaces
High Speed Data Acquisition
Data Encryption/Decryption
Intel i960 Interface
General Purpose PCI Interfacing
DESCRIPTION
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing
system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places
them closer to the system’s processor bus, providing faster data transfer between the processor and peripherals. The PCI
Local bus also addresses the industry’s need for a standard that is not directly dependent on the speed, size and type of
processor bus. It represents the first microprocessor independent bus offering performance more than adequate for the
most demanding applications, such as full-motion video.
Applied Micro Circuits Corporation (AMCC), the premier supplier of single chip solutions, has developed and produced the S5933 to solve the problem of interfacing applications to the PCI Local bus. The S5933, or ‘Matchmaker’, is
a powerful and flexible PCI controller supporting several levels of interface sophistication. At the lowest level, it can
serve simply as a PCI bus Target with modest transfer requirements. For high-performance applications, the S5933 can
become a Bus Master to attain the PCI Local bus peak transfer capability of 132 MBytes/sec.
The MatchMaker is an off-the-shelf, low-cost, standard product, which is PCI 2.1 compliant. And, since AMCC is a
member of the PCI Special Interest Group, the S5933 has been tested in "compliance workshops" along with other manufacturer's PCI systems, chip sets and BIOSs. This removes the burden of compliance testing from the designer and thus
significantly reduces development time. Utilizing the S5933 allows the designer to focus on the actual application, not
debugging the PCI interface.
The MatchMaker allows special direct data accessing between the PCI bus and the user application through implementation of four definable Pass-Thru data channels. Each data channel is implemented by defining a Host memory segment
size and 8/16/32-bit user bus width. The addition of two 32 byte FIFOs, also used in S5933 Bus Mastering applications,
provides further versatility to data transfer capabilities. FIFO DMA transfers are supported using Address and Transfer
Count Registers. Four 32-bit Mailbox Registers coupled with a Status Register and extensive interrupt capabilities provide flexible user command or message transfers between the two buses. In addition, the S5933 also allows use of an
external serial, or byte-wide non-volatile memory to perform any pre-boot initialization requirements and to provide
custom expansion BIOS or POST code capability.
6290 Sequence Drive, San Diego, California 92121-4358
800-755-2622 Fax: 619-450-9885
http://www.amcc.com
S5933
PCI Local Bus
32-Bit PCI “MatchMaker”
2.1 PCI Local Bus
Interface Logic
S5933
User
Application
Pass-Thru Data &
Address Registers
I/O Audio
Bus Master Transfer
Count & Address
Registers
FIFOs
AMCC
Add-On
Local Bus
Interface Logic
Mailboxes
Mux/Demux
Configuration
Registers
Buffers
Mux/Demux
ISDN
FDDI
ATM
Graphics/
MPEG/
Grabber
Buffers
Read/Write
Control
Proprietary
Backplane
Satellite
Receiver/
Modem
Status Registers
Serial/Parallel nvRAM
Configuration Space
Expansion BIOS
Figure 1
S5933 Architecture
The block diagram in figure 1 above shows the
major functional elements within the S5933. The
S5933 provides three physical bus interfaces: the
PCI Local bus, the user local bus referred to as the
Add-On Local bus and the optional serial and bytewide non-volatile memory buses. Data movement
between buses can take place through mailbox registers or the FIFO data channel, or a user can define
and enable one or more of the four Pass-Thru data
channels. S5933 Bus Master or DMA data transfers
to and from the PCI Local bus are performed
through the FIFO data channel under either Host or
Add-On software control or Add-On hardware control using dedicated S5933 signal pins.
The S5933 signal pins are shown in Figure 2 right.
The PCI Local Bus signals are detailed on the left
side; Add-On Local Bus signal are detailed on the
right side. All additional S5933 device control signals are shown on the lower right side.
PCLK
INTA#
RST#
S5933
BPCLK
IRQ#
SYSRST#
AD[31:0]
DQ[31:0]
C/BE[3:0]#
PCI
Local
Bus
REQ#
GNT#
FRAME#
DEVSEL#
IRDY#
TRDY#
IDSEL#
STOP#
LOCK#
PAR
PERR#
SERR#
S5933
Control
MODE
FLT#
SNV
The S5933 supports a two wire serial nvRAM bus
and a byte-wide EPROM/FLASH bus. This allows
the designer to customize the S5933 configuration
by loading setup information on system power-up.
Add-On Bus
Control
Add-On
Data Bus
SELECT#
ADR[6:2]
BE[3:0]#
RD#
WR#
S5933 Register
Access
PTATN#
PTBURST#
PTNUM[1:0]#
PTBE[3:0]#
PTADR#
PTWR
PTRDY#
Pass-Thru
Control/Access
RDFIFO#
WRFIFO#
RDEMPTY
WRFULL
Direct FIFO
Access
EA[15:0]
EQ[7:0]
Byte Wide
Config/BIOS Opt.
EWR#/SDA
ERD#/SCL
Serial Bus
Config/BIOS Opt.
Figure 2
S5933 Register Architecture
Control and configuration of the Add-On Local bus, and the MatchMaker itself, is performed through three primary
groups of registers. These groups consist of PCI Configuration Registers, PCI Operation Registers and Add-On Operation Registers. All these registers are user configurable through their associated bus or from an external non-volatile
memory device. This section will provide a brief overview of each of these register groups and the optional non-volatile interface.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
2
S5933
32-Bit PCI “MatchMaker”
PCI Configuration Registers
All PCI compliant devices are required to provide a group of Configuration Registers for the
host system. These registers are polled during
power up initialization and contain specific
device and add-in card product information
including Vendor ID, Device ID, Revision and
the amount of memory required for product
operation. The S5933 can either load these registers with default values or initialize them from
an external non-volatile memory area called
'Configuration Space'. The S5933 can accommodate a total of 256 bytes of external memory
for this purpose. The first 64 bytes is reserved
for user defined configuration data which is
loaded into the PCI Configuration Registers
during power-up initialization. The remaining
192 bytes may be used to implement an Expansion BIOS or contain add-in card POST code.
Table 1 shows all the S5933 PCI Configuration
Registers.
PCI Operation Registers
Byte 3
Byte 2
Byte 1
Byte 0
Vendor ID
00h
PCI Status
PCI Command
04h
Class Code
Built-In Self Test
Max. Latency
Address
Device ID
Header Type
Latency Timer
Revision ID
08h
CacheLine Size
0Ch
Base Address Register 0
10h
Base Address Register 1
14h
Base Address Register 2
18h
Base Address Register 3
1Ch
Base Address Register 4
20h
Base Address Register 5
24h
Reserved Space
28h
Reserved Space
2Ch
Expansion ROM Base Address
30h
Reserved Space
34h
Reserved Space
38h
Min. Grant
Interrupt Pin
Interrupt Line
3Ch
The second group of registers are the PCI OperTable 1
ation Registers shown in Table 2. This group
consists of sixteen 32-bit (DWORD) registers
accessible to the Host processor from the PCI Local bus. These are the main registers through which the PCI Host
configures S5933 operation and communicates with the Add-On Local bus. These registers encompass the PCI bus
incoming and outgoing Mailboxes, FIFO data channel, Bus
Master Address and Count registers, Pass-Thru data channel
Address
PCI Operation Registers
registers and S5933 device Status and Control registers.
Offset
Outgoing Mailbox Register 1 (OMB1)
00h
Outgoing Mailbox Register 2 (OMB2)
04h
Outgoing Mailbox Register 3 (OMB3)
08h
Outgoing Mailbox Register 4 (OMB4)
0Ch
Incoming Mailbox Register 1 (IMB1)
10h
Incoming Mailbox Register 2 (IMB2)
14h
Add-On Bus Operation Registers
Incoming Mailbox Register 3 (IMB3)
18h
Incoming Mailbox Register 4 (IMB4)
1Ch
FIFO Register Port (bidirectional) (FIFO)
20h
Master Write Address Register (MWAR)
24h
Master Write Transfer Count Register (MWTC)
28h
Master Read Address Register (MRAR)
2Ch
Master Read Transfer Count Register (MRTC)
30h
Mailbox Empty/Full Status Register (MBEF)
34h
Non-Volatile Memory Interface
Interrupt Control/Status Register (INTCSR)
38h
Bus Master Control/Status Register (MCSR)
3Ch
Table 2
The third and last register group consists of the Add-On
Operation Registers, shown in Table 3. This group of eighteen 32-bit (DWORD) registers is accessible to the Add-On
Local bus. These are the main registers through which the
Add-On logic configures S5933 operation and communicates
with the PCI Local bus. These registers encompass the AddOn bus Mailboxes, Add-On FIFO, DMA Address/Count Registers (when Add-On initiated Bus Mastering), Pass-Thru
Registers and Status/Control registers.
The S5933 contains a set of PCI Configuration Registers.
These registers can be initialized with default values or with
designer specified values contained in an external nvRAM.
The nvRAM can be either a serial (2 Kbytes, maximum) or a
byte-wide device (64 Kbytes, maximum).
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
3
S5933
32-Bit PCI “MatchMaker”
The optional nvRAM allows the Add-On card manufacturer to initialize the S5933 with his specific Vendor ID
and Device ID numbers along with desired S5933 operation characteristics. The non-volatile memory feature
also provides for the Expansion BIOS and POST code
(power-on-self-test) options on the PCI bus.
Mailbox Operation
The Mailbox Registers are divided into two four
DWORD sets. Each set is dedicated to one bus for transferring data to the other bus. Figure 3 below shows a
block diagram of the mailbox section of the S5933. The
provision of Mailbox Registers provides an easy path for
the transfer of user information (command, status or
parametric data) between the two buses. An empty/full
indication for each Mailbox Register, at the byte level, is
determined by polling a Status Register accessible to
both the PCI and Add-On buses. Providing Mailbox byte
level empty/full indications allows for greater flexibility
in 8-, 16- or 32-bit system interfaces. i.e., transferring a
single byte to an 8-bit Add-On bus without requiring the
assembling or disassembling of 32-bit data.
Add-On Bus Operation Registers
Address
Incoming Mailbox Register 1 (AIMB1)
00h
Incoming Mailbox Register 2 (AIMB2)
04h
Incoming Mailbox Register 3 (AIMB3)
08h
Incoming Mailbox Register 4 (AIMB4)
0Ch
Outgoing Mailbox Register 1 (AOMB1)
10h
Outgoing Mailbox Register 2 (AOMB2)
14h
Outgoing Mailbox Register 3 (AOMB3)
18h
Outgoing Mailbox Register 4 (AOMB4)
1Ch
FIFO Port (AFIFO)
20h
Bus Master Write Address Register (MWAR)
24h
Pass-Thru Address Register (APTA)
28h
Pass-Thru Data Register (APTD)
2Ch
Bus Master Read Address Register (MRAR)
30h
Maibox Empty/Full Status Register (AMBEF)
34h
Interrupt Control/Status Register (AINT)
38h
General Control/Status Register (ARCR)
3Ch
Bus Master Write Transfer Count (MWTC)
58h
Bus Master Read Transfer Count (MRTC)
5Ch
Table 3
The generation of interrupts from Mailbox Registers is
equivalent with the commonly known 'DOORBELL'
Add-On Local Bus
PCI Local Bus
interrupt technique. Bit locations
configured within the S5933’s OperS5933
ation Registers select a Mailbox and
Mailbox byte which is to generate an
PCI MB1
PCI MB2
PCI MB3
PCI MB4
interrupt when full or touched. A
Byte 0
Byte 0
Byte 0
Byte 0
mailbox interrupt control register is
PCI MB1
PCI MB2
PCI MB3
PCI MB4
Byte 1
Byte 1
Byte 1
Byte 1
then used to enable interrupt generaPCI MB1
PCI MB2
PCI MB3
PCI MB4
tion and to select if the interrupt is to
Byte 2
Byte 2
Byte 2
Byte 2
be generated on the PCI or Add-On
PCI MB1
PCI MB2
PCI MB3
PCI MB4
Local bus. PCI Local bus interrupts
Byte 3
Byte 3
Byte 3
Byte 3
may also be generated from direct
Add MB1
Add MB2
Add MB3
Add MB4
hardware interfacing due to a unique
Byte 0
Byte 0
Byte 0
Byte 0
AMCC feature. A dedicated MailAdd MB1
Add MB2
Add MB3
Add MB4
Byte 1
Byte 1
Byte 1
Byte 1
box byte of the S5933 is directly
Add MB1
Add MB2
Add MB3
Add MB4
accessible via a set of hardware
Byte 2
Byte 2
Byte 2
Byte 2
device signal pins. A single mailbox
Add MB1
Add MB2
Add MB3
Add MB4
load signal pin latches Add-On bus
Byte 3
Byte 3
Byte 3
Byte 3
data directly into the Mailbox initiatMailbox Status Register
ing a PCI bus interrupt if enabled.
The mailbox data may also be read
in a similar manner. This option is
shared with the byte wide non-volaFigure 3
tile memory signal pins. The S5933
must use the serial nvRAM option for the direct mailbox option signals to be available or they will be assigned to the
byte wide at power up.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
4
S5933
32-Bit PCI “MatchMaker”
Pass-Thru Operation
Address Latch
Add-On PassThru Address
Register
Add-On Pass-Thru Write Data
Add-On Local Bus
S5933
PCI Local Bus
Pass-Thru operation executes PCI bus cycles in real
time with the Add-On bus. This allows the PCI bus
to directly read or write to Add-On resources. The
S5933 allows the designer to declare up to four individual Pass-Thru Regions. Each region may be
defined as 8-, 16-, or 32-bits wide, mapped into host
memory or I/O space and may be up to 512MB bytes
in size. Figure 4 right shows a block diagram of the
S5933 Pass-Thru architecture.
Add-On Pass-Thru Read Data
Pass-Thru operations are performed in PCI target
only mode, making this data channel useful for converting existing ISA or EISA designs over to the fast
Figure 4
PCI architecture. The Pass-Thru data channel utilizes separate Add-On bus signal pins to reflect a
PCI bus read or write request. Add-On logic decodes these signals to determine if it must read or write data to the
S5933 to satisfy the request. Information decoded includes PCI request occurring, the byte lanes involved, the specific Pass-Thru region accessed and if the request is a burst or single-cycle access. All requested Pass-Thru address
and data information is passed via Add-On Operation Registers.
Pass-Thru operation supports single PCI data cycles and PCI data bursts. During PCI burst operations, the S5933 is
capable of transferring data at the full PCI bandwidth. Should slower Add-On logic be implemented, the S5933 automatically issues PCI bus waits or a Host retry indication until the requested transfer is satisfied.
FIFO PCI Bus Mastering Operation
FIFO PCI Bus Master data transfers are processed by one of two 8-DWORD FIFOs. The FIFO block diagram is
shown in Figure 5. The particular FIFO selected for a data transfer is dependent only on the direction of data flow and
is completely transparent to the user. Internal S5933 decode logic selects the FIFO that is dedicated to transferring
data to the other bus.
The way data is transferred by a FIFO, is determined by Operation and Configuration Registers contained within the
S5933. A FIFO may be configured for either PCI or Add-On initiated Bus Mastering with programmable byte
advance conditions, read vs. write priorities and Add-On bus widths. Advance conditions allow the FIFO to implement 8-, 16- or 32-bit bus widths. Configuring the S5933 for Bus Master operation enables separate address and data
count registers, which are loaded with the PCI memory address location and number of bytes to be read or written.
This is accomplished by either the Host CPU or Add-On logic. Data can be transferred between the two buses transparent to the PCI Host processor, however, the Add-On logic is required to service the S5933 Add-On Local bus. An
indication of transfer completion can be seen by polling a status register done bit or S5933 signal pin or enabling a
'transfer count = 0' interrupt to either bus.
Further FIFO configuration bits select 16, 32, or 64 bit Endian conversion options for incoming and outgoing data.
Endian conversion allows an Add-On processor and the host to transfer data in their native Endian format. Other configuration bits determine if the Add-On Local bus width is 8, 16 or 32 bits. 16-bit bus configurations internally steer
FIFO data from the upper 16 bits of the DWORD and then to the lower 16-bits on alternate accesses. FIFO pointers
are then updated when appropriate bytes are accessed. Other methods are available for 8-bit or 16-bit Add-Ons.
Efficient FIFO management configuration schemes unique to the AMCC S5933 specify how full or empty a FIFO
must be before it requests the PCI Local bus. These criteria include bus requests when any of the 8 DWORDs are
empty, or when four or more DWORDs are empty. This allows the designer to control how often the S5933 requests
the bus. The S5933 always attempts to perform burst operations to empty or fill the FIFOs. Further FIFO capabilities
over the standard register access methods allow for direct hardware FIFO access. This is provided through separate
access pins on the S5933. Other status output pins allow for easily cascading external FIFOs to the Add-On design.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
5
S5933
32-Bit PCI “MatchMaker”
PCI Local Bus
Endian
Converter
B0
B0
B0
B0
B0
B0
B0
B0
B1
B1
B1
B1
B1
B1
B1
B1
B2
B2
B2
B2
B2
B2
B2
B2
B3
B3
B3
B3
B3
B3
B3
B3
B0
B0
B0
B0
B0
B0
B0
B0
B1
B1
B1
B1
B1
B1
B1
B1
B2
B2
B2
B2
B2
B2
B2
B2
B3
B3
B3
B3
B3
B3
B3
B3
Endian
Converter
Add-On Local Bus
S5933
32-Bit Master Write Address Register
32-Bit Master Read Address Register
30-Bit Master Read Count Register
28-Bit Master Write Count Register
Figure 5
Summary
Because the PCI bus applies to numerous system architectures, it allows a single add-in card hardware design to be
created for multiple platforms. The PCI standard also provides the bandwidth required for many new, high-performance applications.
The AMCC S5933 provides a flexible, low-cost, compliant interface to the PCI bus. The architecture of the S5933
makes it an excellent choice for cards being converted from the ISA/EISA standard, as well as newer applications
requiring high data rates and bus mastering capabilities. These applications include frame grabbers, work station
graphics, satellite receivers, modems, ISDN/FDDI/ATM communications and I/O interfaces. The S5933 allows the
hardware developer to focus on the actual application development rather than debugging the PCI bus interface logic.
This significantly shortens design cycles and decreases development costs.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
6
S5933
32-Bit PCI “MatchMaker”
S5933 PIN DESCRIPTIONS
AD[31:0]
t/s
Address/Data. Address and data are multiplexed on the same PCI bus pins. A PCI Bus
transaction consists of an address phase followed by one or more data phases. An address
phase occurs on the PCLK cycle in which FRAME# is asserted. A data phase occurs on
the PCLK cycles in which IRDY# and TRDY# are both asserted.
C/BE[3:0]#
t/s
Bus Command/Byte Enable. Bus commands and byte enables are multiplexed on the same
pins. These pins define the current bus command during an address phase. During a data
phase, these pins are used as Byte Enables, with C/BE[0]# enabling byte 0 (LSB) and C/
BE[3]# enabling byte 3 (MSB).
C/BE# [3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
PAR
t/s
Parity. Parity is always driven as even from all AD[31:0] and C/BE[3:0]# signals. The parity is valid during the clock following the address phase and is driven by the bus master.
During a data phase for write transactions, the bus master sources this signal on the clock
following IRDY# active; during a data phase for read transactions, this signal is driven by
the target and is valid on the clock following TRDY# active. The PAR signal has the same
timing as AD[31:0], delayed by one clock.
PCLK
in
Clock. The rising edge of this signal is the reference upon which all other signals are based
except for RST# and INTA#. The maximum PCLK frequency for the S5933 is 33 MHz
and the minimum is DC (0 Hz).
RST#
in
Reset is used to bring all other signals within the S5933 to a known, consistent state. All
PCI bus interface output signals are not driven (tri-stated), and open drain signals such as
SERR# are floated.
FRAME#
s/t/s
Frame. This signal is driven by the current bus master to indicate the beginning and duration of a bus transaction. When FRAME# is first asserted, it indicates a bus transaction is
beginning with a valid addresses and bus command present on AD[31:0] and C/BE[3:0].
FRAME# remains asserted during a burst data transfer and is deasserted to signify the
final data phase.
IRDY#
s/t/s
Initiator Ready. This signal is always driven by the bus master to indicate its ability to
complete the current data phase. During write transactions, it indicates AD[31:0] contains
valid data. Wait states occur until both TRDY# and IRDY# are asserted together.
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S5933
32-Bit PCI “MatchMaker”
TRDY#
s/t/s
Target Ready. This signal is sourced by the selected target and indicates the target is able
to complete the current data phase of a bus transaction. For read operation, it indicates that
the target is providing valid data on the AD[31:0] pins. Wait states occur until both
TRDY# and IRDY# are asserted together.
STOP#
s/t/s
Stop. The Stop signal is driven by a selected target and conveys a request to the bus master
to stop the current transaction.
LOCK#
in
Lock. The lock signal provides for the exclusive use of a resource. The S5933 may be
locked by one master at a time. The S5933 cannot lock a target when it is a master.
IDSEL
in
Initialization Device Select. This pin is used as a chip select during configuration read or
write transactions.
DEVSEL#
s/t/s
Device Select. This signal is driven by a target decoding and recognizing its bus address.
This signal informs a bus master whether an agent has decoded a current bus cycle.
INTA#
o/d
Interrupt A. This signal is defined as optional and a level sensitive Host interrupt. The
INTA# is used for any single function device requiring an interrupt capability.
REQ#
out
Request. This signal is sourced by an agent wishing to become the bus master. It is a pointto-point signal and each master has its own REQ#.
GNT#
in
Grant. The GNT# signal is a dedicated, point-to-point signal provided to each potential
bus master and signifies that access to the bus has been granted.
PERR#
s/t/s
Parity Error. Is used for reporting data parity errors for all bus transactions except for Special Cycles. It is driven by the agent receiving data two clock cycles after the parity was
detected as an error. This signal is driven inactive (high) for one clock cycle prior to
returning to the tri-state condition.
SERR#
o/d
System Error. Used to report address and data parity errors on Special Cycle commands
and any other error condition having a catastrophic system impact.
SCL
t/s
Serial Clock. This clock provides timing for transactions on the two-wire serial bus. This
signal is intended to be directly connected to one serial non-volatile RAM. This pin is
shared with the byte-wide interface signal, ERD#.
SDA
t/s
Serial Data/Address. This bidirectional pin is used to transfer addresses and data to or
from a serial nvRAM. It is an open drain output requiring a 10K external pull-up resistor.
This pin is shared with the byte-wide interface signal, EWR#.
EA[15:0]
t/s
External nv Memory Address. These signals connect directly to the external byte wide or
EPROM address pins EA0 through EA15. The PCI interface controller assembles 32-bit
wide accesses through multiple read cycles of the 8-bit device. The address space from
0040h through 007Fh is used to preload and initialize the PCI configuration registers.
Should an external nv memory be used, the minimum size required is 128 bytes and the
maximum is 64K bytes. When a serial memory is connected to the S5933, the pins
EA[7:0] are reconfigured to become hardware Add-On to PCI mailbox register controls
with the EA8 pin as the mailbox load clock. Also, the EA15 signal pin will provide an
indication that the PCI to Add-On FIFO is full (FRF), and the EA14 signal pin will indicate whether the add-On to PCI FIFO is empty (FWE).
ERD#
out
External nv Memory Read Control. This pin is asserted during read operations involving
the external non-volatile memory. Data is transferred into the S5933 during the low to high
transition of ERD#. This pin is shared with the serial external memory interface signal,
SCL.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
8
S5933
32-Bit PCI “MatchMaker”
EWR#
t/s
External nv Memory Write Control. This pin is asserted during write operations involving
the external non-volatile memory. Data is presented on pins EQ[7:0] along with its address
on pins EA[15:0] throughout the entire assertion of EWR#. This pin is shared with the
serial external memory interface signal, SDA.
EQ[7:0]
t/s
External Memory Data Bus. These pins are used to directly connect with the data pins of
an external non-volatile memory. When a serial memory is connected to the S5933, the
pins EQ4, EQ5, EQ6, and EQ7 become reconfigured to provide signal pins for bus mastering control from the Add-On interface.
DQ[31:0]
t/s
Address/Data Bus. The 32 bit Add-On data bus. The DQMODE signal configures the bus
width for either 32 or 16 bits. All DQ[31:0] signals have an internal pull-up.
ADR[6:2}
in
Address [6:2]. These inputs select which S5933 register is to be read from or written to. To
be used in conjunction with SELECT#, BE[3:0]# and WR# or RD#. The following table
shows the register addresses.
ADR
[6
0
0
0
0
0
0
0
1
5
0
0
1
1
1
1
1
0
4
0
1
0
0
1
1
1
0
3
1
1
1
1
0
1
1
0
2]
1
1
0
1
1
0
1
0
Description
Add-On Incoming Mailbox Register
Add-On Outgoing Mailbox Register
Add-On Pass-Thru Address Register
Add-On Pass-Thru Data Register
Add-On Mailbox Status Register
Add-On Interrupt Control Register
Add-On Reset Control Register
Pass-Thru/FIFO Configuration Register
BE[2:0]#
in
Byte Enable [2:0]. Provides individual read/write byte enabling during register read or
write transactions. BE2# enables activity over DQ[23:16], BE1# enables DQ[15:8], and
BE0# enables DQ[7:0]. During read transactions, enables the output driver for each byte
lane; for write transactions, serves as an input enable to perform the write to each byte
lane.
BE3#/ADR1
in
Byte Enable 3/Address 1. BE3#, enables DQ[31:24] input drivers for writing data to registers identified by ADR[6:2] and enables DQ[31:24] output drivers to read registers identified by ADR[6:2]. To be used in conjunction with SELECT# and RD# or WR#. ADR1,
selects the upper or lower WORD of a DWORD when a 16 bit wide bus is selected. 1 =
lower, 0 = upper.
SELECT#
in
Select. Enables internal S5933 logic to decode WR#, RD# and ADR[6:2] when reading or
writing to any Add-On register.
WR#
in
Write Enable. Asserting this signal writes DQ bus data byte(s) selected by BE[3:0]# into
the S5933 register defined by SELECT# and ADR[6:2].
RD#
in
Read Enable. Asserting this signal drives data byte(s) selected by BE[3:0]# from the
S5933 register defined by SELECT# and ADR[6:2] onto the DQ bus.
MODE
in
DQ Mode. Defines the DQ bus width when accessing data using WR#, RD#, SELECT#
and ADR[6:2]#. Low = 32-bit wide DQ bus. High = 16-bit wide DQ bus. When high, the
signal BE3# is re-assigned to the ADR1 signal and only DQ[15:0] is active.
PTATN#
out
Pass-Thru Attention. Signals a decoded PCI to Pass-Thru region bus cycle. PTATN# is
generated to signal Add-On logic Pass-Thru data must be read from or written to the
S5933.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
9
S5933
32-Bit PCI “MatchMaker”
PTBURST#
out
Pass-Thru Burst. Informs the Add-On bus the current Pass-Thru region decoded PCI bus
cycle is a burst access.
PTRDY#
in
Pass-Thru Ready. This input indicates when Add-On logic has completed a Pass-Thru
cycle and another may be initiated.
PTNUM[1:0]
out
Pass-Thru Number. Identifies which of the four Pass-Thru regions the Host read/write is
requesting. Only valid for the duration of PTATN#. 00 = Base Address Register 1, 01 =
Base Address Register 2, 10 = Base Address Register 3, 11 = Base Address Register 4.
PTBE[3:0]#
out
Pass-Thru Byte Enables. During a PCI to Pass-Thru read, Indicates which bytes of a
DWORD is to be written into. During a PCI to Pass-Thru write, indicates which bytes of a
DWORD are valid to read. PTBE[3:0]# are only valid while PTATN# is asserted.
PTADR#
in
Pass-Thru Address. When asserted, the 32-bit Pass-Thru address register contents is driven
onto the DQ[31:0] bus. All other Add-On control signals must be inactive during the
assertion of PTADR#.
PTWR
out
Pass-Thru Write. This signal indicates the current PCI to Pass-Thru bus transaction is a
read or write cycle. Valid only when PTATN# is active.
SYSRST#
out
System Reset. An active-low buffered PCI bus RST# output signal. The signal is asynchronous and can be asserted through software from the PCI host interface.
BPCLK
out
Buffered PCI Clock. This output is a buffered form of the PCI bus clock and has all of the
behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability).
IRQ#
out
Interrupt Request. This output signals Add-On logic a significant event has occurred as a
result of activity within the S5933.
FLT#
in
Float. Floats all S5933 output signals when asserted. This signal is connected to an internal pull-up resistor.
SNV
in
Serial Non-Volatile Device. This input, when high, indicates that a serial boot device or
that no boot device in present. When this pin is low, a byte-wide boot device is present.
WRFIFO#
in
Write FIFO. This signal provides a method to directly write the FIFO without having to
generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO.
Access width is either 32 bits or 16 bits depending on the data bus size available. This signal is intended for implementing PCI DMA transfers with the Add-On system. This pin
has an internal pull-up resistor.
RDFIFO#
in
Read FIFO. This signal provides a method to directly read the FIFO without having to
generate the SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO.
Access width is either 32 bits or 16 bits depending on the data bus size defined by the
MODE pin. This signal is intended for implementing PCI DMA transfers with the Add-On
system. This pin has an internal pull-up resistor.
WRFULL
out
Write FIFO Full. This pin indicates whether the Add-On-to-PCI bus FIFO is able to
accept more data. This pin is intended to be used to implement DMA hardware on the
Add-On system bus. A logic low output from this pin can be used to represent a DMA
write (Add-On-to-PCI FIFO) request.
RDEMTPY
out
Read FIFO Empty. This pin indicates whether the read FIFO (PCI-to-Add-On FIFO) contains data. This pin is intended to be used by the Add-On system to control DMA transfers
from the PCI bus to the ADd-On system bus. A logic low from this pin can be used to represent a DMA (PCI-to-Add-On FIFO) request.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
10
S5933
32-Bit PCI “MatchMaker”
TIMING DIAGRAMS
Synchronous RDFIFO# Timing
BPCLK
RDFIFO#
DQ[31:0]
RDEMPTY
1
2
3
4
New Valid
Old Valid
FRF
Notes:
1. The data 1 valid time is dependent on where RDFIFO# is asserted in it's window.
2. The data 4 signal is cut short due to the de-assertion of RDFIFO#.
3. The RDEMPTY is an example relative to data 2, if the FIFO went empty on data 2.
Synchronous WRFIFO# Timing
BPCLK
WRFIFO#
DQ[31:0]
WRFULL
1
2
Old Valid
3
New Valid
FWE
Notes:
1. The WRFULL is an example relative to data 2, if data 2 were to fill the FIFO.
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
11
S5933
32-Bit PCI “MatchMaker”
Multiple Synchronous RD# Operation
BPCLK
SELECT#
ADR[6:2]
BE[3:0]
1
DQ[31:0]
2
3
4
5
6
7
8
RD#
RDEMPTY
FRF
Multiple Synchronous WR# Operation
BPCLK
SELECT#
ADR[6:2]
BE[3:0]#
DQ[31:0]
1
2
3
4
5
WR#
WRFULL
FWE
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
12
6
7
8
S5933
32-Bit PCI “MatchMaker”
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (VDD Core)-0.3 V to 7.0 V
Input Pin Voltage Range-0.5 V to VDD + 0.5 V
Storage Temperature Range-55 to 125 °C
⊗ Stresses beyond those listed under absolute maximum ratings may cause permanent damage to this device. These are stress ratings only.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
Supply Voltage
Min
Max
Units
Test Conditions
Notes
4.75
5.25
Volts
Vih
High Level Input Voltage
2.0
-
Volts
Vil
Low Level Input Voltage
-0.5
0.8
Volts
Voh
High Level Output Voltage
2.4
-
Volts
Iout = -2 ma
Vol
Low Level Output Voltage
-
0.55
Volts
Iout = 3 ma, 6 ma
1
Iih
High Input Leakage Current
-
70
µA
Vin = 2.7 VDC
2
Iil
Vin = 0.5 VDC
2
Low Input Leakage Current
-
-70
µA
Cin
Input Pin Capacitance
-
10
pF
CCLK
CLK Pin Capacitance
5
12
pF
IDSEL Pin Capacitance
-
8
pF
CIDSEL
To PCI Spec 2.2
3
Notes:
1. PCI bus signals without pull-up resistors will provide the 3 ma output current. Signals which require a
pull-up Resistor (FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR# and PERR#) will provide 6
ma output current.
2. Input leakage applies to all inputs and bidirectional buffers.
3. The PCI specification limits all PCI inputs not located on the motherboard to 10 pF (the PCI clock is
allowed to be 12 pF).
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
13
S5933
32-Bit PCI “MatchMaker”
PCI
Local Bus
56
55
54
52
48
47
46
44
42
40
39
38
36
35
34
32
14
12
8
7
6
4
3
2
158
156
155
154
152
148
147
146
43
28
15
159
144
143
16
20
18
19
160
22
23
27
24
26
142
139
58
Device
Controls
Power &
Ground
59
138
135
10
30
50
70
90
110
130
150
11
31
51
71
91
111
131
151
134
136
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S5933 MatchMaker
C/BE0#
C/BE1#
C/BE2#
C/BE3#
REQ#
GNT#
FRAME#
DEVSEL#
IRDY#
TRDY#
IDSEL#
STOP#
LOCK#
BPCLK
IRQ#
SYSRST#
ADR2
ADR3
ADR4
ADR5
ADR6
BE0#
BE1#
BE2#
BE3#/ADR1
SELECT#
WR#
RD#
PAR
PERR#
SERR#
PTNUM0
PTNUM1
CLK
RST#
INTA#
PTBE0#
PTBE1#
PTBE2#
PTBE3#
MODE
FLT#
SNV
PTATN#
PTBURST#
PTADR#
PTWR
PTRDY#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
WRFULL
WRFIFO#
RDEMPTY
RDFIFO#
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
EO8
EO9
EO10
EO11
EO12
EO13
FWE/EO14
FRF/EO15
N/C
N/C
EQ0
EQ1
EQ2
EQ3
FWC#/EQ4
FRC#/EQ5
AMREN/EQ6
AMWEN/EQ7
EWR#/SDA
ERD#/SCL
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
14
100
99
98
96
95
94
92
88
86
84
83
82
80
79
78
76
157
145
133
125
117
105
93
85
77
65
53
45
37
25
13
5
Add-On
Local Bus
140
124
126
Add-On Local
Bus Controls
68
67
66
64
132
87
63
62
60
Add-On Local
Bus Register
Controls
75
74
72
123
122
116
118
119
120
Pass-Thru Data
Controls
114
112
107
108
115
103
102
106
104
57
61
69
73
81
89
97
101
109
113
121
129
137
141
149
153
FIFO Data
Controls
Byte-Wide
nvRAM Data
1
9
17
21
29
33
41
49
127
128
nvRAM Bus
S5933
32-Bit PCI “MatchMaker”
PACKAGE INFORMATION
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
PTBE3#
PTBE2#
PTBE1#
DQ20
PTBE0#
PTRDY#
PTATN#
EA9
PTBURST#
VDD
VSS
EA8
PTWR
PTADR#
RDEMPTY
DQ21
RDFIFO#
WRFULL
WRFIFO#
EA7
DQ0
DQ1
DQ2
EA6
DQ3
DQ4
DQ5
DQ22
DQ6
VDD
VSS
EA5
DQ7
BE0#
DQ8
DQ23
DQ9
DQ10
DQ11
EA4
160 PQFP
S5933
160 PQFP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
DQ12
DQ13
DQ14
DQ24
DQ15
SELECT#
WR#
EA3
RD#
VDD
VSS
EA2
ADR2
ADR3
ADR4
DQ25
ADR5
BE1#
BE2#
EA1
BE3#
MODE
INTA#
EA0
AD0
AD1
AD2
DQ26
AD3
VDD
VSS
EQ7/AMWEN
AD4
AD5
AD6
DQ27
AD7
C/BEO#
AD8
EQ6/AMREN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
EQ0
AD23
AD22
AD21
DQ31
AD20
AD19
AD18
EQ1
VSS
VDD
AD17
DQ30
AD16
C/BE2#
FRAME#
EQ2
IRDY#
TRDY#
DEVSEL#
EQ3
STOP#
LOCK#
PERR#
DQ29
SERR#
PAR
C/BE1#
EQ4/FWC#
VSS
VDD
AD15
EQ5/FRC#
AD14
AD13
AD12
DQ28
AD11
AD10
AD9
EA10
PTNUM1
PTNUM0
IRQ#
DQ19
SYSRST#
EWR#/SDA
ERD#/SCL
EA11
VSS
VDD
ADR6
DQ18
NC
SNV
NC
EA12
FLT#
RST#
BPCLK
EA13
CLK
GNT#
REQ#
DQ17
AD31
AD30
AD29
EA14/FWE
VSS
VDD
AD28
EA15/FRF
AD27
AD26
AD25
DQ16
AD24
C/BE3#
IDSEL
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
15
S5933
32-Bit PCI “MatchMaker”
PACKAGE INFORMATION
160 PQFP
D
Symbol
D1
MIN
NOM
MAX
A
-
-
4.07
A1
A2
0.25
3.17
-
-
D
31.90 BSC
D1
E
28.00 BSC
31.90 BSC
S5933
160 PQFP
E1
E
E1
28.00 BSC
L
e
0.65
0.80
0.65 BSC
1.03
B
0.22
-
0.38
c
α
0.11
5
-
0.23
16
β
0
-
7
γ
G
H
0
-
-
0.13
1.95 BSC
-
J
0.13
-
0.30
K
2H
0.40
-
3.9
-
Pin 1
Indicator
B
e
See Detail
A
A
A2
Seating
Plane
0.10 C
C
A1
α
K
γ
α
L
J Radius
Detail A
β
H
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
16
-C-
S5933
32-Bit PCI “MatchMaker”
The material in this document supersedes
all previous documentation issued for any
of the products included herein.
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises
its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.
AMCC does not assume any liability arising out of the application or
use of any product or circuit described herein, neither does it convey any
license under its patents rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of
those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED,
INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE
FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Copyright © 1998 Applied Micro Circuits Corporation
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
17
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18
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