SRAM MT5C1008(LL) Ultra Low Power Austin Semiconductor, Inc. 128K x 8 SRAM PIN ASSIGNMENT (Top View) WITH DUAL CHIP ENABLE ULTRA LOW POWER 32-Pin DIP (C) AVAILABLE AS MILITARY SPECIFICATIONS NC 1 32 VCC A16 2 31 A15 •MIL-STD-883, para. 1.2.2 compliant A14 3 30 CE2 A12 4 29 WE\ A7 5 28 A13 A6 6 26 A8 A5 7 27 A9 A4 8 25 A11 A3 9 24 OE\ A2 10 23 A10 A1 11 22 CE1\ A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 FEATURES • • • • • • • • High Speed: 30 ns Low active power: 715 mW worst case Low CMOS standby power: 3.3 mW worst case 2.0V data retention, Ultra Low 0.3mW worst case power dissipation Battery backup applications Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE1\, CE2, and OE\ options OPTIONS MARKING • Timing 30ns access -30 GENERAL DESCRIPTION • Package(s) Ceramic DIP (400 mil) • Temperature Military (-55°C to +125°C) • Options 2V data retention/very low power C The MT5C1008 SRAM is a high-performance CMOS static RAM organized as 131, 072 words by 8 bits, offering low active power and ultra low standby and data retention current levels. Easy memory expansion is provided by an active LOW Chip Enable (CE1\), an active HIGH Chip Enable (CE2), and active Low Output Enable (OE\), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1\) and Write Enable (WE\) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1\) and Output Enable (OE\) LOW while forcing Write Enable (WE\) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1\) HIGH or CE2 LOW), the outputs are disabled (OE\ HIGH), or during a write operation (CE1\ LOW, CE2 HIGH, and WE\ LOW). No. 111 MIL LL For more products and information please visit our web site at www.austinsemiconductor.com MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM MT5C1008(LL) Ultra Low Power Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM TRUTH TABLE MODE OE\ CE1\ CE2 WE\ I/O0 - I/O7 POWER Power-Down X H X X High Z Standby (ISB) Power-Down X X L X High Z Standby (ISB) Read L L H H Data Out Active (ICC) Write X L H L Data In Active (ICC) Selected, Outputs Disabled H L H H High Z Active (ICC) MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM MT5C1008(LL) Ultra Low Power Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* 1 Supply Voltage Range on Vcc to Relative GND ..-0.5V to +7.0V Storage Temperature .............................................-65°C to +150°C Ambient Temperature with Power Applied........-55°C to +125°C DC Voltage Applied to Outputs in High Z State1.................................................-0.5V to Vcc + 0.5V DC Input Voltage1.............................................-0.5V to Vcc + 0.5V *Stresses at or greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods will affect reliability. Refer to page 17 of this data sheet for a technical note on this subject. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity. ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (-55oC < TC < 125oC; VCC = 5.0V +10%) -30 PARAMETER CONDITIONS SYM MIN Output HIGH Voltage Vcc = MIN, IOH = -4.0 mA VOH 2.4 Output LOW Voltage Vcc = MIN, IOL = 8.0 mA VOL MAX UNITS V 0.4 V Input HIGH Voltage VIH 2.2 VCC+0.3 V Input LOW Voltage VIL -0.3 0.8 V Input Load Current GND < VI < Vcc IIX -10 +10 µA Output Leakage Current GND < VI < Vcc, Output Disabled IOZ -10 +10 µA ICC 130 mA ISB1 4 mA ISB2 0.6 mA Vcc Operating Supply Current Vcc = MAX, IOUT = 0 mA Automatic CE PowerDown Current - TTL Inputs MAX Vcc, CE1\ > VIH or Automatic CE PowerDown Current - CMOS Inputs MAX Vcc, CE1\ > Vcc - 0.3V, or CE2 < 0.3V, VIN > Vcc - 0.3V, or f = f = 1/tRC CE2 < VIL, VIN > VIH or NOTES 1 VIN < VIL, f = fMAX VIN < 0.3V, f = 0 NOTES: 1. VIL(MIN) = -2.0V for pulse durations of less than 20ns. MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM MT5C1008(LL) Ultra Low Power Austin Semiconductor, Inc. CAPACITANCE1 PARAMETER CONDITIONS Input Capacitance (A0 - A16) Input Capacitance (CE\, WE\, OE\) TA = 25°C, f = 1MHz, Vcc = 5.0V Output Capacitance SYM MAX UNITS CIN 8 pF CCLK 10 pF COUT 12 pF NOTES: 1. Tested initially and after any design or process changes that may effect these parameters. AC TEST LOADS AND WAVEFORMS DATA RETENTION CHARACTERISTICS (-55oC < TC < 125oC; VCC = 5.0V +10%) PARAMETER CONDITIONS Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time 0.2V, Vcc = VDR = 2.0V, CE1\ > Vcc - 0.3V or CE2 < 0.3V, VIN > Vcc - 0.3V or VIN < 0.3V Operation Recovery Time SYM MIN VDR 2.0 ICCDR MAX UNITS V 150 µA tCDR 0 ns tR 200 µs DATA RETENTION WAVEFORM MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM MT5C1008(LL) Ultra Low Power Austin Semiconductor, Inc. SWITCHING CHARACTERISTICS1 (-55oC < TC < 125oC; VCC = 5.0V +10%) -30 PARAMETER SYM MIN Read Cycle Time tRC 30 Address to Data Valid tAA MAX UNITS NOTES READ CYCLE ns 30 ns Data Hold from Address Change tOHA CE1\ LOW to Data Valid, CE2 HIGH to Data Valid tACE 30 ns OE\ LOW to Data Valid tDOE 12 ns OE\ LOW to Low Z tLZOE OE\ HIGH to High Z tHZOE CE1\ LOW to Low Z, CE2 HIGH to Low Z tLZCE CE1\ HIGH to High Z, CE2 LOW to High Z tHZCE WRITE CYCLE 3 ns 0 ns 8 3 15 ns 2, 3 ns 3 ns 2, 3 5 4 Write Cycle Time tWC 30 ns CE1\ LOW to Write End, CE2 HIGH to Write End tSCE 22 ns Address Set-Up to Write End tAW 22 ns Address Hold from Write End tHA 0 ns Address Set-Up to Write Start tSA 0 ns tPWE 22 ns Data Set-up to Write End tSD 18 ns Data Hold from Write End tHD 0 ns WE\ HIGH to Low Z tLZWE 5 ns 3 WE\ LOW to High Z tHZWE ns 2, 3 WE\ Pulse Width 8 NOTES: 1. Test conditions assume signal transition time of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30pF load capacitance. 2. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5pF as in part (b) of AC Test Loads. Transition is measured ±500mV from steady-state voltage. 3. At any given temperature and voltage condition, tHZCE < tLZCE, tHZOE < tLZOE, and tHZWE < tLZWE for any given device. 4. The internal write time of the memory is defined by the overlap of CE1\ LOW, CE2 HIGH, and WE\ LOW. CE1\ and WE\ must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. 5. The minimum write cycle time for Write Cycle No. 3 (WE\ controlled, OE\ LOW) is the sum of tHZWE and tSD. MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SRAM Austin Semiconductor, Inc. MT5C1008(LL) Ultra Low Power SWITCHING WAVEFORMS Read Cycle No. 11,2 Read Cycle No. 2 (OE\ Controlled)2,3 NOTES: 1. Device is continuously selected. OE\, CE1\ = VIL, CE2 = VIH. 2. WE\ is HIGH for read cycle. 3. Address valid prior to or coincident with CE1\ transition LOW and CE2 transition HIGH. MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SRAM Austin Semiconductor, Inc. MT5C1008(LL) Ultra Low Power SWITCHING WAVEFORMS (continued) Write Cycle No. 1 (CE1\ or CE2 Controlled)1,2 Write Cycle No. 2 (WE\ Controlled, OE\ HIGH During Write)1,2 NOTES: 1. Data I/O is high impedance if OE\ = VIH. 2. If CE1\ goes HIGH or CE2 goes LOW simultaneously with WE\ going HIGH, the output remains in a high-impedance state. 3. During this period the I/Os are in the output state and input signals should not be applied. MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SRAM Austin Semiconductor, Inc. MT5C1008(LL) Ultra Low Power SWITCHING WAVEFORMS (continued) Write Cycle No. 3 (WE\ Controlled, OE\ LOW)1 NOTES: 1. If CE1\ goes HIGH or CE2 goes LOW simultaneously with WE\ going HIGH, the output remains in a high-impedance state. 2. During this period the I/Os are in the output state and input signals should not be applied. MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SRAM MT5C1008(LL) Ultra Low Power Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #111 (Package Designator C) D S1 S2 A Q L1 Pin 1 L S e b b1 E NOTE 0o to 15o c E1 Detail A ASI SPECIFICATIONS MIN MAX SYMBOL A --0.232 b 0.014 0.023 b1 0.038 0.065 c 0.008 0.015 D --1.700 E 0.350 0.405 E1 0.390 0.420 e 0.100 BSC L 0.125 0.200 L1 0.150 --Q 0.015 0.060 S --0.100 S1 0.005 --S2 0.005 --NOTE: Either configuration in detail A is allowed. *All measurements are in inches. MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 SRAM MT5C1008(LL) Ultra Low Power Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: MT5C1008C-30LL/MIL Device Package Speed Options** Process Number Type ns MT5C1008 C -30 LL /* *AVAILABLE PROCESSES MIL = Military Processing (MIL-STD-883, para. 1.2.2 compliant) -55oC to +125oC ** OPTIONS LL = 2V Data Retention/Ultra Low Power NOTE: For other speeds and options, see the MT5C1008 data sheet (available from www.austinsemiconductor.com). MT5C1008(LL) Rev. 1.0 7/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10