HSDL-3211 IrDA® Data Compliant Low Power 1.15 Mbit/s Infrared Transceiver Data Sheet Description The HSDL-3211 is a new generation low profile high speed infrared transceiver module that provides interface between logic and IR signals for throughair, serial, half-duplex IR data-link. The module is fully compliant to IrDA Physical Layer specification version 1.4 low power from 9.6kbit/s to 1.152 Mbit/s (MIR) and is IEC825-Class 1 Eye Safe. Features • Fully compliant to IrDA 1.4 physical layer low power specification from 9.6 kbit/s to 1.152 Mbit/s (MIR) • Miniature package – Height: 2.5 mm – Width: 8.0 mm – Depth: 3.0 mm • No data rate switching required • Typical link distance > 50 cm The HSDL-3211 can be shutdown completely to achieve very low power consumption. In the shutdown mode, the PIN diode will be inactive and thus producing very little photocurrent even under very bright ambient light. It is also designed to interface to input/output logic circuits as low as 1.8V. These features are ideal for mobile devices that require low power consumption. • Guaranteed temperature performance, -25o to 85oC – Critical parameters are guaranteed over temperature and supply voltage • Low power consumption – Low shutdown current (1 nA typical) – Complete shutdown of TXD, RXD, and PIN diode • Withstands >100 mVp-p power supply ripple typically • Excellent EMI performance • Vcc supply 2.4 to 3.6 Volts VCC CX2 • Interfacing with I/O logic circuits as low as 1.8 V CX4 • Lead-free package CX1 GND (8) VCC (6) IOVCC (7) • LED stuck-high protection • Designed to accommodate light loss with cosmetic windows SD (5) RECEIVER • IEC 825-class 1 eye safe RXD (4) Applications SHIELD HSDL-3211 TXD (3) LED C (2) R1 TRANSMITTER LED A (1) Vled CX3 Figure 1. Functional block diagram of HSDL-3211. 8 7 6 5 4 3 2 Figure 2. Rear view diagram with pinout. 1 • Mobile telecom – Mobile phones – Smart phones – Pagers • Data communication – Pocket PC handheld products – Personal digital assistants – Portable printers • Digital imaging – Digital cameras – Photo-imaging printers • Electronic wallet • Small industrial & medical instrumentation – General data collection devices – Patient & pharmaceutical data collection devices Application Support Information The Application Engineering Group is available to assist you with the application design associated with the HSDL-3211 infrared transceiver module. You can contact them through your local sales representatives for additional details. Order Information Part Number Packaging Type Package Quantity HSDL-3211-021 Tape and Reel Front View 2500 I/O Pins Configuration Table Pin Symbol Description I/O Type Notes 1 LED A LED Anode I 1 2 LED C LED Cathode 3 TXD Transmit Data. Active High. I 3 4 RXD Receive Data. Active Low. O 4 5 SD Shutdown. Active High. I 5 6 Vcc Supply Voltage 6 7 IOVcc Input/Output ASIC Vcc 7 8 GND Ground 8 - Shield EMI Shield 9 2 Recommended Application Circuit Components Component Recommended Value Notes R1 3.9Ω ± 5%, 0.25 watt for 2.4 ≤ Vled < 2.7V 5.6Ω ± 5%, 0.25 watt for 2.7 ≤ Vled < 3.3V 10Ω ± 5%, 0.25 watt for 3.3 ≤ Vled < 4.2V 15Ω ± 5%, 0.25 watt for 4.2 ≤ Vled < 5.5V CX1, CX4 0.47 µF ± 20%, X7R Ceramic 10 CX2, CX3 6.8 µF ± 20%, Tantalum 11 Notes: 1. Tied through external series resistor, R1, to regulated Vled from 2.4 to 5.5V. Please refer to table below for recommended series resistor value. 2. Internally connected to LED driver. Leave this pin unconnected. 3. This pin is used to transmit serial data when SD pin is low. If this pin is held high for longer than 50 ms, the LED is turned off. Do NOT float this pin. 4. This pin is capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. The pin is in tri-state when the transceiver is in shutdown mode. The receiver output echoes transmitted signal. 5. The transceiver is in shutdown mode if this pin is high. Do NOT float this pin. 6. Regulated, 2.4 to 3.6 Volts. 7. Connect to ASIC logic controller Vcc voltage or supply voltage. The voltage at this pin must be equal to or less than supply voltage. 8. Connect to system ground. 9. Connect to system ground via a low inductance trace. For best performance, do not connect directly to the transceiver pin GND 10. CX1 must be placed within 0.7 cm of the HSDL-3211 to obtain optimum noise immunity. 11. In environments with noisy power supplies, including CX2, as shown in Figure 1, can enhance supply ripple rejection performance. 2 Marking Information The unit is marked with ‘yyww’ on the shield: yy = year ww = work week CAUTIONS: The BiCMOS inherent to the design of this component increases the component’s susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Absolute Maximum Ratings For implementations where case to ambient thermal resistance is ≤ 50°C/W. Parameter Symbol Min. Max. Units Storage Temperature TS -40 +100 °C Operating Temperature TA -25 +85 °C LED Anode Voltage VLEDA 0 6.5 V Supply Voltage VCC 0 6.5 V Input Voltage: TXD, SD/Mode VI 0 6.5 V Output Voltage: RXD VO 0 6.5 V DC LED Transmit Current ILED (DC) 150 mA Average Transmit Current ILED (PK) 600 mA Conditions ≤ 90 µs pulse width ≤ 25% duty cycle Recommended Operating Conditions Parameter Symbol Min. Operating Temperature TA Supply Voltage Input/Output Voltage Logic Input Voltage for TXD, SD/Mode Receiver Input Irradiance LED (Logic High) Current Pulse Amplitude Receiver Data Rate Max. Units -25 +85 °C VCC 2.4 3.6 V IOVcc 1.8 Vcc V Logic High VIH IOVcc – 0.5 IOVcc V Logic Low VIL 0 0.4 V Logic High EIH, min EIH, max 0.0081 500 mW/cm2 mW/cm2 Logic Low EIL 0.3 µW/cm2 ILEDA Typ. 150 0.0096 Conditions 9.6kbit/s ≤ in-band signals ≤1.152 Mbit/s [12] For in-band signals [12] mA 1.152 Mbit/s Note : 12. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 ≤ λp ≤ 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4. 3 Electrical & Optical Specifications Specifications (Min. & Max. values) hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values (Typ.) are at 25°C, Vcc set to 3.0V and IOVcc set to 1.8V unless otherwise noted. Parameter Symbol Min. Viewing Angle 2θ 30 Peak Sensitivity Wavelength λp Typ. Max. Units Conditions Receiver ° 880 nm Logic High VOH IOVCC – 0.2 IOVCC V IOH = -200 µA, EI ≤ 0.3 µW/cm2 Logic Low VOL 0 0.4 V IOL = 200 µA, EI ≥ 8.1 µW/cm2 RXD Pulse Width (SIR)[13] tPW (SIR) 1 4.0 µs θ ≤ 15°, CL = 9 pF RXD Pulse Width (MIR)[14] tPW(MIR) 100 500 ns θ ≤ 15°, CL = 9 pF RXD Rise and Fall Times tr, tf 25 ns CL = 9 pF Receiver Latency Time[15] tL 25 50 µs Receiver Wake Up Time[16] tW 50 100 µs RXD Output Voltage Transmitter IEH 10 Viewing Angle 2θ 30 Peak Wavelength λp 875 nm Spectral Line Half Width ∆λ 35 nm High IH 0.02 10 µA VTXD ≥ VIH Low IL -0.02 10 µA 0 ≤ VTXD ≤ VIL mA VTXD ≥ VIH, R1=5.6ohm, Vled=3.0V TXD Input Current -10 45 mW/sr ILEDA= 150 mA, θ ≤ 15°, VTXD ≥ VIH, VSD ≤ VIL, Ta=25°C Radiant Intensity 60 150 ° LED ON Current ILEDA TXD Pulse Width (SIR) tPW (SIR) 1.5 1.6 1.8 µs tPW (TXD) = 1.6 µs at 115.2 kbit/s TXD Pulse Width (MIR) tPW(MIR) 148 217 260 ns tPW (TXD) = 217 ns at 1.152 Mbit/s Maximum Optical PW[17] tPW(max.) 50 100 µs TXD Rise and fall Time (Optical) tr, tf 40 ns tPW (TXD) = ns at 1.152 Mbit/s LED Anode On-State Voltage VON(LEDA) 1.6 2.0 V ILEDA=150 mA, VTXD ≥VIH Shutdown ICC1 0.001 1 µA VSD ≥ VIH, Ta= 25 °C Idle ICC2 0.4 1.0 mA VSD ≤ VIL, VTXD ≤ VIL, EI=0 Transceiver Supply Current Notes: 13. For in-band signals from 9.6 kbit/s to 115.2 kbit/s, where 9 µW/cm2 ≤ EI ≤ 500 mW/cm2. 14. For in-band signals from 0.576 Mbit/s to 1.152 Mbit/s, where 22.5 µW/cm2 ≤ EI ≤ 500 mW/cm2. 15. Latency time is defined as the time from the last TxD light output pulse until the receiver has recovered full sensitivity. 16. Receiver wake up time is measured from Vcc power on or SD pin high to low transition to a valid RXD output. 17. The maximum optical PW is the maximum time the LED remains on when the TXD is constantly high. This is to prevent long turn on time of the LED for eye safety protection. 4 tpw tpw VOH LED ON 90% 90% 50% 50% 10% VOL 10% LED OFF tf tr Figure 3. RxD output waveform. tr tf Figure 4. LED optical waveform. SD TXD RX LIGHT RXD LED tRW tpw (MAX.) Figure 5. TxD “Stuck On” protection waveform. Figure 6. Receiver wakeup time waveform. 0.18 50 0.16 0.14 40 LOP (mW/Sr) Iled (A) 0.12 0.10 0.08 0.06 30 20 0.04 10 0.02 0 1.4 1.5 1.6 1.7 1.8 VledA (V) Figure 7. LED anode voltage vs. LED current. 5 0 0 0.05 0.1 0.15 0.2 lled (A) Figure 8. LED current vs. radiant intensity. HSDL-3211 Package Dimensions 2.0 0.8 0.4 6 HSDL-3211 Tape and Reel Dimensions 4.0 ± 0.1 Unit: mm 1.75 ± 0.1 1.5 ± 0.1 1.5 +0.10 POLARITY Pin 8: GND 7.5 ± 0.1 16.0 ± 0.2 Pin 1: LEDA 0.4 ± 0.05 8.4 ± 0.1 Material of Carrier Tape: Conductive Polystyrene Material of cover tape: PVC Method of cover: Heat activated adhesive 3.4 ± 0.1 2.8 ± 0.1 8.0 ± 0.1 Progressive Direction Empty Parts Mounted Leader (400mm min) (40mm min) Empty (40mm min) Option # "B" "C" Quantity 021 330 80 2500 Unit: mm Detail A 2.0 ± 0.5 B C 13.0 ± 0.5 R1.0 LABEL 21 ± 0.8 Detail A 16.4 +2 0 2.0 ± 0.5 Note: The carrier tape is compliant to the packaging materials standards for ESD sensitive device, EIA-541 7 Moisture Proof Packaging All HSDL-3211 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 4. Baking Conditions If the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. Package UNITS IN A SEALED MOISTURE-PROOF PACKAGE Temp. Time In reels 60°C ≥ 48 hours In bulk 100°C ≥ 4 hours 125°C ≥ 2 hours 150°C ≥ 1 hour Baking should only be done once. PACKAGE IS OPENED (UNSEALED) Recommended Storage Conditions ENVIRONMENT LESS THAN 30°C, AND LESS THAN 60% RH YES PACKAGE IS OPENED LESS THAN 72 HOURS NO PERFORM RECOMMENDED BAKING CONDITIONS Figure 9. Baking conditions chart. 8 10°C to 30°C Relative Humidity below 60% RH Time from Unsealing to Soldering After removal from the bag, the parts should be soldered within three days if stored at the recommended storage conditions. If times longer than three days are needed, the parts must be stored in a dry box. YES NO BAKING IS NECESSARY Storage Temperature NO Recommended Reflow Profile MAX. 260°C T – TEMPERATURE – (°C) 255 R4 R3 230 220 200 180 R2 60 sec. MAX. ABOVE 220°C 160 R1 120 R5 80 25 0 50 100 150 200 250 300 t-TIME (SECONDS) P1 HEAT UP P2 SOLDER PASTE DRY P3 SOLDER REFLOW P4 COOL DOWN Process Zone Symbol ∆T Maximum ∆T/∆time Heat Up P1, R1 25°C to 160°C 4°C/s Solder Paste Dry P2, R2 160°C to 200°C 0.5°C/s P3, R3 200°C to 255°C (260°C at 10 seconds max) 4°C/s P3, R4 255°C to 200°C -6°C/s P4, R5 200°C to 25°C -6°C/s Solder Reflow Cool Down The reflow profile is a straightline representation of a nominal temperature profile for a convective reflow solder process. The temperature profile is divided into four process zones, each with different ∆T/∆time temperature change rates. The ∆T/∆time rates are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and HSDL-3211 castellation pins are heated to a temperature of 160°C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4°C per second to allow for even heating of both the PC board and HSDL-3211 castellations. 9 Process zone P2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 200° C (392° F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255° C (491° F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 60 seconds, the intermetallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200° C (392° F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25° C (77° F) should not exceed 6° C per second maximum. This limitation is necessary to allow the PC board and HSDL-3211 castellations to change dimensions evenly, putting minimal stresses on the HSDL-3211 transceiver. Appendix A: SMT Assembly Application Note Solder Pad, Mask and Metal Stencil Aperture METAL STENCIL FOR SOLDER PASTE PRINTING STENCIL APERTURE LAND PATTERN SOLDER MASK PCB Figure 10. Stencil and PCBA. Recommended Land Pattern SHIELD SOLDER PAD CL 1.35 MOUNTING CENTER 1.25 2.05 0.10 0.775 1.75 FIDUCIAL 0.60 0.475 1.425 UNIT: mm 2.375 3.325 Figure 11. Stencil and PCBA. 10 Recommended Metal Solder Stencil Aperture It is recommended that only a 0.152 mm (0.006 inches) or a 0.127 mm (0.005 inches) thick stencil be used for solder paste printing. This is to ensure adequate printed solder paste volume and no shorting. See the table below the drawing for combinations of metal stencil aperture and metal stencil thickness that should be used. Aperture opening for shield pad is 2.7 mm x 1.25 mm as per land pattern. Adjacent Land Keepout and Solder Mask Areas Adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. There should be no other SMD components within this area. APERTURES AS PER LAND DIMENSIONS t w l Figure 12. Solder stencil aperature. Stencil thickness, t (mm) Aperture size (mm) length, l width, w 0.152 mm 2.60 ± 0.05 0.55 ± 0.05 0.127 mm 3.00 ± 0.05 0.55 ± 0.05 10.1 0.2 3.85 The minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2 mm. It is recommended that two fiducial crosses be place at midlength of the pads for unit alignment. SOLDER MASK 3.0 UNITS: mm Note: Wet/Liquid PhotoImageable solder resist/mask is recommended. 11 Figure 13. Adjacent land keepout and solder mask areas. Appendix B: PCB Layout Suggestion The following PCB layout guidelines should be followed to obtain a good PSRR and EM immunity resulting in good electrical performance. Things to note: 4. Preferably a multi-layered board should be used to provide sufficient ground plane. Use the layer underneath and near the transceiver 1. The ground plane should be continuous under the part, but should not extend under the shield trace. TOP LAYER CONNECT THE METAL SHIELD AND MODULE GROUND PIN TO BOTTOM GROUND LAYER. 2. The shield trace is a wide, low inductance trace back to the system ground. CX1, CX2, CX3, and CX4 are optional supply filter capacitors; they may be left out if a clean power supply is used. 3. Vled can be connected to either unfiltered or unregulated power supply. If Vled and Vcc share the same power supply, CX3 need not be used and the connections for CX1 and CX2 should be before the current limiting resistor R1. In a noisy environment, including capacitor CX2 can enhance supply rejection. CX1 is generally a ceramic capacitor of low inductance providing a wide frequency response while CX2 and CX3 are tantalum capacitors of big volume and fast frequency response. The use of a tantalum capacitor is more critical on the Vled line, which carries a high current. CX4 is an optional ceramic capacitor, similar to CX1, for the IOVcc line. LAYER 2 CRITICAL GROUND PLANE ZONE. DO NOT CONNECT DIRECTLY TO THE MODULE GROUND PIN. LAYER 3 KEEP DATA BUS AWAY FROM CRITICAL GROUND PLANE ZONE. BOTTOM LAYER (GND) The area underneath the module at the second layer, and 3 cm in all directions around the module is defined as the critical ground plane zone. The ground plane should be maximized in this Figure 14. PCB layout suggestion. 12 module as Vcc, and sandwich that layer between ground connected board layers. Refer to the diagram below for an example of a 4 layer board. zone. Refer to application note AN1114 or the Avago IrDA Data Link Design Guide for details. The layout below is based on a 2-layer PCB. Appendix C: General Application Guide for the HSDL-3211 Description The HSDL-3211, a low-cost and small form factor infrared transceiver, is designed to address the mobile computing market such as PDAs, as well as small-embedded mobile products such as digital cameras and cellular phones. It is fully compliant to IrDA 1.4 low power specification from 9.6 kb/s to 1.152 Mb/s, and supports HP-SIR and TV Remote modes. The design of the HSDL-3211 also includes the following unique features: • Low passive component count. • Shutdown mode for low power consumption requirement. • Interface to input/output logic circuits as low as 1.8V Interface to Recommended I/O chips The HSDL-3211’s TXD data input is buffered to allow for CMOS drive levels. No peaking circuit or capacitor is required. Data rate from 9.6 kb/s up to 1.152 Mb/s is available at the RXD pin. The block diagram below shows how the IR port fits into a mobile phone and PDA platform. Selection of Resistor R1 Resistor R1 should be selected to provide the appropriate peak pulse LED current over different ranges of Vcc as shown in the table below. Recommended R1 Vled Intensity Minimum Peak Pulse LED Current 5.6Ω 3.0 V 45 mW/sr 150 mA SPEAKER AUDIO INTERFACE DSP CORE MICROPHONE ASIC CONTROLLER RF INTERFACE TRANSCEIVER MOD/ DE-MODULATOR IR MICROCONTROLLER USER INTERFACE Figures 15. Mobile phone platform. 13 HSDL-3211 LCD PANEL RAM IR HSDL-3211 CPU FOR EMBEDDED APPLICATION ROM PCMCIA CONTROLLER TOUCH PANEL RS232C DRIVER Figure 16. PDA platform. The link distance testing was done using typical HSDL-3211 units with SMC’s FDC37C669 and FDC37N769 Super I/O controllers. An IR link distance of up to 75 cm was demonstrated for SIR and MIR at full power. 14 COM PORT Appendix D: Window Designs for HSDL-3211 Optical port dimensions for HSDL-3211 To ensure IrDA compliance, some constraints on the height and width of the window exist. The minimum dimensions ensure that the IrDA cone angles are met without vignetting. The maximum dimensions minimize the effects of stray light. The minimum size corresponds to a cone angle of 30° and the maximum size corresponds to a cone angle of 60° . In the figure below, X is the width of the window, Y is the OPAQUE MATERIAL height of the window and Z is the distance from the HSDL-3211 to the back of the window. The distance from the center of the LED lens to the center of the photodiode lens, K, is 5.1mm. The equations for computing the window dimensions are as follows: X = K + 2*(Z+D)*tanA Y = 2*(Z+D)*tanA The above equations assume that the thickness of the window is negligible compared to the distance of the module from the back of the window (Z). If they are IR TRANSPARENT WINDOW Y X IR TRANSPARENT WINDOW K Z A D Figure 17. Window design diagram. 15 OPAQUE MATERIAL comparable, Z' replaces Z in the above equation. Z' is defined as Z' = Z + t/n where ‘t’ is the thickness of the window and ‘n’ is the refractive index of the window material. The depth of the LED image inside the HSDL-3211, D, is 3.17mm. ‘A’ is the required half angle for viewing. For IrDA compliance, the minimum is 15° and the maximum is 30° . Assuming the thickness of the window to be negligible, the equations result in the following tables and graphs. Aperture Width (x, mm) Max. Min. Aperture Height (y, mm) Max. Min. 0 8.76 6.80 3.66 1.70 1 9.92 7.33 4.82 2.33 2 11.07 7.87 5.97 2.77 3 12.22 8.41 7.12 3.31 4 13.38 8.94 8.28 3.84 5 14.53 9.48 9.43 4.38 6 15.69 10.01 10.59 4.91 7 16.84 10.55 11.74 5.45 8 18.00 11.09 12.90 5.99 9 19.15 11.62 14.05 6.52 APERTURE WIDTH (X) vs. MODULE DEPTH APERTURE HEIGHT (Y) vs. MODULE DEPTH 25 16 20 15 10 X MAX. X MIN. 5 0 0 1 2 3 4 59 6 7 8 MODULE DEPTH (Z) – mm Figure 18. Aperture width (X) vs. module depth. 16 APERTURE HEIGHT (Y) – mm APERTURE WIDTH (X) – mm Module Depth (z) mm 14 12 10 8 6 4 Y MAX. Y MIN. 2 0 0 1 2 3 4 59 6 7 8 MODULE DEPTH (Z) – mm Figure 19. Aperture height (Y) vs. module depth. Window Material Almost any plastic material will work as a window material. Polycarbonate is recommended. The surface finish of the plastic should be smooth, without any texture. An IR filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. Light loss should be measured at 875 nm. The recommended plastic materials for use as a cosmetic window are available from General Electric Plastics. Shape of the Window From an optics standpoint, the window should be flat. This ensures that the window will not alter either the radiation pattern of the LED, or the receive pattern of the photodiode. If the window must be curved for mechanical or industrial design reasons, place the same curve on the back side of the window that has an identical radius as the front side. While this will not completely eliminate the lens effect of the front curved surface, it will significantly reduce the effects. The amount of change in the radiation pattern is dependent upon the material chosen for the window, the radius of the front and back curves, and the distance from the back surface to the transceiver. Once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. The following drawings show the effects of a curved window on the radiation pattern. In all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the transceiver to the back surface of the window is 3 mm. Recommended Plastic Materials: Material # Light Transmission Haze Refractive Index Lexan 141 88% 1% 1.586 Lexan 920A 85% 1% 1.586 Lexan 940A 85% 1% 1.586 Note: 920A and 940A are more flame retardant than 141. Flat Window (First Choice) Figure 20. Shape of windows. 17 Curved Front and Back (Second Choice) Curved Front, Flat Back (Do Not Use) For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies, Limited. All rights reserved. 5988-9887EN August 22, 2006