CIRRUS CDB5471

LK\
CDB5471
CDB5471 Evaluation Board and Software
Features
General Description
l Direct
The CDB5471 is an inexpensive tool designed to evaluate the functionality/performance of the CS5471 2channel A/D Converter. In addition to this data sheet, the
CS5471 Data Sheet is required in conjunction with the
CDB5471 Evaluation Board.
Shunt Sensor and Current
Transformer Interface for 3-Phase
Power
l On-Board
Voltage Reference
l On-board
crystal for XIN
Interface to PC
Windows/CVI Evaluation
Software
The CDB5471 includes PC software, allowing the user to
perform data capture (includes option for time domain
analysis, histogram analysis, and frequency domain
analysis). The software also allows real-time RMS calculation/analysis to be performed simultaneously on the
instantaneous data from both channels.
l Lab
-
“Real-Time” RMS calculation
FFT Analysis
Time Domain Analysis
Noise Histogram Analysis
ORDERING INFORMATION
CDB5471
VA-
VA+
CPD
GAIN
OWRS
VIN2+
VIN2-
RESET
VIN3+
VIN3IIN3+
IIN3-
VD+
(Not Populated)
Control Switches
VAVA+
IIN1+
IIN1-
Reset Circuit
FSO
SDO
CLK
SE
IIN2+
IIN2-
Evaluation Board
3V
Regulator
Charge
Pump
Circuitry
VIN1+
VIN1-
GND
+5 VIN
Serial-toParallel
Interface
DB25
l Digital
Two terminal-block connectors serve as inputs to the
CS5471’s two analog input pairs. The CDB5471 includes an optional voltage reference source for CS5471.
A 4.096MHz crystal is provided as a source for CS5471’s
XIN pin, or an external clock source can be supplied by
the user. Digital output data from the CS5471 is transferred to the user’s IBM-compatible PC via the included
25-pin parallel port cable.
To PC
CS5451
Crystal
4.096 MHz
XIN
VREF
IN
OUT
Header
VREF
Voltage
Reference
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 2001
(All Rights Reserved)
FEB ‘01
DS480DB1
1
CDB5471
TABLE OF CONTENTS
1. INTRODUCTION ....................................................................................................................... 4
1.1 CS5471 .............................................................................................................................. 4
1.2 Data Flow on Evaluation Board ......................................................................................... 4
2. HARDWARE ............................................................................................................................. 5
2.1 Evaluation Board Description ............................................................................................. 5
2.2 Power Supply Connections ................................................................................................ 5
2.2.1 Analog Power Supply ............................................................................................ 5
2.2.2 Digital Power Supply ............................................................................................. 5
2.2.3 Charge Pump Options ........................................................................................... 6
2.3 Eval Board Control - Headers/Switches ............................................................................. 6
2.3.1 Analog Inputs ........................................................................................................ 8
2.3.2 Voltage Reference Input ....................................................................................... 9
2.3.3 Clock Source for XIN ............................................................................................. 9
2.3.4 S1 DIP Switch ....................................................................................................... 9
2.3.5 Reset Circuit .......................................................................................................... 9
2.3.6 External Signal In/Out Header .............................................................................. 9
2.3.7 Serial-to-Parallel Interface ..................................................................................... 9
2.3.8 Connecting the Eval Board to PC ....................................................................... 10
3. SOFTWARE ............................................................................................................................ 14
3.1 Installing the Software ...................................................................................................... 14
3.2 Running the Software ...................................................................................................... 14
3.2.1 Getting Started .................................................................................................... 14
3.2.2 The Start-Up Window .......................................................................................... 15
3.2.3 The Conversion Window ..................................................................................... 15
3.2.4 Data Collection Window ...................................................................................... 17
3.2.5 Config Window .................................................................................................... 18
3.2.6 Analyzing Data .................................................................................................... 19
3.2.7 Time Domain Information .................................................................................... 19
3.2.8 Frequency Domain Information ........................................................................... 20
3.2.9 Histogram Information ......................................................................................... 21
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IBM, AT and PS/2 are trademarks of International Business Machines Corporation.
Windows is a trademark of Microsoft Corporation.
Lab Windows and CVI are trademarks of National Instruments.
SPITM is a trademark of Motorola.
MicrowireTM is a trademark of National Semiconductor.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS480DB1
CDB5471
LIST OF FIGURES
Figure 1. Power Supply, CS5471, and Oscillator .............................................. 11
Figure 2. Analog Inputs ..................................................................................... 12
Figure 3. Digital Circuitry ................................................................................... 13
Figure 4. Start-Up Window ................................................................................ 15
Figure 5. Conversion Window ........................................................................... 16
Figure 6. Data Collection Window (Time Domain) ............................................ 17
Figure 7. Configuration Window ........................................................................ 19
Figure 8. Data Collection Window (FFT) ........................................................... 20
Figure 9. Data Collection Window (Histogram) ................................................. 21
Figure 10.Silkscreen ........................................................................................... 22
Figure 11.Circuit Side ......................................................................................... 23
Figure 12.Solder Side......................................................................................... 24
DS480DB1
3
CDB5471
1. INTRODUCTION
The CDB5471 Evaluation Board demonstrates the
performance of the CS5471 6-channel A/D converter.
The CDB5471 evaluation board provides a quick
means of evaluating the CS5471. Analysis software supplied with the CDB5471 allows the user to
observe the CS5471’s digital output data on the user’s PC monitor. The PC software allows the user
to quantify the device’s performance in the timedomain and frequency domain. The user can save
raw data from the CS5471 to a data file, which allows to user to analyze performance with other
tools that may be preferable to the user.
1.1 CS5471
The CS5471 is a highly integrated Two-Channel
Delta-Sigma Analog-to-Digital Converter (ADC)
developed for power measurement/metering applications. However the CS5471 has other potential
uses in various data acquisition applications, particularly in motor/servo control applications which
require very high precision. The CS5471 combines
two delta-sigma modulators with decimation filters, along with a master-mode serial interface on a
single chip device. The CS5471 was designed for
the purpose of performing the A/D conversion operations required at the front-end of a digital singlephase metering system. The six ADC channels can
be thought of as a pair of voltage/current-channel
ADC’s in a digital single-phase power metering application.
The CS5471 contains one programmable gain amplifier (PGA) for the current input. The PGA sets
the maximum input level of the current channel at
±800 mV DC (for gain = 1x) or ±40 mV DC (for
gain = 20x). The voltage channel has only the 1x
gain setting, and so the range of input levels on the
voltage channel is ±800 mV DC.
4
Additional features of CS5471 include a charge
pump driver, on-chip 1.2 V reference, and a digital
input that can select between two different output
word rates. (The two output word rates are equal to
XIN/2048 and XIN/1024.)
The CS5471 requires a 1.2 V reference input on
VREFIN. The ∆Σ modulators and high rate digital
filters allow the user to measure instantaneous voltage and current at an output word rate of 4 kHz (or
2000 kHz, depending on the state of the OWRS
pin) when a 4.096 MHz clock source is used.
1.2 Data Flow on Evaluation Board
The output serial bit-stream from the CS5471 is
shifted into an 8-bit latch circuit so that it can be
quickly ported to the DB25 connector. From this
connector, the data can be sent through the provided 25-pin printer cable to the parallel port of the user’s IBM-compatible PC (the PC must run under
Windows ‘95/’98/2000 operating system).
Once the 8-bit segments of data are ported to the
user’s PC, the LabWindows software (included
with this kit) will re-segment the data into the appropriate 16-bit word format for both of the
CS5471’s two data channels. The data is sent
quickly to the user’s PC, which allows the software
to perform various data processing and graphical illustrations on the digital output data. This includes
real-time RMS, variance, and standard deviation
calculations for both channels. The output data
from each channel can be plotted on-screen in the
time domain or in the frequency domain. A histogram function is also included to help the user to
evaluate the noise characteristics of each channel.
The software can also calculate the mean and standard deviation of the output codes both channels.
This feature allows the user to scrutinize the variation of the A/D converters if the user applies constant DC voltage levels to the inputs. RMS
calculation is also provided to assist in the quick
analysis AC input signals.
DS480DB1
CDB5471
2. HARDWARE
2.1 Evaluation Board Description
The CDB5471 board contains circuitry that will:
• Accept appropriate DC voltage levels from the
user’s +3V and/or +5V power supplies, and
direct this power to the VA+, VD+, VA- and
DGND pins of the CS5471.
• Direct the six analog input signals to the six
input pairs of the CS5471.
• Supply necessary voltage reference input for the
CS5471’s VREFIN pin.
• Supply appropriate crystal/oscillator stimulus to
the CS5471’s XIN pin.
• Direct the output driver signal from the
CS5471’s charge-pump driver pin (CPD) which
is used produce the negative power supply
source for the CS5471’s VA- pin.
• Provide a reset switch that allows the user to set
the CS5471’s RESET pin from logic “1” to logic
“0”.
• Provide two DIP switches which allow the user
to set the logic levels on the CS5471’s GAIN and
OWRS input pins.
• Detect and receive the data frame signal and digital serial output data signals from the CS5471’s
FSO and SDO pins, and send this output data
through the included parallel cable, and up to
user’s PC.
Several areas of blank proto-board space are provided so that, if desired, the user can interface their
own electronic sensor equipment onto the board.
The output from these sensors can be wired to the
two nearby analog input terminal block connectors,
which is then fed to the two analog input channels
of the CS5471. Examples of such sensors would
include voltage and current transformers, shunt resistors, and resistor divider networks.
DS480DB1
The next section of this document describes the
various sections of the board. After this, operation
of the PC software is described in detail.
2.2 Power Supply Connections
The CDB5471 can be used in several different
power supply configurations. Table 1 shows the
various possible power connections with the required jumper settings. There are various +3 V and
+5 V options. The user must supply the +3V, +5V,
GND, and sometimes -2V voltage levels needed to
power the evaluation board.
2.2.1 Analog Power Supply
Referring to Figure 1, the A+ post supplies power
to the positive analog power input pin (VA+) of the
CS5471. This post also supplies power to the
LT1004 voltage reference (D3) and the optional
+3V regulator (U5). If HDR9 is set to the “A-” setting, the A- post can supply the required negative
voltage to the VA- pin of the CS5471.
Note that the evaluation board contains the footprints and connectivity which allows the user to install a LM317 voltage regulator (U5), which can be
used to create +3 V from a +5 V supply. This option is useful if the user wants to interface the evaluation board to another board that can only operate
from a +5V supply. With HDR17 set to “+5V_IN”,
one single +5 V supply can be used to provide both
a +5V to various microcontrollers and/or other peripheral devices, as well as +3 V for the CS5471.
The included schematic diagram shows the circuitry for the +5V regulator circuitry inside a box with
dashed lines. These components are not populated
when the board is shipped from the factory, but the
user can install these components if desired.
2.2.2 Digital Power Supply
The A+ post can be used to supply both the analog
power (to CS5471 VA+ pin) as well as the digital
power (to CS5471 VD+ pin). However if a separate supply voltage is desired for the digital power
5
CDB5471
supply, the “VD+” banana connector post can be
used to independently supply a separate digital
power supply to the input of the CS5471 (VD+
pin), the 4.096 MHz oscillator (U1), and circuitry
for the parallel port interface. This is controlled by
the setting on HDR18.
The user should note that the CS5471 can operate
with a digital supply voltage of either +3V or +5V.
This voltage is defined as the voltage presented
across VD+ and DGND.
2.2.3 Charge Pump Options
The output from CS5471’s charge-pump driver pin
(CPD) can be used to generate a -2V supply when
the proper jumper settings are selected on HDR9.
This -2V supply can be used as the negative power
supply connection for the CS5471’s VA- pin. RePower Supplies
ferring to Figure 1, circuitry for a charge-pump circuit is included on-board. The charge pump circuit
consists of capacitors C11, C12, and C36, and diodes D1 and D2.
As an alternative to using the charge pump circuit,
the user can supply an off-board -2V DC power
source to the “A-” banana connector. This option
is controlled by the setting on HDR9.
2.3 Eval Board Control - Headers/Switches
Table 2 lists the various adjustable headers and
switches on the CDB5471 Evaluation Board, as
well as their default settings (as shipped from the
factory). The header settings can be adjusted by the
user to select various options on the evaluation
board. These options are described further in the
following paragraphs.
Power Post Connections
Analog
Digital
A+
A-
GND
D+
+5 V_IN
HDR9
HDR17
HDR18
+3
+3
+3
-2
0
+3
NC
A- O O
CPD O O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
+3
+3
+3
-2
0
NC
NC
A- O O
CPD O O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
+3
+3
+3
NC
0
+3
NC
AO
CPD O
O
O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
+3
+3
+3
NC
0
NC
NC
AO
CPD O
O
O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
+3
+3
NC
-2
0
NC
+5
A- O O
CPD O O
+5V_IN O
O
A+
O
O
VD+ O
V+ O
O
O
+3
+3
NC
NC
0
NC
+5
AO
CPD O
O
O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
+3
+5
+3
-2
0
+5
NC
A- O O
CPD O O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
+3
+5
+3
NC
0
+5
NC
AO
CPD O
O
O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
+3
+5
NC
-2
0
+5
+5
A- O O
CPD O O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
+3
+5
NC
NC
0
+5
+5
AO
CPD O
O
O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
+5
+3
+5
0
+2
+5
NC
A- O O
CPD O O
+5V_IN O
A+
O
O
O
VD+ O
V+ O
O
O
Table 1. Power Supply Connections
6
DS480DB1
CDB5471
Name
Function Description
Default Setting
Default Jumpers
HDR1
Used to switch IIN3+ on the CS5471 between J2
and AGND.
IIN3+ Set to BNC J2
O
O
O IIN3+
O AGND
HDR2
Used to switch VIN3- on the CS5471 between J3
and AGND.
VIN3- Set to BNC J3
O
O
O VIN3O AGND
HDR3
Used to switch VIN3+ on the CS5471 between J1
and AGND.
VIN3- Set to BNC J1
O
O
O VIN3+
O AGND
HDR4
Used to switch IIN3- on the CS5471 between J4
and AGND.
IIN3- Set to BNC J4
O
O
O IIN3O AGND
HDR5
Used to switch VIN2- on the CS5471 between J6
and AGND.
VIN2- Set to BNC J6
O
O
O VIN2O AGND
HDR6
Used to switch IIN2+ on the CS5471 between J7
and AGND.
IIN2+ Set to BNC J7
O
O
O IIN2+
O AGND
HDR7
Used to switch IIN2- on the CS5471 between J5
and AGND.
IIN2+ Set to BNC J5
O
O
O IIN2O AGND
HDR8
Used to switch VIN2+ on the CS5471 between J8
and AGND.
VIN2+ Set to BNC J8
O
O
O VIN2+
O AGND
HDR9
Used to switch between external VA- and on-board
CS5471 charge-pump circuit, CPD
CPD active
HDR10
Used to switch VIN1+ on the CS5471 between J9
and AGND.
VIN1+ Set to BNC J9
O
O
O VIN1+
O AGND
HDR11
Used to switch IIN1- on the CS5471 between J12
and AGND.
IIN1- Set to BNC J12
O
O
O IIN1O AGND
HDR12
Used to switch IIN1+ on the CS5471 between J10
and AGND.
IIN1- Set to BNC J10
O
O
O IIN1+
O AGND
SW1
S1-1 sets logic level on CS5471 GAIN input pin
S1-2 sets logic level on CS5471 OWRS input pin
SW1-2 Open (GAIN=x1)
SW1-1 Open (XIN/1024)
A- O
CPD O
O
O
2
3
OPEN
HDR13
Used to switch VIN1- on the CS5471 between J11
and AGND.
VIN1- Set to BNC J11
HDR14
Used to switch the VREFIN from external VREF
post connector, to the on board LT1004 reference,
or to the on-chip reference VREFOUT. Refer to
Table 3.
VREFIN Set to onchip reference
VREFOUT
O
O
O
O
O
O VIN1O AGND
O LT1004
O VREFOUT
O EXT VREF
Table 2. Default Header Settings
DS480DB1
7
CDB5471
Name
Function Description
Default Setting
HDR15
Controls the source for the CS5471 XIN clock input.
Set to on-board 4.000
MHz crystal (U1).
HDR16
This header should always be shorted.
HDR17
HDR18
Determines whether the main analog supply will be
powered from the A- post, or from the regulated 3V
voltage (generated from the +5V_IN) post input.
Choose whether the digital circuitry will be powered
by main analog supply, or powered by separate digital supply (through VD+ post).
Default Jumpers
O
O
O
O EXT XIN
O DGND
O 4.0096 MHz
OSC
Short this header
O
O
Set to A-
O
O
O +5V_IN
O A+
Set to main analog
supply
VD+ O
V+ O
O
O
Table 2. Default Header Settings (Continued)
2.3.1 Analog Inputs
Refer to Figure 2. The settings on the 14 analog input headers (2 headers per channel) which are designated as HDR10 through HDR13, determine
which of the input lines will carry a signal, and
which input lines may be grounded. They can be
configured to accept either a single-ended or differential signal. Using the voltage channel as an example (see Figure 2), note that HDR10 sets the
input to the positive side of the first voltage channel
input (VIN1+ pin). HDR13 sets the input to the
negative side of the first voltage channel input
(VIN1- pin). In a single-ended input configuration,
HDR13 would be set to the “AGND” setting, and
HDR10 would be set to “VIN1+” and would conduct the single-ended signal. In a differential input
configuration, HDR13 would be set to “VIN1-”
and HDR10 would be set to “VIN1+” and this pair
of inputs would form the differential input pair into
the VIN1+ and VIN1- pins of the CS5471.
WARNING: DANGER! One of the possible applications for the CS5471 includes data acquisition
for a power metering system. However, the user
should not attempt to directly connect any leads
from a high-voltage power line to the evaluation
board inputs, even if the current/voltage levels are
gain reduced by resistive dividers and/or shunts.
Because the ground terminal of the parallel cable
(from the PC) is near or at earth ground potential,
8
the ground node on the evaluation board will also
be forced to earth ground potential. Serious damage and even personal injury can occur if a “hot”
voltage main is connected to any point on the evaluation board, including the analog input connectors. Such power line signals must be isolated by
current/voltage transformers and reduced in magnitude before they can be safely applied to the evaluation board.
Several patch-circuit areas are provided near the
voltage/current input headers, in case the user
wants to connect special sensor circuitry to the analog inputs (such as transformers, shunt resistors,
etc., for sensory the voltage/current on a singlephase power line). For the input channel, a Shunt
Resistor or Current Transformer can be mounted in
these areas and connections can be made to currentchannel input pair. Likewise, the three channels, a
Voltage Divider or Voltage Transformer can be
connected to the CS5471’s voltage input pair. Note
from Figure 2 that a simple R-C network filters
each sensor’s output to reduce any interference
picked up by the input leads. The 3 dB corner of the
filter is approximately 50 kHz differential and
common mode.
Note that the CDB5471 Evaluation Board is also
used as the evaluation board for the CS5451 A/D
converter, which is a 6-channel version of the
CS5471. The user can use this board to the evaluDS480DB1
CDB5471
ate CS5451 by obtaining a CS5451 sample and
connect it in place of the CS5471 device. Then the
remaining four input channels serve as the inputs to
the CS5451’s four additional input pairs.
Other header options listed in Table 2 allow the
user to set the source of the input clock signal and
the source of the voltage reference (VREFIN) input, etc. The voltage reference options and clock
input options are discussed next.
2.3.2 Voltage Reference Input
To supply the CS5471 with a suitable 1.2 V voltage
reference input at the VREFIN pin, the evaluation
board provides three voltage reference options: onchip, on-board, and external. See HDR14 as shown
in Figure 1. Table 3 illustrates the available voltage
reference settings for HDR14. With HDR14’s
Reference
Description
Select on board
LT1004 Reference
LT1004
(5 ppm/°C)
Select reference supVREFOUT plied from CS5471
VREFOUT pin
EXTVREF
Select external
reference
Referring to Figure 3, the two single-pole singlethrow switches on SW1 DIP switch should be used
to control the logic settings on the CS5471’s
OWRS pin and GAIN pin. When these SW1
switches are set to “OPEN” the corresponding pin
on CS5471 is set to D+ potential, which creates a
logic-high state. When the user closes either of
these SW1 switches, the corresponding pin on
CS5471 is grounded, which creates a logic-low
state on the pin.
2.3.5 Reset Circuit
Circuitry has been provided which allows the user
to execute a hardware reset on the CS5471. (See
Figure 3). By pressing on the S1 switch, the RESET pin on the CS5471 will be held low until the
switch is released.
HDR14
O
O
O
O
O
O
LT1004
VREFOUT
EXT VREF
O
O
O
O
O
O
LT1004
VREFOUT
EXT VREF
O
O
O
O
O
O
LT1004
VREFOUT
EXT VREF
Table 3. Reference Selection
jumpers in position “VREFOUT,” the CS5471’s
on-chip reference provides 1.2 volts. With HDR14
set to position “LT1004,” the LT1004 provides
1.23 volts (the LT1004 temperature drift is typically 50 ppm/°C). By setting HDR14’s jumpers to position “EXT VREF,” the user can supply an
external voltage reference to J16 connector post
(VREF) and AGND inputs.
2.3.3 Clock Source for XIN
A 4.000 MHz crystal is provided to drive the XIN
input of the CS5471. (See Figure 1.) However, the
user has the option to provide an external oscillator
signal for XIN, by switching the setting of HDR15.
DS480DB1
2.3.4 S1 DIP Switch
2.3.6 External Signal In/Out Header
Note that HDR16 is included on the CDB5471
Evaluation Board as a header that is normally left
unconnected. This header provides a way for the
user to interface the CDB5471 Evaluation Board to
other prototype boards, calibrators, logic analyzers,
other peripherals, etc. in order to further evaluate
the CS5471 device and/or to use the evaluation
board as a platform for the prototype development
of a digital power metering solution. However,
note that the CDB5471 Evaluation Board is not intended to be integrated directly into a commercial
digital power meter. The layout of the board is not
optimized for practical power metering situations.
2.3.7 Serial-to-Parallel Interface
Glue-logic on the evaluation board converts the
CS5471 serial data into 8-bit segments (bytes).
The bytes are sent to the DB25 connector (J17), and
then through the standard printer cable to the user’s
PC. This section briefly describes the operation of
the digital circuitry on the CDB5471 that provides
the 8-bit parallel data to the PC. Refer to Figure 3.
9
CDB5471
The user should recall from CS5471 Data Sheet
that the serial interface on the CS5471 device is a
“master-mode” interface, which means that the device provides the clock. Once the CS5471 is powered on, the SCLK pin produces a clock signal, and
data is sent out on the SDO pin of the device. When
the evaluation software is instructed (by the user) to
acquire data through the parallel interface, a twostep process is performed: First the software synchronizes itself to the frame rate of the CS5471,
then the software acquires multiple frames of data
from the CS5471.
2.3.7.1. Synchronization
When the software is commanded to acquire data,
the software will first synchronize itself to the
frame rate of the CS5471 (see CS5471 Data Sheet).
This is done by measuring the amount of time between rising and falling edges of the “BUSY” signal. (BUSY will change state every time the
CS5471 issues eight SCLKs--See next section for a
more detailed description.) By measuring this time
period, the software can determine the idle period
of the frame, which allows it to be prepared to collect a complete frame’s worth of data when the next
CS5471 frame is received. This acquisition sequence is described next.
2.3.7.2. Acquisition
Referring to Figure 3, the CS5471’s SCLK line is
used to clock the 8-bit serial-in/parallel-out shiftregister (U7) which accepts the serial data on SDO
and shifts it into the 8 output bits QA-QG. The
SCLK signal is also fed into the up/down counter
U6 and after every 8 SCLKs, the “QC” pin of U6
will latch the QA-QG output bits of U6 into the 8bit D-Flip-Flop (U3). While this is happening, the
software monitors the “BUSY” signal (from the
“QD” pin of U6). BUSY is the critical handshake
signal. A rising or falling transition on BUSY indicates to the software that it is now time to collect
another byte of data from the latched output on U3.
10
After sixteen SCLKs, the PC software has acquired
two bytes (16 bits) which represents one data sample. The 4-bit up/down counter (U6) will roll over
after every 16 SCLKs. (Note that U6 is cleared by
the CS5471’s FSO signal at the beginning of each
frame, which insures that the counter begins the
frame in the correct state--cleared). This sequence,
which lasts for 16 SCLKs, is performed a total of
six times, although only the first two repetitions of
this sequence are relevant. In the first two sequences, the two 16-bit words from the CS5471 are acquired by the PC. The data contained in the
remaining four sequence executions will be meaningless, as the state of the CS5471’s SDO pin is be
undefined during the last 64 clocks of each data
frame.
After the sixth 16-bit word is acquired, the software
recognizes that the end of a data frame has been
reached, and it will continue to wait for the next
transition on the “BUSY” line. This will not occur
until the first 8 SCLKs of the next frame are sent
from the CS5471. Various other signals in Figure
3 (STRB, FEED, ACK, etc.) are not used during
data capture and are only used for testing (internal
use only).
2.3.8 Connecting the Eval Board to PC
The CDB5471 connects to the user’s IBM-compatible PC with the included 25-pin parallel port cable.
The user should not connect this cable between
the CDB5471 and the parallel port on the PC until
all of the header options in Table 2 have been set
to appropriate settings and the user has applied
power to the CDB5471. The parallel cable attached to the CDB5471 Evaluation Board at J17.
After connecting the parallel port cable between
the PC and CDB5471, the user should always actuate (press down on) the “RESET” switch (S1) at
least one time before performing any other evaluation activities.
DS480DB1
TP40
TP77
LM317LZ
IN
3
OUT
ADJ
C40
C41
.1UF
22UF
1
.1UF
C38
D+
GND
U4
SCLK
SDO
FSO
SE
/GAIN
R30
CON_BANANA
GND
GND
J18
C20
GND
VIN3+
VIN3IN3+
IN3-
.1UF
+3V
HDR17
HDR2X2
CON_BANANA
A+
J14
Z2
C13
47UF
P6KE6V8P
3
4
1
2
V+
C17
R3
4.99K
TP40
TP1
2
GND
C37
D3
LT1004
1.2V
1
4
3
6
5
GND
SCLK
VD+
SDO
DGND
FSO
CPD
XIN
SE
/GAIN
/RESET
AGND
OWRS
VREFIN
VIN1+
VREFOUT
VIN1-
VA+
IIN1+
VA-
IIN1-
VIN3+
VIN2+
VIN3-
VIN2-
IN3+
IIN2+
14
IN3-
1
2
3
4
5
6
7
8
9
10
11
12
13
SCLK
SDO
FSO
SE
/GAIN
TP40
TP76
+3V
C19
3
1
2
3
4
5
6
7
8
9
10
11
12
13
IIN2-
TP79
TP73
TP74
TP14
TP17
TP19
TP21
TP23
TP25
TP27
TP29
TP31
TP33
TP35
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TP78
TP72
TP75
TP15
TP16
TP18
TP20
TP22
TP24
TP26
TP28
TP30
TP32
TP34
C21
3
4
CON_BANANA
VD+
C14
C22
XIN
/RESET
OWRS
VIN1+
VIN1IIN1+
IIN1VIN2+
VIN2IIN2+
IIN2-
10UF
Z3 J20
P6KE6V8P
C23
47UF
.1UF
.1UF
GND
GND
U2
HDR3X2
HDR14
2
TP37
TP39
TP41
TP43
TP45
TP47
TP49
TP51
TP53
TP55
TP57
TP59
TP61
TP63
SSOP28_200_P65MM
4.7UF
TANT
L1
10
FERRITE_BEAD
R2
.1UF
CON_BANANA
GND
TP36
TP38
TP40
TP42
TP44
TP46
TP48
TP50
TP52
TP54
TP56
TP58
TP60
TP62
2
C16
.1UF
GND
VIN3+
VIN3IN3+
IN3-
.1UF
SCLK
VD+
SDO
DGND
FSO
CPD
XIN
SE
/RESET
/GAIN
AGND
OWRS
VREFIN
VIN1+
VREFOUT
VIN1-
VA+
IIN1+
VA-
IIN1-
VIN3+
VIN2+
VIN3-
VIN2-
IN3+
IN3-
IIN2+
14
IIN2-
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XIN
/RESET
OWRS
VIN1+
VIN1IIN1+
IIN1VIN2+
VIN2IIN2+
IIN2-
J13
.33UF
TANT
1
GND
Do Not Populate
V+
HDR18
HDR2X2
HDR1X2
HDR16
1 2
HDR3X2
HDR15
4.0960MHZ
GND
EXT VREF
TP2
TP40
C18
7
GND
2
1
4
3
6
5
XIN
8
D+
TANT
4.7UF
C36
GND
J16
GND
EXT_IN
SKT_SSOP28_ENP
GND
BNC_RA
GND
140
R31
10UF
C39
R29
C42
Z4
P6KE6V8P
3.0V
2
J21
1K
+5V_IN
100
DS480DB1
U5
+5V
CON_BANANA
R32
10
.1UF
14
VCC
U1
CON_BANANA
GND
C2.1UF
Z1
P6KE6V8P
C15
47UF
C1
.1UF
2
4
GND
3
J15
1
HDR2X2
HDR9
A-
D2
BAT85
C11
.039UF
TANT
2.2UF
D1
BAT85
C12
Figure 1. Power Supply, CS5471, and Oscillator
11
CDB5471
GND
GND
12
J22
1
2
3
4
TP67
J5
R23
BNC_RA
HDR2X2
HDR7
301
0.1%
C8
R22
BNC_RA
2
3
4
HDR2X2
HDR6
301
0.1%
1
2
3
4
J6
R21
BNC_RA
HDR2X2
HDR5
301
0.1%
C7
J8
R24
BNC_RA
1
2
3
4
HDR2X2
HDR8
301
0.1%
1
2
3
4
VIN2-
C26
GND
VIN2+
C27
J25
1
2
3
4
GND
.01UF
GND
GND
IIN2+
C25
.01UF
GND
4700PF TP64
GND
.01UF
GND
TP65
IIN2-
C24
.01UF
GND
4700PF TP66
J7
1
GND
1
2
3
4
J23
J24
1
2
3
4
TP71
TP4
R26
BNC_RA
HDR2X2
HDR11
301
0.1%
BNC_RA
3
4
HDR2X2
HDR12
301
0.1%
1
2
3
4
BNC_RA
1
3
C10
R25
BNC_RA
J3
IIN1+
R18
BNC_RA
J2
VIN1-
R17
BNC_RA
3
4
J4
VIN1+
R20
1
2
3
4
BNC_RA
HDR2X2
HDR4
C31
GND
.01UF
GND
IN3+
C34
.01UF
GND
301
0.1%
VIN3-
C33
.01UF
C30
GND
GND
1
2
3
4
GND
IN3-
C35
.01UF
1
2
3
4
2
4
GND
DS480DB1
GND
J26
GND
Figure 2. Analog Inputs
J27
GND
CDB5471
GND
1
2
3
HDR2X2
HDR1
301
0.1%
4700PF TP68
HDR2X2
HDR10
1
GND
GND
VIN3+
C32
.01UF
C29
C5
301
0.1%
4
HDR2X2
HDR2
301
0.1%
.01UF
GND
4700PF TP3
J9
GND
2
4
2
3
GND
.01UF
HDR2X2
HDR13
301
0.1%
1
C28
TP69
TP6
R28
BNC_RA
HDR2X2
HDR3
4700PF TP70
GND
J11
IIN1-
301
0.1%
.01UF
GND
4700PF TP5
R27
2
R19
C6
C9
J10
1
J1
1
2
3
4
J12
GND
D+
1
DATA B
2
3
4
5
HDR7X2
HDR19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
QB
DATA A
QA
CLR
CD
BORROW
CU
6
CARRY
QC
LOAD
QD
DATA C
GND
DATA D
7
8
16
15
R8
14
470
FSO
13
12
11
D+
10
9
MM74HC193N
GND
R6
OWRS
/RESET
/GAIN
SE
FSO
SCLK
SDO
D+
U6
10K
DS480DB1
C43 .1UF
BUSY
GND
INIT
U8
GND
R15
19
4.7K
R7
11
13
15
17
470
D+
2/G
2A1
2A2
2A3
2A4
9
7
5
3
2Y1
2Y2
2Y3
2Y4
R9
470
SE
ACK
C45
10K
10K
SN74HC240N
220PF
COG
DB25M_RA
J17
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
GND
SW1
2
1
GND
GND
QG
QF
QE
QD
QC
QB
QA
/RESET
R10
R36
SDO
470
20K
B
A
CLK
/CLR
VCC
13
12
11
10
6
5
4
3
18
17
14
13
8
7
4
3
8D
7D
6D
5D
4D
3D
2D
1D
14
11
1
CLK
/OC
U7
49.9
C46 .1UF
S1
SW_B3W_1100
GND
GND
R37
2
1
8
9
7
C4
GND
VCC
10
20
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
19
16
15
12
9
6
5
2
D+
U3
D+
C3 .1UF
R13
4.7K
SEL
GND
10K
D+
.1UF
SN74HC374N
SN74HC164N
SW_DIP_2
GND
10K
10K
OPEN
R35
R34
R16
/GAIN
OWRS
R33
GND
D+
10K
10K
R5
R1
GND
C44
R4
GND
.1UF
D+
U8
D+
20
SCLK
R11
470
18
16
14
12
10
VCC
1/G
1Y1
1Y2
1Y3
1Y4
1A1
1A2
1A3
1A4
R12
R14
4.7K
4.7K
STRB
FEED
13
CDB5471
Figure 3. Digital Circuitry
2
4
6
8
GND
SN74HC240N
GND
1
CDB5471
3. SOFTWARE
Note:
The evaluation software was developed with Lab
Windows/CVI, a software development package
from National Instruments. The software is designed to run under Windows 95 or later, and requires about 3 MB of hard drive space (2 MB for
the CVI Run-Time Engine, and 1 MB for the evaluation software). After installing the software, read
the readme.txt file for any last minute updates or
changes. More sophisticated analysis software can
be developed by purchasing the development package from National Instruments (512-794-0100).
3.2 Running the Software
3.1 Installing the Software
Installation Procedure:
1) Turn on the PC, running Windows 95 or later.
2) Insert the Installation Diskette #1 into the PC.
3) Select the Run option from the Start menu.
4) At the prompt, type: A:\SETUP.EXE <enter>.
5) The program will begin installation.
6) If it has not already been installed on the PC,
the user will be prompted to enter the directory
in which to install the LabWindows CVI RunTime Engine. The Run-Time Engine manages executables created with Lab Windows/CVI. If the default directory is
acceptable, select OK and the Run-Time Engine will be installed there.
7) After the Run-Time Engine is installed, the
user is prompted to enter the directory in which
to install the CDB5471 software. Select OK to
accept the default directory.
8) Once the program is installed, it can be run by
double clicking on the EVAL5451 icon, or
through the Start menu.
14
The software is written to run with 640 x 480
resolution; however, it will work with 1024 x 768
resolution. If the user interface seems to be a little
small, the user might consider setting the
display settings to 640 x 480. (640x480 was
chosen to accommodate a variety of
computers).
3.2.1 Getting Started
The CDB5471 Evaluation software allows the user
to obtain, display, and save data that is acquired by
the CS5471 chip. Before running the software, the
first step is to make sure that all of the headers that
are listed in Table 2 are set to an appropriate setting, the exact setting should be determined by the
user. Next, with the user’s DC power supplies still
turned off, the user should connect the necessary
power leads to the banana jack power connectors
on the evaluation board. Refer to Table 1 for various acceptable power supply connection configurations. Then at this time the user should turn on their
DC power supplies, which should apply power to
the CDB5471. Several test point locations are
available on the evaluation board. The user can
check these test points with a voltmeter, to make
sure that the voltages at these test points are at the
expected levels. When the user has verified that the
power supply levels are constant, the user should
connect the included 25-pin cable between J17 of
the evaluation board and the parallel port on the user’s PC. The user should then press down on the S1
“RESET” switch, and make sure to hold it down for
at least ~0.5 seconds before releasing. Finally, the
user can start the PC software. To start the software, double click on the EVAL5451 icon, or initiate through the Start menu.
DS480DB1
CDB5471
Figure 4. Start-Up Window
3.2.2 The Start-Up Window
When the software first executes, the user should
see the Start-Up Window appear on the user’s PC
monitor. This window is shown in Figure 4. From
this window, the user can navigate to three other
main windows: the Conversion Window, the Data
Collection Window, and CS5471 Pinout Diagram.
(The CS5451 Pinout Diagram is also included in a
fourth window.) To navigate to these windows, use
the mouse to click on the “Menu” item, which is located towards the upper left corner of the Start-Up
Window. “Menu” is a pull-down menu which contains four options. From this pull-down menu, the
user can select any of the three windows mentioned
above, and once this is done, the new window
should appear. A fourth option called “Exit”
should be selected when the user wants to terminate
execution of the evaluation board software program.
If the user selects the “CS5471 Pinout Diagram”
option in the “Menu” pull-down, the software will
DS480DB1
display a window which contains the pin diagram
of the CS5471. This pin diagram is included for the
user’s reference. Note that this window has no actual functionality.
The functionality of the Conversion Window and
the Data Collection Window is described next.
3.2.3 The Conversion Window
Refer to Figure 5. After the user presses on the
green-colored “START” button in this window, the
software will begin to collect data for both channels
of the CS5471. For each channel, a certain number
of instantaneous data samples from the CS5471 are
bundled together. The period over which each bundle of samples is taken is called a “computation cycle.”
The user controls the number of
instantaneous data samples that will be taken (per
channel) during one computation cycle by adjusting the number in the box labeled “Evaluation Software Cycle Count:.” Note that the default value for
this is set to 4000. Thus during every computation
cycle, the PC software will acquire 4000 samples
15
CDB5471
(from both channels) and it will update the onscreen results of both channels after calculating the
results on each successive set of 4000 samples.
The results that are displayed on this screen are
therefore updated after each computation cycle.
Note that the results in the very first computation
cycle (after the “START” button has been activated) will not be valid. Accuracy of the Mean, Std.
Dev. and RMS results will increase as the “Samples to Average” value is increased.
The user should understand how to interpret the
values that are displayed in the array of number
boxes in the Conversion Window. For CDB5471,
only the results displayed in the “Voltage 1” and
“Current 1” rows are valid. The result values
that are displayed in these numeric output boxes are
all expressed on a normalized scale. The highest
value (0.999...) represents the highest digital output
code that can be issued from the CS5471 (which is
+32767), while the lowest value -0.999... represents the most negative output code that can be issued from the CS5471 (which is -32768). This is
because the CS5471 issues instantaneous output
codes as two’s complement 16-bit words. Therefore, the range of values that can be returned from
the CS5471 are between -32768 and +32767. The
CS5471 issues instantaneous data, and every computation cycle, the software computes/displays the
quantities which are described below:
Figure 5. Conversion Window
16
DS480DB1
CDB5471
Figure 6. Data Collection Window (Time Domain)
3.2.3.1. Last Value
3.2.3.4. RMS
The first column is labelled as “Last Value.” The
value in this box represents the value of the very
last instantaneous sample that was taken (for both
channels) in the most recently-completed computation cycle. If the user’s analog input waveforms are
AC in nature, then this column of results will rarely
have any meaning. But if the user applies a constant DC input signal to any of the analog input
channels, then the Last Value column for that channel should display an output code that is relatively
constant from one conversion cycle to the next.
The values in this column represent the computed
RMS value over the most recently-completed computation cycle.
3.2.3.2. Mean
3.2.4.1. Collect Button
The values in this column represent the simple average
of the sample values in the latest computation cycle.
This button will collect data from the CS5471, to be
analyzed in the plot area. See the section on Collecting Data Sets for more information.
3.2.3.3. Std Dev.
3.2.4 Data Collection Window
The Data Collection Window (Figs 6, 8, and 9) allows the user to collect samples sets of data from
CS5471 and analyze them using time domain, FFT,
and histogram plots. The Data Collection Window
is accessible through the Menu option, or by pressing F4.
The values in this column represent the computed
standard deviation over the set of values in the most
recent computation cycle.
DS480DB1
17
CDB5471
3.2.4.2. Time Domain / FFT / Histogram
Selector
This selector button is located just to the right of the
Collect Button. The label on this button will
change as the user selects which analysis is to be
performed (“Time Domain” or “FFT” or “Histogram”). When the software is first started, the default mode on this selector button is Time Domain.
This user should click on this button to select which
type of data processing to perform on the collected
data and display in the plot area. Refer to the section on Analyzing Data for more information.
3.2.4.3. “Crystal” Value Indicator Box
The value in this box reflects the frequency of the
CS5451’s clock input (at the XIN pin). Since the
XIN frequency affects the sampling rate (the output
word rate) of the CS5451, this information must be
specified to the software so that it can accurately
depict the frequency-content of the sampled data
(in Hz) when performing an FFT analysis. The
user can enter the crystal frequency that is used on
the CDB5451 board into this box. The default value of this box is set for the on-board 4.096MHz oscillator.
3.2.4.4. OWRS Pin Setting:
This switch should be adjusted whenever the user
toggles the S1-1 DIP switch (on the evaluation
board). The default setting of this switch is HI, corresponding to the default setting on S1-1 (default
setting is “OPEN”). S1-1 drives the CS5471’s
OWRS pin to logic “1”. A logic “1” on OWRS sets
the sampling frequency of both CS5471 input
channels to XIN/1024. To toggle the state of the
on-screen switch, simply click on the switch with
the mouse.
3.2.4.5. Config Button
This button will bring up the configuration window
(shown in Fig 7) in which the user can modify the
data collection specifications. See the discussion
of the Config Window in this document.
18
3.2.4.6. Save Button
The red-colored SAVE button will save the data in
the current plot to a file. The exact path and filename can be specified by the user in the text window
located just to the left of the SAVE button. The
data collected for both channels will be saved to a
text file.
3.2.4.7. Load Button
The green colored LOAD button will load any data
file that was previously generated by clicking on
the red SAVE button. The exact path and filename
must be specified by the user in the text window located just to the left of the LOAD button.
3.2.4.8. Channel Selector Buttons
Clicking on buttons labeled as “V1” and “I1” will
display a certain channel of data. “V1” refers to the
voltage data taken across the Vin1+/Vin1- pins of
the CS5471. In a similar manner, clicking on the
“I1” button will display the data representing the
voltage level across the current channel input pins
(Iin1+/Iin1-).
3.2.5 Config Window
See Figure 7. Clicking on the Config button will
bring up a small pop-up window called the Config
Window. The Config Window allows the user to
set up the data collection and analysis parameters,
which are described next.
3.2.5.1. Number of Samples
This box allows the user to select the number of
samples to collect. The user can choose any wholenumber power of 2 between 16 and 32768.
3.2.5.2. Average
When performing FFT processing, this box will determine the number of FFTs to average. FFTs will
then be collected and averaged when the user clicks
on the Collect Button.
DS480DB1
CDB5471
all six channels). The number of samples that are
actually saved is equal to the number specified in
the Number of Samples box.
3.2.5.6. Ready Button
After the user has adjusted the parameters in the
Config Window to the desired settings, the user
must click on the READY button to close the Config Window and return to the Data Collection Window.
3.2.6 Analyzing Data
Figure 7. Configuration Window
3.2.5.3. FFT Window
This box allows the user to select the type of windowing algorithm for FFT processing. Windowing
algorithms include the Blackman, Black-Harris,
Hanning, 5-term Hodie, and 7-term Hodie. The 5term Hodie and 7-term Hodie are windowing algorithms developed at Cirrus Logic.
3.2.5.4. Histogram Bin Width
This box allows for a variable “bin width” when
plotting histograms of the collected data. Each vertical bar in the histogram plot will contain the number of output codes contained in this box.
Increasing this number may allow the user to view
histograms with larger input ranges.
3.2.5.5. Samples to Discard
This number represents the number of CS5471
sample periods that will be ignored before the software starts to collect samples (when the user presses on the Collect Button). After the software has
skipped over this many data samples, the software
will then begin to save samples from the device (for
DS480DB1
The evaluation software provides three types of
analysis tests - Time Domain, Frequency Domain,
and Histogram. The Time Domain analysis processes acquired conversions to produce a plot of
Output Code versus Conversion Sample Number.
The Frequency Domain analysis processes acquired conversions to produce a magnitude versus
frequency plot using the Fast-Fourier transform
(results up to Fs/2 are calculated and displayed).
The Histogram analysis test processes acquired
conversions to produce a histogram plot. Statistical
noise calculated are also calculated and displayed.
3.2.7 Time Domain Information
The following controls and indicators are associated with the Time Domain Analysis. Time domain
data can be plotted in the Data Collection Window
by setting the Time Domain / FFT / Histogram selector to “Time Domain.”
3.2.7.1. Count
Displays current x-position of the cursor on the
time domain display.
3.2.7.2. Magnitude
Displays current y-value of the cursor on the time
domain display.
3.2.7.3. Maximum
Indicator for the maximum value of the collected
data set.
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CDB5471
3.2.7.4. Minimum
3.2.8.3. S/D
Indicator for the minimum value of the collected
data set.
Indicator for the Signal-to-Distortion Ratio, 4 harmonics are used in the calculations (decibels).
3.2.8 Frequency Domain Information
3.2.8.4. SINAD
The following section describes the indicators associated with FFT (Fast-Fourier Transform) analysis. Refer to Figure 8. FFT data can be plotted in
the Data Collection Window by setting the Time
Domain / FFT / Histogram selector button to
“FFT.”
Indicator for the Signal-to-Noise + Distortion Ratio
(decibels).
3.2.8.1. Frequency
3.2.8.6. S/PN
Displays the x-axis value of the cursor on the FFT
display.
Indicator for the Signal-to-Peak Noise Ratio (decibels).
3.2.8.2. Magnitude
3.2.8.7. FS-PdB
Displays the y-axis value of the cursor on the FFT
display.
Not using windowing, how far down from zero the
peak voltage input value is (decibels).
3.2.8.5. SNR
Indicator for the Signal-to-Noise Ratio, first 4 harmonics are note included (decibels).
Figure 8. Data Collection Window (FFT)
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3.2.9 Histogram Information
3.2.9.4. Variance
See figure 9. The following is a description of the
indicators associated with Histogram Analysis.
Histogram can plotted in the Data Collection Window by setting the Time Domain / FFT / Histogram
selector to “Histogram.”
Indicator for the calculated variance of the collected data set.
3.2.9.1. Bin
Displays the x-axis value of the cursor on the Histogram.
3.2.9.2. Magnitude
Indicator for the maximum value of the collected
data set.
3.2.9.3. Mean
3.2.9.5. STD_DEV
Indicator for the calculated standard deviation of
the collected data set.
3.2.9.6. Maximum
Indicator for the maximum value of the collected
data set.
3.2.9.7. Minimum
Indicator for the minimum value collected in the
data set.
Average value of the collected data set.
Figure 9. Data Collection Window (Histogram)
DS480DB1
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CDB5471
Figure 10. Silkscreen
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DS480DB1
CDB5471
Figure 11. Circuit Side
DS480DB1
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Figure 12. Solder Side
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DS480DB1
• Notes •