CRD4202-2 AC '97 Six Channel CNR Audio Reference Design with PLL Features Description Phase Locked Loop (PLL) Codec Operation Six Channel Analog Audio Outputs Headphone Sense using GPIO CS4202 codec and two CS4334 DACs 20-bit D to A conversion (DAC) 18-bit A to D conversion (ADC) S/PDIF (IEC-958) optical digital output Complete suite of Analog I/O connections: The CRD4202-2 reference design eliminates the cost of the 24.567 MHz crystal by operating the CS4202 in Phase Locked Loop (PLL) mode. This reference design also features six channel analog audio outputs, an optical S/PDIF digital output, and Communication and Networking Riser (CNR) interface. This design uses the CS4202 audio codec which has several advanced features including a built-in headphone amplifier, simultaneous six channel analog and S/PDIF optical digital output, GPIO for headphone detection, and up to 30 dB of internal microphone boost. – Line, Mic, CD, Video, Modem, and Aux Inputs – Modem, Headphone, Line Front, Line Rear and Line Center/Sub-Woofer Outputs The CRD4202-2 reference design is available by ordering the CMK4202-2 manufacturing kit. This kit includes the CRD4202-2 board, a full set of schematic design files (OrCAD® format), PCB job files (PADS® ASCII), PCB artwork files, and bill of materials. This reference design offers significant cost savings over competing solutions and can be easily modified to meet your specific design goals. 2-layer low cost PC board Complies with Intel ® AC '97 revision 2.2 Exceeds Microsoft’s® PC 2001 audio performance requirements. ORDERING INFO CMK4202-2 (Manufacturing Kit) Microphone Input MIC IN INT MODEM Line Input LINE IN Line Output LINE OUT Headphone Output Rear Channel Output Center / Sub-Woofer Output S/PDIF Digital Optical Output Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com HEADPH OUT CD IN VIDEO IN AUX IN Cirrus Logic CRD4202-1 CS4202 SURR OUT CNT/LFE OUT S/PDIF OUT This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved) MAR ‘02 DS549RD1B1 1 CRD4202-2 TABLE OF CONTENTS 1. GENERAL INFORMATION ...................................................................................3 2. SCHEMATIC DESCRIPTION ................................................................................3 2.1 CS4202 Audio Codec .................................................................................3 2.2 Analog Inputs ..............................................................................................3 2.3 Center, LFE, and Surround Outputs ...........................................................4 2.4 Front Channel and Headphone Outputs .....................................................4 2.5 S/PDIF Optical Output ................................................................................4 2.6 CNR Connector and EEPROM ...................................................................4 2.7 Auto Demotion Circuit .................................................................................4 2.8 Phase Locked Loop ....................................................................................4 2.9 Component Selection .................................................................................5 2.10 EMI Components ......................................................................................5 3. GROUNDING AND LAYOUT ................................................................................5 3.1 Partitioned Voltage and Ground Planes .....................................................5 3.2 AC-Link .......................................................................................................5 3.3 CS4202 Layout Notes .................................................................................5 4. REFERENCES .......................................................................................................6 4.1 ADDENDUM ...............................................................................................6 5. BILL OF MATERIALS .........................................................................................21 LIST OF FIGURES Figure 1. Block Diagram ....................................................................................................7 Figure 2. CS4202 Audio Codec .........................................................................................8 Figure 3. Analog Inputs ......................................................................................................9 Figure 4. Center Channel, Surround, and Sub-Woofer Outputs ......................................10 Figure 5. Front Channel and Headphone Sense Output .................................................11 Figure 6. S/PDIF Optical Output ......................................................................................12 Figure 7. CNR Connector ................................................................................................13 Figure 8. Phase Locked Loop ..........................................................................................14 Figure 9. Auto Demotion and Serial Buffers ....................................................................15 Figure 10. PCB Layout: Top Assembly Drawing ..............................................................16 Figure 11. PCB Layout: Top Layer ..................................................................................17 Figure 12. PCB Layout: Bottom Layer .............................................................................18 Figure 13. PCB Layout: Drill Drawing ..............................................................................19 Figure 14. PCB Layout: Top Silkscreen ...........................................................................20 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Microsoft, Windows 95, Windows 98 and Windows Millennium and WHQL is registered trademark of Microsoft. CrystalClear is a trademark of Cirrus Logic, Inc. Intel is a registered trademark of Intel Corporation. OrCAD is a registered trademark of OrCAD, Inc. PADS is a registered trademark of, PADS Software, Inc. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS549RD1B1 CRD4202-2 1. GENERAL INFORMATION 2.1 The CRD4202-2 CNR reference design features six channel CD quality analog and S/PDIF digital audio outputs. The card includes the CS4202 AC '97 audio codec operating in PLL mode, and two CS4334 24-bit serial stereo DACs. This combination gives the CRD4202-2 a rich feature set and industry leading audio performance. The CS4202 audio codec is shown in Figure 2. The analog input signals to the CS4202 originate from the inputs in Figure 3, while the analog outputs are shown in Figure 4 and Figure 5. AFLT1 and AFLT2 (pins 29, 30) require 1000 pF NPO/C0G capacitors connected to analog ground. These capacitors provide a single pole lowpass filter to the inputs of the CS4202 ADC. No other input filtering is required. The CS4202 audio codec includes a stereo 20-bit DAC, a stereo 18-bit ADC, and a very flexible analog audio mixer. The serial data outputs are paired with two CS4334 DACs to provide four additional channels of analog audio. The CS4202 also features three stereo pairs of line level analog inputs, a microphone input, and a stereo pseudo-differential CD input. The input signals can be routed to the ADC for recording or mixed together for recording and direct playback. The CS4202 has internal registers that are used to control its various features such as volume levels, audio muting, and signal routing. The CS4202 maintains high audio quality and exceeds the Microsoft® PC 2001 audio performance specifications. The CS4202 audio codec communicates to the audio controller across the CNR interface using the AC-Link. The AC-Link is a 5-wire serial digital interface that transfers digital audio data and GPIO control/status data between the two devices, sends commands from the audio controller to the codec, and provides codec status information to the controller. For additional information on the AC-Link, see the Intel® AC '97 revision 2.2 specification. 2. SCHEMATIC DESCRIPTION The block diagram in Figure 1 illustrates the interconnections between the schematic pages found at the end of this document. Sections 2.1 through 2.8 describe the circuitry contained in these schematics. CS4202 Audio Codec The AC-Link may require series termination resistors to prevent reflections. These are normally placed as close as possible to the transmitting end of the AC-Link signal. The CS4202 SDATA_IN (pin 8) and BIT_CLK (pin 6) outputs have 47 Ω series termination resistors. The CS4202 is powered by separate analog and digital power supplies, each with their own respective grounds. The AGND symbols refer to analog ground and DGND symbols refer to digital ground. For best results, connect the grounds together at a single point with a 0.050 inch trace underneath the CS4202. Each power pin requires an individual decoupling capacitor. These decoupling capacitors are placed as close as possible to their respective pins. The CS4202 audio codec uses a 0.1 µF ceramic capacitor for each of the +3.3 V digital and +5 V analog supply pins. 2.2 Analog Inputs The LINE_IN, VIDEO_IN, and AUX_IN stereo inputs shown in Figure 3 are AC-coupled to the CS4202 codec with 1 µF capacitors to minimize low frequency roll-off. The pull down resistors are recommended to prevent noise from coupling to the analog inputs when they are not in use. Locations for 6 dB dividers were provided for 2.0 Vrms input compatibility, but are not required for PC 2001 compliance. The microphone input is AC-coupled with a 1 µF capacitor to minimize low frequency roll-off. The DS549RD1B1 3 CRD4202-2 microphone circuit provides low voltage phantom power for electret microphones. Phantom power is derived from the +5 V analog supply and provides a maximum of 4.2 V under no load and a minimum of 2.0 V under a 0.8 mA load, as required by PC 2001 specifications. The CS4202 features a pseudo-differential CD input that minimizes common mode noise and interference. Each CD signal acts as one side of the differential input and CD_C acts as the other side. CD_C is used as the common return path for both the left and right channels. 2.3 Center, LFE, and Surround Outputs The audio outputs in Figure 4 drive the rear speakers (surround), center speaker (CNT), and subwoofer (LFE) in six channel applications. These four outputs are driven digitally from the CS4202 through two serial output ports and converted to analog audio through two high-performance CS4334 24-bit stereo DACs. 2.4 Front Channel and Headphone Outputs Figure 5 details the Headphone and Line Output circuits. The Line Outputs are the main analog outputs in a two channel system, and become the Front Outputs in a six channel audio system. uses an industry standard Toshiba TOTX-173 optical TOSLINK transmitter. 2.6 CNR Connector and EEPROM The CNR connector is shown in Figure 7. CNR is a motherboard interface that supports audio, modem, and LAN subsystems. CNR applications are targeted at OEMs, system manufacturers, and system integrators who wish take advantage of physically separating their audio, modem, or LAN circuitry from the PC motherboard. CNR accomplishes this without the additional cost associated with the interface circuitry required for a PCI bus add-in card. The CRD4202-2 uses the AC-Link, SMBus, and power supply pins. The SMBus signals are connected to an AT24C02 EEPROM to provide Plugand-Play functionality for the CNR card. The EEPROM holds the Subsystem Vendor ID and Subsystem ID. It also contains other information for implementing a Plug-and-Play CNR card. For additional information on the CNR design specifications, programming utilities, and information on programming the EEPROM, visit the Intel® Communications and Network Riser (CNR) homepage at http://developer.intel.com/technology/cnr/. 2.7 Auto Demotion Circuit The CS4202 has a built in headphone amplifier on pins 39 and 41. These outputs are capable of driving headphones with impedances as low as 32 Ω. The headphone outputs are AC-coupled through 220 µF capacitors. These large capacitor values create excellent low frequency response even under 32 Ω loads. The configuration of the codec on the CRD4202-2 will always be set as the primary audio codec in PLL mode. In crystal mode operation it can automatically demote to a secondary codec in the presence of a motherboard codec when R54 is changed to 100 kΩ (Figure 9). This feature is in accordance with the AC '97 Codec Disable and Demotion Rules. 2.5 2.8 S/PDIF Optical Output The S/PDIF (IEC-958) digital output shown in Figure 6 is compatible with digital inputs on consumer devices such as Mini Disk recorders and consumer stereo receivers. The S/PDIF output operates at a fixed sampling frequency of 48 kHz. It 4 Phase Locked Loop The CRD4202-2 reference design is configured to operate the CS4202 in Phase Locked Loop (PLL) mode as the primary codec. The external clock must be one of the three supported rates, and the codec ID pins must be properly configured to identify DS549RD1B1 CRD4202-2 the input clock frequency. Location Y2 in Figure 8 is populated with a 14.31818 MHz surface mounted clock oscillator (test clock) to demonstrate the CS4202 PLL operation. 2.9 Component Selection Great attention was given to the particular components used on the CRD4202-2 board with cost, performance, and package selection as the most important factors. Listed are some of the guidelines used in the selection of components: • No components smaller than 0805 SMT package. • Only single package passive components. No resistor packs. This reduces the risk of crosstalk between analog audio signals. • All components except connectors are in surface mount packages. 2.10 EMI Components Optional capacitors or inductors may be included to help the board meet EMI compliance tests, such as FCC Part 15. Choose these component values according to individual requirements. 3. GROUNDING AND LAYOUT The component layout and signal routing of the CRD4202-2 provide a good model for developing new CNR add-in card designs. 3.1 Partitioned Voltage and Ground Planes It is critical for good audio performance to separate digital and analog sections to prevent digital noise from affecting the performance of the analog circuits. The analog section of the CRD4202-2 is physically isolated from the digital section with a 0.10 inch partition. Partitioning is defined as the absence of copper on all PCB signal layers. The analog and digital sections have their own separate ground planes. All analog components, power traces, and signal traces are routed over the analog DS549RD1B1 ground plane. Digital components, power traces, and signal traces are not allowed to crossover into the analog section. The CS4202 audio codec is placed at the transition point between the analog and digital ground planes. The analog and digital ground planes must be tied together externally for the CS4202 to maintain proper voltage references. For best results, the two ground planes are tied together with a single 0.050 inch trace under the CS4202 near its digital ground pins. Data converters are generally susceptible to noise on the crystal pins. In order to reduce noise from coupling onto these pins, the area around the 24.576 MHz crystal and its signal traces are filled with copper on the top and bottom of the PCB and attached to digital ground. A separate chassis ground provides a noise-free reference point for all of the EMI suppression components. The chassis ground plane is connected to the analog ground plane at the external jacks. 3.2 AC-Link According to the AC '97 revision 2.2 specification, the AC-Link signals can have a maximum capacitance (including traces, connectors, and circuitry) of 47.5 pF on BIT CLK and SDATA_IN (assuming a single codec). If this capacitance is exceeded, timing violations may occur and cause the system to malfunction. In order to avoid adding excessive capacitance, do not add any EMI capacitors to ground on any of the AC-Link lines. In addition, keep the trace length of the AC-Link as short as possible. Keeping the AC-Link trace length under 8 inches is strongly recommend. 3.3 CS4202 Layout Notes Refer to the CS4202 Data Sheet for analog and digital partitioning guidelines and bypass capacitor placement. Pay special attention to the location of bypass capacitors on REFFLT, AFLT1, AFLT2, and the placement of the power supply capacitors. 5 CRD4202-2 4. REFERENCES 1) Intel®, Audio Codec '97 Component Specification, Revision 2.2, September, 2000. http://developer.intel.com/ial/scalableplatforms/audio/index.htm/ 2) Intel®, CNR Specification, Revision 1.1, October 18, 2000. http://developer.intel.com/technology/cnr/ 3) Cirrus Logic, CS4202 Audio Codec '97 Data Sheet http://www.cirrus.com/products 4) Steve Harris, Clif Sanchez, Personal Computer Audio Quality Measurements, Version 1.0 http://www.cirrus.com/pubs/meas100.pdf 5) Microsoft, PC Design Guidelines, http://www.microsoft.com/hwdev/desguid.htm 6) M. Montrose, Printed Circuit Board Design Techniques for EMC Compliance (2nd edition), IEEE Press, New York: 2000. 4.1 ADDENDUM • Schematic drawings • Layout drawings • Bill of materials 6 DS549RD1B1 CRD4202-2 ANALOG_IN CS4202 LINE_IN_L LINE_IN_R CD_IN_L CD_IN_L CD_IN_R CD_IN_R CD_C ANALOG_OUT LINE_IN_L LINE_IN_R HP_OUT_L HP_OUT_R HP_OUT_L HP_OUT_R HP_OUT_C HP_OUT_C GPIO2 GPIO2 CD_C VIDEO_IN_L VIDEO_IN_L VIDEO_IN_R VIDEO_IN_R AUX_IN_L AUX_IN_L AUX_IN_R AUX_IN_R LINE_OUT_L LINE_OUT_L LINE_OUT_R LINE_OUT_R SPDIF_OUT MIC_IN MIC1 PHONE_IN PHONE_IN MONO_OUT MONO_OUT PC_BEEP PC_BEEP XTAL_IN XTAL_IN SPDIF_OUT SPDIF_TX PLL (optional) ASDOUT ID1# ASYNC ID1# ABITCLK ID0# ARST# ID0# PRIM_DN# SERIAL_PORT XTAL_OUT ASDIN XTAL_OUT SDOUT0 SDOUT0 SDOUT1 SDOUT1 SCLK LRCLK SCLK LRCLK MCLK PRIM_SEC_SWITCH ASDOUT ASDIN1 ASYNC ASDIN0 ASDIN1 ARST# ASDIN0 ABITCLK CNR_BUS PRIM_DN# ASDIN PRIM_DN# Figure 1. Block Diagram DS549RD1B1 7 8 U1 +3.3VD 25 38 +5VA 1 9 12 PC_BEEP C1 0.1uF Z5U C2 0.1uF Z5U C3 0.1uF Z5U C4 0.1uF Z5U 13 14 15 16 17 PHONE_IN AUX_IN_L AUX_IN_R VIDEO_IN_L VIDEO_IN_R CD_IN_L DGND 18 19 20 21 22 CD_C CD_IN_R MIC1 AGND LINE_IN_L LINE_IN_R R55 PRIM_DN# C5 2.2uF Y5V C6 0.1uF X7R C7 1000pF NPO C8 1000pF NPO NO POP AVdd1 AVdd2 AVss1 AVss2 DVdd1 DVdd2 DVss1 DVss2 PC_BEEP PHONE AUX_L AUX_R VIDEO_IN_L VIDEO_IN_R CD_L CD_C CD_R MIC1 BIT_CLK SDATA_OUT SDATA_IN SYNC RESET# LINE_OUT_L LINE_OUT_R HP_OUT_L 23 24 MIC2 LINE_IN_L LINE_IN_R HP_OUT_C HP_OUT_R GPIO2 28 27 Vrefout MONO_OUT 29 30 REFFLT AFLT1 AFLT2 45 46 ID0# HPCFG ID1# GPIO0/LRCLK GPIO1/SDOUT GPIO3 GPIO4/SDO2 2 3 XTAL_IN XTAL_OUT CS4202 XTL_IN XTL_OUT SPDIF_OUT EAPD/SCLK 26 42 4 7 6 R1 5 8 R2 10 11 47 47 35 36 ABITCLK ASDOUT ASDIN ASYNC ARST# DGND AGND LINE_OUT_L LINE_OUT_R 39 40 HP_OUT_L HP_OUT_C HP_OUT_R GPIO2 41 32 37 MONO_OUT 48 47 SPDIF_OUT SCLK 31 43 LRCLK SDOUT0 44 33 34 SDOUT1 AGND AGND ID1# ID0# GND TIE 0.050 inches DS549RD1B1 AGND C12 1000pF NPO DGND Y1 NO POP C13 1000pF NPO C14 NO POP DGND C15 NO POP DGND Figure 2. CS4202 Audio Codec CRD4202-2 C11 1000pF NPO MONO_OUT LINE_OUT_L LINE_OUT_R AGND For 6 channel Operation, pin 33 is pulled low. LINE IN L1 J2 L2 C18 4 3 5 2 1 Connect CGND C20 100pF NPO 0 R6 1uF ELEC LINE_IN_R 100K R8 to AGND at C17 0 C21 1uF ELEC + C19 100pF NPO CD_C 100K AGND R9 R4 J1 1uF ELEC + AGND 31@100MHz CD_IN_R 100K + R5 AGND 31@100MHz 1uF ELEC + 4 3 2 1 C16 AGND DS549RD1B1 CD IN R10 LINE_IN_L 100K the jack L3 1uF ELEC + AGND 31@100MHz C22 R12 CD_IN_L AGND CGND 100K +5VA VIDEO IN MIC IN L4 31@100MHz R16 R18 1uF ELEC R19 R14 J3 0 C25 R15 VIDEO_IN_L 1.5K C24 1uF ELEC 100K 2.2K 4 3 5 2 1 VIDEO_IN_R 100K + AGND 31@100MHz C23 1uF ELEC + L5 0 + 4 3 2 1 R13 AGND J4 C26 100pF NPO Connect CGND C27 100pF NPO MIC_IN + C28 10uF ELEC to AGND at the jack AGND AGND AUX IN AGND CGND BEEP IN L6 31@100MHz 0 C30 1uF ELEC + 4 3 2 1 R20 AGND J5 R22 L7 AUX_IN_R 0 C33 R25 C31 R23 4.7K C32 2700pF X7R 1uF ELEC + AGND 31@100MHz R24 47K 0.1uF Z5U PC_BEEP 31@100MHz 100K 2 1 L8 R21 J6 AUX_IN_L 100K -3 dB corners at 60 Hz and 13.8 kHz (Ri >= 28 kOhm) DGND AGND AGND AGND INTERNAL MODEM CONNECTION L9 31@100MHz 0 C34 1uF ELEC + R27 L10 R28 0 31@100MHz R29 47K C35 1uF ELEC MONO_OUT AGND + AGND PHONE_IN 100K Figure 3. Analog Inputs 9 CRD4202-2 4 3 2 1 R26 AGND J7 10 +5VA SURROUND JACK C36 SDOUT0 1 2 3 4 SDATA DEM#/SCLK LRCK MCLK AOUTR VA+ AGND AOUTL 5 7 6 8 1uF ELEC R30 + CS4334 1uF ELEC R31 + U2 C37 560 J8 4 3 5 560 2 1 Connect CGND R32 220K R33 220K R34 47K R35 47K C38 2700pF X7R +5VA + C40 10uF ELEC C41 0.1uF Z5U C39 2700pF X7R to AGND at the jack C42 0.1uF Z5U AGND AGND AGND CGND AGND CNT/LFE JACK C43 SDOUT1 SCLK LRCLK MCLK 1 2 3 4 SDATA DEM#/SCLK LRCK MCLK AOUTR VA+ AGND AOUTL 5 7 6 8 1uF ELEC R36 + CS4334 1uF ELEC R37 + U3 C44 560 J9 4 3 5 560 2 1 Connect CGND R38 220K R39 220K R40 47K R41 47K C45 2700pF X7R C46 2700pF X7R to AGND at the jack AGND AGND DS549RD1B1 Figure 4. Center Channel, Surround, and Sub-Woofer Outputs CGND AGND CRD4202-2 AGND DS549RD1B1 LINE OUT + 1uF ELEC + JACK C48 1uF ELEC LINE_OUT_R C49 LINE_OUT_L J10 4 3 5 2 1 Connect CGND to AGND at R44 220K R45 220K AGND C50 100pF NPO the jack C51 100pF NPO AGND CGND +5VA R56 10K HEADPHONE GPIO2 + C54 + 220uF ELEC 1uF ELEC 3 1 C55 HP_OUT_R C56 HP_OUT_C J11 7 6 2 + HP_OUT_L JACK 220uF ELEC Connect CGND R48 10K R49 10K Figure 5. Front Channel and Headphone Sense Output CGND to AGND at C58 100pF NPO the jack AGND AGND 11 CRD4202-2 AGND C57 100pF NPO CRD4202-2 SPDIF_TX J12 5 4 +5VD 3 R50 DGND 8.2K 2 C59 0.1uF Z5U 1 6 TOTX-173 DGND DGND Figure 6. S/PDIF Optical Output 12 DS549RD1B1 DS549RD1B1 P1 B1 B2 B3 B4 B5 B6 B9 10uF Z5U ELEC B16 B17 B18 B24 B25 USB+ reserved +5Vdual GND USB- USB_OC# GND +12V GND +3.3Vdual +5VD GND EE_DOUT EE_SHCLK EE_DIN EE_CS GND SMB_A1 SMB_A0 SMB_SCL B26 B27 B28 ASYNC ASDOUT GND GND B22 B23 B29 B30 SMB_A2 SMB_SDA CDC_DN_ENAB# GND AC97_RESET# AC97_SDATA_IN2 AC97_SYNC AC97_SDATA_OUT AC97_SDATA_IN1 AC97_SDATA_IN0 AC97_BITCLK ABITCLK GND LAN_CLK LAN_RXD1 reserved +3.3VD B20 B21 PRIM_DN# GND LAN_TXD2 LAN_TXD0 -12V B19 DGND reserved reserved LAN_RXD2 LAN_RXD0 B14 B15 0.1uF GND reserved LAN_RSTSYNC GND B12 B13 + C62 reserved GND GND LAN_TXD1 B10 B11 C61 reserved reserved reserved reserved B7 B8 +3.3VD reserved GND A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 +5VD A14 A15 +12VD A16 C63 A17 A18 0.1uF 10uF Z5U ELEC + C64 A19 A20 A21 +3.3VD DGND A22 A23 2 A24 A25 3 5 A26 6 U5 ARST# A27 A28 ASDIN1 ASDIN0 A29 A30 1 A1 Vcc A2 SDA SCL A0 WP Vss 8 C60 7 0.1uF Z5U 4 AT24C02 DGND CNR Connector TP1 TP2 TP3 DGND DGND +12VD TP4 TP5 TP6 +5VA U6 IN OUT 3 C65 0.1uF Z5U + C66 10uF ELEC 2 GND 1 MC78M05C ELEC AGND Connect AGND to DGND with a 50 mil trace near the codec. Connect CGND to DGND with a 50 mil trace near the finger edge of the board. Figure 7. CNR Connector 13 CRD4202-2 DGND + C67 10uF ID0# ID1# Test Clock Only PLL (Phase Locked Loop) XTAL_OUT XTAL_IN CRD4202-2 For PLL operation: +3.3VD 4 R51 2.2K 1 R52 NO POP C69 220 pF 1) Populate R54 = 1K (Disable MB audio) 2) DO NOT populate: Y1, C14, C15, and R55 3) Apply external oscillator to XTAL_IN (pin 2) R53 0 (CRD4202-2 will use 14.318 MHz test oscillator ECS-8FA3) 3 C68 .022 uF 4) Populate R51, R52, R53, C68, and C69 according to 2 the desired input clock rate: Y2 14.318 MHz DGND DGND Clock rate (MHz) R51 R52 14.31818 2.2K NO POP 0 ohm R53 C68 C69 24.576 NO POP NO POP NO POP NO POP NO POP 27 2.2K 0 ohm NO POP 0.022uF 220pF 48 2.2K 0 ohm 0 ohm 0.022uF 220pF 0.022uF 220pF DGND Figure 8. Phase Locked Loop 14 DS549RD1B1 CRD4202-2 +3.3VD C70 0.1uF X7R R54 = 1K forces R54 1K U7 TC7SZ125FU 5 motherboard codec(s) to be held in RESET 4 ASDIN1 3 1 2 PRIM_DN# DGND 2 4 ASDIN0 3 ASDIN C71 0.1uF X7R 5 U8 TC7SZ126FU 1 +3.3VD DGND DO NOT use this circuit for motherboard designs. This circuit is strictly for CNR cards. For motherboard designs: connect ASDIN to ASDIN0 if primary codec, connect ASDIN to ASDIN1 if secondary codec. Replace R54 with 100K for automatic demotion when used with primary motherboard codec(s). Figure 9. Auto Demotion and Serial Buffers DS549RD1B1 15 CRD4202-2 Figure 10. PCB Layout: Top Assembly Drawing 16 DS549RD1B1 CRD4202-2 Figure 11. PCB Layout: Top Layer DS549RD1B1 17 CRD4202-2 Figure 12. PCB Layout: Bottom Layer 18 DS549RD1B1 CRD4202-2 Figure 13. PCB Layout: Drill Drawing DS549RD1B1 19 CRD4202-2 Figure 14. PCB Layout: Top Silkscreen 20 DS549RD1B1 DS549RD1B1 5. BILL OF MATERIALS Quantity Reference Manufacturer Part Number Description 1 12 C1,C2,C3,C4,C31,C41, C42,C59,C60,C61,C63,C65 KEMET C0805C104M5UAC CAP, 0805, Z5U, 0.1 µF, 20%, 50V 2 1 C5 KEMET C1206C225M8VAC CAP, 1206, Y5V, 2.2 µF, 20%, 10V 3 3 C6,C70,C71 KEMET C0805C104K5RAC CAP, 0805, X7R, 0.1 µF, 10%, 50V 4 5 C7,C8,C11,C12,C13 KEMET C0805C102K5GAC CAP, 0805, C0G, 1000 pF, 10%, 50V 5 2 C14,C15 KEMET C0805C220K5GAC DO NOT POPULATE 6 19 C16,C17,C18,C21,C22, C23,C24,C25,C30,C33, C34,C35,C36,C37,C43, C44,C48,C49,C56 PANASONIC ECE-V1HA010R CAP, SMT B, ELEC, 1 µF, 20%, 50V 7 8 C19,C20,C26,C27,C50, C51,C57,C58 KEMET C0805C101J5GAC CAP, 0805, COG, 100 pF, 5%, 50V 8 6 C28,C40,C62,C64,C66,C67 PANASONIC ECE-V1CA100R CAP, SMT B, ELEC, 10 µF, 20%, 16V 9 5 C32,C38,C39,C45,C46 KEMET C0805C272K5RAC CAP, 0805, X7R, 2700 pF, 10%, 50V 10 2 C54,C55 PANASONIC ECE-V0GA221P CAP, SMT D, ELEC, 220 µF, 20%, 4V 11 1 C68 KEMET C805C223K5RAC CAP, 0805, X7R, 0.022 µF 10%, 50V 12 1 C69 KEMET C805C221K5RAC CAP, 0805, X7R, 220 pF, 10%, 50V 13 5 J1,J3,J8,J9,J10 A/D ELECTRONICS 3570-50 CONN, 1/8" DOUBLE SW. STEREO PHONE JACK 14 4 J2,J4,J5,J7 MOLEX 70553-0003 HDR, 4X1, 0.025" PIN, 0.1" CTR, 15u" AU 15 1 J6 MOLEX 70553-0036 HDR, 2X1, 0.025" PIN, 0.1" CTR, 150u" SN/PB 16 1 J11 SINGATRON 2SJ-09075N53 CONN, 1/8" SINGLE SW. STEREO PHONE JACK W/INSULATOR 17 1 J12 TOSHIBA TOTX173 CONN, OPTICAL TOSLINK TRANSMITTER 18 10 L1,L2,L3,L4,L5,L6,L7,L8, L9,L10 TDK HF50ACB321611-T IND, FBEAD, 1206, 31@100MHz, 25% CRD4202-2 21 Item 22 1 P1 NONE NONE CNR BUS CONNECTOR 20 2 R2,R1 PHILIPS 9C08052A47R0J RES, SO, 0805, 47, 5%, 1/10W, METAL FILM 21 9 R4,R8,R13,R18,R20,R24, R26,R28,R53 PHILIPS 9C08052A0R00J RES, SO, 0805, 0, 5%, 1/10W, METAL FILM 22 10 R5,R6,R9,R10,R12,R16, R19,R22,R25,R27 PHILIPS 9C08052A1003J RES, SO, 0805, 100K, 5%, 1/10W, METAL FILM 23 2 R14,R51 PHILIPS 9C08052A2201J RES, SO, 0805, 2.2K, 5%, 1/10W, METAL FILM 24 1 R15 PHILIPS 9C08052A1501J RES, SO, 0805, 1.5K, 5%, 1/10W, METAL FILM 25 6 R21,R29,R34,R35,R40,R41 PHILIPS 9C08052A4702J RES, SO, 0805, 47K, 5%, 1/10W, METAL FILM 26 1 R23 PHILIPS 9C08052A4701J RES, SO, 0805, 4.7K, 5%, 1/10W, METAL FILM 27 4 R30,R31,R36,R37 PHILIPS 9C08052A5600J RES, SO, 0805, 560, 5%, 1/10W, METAL FILM 28 6 R32,R33,R38,R39,R44,R45 PHILIPS 9C08052A2203J RES, SO, 0805, 220K, 5%, 1/10W, METAL FILM 29 3 R48,R49,R56 PHILIPS 9C08052A1002J RES, SO, 0805, 10K, 5%, 1/10W, METAL FILM 30 1 R50 PHILIPS 9C08052A8201J RES, SO, 0805, 8.2K, 5%, 1/10W, METAL FILM 31 2 R52,R55 PHILIPS 9C08052A0R00J DO NOT POPULATE 32 1 R54 PHILIPS 9C08052A1001J RES, SO, 0805, 1K, 5%, 1/10W, METAL FILM 33 6 TP1,TP2,TP3,TP4,TP5,TP6 KEYSTONE 5015 MINI SMT TEST POINT 34 1 U1 Cirrus Logic CS4202-JQ IC, TQFP, AC '97 2.2 SERIAL CODEC W/ HP AMP + SRC 35 2 U2,U3 Cirrus Logic CS4334-KS IC, SO, SOIC8, STEREO DAC, 24 BITS 36 1 U5 ATMEL AT24C02N-10SC-2.7 IC, SO, SOIC8, SERIAL EEPROM, 256 x 8, 2.7V 37 1 U6 MOTOROLA MC78M05CDT IC, SO, +5V REGULATOR, DPAK, 4%, 500mA 38 1 U7 TOSHIBA TC7SZ125FU IC, SSOP5-P-0.65A, single 3 state buffer, 2.6ns 39 1 U8 TOSHIBA TC7SZ126FU IC, SSOP5-P-0.65A, single 3 state buffer, 2.6ns 40 1 Y1 FOX FS24.576 DO NOT POPULATE 41 1 Y2 ECS ECS-8FA3 Clock OSC, 14.31818MHz, SMT CRD4202-2 DS549RD1B1 19 • Notes •