CIRRUS CS5464-ISZ

CS5464
Three-channel, Single-phase Power/Energy IC
Features
Description
• Energy Data Linearity: ±0.1% of Reading
over 1000:1 Dynamic Range
• On-chip Functions:
The CS5464 is an integrated power measurement device which combines three ∆Σ
analog-to-digital converters, power calculation
engine, energy-to-frequency converter, and a
serial interface on a single chip. It is designed to
accurately measure instantaneous current and
voltage and calculate VRMS, IRMS, instantaneous
power, active power, apparent power, and reactive power for high-performance power
measurement applications.
- Instantaneous Voltage, Current, and Power
- IRMS and VRMS, Active, Reactive, and
Apparent Power
- Current Fault and Voltage Sag Detect
- System Calibrations / Phase Compensation
- Temperature Sensor
- Energy-to-pulse Conversion
- Positive-only Accumulation Mode
• Meets Accuracy Spec for IEC, ANSI, & JIS
• Low Power Consumption
• Tamper Detection in 2-Wire Distribution
Systems
• GND-referenced Signals with Single Supply
• On-chip 2.5 V Reference (25 ppm/°C typ)
• Power Supply Monitor
• Simple Three-wire Digital Serial Interface
• “Auto-boot” Mode from Serial E2PROM.
• Power Supply Configurations
The CS5464 is optimized to interface to shunt resistors or current transformers for current
measurement, and to resistive dividers or potential transformers for voltage measurement.
The CS5464 features a tamper detection
scheme that uses the larger of the active power
measurements to register energy. Additional features
include
system-level
calibration,
temperature sensor, voltage sag & current fault
detection, and phase compensation.
ORDERING INFORMATION
See Page 45.
VA+ = +5 V; AGND = 0 V; VD+ = +3.3 V to +5 V
RESET
VA+
IIN1+
IIN1-
PGA
4th Order ∆Σ
Modulator
Digital
Filter
VD+
HPF
Option
MODE
CS
SDI
IIN2+
IIN2-
PGA
4th Order ∆Σ
Modulator
Digital
Filter
HPF
Option
Power
Calculation
Engine
VIN+
VIN-
10x
2nd Order ∆Σ
Modulator
Digital
Filter
HPF
Option
Serial
Interface
SDO
SCLK
INT
E-to-F
E1
E2
E3
Temperature
Sensor
VREFIN
VREFOUT
x1
Voltage
Reference
AGND
Power
Monitor
PFMON
Preliminary Product Information
http://www.cirrus.com
System
Clock
Clock
Generator
/K
XIN
Calibration
XOUT CPUCLK
DGND
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
MAR ‘06
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CS5464
TABLE OF CONTENTS
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Control Pins and Serial Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Analog Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Characteristics & Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Inputs (All Channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Inputs (Current Channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Analog Inputs (Voltage Channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Temperature Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Master Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SDI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SDO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Auto-Boot Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
E1, E2, and E3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Voltage and Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Tamper Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Linearity Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Voltage Channel Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Current Channel Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 High-pass Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Energy Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1 Active Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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14
14
15
15
16
16
17
17
17
17
17
17
17
18
18
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5.5.2 Apparent Energy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3 Reactive Energy Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.4 Voltage Channel Sign Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.5 PFMON Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.6 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Sag and Fault Detect Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 On-chip Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Power-down States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Event Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12.1 Typical Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13 Serial Port Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13.1 Serial Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14 Register Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Page 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7. System Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Channel Offset and Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1 Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1.1 Duration of Calibration Sequence . . . . . . . . . . . . . . . . . . . . .
7.1.2 Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2.1 DC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . .
7.1.2.2 AC Offset Calibration Sequence . . . . . . . . . . . . . . . . . . . . . .
7.1.3 Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3.1 AC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . .
7.1.3.2 DC Gain Calibration Sequence . . . . . . . . . . . . . . . . . . . . . . .
7.1.4 Order of Calibration Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Phase Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Active Power Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8. Auto-boot Mode Using E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Auto-boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Auto-boot Data for E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Which E2PROMs Can Be Used? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9. Basic Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10. Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . .
13. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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19
20
20
20
20
21
21
21
21
21
22
22
23
23
23
24
28
28
34
38
39
39
39
39
39
39
40
40
40
41
41
41
41
42
42
42
42
43
44
45
45
46
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CS5464
LIST OF FIGURES
Figure 1. CS5464 Read and Write Timing Diagrams ................................................................. 12
Figure 2. Timing Diagram for E1, E2, and E3 ...................................................................................... 13
Figure 3. Data Measurement Flow Diagram ............................................................................... 14
Figure 4. Data Measurement Flow Diagram ............................................................................... 14
Figure 5. Power Calculation Flow ............................................................................................... 15
Figure 6. Active and Reactive energy pulse outputs .................................................................. 19
Figure 7. Apparent energy pulse outputs.................................................................................... 19
Figure 8. Voltage Channel Sign Pulse outputs ........................................................................... 20
Figure 9. PFMON output to pin E3........................................................................................................ 20
Figure 10. Sag and Fault Detect................................................................................................. 20
Figure 11. Oscillator Connection ................................................................................................ 22
Figure 12. CS5464 Memory Map................................................................................................ 23
Figure 13. Calibration Data Flow ................................................................................................ 39
Figure 14. System Calibration of Offset...................................................................................... 39
Figure 15. System Calibration of Gain........................................................................................ 40
Figure 16. Example of AC Gain Calibration................................................................................ 40
Figure 17. Example of AC Gain Calibration................................................................................ 40
Figure 18. Typical Interface of E2PROM to CS5464 .................................................................. 42
Figure 19. Typical Connection Diagram ..................................................................................... 43
LIST OF TABLES
Table 1. Current Channel PGA Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2. High-pass Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3. E2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. E3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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CS5464
1. OVERVIEW
The CS5464 is a CMOS monolithic power measurement device with a computation engine and an energy-to-frequency pulse output. The CS5464 combines two programmable gain amplifiers, three ∆Σ analog-to-digital converters (ADCs), system calibration, and a computation engine on a single chip.
The CS5464 is designed for power measurement applications and is optimized to interface to a current-sense resistor or transformer for current measurement, and to a resistive divider or potential transformer for voltage measurement. The current channels provide programmable gains to accommodate
various input levels from a multitude of sensing elements. The second current channel is designated for
tamper detection support in applications where required. With a single +5 V supply on VA+/AGND, the
CS5464’s three input channels can accommodate common mode plus signal levels between
(AGND - 0.25 V) and VA+.
The CS5464 also is equipped with a computation engine that calculates instantaneous power, IRMS,
VRMS, apparent power, active (real) power, reactive power, and power factor. Additional features of the
CS5464 include line frequency, current and voltage sag detection, zero-cross detection, positive-only accumulation mode, and three programmable pulse output pins. To facilitate communication to a microprocessor, the CS5464 includes a simple three-wire serial interface which is SPI™ and Microwire™
compatible. The CS5464 provides three outputs for energy registration. Pins E1, E2, and E3 are designed
to interface to a microprocessor.
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CS5464
2. PIN DESCRIPTION
Crystal Out
CPU Clock Output
Positive Digital Supply
Digital Ground
Serial Clock
Serial Data Ouput
Chip Select
Mode Select
Differential Voltage Input
Differential Voltage Input
Voltage Reference Output
Voltage Reference Input
Factory Test
Factory Test
XOUT
CPUCLK
VD+
DGND
SCLK
SDO
CS
MODE
VIN+
VINVREFOUT
VREFIN
TEST1
TEST2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XIN
SDI
E2
E1
INT
RESET
E3
PFMON
IIN+
IINVA+
AGND
IIN2+
IIN2-
Crystal In
Serial Data Input
Energy Output 2
Energy Output 1
Interrupt
Reset
Energy Output 3
Power Fail Monitor
Differential Current Input
Differential Current Input
Positive Analog Supply
Analog Ground
Differential Current Input
Differential Current Input
Clock Generator
Crystal Out
Crystal In
CPU Clock Output
1,28
2
XOUT, XIN - The output and input of an inverting amplifier. Oscillation occurs when connected to
a crystal, providing an on-chip system clock. Alternatively, an external clock can be supplied to
the XIN pin to provide the system clock for the device.
CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
Control Pins and Serial Data I/O
Serial Clock Input
5
SCLK - A Schmitt Trigger input pin. Clocks data from the SDI pin into the receive buffer and out of
the transmit buffer onto the SDO pin when CS is low.
Serial Data Output
6
SDO -Serial port data output pin.SDO is forced into a high impedance state when CS is high.
Chip Select
7
CS - Low, activates the serial port interface.
8
MODE - High, enables the “auto-boot” mode. The mode pin is pull-down by an internal resistor.
Mode Select
Energy Output
22, 25, E3, E1, E2 - Active low pulses with an output frequency proportional to energy.
26
Reset
23
RESET - A Schmitt Trigger input pin. Low activates Reset, all internal registers (some of which
drive output pins) are set to their default states.
Interrupt
24
INT - Low, indicates that an enabled event has occurred.
Serial Data Input
27
SDI - Serial port data input pin. Data will be input at a rate determined by SCLK.
Analog Inputs/Outputs
Differential Voltage Inputs
Differential Current Inputs
9,10
VIN+, VIN- - Differential analog input pins for the voltage channel.
19,20, IIN+, IIN-, IIN2+, IIN2- - Differential analog input pins for the current channel.
15,16
Voltage Reference Output
11
VREFOUT - The on-chip voltage reference output. The voltage reference has a nominal magnitude of 2.5 V and is referenced to the AGND pin on the converter.
Voltage Reference Input
12
VREFIN - The input to this pin establishes the voltage reference for the on-chip modulator.
Power Supply Connections
Positive Digital Supply
3
VD+ - The positive digital supply.
Digital Ground
4
DGND - Digital Ground.
Positive Analog Supply
18
VA+ - The positive analog supply.
Analog Ground
17
AGND - Analog ground.
Power Fail Monitor
21
PFMON - The power fail monitor pin monitors the analog supply. If PFMON’s voltage threshold is
tripped, a Low-Supply Detect (LSD) event is set in the status register.
Test Connections
Factory Test
6
13,14
TEST1, TEST2 - Factory use only. Connect to AGND.
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3. CHARACTERISTICS & SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
Positive Digital Power Supply
Positive Analog Power Supply
Voltage Reference
Specified Temperature Range
Symbol
VD+
VA+
VREFIN
TA
Min
3.135
4.75
-40
Typ
5.0
5.0
2.5
-
Max
5.25
5.25
+85
Unit
V
V
V
°C
ANALOG CHARACTERISTICS
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 5 V ±5%; AGND = DGND = 0 V; VREFIN = +2.5 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz.
Parameter
Accuracy
Active Power
(Note 1)
Average Reactive Power
(Note 1 and 2)
Power Factor
(Note 1 and 2)
Current RMS
(Note 1)
Voltage RMS
(Note 1)
Symbol
Min
Typ
Max
Unit
PActive
-
±0.1
-
%
All Gain Ranges
Input Range 0.1% - 100%
QAvg
-
±0.2
-
%
All Gain Ranges
Input Range 1.0% - 100%
Input Range 0.1% - 1.0%
PF
-
±0.2
±0.27
-
All Gain Ranges
Input Range 1.0% - 100%
Input Range 0.1% - 1.0%
IRMS
-
±0.1
±0.17
-
%
%
%
%
%
All Gain Ranges
Input Range 5% - 100%
VRMS
-
±0.1
-
%
80
-0.25
-
VA+
dB
V
-
500
100
-
mVP-P
mVP-P
NI
80
30
-
94
-115
27
-
22.5
4.5
dB
dB
pF
kΩ
µVrms
µVrms
OD
GE
-
4.0
±0.4
-
µV/°C
%
All Gain Ranges
Input Range 0.1% - 100%
Analog Inputs (All Channels)
Common Mode Rejection
Common Mode + Signal
Analog Inputs (Current Channels)
Differential Input Range
[(IIN+) - (IIN-)]
Total Harmonic Distortion
Crosstalk with Voltage Channel at Full Scale
Input Capacitance
Effective Input Impedance
Noise (Referred to Input)
Offset Drift (Without the High Pass Filter)
Gain Error
(DC, 50, 60 Hz)
CMRR
(Gain = 10)
(Gain = 50)
IIN
(Gain = 50)
THD
(50, 60 Hz)
IC
EII
(Gain = 10)
(Gain = 50)
(Note 3)
Notes: 1. Applies when the HPF option is enabled.
2. Applies when the line frequency is equal to the product of the Output Word Rate (OWR) and the value
of epsilon (ε).
DS682PP1
7
CS5464
ANALOG CHARACTERISTICS (Continued)
Parameter
Analog Inputs (Voltage Channel)
Differential Input Range
Symbol
Min
Typ
Max
Unit
[(VIN+) - (VIN-)]
VIN
-
500
-
mVP-P
Total Harmonic Distortion
Crosstalk with Current Channel at Full Scale
(50, 60 Hz)
Input Capacitance
All Gain Ranges
Effective Input Impedance
Noise (Referred to Input)
THD
IC
EII
NV
65
2
-
75
-70
2.0
-
140
dB
dB
pF
MΩ
µVrms
Offset Drift (Without the High Pass Filter)
Gain Error
Temperature Channel
Temperature Accuracy
Power Supplies
Power Supply Currents (Active State)
OD
GE
-
16.0
±3.0
-
µV/°C
%
T
-
±5
-
°C
PSCA
PSCD
PSCD
-
1.3
2.9
1.7
-
mA
mA
mA
PC
-
33
20
7
10
36
23
-
mW
mW
mW
uW
48
68
60
2.3
-
55
75
65
2.45
2.55
2.7
dB
dB
dB
V
V
(Note 3)
IA+
ID+ (VA+ = VD+ = 5 V)
ID+ (VA+ = 5 V, VD+ = 3.3 V)
Power Consumption
(Note 4)
Active State (VA+ = VD+ = 5 V)
Active State (VA+ = 5 V, VD+ = 3.3 V)
Stand-by State
Sleep State
Power Supply Rejection Ratio (50, 60 Hz)
(Note 5)
Voltage Channel
Current Channel (Gain = 50x)
Current Channel (Gain = 10x)
PFMON Low-voltage Trigger Threshold
PFMON High-voltage Power-on Trip Point
(Note 6)
(Note 7)
PSRR
PMLO
PMHI
Notes: 3. Applies before system calibration.
4. All outputs unloaded. All inputs CMOS level.
5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV
(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The
“+” and “-” input pins of both input channels are shorted to AGND. The CS5464 is then commanded to
continuous conversion acquisition mode, and digital output data is collected for the channel under test.
The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted
into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied
at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined
as Veq. PSRR is (in dB):
150
PSRR = 20 ⋅ log ---------V eq
6. When voltage level on PFMON is sagging, and LSD bit = 0, the voltage at which LSD is set to 1.
7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on
PFMON at which the LSD bit can be permanently reset back to 0.
8
DS682PP1
CS5464
VOLTAGE REFERENCE
Parameter
Symbol
Min
Typ
Max
Unit
VREFOUT
+2.4
+2.5
+2.6
V
Reference Output
Output Voltage
Temperature Coefficient
(Note 8)
TCVREF
-
25
60
ppm/°C
Load Regulation
(Note 9)
∆VR
-
6
10
mV
VREFIN
+2.4
+2.5
+2.6
V
Input Capacitance
-
4
-
pF
Input CVF Current
-
100
-
nA
Reference Input
Input Voltage Range
Notes: 8. The voltage at VREFOUT is measured across the temperature range. From these measurements the
following formula is used to calculate the VREFOUT Temperature Coefficient:.
(
MAX
MIN )
AVG
(T
A
MAX
1
- T AM IN
(
- VREFOUT
( (VREFOUT
VREFO UT
( 1.0 x 10
6
(
TC VREF =
9. Specified at maximum recommended output of 1 µA, source or sink.
DIGITAL CHARACTERISTICS
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
MCLK = 4.096 MHz.
Parameter
Symbol
Min
Typ
Max
Unit
MCLK
2.5
4.096
20
MHz
40
-
60
%
40
-
60
%
-2.8
-
+2.8
°
-
DCLK/8
-
Hz
-
DCLK/1024
-
Hz
-
0.5
-
Hz
25
-
100
%F.S.
Master Clock Characteristics
Master Clock Frequency
Internal Gate Oscillator (Note 11)
Master Clock Duty Cycle
CPUCLK Duty Cycle
(Note 12 and 13)
Filter Characteristics
Phase Compensation Range
Input Sampling Rate
(Voltage Channel, 60 Hz)
DCLK = MCLK/K
Digital Filter Output Word Rate
High-pass Filter Corner Frequency
(Both Channels)
OWR
-3 dB
Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR
Channel-to-channel Time-shift Error
1.0
(Note 15)
µs
Input/Output Characteristics
High-level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
VIH
0.6 VD+
(VD+) - 0.5
0.8 VD+
-
-
V
V
V
-
-
0.8
1.5
0.2 VD+
V
V
V
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
DS682PP1
VIL
9
CS5464
Parameter
Symbol
Min
Typ
Max
Unit
-
-
0.48
0.3
0.2 VD+
V
V
V
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN
SCLK and RESET
High-level Output Voltage
VIL
Iout = +5 mA
VOH
(VD+) - 1.0
-
-
V
Iout = -5 mA (VD = +5V)
Iout = -2.5 mA (VD = +3.3V)
VOL
-
-
0.4
0.4
V
V
Iin
-
±1
±10
µA
3-state Leakage Current
IOZ
-
-
±10
µA
Digital Output Pin Capacitance
Cout
-
5
-
pF
Low-level Output Voltage
Input Leakage Current
(Note 16)
Notes: 10. All measurements performed under static conditions.
11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is
used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between
2.5 MHz - 5.0 MHz.
12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification.
13. The frequency of CPUCLK is equal to MCLK.
14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is
limited by the full-scale signal applied to the channel input.
15. Configuration Register bits PC[6:0] are set to “0000000”.
16.
10
The MODE pin is pulled low by an internal resistor.
DS682PP1
CS5464
SWITCHING CHARACTERISTICS
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
Logic Levels: Logic 0 = 0 V, Logic 1 = VD+.
Parameter
Symbol
Min
Typ
Max
Unit
trise
-
50
1.0
-
µs
ns
tfall
-
50
1.0
-
µs
ns
tost
-
60
-
ms
SCLK
-
-
2
MHz
t1
t2
200
200
-
-
ns
ns
CS Falling to SCLK Rising
t3
50
-
-
ns
Data Set-up Time Prior to SCLK Rising
t4
50
-
-
ns
Data Hold Time After SCLK Rising
t5
100
-
-
ns
CS Falling to SDO Driving
t6
-
20
50
ns
SCLK Falling to New Data Bit (hold time)
t7
-
20
50
ns
CS Rising to SDO Hi-Z
t8
-
20
50
ns
Rise Times
(Note 16)
Any Digital Output
Fall Times
(Note 16)
Any Digital Output
Start-up
Oscillator Start-up Time
XTAL = 4.096 MHz (Note 17)
Serial Port Timing
Serial Clock Frequency
Serial Clock
Pulse Width High
Pulse Width Low
SDI Timing
SDO Timing
Auto-Boot Timing
Serial Clock
Pulse Width Low
Pulse Width High
t9
t10
8
8
MCLK
MCLK
MODE setup time to RESET Rising
t11
50
ns
RESET rising to CS falling
t12
48
MCLK
CS falling to SCLK rising
t13
100
SCLK falling to CS rising
t14
CS rising to driving MODE low (to end auto-boot sequence)
t15
50
ns
SDO guaranteed setup time to SCLK rising
t16
100
ns
8
MCLK
16
MCLK
Notes: 16. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
DS682PP1
11
CS5464
t3
CS
t1
t2
SC LK
C o m m a n d T im e 8 S C L K s
H ig h B y te
LSB
MSB
MSB-1
LSB
MSB-1
LSB
MSB
MSB
t5
MSB-1
LSB
SDI
MSB-1
MSB
t4
M id B y te
L o w B y te
SDI Write Timing (Not to Scale)
CS
t1
t8
LSB
MSB-1
LSB
MSB
Low B yte
MSB-1
LSB
UNKNOW N
MSB-1
MSB
SDO
M id B yte
MSB
H igh B yte
t6
t7
t2
LSB
MSB-1
SDI
MSB
SCLK
C om m and T im e 8 S C LK s
S Y N C 0 or S Y N C 1
C om m and
S Y N C 0 or S Y N C 1
C om m and
S Y N C 0 or S Y N C 1
C om m and
SDO Read Timing (Not to Scale)
t11
t15
MODE
( IN P U T )
RESET
( IN P U T )
CS
t14
t12
t7
t13
(O U T P U T )
SCLK
(O U T P U T )
t10
SDO
t16
t9
t4
t5
STOP bit
(O U T P U T )
SDI
( IN P U T )
Last 8
B it s
D a ta fro m E E P R O M
Auto-boot Sequence Timing (Not to Scale)
Figure 1. CS5464 Read and Write Timing Diagrams
12
DS682PP1
CS5464
SWITCHING CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
tperiod
250
-
-
µs
Pulse Width
tpw
244
-
-
µs
Rising Edge to Falling Edge
t3
6
-
-
µs
E2 Setup to E1 and/or E3 Falling Edge
t4
1.5
-
-
µs
E1 Falling Edge to E3 Falling Edge
t5
248
-
-
µs
E1, E2, and E3 Timing
(Note 18 and 19)
Period
Notes: 18. Pulse output timing is specified at MCLK = 4.096 MHz, E2MODE = 0, and E3MODE[1:0] = 0. Refer to
5.5 Energy Pulse Output on page 18 for more information on pulse output pins.
19. Timing is proportional to the frequency of MCLK.
tperiod
tpw
E1
t3
t4
E2
t4
E3
tpw
t5
tperiod
t5
t3
Figure 2. Timing Diagram for E1, E2, and E3
ABSOLUTE MAXIMUM RATINGS
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter
DC Power Supplies
Input Current, Any Pin Except Supplies
Symbol
Min
Typ
Max
Unit
(Notes 20 and 21)
Positive Digital
Positive Analog
VD+
VA+
-0.3
-0.3
-
+6.0
+6.0
V
V
(Notes 22, 23, 24)
IIN
-
-
±10
mA
IOUT
-
-
100
mA
PD
-
-
500
mW
Output Current, Any Pin Except VREFOUT
Power Dissipation
(Note 25)
Analog Input Voltage
All Analog Pins
VINA
- 0.3
-
(VA+) + 0.3
V
Digital Input Voltage
All Digital Pins
VIND
-0.3
-
(VD+) + 0.3
V
Ambient Operating Temperature
TA
-40
-
85
°C
Storage Temperature
Tstg
-65
-
150
°C
Notes: 20. VA+ and AGND must satisfy [(VA+) - (AGND)] ≤ + 6.0 V.
21. VD+ and AGND must satisfy [(VD+) - (AGND)] ≤ + 6.0 V.
22. Applies to all pins including continuous over-voltage conditions at the analog input pins.
23. Transient current of up to 100 mA will not cause SCR latch-up.
24. Maximum DC input current for a power supply pin is ±50 mA.
25. Total power dissipation, including all input currents and output currents.
DS682PP1
13
CS5464
to Voltage
Channel 2
VOLTAGE
x10
SINC 3
+
DELAY
REG
IIR
X
VDCoff Vgn
APF
+
Σ
MUX
2nd Order
∆Σ
Modulator
V
HPF
HPF
X
VQ
SYSGain
Digital Filter
IIR
X
ε
X
Control Register
PC[7] PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0]
2322
...
VHPF
IHPF
6
5
...
X
Q
3 2 1 0
2π
X
Operational Modes Register
P
7
PGA
4th Order
∆Σ
Modulator
DELAY
REG
SINC 3
+
IIR
X
Σ
HPF
X
+
SYSGain
Digital Filter
MUX
CURRENT
APF
IDCoff
REGISTER NAMES INDICATED
IN SHADED AREAS.
I
I gn
Figure 3. Data Measurement Flow Diagram
4. THEORY OF OPERATION
The CS5464 is a four-channel analog-to-digital converter (ADC) followed by a computation engine that performs power calculations and energy-to-pulse
conversion. The data flow for the voltage and current
channel measurement and the power calculation algorithms are depicted in Figures 3, 4, and 5.
amplified signals are sampled by a fourth-order
delta-sigma modulator for digitization. The converters
sample at a rate of MCLK/8. The over-sampling provides a wide dynamic range and simplified anti-alias filter design.
4.1 Digital Filters
The CS5464 analog inputs are structured with two Current channels and two Voltage channels, then optimized
to simplify interfacing to various sensing elements. As
shown in Figures 3 and 4, the current channels are fully
independent while the two voltage channels are multiplexed.
The decimating digital filters on the four channels are
Sinc3 filters followed by 4th-order IIR filters. The single-bit data is passed to the low-pass decimation filter
and output at a fixed word rate. The output word is
passed to an IIR filter to compensate for the magnitude
roll off of the low-pass filtering operation.
The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is subject to a gain of 10x. A second-order delta-sigma modulator samples the amplified signal for digitization.
Simultaneously, the current-sensing elements introduce
a voltage waveform on the two current channel inputs
IIN± and IIN2±, which is subject to the two selectable
gains of the programmable gain amplifier (PGA). The
from Voltage Channel 1
SINC 3
IIR
X
V2 dcoff
MUX
Temp
Sensor
2nd Order
∆Σ
Modulator
+
DELAY
REG
V2gn
APF
X
HPF
HPF
+
Σ
MUX
An optional digital high-pass filter (HPF in Figures 3 and
4) removes any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled the DC component will be removed
V2
V2Q
Digital Filter SYSGain
Temperature
Registers
IIR
X
ε
X
X
Q2
Control Register
PC[7] PC[6] PC[5] PC[4] PC[3] PC[2] PC[1] PC[0]
2322
...
VHPF
8
IHPF
7
...
π
3 2 1 0
X
PGA
4th Order
∆Σ
Modulator
DELAY
REG
SINC 3
X
IIR
+
Σ
X
+
Digital Filter
SYSGain
I2 dcoff
HPF
APF
I2gn
MUX
Operational Modes Register
7
CURRENT 2
P2
I2
REGISTER NAMES INDICATED
IN SHADED AREAS.
Figure 4. Data Measurement Flow Diagram
14
DS682PP1
CS5464
Vacoff
(V2acoff)
Σ
N
X
V (V2)
÷N
Σ
N
X
I (I2)
Poff (P2off)
PulseRateE
÷N
+
√
+
VRMS
(V2RMS)
Σ
Iacoff
(I2acoff)
+
S (S2)
+
X
X
-
+
IRMS
(I2RMS)
Σ
Inverse
X
Σ
Σ
N
Q (Q2)
QTRIG
(Q2TRIG)
PF
(PF2)
Energy-to-pulse
N
Σ
√
Σ
X
+
P (P2)
√
+
÷N
PACTIVE
(P2ACTIVE)
÷N
QAVG
(Q2AVG)
E1
E2
E3
X
REGISTER NAMES (CHANNEL 2 REGISTER
NAMES) INDICATED IN SHADED AREAS.
Figure 5. Power Calculation Flow
from the calculated VRMS and I RMS as well as the apparent power.
When the optional HPF in either channel is disabled, an
all-pass filter (APF) in the complement channel is implemented. The APF has an amplitude response that is flat
within the channel bandwidth and is used for matching
phase in systems where only one channel’s HPF is engaged. For more information, see 5.3 High-pass Filters
on page 17.
4.2 Voltage and Current Measurements
The digital filter output word is subject to a DC offset adjustment and a gain calibration (See Section 7. System
Calibration on page 39). The calibrated measurement is
available by reading the instantaneous voltage and current registers.
The Root Mean Square (RMS in Figure 5) calculations
are performed on N instantaneous voltage and current
samples, Vn and In, respectively (where N is the cycle
count), using the formula:
4.3 Power Measurements
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Figure 3 and 4). The product is then averaged over N conversions to compute active power and is used to drive
energy pulse output E1. Energy output E2 is configurable and can provide an energy sign, a pulse output
that is proportional to the apparent power, or a tamper
indicator. Energy output E3 provides a pulse output that
is proportional to the reactive power or the apparent
power. Output E3 can also be set to indicate the
PFMON comparator output or to indicate the sign of the
voltage applied to the voltage channel.
The apparent power (S, S2) is the combination of the
active power and reactive power, without reference to
an impedance phase angle, and is calculated by the
CS5464 using the following formula:
S = V RMS × I RMS
Power Factor (PF, PF2) is the active power (PActive,
P2Active) divided by the apparent power (S, S2)
N–1
I RMS =
∑ In
n=0
--------------------N
and likewise for VRMS, using Vn. IRMS and VRMS are accessible by register reads, which are updated once every cycle count (referred to as a computational cycle).
DS682PP1
P Active
PF = -----------------S
The sign of the power factor is determined by the active
power.
The CS5464 calculates the reactive power (QTrig,
Q2Trig) utilizing trigonometric identities, using the formula
Q Trig =
2
S 2 – P Active
15
CS5464
The average reactive power calculation (QAvg, Q2Avg) is
generated by averaging the voltage then multiplying
that value by the current measurement with a 90° phase
difference between the two. The 90° phase shift is realized by applying an IIR digital filter in the voltage channel to obtain quadrature voltage (see Figure 3 and 4).
This filter will give exactly -90° phase shift across all frequencies, and utilizes epsilon (ε) to achieve unity gain
at the line frequency.
The instantaneous quadrature voltage (VQ, V2Q) and
current (I, I2) samples are multiplied to obtain the instantaneous quadrature power (Q, Q2). The product is
then averaged over N conversions, utilizing the formula
4.4 Tamper Detection
The third channel (inputs IIN2±) can be used for tamper
detection when required by the application. Typically using a shunt resistor to save cost, the tamper input monitors the current through the neutral connection. See
Figure 19 on page 43.
The CS5464 calculates active power, P and P2, using
current channel inputs, IIN± and IIN2±, respectively.
The active powers are then compared, looking for deviations greater then a programmable threshold, as an indicator of a connection fault, potentially caused by
tampering. When tamper detect is enabled (by default)
the current channel that produces the larger active power will be registered in the pulse output accumulation
registers and pulse output pins.
4.5 Linearity Performance
N
∑ Qn
n=1
Q Avg = -----------------------N
The peak current (Ipeak, I2peak) and peak voltage (Vpeak,
V2peak) are the instantaneous current and voltage, respectively, with the greatest magnitude detected during
the previous computation cycle. Active, apparent, reactive, and fundamental power are updated every computation cycle.
16
The linearity of the VRMS, I RMS, active, reactive, and
power-factor power measurements (before calibration)
will be within ±0.1% of reading over the ranges specified, with respect to the input voltage levels required to
cause full-scale readings in the IRMS and VRMS registers. Refer to Accuracy Specifications on page 7.
Until the CS5464 is calibrated, the accuracy of the
CS5464 (with respect to a reference line-voltage and
line-current level on the power mains) is not guaranteed
to within ±0.1%. (See Section 7. System Calibration on
page 39.) The accuracy of the internal calculations can
often be improved by selecting a value for the Cycle
Count Register that will cause the time duration of one
computation cycle to be equal to (or very close to) a
whole number of power-line cycles (and N must be 4000
or greater).
DS682PP1
CS5464
5. FUNCTIONAL DESCRIPTION
5.1 Analog Inputs
The CS5464 is equipped with three fully differential input channels. The inputs VIN±, IIN±, and IIN2± are designated as the voltage, current, and current 2 channel
inputs, respectively. The full-scale differential input voltage for the current and voltage channel is ±250 mVP.
5.1.1 Voltage Channel Input
250mV P
2
5.2 IIR Filters
The current and voltage channels are equipped with a
3rd-order IIR filter, that is used to compensate for the
magnitude roll off of the low-pass decimation filter.
5.3 High-pass Filters
The output of the line voltage resistive divider or transformer is connected to the VIN+ and VIN- input pins of
the CS5464. The voltage channel is equipped with a
10x fixed-gain amplifier. The full-scale signal level that
can be applied to the voltage channel is ±250 mV. If the
input signal is a sine wave, the maximum RMS voltage
at a gain 10x is:
--------------------- ≅ 176.78mV
applied to the voltage and/or current channel, the maximum input range should be adjusted accordingly.
RMS
which is approximately 70.7% of maximum peak voltage. The voltage channel is also equipped with a Voltage Gain Register, allowing for an additional
programmable gain of up to 4x.
By removing the offset from either channel, no error
component will be generated at DC when computing the
active power. By removing the offset from both channels, no error component will be generated at DC when
computing VRMS, IRMS, and apparent power. Operational Mode Register bits VHPF, VHPF2, IHPF and IHPF2
activate the HPF in the voltage and current channel, respectively. When a high-pass filter is active in only one
channel, an all-pass filter (APF) is applied to the companion channel. The APF has an amplitude response
that is flat within the channel bandwidth and is used for
matching phase in systems where only one HPF is engaged.
VHPF(2) IHPF(2)
5.1.2 Current Channel Inputs
0
The output of the current-sense resistor or transformer
is connected to the IIN+ (IIN2+) and IIN- (IIN2-) input
pins of the CS5464. To accommodate different current-sensing elements, the current channel incorporates a programmable gain amplifier (PGA) with two
programmable input gains. Configuration Register bit
Igain (I2gain) defines the two gain selections and corresponding maximum input signal level.
Igain, I2gain
Maximum Input
Gain
0
±250 mV
10x
1
±50 mV
50x
Table 1. Current Channel PGA Setting
For example, if Igain=0 (I2gain=0), current channel 1(2)
PGA gain is set to 10x. If the input signals are pure sinusoids with zero phase shift, the maximum peak differential signal on the current or voltage channel is
±250 mVP. The input signal levels are approximately
70.7% of maximum peak voltage and produce a
full-scale energy pulse registration equal to 50% of absolute maximum energy registration. This will be discussed further in See Section 5.5 Energy Pulse Output
on page 18.
0
Filter Configuration
All Filters Off on Channel 1(2)
0
1
HPF on Current Channel 1(2)
1
0
HPF on Voltage Channel 1(2)
1
1
HPF on Current & Voltage Channels 1(2)
Table 2. High-pass Filter Configuration
5.4 Performing Measurements
The CS5464 performs measurements of instantaneous
voltage (Vn) and current (In), and calculates instantaneous power (Pn) at an output word rate (OWR) of
( MCLK ⁄ K )
OWR = ----------------------------1024
where K is the value of the clock divider selected in the
Configuration Register by bits K[3:0]. Note that a value
of K[3:0] = 0000 results in a clock divider setting of 16,
rather than zero.
The RMS voltage (VRMS, V2RMS), RMS current (IRMS,
I2RMS), and active power (Pactive, P2active) are computed using N instantaneous samples of Vn, In, and Pn respectively, where N is the value in the Cycle Count
Register and is referred to as a “computation cycle”. The
apparent power (S, S2) is the product of VRMS and IRMS.
A computation cycle is derived from the master clock
The Current Gain Register also facilitates an additional
programmable gain of up to 4x. If an additional gain is
DS682PP1
17
CS5464
(MCLK), with frequency: Under default conditions and
OWR
Computation Cycle = --------------N
with K = 1, N = 4000, and MCLK = 4.096 MHz – the
OWR = 4000 and the Computation Cycle = 1 Hz.
All measurements are available as a percentage of full
scale. The format for signed registers is a two’s complement, normalized value between -1 and +1. The format
for unsigned registers is a normalized value between 0
and 1. A register value of
23
(2 – 1)
------------------------ = 0.99999988
23
2
the sign of both active and reactive energy. (See Figure
2. Timing Diagram for E1, E2, and E3 on page 13.)
The E1 pulse output is designed to indicate the Active
Energy. The E2 pin can be used to register Apparent
Energy, to indicate a tamper detection has occurred, or
to indicate the sign of energy. Table 3 defines the pulse
output mode, which is controlled by bit E2MODE[1:0] in
the Operational Mode Register.
E2MODE1 E2MODE0
0
Sign of Energy
0
1
Apparent Energy
1
0
Tamper Indicator
1
1
Reserved
Table 3. E2 Pin Configuration
represents the maximum possible value.
At each instantaneous measurement, the CRDY bit will
be set in the Status Register, and the INT pin will become active if the CRDY bit is unmasked in the Mask
Register. At the end of each computation cycle, the
DRDY bit will be set in the Status Register, and the INT
pin will become active if the DRDY bit is unmasked in
the Mask Register. When these bits are asserted, they
must be cleared before they can be asserted again.
If the Cycle Count Register (N) is set to 2, all output calculations are instantaneous, and DRDY, like CRDY, will
indicate when instantaneous measurements are finished. The Cycle Count Register (N) must be ≥ 2.
Epsilon (ε) is the ratio of the input line frequency (fi) to
the sample frequency (fs) of the ADC.
ε
= fi ⁄ fs
where fs = MCLK / (K x 1024). With MCLK = 4.096 MHz
and clock divider K = 1, fs = 4000 Hz. For the two
most-common line frequencies, 50 Hz and 60 Hz
ε
E2 Output Mode
0
The E3 pin can be set to register Reactive Energy (default), PFMON, Voltage Channel Sign, or Apparent Energy. Table 4 defines the pulse output format, which is
controlled by bits E3MODE[1:0] in the Operational
Mode Register.
E3MODE1
E3MODE0
E3 OutPut Mode
0
0
Reactive Energy
0
1
PFMON
1
0
Voltage Channel Sign
1
1
Apparent Energy
Table 4. E3 Pin Configuration
The pulse output frequencies of E1, E2, and E3 are directly proportional to the power calculated from the input
signals. The value contained in the PulseRateE Register is the ratio of the frequency of energy-output pulses
to the number of samples, at full scale, which defines
the average frequency for the output pulses. The pulse
width, tpw in Figure 2, is an integer multiple of MCLK cycles approximately equal to:
= 50 Hz ⁄ 4000 Hz = 0.0125
t pw ( sec )
1
≅ (-----------------------------------MCLK/K ) / 1024
and
ε
= 60 Hz ⁄ 4000 Hz = 0.015
respectively. Epsilon is used to set the gain of the 90°
phase shift (IIR) filter for the average reactive power calculation.
5.5 Energy Pulse Output
The CS5464 provides three output pins for energy registration. By default, E1 is used to register active energy,
E3 is used to register reactive energy, and E2 indicates
18
If MCLK = 4.096 MHz and K = 1 then tpw ≅ 0.25 ms.
5.5.1 Active Energy
The E1 pin produces active-low pulses with an output
frequency proportional to the active power. The E2 pin
is the energy direction indicator. Positive energy is represented by E1 pin falling while the E2 is high. Negative
energy is represented by the E1 pin falling while the E2
is low. The E1 and E2 switching characteristics are
DS682PP1
CS5464
specified in Figure 2. Timing Diagram for E1, E2, and E3
on page 13.
Figure 6 illustrates the pulse output format with positive
active energy and negative reactive energy.
E1
E2
E3
Figure 6. Active and Reactive energy pulse outputs
The pulse output frequency of E1 is directly proportional
to the active power calculated from the input signals. To
calculate the output frequency of E1, the following transfer function can be utilized:
VIN × VGAIN × IIN × IGAIN × PF × PulseRate
FREQ P = --------------------------------------------------------------------------------------------------------------------------------2
VREFIN
FREQP = Average frequency of active energy E1 pulses [Hz]
VIN = rms voltage across VIN+ and VIN- [V]
VGAIN = Voltage channel gain
IIN = rms voltage across IIN+ and IIN- [V]
IGAIN = Current channel gain
PF = Power Factor
PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]
VREFIN = Voltage at VREFIN pin [V]
With MCLK = 4.096 MHz, PF = 1, and default settings,
the pulses will have an average frequency equal to the
frequency specified by PulseRateE when the input signals applied to the voltage and current channels cause
full-scale readings in the instantaneous voltage and current registers. The maximum pulse frequency from the
E1 pin is (MCLK/K)/2048.
5.5.2 Apparent Energy Mode
Pin E2 outputs apparent energy pulses when the Operational Mode Register bit E2MODE = 1. Pin E3 outputs
apparent energy pulses when the Operational Mode
Register bits E3MODE[1:0] = 3 (11b). Figure 7 illustrates the pulse output format with apparent energy on
E2 (E2MODE = 1 and E3MODE[1:0] = 0)
E1
E2
E3
function can be utilized to calculate the output frequency
on E2 (and/or E3).
FREQ
S
VIN × VGAIN × IIN × IGAIN × PulseRate
= -----------------------------------------------------------------------------------------------------------------2
VREFIN
FREQS = Average frequency of apparent energy E2 and/or E3 pulses [Hz]
VIN = rms voltage across VIN+ and VIN- [V]
VGAIN = Voltage channel gain
IIN = rms voltage across IIN+ and IIN- [V]
IGAIN = Current channel gain
PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]
VREFIN = Voltage at VREFIN pin [V]
With MCLK = 4.096 MHz and default settings, the pulses will have an average frequency equal to the frequency specified by PulseRateE when the input signals
applied to the voltage and current channels cause
full-scale readings in the instantaneous voltage and current registers. The maximum pulse frequency from the
E2 (and/or E3) pin is (MCLK/K)/2048. The E2 (and/or
E3) pin outputs apparent energy, but has no energy direction indicator.
5.5.3 Reactive Energy Mode
Reactive energy pulses are output on pin E3 by setting
bit E3MODE[1:0] = 0 (default) in the Operational Mode
Register. Positive reactive energy is registered by E3
falling when E2 is high. Negative reactive energy is registered by E3 falling when E2 is low. Figure 6 on
page 19 illustrates the pulse output format with negative
reactive energy output on pin E3 and the sign of the energy on E2. The E3 and E2 pulse output switching characteristics are specified in Figure 2 on page 13.
The pulse output frequency of E3 is directly proportional
to the reactive power calculated from the input signals.
To calculate the output frequency on E3, the following
transfer function can be utilized:
VIN × VGAIN × IIN × IGAIN × PQ × PulseRate
FREQ Q = ---------------------------------------------------------------------------------------------------------------------------------2
VREFIN
FREQQ = Average frequency of reactive energy E3 pulses [Hz]
VIN = rms voltage across VIN+ and VIN- [V]
VGAIN = Voltage channel gain
IIN = rms voltage across IIN+ and IIN- [V]
IGAIN = Current channel gain
PQ = 1 – PF2
PulseRate = PulseRateE x (MCLK/K)/2048 [Hz]
VREFIN = Voltage at VREFIN pin [V]
Figure 7. Apparent energy pulse outputs
The pulse output frequency of E2 (and/or E3) is directly
proportional to the apparent power calculated from the
input signals. Since apparent power is without reference
to an impedance phase angle, the following transfer
DS682PP1
With MCLK = 4.096 MHz, PF = 0 and default settings,
the pulses will have an average frequency equal to the
frequency specified by PulseRateE when the input signals applied to the voltage and current channels cause
full-scale readings in the instantaneous voltage and cur-
19
CS5464
rent registers. The maximum pulse frequency from the
E1 pin is (MCLK/K)/2048.
5.5.4 Voltage Channel Sign Mode
Setting bits E3MODE[1:0] = 2 (10b) in the Operational
Mode Register outputs the sign of the voltage channel
on pin E3. Figure 8 illustrates the output format with voltage channel sign on E3.
Therefore with PF = 1 and:
VIN = 220V × ( ( 150mV ) ⁄ ( 250V ) ) = 132mV
IIN = 15A × ( ( 150mV ) ⁄ ( 20A ) ) = 112.5mV
the pulse rate is:
2
100 × 2.5
PulseRate = ----------------------------------------------------------------- = 420.8754Hz
0.132 × 10 × 0.1125 × 10
and the PulseRateE Register is set to:
E1
E2
PulseRateE =
E3
Figure 8. Voltage Channel Sign Pulse outputs
Output pin E3 is high when the line voltage is positive
and pin E3 is low when the line voltage is negative.
5.5.5 PFMON Output Mode
Setting bit E3MODE[1:0] = 1 (01b) in the Operational
Mode Register outputs the state of the PFMON comparator on pin E3. Figure 9 illustrates the output format with
PFMON on E3.
E1
E2
E3
Above PFMON Threshold
Below PFMON Threshold
Figure 9. PFMON output to pin E3
When PFMON is greater than the threshold, pin E3 is
high and when PFMON is less than the threshold pin E3
is low.
5.5.6 Design Example
EXAMPLE #1:
The maximum rated levels for a power line meter are
250 V rms and 20 A rms. The required number of pulses-per-second on E1 is 100 pulses per second
(100 Hz), when the levels on the power line are
220 V rms and 15 A rms.
PulseRate
--------------------------------------( MCLK ⁄ K ) ⁄ 2048
=
0.2104377
with MCLK = 4.096 MHz and K = 1.
5.6 Sag and Fault Detect Feature
Status bit VSAG (V2SAG) and IFAULT (I2FAULT) in the
Status Register, indicates a sag occurred in the power
line voltage (voltage 2) and current (current 2), respectively. For a sag condition to be identified, the absolute
value of the instantaneous voltage or current must be
less than the sag level for more than half of the sag duration (see Figure 10).
To activate voltage sag detection, a voltage sag level
must be specified in the Voltage Sag Level Register
(VSAGlevel, V2SAGlevel), and a voltage sag duration
must be specified in the Voltage Sag Duration Register
(VSAGduration, V2SAGduration). To activate current fault
detection, a current sag level must be specified in the
Current Fault Level Register (ISAGlevel, I2SAGlevel), and
a current sag duration must be specified in the Current
Fault Duration Register (ISAGduration, I2SAGduration).
The voltage and current sag levels are specified as the
average of the absolute instantaneous voltage and current, respectively. Voltage and current sag duration is
specified in terms of ADC cycles.
With a 10x gain on the voltage and current channel the
maximum input signal is 250 mVP. (See Section 5.1 Analog Inputs on page 17.) To prevent over-driving the
channel inputs, the maximum rated rms input levels will
register 0.6 in VRMS and IRMS by design. Therefore the
voltage level at the channel inputs will be 150 mV rms
when the maximum rated levels on the power lines are
250 V rms and 20 A rms.
Level
Solving for PulseRateE using the transfer function:
2
FREQ P × VREFIN
PulseRate = --------------------------------------------------------------------------------------------VIN × VGAIN × IIN × IGAIN × PF
20
Duration
Figure 10. Sag and Fault Detect
DS682PP1
CS5464
5.7 On-chip Temperature Sensor
The on-chip temperature sensor is designed to assist in
characterizing the measurement element over a desired
temperature range. Once a temperature characterization is performed, the temperature sensor can then be
utilized to assist in compensating for temperature drift.
Temperature measurements are performed during continuous conversions and stored in the Temperature
Register. The Temperature Register (T) default is Celsius scale (°C). The Temperature Gain Register (Tgain)
and Temperature Offset Register (Toff) are constant values allowing for temperature scale conversions.
The temperature update rate is a function of the number
of ADC samples. With MCLK = 4.096 MHz and K = 1
the update rate is:
2240 samples
--------------------------------------- =
( MCLK ⁄ K ) ⁄ 1024
0.56 sec
Applying the above relationship to the CS5461A temperature measurement algorithm
–4
o
o
9
T 〈 F〉 = ⎛⎝ --- × T gain ⎞⎠ T 〈 C〉 + ⎛⎝ T off + ( 17.7778 × 2.737649 ⋅ 10 )⎞⎠
5
If Toff = -0.09504 and Tgain = 26.443 for a Celsius scale,
then the modified values are Toff = -0.09017
(0xF47550) and Tgain = 47.6 (0x5F3333) for a Fahrenheit scale.
5.8 Voltage Reference
The CS5464 is specified for operation with a +2.5 V reference between the VREFIN and AGND pins. To utilize
the on-chip 2.5 V reference, connect the VREFOUT pin
to the VREFIN pin of the device. The VREFIN can be
used to connect external filtering and/or references.
The Cycle Count Register (N) must be set to a value
greater than one. Status bit TUP in the Status Register,
indicates when the Temperature Register is updated.
5.9 System Initialization
The Temperature Offset Register sets the zero-degree
measurement. To improve temperature measurement
accuracy, the zero-degree offset may need to be adjusted after the CS5464 is initialized. Temperature-offset
calibration is achieved by adjusting the Temperature
Offset Register (Toff) by the differential temperature
(∆T) measured from a calibrated digital thermometer
and the CS5464 temperature sensor. A one-degree adjustment to the Temperature Register (T) is achieved by
adding 2.737649x10-4 to the Temperature Offset Register (Toff). Therefore,
A hardware reset is initiated when the RESET pin is asserted with a minimum pulse width of 50 ns. The RESET signal is asynchronous, with a Schmitt-trigger
input. Once the RESET pin is de-asserted, an
eight-XIN-clock-period delay is enabled.
T off
=
T off
+ ( ∆ T × 2.737649 ⋅ 10 – 4 )
if Toff = -0.094488 and ∆T = -2.0 (°C), then
T
off
= ( – 0.094488 + ( – 2.0 × 2.737649 ⋅ 10 –4 ) ) =
– 0.09504
or 0xF3D5BB (2’s compliment notation) is stored in the
Temperature Offset Register (Toff).
To convert the Temperature Register (T) from a Celsius
scale (°C) to a Fahrenheit scale (°F) utilize the formula
o
9 o
F = --- ( C + 17.7778 )
5
Upon powering up, the digital circuitry is held in reset
until the analog voltage reaches 4.0 V. At that time, an
eight-XIN-clock-period delay is enabled to allow the oscillator to stabilize. The CS5464 will then initialize.
A software reset is initiated by writing the command
0x80. After a hardware or software reset, the internal
registers (some of which drive output pins) will be reset
to their default values. Status bit DRDY in the Status
Register, indicates the CS5464 is in its active state and
ready to receive commands.
5.10 Power-down States
The CS5464 has two power-down states, Stand-by and
Sleep. In the stand-by state all circuitry except the voltage reference and crystal oscillator is turned off. To return the device to the active state, a power-up command
is sent to the device.
In Sleep state, all circuitry except the instruction decoder is turned off. When the power-up command is sent to
the device, a system initialization is performed (See
Section 5.9 System Initialization on page 21).
5.11 Oscillator Characteristics
XIN and XOUT are the input and output of an inverting
amplifier configured as an on-chip oscillator, as shown
in Figure 11. The oscillator circuit is designed to work
DS682PP1
21
CS5464
with a quartz crystal. To reduce circuit cost, two load capacitors C1 and C2 are integrated in the device, from
XIN to DGND, and XOUT to DGND. PCB trace lengths
should be minimized to reduce stray capacitance. To
drive the device from an external clock source, XOUT
should be left unconnected while XIN is driven by the
external circuitry. There is an amplifier between XIN and
the digital section which provides CMOS level signals.
This amplifier works with sinusoidal inputs so there are
no problems with slow edge times.
The CS5464 can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must
be set such that the internal MCLK will run somewhere
between 2.5 MHz and 5 MHz. The K divider value is set
with the K[3:0] bits in the Configuration Register. As an
example, if XIN = MCLK = 15 MHz, and K is set to 5,
DCLK will equal 3 MHz, which is a valid value for DCLK.
5.12 Event Handler
The INT pin is used to indicate that an internal error or
event has taken place in the CS5464. Writing a logic 1
to any bit in the Mask Register allows the corresponding
bit in the Status Register to activate the INT pin. The interrupt condition is cleared by writing a logic 1 to the bit
that has been set in the Status Register.
The behavior of the INT pin is controlled by the IMODE
and IINV bits of the Configuration Register.
IMODE
IINV
INT Pin
0
0
Active-low Level
0
1
Active-high Level
1
0
Low Pulse
1
1
High Pulse
Table 5. Interrupt Configuration
If the interrupt output signal format is set for either falling
or rising edge, the duration of the INT pulse will be at
least one DCLK cycle (DCLK = MCLK/K).
XOUT
C1
Oscillator
Circuit
5.12.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
XIN
INITIALIZATION:
C2
DGND
1) All Status bits are cleared by writing 0xFFFFFF to
the Status Register.
C1 = C2 = 22 pF
Figure 11. Oscillator Connection
22
2) The condition bits which will be used to generate
interrupts are then set to logic 1 in the Mask Register.
3) Enable interrupts.
DS682PP1
CS5464
INTERRUPT HANDLER ROUTINE:
4) Read the Status Register.
5) Disable all interrupts.
6) Branch to the proper interrupt service routine.
7) Clear the Status Register by writing back the read
value in step 4.
8) Re-enable interrupt
If the serial port interface becomes unsynchronized with
respect to the SCLK input, any attempt to clock valid
commands into the serial interface may result in unexpected operation. Therefor, the serial port interface
must then be re-initialized by one of the following actions:
-
Drive the CS pin high, then low.
-
Hardware Reset (drive RESET pin low for at
least 10 µs).
-
Issue the Serial Port Initialization Sequence,
which is 3 (or more) SYNC1 command bytes
(0xFF) followed by one SYNC0 command byte
(0xFE).
9) Return from interrupt service routine.
This handshaking procedure ensures that any new interrupts activated between steps 4 and 7 are not lost
(cleared) by step 7.
5.13 Serial Port Overview
The CS5464 incorporates a serial port transmit and receive buffer with a command decoder that interprets
one-byte (8-bit) commands as they are received. There
are four types of commands: instructions, synchronizing, register writes, and register reads (See Section
5.15 Commands on page 24).
Instructions are one byte in length and will interrupt any
instruction currently executing. Instructions do not affect
register reads currently being transmitted.
Synchronizing commands are one byte in length and
only affect the serial interface. Synchronizing commands do not affect operations currently in progress.
If a re-synchronization is necessary, it is best to re-initialize the part either by hardware or software reset
(command 0x80), as the state of the part may be unknown.
5.14 Register Paging
Read/write commands access one of the 32 registers
within a specified page. By default, Page = 0. To access
registers in another page, the Page Register (address
0x1F) must be written with the desired page number.
0xFFF
Register writes must be followed by three bytes of data.
Register reads can return up to four bytes of data.
Commands and data are transferred most-significant bit
(MSB) first. Figure 1 on page 12, defines the serial port
timing and required sequence necessary for writing to
and reading from the serial port receive and transmit
buffer, respectively. While reading data from the serial
port, commands and data can be written simultaneously. Starting a new register read command while data is
being read will terminate the current read in progress.
This is acceptable if the remainder of the current read
data is not needed. During data reads, the serial port requires input data. If a new command and data is not
sent, SYNC0 or SYNC1 must be sent.
Pages
0x40 - 0x7F
Hardware Registers*
32 Pages
Pages
0x20 - 0x3F
Software Register*
32 Pages
Pages
0 - 0x1F
0x800
0x7FF
0x400
0x3FF
0x000
* Accessed using register read/write commands.
5.13.1 Serial Port Interface
The serial port interface is a “4-wire” synchronous serial
communications interface. The interface is enabled to
start excepting SCLKs when CS (Chip Select) is asserted (logic 0). SCLK (Serial bit-clock) is a Schmitt-trigger
input that is used to strobe the data on SDI (Serial Data
In) into the receive buffer and out of the transmit buffer
onto SDO (Serial Data Out).
ROM
2048 Words
Figure 12. CS5464 Memory Map
Example:
Reading register 6 in page 3.
1. Write 3 to page register with command and data:
0x7E 0x00 0x00 0x03
2. Read register 6 with command:
0x0C 0xFF 0xFF 0xFF
DS682PP1
23
CS5464
5.15 Commands
All commands are 8 bits in length. Any command byte value that is not listed in this section is invalid. Commands
that write to registers must be followed by 3 bytes of data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent which can execute during the original read). All commands except register reads, register writes, and SYNC0 & SYNC1 will abort any currently executing commands.
5.15.1 Start Conversions
B7
1
B6
1
B5
1
B4
0
B3
C3
B2
0
B1
0
B0
0
Initiates acquiring measurements and calculating results. The device has two modes of acquisition.
C3
Modes of acquisition/measurement
0 = Perform a single computation cycle
1 = Perform continuous computation cycles
5.15.2 SYNC0 and SYNC1
B7
1
B6
1
B5
1
B4
1
B3
1
B2
1
B1
1
B0
SYNC
The serial port is resynchronized to byte boundaries by sending three or more consecutive SYNC1 commands followed by a SYNC0 command. The SYNC0 or SYNC1 commands can also be used as a NOP command.
SYNC
Designates calibration
0 = This command is the end of the serial port re-initialization sequence.
1 = This command is part of the serial port re-initialization sequence.
5.15.3 Power-down, Power-up, Halt and Software Reset
B7
1
B6
0
B5
S1
B4
S0
B3
0
B2
0
B1
0
B0
0
To conserve power the CS5464 has two power-down states. In stand-by state all circuitry, except the analog/digital
clock generators, is turned off. In the sleep state all circuitry, except the digital clock generator and the command
decoder, is turned off. Bringing the CS5464 out of sleep state requires more time than out of stand-by state, because
of the extra time needed to re-start and re-stabilize the analog clock signal. If the device is powered-down, Power-Up/Halt will initiate a power on reset. If the part is already powered-on, all computations will be halted.
S[1:0]
24
Power-down state
00 = Software Reset
01 = Halt and enter sleep power saving state. This state requires a slow power-on time
10 = Power-up and Halt
11 = Halt and enter stand-by power saving state. This state allows quick power-on time
DS682PP1
CS5464
5.15.4 Register Read/Write
B7
0
B6
W/R
B5
RA4
B4
RA3
B3
RA2
B2
RA1
B1
RA0
B0
0
The Read/Write informs the command decoder that a register access is required. During a read operation, the addressed register is loaded into the device’s output buffer and clocked out by SCLK. During a write operation, the
data is clocked into the input buffer and transferred to the addressed register upon completion of the 24th SCLK.
W/R
Write/Read control
0 = Read register
1 = Write register
RA[4:0]
Register address bits (bits 5 through 1) of the read/write command.
Page 0
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RA[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Name
Config
I
V
P
PActive
IRMS
VRMS
I2
V2
P2
P2Active
I2RMS
V2RMS
QAvg
Q
Status
Q2Avg
Q2
Ipeak
Vpeak
S
PF
I2peak
V2peak
S2
PF2
Mask
T
Ctrl
Ppulse
Spulse
Qpulse / Page
Description
Configuration
Instantaneous Current
Instantaneous Voltage
Instantaneous Power
Average Active (Real) Power
RMS Current
RMS Voltage
Instantaneous Current 2
Instantaneous Voltage 2
Instantaneous Power 2
Average Active (Real) Power 2
RMS Current 2
RMS Voltage 2
Average Reactive Power
Instantaneous Reactive Power
Status (Write of ‘1’ to status bit will clear the bit)
Average Reactive Power 2
Instantaneous Reactive Power 2
Peak Current
Peak Voltage
Apparent Power
Power Factor
Peak Current 2
Peak Voltage 2
Apparent Power 2
Power Factor 2
Mask
Temperature
Control
Active Energy Pulse Output Accumulator
Apparent Energy Pulse Output Accumulator
Reactive Energy Pulse Output Accumulator (read only)
and Page (write only)
Note: For proper operation, do not attempt to write to unspecified registers.
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CS5464
Page1
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
28
RA[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01111
10000
10001
10010
10011
10100
10101
10110
10111
11100
Name
Idcoff
Ign
Vdcoff
Vgn
Poff
Iacoff
Vacoff
I2dcoff
I2gn
V2dcoff
V2gn
P2off
I2acoff
V2acoff
PulseRateE
Mode
Epsilon
Tamperlevel
Cycle Count
QTrig
Q2Trig
TGain
Toff
SYSgain
Description
Current DC offset
Current Gain Calibration
Voltage DC offset
Voltage Gain Calibration
Power Offset
Current AC (RMS) offset
Voltage AC (RMS) offset
Current DC offset 2
Current Gain Calibration 2
Voltage DC offset 2
Voltage Gain Calibration 2
Power Offset 2
Current AC (RMS) offset 2
Voltage AC (RMS) offset 2
Sets the energy-to-frequency output pulse rate
Operational Modes
Epsilon
Sets tamper threshold level
Number of conversions in one computation cycle (N)
Reactive Power calculated from Power Triangle
Reactive Power calculated from Power Triangle 2
Temperature Sensor Gain
Temperature Sensor Offset
System Gain
RA[4:0]
00000
00001
00100
00101
01000
01001
01100
01101
Name
VSAGduration
VSAGlevel
ISAGduration
ISAGlevel
V2SAGduration
V2SAGlevel
I2SAGduration
I2SAGlevel
Description
VSAG Duration
VSAG Level
ISAG Duration
ISAG Level
VSAG Duration 2
VSAG Level 2
ISAG Duration 2
ISAG Level 2
Page2
Address
0
1
4
5
8
9
12
13
Note: For proper operation, do not attempt to write to unspecified registers.
26
DS682PP1
CS5464
5.15.5 Calibration
B7
1
B6
0
B5
CAL5
B4
CAL4
B3
CAL3
B2
CAL2
B1
CAL1
B0
CAL0
The CS5464 can perform system calibrations. Proper input signals must be applied to the current and voltage channel before performing a designated calibration.
CAL[5:4]*
Designates calibration to be performed
00 = Channel DC offset
01 = Channel DC gain
10 = Channel AC offset
11 = Channel AC gain
CAL[3:0]*
Designates channel to calibrate
0001 = Current channel
0010 = Voltage channel
0100 = Current channel 2
1000 = Voltage channel 2
*By utilizing different combinations for CAL[3:0], multiple channels can be calibrated simultaneously, e.g.
CAL[5:0] = 001111 commands the CS5464 to perform a DC offset calibration on all four channels. Values
for CAL[5:0] not specified should not be used.
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CS5464
6. REGISTER DESCRIPTION
1.
“Default” = bit status after power-on or reset
2.
Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
6.1 Page 0 Registers
6.1.1 Configuration (Config) Register
Address: 0
23
PC[7]
22
PC[6]
21
PC[5]
20
PC[4]
19
PC[3]
18
PC[2]
17
PC[1]
16
PC[0]
15
EWA
14
-
13
-
12
IMODE
11
IINV
10
-
9
-
8
-
7
-
6
-
5
-
4
iCPU
3
K[3]
2
K[2]
1
K[1]
0
K[0]
Default = 0x000001
28
PC[7:0]
Phase compensation. Sets a delay in the voltage channel relative to the current channel 1. Default setting is 00000000 = 0.0215 degree phase delay at 60 Hz (when MCLK = 4.096 MHz).
EWA
Allows the E1 and E2 pins to be configured as open-collector output pins.
0 = Normal outputs (default)
1 = Only the pull-down device of the E1 and E2 pins are active
IMODE, IINV
Soft interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = Active-low level (default)
01 = Active-high level
10 = Low pulse
11 = High pulse
iCPU
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising edge logic
K[3:0]
Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range between 1 and 16. Note that a value of “0000” will set K to 16 (not zero). K = 1 at reset.
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CS5464
6.1.2 Instantaneous Current (I, I2), Voltage (V, V2), and Power (P, P2) Registers
Address: 1 (I), 2 (V), 3 (P), 7 (I2), 8 (V2), 9 (P2)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
I (I2) and V (V2)contain the instantaneous measured values for current and voltage, respectively. The instantaneous voltage (voltage 2) and current (current 2) samples are multiplied to obtain Instantaneous Power, P (P2).
The value is represented in two's complement notation and in the range of -1.0 ≤ I, V, P < 1.0
(-1.0 ≤ I2, V2, P2 < 1.0), with the binary point to the right of the MSB.
6.1.3 Active (Real) Power (PActive, P2Active) Registers
Address: 4 (PActive), 10 (P2Active)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
The instantaneous power is averaged over each computation cycle (N conversions) to compute Active Power,
PActive (P2Active). The value will be within in the range of -1.0 ≤ PActive< 1.0 (-1.0 ≤ P2Active< 1.0). The value is represented in two's complement notation, with the binary point to the right of the MSB.
6.1.4 RMS Current (IRMS, I2RMS) & Voltage (VRMS, V2RMS) Registers
Address: 5 (IRMS), 6 (VRMS), 11 (I2RMS), 12 (V2RMS)
MSB
2-1
LSB
2-2
2-3
2-4
2-5
2-6
2-7
2-8
.....
2-18
2-19
2-20
2-21
2-22
2-23
2-24
IRMS (I2RMS) and VRMS (V2RMS) contain the Root Mean Square (RMS) values of I (I2) and V (V2), calculated
each computation cycle. The value is represented in unsigned binary notation and in the range of
0.0 ≤ IRMS, VRMS < 1.0 (0.0 ≤ I2RMS, V2RMS < 1.0), with the binary point to the left of the MSB.
6.1.5 Instantaneous Reactive Power (Q, Q2) Registers
Address: 14 (Q), 17 (Q2)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
The Instantaneous Reactive Power (Q, Q2) is the product of the voltage (voltage 2) signal, shifted 90 degrees,
and the current (current 2) signal. The value is represented in two's complement notation and in the range of
-1.0 < Q < 1.0 (1.0 < Q2 < 1.0), with the binary point to the right of the MSB.
6.1.6 Average Reactive Power (QAvg, Q2Avg) Registers
Address: 13 (QAvg), 16 (Q2Avg)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
The Average Reactive Power (QAVG, Q2AVG) is Q (Q2) averaged over N samples. The value is represented in
two's complement notation and in the range of -1.0 < QAVG < 1.0 (-1.0 < Q2AVG < 1.0), with the binary point to
the right of the MSB.
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CS5464
6.1.7 Status (Status) and Mask (Mask) Register
Address: 15 (Status); 26 (Mask)
23
DRDY
22
I2OR
21
V2OR
20
CRDY
19
I2ROR
18
V2ROR
17
IOR
16
VOR
15
E2OR
14
IROR
13
VROR
12
EOR
11
IFAULT
10
VSAG
9
I2FAULT
8
V2SAG
7
TUP
6
V2OD
5
I2OD
4
VOD
3
IOD
2
LSD
1
FUP
0
IC
Default =
0x800001 (Status Register), 0x000000 (Mask Register)
The Status Register indicates status within the chip. In normal operation, writing a '1' to a bit will cause the bit
to reset. Writing a '0' to a bit will not change it’s current state.
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in a Mask bit will allow the
corresponding bit in the Status Register to activate the INT pin when the status bit is asserted.
DRDY
Data Ready. During conversions, this bit will indicate the end of computation cycles. For calibrations, this bit indicates the end of a calibration sequence.
IOR (I2OR)
Current Out of Range. Set when the magnitude of the measured current value causes the I
(I2) register to overflow.
VOR (V2OR)
Voltage Out of Range. Set when the magnitude of the measured voltage value causes the
V (V2) register to overflow.
CRDY
Conversion Ready. Indicates a new conversion is ready. This will occur at the output word
rate.
IROR (I2ROR)
RMS Current Out of Range. Set when the calculated RMS current value causes the IRMS
(I2RMS) register to overflow.
VROR (V2ROR)
RMS Voltage Out of Range. Set when the calculated RMS voltage value causes the VRMS
(V2RMS) register to overflow.
EOR (E2OR)
Energy Out of Range. Set when PActive (P2Active) overflows.
IFAULT (I2FAULT) Indicates a current fault occurred in the power line current. If the absolute value of the instantaneous current is less than ISAGlevel (I2SAGlevel) for more than half of the ISAGduration
(I2SAGduration), the IFAULT (I2FAULT) bit will be set.
VSAG (V2SAG)
Indicates a voltage sag occurred in the power line voltage. If the absolute value of the instantaneous voltage is less than VSAGlevel (V2SAGlevel) for more than half of the VSAGduration
(V2SAGduration), the VSAG (V2SAG) bit will be set.
TUP
Temperature Updated. Indicates a temperature conversion is ready.
VOD (V2OD)
Modulator Oscillation Detected on the voltage (voltage 2) channel. Set when the modulator
oscillates due to an input above full scale. The level at which the modulator oscillates is significantly higher than the voltage (voltage 2) channel’s differential input voltage range.
IOD (I2OD)
Modulator Oscillation Detected on the current (current 2) channel. Set when the modulator
oscillates due to an input above full scale. The level at which the modulator oscillates is significantly higher than the current (current 2) channel’s differential input voltage range.
Note: The IOD (I2OD) and VOD (V2OD) bits may be ‘falsely’ triggered by very brief voltage
30
DS682PP1
CS5464
spikes from the power line. This event should not be confused with a DC overload
situation at the inputs, when the IOD (I2OD) and VOD (V2OD) bits will re-assert
themselves even after being cleared, multiple times.
LSD
Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage threshold (PMLO), with respect to AGND pin. For a given part, PMLO can be as low as 2.3 V. LSD bit
cannot be permanently reset until the voltage at PFMON pin rises back above the high-voltage
threshold (PMHI), which is typically 100 mV above the device’s low-voltage threshold. PMHI will
never be greater than 2.7 V.
FUP
Epsilon Updated. Indicates an update to the epsilon value has been placed in the register.
IC
Invalid Command. Normally logic 1. Set to logic 0 if the host interface is strobed with an 8-bit
word that is not recognized as one of the valid commands (see See Section 5.15 Commands
on page 24).
6.1.8 Peak Current (Ipeak, I2peak) and Peak Voltage (Vpeak, V2peak) Register
Address: 18 (Ipeak), 19 (Vpeak), 22 (I2peak), 23 (V2peak)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
The Peak Current (Ipeak, I2peak) and Peak Voltage (Vpeak, V2peak) registers contain the instantaneous current
and voltage with the greatest magnitude detected during the last computation cycle. The value is represented
in two's complement notation and in the range of -1.0 ≤ Ipeak, Vpeak < 1.0 (-1.0 ≤ I2peak, V2peak < 1.0), with the
binary point to the right of the MSB.
6.1.9 Apparent Power (S, S2) Register
Address: 20 (S), 24 (S2)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Apparent power S (S2) is the product of the VRMS and IRMS (V2RMS and I2RMS), The value is represented in
unsigned notation and in the range of 0 ≤ S < 1.0 (0 ≤ S2 < 1.0), with the binary point to the right of the MSB.
6.1.10 Power Factor (PF, PF2) Register
Address: 21, 25
MSB
-(20)
2-1
LSB
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Power Factor is calculated by dividing the Active (Real) Power by Apparent Power. The value is represented in
two's complement notation and in the range of -1.0 ≤ PF < 1.0 (-1.0 ≤ PF2 < 1.0), with the binary point to the
right of the MSB.
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CS5464
6.1.11 Temperature (T) Register
Address: 27
MSB
LSB
-(27)
26
25
24
23
22
21
20
2-10
.....
2-11
2-12
2-13
2-14
2-15
2-16
T contains measurements from the on-chip temperature sensor. Measurements are performed during continuous conversions, with the default the Celsius scale (oC). The value is represented in two's complement notation
and in the range of -128.0 ≤ T < 128.0, with the binary point to the right of the eighth MSB.
6.1.12 Control (Crtl) Register
Register Address: 28
23
PC2[7]
22
PC2[6]
21
PC2[5]
20
PC2[4]
19
PC2[3]
18
PC2[2]
17
PC2[1]
16
PC2[0]
15
-
14
-
13
-
12
I2gain
11
-
10
-
9
-
8
STOP
7
-
6
-
5
Igain
4
INTOD
3
-
2
NOCPU
1
NOOSC
0
-
Default = 0x000000
32
PC2[7:0]
Phase compensation. Sets a delay in the voltage channel relative to current channel 2. Default
setting is 00000000 = 0.0215 degree phase delay at 60 Hz (when MCLK = 4.096 MHz).
Igain (I2gain)
Sets the gain of the current (current 2) PGA.
0 = Gain is 10 (default)
1 = Gain is 50
STOP
Terminates the auto-boot sequence.
0 = Normal (default)
1 = Stop sequence
INTOD
Converts INT output pin to an open drain output.
0 = Normal (default)
1 = Open drain
NOCPU
Saves power by disabling the CPUCLK pin.
0 = Normal (default)
1 = Disables CPUCLK
NOOSC
Saves power by disabling the crystal oscillator.
0 = Normal (default)
1 = Disabling oscillator circuit
DS682PP1
CS5464
6.1.13 Active Energy Pulse Output Accumulator (Ppulse) Register
Address: 29
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
The Active Energy Pulse Output Accumulator (Ppulse) contains the sum of the active power and is used to drive
the pulse output. If a tamper condition is detected, this register is equal to P2Active. The value is represented in
two's complement notation and in the range of -1.0 ≤ Ppulse < 1.0, with the binary point to the right of the MSB.
6.1.14 Apparent Energy Pulse Output Accumulator (Spulse) Register
Address: 30
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
The Apparent Energy Pulse Output Accumulator (Spulse) contains the apparent power and is used to drive the
pulse output. This result is updated after each computation cycle. If a tamper condition is detected, this register
is equal to S2. The value is represented in two's complement notation and in the range of -1.0 ≤ Spulse < 1.0,
with the binary point to the right of the MSB.
6.1.15 Reactive Energy Pulse Output Accumulator (Qpulse) Register
Address: 31 (read only)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
The Reactive Energy Pulse Output Accumulator (Qpulse) contains the sum of the reactive power and is used to
drive the pulse output. If a tamper condition is detected, this register is equal to Q2Avg. The value is represented
in two's complement notation and in the range of -1.0 ≤ Qpulse < 1.0, with the binary point to the right of the MSB.
6.1.16 Page Register
Address: 31 (write only)
MSB
26
LSB
25
24
23
22
21
20
Default = 0x00
Determines which register page the serial port will access.
DS682PP1
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CS5464
6.2 Page 1 Registers
6.2.1 Current DC Offset (Idcoff, I2dcoff) and Voltage DC Offset (Vdcoff, V2dcoff) Registers
Address: 0 (Idcoff), 2 (Vdcoff), 7 (I2dcoff), 9 (V2dcoff)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0x000000
The DC Offset registers (Idcoff,Vdcoff, I2dcoff,V2dcoff) are initialized to 0.0 on reset. When DC Offset calibration is
performed, the register is updated with the DC offset measured over a computation cycle. DRDY will be set at
the end of the calibration. This register may be read and stored for future system offset compensation. The value
is represented in two's complement notation and in the range of -1.0 ≤ Idcoff, Vdcoff < 1.0
(-1.0 ≤ I2dcoff, V2dcoff < 1.0), with the binary point to the right of the MSB. See Section 7.1.2.1 DC Offset Calibration Sequence on page 39 for more information.
6.2.2 Current Gain (Ign, I2gn) and Voltage Gain (Vgn, V2gn) Registers
Address: 1 (Ign), 3 (Vgn), 8 (I2gn), 10 (V2gn)
MSB
21
LSB
20
2-1
2-2
2-3
2-4
2-5
2-6
.....
2-16
2-17
2-18
2-19
2-20
2-21
2-22
Default = 0x400000 = 1.000
The gain registers (Ign,Vgn, I2gn,V2gn) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is
performed, the register is updated with the gain measured over a computation cycle. DRDY will be set at the
end of the calibration. This register may be read and stored for future system gain compensation. The value is
in the range 0.0 ≤ Ign,Vgn < 3.9999 (0.0 ≤ I2gn,V2gn < 3.9999), with the binary point to the right of the second
MSB.
6.2.3 Power Offset (Poff, P2off) Registers
Address: 4 (Poff), 11 (P2off)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0x000000
Power Offset (Poff, P2off) is added to the instantaneous power being accumulated in the Pactive (P2active) register, and can be used to offset contributions to the energy result that are caused by undesirable sources of energy
that are inherent in the system. The value is represented in two's complement notation and in the range of
-1.0 ≤ Poff < 1.0 (-1.0 ≤ P2off < 1.0), with the binary point to the right of the MSB.
6.2.4 Current AC Offset (Iacoff, I2acoff) and Voltage AC Offset (Vacoff, V2acoff) Registers
Address: 5 (Iacoff), 6 (Vacoff), 12 (I2acoff), 13 (V2acoff)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0x000000
The AC Offset Registers (Vacoff, Iacoff, V2acoff, I2acoff) are initialized to zero on reset, allowing for uncalibrated normal
operation. AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cycles (where N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration.
34
DS682PP1
CS5464
These values may be read and stored for future system AC offset compensation. The value is represented in
two's complement notation in the range of -1.0 ≤ Vacoff, Iacoff < 1.0 (-1.0 ≤ V2acoff, I2acoff < 1.0), with the binary point
to the right of the MSB.
6.2.5 PulseRateE Register
Address: 15
MSB
-(2
LSB
0)
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-17
.....
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0x800000 = 1.00 (2 kHz @ 4.096 MHz MCLK)
PulseRateE sets the frequency of E1, E2, & E3 pulses. E1, E2, E3 frequency = (MCLK x PulseRateE) / 2048 at
full scale. For a 4 khz sample rate, the maximum pulse rate is 2 khz. The value is represented in two's complement notation and in the range is -1.0 ≤ PulseRateE < 1.0, with the binary point to the right of the MSB. Negative
values have the same effect as positive. See Section 5.5 Energy Pulse Output on page 18 for more information.
6.2.6 Operational Mode (Mode) Register
Address: 16
23
TAMPER
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
TOFF
11
-
10
E2MODE[1]
9
E2MODE[0]
8
VHPF2
7
6
5
4
3
2
1
0
IHPF2
VHPF
IHPF
-
E3MODE[1]
E3MODE[0]
POS
AFC
Default = 0x000000
TAMPER
Indicates when the meter has been tampered with.
0 = Normal operation. Energy is registered using P. (default)
1 = Tamper condition has been detected. Energy is registered using P2.
TOFF
Tamper Detection Off
0 = Enables tamper detection. (default)
1 = Disables tamper detection.
E2MODE[1:0]
E2 Output Mode
00 = Sign of Active Power (default)
01 = Apparent Power
10 = Tamper Detect
11 = Reserved
VHPF2:IHPF2 High-pass Filter Enable
00 = High-pass filter disabled on voltage channel 2 & current channel 2 (default)
01 = High-pass filter enabled on current channel 2 with all-pass filter on voltage channel 2
10 = High-pass filter enabled on voltage channel 2 with all-pass filter on current channel 2
11 = High-pass filter enabled on voltage channel 2 & current channel 2
VHPF:IHPF
DS682PP1
High-pass Filter Enable
00 = High-pass filter disabled on voltage channel 1 & current channel 1 (default)
01 = High-pass filter enabled on current channel 1 with all-pass filter on voltage channel 1
10 = High-pass filter enabled on voltage channel 1 with all-pass filter on current channel 1
11 = High-pass filter enabled on voltage channel 1 & current channel 1
35
CS5464
E3MODE1:0
E3 Output Mode
00 = Reactive Power (default)
01 = PFMON
10 = Voltage sign
11 = Apparent Power
POS
Positive Energy Only. Negative energy pulses on E1 are suppressed. However, negative P register results will NOT be suppressed.
AFC
Enables automatic line frequency measurement and sets the frequency of the local sine/cosine
generator used in fundamental/harmonic measurements. When AFC is enabled, the Epsilon
register will be updated periodically.
6.2.7 Epsilon (ε) Register
Address: 17
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0x01999A = 0.0125 sec
Epsilon (ε) is the ratio of the input line frequency to the sample frequency of the ADC (See Section 5.4 Performing Measurements on page 17). Epsilon is either written to the register, or measured during conversions. The
value is represented in two's complement notation and in the range of -1.0 ≤ ε < 1.0, with the binary point to the
right of the MSB. Negative values have no significance.
6.2.8 Tamper Threshold (Tamperlevel) Register
Address: 18
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 828F5C = 2%
Tamper Threshold (Tamperlevel) sets the level at which the two active powers, PActive or P2Active, can differ before a tamper condition is detected. When this threshold is reached the CS5464 will use the higher of the two
power calculation in the pulse out accumulation registers. The value is represented in two's complement notation and in the range of -1.0 ≤ Tamperlevel < 1.0, with the binary point to the right of the MSB.
6.2.9 Cycle Count Register
Address: 19
MSB
223
LSB
222
221
220
219
218
217
216
.....
26
25
24
23
22
21
20
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024∗N). A one second computational cycle period occurs when
MCLK = 4.096 MHz, K = 1, and N = 4000. The Cycle Count register must be ≥ 2.
36
DS682PP1
CS5464
6.2.10 Reactive Power (QTrig, Q2Trig) Registers
Address: 20 (QTrig), 21 (Q2Trig)
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
The Reactive Power (QTrig, Q2Trig) is calculated using trigonometric identities. (See Section 4.3 Power Measurements on page 15). The value is represented in unsigned notation and in the range of 0 ≤ QTrig < 1.0
(0 ≤ Q2Trig < 1.0), with the binary point to the right of the MSB.
6.2.11 Temperature Gain (TGain) Register
Address: 2
MSB
26
LSB
25
24
23
22
21
20
2-1
.....
2-11
2-12
2-13
2-14
2-15
2-16
2-17
Default = 0x34E2E7 = 26.443169117
Temperature gain (TGain) is utilized to convert from one temperature scale to another. The Celsius scale (oC) is
the default. Values will be within in the range of 0 ≤ TGain < 128. The value is represented in unsigned notation,
with the binary point to the right of bit 7th MSB.
6.2.12 Temperature Offset (Toff) Register
Address: 3
MSB
-(20)
LSB
2-1
2-2
2-3
2-4
2-5
2-6
2-7
.....
2-17
2-18
2-19
2-20
2-21
2-22
2-23
Default = 0xF38701 = -0.0974425
Temperature offset (Toff) is used to remove the temperature channel’s offset at the zero-degree reading. Values
are represented in two's complement notation and in the range of -1.0 ≤ Toff < 1.0, with the binary point to the
right of the MSB.
DS682PP1
37
CS5464
6.3 Page 2 Registers
6.3.1 Voltage Sag Duration (VSAGduration, V2SAGduration) Registers
Address: 0 (VSAGduration), 8 (V2SAGduration)
MSB
0
LSB
222
221
220
219
218
217
216
26
.....
25
24
23
22
21
20
Default = 0x000000
Voltage Sag Duration (VSAGduration, V2SAGduration) defines the number of instantaneous measurements utilized
to determine a sag event. Setting these register to zero will disable this feature. The value is represented in unsigned notation. See Section 5.6 Sag and Fault Detect Feature on page 20
6.3.2 Current Fault Duration (ISAGduration, I2SAGduration) Registers
Address: 4 (ISAGduration), 12 (I2SAGduration)
MSB
0
LSB
222
221
220
219
218
217
216
26
.....
25
24
23
22
21
20
Default = 0x000000
Current Fault Duration (ISAGduration, I2SAGduration) defines the number of instantaneous measurements utilized
to determine a sag event. Setting these register to zero will disable this feature. The value is represented in unsigned notation. See Section 5.6 Sag and Fault Detect Feature on page 20.
6.3.3 Voltage Sag Level (VSAGlevel, V2SAGLevel) Registers
Address: 1 (VSAGlevel), 9 (V2SAGlevel)
MSB
2-1
LSB
2-2
2-3
2-4
2-5
2-6
2-7
2-8
.....
2-18
2-19
2-20
2-21
2-22
2-23
2-24
Default = 0x000000
Voltage Sag Level (VSAGlevel), V2SAGlevel) defines the voltage level that the magnitude of input samples, averaged over the sag duration, must fall below in order to register a sag condition. These value are represented in
unsigned notation and in the range of 0 ≤ VSAGlevel < 1.0 (0 ≤ V2SAGlevel < 1.0), with the binary point to the left
of the MSB. See Section 5.6 Sag and Fault Detect Feature on page 20.
6.3.4 Current Fault Level (ISAGlevel, I2SAGlevel) Registers
Address: 5 (ISAGlevel), 13 (I2SAGlevel)
MSB
2-1
LSB
2-2
2-3
2-4
2-5
2-6
2-7
2-8
.....
2-18
2-19
2-20
2-21
2-22
2-23
2-24
Default = 0x000000
Current Fault Level (ISAGlevel, I2SAGlevel) defines the voltage level that the magnitude of input samples, averaged over the fault duration, must fall below in order to register a fault condition. These value are represented
in unsigned notation and in the range of 0 ≤ ISAGlevel < 1.0 (0 ≤ I2SAGlevel < 1.0), with the binary point to the left
of the MSB. See Section 5.6 Sag and Fault Detect Feature on page 20.
38
DS682PP1
CS5464
7. SYSTEM CALIBRATION
7.1 Channel Offset and Gain Calibration
The CS5464 provides digital DC offset and gain compensation that can be applied to the instantaneous voltage and current measurements, and AC offset
compensation to the voltage and current RMS calculations.
Since the voltage and current channels have independent offset and gain registers, system offset and/or
gain can be performed on either channel without the
calibration results from one channel affecting the other.
N + 30 conversion cycles to complete. For AC offset calibrations, the sequence takes at least 6N + 30 ADC cycles to complete, (about 6 computation cycles). As N is
increased, the accuracy of calibration results will increase.
7.1.2 Offset Calibration Sequence
For DC and AC offset calibrations, the VIN± (V2IN±)
pins of the voltage and IIN± (I2IN±) pins of the current
channels should be connected to their ground reference
level. (see Figure 14.)
The computational flow of the calibration sequences are
illustrated in Figure 13. The flow applies to both the voltage channel and current channel.
External
Connections
+
+
AIN+
0V +-
7.1.1 Calibration Sequence
The CS5464 must be operating in its active state and
ready to accept valid commands. Refer to 5.15 Commands on page 24. The calibration algorithms are dependent on the value N in the Cycle Count Register (see
Figure 13). Upon completion, the results of the calibration are available in their corresponding register. The
DRDY bit in the Status Register will be set. If the DRDY
bit is to be output on the INT pin, then DRDY bit in the
Mask Register must be set. The initial values in the AC
gain and offset registers do affect the results of the calibration results.
7.1.1.1 Duration of Calibration Sequence
The value of the Cycle Count Register (N) determines
the number of conversions performed by the CS5464
during a given calibration sequence. For DC offset and
gain calibrations, the calibration sequence takes at least
XGAIN
-
CM +-
AIN-
Figure 14. System Calibration of Offset
The AC offset registers must be set to the default
(0x000000).
7.1.2.1 DC Offset Calibration Sequence
Channel gain should be set to 1.0 when performing DC
offset calibration. Initiate a DC offset calibration. The DC
offset registers are updated with the negative of the average of the instantaneous samples collected over a
computational cycle. Upon completion of the DC offset
calibration the DC offset is stored in the corresponding
DC offset register. The DC offset value will be added to
Instantaneous
V, I, V2, I2
In
Modulator
Filter
+
X
X
+
DC Offset
Idcoff, Vdcoff,
I2dcoff, V2dcoff
Gain
Ign, Vgn,
I2gn, V2gn
Inverse
-1
Σ
N
+
÷ N
+
√
+
+
Σ
N
RMS
IRMS, VRMS,
I2RMS, V2RMS
Iacoff, Vacoff,
I2acoff, V2acoff
AC Offset
÷N
-1
X
X
0.6
RMS
= NAMES OF READABLE/WRITABLE REGISTERS.
Figure 13. Calibration Data Flow
DS682PP1
39
CS5464
each instantaneous measurement to nullify the DC
component present in the system during conversion
commands.
7.1.2.2 AC Offset Calibration Sequence
Corresponding offset registers Iacoff (I2acoff) and/or
Vacoff (V2acoff) should be cleared prior to initiating AC
offset calibrations. Initiate an AC offset calibration.The
AC offset registers are updated with an offset value that
reflects the RMS output level. Upon completion of the
AC offset calibration the AC offset is stored in the corresponding AC offset register. The AC offset register value is subtracted from each successive VRMS and IRMS
calculation.
measurement will be multiplied by its corresponding AC
gain value.
A typical rms calibration value which allows for reasonable over-range margin would be 0.6 or 60% of the voltage and current channel’s maximum input voltage level.
Two examples of AC gain calibration and the updated
digital output codes of the channel’s instantaneous data
registers are shown in Figure 16 and 17. Figure 17
Before AC Gain Calibration (Vgn Register = 1)
Sinewave
R eference
+
Signal
-
IN+
+
+
-
CM
+
-
For gain calibrations, there is an absolute limit on the
RMS voltage levels that are selected for the gain calibration input signals. The maximum value that the gain
registers can attain is 4. Therefore, if the signal level of
the applied input is low enough that it causes the
CS5464 to attempt to set either gain register higher than
4, the gain calibration result will be invalid and all
CS5464 results obtained while performing measurements will be invalid.
If the channel gain registers are initially set to a gain other than 1.0, AC gain calibration should be used.
7.1.3.1 AC Gain Calibration Sequence
The corresponding gain register should be set to 1.0,
unless a different initial gain value is desired. Initiate an
AC gain calibration. The AC gain calibration algorithm
computes the RMS value of the reference signal applied
to the channel inputs. The RMS register value is then divided into 0.6 and the quotient is stored in the corresponding
gain
register.
Each
instantaneous
40
-230 mV
-0.92
-250 mV
-1.0000...
250 mV
0.92231
230 mV
0.84853
INPUT
0V
SIGNAL
Instantaneous Voltage
Register Values
-230 mV
-0.84853
-250 mV
-0.92231
VRMS Register = 0.600000
-
Figure 15. System Calibration of Gain.
Instantaneous Voltage
Register Values
After AC Gain Calibration (Vgn Register changed to approx. 0.9223)
XG AIN
IN-
0.92
VRMS Register = 230/√2 x 1/250 ≈ 0.65054
Sinewave
External
Connections
0.9999...
230 mV
INPUT
0V
SIGNAL
7.1.3 Gain Calibration Sequence
When performing gain calibrations, a reference signal
should be applied to the VIN± (V2IN±) pins of the voltage and IIN± (I2IN±) pins of the current channels that
represents the desired maximum signal level. Figure 15
shows the basic setup for gain calibration.
250 mV
Figure 16. Example of AC Gain Calibration
Before AC Gain Calibration (Vgain Register = 1)
250 mV
0.9999...
230 mV
0.92
DC Signal
Instantaneous Voltage
Register Values
INPUT 0 V
SIGNAL
-1.0000...
-250 mV
230
VRMS Register = 250
= 0.92
After AC Gain Calibration (Vgain Register changed to approx. 0.65217)
250 mV
0.65217
230 mV
0.6000
DC Signal
INPUT
0V
SIGNAL
Instantaneous Voltage
Register Values
-0.65217
-250 mV
VRMS Register = 0.600000
Figure 17. Example of AC Gain Calibration
DS682PP1
CS5464
shows that a positive (or negative) DC-level signal can
be used even though an AC gain calibration is being executed.
However, an AC signal cannot be used for DC gain calibration.
7.1.3.2 DC Gain Calibration Sequence
Initiate a DC gain calibration. The corresponding gain
register is restored to default (1.0). The DC gain calibration averages the channel’s instantaneous measurements over one computation cycle (N samples). The
average is then divided into 1.0 and the quotient is
stored in the corresponding gain register
After the DC gain calibration, the instantaneous register
will read at full-scale whenever the DC level of the input
signal is equal to the level of the DC calibration signal
applied to the inputs during the DC gain calibration.The
HPF option should not be enabled if DC gain calibration
is utilized.
7.1.4 Order of Calibration Sequences
1. If the HPF option is enabled, any DC component that
may be present in the selected signal path will be removed and a DC offset calibration is not required.
However, if the HPF option is disabled the DC offset
calibration sequence should be performed.
When using high-pass filters, it is recommended that
the DC Offset register for the corresponding channel
be set to zero. When performing DC offset calibration, the corresponding gain channel should be set to
one.
2. If there is an AC offset in the VRMS or IRMS calculation, the AC offset calibration sequence should be
performed.
3. Perform the gain calibration sequence.
4. Finally, if an AC offset calibration was performed
(step 2), the AC offset may need to be adjusted to
compensate for the change in gain (step 3). This can
be accomplished by restoring zero to the AC offset
register and then perform an AC offset calibration sequence. The adjustment could also be done by
DS682PP1
multiplying the AC offset register value that was calculated in step 2 by the gain calculated in step 3 and
updating the AC offset register with the product.
7.2 Phase Compensation
The CS5464 is equipped with phase compensation to
cancel out phase shifts introduced by the measurement
element. Phase Compensation is set by bits PC[7:0] (for
channel 1) in the Configuration Register and bits
PC2[7:0] (for channel 2) in the Control Register
The default value of PC[7:0] (PC2[7:0]) is zero. With
MCLK = 4.096 MHz and K = 1, the phase compensation has a range of ±5.4 degrees when the input signals
are 60 Hz. Under these conditions, each step of the
phase compensation register (value of one LSB) is approximately 0.04 degrees. For values of MCLK other
than 4.096 MHz, the range and step size should be
scaled by 4.096 MHz/(MCLK/K). For power line frequencies other than 60Hz, the values of the range and
step size of the PC[7:0] (PC2[7:0]) bits can be determined by converting the above values from angular
measurement into the time domain (seconds), and then
computing the new range and step size (in degrees)
with respect to the new line frequency. To calculate the
phase shift induced between the voltage and the current
channel use the equation:
Phase
o
Freq × 360 × PC [ 7:0 ]
= --------------------------------------------------( MCLK ⁄ K ) ⁄ 8
Freq = Line Frequency [Hz]
PC[7:0] = 2’s Compliment number in the range of -128 < PC[7:0} < 127
7.3 Active Power Offset
The Power Offset Register can be used to offset system
power sources that may be resident in the system, but
do not originate from the power line signal. These sources of extra energy in the system contribute undesirable
and false offsets to the power and energy measurement
results. After determining the amount of stray power, the
Power Offset Register can be set to cancel the effects
of this unwanted energy.
41
CS5464
8. AUTO-BOOT MODE USING E2PROM
When the CS5464 MODE pin is asserted (logic 1), the
CS5464 auto-boot mode is enabled. In auto-boot mode,
the CS5464 downloads the required commands and
register data from an external serial E2PROM, allowing
the CS5464 to begin performing energy measurements.
8.2 Auto-boot Data for E2PROM
Below is an example code set for an auto-boot sequence. This code is written into the E2PROM by the user. The serial data for such a sequence is shown below
in single-byte hexidecimal notation:
8.1 Auto-boot Configuration
-7E 00 00 01
Change to page 1.
-60 00 01 E0
Write Operation Mode Register, turn high-pass
filters on.
-42 7F C4 A9
Write value of 0x7FC4A9 to Current Gain
Register.
-46 FF B2 53
Write value of 0xFFB253 to Voltage Gain
Register.
-50 7F C4 A9
Write value of 0x7FC4A9 to Current 2 Gain
Register.
-54 FF B2 53
Write value of 0xFFB253 to Voltage 2 Gain
Register.
-7E 00 00 00
Change to page 0.
-74 00 00 04
Unmask bit #2 (LSD) in the Mask Register.
-E8
Start continuous conversions
-78 00 01 00
Write STOP bit to Control Register, to terminate
auto-boot initialization sequence.
A typical auto-boot serial connection between the
CS5464 and a E2PROM is illustrated in Figure 18. In auto-boot mode, the CS5464’s CS and SCLK are configured as outputs. The CS5464 asserts CS (logic 0),
provides a clock on SCLK, and sends a read command
to the E2PROM on SDO. The CS5464 reads the user-specified commands and register data presented on
the SDI pin. The E2PROM’s programmed data is utilized
by the CS5464 to change the designated registers’ default values and begin registering energy.
VD+
E1
E2
5K
Pulse Output
Counter
EEPROM
CS5464
SCK
SCLK
MODE
SDI
SO
SDO
SI
5K
CS
CS
Connector to Calibrator
Figure 18. Typical Interface of E2PROM to CS5464
Figure 18 also shows the external connections that
would be made to a calibrator device, such as a PC or
custom calibration board. When the metering system is
installed, the calibrator would be used to control calibration and/or to program user-specified commands and
calibration values into the E2PROM. The user-specified
commands/data will determine the CS5464’s exact operation, when the auto-boot initialization sequence is
running. Any of the valid commands can be used.
42
8.3 Which E2PROMs Can Be Used?
Several industry-standard serial E2PROMs that will successfully run auto-boot with the CS5461A are listed below:
•
•
•
Atmel AT25010, AT25020 or AT25040
National Semiconductor NM25C040M8 or NM25020M8
Xicor X25040SI
These types of serial E2PROMs expect a specific 8-bit
command (00000011) in order to perform a memory
read. The CS5461A has been hardware programmed to
transmit this 8-bit command to the E2PROM at the beginning of the auto-boot sequence.
DS682PP1
CS5464
9. BASIC APPLICATION CIRCUITS
Figure 19 shows the CS5464 configured to measure
power in a single-phase, 2-wire system while operating
in a single-supply configuration. In this diagram, a shunt
resistor is used to sense the line current and a voltage
divider is used to sense the line voltage. In this type of
shunt-resistor configuration, the common-mode level of
the CS5464 must be referenced to the line side of the
power line. This means that the common-mode potential of the CS5464 will track the high-voltage levels, as
well as low-voltage levels, with respect to earth ground.
Isolation circuitry is required when an earth-ground-referenced communication interface is connected. A current transformer, or CT, is connected to the return line
current, which implements the tamper detection circuit.
10 kΩ
5 kΩ
L2
LINE
VOLTAGE
L1
500 Ω
10 Ω
500
470 µF
470 nF
0.1 µF
0.1 µF
3
VD+
18
VA+
CS5464
9
CVCVdiff
R1
10
19
VIN-
RESET
C Idiff
R Shunt
C I+
R I+
20
R I-
15
1kΩ
IIN+
IIN2-
C Idiff
RBurden
1kΩ
XIN
16
23
7
CS
27
SDI
6
SDO
5
SCLK
24
INT
26
E2
25
E1
12
VREFIN
11
VREFOUT
Note:
Serial
Data
Interface
Pulse Output
Counter
IIN2+
RI+
LOAD
Optional
Clock
Source
28
IIN-
C I-
R I-
CT
4.096 MHz
CV+
R V-
ISOLATION
R2
VIN+
21
PFMON
2
CPUCLK
1
XOUT
13
TEST1
14
TEST2
0.1 µF
Indicates common (floating) return.
AGND
17
DGND
4
Figure 19. Typical Connection Diagram (Single-phase, 2-wire – Direct Connect to Power Line)
DS682PP1
43
CS5464
10.PACKAGE DIMENSIONS
28L SSOP PACKAGE DRAWING
N
D
E11
A2
E
e
b2
SIDE VIEW
A
∝
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.064
0.009
0.390
0.291
0.197
0.022
0.025
0°
INCHES
NOM
-0.006
0.069
-0.4015
0.307
0.209
0.026
0.0354
4°
MAX
0.084
0.010
0.074
0.015
0.413
0.323
0.220
0.030
0.041
8°
MIN
-0.05
1.62
0.22
9.90
7.40
5.00
0.55
0.63
0°
MILLIMETERS
NOM
-0.15
1.75
-10.20
7.80
5.30
0.65
0.90
4°
NOTE
MAX
2.13
0.25
1.88
0.38
10.50
8.20
5.60
0.75
1.03
8°
2,3
1
1
JEDEC #: MO-150
Controlling Dimension is Millimeters
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch
and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in
excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more
than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
2.
44
DS682PP1
CS5464
11. ORDERING INFORMATION
Model
CS5464-IS
CS5464-ISZ (lead free)
Temperature
Package
-40 to +85 °C
24-pin SSOP
12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS5464-IS
240 °C
2
365 Days
CS5464-ISZ (lead free)
260 °C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS682PP1
45
CS5464
13. REVISION HISTORY
Revision
Date
Changes
T1
NOV 2005
Target Data Sheet
PP1
MAR 2006
Preliminary Release
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available.
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
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