BL6523B
FEATURES
Single 5V supply, 25mW（typical）
Interralated patents are pending
High accuracy, less than 0.1% error over a
DESCRIPTION
dynamic range of 3000:1
The BL6523B is a low cost, high accuracy, high
High stability, less than 0.1% error in the output
stability, electrical energy measurement IC intended
frequency fluctuation
to single phase, multifucion applications.
Measure the active power in the positive
Single Phase, Multifunction Energy meter IC
The BL6523B incorporates three high accuracy
orientation and negative orientation, transform to
Sigma-Delta
fast pulse output(CF）
management and digital signal processing circuit
Provide two current input for line and neutral
using to calculates active energy, apparent energy,
current measurement
IRMS, VRMS etc.
Mesure instantaneous IRMS and VRMS over a
ADC,
voltage
reference,
The BL6523B have two current input
power
for line
dynamic range of 1500:1
and neutral current measurement, when these currents
Provide SAG detection and Phase failure
differ by more than the programmable Fault
detection
threshold value(RMS or WATT), the BL6523B give
On-chip power supply detector
the tamper indicator and can enable neutral current
On-chip
anti-creep
protection
with
the
billing,
programmable threshold set
The BL6523B measures line voltage, current and
Provide the pulse output with programmable
calculates active, apparent energy, power factor, line
frequency adjustment
frequency, detect sag, overvoltage, overcurrent, peak,
Provide the programmable gain adjustment and
reverse power, zero-crossing voltage.
phase compensation
The BL6523B provides access to on-chip meter
Measure the power factor (PF）
Provide a programmable interrupt request signal
registers via SPI communication interface.
The BL6523B provide all-digital domain offset
（/IRQ）
compensation, gain adjustment, phase compensation
Provide a SPI communication interface
(maximum ±2.54°adjustable）.
On-chip voltage reference of 2.5V
With 3.58MHz external crystal oscillator
BLOCK DIAGRAM
AVDD
1
24
DVDD
IAP
2
23
/RST
IAN
3
22
CF
4
21
DIN
5
20
DOUT
VP
6
19
SCLK
VN
7
VREF
8
AGND
9
BL6523B
IBP
IBN
18
/CS
15
/IRQ
14
AT3
AT1
12
13
AT2
Power detector
Clock
IBP
IBN
PGA
ADC
CLKIN
11
Voltage Ref
ADC
16
10
CLKOUT
CLKIN
PGA
CLKOUT
AT0
AVDD DVDD
IAP
IAN
17
DGND
VREF
VP
VN
A_WATT,B_WATT,VA
WattHR/VAHR
/CS
Fault detector
CF
AT3
AT2
AT1
AT0
PF
Sag detector
Interrupt detector
BL6523B
SSOP24
AGND
SPI
Peak detector
ADC
/RST
/IRQ
DIN
DOUT
SCLK
Irms,Vrms
DSP
PGA
interrupt
Logic
output
DGND
PIN DESCRIPTIONS（SSOP24）
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v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
Pin
Symbol
DESCRIPTIONS
1
AVDD
Power Supply (+5V). Provides the supply voltage for the circuitry. It
should be maintained at 5 V±5% for specified operation.
2，3，
4，5
IAP，IAN，
IBP，IBN
Analog input for current channel, These inputs are fully differential
voltage inputs with a maximum signal level of ±660 mV, Adjustable
Gain.
6，7
VP，VN
Negative and Positive Inputs for Voltage Channel. These inputs provide a
fully differential input pair. The maximum differential input voltage is ±
750 mV for specified operation.Adjustable Gain.
8
VREF
On-Chip Voltage Reference. The on-chip reference has a nominal value of
2.5V ± 8% and a typical temperature coefficient of 30ppm/℃. An
external reference source may also be connected at this pin.
9
AGND
Ground Reference. Provides the ground reference for the circuitry.
10
DGND
Digital Ground
11，12， AT0，AT1，
13，14
AT2，AT3
Programmable digital output. See AT_SEL register section. Default
output:AT0=FAULT、AT1=REVP、AT2=ZX、AT3=nSAG。
15
/IRQ
16
CLKIN
Clock In. An external clock can be provided at this logic input,
Alterrnatively, a crystal (3.58MHz) can be connected across this pin and
pin17 to provide a clock source.
17
CLKOUT
Clock out. A crystal can be connected across this pin and Pin16 as
described above to provide a clock source.
18
/CS
Chip select for SPI interface. This pin must be pulled low if using the
SPIinterface.
19
SCLK
Serial clock input for the synchronous serial interface. All serial
communication data are synchronized to the clock.
20
DOUT
Data output for SPI interface. Data is shifted out at this pin on the rising
edge of SCLK. This output is normally in a high impedance state, unless
it is driving data out to the serial data bus.
21
DIN
Data input for SPI interface. Data is shifted in at this pin on the rising
edge of SCLK
22
CF
Calibration Frequency. The CF logic output gives instantaneous real
power information. This output is intended to use for calibration purposes.
The full-scale output frequency can be scaled by the value of WA_CFDIV
register. When the power is low, the pulse width is equal to 90ms. When
the power is high and the output period less than 180ms, the pulse width
equals to half of the output period.
23
/RST
24
Interrupt output.
Reset Pin. Logic low on this pin will hold the ADCS and digital circuitry
in a reset condition and clear internal registers.
DVDD DiDigital Power Supply（+5V）,provides the supply voltage for the digital
circuitry. It should be maintained at +4.75V~+5.25V for specified
operation
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BL6523B
Package Dimensions
ABSOLUTE MAXIMUM RATIONS
Single Phase, Multifunction Energy meter IC
（T = 25 ℃）
Parameter
Symbol
Value
单位
Power Voltage AVDD、DVDD
AVDD、DVDD
-0.3 ~ +7
V
Analog Input Voltage to AGND
IAP、IBP、VP
-6 ~ +6
V
Digital Input Voltage to DGND
DIN、SCLK、/CS
-0.3 ~ VDD+0.3
V
Digital Output Voltage to DGND
CF、AT0、AT1、AT2、AT3
/IRQ、DOUT
-0.3 ~ VDD+0.3
V
Operating Temperature Range
Topr
-40 ~ +85
℃
Storage Temperature Range
Tstr
-55 ~ +150
℃
Power Dissipation（SSOP24）
P
80
mW
Electronic Characteristic Patameter
（AVDD = DVDD = 5V, AGND＝DGND＝0V, CLKIN=3.58MHz, T=25℃）
Parameter
Measure Error on
Active Power
Symbol
Test Condition
Measure
Pin
Min
Value
Typical
Value
Max
Value
Unit
0.1
0.3
%
WATTerr
Over a dynamic
range 3000:1
PF08err
Current lead
37°
（PF=0.8）
0.5
%
Phase error when
PF=0.5Inductive
PF05err
Current lags
60°
（PF=0.5）
0.5
%
AC PSRR
ACPSRR
IP/N=100mV
Phase error when
PF=0.8 Capacitive
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CF
0.01
%
v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
DC PSRR
DCPSRR
VP/N=100mV
0.1
%
Vrms measurement
Error
VRMSerr
1500:1 input DR
0.3
%
Irms measurement
Error
IRMSerr
1500:1 input DR
0.3
%
±
1200
Maximum Input
voltage
DC Input Voltage
370
mV
kΩ
Input Signal
Bandwidth
（-3dB）
Gain Error
External 2.5V
reference
-4
+4
%
Gain Error match
External 2.5V
reference
-1.5
+1.5
%
On-chip reference
Vref
Reference Error
Vreferr
Temperature
Coefficient
TempCoef
14
VREF
kHz
2.5
V
±
200
mV
30
Input High Voltage
DVDD=5V±
5%
Input Low Voltage
DVDD=5V±
5%
Output High
Voltage
DVDD=5V±
5%
Output Low
Voltage
DVDD=5V±
5%
ppm/℃
2.6
V
0.8
V
4
V
1
V
Analog Power
AVDD
VAVDD
4.75
5.25
V
Digital Power
DVDD
VDVDD
4.75
5.25
V
AIDD
IAVDD
AVDD=5.25V
3
mA
DIDD
IDVDD
DVDD=5.25
2
mA
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v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
THEORY OF OPERATION
BL6523B System Block
IA_WAVE
IAP
IAN
LNA
ADC
GAIN[3:0]
VP
VN
LNA
ADC
LNA
SINC4
Phase
SINC4
GAIN[7:4]
Phase
x²
SINC4
LPF
x²
root
x²
+
LPF
+
WA_LOS_L
+
×
root
ANTICREEP
×
LPF
ANTICREEP
IB_PEAK
IA_RMS
ANTICREEP
root
×
IB_RMS
ANTICREEP
V_RMS
V_RMSGN RMS_CREEP
WATTHR
A_WATTGN
ʃ(P+N
)
A_WATT
×
PEAK
IB_RMSGN RMS_CREEP
V_RMSOS
IA_WAVE
×
IB_WAVE
IA_RMSGN RMS_CREEP
IB_RMSOS
V_WAVE
V_CHOS
V_PEAK
IB_CHGN IB_CHOS
+
LPF
V_CHGN
HPF
IA_RMSOS
IB_WAVE
+
IA_PEAK
V_WAVE
PEAK
×
HPF
IB_PHCAL
IA_WAVE
PEAK
+
IA_CHGN IA_CHOS
V_PHCAL
ADC
×
HPF
IA_PHCAL
GAIN[11:8]
IBP
IBN
Phase
×
+
÷
ʃP
V_WAVE
WA_REVP
WA_CREEP
A_WATTOS
PWAHR
B_WATTOS
×
LPF
ANTICREEP
×
ʃN
WA_LOS_H
WA_CFDIV
NWAHR
+
ʃT(P+N
)
B_WATT
IB_WAVE
LINE_WATTHR
B_WATTGN
LINECYC
IA_RMS
IA_RMS
COMP
÷
PF
IB_RMS
×
IB_RMS
×
+
VAGN
VAOS
ʃ
VAHR
FAULT
A_WATT
V_RMS
VA
COMP
B_WATT
Principle of Energy Measure
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CF
v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
In energy measure, the power information varying with time is calculated by a direct
multiplication of the voltage signal and the current signal. Assume that the current signal and the
voltage signal are cosine functions, V,I are the peak values of the voltage signal and the current
signal; the phase difference between the current signal and the voltage signal is expressed as
Ф,Then the power is given as follows:
p (t ) V cos(wt ) I cos(wt )
If =0 时：
p (t )
If 0 时：
VI
(1 c o s2(wt )
2
p (t ) V cos(wt ) I cos(wt )
V cos(wt ) I cos(wt ) cos( ) sin( wt ) sin( )
VI
(1 cos(2 wt )) cos( ) VI cos(wt ) sin( wt ) sin( )
2
VI
VI
(1 cos(2 wt )) cos( ) sin( 2 wt ) sin( )
2
2
p(t) is called as the instantaneous power signal. The ideal p(t) consists of the DC component and
AC component whose frequency is 2ω. The DC component is called as the average active power.
The current signal and voltage signal is converted to digital signals by high-precsion ADCS,
then through the drop sampling filter (SINC4), high-pass filter (HPF) filter out the high frequency
noise and DC gain, get the required current and voltage sampling data.
Current sampling data multiplied by voltage sampling data gets instantaneous active power,
then through the low pass filter (LPF), output average active power.
Current sampling data and voltage sampling data processed by square circuit, low-pass
filter( LPF1), square root circuit, get the current RMS and voltage RMS.
Active power through a certain time integral, get active energy.
Front-end gain adjustment
Every analog channel has a programmable gain amplifier (PGA), gain selection is achieved
by the gain register (GAIN), the default value of the gain register (GAIN) is 000H.
Every 4-bit of the gain register used to select the current channel or voltage channel PGA.
Gain[3:0] used to select Current A channel PGA,Gain[7:4] used to select Current B channel PGA,
Gain[11:8] used to select Voltage channel PGA.
For example Gain [3:0]:
x000=1x
x001=2x
x010=4x
x011=8x
x100=16x
x101=24x
x110=32x
x111=32x
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BL6523B
Single Phase, Multifunction Energy meter IC
Phase compensation
BL6523B provides the method of small phase error digital calibration. It will be a small time
delay or advance into signal processing circuit in order to compensate for small phase error.
Because this compensation should be promptly, so this method applies only to 0.1~0.5 range of
small phase error.
Phase calibration register(IA_PHCAL、IB_PHCAL、V_PHCAL) is a binary 8-bit register,
corresponding to the compensation current A channel, current B channel and voltage channel
phase. The default value is 00H. Bit[7] is enable bit, when Bit[7]＝0,disable compensation;Bit[7]
＝1,enable compensation. Bit[6:0] used to adjust the delay time，1.1us/1LSB. With a line
frequency of 50Hz, the resolution is 360（1/900KHz）50Hz=0.02, The adjustable range is
0~2.54.
Input channle offset calibration
BL6523B contains the input channel offset calibration registers (IA_CHOS, IB_CHOS,
V_CHOS), these registers are in 12-bit sign magnitude format, the default value is 000H. The
offset may result from the analog input and the analog-digital conversion circuit itself.
Active power offset calibration
BL6523B contains the active power offset calibration (A_WATTOS,B_WATTOS). Both
registers are in 12-bit sign magnitude format, the default value is 000H. The offset can exist in the
power calculations due to crosstalk between channels on the PCB and in the BL6523B. The active
power offset calibration allows these offsets to be removed to increase the accuracy of the
measurement at low input power levels.
ActivePowe r ActivePowe r0 X _ WATTOS
Active power gain adjustment
The gain registers (A_WATTGN, B_WATTGN) are used to adjust the active power
measurement range. Both registers are in 12-bit sign magnitude format, the default value is 000H.
The following formula shows how to adjust the output active power:
Output ActivePowe r Active Power (1
X _ WATTWG
)
212
The minimum value that can be write to the X_WATTGN register is 801H(HEX), which
represents a gain adjustmen of -50%. The maximum value that can be write to the X_WATTGN
register is 7FFH (HEX), which represents a gain adjustmen of +50%.
Similar gain calibration regisets are available for current channel A, current channel B and
voltage channel (IA_CHGN, IB_CHGN, V_CHGN).
No-load threshold of active power
BL6523B contains two no-load detection feature that eliminates meter creep. BL6523B can
set the no-load threshold on the active power (WA_CREEP), this register is in 24-bit unsign
magnitude format. The low 12-bit(WA_CREEP_L) is used to set the active power threshold value,
When the absolute value of the input power signal is less than this threshold, the output active
power is set to zero. This can make the active power register to 0 in no-load conditions, even a
small noise signal input .
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BL6523B
Single Phase, Multifunction Energy meter IC
0 , | WATT | WA _ CREEP _ L
WATT
WATT , | WATT | WA _ CREEP _ L
The high 12-bit of WA_CREEP register(WA_CREEP_H) is used to set the active power timer threshold value.
The default value is 0xFFF.
There have a internal TIME_CREEP register in BL6523B, when detect the CF pulse
output , the TIME_CREEP register is set to the value of WA_CREEP_H. If not detected the CF pulse output, the
TIME_CREEP register value decrease. If the TIME_CREEP register decrease to 0, there is still no CF
signal output, the BL6523B produce a reset signal used to reset the internal energy accumulated
register of CF pulse and reload the value of WA_CREEP_H to the TOME_CREEP register. The
resolution of the WA_CREEP_H is 4.6s / LSB, so the maxium timing anti-creep time is about
5h13m.
MODE[6]=1 enable timing anti-creep function.
MODE[6]=0 disable timing anti-creep function.
Active power compensation of small signal
BL6523B contains a small active power signal compensation register (WA_LOS), this
register is in 12-bit sign magnitude format. The default value is 000H。
Reverse indicator threshold
BL6523B contains a reverse indicator threshold register(WA_REVP), this register is in 12-bit
unsigned magnitude format, When the input power signal is negative and the absolute value is
greater than the power threshold，the BL6523B output the REVP indicator.
Active energy calculation
The relationship between power and energy can be expressed as：
Power
dEnergy
dt
Conversely, energy is given as the integral of power.
Energy Power dt
In BL6523B, the active power signals are accumulated in a 53 internal registers continuously
to get active energy, Active energy register WATTHR [23:0] take out this internal register[52:29]
as active energy output. This discrete time accumulation is equivalent to integration in continuous
time.
E p(t )dt LimT 0 { P(nT ) T }
n 0
Where:
n is the discrete time-sample number; T is the sampling period; the sampling period of
BL6523B is 1.1us.
The BL6523B include a interrupt (APEHF) that is triggered When the active energy
register(WATTHR) is half full. If the enable APEHF bit in the interrupt mask register set to logic
high, the / IRQ output Pin goes logic low.
The BL6523B include line cycle energy register(LINE_WATTHR). The number of cycles is
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BL6523B
Single Phase, Multifunction Energy meter IC
writen to the LINECYC register, the LSB of the LINECYC register is 0.1S. At the end of a line
cycle accumulation cycle, the LINE_WATTHR regiseter is updated. The LINE_WATTHR register
hold its current value until the end of the next line cycle period, when the content is replaced with
the new reading. If a new value is written to the LINECYC register midway through a line cycle
accumulation, the new value is not internally loaded until the end of a line cycle period.
Frequency output
The BL6523B provides a energy-to-frequency conversion for calibration purpose. After
initial calibration at manufacturing, the manufacturer or end customer is often required to verify
the meter accuracy. One convenient way to do this is to provide an output frequency that is
proportional to the active power. This output frequency provides a simple sigle-wire interface that
can be optically isolated to interface to external calibration equipment.
BL6523B includes a programmable calibration frequency output PIN (CF). The
digital-to-frequency converter is used to generate the pulse output. The pulse output (CF) stay high
for 90ms if the pulse period is longer than 180ms. If the pulse period is shorter than 180ms, the
duty cycle of de pulse output is 50%. The maximum output frequency with ac inputs at full scale
and with WA_CFDIV=100H is approximately 0.5 kHz.
The BL6523B can set the CF frequency through the WA_CF_DIV register . The default value
－
of the WA_CFDIV register is 001H (HEX). When set WA_CFDIV[x]=1, the CF frequency is 2(x
4)
*CFWA_CFDIV=010H.
Root mean square measurement
The rms is expressed mathematically as:
T
1
V 2 (t )dt
T 0
Vrms
For time-sampled signals:
1
N
Vrms
N
V
2
(i )
i 1
rms offset calibration
BL6523B contains the rms offset calibration (IA_RMSOS, IB_RMSOS, V_RMSOS). These
registers are in 12-bit sign magnitude format, the default value is 000H. The offset can exist in the
rms calculations due to input noise that is intergrated in the dc component of square calculation.
The rms offset calibration allows these offsets to be removed to increase the accuracy of the
measurement at low input power levels.
I ARMS I ARMS 0 IX _ RMSOS 217
2
rms gain calibration
The gain registers (IA_RMSGN, IB_RMSGN, V_RMSGN) are used to adjust the rms
measurement range. Both registers are in 12-bit sign magnitude format, the default value is 000H.
The following formula shows how to adjust the rms:
Output rms rms (1
X _ RMSGN
)
212
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v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
The minimum value that can be write to the X_RMSGN register is 801H(HEX), which
represents a gain adjustmen of -50%. The maximum value that can be write to the
X_RMSGN register is 7FFH (HEX), which represents a gain adjustmen of +50%.No-load
threshold of RMS
BL6523B can set the no-load threshold on the RMS_CREEP register, this register is in 12-bit
unsign magnitude format. When the value of the RMS register is less than this threshold, the RMS
register is set to zero. This can make the RMSregister to 0 in no-load conditions, even a small
noise signal input .
| RMS | RMS _ CREEP 2 1.3655
0
RMS
RMS , | RMS | RMS _ CREEP 2 1.3655
Apparent Power and Apparent Energy Calculation
In BL6523B, the apparent power is defined as the product of V_RMS and IX_RMS.
VA＝IX_RMS×V_RMS
The apparent energy is given as the intergral of the apparent power. The apparent power
signals are accumulated in an internal 49-bit register, apparent energy register VAHR [23:0] take
out this internal register [48:25] as apparent energy output. The BL6523B include a interrupt
(VAPEHF) that is triggered When the apparent energy register(VAHR) is half full. If the enable
VAPEHF bit in the interrupt mask register set to logic high, the / IRQ output Pin goes logic low.
Power Factor
PF＝ (WATT/VA)
PF register is in 24-bit sign magnitude format. Power factor =(sign bit)*((PF[22]×2^－1）＋
（PF[21]×2^－2）＋。
。
。), the register value of 0x7FFFFF(HEX) corresponds to a power factor
value of 1, the register value of 0x800000(HEX) corresponds to a power factor of -1, the register
value of 0x400000(HEX) corresponds to a power factor of 0.5.
Operation Mode Select
Metering channel selection
The default metering channel of BL6523B is channel A. the MODE[0] of MODE register is
used to select the metering channel.
MODE[0]=0, the metering channel is channel A;
MODE[0]=1, the metering channel is channel B;
MODE[1]=0; disable auto channel select;
MODE[1]=1; enable auto channel select; when the chip detect the imbalance of two current
channel, the chip select the bigger current channel as the metering channel.
High-pass filter selection
In the analog-digital conversion circuit, the current and voltage channels have high-pass
filters to eliminate the DC offset. The MODE[4:2] of MODE register is used to select high-pass
filter.
MODE[2]=0, enable the high-pass filter of current channel A;
MODE[2]=1,disable the high-pass filter of current channel A;
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BL6523B
Single Phase, Multifunction Energy meter IC
MODE[3]=0, enable the high-pass filter of current channel B;
MODE[3]=1,disable the high-pass filter of current channel B;
MODE[4]=0, enable the high-pass filter of voltage channel;
MODE[4]=1,disable the high-pass filter of voltage channel;
MODE[7]=1
When BL6523B measure AC signal, MODE[7] must be set to 1.
Energy accumulation mode selection
The MODE[9:8] of the MODE regiset is used to select energy accumulation mode.
MODE[9:8]=00, absolute energy accumulation;
MODE[9:8]=01, positive-only energy accumulation;
MODE[9:8]=10, arithmetical energy accumulation;
MODE[9:8]=11, negative-only energy accumulation;;
The current imbalance judgment
The BL6523B contains the detection of current imbalance. MODE[11:10] of the MODE
register is used to set the current rms imbalance threshold. When the Line current rms and neutral
current rms difference exceeds the threshold, the BL6523B give the FAULT indicator.
MODE[11]
MODE[10]
Threshold
0
0
12.5%(default)
0
1
6.25%
1
0
3.125%
1
1
10.1%
Electric parameters monitor
Power Supply Monitor
The BL6523B contains an on-chip power supply monitor. The analog supply (AVDD) is
continuously monitored by the BL6523B. if the supply is less than 4V±5%, the BL6523B will be
reset. This is useful to ensure correct device startup at power-up and power-down. The power
supply monitor has built in hysteresis and filtering. This gives a high degree of immunity to false
triggering due to noisy supplies. The power supply and decoupling for the part should be such that
the ripple at AVDD does not exceed 5V5% as specified for normal operation.
Zero-Crossing Detection
The BL6523B includes a zero-crossing detection on voltage channel. The ZX output pin
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BL6523B
Single Phase, Multifunction Energy meter IC
goeshigh on positive-going edge of the voltage channel zero crossing.
Zero-Crossing Timeout
The BL6523B includes a zero-crossing timeout feature that is designed to detect when no
zero crossings are obtained over a programmable time period. The duration of the zero-crossing
timeout is programmed in the 16-bit ZXTOUT register. The value in the ZXTOUT register is
decremented by 1LSB ervery 70.5us. if a zero-crossing is obtained, the ZXTOUT register is
reloaded. If the ZXTOUT register reaches 0, a zero-crossing timeout event is issued. The
maximum programmable timeout period is 4.369 secs. A interrupt is associated with the
zero-crossing timeout feature. If enabled, a zero-crossing timeout event causes the external IRQ
pin to go low.
Voltage Sag Detection
The BL6523B includes a sag detection features that warns the user when the absolute value
of the line voltage falls below the programmable threshold for a programmable number of half line
cycles. The voltage sag feature is controlled by two registers: SAGLVL and SAGCYC. These
registers control the sag voltage threshold and the sag period, respectively.
The 12-bit SAGLVL register contains the amplitude that the voltage channel must fall
belowbefore a sg event occurs.The sag threshold is the number of half line cycles below which
the voltage channel must remain before a a sag condition occurs. Each LSB of the SAGCYC
register corresponds to one half line cycle period. The default value is 0xFF(HEX). At 50Hz,
the maximum sag cycle time is 2.55 seconds.
Peak Detection
The BL6523B continuously records the maximum value of the current and voltage channels.
The three registers that record the peak values on current channel A, current channel B, and the
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BL6523B
Single Phase, Multifunction Energy meter IC
voltage channel, respectively, are IAPEAK, IBPEAK, VPEAK.
Peak monitor
The BL6523B include an overcurrent and overvoltage feature that detects whether the
absolute value of the current or voltage waveform exceeds a programmable threshold. Three peak
threshold register (IA_PKLVL, IB_PKLVL, V_PKLVL) are used to set the current or voltage
channel peak threshold, respectively.
If the BL6523B detects an overvoltage condition, the PKV bit of the interrupt status register
is set to 1. If the PKV bit of the interrupt mask register is enable, the IRQ output go low. The
overcurrent detection feature works in the similar manner.
Interrupt
The BL6523B use interrupt status register and interrupt mask register to manage interrupts.
When an interrupt event occurs, the corresponding bit in the STATUS register is set to 1. If the
enable bit for this interrupt, located in the MAK register is set to 0, the external IRQ pin is pulled
to logic 0. The status bit located in the STATUS register is set when an interrupt event occurs,
regardless of whether the external interrupt is enabled.
All interrupts are latched and require servicing to clear. To service the interrupt and return the
IRQ pin to logic 1, the status bits must be cleared using the STATUS register. After completion of
a read from the STATUS register, the IRQ pin returns to logic 1.the status bit can’t be cleared after
a read operation of STAUTS register, but can be writen 0 to the corresponding bit in the status
register through the SPI interface clearing the status bit.
SPI interface
The SPI communication packet consists of an initial byte, The Bit [7:6] of this byte dictates
whether a read or a write is being issued. The Bit [7:6] of this byte should be set to 00 for a read
operation and to 01 for a write operation. The Bit [5:0] of this byte is the address of the register
that is to be read from or written to. This byte should be transmitted MSB first. When this initial
byte transmission is complete, the register data is either sent from the BL6523B on the DOUT pin
(in the case of a read) or is written to the BL6523B DIN Pin by the external microcontroller (in the
case of a write). All data is sent or received MSB first. The lenth of the data transfer is 24 bits
long.
The serial peripheral interface of BL6523B uses four communication pins: SCLK, DIN,
DOUT and /CS. The SPI communication operates in slave mode, a clock must be provided on the
SCLK pin. This clock synchronizs all communication. The DIN pin is an input to the BL6523B;
data is sampled by BL6523B on the rising edge of SCLK. The DOUT pin is an output from the
BL6523B; data is shifted out on the rising edge of SCLK. The /CS (chip select) input must be
driven low to initialize the communication and driven high at the end of the communication.
Driving the /CS input high before the completion of a data transfer ends the communication.
SPI Write operation
Serial write sequence is shown in the figure. The Bit[7:6] of the first bytes in DIN is 01,
indicate a write operation. The Bit[5:0] of this byte indicate the address of register. The last three
bytes is the data that will be writed to the register. The data written to the BL6523B should be
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v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
ready before the rising edge of SLCK. The SPI interface will shift the data in the BL6523B on the
rising edge of SCLK.
/CS
t1
t2
t3
t7
t8
SCLK
t5
t4
t6
DIN
A5
A4
A3 A2 A1 A0
D7
命令字节
D6
D5
D4
D0
D7 D6 D5
数据高字节
D0
数据低字节
（DVDD＝5V± 5％，DGND＝0V，CLKIN＝3.58MHz XTAL，25℃）
min
type
max
unit
t1
/CS to the rising edge of SCLK
5000
ns
t2
The high pulse width of SCLK
5000
ns
t3
The low pulse width of SCLK
5000
ns
t4
Data setup time before the rising edge of SCLK
3000
ns
t5
Data hold time after the rising edge of SCLK
2000
ns
t6
Transmission time between two bytes
80
us
t7
The shortest interval between two bytes of data
5000
ns
t8
The shortet /CS hold time after the falling edge
of SCLK
5000
ns
SPI read operation
Serial write sequence is shown in the figure. The Bit[7:6] of the first bytes in DIN is 00,
indicate a read operation. The Bit[5:0] of this byte indicate the address of register. The data written
to the BL6523B should be ready on DIN before the rising edge of SLCK. After the BL6523B
receive the address of register, the BL6523B will shift out the data of the register on DOUT pin on
the rising edge of SCLK.
/CS
t1
t2
t3
t9
t10
SCLK
t4
DIN
A5
A4
A3
A2 A1 A0
t12
t11
DOUT
D7
命令字节
D6
D5
D4
数据高字节
D0
D7
D6
D5
D0
数据低字节
（DVDD＝5V± 5％，DGND＝0V，CLKIN＝3.58MHz XTAL，25℃）
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v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
min
type
max
unit
t9
The shortest interval from the End of the read
command to the start of read data read
5000
ns
t10
The shortest interval between two bytes of data
5000
ns
t11
Data setup time after the rising edge of SCLK
t12
Data hold time after the falling edge of SCLK
15/19
10000
5000
ns
ns
v1.0
BL6523B
Register
Register list
AD
DR
ESS
REGISTER
NAME
EXT
ERN
AL
R/W
INT
ERN
AL
R/W
BI
T
Single Phase, Multifunction Energy meter IC
DEFA
ULT
DESCRIPTION
ELECTRIC PARAMETERS REGISTER（INTERNAL WRITE）
01H
IA_WAVE
R
W
24
0
Wave register of channel A
02H
IB_WAVE
R
W
24
0
Wave register of channel B
03H
V_WAVE
R
W
24
0
Wave register of Voltage
04H
LINE_
WATTHR
R
W
24
0
Line cycle energy register
05H
IA_RMS
R
W
24
0
Irms register(channel A)
06H
IB_RMS
R
W
24
0
Irms register(channel B)
07H
V_RMS
R
W
24
0
Vrms
08H
PF
R
W
24
0
Power Factor
09H
FREQ
R
W
24
0
Frequency register
0AH
A_WATT
R
W
24
0
Average active power of channel A
0BH
VA
R
W
24
0
Average apparent power
0CH
WATTHR
R
W
24
0
Active energy
0DH
VAHR
R
W
24
0
Apparent energy
0EH
PWAHR
R
W
24
0
Positive active energy
0FH
NWAHR
R
W
24
0
Negative active energy
10H
IA_PEAK
R
W
24
0
Current A Peak register
11H
IB_PEAK
R
W
24
0
Current B Peak register
12H
V_PEAK
R
W
24
0
Voltage Peak register
13H
B_WATT
R
W
24
0
Average active power of channel B
Calibration registers ( External write，Except 3AH）
14H
MODE
R/W
R
12
000H
Mode regiser,
15H
GAIN
R/W
R
12
000H
Channel Gain register
16H
FAULTLVL
R/W
R
12
044H
Current imbalance shielding threshold
register
17H
WA_CREEP
R/W
R
24
FFF02
BH
Active power no-load threshold register
18H
WA_REVP
R/W
R
12
087H
Reverse threshold register
19H
WA_CFDIV
R/W
R
12
001H
Active power CF frequency divider
1AH
A_WATTOS
R/W
R
12
0
Active power offset correction(current
channel A)
1BH
B_WATTOS
R/W
R
12
0
Active power offset correction(current
B)
1CH
A_WATTGN
R/W
R
12
0
Active power gain(current channel A)
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v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
1DH
B_WATTGN
R/W
R
12
0
Active power gain(current channel B)
1EH
IA_PHCAL
R/W
R
8
0
Phase
calibration
register(current
channel
A)(bit[7]is
enable
bit,2.2us/1LSB）
1FH
IB_PHCAL
R/W
R
8
0
Phase
calibration
channel B)
register(current
20H
V_PHCAL
R/W
R
8
0
Phase
calibration
channel)
register(voltage
21H
VAOS
R/W
R
12
0
Apparent Power Offset Calibration
Register
22H
VAGN
R/W
R
12
0
Apparent power gain adjust register
23H
IA_RMSGN
R/W
R
12
0
Current A RMS gain adjust register
24H
IB_RMSGN
R/W
R
12
0
Current B RMS gain adjust register
25H
V_RMSGN
R/W
R
12
0
Voltage RMS gain adjust register
26H
IA_RMSOS
R/W
R
12
0
Current A RMS Offset Calibration
register
27H
IB_RMSOS
R/W
R
12
0
Current B RMS Offset Calibration
register
28H
V_RMSOS
R/W
R
12
0
Voltage RMS Offset Calibration register
29H
RMS_CREEP
R/W
R
12
0
RMS small signal threshold register
2AH
WA_LOS
R/W
R
24
0
Active-power offset Calibration register
Bit[23:12] B channel;
Bit[11:0] A channel;
2BH
IA_CHOS
R/W
R
12
0
Current A channel offset adjustment
register，
2CH
IB_CHOS
R/W
R
12
0
Current B channel offset adjustment
register
2DH
V_CHOS
R/W
R
12
0
Voltage
register
2EH
IA_CHGN
R/W
R
12
0
Current A channel gain adjustment
register
2FH
IB_CHGN
R/W
R
12
0
Current B channel gain adjustment
register
30H
V_CHGN
R/W
R
12
0
Voltage
register
31H
LINECYC
R/W
R
12
000H
32H
ZXTOUT
R/W
R
16
FFFFH
33H
SAGCYC
R/W
R
8
FFH
34H
SAGLVL
R/W
R
12
0
35H
IA_PKLVL
R/W
R
12
FFFH
17/19
channel
channel
Line energy
register
offset
gain
adjustment
adjustment
accumulation
cycles
Zero-crossing timeout
Sag period
Sag voltage level
Current peak threshold (current channel
A)
v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
36H
IB_PKLVL
R/W
R
12
FFFH
Current peak threshold (current channel
B)
37H
V_PKLVL
R/W
R
12
FFFH
Voltage peak threshold
38H
AT_SEL
R/W
R
16
0
Logic output selection
39H
MASK
R/W
R
12
0
Interrupt mask register,
3AH
STATUS
R
W
12
0
Interrupt state register
Special register
3BH
READ
R
R
24
0
Contains the data from the last read
operation of SPI
3CH
WRITE
R
R
24
0
Contains the data from the last write
operation of SPI
3DH
CHKSUM
R
R
24
0x0121
F2H
3EH
WRPROT
R/W
R
8
0
Checksum。The sum of register
14H~39H
Write protection register. Write 55H, it
means that allows write to writable
register。
Logic output selection register(AT_SEL)
The BL6523B contains four logic output pin(AT0~AT3) that can output some measurement
states. The AT_SEL register is used to set the AT0~AT3 pin output, AT_SEL [3：0] corresponds to
AT0; AT_SEL[7：4] corresponds to AT1; AT_SEL[11：8] corresponds to AT2; AT_SEL[15：12]
corresponds to AT3. The default value of AT_SEL register is 0x0000, the default output is
AT0=FAULT, AT1=REVP, AT2=ZX, AT3=nSAG.
设置
ATX
OUTPUT
DEFAULT
0000
DESCRIPTION
AT0=FAULT、AT1=REVP、AT2=ZX、AT3=nSAG
0001
nSAG
0
Sag event has occurred
0010
ZXTO
0
Indicates that zero crossing has been missing on the voltage
channel for the length of time specified in the ZXTOUT
register
0011
ZX
0
Voltage channel zero crossing
0100
PKIA
0
Current channel A peak has exceeded IAPKLVL
0101
PKIB
0
Current channel B peak has exceeded IBPKLVL
0110
PKV
0
Voltage peak has exceeded VPKLVL
0111
REVP
0
Sign of active power has changed to negative
1000
APEHF
0
Active energy register(WATTR) is half full
1001
VAPEHF
0
Apparent energy register(VAHR) is half full
1010
FAULT
0
Fault=1 indicates the imbalance in two channels rms, the
difference is greater than the FAULTLVL
1011
CHSEL
0
0 indicates measureing power with channel A;
1 indicates measureing power with channel B;
其余
Reversed
0
Reserved
18/19
v1.0
BL6523B
Single Phase, Multifunction Energy meter IC
Interrupt mask register（MASK）
BITS
INTERRUP DEFAULT
NAME
DESCRIPTION
0
SAG
0
Enable the interrupt that sag event has occurred
1
ZXTO
0
Enable the interrupt of ZXTO
2
ZX
0
Enable the interrupt of ZX
3
PKIA
0
Enable the interrupt of PAIA
4
PKIB
0
Enable the interrupt of PKIB
5
PKV
0
Enable the interrupt of PKV
6
REVP
0
Enable the interrupt of REVP
7
APEHF
0
Enable the interrupt of APEHF
8
VAPEHF
0
Enable the interrupt of VAPEHF
9
FAULT
0
Enable the interrupt of FAULT
10
CHSEL
0
Enable the interrupt of CHSEL
Others
Reversed
0
Reversed
Interrupt status registers(STATUS)
BITS
BIT
NAME
DEFAULT
DESCRIPTION
0
SAG
0
Sag event has occurred
1
ZXTO
0
Indicates that zero crossing has been missing on the voltage
channel for the length of time specified in the ZXTOUT
register
2
ZX
0
Voltage channel zero crossing
3
PKIA
0
Current channel A peak has exceeded IAPKLVL
4
PKIB
0
Current channel B peak has exceeded IBPKLVL
5
PKV
0
Voltage peak has exceeded VPKILVL
6
REVP
0
Sign of active power has changed to negative
7
APEHF
0
Active energy is half full
8
VAPEHF
0
Apparent energy is half full
9
FAULT
0
Fault=1 indicates the imbalance in two channels rms, the
difference is greater than the FAULTLVL
10
CHSEL
0
0 indicates measureing power with channel A;
1 indicates measureing power with channel B;
Others
Reversed
0
Reserved
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v1.0