DS1283 DS1283 Watchdog Timekeeper Chip FEATURES PIN ASSIGNMENT • Keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years; valid leap year compersation up to 2100 INTA 1 28 V CC X1 2 27 WE • Watchdog timer restarts an out–of–control processor X2 3 26 • Alarm function provides notice of real time related oc- NC 4 25 A5 5 24 RCLR A4 6 23 SQW currences • Designed for battery operation INTB(INTB) V BAT A3 7 22 OE and square wave outputs maintain 28–pin JEDEC footprint A2 8 21 INTP A1 9 20 CE • All registers are individually addressable via the ad- A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 • Programmable interrupts dress and data bus • Accuracy is better than ±2 minutes/month at 25°C • 50 bytes of user nonvolatile RAM DS1283 28–PIN DIP (600 MIL) • Optional 28–pin SOIC surface mount package • Low–power CMOS circuitry is maintained on less than 1 µA in standby mode • Optional industrial temperature range –40°C to +85°C DESCRIPTION The DS1283 Watchdog Timekeeper Chip is a self–contained real time clock, alarm, watchdog timer, and interval timer in a 28–pin JEDEC DIP or 28–pin SOIC surface mount package. The DS1283 is specifically designed to maintain internal operations from a single low voltage supply. In fact, the only two external components required by the DS1283 are a battery and crystal. For a complete description of operating conditions, electrical characteristics, bus timing, and pin descriptions other than X1, X2, VBAT, VCC, RCLR, INTB, and INTP see the DS1286 Watchdog Timekeeper data sheet. Copyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. V CC INTA 1 28 X1 2 27 WE X2 3 26 INTB(INTB) NC 4 25 VBAT A5 5 24 RCLR A4 6 23 SQW A3 7 22 OE A2 8 21 INTP A1 9 20 CE A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ2 13 16 DQ4 GND 14 15 DQ3 DS1283S 28–PIN SOIC (330 MIL) NOTE: Pin 4 must be left disconnected. 032697 1/5 DS1283 PIN DESCRIPTION PIN # NAME I/O DESCRIPTION 1 INTA O Interrupt Output A (open drain) 2–3 X1,X2 I 32.768 KHz Crystal 4 NC – No Connection 5-10 A0-A5 I Address Inputs: A5=Pin 5; A0=Pin 10 11 DQ0 I/O Data Input/Output 12 DQ1 I/O Data Input/Output 13 DQ2 I/O Data Input/Output 14 GND – 15 DQ3 I/O Data Input/Output 16 DQ4 I/O Data Input/Output 17 DQ5 I/O Data Input/Output 18 DQ6 I/O Data Input/Output 19 DQ7 I/O Data Input/Output 20 CE I Chip Enable 21 INTP O Interrupt Output P (open drain) 22 OE I Output Enable 23 SQW O Square Wave Output 24 RCLR I RAM Clear 25 VBAT I Battery Input 26 INTB (INTB) O Interrupt Output B (open drain) 27 WE I Write Enable 28 VCC I VCC Input Ground PIN DESCRIPTIONS X1, X2 – Connections for a standard 32.768 KHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a load capacitance (CL) of 6 pF. The crystal is connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. For more information on crystal selection and 032697 2/5 crystal layout considerations, please consult Application Note 58, “Crystal Considerations with Dallas Real Time Clocks.” VBAT, VCC – Inputs for batteries or power supplies between 5.5 and 2.5 volts. The VCC supply voltage should never exceed VBAT + 0.3 volts. The VBAT input is used to maintain all internal functions while the VCC input is used to keep all inputs and outputs functional. Therefore, to keep the device fully functional, VBAT and VCC must be at the same voltage potential. As long as the supply voltages are between 4.5 and 5.5 volts, the timing and the input/output levels are guaranteed. In this mode, the active current drain is 2 mA (CE=VIL) and the standby current drain is 0.5 mA (CE=VIH). Data retention mode occurs when the VBAT supply is between 5.5 and 2.5 volts and the VCC supply is grounded. In the data retention mode the current drain is less than 1 µA maximum at 5.5 volts (CE=VBAT–0.2 volts). The current drain specifications are stated with all outputs unloaded. RCLR – The RCLR pin is used to clear (set to logic 1) all 50 bytes of user nonvolatile RAM but does not affect the registers involved with time, alarm, and watchdog functions. In order to clear the RAM, RCLR must be forced to an input logic 0 (–0.3 to +0.8 volts). The RCLR function is designed to be used via human interface (shorting to ground manually or by switch) and not to be driven with external buffers. This pin is internally pulled up and should be left floating when not in use. INTB – Interrupt B on the DS1283 operates identical to interrupt B on the DS1286 except that the sink and source current is limited to 500 µA. This pin should be pulled up or down if not used. INTP – Interrupt P on the DS1283 was a missing or no connection pin on the DS1286. This interrupt works in the same manner as INTA as programmed by the IPSW bit. However, INTP is also logically ORed with the MSB of the date register (see Figure 1). This bit is called the INP bit on the DS1283 and is forced to zero on the DS1286. When the INP bit (interrupt P bit) is set to logical one, interrupt P will be held active low. When INP is set to logical zero, INTP is always at the same logic state as INTA. This pin is an open drain capable of sinking 4 mA. DS1283 DS1283 WATCHDOG TIMEKEEPER REGISTERS Figure 1 BIT 7 ADDRESS 0 CLOCK, CALENDAR, TIME OF DAY ALARM REGISTERS THIS BIT IS FORCED TO ZERO ON THE DS1286 0.1 SECONDS 0 10 SECONDS 2 0 10 MINUTES 3 M 10 MIN ALARM 4 0 12/24 5 M 12/24 (RETRIGGERABLE/ REPETITIVE COUNTDOWN ALARM) USER REGISTERS 00–59 00–23 01–12+A/P HR ALARM HR 00–23 0 0 0 7 M 0 0 0 0 8 INP 0 10 DATE EOSC ESQW 0 01–07 DAYS 01–07 DAY ALARM 01–31 DATE 10MO 01–12 MONTHS 00–99 YEARS 10 YEARS IPSW MIN ALARM A/P 0 TE 00–59 HOURS 0 B MINUTES 01–12+A/P HR A/P 10 00–59 SECONDS 6 A WATCHDOG ALARM REGISTERS 10 IBH LO C 0.1 SECONDS D 10 SECONDS RANGE 00–99 0.01 SECONDS 1 9 COMMAND REGISTERS BIT 0 PU LVL WAM TDM WAF 0.01 SECONDS SECONDS TDF 00–99 00–99 E 3F 032697 3/5 DS1283 DS1283 28–PIN DIP PKG MIN MAX A IN. MM 1.445 1.470 B IN. MM 0.530 0.550 C IN. MM 0.140 0.160 D IN. MM 0.600 0.625 E IN. MM 0.015 0.040 C F IN. MM 0.120 0.145 F G IN. MM 0.090 0.110 H IN. MM 0.625 0.675 J IN. MM 0.008 0.012 K IN. MM 0.015 0.022 B 1 A K E G D J H 032697 4/5 28–PIN DIM DS1283 DS1283 28–PIN SOIC K G PKG C A E 28–PIN DIM MIN MAX A IN. MM 0.706 17.93 0.728 18.49 B IN. MM 0.338 8.58 0.350 8.89 C IN. MM 0.086 2.18 0.110 2.79 D IN. MM 0.020 0.58 0.050 1.27 E IN. MM 0.002 0.05 0.014 0.36 F IN. MM 0.090 2.29 0.124 3.15 G IN. MM 0.050 1.27 H IN. MM 0.460 11.68 0.480 12.19 J IN. MM 0.006 0.15 0.013 0.33 K IN. MM 0.014 0.36 0.020 0.51 BSC B F 0–8 deg. typ. J H D 032697 5/5