DS2167/DS2168 DS2167/DS2168 ADPCM Processor FEATURES • Speech compression chip compatible with standard PIN ASSIGNMENT RST 1 24 VDD TM0 2 23 YIN – DS2167 supports “new” T1Y1 recommendations (July 1986) and “new” CCITT G.721 recommendations – DS2168 supports “old” CCITT G.721 recommendations TM1 3 22 CLKY A0 4 FSY A1 5 21 20 A2 6 19 CS A3 7 18 SDI • Dual independent channel architecture – device may A4 8 9 17 SCLK 16 XOUT SPS 10 15 FSX MCLK 11 CLKX VSS 12 14 13 be programmed to perform full duplex, 2-channel expansions, or 2-channel compressions • Interconnects directly with µ-law or A-law codec/filter A5 devices TM1 TM0 RST NC VDD YIN logic” in multiple channel applications – No host processor required – Ideal for voice mail applications NC A0 A1 A2 A3 A4 A5 54 3 2 6 7 8 9 1 28 27 26 25 24 23 22 21 10 20 11 12 13 14 15 16 17 1819 FSY YOUT CS SDI SCLK XOUT NC SPS MCLK VSS NC XIN CLKX FSX • Hardware mode intended for stand-alone use XIN 24-Pin DIP (600 MIL) • Serial PCM and control port interfaces minimize “glue – On-chip channel counters identify input and output timeslots in TDM-based systems – Unique addressing scheme simplifies device control; 3-wire port shared among 64 devices – Bypass and idle features allow dynamic allocation of channel bandwidth, minimize system power requirements YOUT CLKY ADPCM algorithms: 28-Pin PLCC • 28-pin surface-mount package available, designated DS2167Q/DS2168Q DESCRIPTION The DS2167 and DS2168 are dedicated digital signal processor (DSP) CMOS chips optimized for Adaptive Differential Pulse Code Modulation (ADPCM) based compression algorithms. The devices halve the trans- mission bandwidth of “toll quality” voice from 64K to 32K bits/second and are utilized in PCM-based telephony networks. 022698 1/15 DS2167/DS2168 PRODUCT OVERVIEW The DS2167 and DS2168 contain three major functional blocks: a high performance (10 MIPS) DSP “engine,” two independent PCM data interfaces (“X” and “Y”) which connect directly to serial time division multiplexed (TDM) backplanes and a microcontroller-compatible serial port for on-the-fly device configuration. A 10MHz master clock is required by the DSP engine. The devices’ dual channel architecture supports full duplex, dual compression or dual expansion operation. The PCM data interfaces support 1.544, 2.048 and 4.096 MHz data rates. Each device samples the serial PCM or ADPCM bit stream during a user-programmed input timeslot, processes the data and outputs the result during a user-programmed output timeslot. Each PCM interface has a control register which specifies functional characteristics (compress, expand, bypass and idle), data format (µ-law or A-law) and algorithm reset control. With the SPS pin strapped high, the software mode is enabled and the serial port is used to program control and timeslot registers. In this mode, a novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system level interconnect. With SPS low, the hardware mode is enabled. This mode disables the serial port and maps appropriate control register bits to address and port inputs. Under hardware mode, no host controller is required and all PCM I/O defaults to timeslot 0. This stand-alone mode is compatible with popular codecs. DS2168 BLOCK DIAGRAM Figure 1 FSX CLKX XIN XOUT “X” SIDE PCM/ADPCM DATA INTERFACE SCLK SPS CS SDI MCLK SERIAL PORT CONTROL/ HARDWARE MODE LOGIC ADPCM PROCESSING “ENGINE” A0 - A5 RST TM0 RESET AND TEST LOGIC TM1 VDD VSS FSY CLKY YIN 022698 2/15 “Y” SIDE PCM/ADPCM DATA INTERFACE YOUT DS2167/DS2168 PIN DESCRIPTION Table 1 PIN SYMBOL TYPE DESCRIPTION 1 RST I Reset. A high-low-high transition clears all internal registers and reset both algorithms. The device should be reset on system power-up, and/or when changing to/from hardware mode. 2 TM0 I Test Modes 0 and 1. Tie to VSS for normal operation 3 TM1 4 A0 I 5 A1 Address Select. A0=LSB; A5=MSB. Must match address/command word to enable serial port write. 6 A2 7 A3 8 A4 9 A5 10 SPS I Serial Port Select. Tie to VDD to select the serial port, to VSS to select the hardware mode. 11 MCLK I Master Clock. 10 MHz clock for ADPCM processing “engine”; may asynchronous to SCLK, CLKX and CLKY. 12 VSS – Signal Ground. 0.0 volts 13 XIN I X Data In. Samples on falling edge of CLKX during selected timeslots. 14 CLKX I X Data Clock. Data clock for X side PCM interface; must be coherent and rising edge aligned with FSX. 15 FSX I X Frame Sync. 8 KHz frame sync for X side PCM interface. 16 XOUT O X Data Out. Updated on rising edge of CLKX during selected timeslots. 17 SCLK I Serial Data Clock. Used to write serial port registers. 18 SDI I Serial Data In. Data for onboard control registers. Sampled on rising edge of SCLK. 19 CS I Chip Select. Must be low to write the serial port. 20 YOUT O Y Data Out. Updated on rising edge of CLKY during selected timeslots. 21 FSY I Y Frame Sync. 8 KHz frame sync for Y side PCM interface. 22 CLKY I Y Data Clock. Data clock for Y side PCM interface; must be coherent and rising edge aligned with FSY. 23 YIN I Y Data In. Samples on falling edge of CLKY during selected timeslots. 24 VDD – Positive Supply. 5.0 volts. HARDWARE RESET RST allows the user to reset both channel algorithms and register contents. This input must be held low for at least 1 ms on system power-up after master clock is stable to assure proper initialization of the device. RST should also be asserted when changing to/from the hardware mode. RST clears all bits of the control register except IPD; IPD is set for both channels, powering down the device. 022698 3/15 DS2167/DS2168 HARDWARE MODE The hardware mode is intended for preliminary system prototyping or for applications which do not require the features of the serial port. Tying SPS to VSS disables the serial port, clears all internal registers and maps IPD, µ/A and CP/EX of the X and Y side interfaces to the port and address inputs. Input and output timeslots for the X and Y side interfaces are fixed at 0. Such applications include, but are not limited to: 1) systems in which timeslot and algorithm are fixed, 2) stand-alone ADPCM combo applications, 3) “hardware” oriented systems where no host controller is available. HARDWARE MODE Table 2 PIN #/NAME REG. LOCATION 4/A0 CP/EX (X) NAMES AND DESCRIPTION Channel X coding 0 = Expand 1 = Compress 6/A2 µ/A (X) Channel X data format 0 = A-law 1 = µ-law 7/A3 CP/EX (Y) Channel Y coding 0 = Expand 1 = Compress 9/A5 µ/A (Y).2 Channel Y data format 0 = A-law 1 = µ-law 18/SDI IPD (Y) Y idle select 0 = Channel active 1 = Channel idle 19/CS IPD (X) X idle select 0 = Channel active 1 = Channel idle NOTES: 1. SCLK, A1 and A4 must be tied to VSS when the hardware mode is selected. 2. When both X and Y sides are idled, the devices enter a stand-by mode which significantly reduces power consumption. 3. The DS2167 will power-up within 200 ms after the X or Y side is reactivated (SDI and/or CS not equal to 0) from standby. 4. The DS2168 must be hardware reset when reactivated from standby. Power-up occurs immediately after the reset. 022698 4/15 DS2167/DS2168 CODEC/FILTER HARDWARE MODE INTERCONNECT Figure 2 POWER ON RESET (DS1231) TRANSMIT FRAME SYNC TRANSMIT DATA CLOCK RST VDD SCLK A0 DX XIN A5 FSX FSX A2 VCC MCLKX VBB TSX TRANSMIT ANALOG INTERFACE VFXI+ VFSIGSX RECEIVE ANALOG INTERFACE BCLKX CLKX DR YOUT FSY FSR BCLK/ CLKSEL CLKY DS2167/DS2167 GNDA CODEC/FILTER TP3054 (µ-LAW) -5.0 V XOUT YIN TP3057 (µ-LAW) TRANSMIT DATA RECEIVE DATA A3 A4 A1 MCLK/PDN SPS VFRO POWER DOWN TM0 RECEIVE DATA CLOCK SDI TM1 CS VSS MCLK ACTIVE 10 MHz CLOCK RECEIVE FRAME SYNC NOTE: Suggested Codec/Filters TP305X National Semiconductor ETC505X SGS–Thomson Microelectronics MC1455XX Motorola TCM29CXX Texas Instruments HD44238C Hitachi *other generic Codec/Filter devices can be substituted. SOFTWARE MODE Tying SPS high enabled the software mode. In this mode, a host microcontroller writes configuration data to the DS2167/DS2168 serial port via inputs SCLK, SDI, and CS. Independent control and timeslot registers establish operating characteristics for the X-side and Yside PCM interfaces. ADDRESS/COMMAND BYTE In the software mode, the address/command byte is the first byte written to the serial port; it identifies which of 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must match that at inputs A0–A5. If no match occurs, the device ignores the following configuration data. If an address match occurs, the next three bytes written are accepted as control, input and output timeslot data. Bit ACB.6 determines which side (X or Y) of the device is to be updated. CONTROL REGISTER The control register establishes idle, algorithm reset, bypass, data format and channel coding for the selected PCM interface. The X and Y side PCM interfaces may be independently disabled (output tri-stated) via IPD; when IPD is set for 022698 5/15 DS2167/DS2168 both X and Y interfaces, the device enters a low-power standby mode. The DS2167 will power-up within 200 ms after the X or Y side is reactivated (IPD=0) from standby. The DS2168 requires an external hardware reset after IPD is cleared to “wake-up” from standby. The DS2168 will power-up immediately after the low-high transition on RST. ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST will be cleared by the device when the algorithm reset is complete. The bypass feature is enabled when BYP is set and IPD is clear. During bypass, no expansion or compression of data occurs. This feature allows the user to interchange timeslots under control of the timeslot registers. Bypass operates on byte-wide slots when CP/EX=1, on nibblewide slots when CP/EX=0. A-law (µ/A=0) or µ-law PCM (µ/A=1) coding is independently selected for the X and Y side interfaces by bit µ/A. If BYP and IPD are clear, CP/EX determines if input data is to be compressed or expanded. TIMESLOT ASSIGNMENT On-chip counters establish when PCM data I/O occurs and are programmed via the timeslot registers. Timeslot size (4 or 8 bits wide) is determined by the state of CP/EX. Timeslots are counted from the rising edge of FSX and FSY. ADDRESS/COMMAND BYTE Figure 3 (MSB) – (LSB) X/Y SYMBOL POSITION A5 A4 A3 A2 NAME AND DESCRIPTION – ACB.7 Reserved, must be 0 for proper operation. X/Y ACB.6 X/Y Channel Select. 0 = Update channel Y characteristics. 1 = Update channel X characteristics. A5 ACB.5 MSB of Device Address. A4 ACB.4 A3 ACB.3 A2 ACB.2 A1 ACB.1 A0 ACB.0 022698 6/15 LSB of Device Address. A1 a0 DS2167/DS2168 CONTROL REGISTER Figure 4 (MSB) (LSB) – – IPD ALRST BYP µ/A SYMBOL POSITION – CR.7 Reserved, must be 0 for proper operation. – CR.6 Reserved, must be 0 for proper operation. IPD CR.5 Idle and Power Down. 0 = channel enabled. 1 = channel disabled (output tri-stated). ALRST CR.4 Algorithm Reset. 0 = Normal operation. 1 = Reset algorithm for selected channel. BYP CR.3 Bypass. 0 = Normal operation. 1 = Bypass selected channel. µ/A CR.2 Data Format 0 = A-law. 1 = µ-law. – CR.1 Reserved, must be 0 for proper operation. CP/EX CR.0 Channel Coding. 0 = Expand (decode) selected channel. 1 = Compress (encode) selected channel. – CP/EX NAME AND DESCRIPTION INPUT TIMESLOT REGISTER Figure 5 (MSB) – (LSB) – D5 D4 D3 D2 SYMBOL POSITION – ITR.7 Reserved, must be 0 for proper operation. – ITR.6 Reserved, must be 0 for proper operation. D5 ITR.5 MSB of input timeslot word. D4 ITR.4 D3 ITR.3 D2 ITR.2 D1 ITR.1 D0 ITR.0 D1 D0 NAME AND DESCRIPTION LSB of input timeslot word. 022698 7/15 DS2167/DS2168 OUTPUT TIMESLOT REGISTER Figure 6 (MSB) (LSB) – – D5 D4 D3 D2 SYMBOL POSITION – OTR.7 Reserved, must be 0 for proper operation. – OTR.6 Reserved, must be 0 for proper operation. D5 OTR.5 MSB of output timeslot word. D4 OTR.4 D3 OTR.3 D2 OTR.2 D1 OTR.1 D0 OTR.0 D1 D0 NAME AND DESCRIPTION LSB of output timeslot word. PCM I/O TIMING (1.544 MHz BACKPLANE) Figure 7 CLKX, CLKY 193 TIMESLOT 0 TIMESLOT N TIMESLOT 23 193 FSX, FSY XIN, YIN MSB LSB XOUT, YOUT ADPCM I/O TIMING (1.544 MHz BACKPLANE) Figure 8 CLKX, CLKY 193 TIMESLOT 0 TIMESLOT 1 TIMESLOT N TIMESLOT 45 FSX, FSY XIN, YIN MSB XOUT, YOUT 022698 8/15 LSB TIMESLOT 46 TIMESLOT 47 193 DS2167/DS2168 SERIAL PORT WRITE command and control) or four bytes (address/command, control, input timeslot and output timeslot) in length. Writes should be terminated on byte boundaries to insure data integrity. PCM and ADPCM outputs will tristate during register updates. All port writes are initiated by driving CS low and terminated when CS returns high. Data is sampled on the rising edge of SCLK and must be written to the device LSB first. Writes to the device may be two bytes (address/ SERIAL PORT WRITE Figure 9 CS SCLK SDI1 A0 A1 A2 A3 A4 A5 X/Y – CR0 CR1 CR2 CR3 CR4 A0 A1 NOTE: ÉÉÉ ÉÉ ÉÉÉ ÉÉ A2 1. 2-byte write shown. 8051-BASED CONTROL SYSTEM Figure 10 8051 CONTROLLER P1.0 RXD TXD POWER-ON RESET (DS1231) VDD RST VDD RST TM0 YIN TM0 YIN TM0 YIN TM1 CLKY TM1 CLKY TM1 CLKY A1 A2 A3 A4 A5 FSY A0 YOUT A1 CS A2 SDI A3 SCLK A4 XOUT A5 FSX SPS MCLK CLKX XIN VSS 10 MHz CLOCK SPS MCLK VSS FSY A0 YOUT A1 CS A2 SDI A3 SCLK A4 XOUT A5 FSX CLKX XIN SPS MCLK VSS VDD FSY DS2167/68 #63 DS2167/68 #0 A0 DS2167/68 #1 RST YOUT CS SDI SCLK XOUT FSX CLKX XIN PCM DATA HI-WAY “Y” PCM DATA HI-WAY “X” 022698 9/15 DS2167/DS2168 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –1.0V to 7.0V 0°C to +70°C –55°C to 125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER SYMBOL MIN Logic 1 VIH Logic 0 Supply (0°C to 70°C) TYP MAX UNITS 2.0 VCC +0.3 V VIL -0.3 +0.8 V VDD 4.5 5.5 V CAPACITANCE PARAMETER Input Capacitance Output Capacitance (tA = 25°C) SYMBOL MAX UNITS CIN MIN TYP 5 pF COUT 10 pF DC ELECTRICAL CHARACTERISTICS PARAMETER NOTES SYMBOL NOTES (0°C to 70°C; VDD = 5V + 10%) MIN TYP MAX UNITS NOTES Supply Current (Active) IDDA 30 mA 1,2 Supply Current (Idle) IDDPD 1 mA 1,2,3 IIL -1.0 +1.0 µA Output Leakage ITRI -1.0 +1.0 µA Output Current @ 2.4V IOH -1.0 mA Output Current @ 0.4V IOL 4.0 mA Input Leakage NOTES: 1. CLKX = CLKY = 1.544 MHz; MCLK = 10 MHz. 2. Outputs open; inputs swinging full supply levels. 3. Both channels in idle mode. 4. XOUT and YOUT when tri-stated. 022698 10/15 4 DS2167/DS2168 PCM INTERFACE AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MCLK Period tPM MCLK Pulse Width MCLK Rise and Fall Times CLKX, CLKY Period CLKX, CLKY Pulse Width CLKX, CLKY Rise and Fall Times Hold Time from CLKX, CLKY to FSX, FSY tWMH, tWML (0°C to 70°C, VDD = 5V + 10%) MIN TYP MAX 100 45 tRM, tFM NOTES ns 5 50 55 ns 5 10 ns 5208 ns tPXY 244 488 tWXYH, tWXYL 100 244 tRXY, tFXY UNITS 10 4 ns 20 ns tHOLD 0 ns 1 Setup Time from FSX, FSY to CLKX, CLKY low tSF 50 ns 1 Hold Time from CLKX, CLKY low to FSX, FSY low tHF 100 ns 1 XIN, YIN Setup to CLKX, CLKY low tSD 50 ns 1 XIN, YIN Hold to CLKX, CLKY low tHD 50 ns 1 Delay Time from CLKX, CLKY to Valid XOUT, YOUT tDXYO 10 150 ns 2 Delay Time from CLKX, CLKY to XOUT, YOUT Tri-stated tDXYZ 20 150 ns 1,2,3 NOTES: 1. Measured at VIH = 2.0V, VIL = 0.8V, and 10 ns maximum rise and fall times. 2. Load = 150 pF + 2 LSTTL loads. 3. For LSB of PCM byte or ADPCM nibble. 4. Maximum width of FSX, FSY is one CLKX, CLKY period. 5. MCLK = 10 MHz + 500 ppm. 022698 11/15 DS2167/DS2168 MASTER CLOCK/RESET AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MCLK Period tPM (0° to 70°C, VDD = 5V + 10%) MIN TYP 100 MCLK Pulse Width tWMH, tWML 45 RST Pulse Width tWRL 1 50 MIN SDI to SCLK Setup tDC SCLK to SDI Hold SCLK High Time SCLK Rise and Fall Times NOTES ns 5 ns (0°C to 70°C, VDD = 5V + 10%) SYMBOL SCLK Low Time 55 UNITS ms SERIAL PORT AC ELECTRICAL CHARACTERISTICS PARAMETER MAX TYP UNITS NOTES 55 ns 1 tCDH 55 ns 1 tCL 250 ns 1 tCH 250 ns 1 ns 1 tR, tF MAX 100 CS to SCLK Setup tCC 50 ns 1 SCLK to CS Hold tCCH 250 ns 1 CS Inactive Time tCWH 250 ns 1 SCLK Setup to CS Falling tSCC 50 ns 1 NOTES: 1. Measured at VIH = 2.0V, VIL = 0.8V, and 10 ns maximum rise and fall times. 2. MCLK = 10 MHz + 500 ppm. 022698 12/15 DS2167/DS2168 PCM INTERFACE AC TIMING DIAGRAM Figure 11 tPXY tHOLD tRXY tFXY tWXYH tWXYL CLKX CLKY tHF FSX FSY tSF ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ tSD tHD XIN YIN XOUT YOUT tDXYZ tDXYO MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 12 tPM tFM tRM tWMH tWML MCLK tWRL RST SERIAL PORT WRITE AC TIMING DIAGRAM Figure 13 tCWH CS tCC tR tCH tF tCCH tSCC SCLK ÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉ tCL tDC SDI tCDH ÉÉÉÉÉÉ ÉÉÉÉÉÉ 022698 13/15 DS2167/DS2168 DS2167/DS2168 ADPCM PROCESSOR 24-PIN DIP B D 1 A E C F K G INCHES DIM MIN MAX A IN. MM 1.245 31.62 1.270 32.25 B IN. MM 0.530 13.46 0.550 13.97 C IN. MM 0.140 3.56 0.160 4.06 D IN. MM 0.600 15.24 0.625 15.88 E IN. MM 0.015 0.380 0.050 1.27 F IN. MM 0.120 3.05 0.145 3.68 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.625 15.88 0.675 17.15 J IN. MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.38 0.022 0.56 022698 14/15 J H DS2167/DS2168 DS2167/DS2168Q ADPCM PROCESSOR 28-PIN PLCC E E1 B L1 N 1 D1 D D2 B1 CH1 e1 C A E2 A2 A1 INCHES DIM. MIN. MAX. A 0.165 0.180 A1 0.090 0.120 A2 0.020 – B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 D 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E1 0.450 0.456 E2 0.390 0.430 L1 0.060 – N 28 – e1 CH1 0.050 BSC 0.042 0.048 022698 15/15