INTEGRATED CIRCUITS DATA SHEET SAA4981 Monolithic integrated 16 : 9 compressor Preliminary specification Supersedes data of May 1994 File under Integrated Circuits, IC02 1995 Oct 05 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SAA4981 • 5 MHz bandwidth The synchronisation input HREF is a line frequency reference signal. The bandwidth of the IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y, (B−Y) and (R−Y) and provides the following two possibilities: • Bypass function 1. Bypass function (the input signal is not compressed) • Inputs for luminance and chrominance of side panels 2. Compressed video by a factor of 4⁄3 with three different fixed screen positions (left, centre and right). The luminance and chrominance of the side panels are determined by the external signals YSIDE, BYSIDE and RYSIDE. FEATURES • Fixed horizontal compression by a factor of video standards 4⁄ 3 for most • Three fixed screen positions (left, centre and right) • Standard video inputs and outputs (Y, (B−Y) and (R−Y)) • Horizontal and vertical sync signals are not processed • Pre filters and post filters on chip. The horizontal compression is a time discrete and amplitude continuous signal processing. This provides pre and post filters which are realized on-chip. The internal clock generation is achieved with a 54 MHz horizontal PLL which is synchronized to the positive edge of the HREF signal. The function of the IC is controlled by the three control signals CTRL1, CTRL2 and CTRL3. GENERAL DESCRIPTION The integrated 16 : 9 compressor is an IC which compresses the active part of a video line by a factor of 4⁄3 from, for example, 52 µs to 39 µs. This is necessary to display 4:3 video software on a 16 : 9 tube in the correct proportion. The capacitively coupled video inputs are Y, (B−Y) and (R−Y). QUICK REFERENCE DATA Voltages for video signals are peak-to-peak values for 75% colour bars. All voltages are referenced to VEEA = VEED = 0 V. SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.5 V VCCD digital supply voltage 4.75 5.0 5.5 V ViY(p-p) Y input voltage (peak-to-peak value) − 0.32 0.45 V ViU(p-p) (B−Y) input voltage (peak-to-peak value) − 1.33 1.9 V ViV(p-p) (R−Y) input voltage (peak-to-peak value) − 1.05 1.5 V ViHREF input HREF top pulse 3.0 − 6.5 V VoY(p-p) YOUT output voltage (peak-to-peak value) − 0.32 0.5 V VoU(p-p) (B−Y)OUT output voltage (peak-to-peak value) − 1.33 2.1 V VoV(p-p) (R−Y)OUT output voltage (peak-to-peak value) − 1.05 1.7 V ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION SAA4981 DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1 SAA4981T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 1995 Oct 05 2 19 VEED 8 7 SC LINE MEMORY CLAMP SUB 4 MUX SC LINE MEMORIES 5 MHz LOW-PASS FILTER SC LINE MEMORY 6.7 MHz LOW-PASS FILTER 18 MUX Y YOUT SAA4981 C1 SC LINE MEMORY 22 CLAMP (B-Y)IN MUX SC LINE MEMORIES 5 MHz LOW-PASS FILTER SC LINE MEMORY 6.7 MHz LOW-PASS FILTER 3 SC LINE MEMORY 21 CLAMP MUX SC LINE MEMORIES 5 MHz LOW-PASS FILTER SC LINE MEMORY 6 C2 MUX RY C1 C2 17 (B-Y)OUT C3 6.7 MHz LOW-PASS FILTER 3 HORIZONTAL SEPARATION 16 (R-Y)OUT C3 C1 C2 CONTROLLER 3 C3 54 MHz PLL TEST 9 10 11 1 2 3 24 5 CTRL3 14 13 MHA277 BYSIDE RYSIDE YSIDE CTRL2 CTRL1 15 CLMBY Fig.1 Block diagram. CLMRY CLAOUT BGREF SAA4981 CLMY Preliminary specification 12 CLAMP REFERENCE handbook, full pagewidth HREF C3 MUX BY C1 (R-Y)IN C2 Philips Semiconductors 20 VCCD Monolithic integrated 16 : 9 compressor VEEA BLOCK DIAGRAM 1995 Oct 05 23 YIN VCCA Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SAA4981 PINNING SYMBOL PIN DESCRIPTION CLMY 1 decoupling capacitor for Y reference voltage CLMBY 2 decoupling capacitor for BY reference voltage CLMRY 3 decoupling capacitor for RY reference voltage SUB 4 substrate connection (see Fig.5) CLAOUT 5 internal clamping reference voltage output handbook, halfpage CLMY 1 24 BGREF CLMBY 2 23 YIN CLMRY 3 22 (B-Y)IN SUB 4 21 (R-Y)IN CLAOUT 5 20 VCCA HREF 6 HREF 6 horizontal reference input VEED 7 ground for digital section VCCD 8 positive digital supply voltage CTRL1 9 control input 1 CTRL2 10 control input 2 CTRL3 11 control input 3 TEST 12 test mode activation RYSIDE 13 side panel input for RY CTRL2 10 15 YSIDE BYSIDE 14 side panel input for BY CTRL3 11 14 BYSIDE YSIDE 15 side panel input for Y TEST 12 13 RYSIDE (R−Y)OUT 16 output signal for (R−Y) (B−Y)OUT 17 output signal for (B−Y) YOUT 18 output signal for Y VEEA 19 ground for analog section VCCA 20 positive analog supply voltage (R−Y)IN 21 input signal for (R−Y) (B−Y)IN 22 input signal for (B−Y) YIN 23 input signal for Y BGREF 24 decoupling capacitor for internal reference voltage 1995 Oct 05 SAA4981 19 VEEA VEED 7 18 YOUT VCCD 8 17 (B−Y)OUT CTRL1 9 16 (R−Y)OUT MHA276 Fig.2 Pin configuration. 4 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SAA4981 FUNCTIONAL DESCRIPTION Output multiplexer MUX Y, MUX (B−Y) and MUX (R−Y) Applicable video standards The output multiplexers are controlled via C1 and C2 fed from the controller. The multiplexers are used to connect one of the four input signals to the output and, also, enable fast switching. The integrated 16 : 9 compressor can be used for the following video standards; B, C, D, G, H, I, K, K1, L, M and N. standards D, I, K, K1 and L will show a reduced video bandwidth above 5 MHz. The input signals of the multiplexers for one component [Y, (B−Y) or (R−Y)] are as follows: Clamping circuit • The output signal of the post filter The clamping circuits clamp the video input signals Y, (B−Y) and (R−Y) to the DC level of the clamp reference signal fed from the clamp reference circuit. This is necessary to ensure that the input signals are in the correct input voltage range for the 5 MHz low-pass filters and the SC line memories. • The uncompressed signal after the input clamping Internal pre filters The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal, which is generated in the horizontal separation circuit. It is also possible to use the positive edge of the burst key of a sandcastle signal. • The clamping reference signal • The signal for the side panel determined by YSIDE, BYSIDE and RYSIDE. The horizontal separation circuit Before the signals are sampled in the time discrete and amplitude continuous area, low-pass filtering is necessary to avoid any aliasing. Even if the inputs have already been low-pass filtered further filtering is advantageous for the electromagnetic compatibility (EMC). The same transfer function is used for all three low-pass filters because of the same bandwidth for the luminance and chrominance signals (up to 5 MHz). 54 MHz horizontal PLL The 13.5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for the reading clock are generated in the 54 MHz horizontal PLL. The 13.5 MHz clock and the 18 MHz clock are line locked. SC line memories Clamp reference After the low-pass filters the input signals are fed to the SC line memories. The signals are sampled at a clock frequency of 13.5 MHz. One video line later the signals are read with a clock frequency of 18 MHz in the compression mode. The result of the different clock frequencies is a horizontal compression by a factor of 4⁄3. The clocks and the horizontal starting pulses for the SC line memories are fed from the controller. Reference voltages are generated In the clamp reference block. These DC signals are used in the clamping circuits as input signals for the output multiplexers and as reference voltages for the SC line memories. Four external capacitors at the pins CLMY, CLMBY, CLMRY and BGREF respectively are necessary to provide smoothing for the reference voltages. A black level reference signal is available at CLAOUT. Two line memories are required for each signal path because in the compression mode, in one video line the signals are sampled to the SC line memories with 13.5 MHz and one video line later the signals are read with 18 MHz. In the bypass mode, via the SC line memories, in one video line the signals are sampled with 13.5 MHz and one video line later the signals are read with 13.5 MHz. The SC line memories are suitable for signals with a bandwidth up to 5 MHz. With a multiplexer (MUX) behind the SC line memories, the sampled video signal is connected to the internal post filters. 1995 Oct 05 5 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SAA4981 Controller Signals for the side panels The controller generates the clocks and the horizontal start signals for the SC line memories and, also, the control signals for the output multiplexers. The timing for the start reading signal for three different screen positions (left, centre and right) and the control signals for the multiplexers (C1 and C2) is fixed. For the uncompressed signals a bypass via the SC line memories and a bypass not via the SC line memories is available. When the signals do not pass the line memories, the frequency response is not affected by the si-function. The compression and bypass mode via the line memories is delayed by one line with respect to the bypass mode not via the line memory. The luminance and chrominance of the side panels is determined by the external signals YSIDE, BYSIDE and RYSIDE. This external generated side panel signal can be referenced to the internal black level reference signal via the output CLAOUT (pin 5). Horizontal timing (see Fig.3) The horizontal timing refers to the positive edge of the input HREF signal. The following timing parameters are valid for a horizontal frequency of 15.625 kHz. Input clamping typically starts at tA = 1.55 µs and ends at tB = 3.78 µs. The 16 : 9 compressor is controlled via the control signals CTRL1, CTRL2 and CTRL3 (see Table 1). The test input must be LOW level. Table 1 Functions of the control signals CTRL1 CTRL2 CTRL3 FUNCTION LOW LOW LOW bypass (through the line memories) LOW HIGH LOW compression, left position HIGH LOW LOW compression, centre position HIGH HIGH LOW compression, right position LOW LOW HIGH bypass (not through the line memories) Internal post filters The output signals of the SC line memories have to be filtered with three 6.7 MHz low-pass filters to eliminate the high frequencies caused by the time discrete signal processing. The cut-off frequency of 6.7 MHz is necessary because, as a result of the 3⁄4 compression factor, the frequencies are shifted to a higher frequency band with the inverse compression factor (e.g. 5 MHz → compression → 6.67 MHz). Due to the common bandwidth requirements for all three outputs of the SC line memories the same transfer function for the filters can be used. Remark: These filters do not provide an si-correction. This means that an input signal with a frequency of 5 MHz will be damped by 2.1 dB at the output if the signal passes an SC line memory. 1995 Oct 05 6 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor handbook, full pagewidth SAA4981 HREF 64 µs 1.5 µs 1.5 µs (2) (2) (1) sampled video 49 µs (used for compression) 6.3 µs 52 µs 36.75 µs side compressed video side panel (centre position) panel side compressed video panel (right position) compressed video side (left position) panel bypassed video (bypass via the Line Memories) (2) (2) bypassed video (1) (full bypass not through the Line Memories) MHA278 (1) Nominal timing for a 52 µs active video signal to generate a centred compressed video signal. (2) Worst case picture position for a 52 µs active video signal to generate no visible blanking between side panels and compressed video. Fig.3 Horizontal timing. 1995 Oct 05 7 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor handbook, full pagewidth CVBS Y/C COLOUR DECODER TDA4650 OR TDA4655/7 AND TDA4665 sync Y −(B−Y) −(R−Y) 3 SAA4981 Y −(B−Y) −(R−Y) PICTURE SIGNAL IMPROVEMENT TDA4670/1 3 16:9 COMPRESSOR SAA4981 YOUT −(B−Y)OUT −(R−Y)OUT 3 VIDEO PROCESSOR TDA4680/7 TDA4780 R G B ASC 3 SYNC TDA2579B 1 CTRL sandcastle 3 1 SIDE MHA279 1 Fig.4 Receiver for 16 : 9, 50 Hz and 15.625 kHz with 16 : 9 compressor. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL Vn PARAMETER CONDITIONS voltage on any pin (except pin 6 HREF) MIN. MAX. UNIT VEEA − 0.5 VCCA + 0.5 V VEED − 0.5 VCCD + 0.5 V V6 input voltage at pin 6 −0.5 +6.5 V Ptot total power dissipation − 0.5 W Tstg storage temperature −25 +150 °C Tamb operating ambient temperature Ves electrostatic handling for all pins −20 +70 °C note 1 −500 +500 V note 2 −4000 +4000 V Notes 1. Equivalent to discharging a 200 pF capacitor via a 0 Ω series resistor. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. QUALITY SPECIFICATION In accordance with UZW-B0/FQ-0601. ESD classification A. 1995 Oct 05 8 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SAA4981 CHARACTERISTICS VCCA = VCCD = 5 V; Tamb = 25 °C; fHREF = 15.625 kHz; substrate connected to VEED; YSIDE, BYSIDE and RYSIDE are connected to CLAOUT; all voltages are referenced to VEEA = 0 V; input signal EBU colour bar 100/0/75/0 (CCIR recommended 471-1), Y = 0.32 V (p-p), (B−Y) = 1.33 V (p-p), (R−Y) = 1.05 V (p-p); source impedance Zis = 300 Ω; coupling capacitor Ck = 2.2 nF; output loads connected to ground RL = 1 MΩ, CL = 20 pF; measured in Fig.5; test input pin 12 has to be connected to VEED; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply (pins 20, 19, 8, 7 and 4); note 1 VCCA analog supply voltage 4.75 5.0 5.5 V ICCA analog supply current 35 50 65 mA VCCD digital supply voltage 4.75 5 5.5 V ICCD digital supply current 1 9 14 mA − 0.32 0.45 V Video inputs (pins 23, 22 and 21) Y ViY(p-p) input voltage (peak-to-peak value) active video CI(Y) input capacitance − − 10 pF ILI(Y) input leakage current between clamping − − 0.1 µA RiY(cl) input resistance during clamping − 2 5 kΩ − 1.33 1.9 V (B−Y) Vi(B-Y)(p-p) input voltage (peak-to-peak value) active video CI(B-Y) input capacitance − − 10 pF ILI(B-Y) input leakage current between clamping − − 0.1 µA RI(B-Y)(cl) input resistance during clamping − 2 5 kΩ − 1.05 1.5 V (R−Y) Vi(R−Y)(p-p) input voltage (peak-to-peak value) active video CI(R−Y) input capacitance − − 10 pF ILI(R−Y)(cl) input leakage current between clamping − − 0.1 µA RI(R−Y)(cl) input resistance during clamping − 2 5 kΩ HREF input (pin 6) Vi(top) input voltage of the top pulse 3.0 − 6.5 V ILI(HREF) input leakage current − − 10 µA CI(HREF) input capacitance − − 10 pF Vslice slicing level below top pulse 0.5 0.75 1.0 V fi input frequency 14.0 15.6 17.2 kHz tW pulse width 1 − − µs SHREF steepness 400 − − mV/ns 0.5 V under top Side panel inputs (pins 15, 14 and 13) Vi(side) input voltage 0.5 − 2.5 V CI(side) input capacitance − − 10 pF ILI(side) input leakage current − − 0.1 µA 1995 Oct 05 9 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SYMBOL PARAMETER SAA4981 CONDITIONS MIN. TYP. MAX. UNIT Control inputs/outputs (pins 9, 10 and 11) VIH HIGH level input voltage 3.5 − − V VIL LOW level input voltage − − 1.5 V CIctr input capacitance − − 10 pF ILIctr input leakage current − − 1 µA 1.3 1.45 1.6 V Clamping reference output (pin 5) Vo5 output voltage RL load resistor 10 − − kΩ CL load capacitor − − 30 pF External capacitors (pins 1, 2 and 3) CDL value for capacitor − 100 − nF VoCDL output voltage 1.3 1.45 1.6 V External capacitor (pin 24) CBGREF value for capacitor − 100 − nF VoBGREF output voltage 1.1 1.25 1.4 V Video output signals (pins 18, 17 and 16) YOUT RO(Y) output resistance − − 100 Ω VoY(p-p) output voltage (peak-to-peak value) − 0.32 0.5 V S/N signal-to-noise ratio 0.32 V (p-p)/Veff noise; unweighted; fi = 200 kHz to 5 MHz 52 − − dB FPN(p-p) fixed pattern noise peak-to-peak referenced to 0.32 V (p-p) video fclk < 5 MHz 42 − − dB αctY crosstalk between different inputs fi = 1 MHz 40 − − dB |td| delay between different outputs − − 30 ns td jitter in output signal referenced to HREF input signal − − 10 ns Bypass not via the SC line memories GY1 frequency response fripple = 0 to 4 MHz −0.5 − +0.5 dB GY2 frequency response attenuation at 5 MHz compared to 1 MHz 0 − −2 dB Bypass via the SC line memories; note 2 GY3 YOUT/YIN at input frequency fi = 1 MHz −1.1 − +0.9 dB GY4 YOUT/YIN at input frequency fi = 2 MHz −1.3 − +0.7 dB GY5 YOUT/YIN at input frequency fi = 3 MHz −1.7 − +0.3 dB GY6 YOUT/YIN at input frequency fi = 4 MHz −2.3 − −0.3 dB GY7 YOUT/YIN at input frequency fi = 5 MHz −3.1 − −1.1 dB 1995 Oct 05 10 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SYMBOL PARAMETER SAA4981 CONDITIONS MIN. TYP. MAX. UNIT Compressed video; note 2 GY8 YOUT/YIN at input frequency fi = 1 MHz; fo = 1.3 MHz −1 − +1 dB GY9 YOUT/YIN at input frequency fi = 2 MHz; fo = 2.7 MHz −1 − +1 dB GY10 YOUT/YIN at input frequency fi = 3 MHz; fo = 4 MHz −2 − 0 dB GY11 YOUT/YIN at input frequency fi = 3.75 MHz; fo = 5 MHz −3 − −1 dB GY12 YOUT/YIN at input frequency fi = 4 MHz; fo = 5.3 MHz −4 − −1 dB GY13 YOUT/YIN at input frequency fi = 5 MHz; fo = 6.67 MHz −6 − −1 dB AYpre pre filter stop-band characteristic, damping factor for input signals fi > 10 MHz 20 − − dB fi > 20 MHz 32 − − dB fi > 100 MHz 42 − − dB fi > 14 MHz 20 − − dB fi > 20 MHz 32 − − dB fi > 100 MHz 40 − − dB AYpost post filter stop-band characteristic, damping factor for input signals (B−Y)OUT RO(U) output resistance − − 100 Ω VoU(p-p) output voltage (peak-to-peak value) − 1.33 2.1 V S/N signal-to-noise ratio 1.33 V (p-p)/Veff noise; unweighted; fi = 200 kHz to 5 MHz 54 − − dB FPN(p-p) fixed pattern noise peak-to-peak referenced to 1.33 V (p-p) video fclk < 5 MHz 42 − − dB αctU crosstalk between different inputs fi = 1 MHz 40 − − dB |td| delay between different outputs − − 30 ns td jitter in output signal to input HREF signal − − 10 ns Bypass not via the SC line memories GU1 frequency response fripple = 0 to 4 MHz −0.5 − +0.5 dB GU2 frequency response attenuation at 5 MHz compared to 1 MHz 0 − −2 dB Bypass via the SC line memories; note 2 GU3 (B−Y)OUT/(B−Y)IN at input frequency fi = 1 MHz −1.1 − +0.9 dB GU4 (B−Y)OUT/(B−Y)IN at input frequency fi = 2 MHz −1.3 − +0.7 dB GU5 (B−Y)OUT/(B−Y)IN at input frequency fi = 3 MHz −1.7 − +0.3 dB GU6 (B−Y)OUT/(B−Y)IN at input frequency fi = 4 MHz −2.3 − −0.3 dB GU7 (B−Y)OUT/(B−Y)IN at input frequency fi = 5 MHz −3.1 − −1.1 dB 1995 Oct 05 11 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SYMBOL PARAMETER SAA4981 CONDITIONS MIN. TYP. MAX. UNIT Compressed video; note 2 GU8 (B−Y)OUT/(B−Y)IN at input frequency fi = 1 MHz; fo = 1.3 MHz −1 − +1 dB GU9 (B−Y)OUT/(B−Y)IN at input frequency fi = 2 MHz; fo = 2.7 MHz −1 − +1 dB GU10 (B−Y)OUT/(B−Y)IN at input frequency fi = 3 MHz; fo = 4 MHz −2 − 0 dB GU11 (B−Y)OUT/(B−Y)IN at input frequency fi = 3.75 MHz; fo = 5 MHz −3 − −1 dB GU12 (B−Y)OUT/(B−Y)IN at input frequency fi = 4 MHz; fo = 5.3 MHz −4 − −1 dB GU13 (B−Y)OUT/(B−Y)IN at input frequency fi = 5 MHz; fo = 6.67 MHz −6 − −1 dB AUpre pre filter stop-band characteristic, damping factor for input signals fi > 10 MHz 20 − − dB fi > 20 MHz 32 − − dB fi > 100 MHz 42 − − dB fi > 14 MHz 20 − − dB fi > 20 MHz 32 − − dB fi > 100 MHz 40 − − dB AUpost post filter stop-band characteristic, damping factor for input signals (R−Y)OUT RO(V) output resistance − − 100 Ω VoV output voltage (peak-to-peak value) − 1.05 1.7 V S/N signal-to-noise ratio 1.05 V (p-p)/Veff noise; unweighted; fi = 200 kHz to 5 MHz 52 − − dB FPN(p-p) fixed pattern noise peak-to-peak referenced to 1.05 V (p-p) video fclock < 5 MHz 40 − − dB αctV crosstalk between different inputs fi = 1 MHz 40 − − dB |td| delay between different outputs − − 30 ns td jitter in output signal to input HREF signal − − 10 ns Bypass not via the SC line memories GV1 frequency response fripple = 0 to 4 MHz −0.5 − +0.5 dB GV2 frequency response attenuation at 5 MHz compared to 1 MHz 0 − −2 dB Bypass via the SC line memories; note 2 GV3 (R−Y)OUT/(R−Y)IN at input frequency fi = 1 MHz −1.1 − +0.9 dB GV4 (R−Y)OUT/(R−Y)IN at input frequency fi = 2 MHz −1.3 − +0.7 dB GV5 (R−Y)OUT/(R−Y)IN at input frequency fi = 3 MHz −1.7 − +0.3 dB GV6 (R−Y)OUT/(R−Y)IN at input frequency fi = 4 MHz −2.3 − −0.3 dB GV7 (R−Y)OUT/(R−Y)IN at input frequency fi = 5 MHz −3.1 − −1.1 dB 1995 Oct 05 12 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SYMBOL PARAMETER SAA4981 CONDITIONS MIN. TYP. MAX. UNIT Compressed video; note 2 GV8 (R−Y)OUT/(R−Y)IN at input frequency fi = 1 MHz; fo = 1.3 MHz −1 − +1 dB GV9 (R−Y)OUT/(R−Y)IN at input frequency fi = 2 MHz; fo = 2.7 MHz −1 − +1 dB GV10 (R−Y)OUT/(R−Y)IN at input frequency fi = 3 MHz; fo = 4 MHz −2 − 0 dB GV11 (R−Y)OUT/(R−Y)IN at input frequency fi = 3.75 MHz; fo = 5 MHz −3 − −1 dB GV12 (R−Y)OUT/(R−Y)IN at input frequency fi = 4 MHz; fo = 5.3 MHz −4 − −1 dB GV13 (R−Y)OUT/(R−Y)IN at input frequency fi = 5 MHz; fo = 6.67 MHz −6 − −1 dB AVpre pre filter stop-band characteristic, damping factor for input signals fi > 10 MHz 20 − − dB fi > 20 MHz 32 − − dB fi > 100 MHz 42 − − dB fi > 14 MHz 20 − − dB fi > 20 MHz 32 − − dB fi > 100 MHz 40 − − dB AVpost post filter stop-band characteristic, damping factor for input signals Video outputs YOUT, (B−Y)OUT and (R−Y)OUT RATIO OF OUTPUT AMPLITUDES FOR EQUAL INPUT SIGNALS FOR Y, (B−Y) AND (R−Y) VoY/VoU YOUT/(B−Y)OUT VI = 0.32 V (p-p); fi ≤ 1 MHz −0.4 − +0.4 dB VoY/VoV YOUT/(R−Y)OUT VI = 0.32 V (p-p); fi ≤ 1 MHz −0.4 − +0.4 dB VoU/VoV (B−Y)OUT/(R−Y)OUT VI = 1.33 V (p-p) −0.4 − +0.4 dB Notes 1. ∆V1 = VCCA − VCCD ≤ 300 mV; ∆V2 = VEED − VEEA ≤ 300 mV with VEED = SUB (latch-up prevention). 2. This frequency response includes the si-attenuation as a result of the time discrete signal processing. An si-correction is not performed. 1995 Oct 05 13 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SAA4981 APPLICATION INFORMATION +5V ook, full pagewidth 47 µF 10 nF 47 µF ferrit pearl VEEA video signal inputs VEEA 100 nF video signal outputs 10 nF 47 µF 2.2 Ω CLAOUT (1) 2.2 nF 24 2.2 nF 23 2.2 nF 22 10 nF 21 20 19 18 17 16 15 14 13 8 9 10 11 12 SAA4981 1 100 nF 2 100 nF 3 100 nF 4 5 6 7 2.2 Ω (2) VEED 10 nF VEED VEEA VEEA VEEA VEED 15 Ω line reference input 5.6 Ω 10 nF control inputs see Table 1 ferrit pearl clamp reference voltage output 47 µF VEEA +5V MHA280 (1) Connected to CLAOUT for black side panels. (2) Substrate (pin 4) has to be connected to VEED. VEEA and VEED. Substrates have to be separated as much as possible. Fig.5 Application diagram. 1995 Oct 05 14 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SAA4981 PACKAGE OUTLINES seating plane DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1 ME D A2 L A A1 c e Z b1 w M (e 1) b MH 13 24 pin 1 index E 1 12 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.1 0.51 4.0 1.7 1.3 0.53 0.38 0.32 0.23 32.0 31.4 14.1 13.7 2.54 15.24 3.9 3.4 15.80 15.24 17.15 15.90 0.25 2.2 inches 0.20 0.020 0.16 0.066 0.051 0.021 0.015 0.013 0.009 1.26 1.24 0.56 0.54 0.10 0.60 0.15 0.13 0.62 0.60 0.68 0.63 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT101-1 051G02 MO-015AD 1995 Oct 05 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-23 15 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SAA4981 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 inches 0.10 Z (1) θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013AD 1995 Oct 05 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 16 o 8 0o Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1995 Oct 05 SAA4981 17 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor SAA4981 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Oct 05 18 Philips Semiconductors Preliminary specification Monolithic integrated 16 : 9 compressor NOTES 1995 Oct 05 19 SAA4981 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 533061/1500/02/pp20 Document order number: Date of release: 1995 Oct 05 9397 750 00346