3D7105 data 3 delay devices, inc. MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7105) FEATURES • • • • • • • • • • • • PACKAGES IN 1 8 VDD All-silicon, low-power CMOS VDD IN 1 8 O2 2 7 O1 technology O4 3 6 O3 O1 O2 2 7 GND 4 5 O5 TTL/CMOS compatible O3 O4 3 6 inputs and outputs 3D7105Z O5 GND 4 5 SOIC Vapor phase, IR and wave (150 Mil) solderable 3D7105M DIP Auto-insertable (DIP pkg.) 3D7105H Gull-Wing (300 Mil) Low ground bounce noise Leading- and trailing-edge accuracy IN 1 16 VDD Delay range: .75 through 80ns N/C 2 15 N/C Delay tolerance: 5% or 1ns N/C 3 14 N/C O2 4 13 O1 Temperature stability: ±3% typical (0C-70C) N/C 5 12 N/C O4 6 11 O3 Vdd stability: ±1% typical (4.75V-5.25V) N/C 7 10 N/C GND 8 9 O5 Minimum input pulse width: 30% of total delay 14-pin DIP and 16-pin SOIC available as drop-in 3D7105S SOIC replacements for hybrid delay lines (300 Mil) IN 1 14 VDD N/C 2 13 N/C N/C 3 12 O1 O2 4 11 N/C N/C 5 10 O3 O4 6 9 N/C GND 7 8 O5 3D7105 DIP 3D7105G Gull-Wing 3D7105K Unused pins removed (300 Mil) FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS The 3D7105 5-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 8.0ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7105 is TTL- and CMOScompatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy. IN O1 O2 O3 O4 O5 VCC GND N/C Delay Line Input Tap 1 Output (20%) Tap 2 Output (40%) Tap 3 Output (60%) Tap 4 Output (80%) Tap 5 Output (100%) +5 Volts Ground No Connection The all-CMOS 3D7105 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC. TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER DIP-8 3D7105M 3D7105H SOIC-8 3D7105Z DIP-14 3D7105 3D7105G 3D7105K TOLERANCES SOIC-16 3D7105S TOTAL DELAY (ns) TAP-TAP DELAY (ns) INPUT RESTRICTIONS Max Operating Frequency -.75 -.75 -.75 -.75 41.7 MHz 3.0 ± 1.0* 0.75 ± 0.4 -1 -1 -1 -1 37.0 MHz 4.0 ± 1.0* 1.0 ± 0.5 -1.5 -1.5 -1.5 -1.5 30.3 MHz 6.0 ± 1.0* 1.5 ± 0.7 -2 -2 -2 -2 25.6 MHz 8.0 ± 1.0* 2.0 ± 0.8 -2.5 -2.5 -2.5 -2.5 22.2 MHz 10.0 ± 1.0* 2.5 ± 1.0 -4 -4 -4 -4 15.9 MHz 16.0 ± 1.0* 4.0 ± 1.3 -5 -5 -5 -5 13.3 MHz 25.0 ± 1.3 5.0 ± 1.5 -8 -8 -8 -8 9.52 MHz 40.0 ± 2.0 8.0 ± 1.5 * Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ± 1.0ns NOTE: Any dash number between .75 and 8 not shown is also available. Doc #96006 12/2/96 DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 Absolute Max Oper. Freq. 166.7 MHz 166.7 MHz 166.7 MHz 166.7 MHz 133.3 MHz 83.3 MHz 66.7 MHz 41.7 MHz Min Operating Pulse Width 12.0 ns 13.5 ns 16.5 ns 19.5 ns 22.5 ns 31.5 ns 37.5 ns 52.5 ns Absolute Min Oper. P.W. 3.00 ns 3.00 ns 3.00 ns 3.00 ns 3.75 ns 6.00 ns 7.50 ns 12.0 ns 1996 Data Delay Devices 1 3D7105 APPLICATION NOTES To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7105 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. OPERATIONAL DESCRIPTION The 3D7105 five-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-totap delay deviations over temperature and supply voltage variations. INPUT SIGNAL CHARACTERISTICS The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified. OPERATING PULSE WIDTH The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. OPERATING FREQUENCY The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed. The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D7105 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. IN O1 O2 25% O3 25% O4 25% O5 25% IN O1 20% O2 20% Temp & VDD Compensation O3 20% O4 20% O5 20% Temp & VDD Compensation Dash numbers < 5 Dash numbers >= 5 VDD GND VDD GND Figure 1: 3D7105 Functional Diagram Doc #96006 12/2/96 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 3D7105 APPLICATION NOTES (CONT’D) custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted. POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D7105 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. The thermal coefficient is reduced to 600 PPM/C, which is equivalent to a variation , over the 0C-70C operating range, of ±3% from the room-temperature delay settings and/or 1.0ns, whichever is greater. The power supply coefficient is reduced, over the 4.75V-5.25V operating range, to ±1% of the delay settings at the nominal 5.0VDC power supply and/or 1.5ns, whichever is greater. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. DEVICE SPECIFICATIONS TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Input Pin Current Storage Temperature Lead Temperature SYMBOL VDD VIN IIN TSTRG TLEAD MIN -0.3 -0.3 -1.0 -55 MAX 7.0 VDD+0.3 1.0 150 300 UNITS V V mA C C NOTES 25C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Current SYMBOL IDD VIH VIL IIH IIL IOH MIN -4.0 UNITS mA V V µA µA mA Low Level Output Current IOL 4.0 mA Output Rise & Fall Time T R & TF *IDD(Dynamic) = 5 * CLD * VDD * F where: CLD = Average capacitance load/tap (pf) F = Input frequency (GHz) Doc #96006 12/2/96 MAX 30 2.0 0.8 1 1 2 ns NOTES VIH = VDD VIL = 0V VDD = 4.75V VOH = 2.4V VDD = 4.75V VOL = 0.4V CLD = 5 pf Input Capacitance = 10 pf typical Output Load Capacitance (CLD) = 25 pf max DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 3D7105 SILICON DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (Vcc): 5.0V ± 0.1V Input Pulse: High = 3.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1.25 x Total Delay Period: PERIN = 2.5 x Total Delay OUTPUT: Rload: Cload: Threshold: Device Under Test 10KΩ ± 10% 5pf ± 10% 1.5V (Rising & Falling) Digital Scope 10KΩ 5pf 470Ω NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM PULSE GENERATOR OUT TRIG IN DEVICE UNDER TEST (DUT) REF OUT1 OUT2 OUT3 OUT4 OUT5 IN TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER Figure 2: Test Setup PERIN PWIN tRISE INPUT SIGNAL tFALL VIH 2.4V 1.5V 0.6V 2.4V 1.5V 0.6V tPLH OUTPUT SIGNAL VIL tPHL VOH 1.5V 1.5V VOL Figure 3: Timing Diagram Doc #96006 12/2/96 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4