PDU108H
data 3
delay
devices, inc.
3-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU108H)
FEATURES
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PACKAGES
Digitally programmable in 8 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced & buffered
Fits standard 16-pin DIP socket
GND
1
16
GND
ENB
2
15
OUT
IN
6
A0
7
10
A1
VEE
8
9
A2
PDU108H-xx DIP
PDU108H-xxM Military DIP
GND
ENB
N/C
N/C
N/C
IN
A0
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OUT
N/C
N/C
N/C
N/C
A1
A2
PDU108H-xxC3 SMD
PDU108H-xxMC3 Mil SMD
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU108H-series device is a 3-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on
the address code (A2-A0) according to the following formula:
IN
OUT
A2
A1
A0
ENB
VEE
GND
TDA = TD0 + TINC * A
Signal Input
Signal Output
Address Bit 2
Address Bit 1
Address Bit 0
Output Enable
-5 Volts
Ground
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns
through 50ns, inclusively. The enable pin (ENB) is held LOW during
normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not
latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
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DASH NUMBER SPECIFICATIONS
Total programmed delay tolerance: 5% or 1ns,
whichever is greater
Inherent delay (TD0): 2.8ns typical
Setup time and propagation delay:
Address to input setup (TAIS):
3.6ns
Disable to output delay (TDISO): 1.7ns typical
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VEE: -5VDC ± 5%
Power Dissipation: 290mw typical (no load)
Minimum pulse width: 25% of total delay
Part
Number
PDU108H-.5
PDU108H-1
PDU108H-2
PDU108H-3
PDU108H-5
PDU108H-10
PDU108H-20
PDU108H-40
PDU108H-50
Incremental Delay
Per Step (ns)
0.5 ± 0.3
1.0 ± 0.4
2.0 ± 0.4
3.0 ± 0.5
5.0 ± 0.6
10.0 ± 1.0
20.0 ± 1.5
40.0 ± 2.0
50.0 ± 2.5
Total
Delay (ns)
3.5 ± 1.0
7.0 ± 1.0
14 ± 1.0
21 ± 1.0
35 ± 1.7
70 ± 3.5
140 ± 7.0
280 ± 14.0
350 ± 17.5
NOTE: Any dash number between .5 and 50
not shown is also available.
2001 Data Delay Devices
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU108H
APPLICATION NOTES
spurious signals persists until the required TDISH
has elapsed.
ADDRESS UPDATE
The PDU108H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay tolerance
specifications and monotonicity are guaranteed.
The suggested conditions are those for which
signals will propagate through the unit without
significant distortion. The absolute conditions
are those for which the unit will produce some
type of output for a given input.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, TOAX,
is required before the address lines can change.
This time is given by the following relation:
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT pin.
The possibility of spurious signals persists until
the required TOAX has elapsed.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will remain
constant from pulse to pulse if the input pulse
width and period remain fixed. In other words,
the delay of the unit exhibits frequency and pulse
width dependence when operated beyond the
recommended conditions. Please consult the
technical staff at Data Delay Devices if your
application has specific high-frequency
requirements.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
TDISH = Ai * TINC
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
A2-A0
A i-1
Ai
TOAX
TAENS
TAIS
ENB
TENIS
PWIN
TDISH
IN
TDA
PWOUT
TDISO
OUT
Figure 1: Timing Diagram
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
PDU108H
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
Absolute
Input Period
Suggested
Recommended
Absolute
Input Pulse Width
Suggested
Recommended
SYMBOL
TDT
TD0
TDISO
TAENS
TAIS
TENIS
TOAX
TDISH
PERIN
PERIN
PERIN
PWIN
PWIN
PWIN
MIN
TYP
7
2.8
1.7
UNITS
TINC
ns
ns
ns
ns
ns
1.0
3.6
3.6
See Text
See Text
20
50
200
10
25
100
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VEE
VIN
TSTRG
TLEAD
MIN
-7.0
VEE - 0.3
-55
MAX
0.3
0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 75C)
PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Doc #97043
10/1/01
SYMBOL
VOH
VOL
VIH
VIL
IIH
IIL
MIN
TYP
-0.960
-1.650
-0.980
-1.650
10
-20
MAX
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
UNITS
V
V
V
V
mA
mA
NOTES
VIH = MAX,50Ω to -2V
VIL = MIN, 50Ω to -2V
VIH = MAX
VIL = MIN
3
PDU108H
PACKAGE DIMENSIONS
16 15
10
9
.400
TYP.
1 2
6
7
8
.800 TYP.
.020 .320
TYP. MAX.
.150
±.030
.100
TYP.
.018
TYP.
.010 TYP.
.300
TYP.
.700 TYP.
PDU108H-xx (Commercial DIP)
PDU108H-xxM (Military DIP)
.020 TYP.
.040
TYP.
16 15 14 13 12 11 10
.010±.002
9
.882
±.005
.710 .590
±.005 MAX.
1
2
3
4
5
.090
6
7
.007
±.005
8
.100
.320
MAX.
.700
.880±.020
.050
±.010
PDU108H-xxC3 (Commercial SMD)
PDU108H-xxMC3 (Military SMD)
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
4
PDU108H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
o
o
Ambient Temperature: 25 C ± 3 C
Supply Voltage (Vcc): -5.0V ± 0.1V
Input Pulse:
Standard 10KH ECL
levels
Source Impedance:
50Ω Max.
Rise/Fall Time:
2.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
PWIN = 1.5 x Total Delay
Period:
PERIN = 10 x Total Delay
OUTPUT:
Load:
Cload:
Threshold:
50Ω to -2V
5pf ± 10%
(VOH + VOL) / 2
(Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
REF
PULSE
GENERATOR
OUT
IN
TRIG
DEVICE UNDER
TEST (DUT)
OUT
IN
OSCILLOSCOPE
TRIG
ADDRESS SELECT
Test Setup
PERIN
PWIN
TRISE
INPUT
SIGNAL
TFALL
VIH
80%
50%
20%
80%
50%
20%
DRISE
OUTPUT
SIGNAL
VIL
DFALL
VOH
50%
50%
VOL
Timing Diagram For Testing
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5