PDU53
data 3
delay
devices, inc.
3-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU53)
FEATURES
•
•
•
•
•
PACKAGES
Digitally programmable in 8 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 100K-ECL interfaced & buffered
Available in 16-pin DIP (600 mil) socket or SMD
N/C
N/C
GND
OUT
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
16
15
IN
A2
14
13
A1
VEE
12
11
A0
N/C
10
9
N/C
N/C
PDU53-xx DIP
PDU53-xxM Military DIP
N/C
N/C
GND
OUT
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
A2
A1
VEE
A0
N/C
N/C
N/C
PDU53-xxC3 SMD
PDU53-xxMC3 Mil SMD
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU53-series device is a 3-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends
on the address code (A2-A0) according to the following formula:
IN
OUT
A2
A1
A0
VEE
GND
TDA = TD0 + TINC * A
Signal Input
Signal Output
Address Bit 2
Address Bit 1
Address Bit 0
-5 Volts
Ground
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The
address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
•
Part
Number
PDU53-100
PDU53-200
PDU53-250
PDU53-400
PDU53-500
PDU53-750
PDU53-1000
PDU53-1200
PDU53-1500
PDU53-2000
PDU53-2500
PDU53-3000
•
•
•
•
•
•
•
•
Total programmed delay tolerance: 5% or 40ps,
whichever is greater
Inherent delay (TD0): 2.2ns typical
Address to input setup (TAIS): 2.9ns
Operating temperature: 0° to 85° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VEE: -5VDC ± 0.7V
Power Supply Current: -150ma typical (50Ω to -2V)
Minimum pulse width: 3ns or 15% of total delay,
whichever is greater
Minimum period: 8ns or 2 x pulse width, whichever
is greater
A2-A0
A i-1
PWIN
Ai
TOAX
Incremental Delay
Per Step (ps)
100 ± 50
200 ± 60
250 ± 60
400 ± 80
500 ± 100
750 ± 100
1000 ± 200
1200 ± 200
1500 ± 200
2000 ± 400
2500 ± 400
3000 ± 500
Total Delay
Change (ns)
0.70
1.40
1.75
2.80
3.50
5.25
7.00
8.40
10.50
14.00
17.50
21.00
NOTE: Any dash number between 100 and 3000
not shown is also available.
TAIS
IN
TDA
PW OUT
OUT
Figure 1: Timing Diagram
1997 Data Delay Devices
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DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU53
APPLICATION NOTES
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
ADDRESS UPDATE
The PDU53 is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
TOAX, is required before the address lines can
change. This time is given by the following
relation:
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required TOAX has elapsed.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
PACKAGE DIMENSIONS
16 15 14 13 12 11 10
9
.600
±.005
.580
MAX.
.010
±.002
1
2
3
4
5
6
7
8
.870±.010
.380
MAX.
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
.015 TYP.
.018
TYP.
.070 MAX.
.700±.010
7 Equal spaces
each .100±.010
Non-Accumulative
PDU53-xx (Commercial DIP)
PDU53-xxM (Military DIP)
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DATA DELAY DEVICES, INC.
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2
PDU53
PACKAGE DIMENSIONS (cont’d)
.020 TYP.
.040
TYP.
16 15 14 13 12 11 10
.010±.002
9
.882
±.005
.710 .590
±.005 MAX.
1
2
3
4
5
6
.090
7
.007
±.005
8
.100
.280
MAX.
.700
.880±.020
.050
±.010
PDU53-xxC3 (Commercial SMD)
PDU53-xxMC3 (Military SMD)
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
Address to Input Setup Time
Output to Address Change
Absolute
Input Period
Suggested
Recommended
Absolute
Input Pulse Width
Suggested
Recommended
SYMBOL
TDT
TD0
TAIS
TOAX
PERIN
PERIN
PERIN
PWIN
PWIN
PWIN
MIN
TYP
7
2.2
2.9
See Text
30
50
200
15
25
100
UNITS
TINC
ns
ns
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VEE
VIN
TSTRG
TLEAD
MIN
-7.0
VEE - 0.3
-65
MAX
0.3
0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 85C)
PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
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SYMBOL
VOH
VOL
VIH
VIL
IIH
IIL
MIN
-1.025
-1.810
-1.165
-1.810
0.5
MAX
-0.880
-1.620
-0.880
-1.475
340
UNITS
V
V
V
V
µA
µA
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
NOTES
VIH = MAX,50Ω to -2V
VIL = MIN, 50Ω to -2V
VIH = MAX
VIL = MIN
3
PDU53
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): -4.5V ± 0.1V
Input Pulse:
Standard 100K ECL
levels
Source Impedance:
50Ω Max.
Rise/Fall Time:
1.0 ns Max. (measured
between 20% and 80%)
Pulse Width:
PWIN = 10ns
Period:
PERIN = 100ns
OUTPUT:
Load:
Cload:
Threshold:
50Ω to -2V
5pf ± 10%
(VOH + VOL) / 2
(Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
REF
PULSE
GENERATOR
OUT
IN
TRIG
DEVICE UNDER
TEST (DUT)
OUT
IN
OSCILLOSCOPE
TRIG
ADDRESS SELECT
Test Setup
PERIN
PWIN
TRISE
INPUT
SIGNAL
TFALL
VIH
80%
50%
20%
80%
50%
20%
TRISE
OUTPUT
SIGNAL
VIL
TFALL
VOH
50%
50%
VOL
Timing Diagram For Testing
Doc #98003
Powered
3/18/98
by ICminer.com
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672
Electronic-Library Service CopyRight 2003
http://www.datadelay.com
4