DCD DFPADD

DFPADD
Floating Point Pipelined Adder Unit
ver 2.50
OVERVIEW
The DFPADD uses the pipelined mathematics algorithm to compute sum of two arguments. The input numbers format is according to IEEE-754 standard. DFPADD supports
single precision real number. Add operation
was pipelined up to 5 levels. Input data are
fed every clock cycle. The first result appears
after 5 clock periods latency and next results
are available each clock cycle. Full IEEE754 precision and accuracy were included.
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DELIVERABLES
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Math coprocessors
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DSP algorithms
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Embedded arithmetic coprocessor
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Data processing & control
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KEY FEATURES
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Full IEEE-754 compliance
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Single precision real format support
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Simple interface
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No programming required
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5 levels pipeline
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Full accuracy and precision
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Results available at every clock
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Overflow, underflow and invalid operation
flags
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Fully configurable
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are trademarks of their respective owners.
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ NCSim automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
Synthesis scripts
Example application
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
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APPLICATION
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Fully synthesizable, static synchronous
design with no internal tri-states
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Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implemenhttp://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
tation. It also permits FPGA prototyping before ASIC production.
Unlimited Designs license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
BLOCK DIAGRAM
adatai(31:0)
Arguments
Checker
bdatai(31:0)
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
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Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
●
Unlimited Designs license for
○ HDL Source
○ Netlist
●
Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
SYMBOL
adatai(31:0)
datao(31:0)
bdatai(31:0)
ofo
ufo
ifo
en
rst
clk
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
Input
Global system clock
rst
Input
Global system reset
en
Input
Enable computing
adatai[31:0]
Input
A data bus input
bdatai[31:0]
Input
B data bus input
datao[31:0]
Output Data bus output
ofo
Output Overflow flag
ufo
Output Underflow flag
ifo
Output Invalid result flag
All trademarks mentioned in this document
are trademarks of their respective owners.
Main FP
Pipelined Unit
Result
Composer
datao(31:0)
ofo
ufo
ifo
en
rst
clk
Arguments Checker - performs input data
analyze against IEEE-754 number standard
compliance. The appropriate numbers and
information about the input data classes are
given as the results to Main FP Pipelined
Unit.
Main FP Pipelined Unit - performs floating
point add function. Gives the complex information about the results and makes final
flags settings.
Result Composer - performs result rounding
function, data alignment to IEEE-754 standard, and the final flags setting.
PERFORMANCE
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route :
Speed
Logic Cells
Fmax
grade
FLEX10KE
-1
1110
47 MHz
ACEX1K
-1
1110
47 MHz
APEX20K
-1
955
55 MHz
APEX20KE
-1
955
52 MHz
APEX20KC
-7
955
68 MHz
APEX-II
-7
955
88 MHz
MERCURY
-5
975
117 MHz
STRATIX
-5
845
107 MHz
CYCLONE
-6
845
104 MHz
STRATIX-II
-3
690
153 MHz
CYCLONE-II
-6
845
105 MHz
Core performance in ALTERA® devices
Device
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
CONTACTS
For any modification or special request
please contact to Digital Core Design or local
distributors.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
[email protected]
e-mail: [email protected]
tel.
: +48 32 282 82 66
fax
: +48 32 282 74 37
Distributors:
ttp://www.dcd.pl/apartn.php
Please check hhttp://www.dcd.pl/apartn.php
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.