DCD DINT2FP

DINT2FP
Integer to Floating Point Pipelined Converter
ver 2.32
OVERVIEW
The DINT2FP is the pipelined integer to
floating point converter. The input and output
numbers format is according to IEEE-754
standard. DINT2FP supports double word
integers (4 Bytes) and single precision real
numbers. Convert operation is pipelined to 3
levels. Input data are fed every clock cycle.
The first result appears after latency equal to
3 clock periods and next results are available
each clock cycle. Full precision and accuracy are accomplished.
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DELIVERABLES
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Math coprocessors
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DSP algorithms
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Embedded arithmetic coprocessor
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Data processing & control
KEY FEATURES
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Full IEEE-754 compliance
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Double word integer input numbers (4
Bytes)
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Single precision real output numbers
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Simple interface
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No programming required
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3 levels pipelining
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Full accuracy and precision
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Results available at every clock
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Fully configurable
All trademarks mentioned in this document
are trademarks of their respective owners.
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ NCSim automatic simulation macros
◊ Tests with reference responses
Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
Synthesis scripts
Example application
Technical support
◊ IP Core implementation support
◊ 3 months maintenance
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◊
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APPLICATION
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Fully synthesizable, static synchronous
design with no internal tri-states
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Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implemenhttp://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
tation. It also permits FPGA prototyping before ASIC production.
Unlimited Designs license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
●
Single Design license for
○ VHDL, Verilog source code called HDL
Source
○ Encrypted, or plain text EDIF called Netlist
●
Unlimited Designs license for
○ HDL Source
○ Netlist
●
Upgrade from
○ Netlist to HDL Source
○ Single Design to Unlimited Designs
SYMBOL
datai(31:0)
datao(31:0)
en
rst
clk
TYPE
DESCRIPTION
clk
Input
Global system clock
rst
Input
Global system reset
en
Input
Enable computing
datai[31:0]
Input
Data bus input
datao[31:0]
Argument
Checker
datai(31:0)
Main FP
Pipelined Unit
Result
Composer
datao(31:0)
en
rst
clk
Arguments Checker - performs input data
analyze against IEEE-754 number standard
compliance. The appropriate numbers and
information about the input data classes are
given as the results to Main FP Pipelined
Unit.
Main FP Pipelined Unit - performs integer to
floating point conversion. Gives the complex
information about the results to Result Composer module.
Result Composer - performs result rounding
function, and data alignment to IEEE-754
standard.
PERFORMANCE
PINS DESCRIPTION
PIN
BLOCK DIAGRAM
Output Data bus output
All trademarks mentioned in this document
are trademarks of their respective owners.
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route :
Speed
Logic Cells
Fmax
grade
FLEX10KE
-1
570
83 MHz
ACEX1K
-1
570
80 MHz
APEX20K
-1
470
61 MHz
APEX20KE
-1
470
73 MHz
APEX20KC
-7
470
87 MHz
APEX-II
-7
470
103 MHz
MERCURY
-5
570
157 MHz
STRATIX
-5
400
150 MHz
CYCLONE
-6
385
156 MHz
STRATIX-II
-3
330
234 MHz
CYCLONE-II
-6
410
149 MHz
Core performance in ALTERA® devices
Device
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.