TI SN74AUCH16374DGGR

SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
D
D
D
D
D
D
D
D
D
D
DGG OR DGV PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.8 ns at 1.8 V
Low Power Consumption, 20 µA Max ICC
±8-mA Output Drive at 1.8 V
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
description/ordering information
This 16-bit edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
The SN74AUCH16374 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two
8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the
flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
PACKAGE†
TA
–40°C to 85°C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel
SN74AUCH16374DGGR
AUCH16374
TVSOP – DGV
Tape and reel
SN74AUCH16374DGVR
MJ374
VFBGA – GQL
Tape and reel
SN74AUCH16374GQLR
MJ374
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
A
1OE
NC
NC
NC
NC
1CLK
B
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
1D4
1Q6
1Q5
VCC
GND
1D3
D
VCC
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
C
D
E
F
G
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
GND
2D6
2D5
2D8
2D7
NC
NC
2CLK
H
J
2Q7
2Q8
VCC
GND
J
K
2OE
NC
NC
K
NC – No internal connection
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
logic diagram (positive logic)
1OE
1CLK
1D1
1
2OE
48
47
2CLK
C1
2
1D
1Q1
24
25
C1
2D1
36
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
2
POST OFFICE BOX 655303
1D
• DALLAS, TEXAS 75265
13
2Q1
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
High-level output current
∆t/∆v
Low-level output current
0.8
2.7
VCC
0.65 × VCC
UNIT
V
V
1.7
0
0.35 × VCC
V
0.7
0
3.6
V
Active state
0
V
3-state
0
VCC
3.6
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
IOL
MAX
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
–3
–5
mA
–8
–9
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
V
–0.7
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
IBHL‡
IBHH§
IBHLO¶
All inputs
MIN
TYP†
MAX
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI = 0.35 V
±5
0 to 2.7 V
VI = 0.47 V
VI = 0.57 V
1.1 V
10
1.4 V
15
1.65 V
20
VI = 0.7 V
VI = 0.8 V
2.3 V
40
1.1 V
–5
VI = 0.9 V
VI = 1.07 V
1.4 V
–15
1.65 V
–20
VI = 1.7 V
2.3 V
–40
VI = 0 to VCC
IBHHO#
VI = 0 to VCC
Ioff
IOZ
VI or VO = 2.7 V
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
1.3 V
75
1.6 V
125
1.95 V
175
2.7 V
275
1.3 V
–75
1.6 V
–125
1.95 V
–175
2.7 V
–275
µA
µA
µA
µA
2.7 V
0.8 V to 2.7 V
2.5 V
V
µA
0
IO = 0
UNIT
VCC–0.1
3
±10
µA
±10
µA
20
µA
pF
Co
VO = VCC or GND
2.5 V
5
pF
† All typical values are at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V
TYP
MIN
VCC = 1.5 V
± 0.1 V
MAX
MIN
VCC = 1.8 V
± 0.15 V
MAX
250
MIN
MAX
250
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
85
250
250
MHz
Pulse duration, CLK high or low
5.9
1.9
1.9
1.9
1.9
ns
tsu
th
Setup time, data before CLK↑
1.4
1.2
0.7
0.6
0.6
ns
Hold time, data after CLK↑
0.1
0.4
0.4
0.4
0.4
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
TYP
MIN
85
250
fmax
VCC = 1.5 V
± 0.1 V
MAX
MIN
MAX
250
VCC = 1.8 V
± 0.15 V
MIN
TYP
VCC = 2.5 V
± 0.2 V
MAX
250
MIN
UNIT
MAX
250
MHz
tpd
CLK
Q
7.3
1
4.5
0.8
2.9
0.7
1.5
2.8
0.7
2.2
ns
ten
OE
Q
7
1.2
5.3
0.8
3.6
0.8
1.5
2.9
0.7
2.2
ns
tdis
OE
Q
8.2
2
7.1
1
4.8
1.4
2.7
4.5
0.5
2.2
ns
operating characteristics, TA = 25°C†
TEST
CONDITIONS
PARAMETER
Cpd‡
(each
output)
Power
dissipation
capacitance
Outputs
enabled,
1 output
switching
1 fdata = 5 MHz
1 fclk = 10 MHz
1 fout = 5 MHz
OE = GND
CL = 0 pF
VCC = 0.8 V
TYP
24
VCC = 1.2 V
TYP
24
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
24.1
26.2
31.2
pF
Outputs
disabled,
1 clock
and 1
data
switching
1 fdata = 5 MHz
1 fclk = 10 MHz
Power
Cpd
fout = not
dissipation
7.5
7.5
8
9.4
13.2
pF
switching
(Z)
capacitance
OE = VCC
CL = 0 pF
1 fdata = 0 MHz
Outputs
1 fclk = 10 MHz
Cpd§
disabled,
Power
fout = not
clock
dissipation
13.8
13.8
14
14.7
17.5
pF
(each
switching
clock) capacitance only
OE = VCC
switching
CL = 0 pF
† Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)}.
‡ Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz in this
test, but its ICC component has been subtracted out).
§ Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
CL
RL
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUCH16374DGGR
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74AUCH16374DGVR
ACTIVE
TVSOP
DGV
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74AUCH16374GQLR
ACTIVE
VFBGA
GQL
56
1000
None
SNPB
Level-1-240C-UNLIM
SN74AUCH16374ZQLR
ACTIVE
VFBGA
ZQL
56
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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