ESMT AD6255A Class-D Audio Power Amplifier with USB / I2S Interface and Recording function Features z Compliant with USB Specification v1.1, and USB 2.0 full speed z Embedded high efficiency, high performance class D stereo amplifier z Support I2S input and I2S output interface of master mode Sampling frequencies(Fs)：48kHz z +6dB enhancement(Theater function) z Support recording function z Support both bus-powered and self-powered operation z Supports Win Me//2000/XP and MacOS z True plug-and-play application, no driver is required for basic USB speaker application z Support volume/mute control with external button z Built-in 5V to 3.3V regulator for internal device operation z Total efficiency 80% for 8Ω load @ -1dB 1kHz sine wave input z Loudspeaker PSNR & DR (A-weighting) 80dB (PSNR), 78dB (DR) with Bead filter 82dB (PSNR), 78dB (DR) with Chock filter z Anti-pop design z Over-temperature protection z Under-voltage shutdown z Short-circuit detection z 12 MHz Crystal Input z 32-pin LQFP(Pb free) Description AD6255A is a single chip of Class-D audio amplifier with USB/I2S interface and supports recording function. When using the power supplied from the USB port, AD6255A can drive a pair of up to 1W speakers due to the built-in, high efficiency and high performance class D amplifiers. The device also has an I2S input port and I2S output port. The I2S input port allows other external audio sources to use the class D amplifier to share the speakers. The I2S output port allows other high performance audio device (i.e. AD8356A/AD8256A) to be controlled by AD6255A. Functional Block Diagram Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2007 Revision: 1.3 1/15 ESMT AD6255A Pin Assignment Pin Description Pin 1 Name MSDA Type I/O Description 2 I C’s SDA of Master mode Characteristics Schmitt trigger TTL input buffer 2 2 MSCL O I C’s SCL of master mode 3 PDO O Power-down output (Note1) 4 SDATAO O Serial audio output (Note1) 5 LRCIN O L/R clock output(Fs) (Note1) 6 BCLK O BCLK output(64xFs) (Note1) 7 SDATAI I Serial audio data input 8 MCLK O Master clock(256xFs) 9 GNDR P Ground for right channel 10 RB O Right channel output- 11 RA O Right channel output+ 12 VDDR P Supply for right channel 13 VDDL P Supply for left channel 14 LA O Left channel output+ 15 LB O Left channel output- Elite Semiconductor Memory Technology Inc. Schmitt trigger TTL input buffer Publication Date: Apr. 2007 Revision: 1.3 2/15 ESMT 16 GNDL AD6255A P Ground for left channel 17 2 USB/I S I Low is USB mode, high is I2S mode Schmitt trigger TTL input buffer 18 SEL1 I Mode selection bit 1 Schmitt trigger TTL input buffer 19 SEL0 I Mode selection bit 0 Schmitt trigger TTL input buffer 20 XO O Crystal output 21 XI I Crystal input 22 GND P Ground 23 REGO O 3.3V regulator output 24 VDD P 5V supply voltage 25 USBDM I/O USB data D- 26 USBDP I/O USB data D+ 27 THEATER I Theater mode, high active 28 VOLDN I Volume down, low active With internal pull-up resistor 29 VOLUP I Volume up, low active With internal pull-up resistor 30 MUTE I Power-down and mute of Class D 31 ERROR O Error output Open-Drain output 32 RESET I Reset signal Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer Note1: Must be strapped resistor 1MΩ to 3.3V(REGO) or GND. BCLK, LRCIN and PDO must be strapped to GND. SDATAO is strapped by 1MΩ to GND when AD6255A’s volume/mute is controlled by external button, otherwise strapped by 1MΩ to 3.3V when AD6255A is I2C slave mode for SEL1 is logic LOW. Absolute Maximum Ratings Symbol VDD VDDL(R) Vi Tstg Ta Parameter Supply for regulator input Supply for Left (Right) Channel Input Voltage Storage Temperature Ambient Operating Temperature Voltage Difference between VDDL and VDDR Voltage Difference between VDDL(VDDR) and DVDD/AVDD VDDL(VDDR) Power-on Voltage Ramp Min 0 0 -0.3 -65 0 -1 -3 Max 5.5 5.5 3.6 150 70 1 3 0.2 Units V V V o C o C V V V/μs Recommended Operating Conditions Symbol Parameter Typ Units VDD Supply for regulator input 4.5~5.5 V VDDL(R) Supply for Driver Stage 3.0~5.0 Ta Ambient Operating Temperature Elite Semiconductor Memory Technology Inc. 0~70 V o C Publication Date: Apr. 2007 Revision: 1.3 3/15