XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER FEBRUARY 2007 REV. 1.0.0 FUNCTIONAL DESCRIPTION all the outputs except synchronously disabled. The XRK4993 is a 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer. It is intended for high-performance computer systems and offers user selectable control over system clock functions to optimize timing. Eight ouputs, arranged in four banks, can each drive 75Ω terminated transmission lines while delivering minimal and specified output skews and full-swing Low Voltage TTL logic levels. QC0 and QC1 When PE is held high, all the outputs are synchronized with the positive edge of the CLKIN clock input. When PE is held low, all the outputs are synchronized with the negative edge of CLKIN. The device has LVTTL outputs with 12mA balanced drive. FEATURES • 3 pairs of programmable skew outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge Banks A, B, C (two outputs per bank) can be individually selected for one of nine delay or function configurations through two dedicated three-level inputs. These outputs are able to lead or lag the CLKIN input reference clock by up to 6 time units from their nominal "zero" skew position. The integrated PLL allows external load and transmission line delay effects to be canceled achieving zero delay capability. Combining the zero delay capability with the selectable output skew functions, output-to-output delays of up to +12 time units can be created. synchronization: Excellent for DSP applications • • • • • • • • • • • The XRK4993’s divide functions (divide-by-two and divide-by-four) allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature facilitates clock distribution while allowing maximum system clock flexibility. When the OE pin is held low, all the outputs are synchronously enabled. However, if OE is held high, Synchronous output enable Output frequency: 3.75MHz to 85MHz 2x, 4x, 1/2, and 1/4 output frequencies 3 skew grades 3-level inputs for skew and PLL range control PLL bypass mode External feedback, internal loop filter 12mA balanced drive outputs Available in 28 pin QSOP package Jitter < 200 ps peak-to-peak CLKIN input is 5V tolerant FIGURE 1. BLOCK DIAGRAM OF THE XRK4993 CLKIN Ref FB_IN H QA0 M QA1 L PLL QB0 Feedback Bank “SKEW” Control PE FSEL* PLL_BYPASS* QB1 QC0 QC1 2 2 2 SELA[1:0]* SELB[1:0]* SELC [1:0]* are QD0 QD1 OE * Three-level inputs Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 PRODUCT ORDERING INFORMATION PRODUCT NUMBER ACCURACY OPERATING TEMPERATURE RANGE XRK4993IR-2 250 ps -40°C to +85°C XRK4993CR-2 250 ps 0°C to +70°C XRK4993IR-5 500 ps -40°C to +85°C XRK4993CR-5 500 ps 0°C to +70°C XRK4993IR-7 750 ps -40°C to +85°C XRK4993CR-7 750 ps 0°C to +70°C FIGURE 2. PIN OUT OF THE XRK4993 CLKIN 1 28 GND VCCQ 2 27 PLL_BYPASS FSEL 3 26 SELB1 SELC0 4 25 SELB0 SELC1 5 24 OE PE 6 23 SELA1 VCCN 7 22 SELA0 QD1 8 21 VCCN QD0 9 20 QA0 GND 10 19 QA1 QC1 11 18 GND QC0 12 17 GND VCCN 13 16 QB0 FB_IN 14 15 QB1 QSOP Top View TABLE 1: FREQUENCY R ANGE SELECT AND tU CALCULATION [1] fNOM (MHZ) tU = 1 / (fNOM X N) APPROXIMATE FREQUENCY (MHZ) AT FSEL[2,3] MIN MAX LOW 15 35 44 22.7 MID 25 60 26 38.5 HIGH 40 85 16 62.5 2 WHERE N= WHICH tU = 1.0ns XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 PIN DESCRIPTIONS PIN NAME PIN # TYPE DESCRIPTION CLKIN 1 Input Reference Clock Input FB_IN 14 Input Feedback Input PLL_BYPASS 27 Threelevel Input When MID or HIGH, disables PLL (see Special Functions). CLKIN goes to all outputs. Skew Selections (see Control Summary Table) remain in effect. Set LOW for normal operations. OE 24 Input Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0]). QC[1:0] may be used as the feedback signal to maintain phase lock. Set OE LOW for normal operation. PE 6 Input Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the falling/rising edge of the reference clock. SELA0 SELA1 22 23 Threelevel Input SELB0 SELB1 25 26 Threelevel Input SELC0 SELC1 4 5 Threelevel Input FSEL 3 Threelevel Input Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.) QA0 QA1 20 19 Output Three output banks of two outputs with programmable skew (QA[1:0], QB[1:0], QC[1:0]). QD[1:0] outputs have fixed zero skew outputs. QB0 QB1 16 15 Output QC0 QC1 12 11 Output QD0 QD1 9 8 Output VCCN 7 13 21 PWR Power supply for output buffers. VCCQ 2 PWR Power supply for phase locked loop and other internal circuitry. GND 10 17 18 28 PWR Ground. 3-level inputs for selecting 1 of 9 skew taps or frequency functions. 3 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 SKEW SELECT CONTROL The skew select control consists of four independent sections. Each bank has two low-skew, high-fanout drivers (Qx0, Qx1), and two corresponding three-level function select (SELx0, SELx1) inputs. The nine possible output states for each bank as shown in Table 2 as determined by each bank’s select inputs. All timing measurements are made with respect to the CLKIN input assuming that the output connected to the FB_IN input configured for 0 tU operation. TABLE 2: PROGRAMMABLE SKEW CONFIGURATIONS [1] FUNCTION SELECTS OUTPUT FUNCTIONS SELX1 SELX0 QA[1:0], QB[1:0] QC[1:0] LOW LOW -4tU Divide by 2 LOW MID -3tU -6tU LOW HIGH -2tU -4tU MID LOW -1tU -2tU MID MID 0tU 0tU MID HIGH +1tU +2tU HIGH LOW +2tU +4tU HIGH MID +3tU +6tU HIGH HIGH +4tU Divide by 4 NOTES: 1. For all three-level (three-state) inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FSEL is determined by the “normal” operating frequency (fNOM) of the PLL. Nominal frequency (fNOM) always appears at QA0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN inputs will be fNOM when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication. 3. When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached 2.8V. 4. QD[1:0] fixed at zero skew. BYPASS MODE BYPASS mode allows the chip to be used in applications where the relative timing between outputs is maintained but the system clocking is interrupted or at a much lower frequency. An example might be "singlestepping" the system for diagnostics. The PLL_BYPASS pin is normally held at Ground (Low). To accommodate low frequency (below the PLL lock range) or infrequent pulses, the PLL_BYPASS, in conjunction with the FSEL pin (see Table 3) can be used to by-pass the PLL and generate an output sequence for the CLKIN signal. Relative timing as set by the SEL(x)1:0 for the various banks will be maintained. The relative timing includes plus and minus n tu and divide-by (2 or 4) settings. There will be a propagation delay as shown in Table 3. A tu will be approximately 2.5nS with PLL_BYPASS at Mid voltage and 0.4nS in the High state. 4 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 In the PLL_BYPASS mode the PE input can be used to invert the outputs. Thus, for a 20% (High) duty cycle input, all outputs will retain the 20% high condition with PE High. For PE Low, however, they will be 80% High. PE does not effect the duty cycle of the divided outputs. TABLE 3: TYPICAL PROPAGATION DELAY WITH ZERO SKEW SETTING PLL_BYPASS INPUT FSEL INPUT TOTAL PROPAGATION DELAY Mid Low or Mid 52nS High 29nS Low or Mid 12nS High 10nS High SPECIAL FUNCTIONS The following special functions have been implemented in the chip. PE pin: • In Normal operation, PE controls the "alignment" edge of the CLKIN and the FB-IN signals. (All other output signals are aligned to the Feedback). PE=Low, aligns the FB_IN faliing edge to the CLKIN falling edge. PE=High, aligns rising edges. • In the "disabled output mode (see below), the disabled state is forced to the opposite state of PE. This keeps the off condition in a low-noise state. • In PLL_BYPASS mode, PE controls the duty cycle (inversion) of the outputs (see PLL_BYPASS mode above). OE pin: • In Normal mode, OE is used to disable all outputs except QC[1,0]. These are maintained to provide PLL Feedback to keep frequency lock. OE is kept low to enable the outputs and High to disable them. This is a synchronized operation to prevent "partial" clocks When OE goes high, the outputs will go to their disabled level at the end of the next active clock cycle. The level is determined by the state of PE. If PE is high, the output will go low at the end of the cycle and remain there until OE return to a low state. If PE is low, at the end of the next clock high state it will continue to remain high until OE returns low. • If OE is high when PLL_BYPASS is at the Mid level, the PLL is enabled to provide an individual bank output control. In this mode, taking both SEL(x)1 & 0 to the Low state will disable that bank's outputs. FB_IN SELA[1:0] SELB[1:0] (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) CLKIN SELC[1:0] -6tU LM -4tU LH -3tU (N/A) -2tU ML -1tU (N/A) 0tU MM +1tU (N/A) +2tU MH +3tU (N/A) +4tU HL +6tU HM LL/HH DIVIDED 5 t0+6tU t0+5tU t0+4tU t0+3tU t0+2tU t0+1tU t0 t0-1tU t0-2tU t0-3tU t0-4tU t0-5tU t0-6tU FIGURE 3. TYPICAL OUTPUTS WITH FB_IN CONNECTED TO A ZERO-SKEW OUTPUT XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Storage Temperature –65°C to +150°C Ambient Temperature with Power Applied –55°C to +125°C Supply Voltage to Ground Potential –0.5V to +7.0V DC Input Voltage –0.5V to +7.0V Output Current into Outputs (LOW) 64 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) >2001V Latch-Up Current. >200 mA OPERATING RANGE RANGE AMBIENT TEMPERATURE VCC Industrial -40°C to +85°C 3.3 + 10% Commercial 0°C to +70°C 3.3 + 10% ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE SYMBOL DESCRIPTION VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage VIHH Three-Level Input HIGH Voltage M IN MAX 2.4 UNIT CONDITION V VCC = Min., IOH = -18mA 0.45 V VCC = Min., IOL = 35mA 2.0 VCC V CLKIN, FB_IN, PE, and OE -0.5 0.8 V 0.87*V CC VCC V Min. < V CC < Max. 0.47*V CC 0.53 * VCC V Min. < V CC < Max. 0.0 0.13 * VCC V Min. < V CC < Max. 20 μΑ VCC = Max., VIN = Max. μΑ VCC = Max., VIN = 0.4V 400 μΑ VIN = VCC 200 μA VIN = VCC/2 -400 μA VIN = GND (PLL_Bypass, FSEL, SELx[1:0]) [5] VIMM Three-Level Input MID Voltage (PLL_Bypass, FSEL, SELx[1:0]) [5] VILL Three-Level Input LOW Voltage (PLL_Bypass, FSEL, SELx[1:0]) [5] IIH Input HIGH Leakage Current (CLKIN and FB_IN inputs only) IIL Input LOW Leakage Current (CLKIN and FB_IN inputs only) IIHH Input HIGH Current (PLL_Bypass, FSEL, SELx[1:0]) IIMM Input MID Current (PLL_Bypass, FSEL, SELx[1:0]) IILL Input LOW Current PLL_Bypass, FSEL, SELx[1:0] -20 -200 6 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE DESCRIPTION SYMBOL M IN Short Circuit Current [6] IOS MAX UNIT -200 mA CONDITION VCC = Max, VOUT = GND (25°C only) ICCQ Operating Current Used by Internal Circuitry ICCN Com’l 95 Ind 100 Output Buffer Current per Output Pair 19 mA VCCN = VCCQ = Max., All Inputs Selects Open mA VCCN = VCCQ = Max., IOUT = 0 mA Inputs Selects Open, fMAX PD Power Dissipation per Output Pair 104 mW VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX CAPACITANCE[7] SYMBOL CIN D ESCRIPTION Input Capacitance MAX. UNIT 10 pF CONDITION TA = 25°C, f=1MHz, VCC=3.3V NOTES: 5. These inputs are normally wired to VCC, GND or left unconnected (actual threshold voltages vary as a percentage of V CC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an addtional tLOCK time before all data sheet limits are achieved. 6. XRK4993 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 7. Applies to CLKIN and FB_IN inputs only. 7 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 FIGURE 4. AC TEST LOAD VCC R1 CL R2 LOAD R1 = 150Ω R2 = 150Ω CL = 20pF (includes fixture and probe capacitance FIGURE 5. INPUT/OUTPUT TEST WAVEFORM 3.0V 2.0V 2.0V Vth = 1.5V Vth = 1.5V 0.8V 0.8V 0.0V <1ns <1ns SWITCHING CHARACTERISTICS OVER THE OPERATING RANGE [2,8] SYMBOL fNOM DESCRIPTION Operating Clock Frequency in MHz MIN M AX UNIT FSEL = LOW [1, 2] 15 35 MHz FSEL = MID [1, 2] 25 60 FSEL = HIGH [1, 2, 3] 40 85 8 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 SWITCHING CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE [2,8] XRK4993-2 SYMBOL XRK4993-5 XRK4993-7 DESCRIPTION UNIT MIN TYP MAX MIN TYP MAX M IN TYP MAX tRPWH CLKIN Pulse Width HIGH 4 4 4 ns tRPWL CLKIN Pulse Width LOW 4 4 4 ns tu Programmable Skew Unit tSKEWPR See Table 1 Zero Output Matched-Pair Skew 0.05 0.2 0.1 0.25 0.1 0.25 ns (Qx[1:0]) [10, 11] tSKEW0 Zero Output Skew (All Outputs) [10, 12] 0.1 0.25 0.25 0.5 0.3 0.75 ns tSKEW1 Output Skew (Rise-Rise, Fall-Fall, 0.25 0.5 0.6 0.7 0.6 1 ns Same Class Outputs)[10, 13] tSKEW2 Output Skew (Rise-Fall) [10, 13] 0.3 1 0.5 1 1 1.5 ns tSKEW3 Output Skew (Rise-Rise, Fall-Fall, 0.25 0.5 0.5 0.7 0.7 1.2 ns 0.5 0.9 0.5 1 1.2 1.7 ns 1.65 ns Different Class Outputs) [10, 13] tSKEW4 Output Skew (Nominal-Divided) [10, 13] tDEV Device-to-Device Skew [9, 14] tPD Propagation Delay, CLKIN Rise to FB_IN Rise tODCV Output Duty Cycle Variation [15] tPWH Output HIGH Time Deviation from 50% 0.75 1.25 -0.25 0 0.25 -0.5 0 0.5 -0.7 0 0.7 ns -1 0 1 -1 0 1 -1.2 0 1.2 ns 2 2.5 3 ns 1.5 3 3.5 ns [16] tPWL Output LOW Time Deviation from 50% [16] tORISE Output Rise Time [16, 17] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns tOFALL Output Fall Time [16, 17] 0.15 1 1.2 0.15 1 1.5 0.15 1.5 2.5 ns tLOCK PLL Lock Time [18] tJR Cycle-to-Cycle Output Jitter 0.5 0.5 0.5 ms RMS [9] 25 25 25 ps Peak-to-Peak 200 200 200 [9] NOTES: 8. Test measurement levels for the XRK4993 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 9. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 10. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75Ω to VCC/2 (XRK4993). 9 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 11. tSKEWPR is defined as the skew between a pair of outputs (Qx0 and Qx1) when all eight outputs are selected for 0tU. 12. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided, but not shifted. 13. There are two classes of outputs: Nominal (multiple of tU delay) and Divided (QC[1:0] or Divide-by-4 mode). 14. tDEV is the output-to-output skew between any two devices operating under the same conditions (V CC ambient temperature, air flow, etc.) 15. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 16. Specified with outputs loaded with 20pF for the XRK4993 devices. Devices are terminated through 75Ω to VCC/2. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 17. tORISE and tOFALL measured between 0.8V and 2.0V. 18. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits FIGURE 6. AC TIMING DIAGRAM (SHOWN WITH PE=HIGH) tREF tRPWH tRPWL CLKIN tPD tODCV tODCV FB_IN tJR Any Q tSKEWPR, tSKEW0, 1 tSKEWPR, tSKEW0, 1 OTHER Q tSKEW3, 4 tSKEW3, 4 tSKEW3, 4 CLKIN DIVIDED BY 2 tSKEW1, 3, 4 tSKEW2, 4 CLKIN DIVIDED BY 4 10 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 FIGURE 7. TIMING DIAGRAM PE=LOW Clkin FB_In Qxn QC div2 QC div4 PE = LOW TIMING: All output changes occur on the falling edge of the Clkin reference signal. Programmable skews are made relative to this edge. FIGURE 8. TIMING DIAGRAM PE=HIGH Clkin FB_In Qxn QC div2 QC div4 PE=HIGH TIMING: When the PE pin is High, all changes begin relative to the rising edge of the Clkin reference signal. This includes not only the "zero tu" signals but also the divided output signals. The divided-by-two outputs will change on each rising edge. As QD can only be 0tu, QC is the only "divide by" output providing either divideby- two or divide-by-four, not both. 11 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 PACKAGE DIMENSIONS 28 LEAD SHRINK SMALL OUTLINE PACKAGE ( QSOP 150 mils body) Rev. 1.00 D 28 15 E H 1 14 C A Seating Plane e α B A1 L SYMBOL A A1 B C D E e H L α MIN 0.053 0.004 0.008 0.006 0.380 0.144 0.0256 0.220 0.016 0° MAX 0.068 0.010 0.012 0.010 0.400 0.164 BSC 0.250 0.050 8° MIN MAX 1.35 1.73 0.10 0.25 0.20 0.30 0.15 0.25 9.65 10.16 3.66 4.17 0.65 BSC 5.59 6.35 0.54 1.27 0° 8° Note: The control dimension is the millimeter column 12 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 REVISION HISTORY REVISION # 1.0.0 DATE DESCRIPTION February 2007 Initial release. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet February 2007. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 13