EXAR XRT73R12IB

XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
JUNE 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XRT73R12 provides a Parallel Microprocessor
Interface for programming and control.
The XRT73R12 is a twelve channel fully integrated
Line Interface Unit (LIU) featuring EXAR’s R3
Technology (Reconfigurable, Relayless Redundancy)
for E3/DS3/STS-1 applications. The LIU incorporates
12 independent Receivers and Transmitters in a
single 420 Lead TBGA package.
Each channel of the XRT73R12 can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz).
Each transmitter can be turned off and tri-stated for
redundancy support or for conserving power.
The XRT73R12’s differential receiver provides high
noise interference margin and is able to receive data
over 1000 feet of cable or with up to 12 dB of cable
attenuation.
The XRT73R12 supports analog, remote and digital
loop-backs. The device also has a built-in Pseudo
Random Binary Sequence (PRBS) generator and
detector with the ability to insert and detect single bit
error for diagnostic purposes.
APPLICATIONS
• E3/DS3 Access Equipment
• DSLAMs
• Digital Cross Connect Systems
• CSU/DSU Equipment
• Routers
• Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 73R12
CS
RD
WR
Addr[7:0]
D[7:0]
PCLK
XRT73R12
CLKOUT_n
µProcessor Interface
SFM_en
RDY
RLOL_n
INT
Pmode
RESET
RTIP_n
RRing_n
AGC/
Equalizer
Slicer
TTIP_n
TRing_n
MTIP_n
MRing_n
DMO_n
ICT
Line
Driver
Device
Monitor
Clock & Data
Recovery
MUX
LOS
Detector
Local
LoopBack
E3Clk
DS3Clk
STS-Clk/12M
Clock
Synthesizer
Peak Detector
HDB3/
B3ZS
Decoder
RxClk_n
RxPOS_n
RxNEG/LCV_n
Remote
LoopBack
RLOS_n
Tx
Pulse
Shaping
Tx
Control
Timing
Control
MUX
HDB3/
B3ZS
Encoder
TxClk_n
TxPOS_n
TxNEG_n
TxON
Channel 0
Channel n...
Channel 11
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT73R12IB
420 Lead TBGA
-40°C to +85°C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FEATURES
• - 40°C to 85°C Industrial Temperature Range
RECEIVER
TRANSMIT INTERFACE CHARACTERISTICS
• R3
Technology
Redundancy)
(Reconfigurable,
• Accepts either Single-Rail or Dual-Rail data from
Relayless
Terminal Equipment and generates a bipolar signal
to the line
• On chip Clock and Data Recovery circuit for high
• Integrated Pulse Shaping Circuit
input jitter tolerance
• Built-in B3ZS/HDB3 Encoder (which can be
• Meets E3/DS3/STS-1 Jitter Tolerance Requirement
• Detects and Clears LOS as per G.775
disabled)
• Accepts Transmit Clock with duty cycle of 30%-
• Receiver Monitor mode handles up to 20 dB flat
70%
loss with 6 dB cable attenuation
• Generates pulses that comply with the ITU-T G.703
• On chip B3ZS/HDB3 encoder and decoder that can
pulse template for E3 applications
be either enabled or disabled
• Generates pulses that comply with the DSX-3 pulse
• On-chip clock synthesizer provides the appropriate
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993
rate clock from a single 12.288 MHz Clock
• Provides low jitter output clock
• Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253CORE
TRANSMITTER
• R3
Technology
Redundancy)
(Reconfigurable,
Relayless
• Transmitter can be turned off in order to support
redundancy designs
• Compliant with Bellcore GR-499, GR-253 and ANSI
RECEIVE INTERFACE CHARACTERISTICS
T1.102 Specification for transmit pulse
• Integrated Adaptive Receive Equalization (optional)
• Tri-state Transmit output capability for redundancy
for optimal Clock and Data Recovery
applications
• Declares and Clears the LOS defect per ITU-T
• Each Transmitter can be independently turned on
G.775 requirements for E3 and DS3 applications
or off
• Meets Jitter Tolerance Requirements, as specified
• Transmitters provide Voltage Output Drive
in ITU-T G.823_1993 for E3 Applications
CONTROL AND DIAGNOSTICS
• Meets Jitter Tolerance Requirements, as specified
• Parallel Microprocessor Interface for control and
in Bellcore GR-499-CORE for DS3 Applications
configuration
• Supports
optional
internal
Transmit
• Declares Loss of Lock (LOL) Alarm
• Built-in B3ZS/HDB3 Decoder (which can be
driver
monitoring
disabled)
• Each channel supports Analog, Remote and Digital
• Recovered Data can be muted while the LOS
Loop-backs
Condition is declared
• Single 3.3 V ± 5% power supply
• 5 V Tolerant digital inputs
• Available in 420 pin TBGA Thermally enhanced
• Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
Package
2
XRT73R12
REV. 1.0.2
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
APPLICATIONS ............................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT 73R12 .................................................................................................................................... 1
ORDERING INFORMATION .................................................................................................................... 1
FEATURES ..................................................................................................................................................................... 2
TRANSMIT INTERFACE CHARACTERISTICS ....................................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS ......................................................................................................................... 2
PIN DESCRIPTIONS (BY FUNCTION) .......................................................................................... 3
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS ....................................................................................... 3
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS ....................................................................................... 6
RECEIVE LINE SIDE PINS ............................................................................................................................................... 8
CLOCK INTERFACE......................................................................................................................................................... 9
GENERAL CONTROL PINS ............................................................................................................................................ 10
POWER SUPPLY PINS .................................................................................................................................................. 12
GROUND PINS ............................................................................................................................................................. 13
TABLE 1: LIST BY PIN NUMBER ............................................................................................................................................................. 14
FUNCTIONAL DESCRIPTION ...................................................................................................... 18
1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) ....................................... 18
1.1 NETWORK ARCHITECTURE ......................................................................................................................... 18
FIGURE 2. NETWORK REDUNDANCY ARCHITECTURE .............................................................................................................................. 18
2.0 CLOCK SYNTHESIZER ....................................................................................................................... 19
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR ............................................ 19
TABLE 2: REFERENCE CLOCK PERFORMANCE SPECIFICATIONS .............................................................................................................. 19
2.1 CLOCK DISTRIBUTION ................................................................................................................................. 20
FIGURE 4. CLOCK DISTRIBUTION CONGIFURED IN E3 MODE WITHOUT USING SFM ................................................................................ 20
3.0 THE RECEIVER SECTION .................................................................................................................. 21
FIGURE 5. RECEIVE PATH BLOCK DIAGRAM .......................................................................................................................................... 21
3.1 RECEIVE LINE INTERFACE .......................................................................................................................... 21
FIGURE 6. RECEIVE LINE INTERFACECONNECTION ................................................................................................................................. 21
3.2 ADAPTIVE GAIN CONTROL (AGC) .............................................................................................................. 21
3.3 RECEIVE EQUALIZER ................................................................................................................................... 21
FIGURE 7. ACG/EQUALIZER BLOCK DIAGRAM ....................................................................................................................................... 22
3.3.1 RECOMMENDATIONS FOR EQUALIZER SETTINGS .............................................................................................. 22
3.4 CLOCK AND DATA RECOVERY ................................................................................................................... 22
3.4.1 DATA/CLOCK RECOVERY MODE ............................................................................................................................ 22
3.4.2 TRAINING MODE........................................................................................................................................................ 22
3.5 LOS (LOSS OF SIGNAL) DETECTOR ........................................................................................................... 22
3.5.1 DS3/STS-1 LOS CONDITION ..................................................................................................................................... 22
TABLE 3: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-1 APPLICATIONS).......................................................................................................................................................................... 23
3.5.2 DISABLING ALOS/DLOS DETECTION ..................................................................................................................... 23
3.5.3 E3 LOS CONDITION:.................................................................................................................................................. 23
FIGURE 8. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 .................................................................................................. 23
FIGURE 9. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775................................................................................................... 24
3.5.4 INTERFERENCE TOLERANCE.................................................................................................................................. 24
FIGURE 10. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1 ...................................................................................................... 24
FIGURE 11. INTERFERENCE MARGIN TEST SET UP FOR E3. ................................................................................................................... 24
TABLE 4: INTERFERENCE MARGIN TEST RESULTS ................................................................................................................................. 25
3.5.5 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 25
FIGURE 12. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING ........................................................................................................ 25
3.6 B3ZS/HDB3 DECODER .................................................................................................................................. 26
4.0 THE TRANSMITTER SECTION ........................................................................................................... 27
FIGURE 13. TRANSMIT PATH BLOCK DIAGRAM ...................................................................................................................................... 27
4.1 TRANSMIT DIGITAL INPUT INTERFACE ..................................................................................................... 27
FIGURE 14. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT73R12 (DUAL-RAIL DATA) .............................................. 27
FIGURE 15. TRANSMITTER TERMINAL INPUT TIMING ............................................................................................................................... 28
FIGURE 16. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED) .................................................................. 28
4.2 TRANSMIT CLOCK ........................................................................................................................................ 29
4.3 B3ZS/HDB3 ENCODER .................................................................................................................................. 29
4.3.1 B3ZS ENCODING ....................................................................................................................................................... 29
I
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 18. B3ZS ENCODING FORMAT ................................................................................................................................................. 29
4.3.2 HDB3 ENCODING ....................................................................................................................................................... 29
FIGURE 17. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED).................................................................................... 29
FIGURE 19. HDB3 ENCODING FORMAT ................................................................................................................................................. 30
4.4 TRANSMIT PULSE SHAPER ......................................................................................................................... 30
FIGURE 20. TRANSMIT PULSE SHAPE TEST CIRCUIT .............................................................................................................................. 30
4.4.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................. 30
4.5 E3 LINE SIDE PARAMETERS ........................................................................................................................ 31
FIGURE 21. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703 ............................................................................. 31
TABLE 5: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS .............................................................. 32
FIGURE 22. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ................................. 33
TABLE 6: STS-1 PULSE MASK EQUATIONS ........................................................................................................................................... 33
TABLE 7: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)..................................... 34
FIGURE 23. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ......................................................................... 34
TABLE 8: DS3 PULSE MASK EQUATIONS ............................................................................................................................................... 35
TABLE 9: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ........................................ 35
4.6 TRANSMIT DRIVE MONITOR ........................................................................................................................ 36
FIGURE 24. TRANSMIT DRIVER MONITOR SET-UP................................................................................................................................... 36
4.7 TRANSMITTER SECTION ON/OFF ............................................................................................................... 36
5.0 JITTER ..................................................................................................................................................37
5.1 JITTER TOLERANCE ..................................................................................................................................... 37
FIGURE 25. JITTER TOLERANCE MEASUREMENTS .................................................................................................................................. 37
5.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS ................................................................................................ 37
FIGURE 26. INPUT JITTER TOLERANCE FOR DS3/STS-1 ...................................................................................................................... 38
5.1.2 E3 JITTER TOLERANCE REQUIREMENTS .............................................................................................................. 38
FIGURE 27. INPUT JITTER TOLERANCE FOR E3..................................................................................................................................... 38
TABLE 10: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ......................................................................... 39
5.2 JITTER TRANSFER ........................................................................................................................................ 39
TABLE 11: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................................................... 39
TABLE 12: JITTER TRANSFER PASS MASKS ........................................................................................................................................... 39
FIGURE 28. JITTER TRANSFER REQUIREMENTS ..................................................................................................................................... 40
5.2.1 JITTER GENERATION................................................................................................................................................ 40
6.0 DIAGNOSTIC FEATURES ...................................................................................................................41
6.1 PRBS GENERATOR AND DETECTOR ......................................................................................................... 41
FIGURE 29. PRBS MODE ................................................................................................................................................................... 41
6.2 LOOPBACKS .................................................................................................................................................. 42
6.2.1 ANALOG LOOPBACK ................................................................................................................................................ 42
FIGURE 30. ANALOG LOOPBACK ........................................................................................................................................................... 42
6.2.2 DIGITAL LOOPBACK ................................................................................................................................................. 43
FIGURE 31. DIGITAL LOOPBACK ............................................................................................................................................................ 43
6.2.3 REMOTE LOOPBACK ................................................................................................................................................ 43
FIGURE 32. REMOTE LOOPBACK ........................................................................................................................................................... 43
6.3 TRANSMIT ALL ONES (TAOS) ...................................................................................................................... 44
FIGURE 33. TRANSMIT ALL ONES (TAOS) ............................................................................................................................................ 44
7.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................45
TABLE 13: SELECTING THE MICROPROCESSOR INTERFACE MODE .......................................................................................................... 45
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK ........................................................................ 45
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 46
TABLE 14: XRT73R12 MICROPROCESSOR INTERFACE SIGNALS ............................................................................................................ 46
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION .......................................................................... 47
FIGURE 35. ASYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS .................................. 47
TABLE 15: ASYNCHRONOUS TIMING SPECIFICATIONS ............................................................................................................................. 48
FIGURE 36. SYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS.................................... 48
TABLE 16: SYNCHRONOUS TIMING SPECIFICATIONS ............................................................................................................................... 48
7.3 REGISTER MAP ............................................................................................................................................. 49
TABLE 17:
COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT73R12............................................................................................ 49
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................................ 58
TABLE 18: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS........................................................................................................ 58
................................................................................................................................................................................... 58
................................................................................................................................................................................... 58
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................................... 58
TABLE 19: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) ..................................................... 58
TABLE 20: APS/REDUNDANCY RECEIVE CONTROL REGISTER - CR8 (ADDRESS LOCATION = 0X08) ....................................................... 59
TABLE 21: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR128 (ADDRESS LOCATION = 0X80) ................................................. 59
II
XRT73R12
REV. 1.0.2
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
TABLE 22: APS/REDUNDANCY RECEIVE CONTROL REGISTER - CR136 (ADDRESS LOCATION = 0X88) ................................................... 60
FIGURE 37. CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR96 (ADDRESS LOCATION = 0X60) ....................................................... 61
TABLE 23: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR224 (ADDRESS LOCATION = 0XE0........................................................ 62
TABLE 24: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR97 (ADDRESS LOCATION = 0X61) ......................................................... 63
.................................................................................................................................................................................. 63
TABLE 25: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR225 (ADDRESS LOCATION = 0XE1)....................................................... 64
TABLE 26: DEVICE/PART NUMBER REGISTER - CR110 (ADDRESS LOCATION = 0X6E) ........................................................................... 64
TABLE 27: CHIP REVISION NUMBER REGISTER - CR111 (ADDRESS LOCATION = 0X6F) ......................................................................... 65
THE PER-CHANNEL REGISTERS........................................................................................................................... 66
REGISTER DESCRIPTION - PER CHANNEL REGISTERS .................................................................................... 66
TABLE 28:
TABLE 29:
TABLE 30:
TABLE 31:
TABLE 32:
TABLE 33:
TABLE 34:
TABLE 35:
TABLE 36:
TABLE 37:
TABLE 38:
TABLE 39:
TABLE 40:
TABLE 41:
TABLE 42:
TABLE 43:
TABLE 44:
TABLE 45:
XRT73R12 REGISTER MAP SHOWING INTERRUPT ENABLE REGISTERS (IER_N) (N = [0:11]) ............................................... 66
SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL N ADDRESS LOCATION = 0XM1 .................................................... 67
XRT73R12 REGISTER MAP SHOWING INTERRUPT STATUS REGISTERS (ISR_N).................................................................. 68
SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM2 .................................................... 68
XRT73R12 REGISTER MAP SHOWING ALARM STATUS REGISTERS (AS_N) .......................................................................... 70
ALARM STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM3................................................................................... 70
XRT73R12 REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_N)................................................................... 73
TRANSMIT CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM4 ........................................................................... 73
XRT73R12 REGISTER MAP SHOWING RECEIVE CONTROL REGISTERS (RC_N) .................................................................... 75
RECEIVE CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM5 ............................................................................. 75
XRT73R12 REGISTER MAP SHOWING CHANNEL CONTROL REGISTERS (CC_N) ................................................................... 77
CHANNEL CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM6 ............................................................................ 77
XRT73R12 REGISTER MAP SHOWING ERROR COUNTER MSBYTE REGISTERS (EM_N) (N = [0:11]) ..................................... 80
ERROR COUNTER MSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMA (M= 0-5 & 8-D) ........................................ 80
XRT73R12 REGISTER MAP SHOWING ERROR COUNTER LSBYTE REGISTERS (EL_N) (N = [0:11]) ....................................... 80
ERROR COUNTER LSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMB (M= 0-5 & 8-D) ......................................... 81
XRT73R12 REGISTER MAP SHOWING ERROR COUNTER HOLDING REGISTERS (EH_N) (N = [0:11]) ..................................... 81
ERROR COUNTER HOLDING REGISTER - CHANNEL N ADDRESS LOCATION = 0XMC (M= 0-5 & 8-D) ........................................ 82
8.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 83
TABLE 46: ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................. 83
TABLE 47: DC ELECTRICAL CHARACTERISTICS:..................................................................................................................................... 84
ORDERING INFORMATION .................................................................................................................. 85
PACKAGE DIMENSIONS - .............................................................................................................................................. 85
REVISION HISTORY ...................................................................................................................................................... 86
III
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
PIN DESCRIPTIONS (BY FUNCTION)
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN #
SIGNAL NAME
TYPE
P4
TxON
I
DESCRIPTION
Transmit On/Off Input
Upon power up, the transmitters are powered on. Turning the transmitters
On or Off is selected through the microprocessor interface by programming
the appropriate channel register if this pin is pulled "High". If the TxON pin
is pulled "Low", all 12 transmitters are powered off.
NOTE:
F22
AA22
H22
Y23
G26
AA25
G1
AA2
H5
Y4
F5
AA5
TxCLK0
TxCLK1
TxCLK2
TxCLK3
TxCLK4
TxCLK5
TxCLK6
TxCLK7
TxCLK8
TxCLK9
TxCLK10
TxCLK11
I
E23
AB24
J22
AA23
G25
AA26
G2
AA1
J5
AA4
E4
AB3
TxPOS0
TxPOS1
TxPOS2
TxPOS3
TxPOS4
TxPOS5
TxPOS6
TxPOS7
TxPOS8
TxPOS9
TxPOS10
TxPOS11
I
TxON is ideal for redundancy applications. See the R3
Technology section of this datasheet for more details.
Internally pulled "High".
Transmit Clock Input
These input pins have three functions:
• They function as the timing source for the Transmit Section of the
corresponding channel within the XRT73R12.
• They are used by the Transmit Section of the LIU IC to sample the
corresponding TxPOS_n and TxNEG_n input pins.
• They are used to clock the PRBS generator
NOTE: The user is expected to supply a 44.736MHz ± 20ppm clock signal
(for DS3 applications), 34.368MHz ± 20 ppm clock signal (for E3
applications) or a 51.84MHz ± 4.6ppm clock signal (for STS-1,
Stratum 3E or better applications).
Transmit Positive Data Input
The function of these digitial input pins depends upon whether the corresponding channel has been configured to operate in the Single-Rail or
Dual-Rail Mode.
Single Rail Mode - Transmit Data Input
Operating in the Single-Rail Mode; all transmit input data will be serially
applied to this input pin. This signal will be latched into the Transmit Section circuitry on the active edge of the TxCLK_n signal.
The Transmit Section of the LIU IC will then encode this data into either the
B3ZS line code (for DS3 and STS-1 applications) or the HDB3 line code
(for E3 applications).
Dual Rail Mode - Transmit Positive Data Input
In the Dual-Rail Mode, the user should apply a pulse to this input pin when
a positive-polarity pulse is to be transmitted onto the line. This signal will
be latched into the Transmit Section circuitry upon the active edge of the
TxCLK_n signal,.
The Transmit Section of the LIU IC will NOT encode this data into either the
B3ZS or HDB3 line codes. If the user configures the LIU IC to operate in
the Dual-Rail Mode, B3ZS/HDB3 encoding must have already been done
prior to this input.
3
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN #
SIGNAL NAME
TYPE
C25
AB25
H23
W23
H24
Y26
H3
Y1
H4
W4
C2
AB2
TxNEG0
TxNEG1
TxNEG2
TxNEG3
TxNEG4
TxNEG5
TxNEG6
TxNEG7
TxNEG8
TxNEG9
TxNEG10
TxNEG11
I
B24
AE24
C20
AD20
C16
AD16
C11
AD11
C7
AD7
C3
AD3
TTip0
TTip1
TTip2
TTip3
TTip4
TTip5
TTip6
TTip7
TTip8
TTip9
TTip10
TTip11
O
C24
AD24
B20
AE20
B16
AE16
B11
AE11
B7
AE7
B3
AE3
TRing0
TRing1
TRing2
TRing3
TRing4
TRing5
TRing6
TRing7
TRing8
TRing9
TRing10
TRing11
O
DESCRIPTION
Transmit Negative Data Input
When a Channel has been configured to operate in the Dual-Rail Mode,
the user should apply a pulse to this input pin anytime the Transmit Section
of the LIU IC to generate a negative-polarity pulse onto the line. This signal
will be latched into the Transmit Section circuitry upon the active edge of
the TxCLK_n signal.
NOTE: In the Single-Rail Mode, this input pin has no function, and should
be tied to GND.
Transmit TTIP Output - Positive Polarity Signal
These output pins along with the corresponding TRING_n output pins,
function as the Transmit DS3/E3/STS-1 Line output signal drivers for a
given channel of the XRT73R12.
Connect this signal and the corresponding TRING_n output signal to a 1:1
transformer.
Whenever the Transmit Section of the Channel generates and transmits a
positive-polarity pulse onto the line, this output pin will be pulsed to a high
ervoltage than its corresponding TRING_n output pins.
Conversely, whenever the Transmit Section of the Channel generates and
transmit a negative-polarity pulse onto the line, this output pin will be
pulsed to a lower voltage than its corresponding TRING_n output pin.
NOTE: This output pin will be tri-stated whenever the TxON input pin or bit-field
is set to "0".
Transmit Ring Output - Negative Polarity Signal
These output pins along with the corresponding TTIP_n output pins, function as the Transmit DS3/E3/STS-1 Line output signal drivers for a given
channel, within the XRT73R12.
Connect this signal and the corresponding TTIP_n output signal to a 1:1
transformer.
Whenever the Transmit Section of the Channel generates and transmits a
positive-polarity pulse onto the line, this output pin will be pulsed to a lower
voltage than its corresponding TTIP_n output pin.
Conversely, whenever the Transmit Section of the Channel generates and
transmit a negative-polarity pulse onto the line, this output pin will be
pulsed to a higher voltage than its corresponding TTIP_n output pin.
NOTE: This output pin will be tri-stated whenever the TxON input pin or bit-field
is set to "0".
4
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS
PIN #
SIGNAL NAME
TYPE
C23
AD23
D19
AC19
D15
AC15
E11
AB11
E8
AB8
C4
AD4
MTip0
MTip1
MTip2
MTip3
MTip4
MTip5
MTip6
MTip7
MTip8
MTip9
MTip10
MTip11
I
D23
AC23
E19
AB19
E16
AB16
D10
AC10
D8
AC8
D4
AC4
MRing0
MRing1
MRing2
MRing3
MRing4
MRing5
MRing6
MRing7
MRing8
MRing9
MRing10
MRing11
I
N3
N4
N5
N1
M1
L2
M2
M3
M4
M5
K2
J1
DMO0
DMO1
DMO2
DMO3
DMO4
DMO5
DMO6
DMO7
DMO8
DMO9
DMO10
DMO11
O
DESCRIPTION
Monitor Tip Input - Positive Polarity Signal
These input pins along with MRing_n function as the Transmit Drive Monitor Output (DMO) input monitoring pins. (1) To monitor the Transmit Output line signal and (2) to perform this monitoring externally, then this pin
MUST be connected to the corresponding TTIP_n output pin via a 270Ω
series resistor. Similarly, the MRING_n input pin MUST also be connected
to its corresponding TRING_n output pin via a 270Ω series resistor.
The MTIP_n and MRING_n input pins will continuously monitor the Transmit Output line signal via the TTIP_n and TRING_n output pins for bipolar
activity. If these pins do not detect any bipolar activity for 128 bit periods,
then the Transmit Drive Monitor circuit will drive the corresponding DMO_n
output pin "High" in order to denote a possible fault condition in the Transmit Output Line signal path.
NOTE:
These input pins are inactive if the user chooses to internally
monitor the Transmit Output line signal.
Monitor Ring Input
These input pins along with MTIP_n function as the Transmit Drive Monitor
Output (DMO) input monitoring pins. (1) To monitor the Transmit Output
line signal and (2) to perform this monitoring externally, then this input pin
MUST be connected to the corresponding TRING_n output pin via a 270Ω
series resistor. Similarly, the MTIP_n input pin MUST be connected to its
corresponding TTIP_n output pin via a 270Ω series resistor.
The MTIP_n and MRING_n input pins will continuously monitor the Transmit Output line signal via the TTIP_n and TRING_n output pins for bipolar
activity. If these pins do not detect any bipolar activity for 128 bit periods,
then the Transmit Drive Monitor circuit will drive the corresponding DMO_n
output pin "High" to indicate a possible fault condition in the Transmit Output Line signal path.
NOTE:
These input pins are inactive if the user chooses to internally
monitor the Transmit Output line signal.
Drive Monitor Output
These output signals are used to indicate a fault condition within the Transmit Output signal path.
This output pin will toggle "High" anytime the Transmit Drive Monitor circuitry either, via the corresponding MTIP and MRING input pins or internally, detects no bipolar pulses via the Transmit Output line signal (e.g., via
the TTIP_m and TRING_m output pins) for 128 bit-periods.
This output pin will be driven "Low" anytime the Transmit Drive Monitor circuitry has detected at least one bipolar pulse via the Transmit Output line
signal within the last 128 bit periods.
5
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN #
SIGNAL NAME
TYPE
D25
AD25
G23
AA24
J24
U24
J3
U3
G4
AA3
D2
AD2
RLOS0
RLOS1
RLOS2
RLOS3
RLOS4
RLOS5
RLOS6
RLOS7
RLOS8
RLOS9
RLOS10
RLOS11
O
G22
AB26
K22
U22
L24
W25
L3
W2
K5
U5
G5
AB1
RLOL0
RLOL1
RLOL2
RLOL3
RLOL4
RLOL5
RLOL6
RLOL7
RLOL8
RLOL9
RLOL10
RLOL11
O
E25
AD26
G24
Y24
L22
T22
L5
T5
G3
Y3
E2
AD1
RxPOS0
RxPOS1
RxPOS2
RxPOS3
RxPOS4
RxPOS5
RxPOS6
RxPOS7
RxPOS8
RxPOS9
RxPOS10
RxPOS11
O
DESCRIPTION
Receive Loss of Signal Output Indicator
This output pin indicates Loss of Signal (LOS) Defect condition for the corresponding channel.
"Low" - Indicates that the corresponding Channel is NOT currently declaring the
LOS defect condition.
"High" - Indicates that the corresponding Channel is currently declaring the LOS
defect condition.
Receive Loss of Lock Output Indicator
This output pin indicates Loss of Lock (LOL) condition for the corresponding
channel.
"Low" - Indicates that the corresponding Channel is NOT declaring the LOL
condition.
"High" - Indicates that the corresponding Channel is currently declaring the LOL
condition.
NOTE: The Receive Section of a given channel will declare the LOL condition
anytime the frequency of the Recovered Clock (RCLK) signal differs
from that of the reference clock programmed for that channel by 0.5%
or more.
Receive Positive Data Output
The function of these output pins depends upon whether the channel has been
configured to operate in the Single-Rail or Dual-Rail Mode.
Dual-Rail Mode - Receive Positive Polarity Data Output
If the channel has been configured to operate in the Dual-Rail Mode, then all
positive-polarity data will be output via this pin. The negative-polarity data will
be output via the corresponding RxNEG_n pin. In other words, the Receive
Section of the corresponding Channel will pulse this output pin "High" for one
period of RCLK_n anytime it receives a positive-polarity pulse via the RTIP/
RRING input pins.
The data output via this pin is updated upon the active edge of RxCLK_n output
clock signal.
Single-Rail Mode - Receive Data Output
In the Single-Rail Mode, all Receive (or Recovered) data will be output via this
pin.
The data output via this pin is updated upon the active edge of the RCLK_n
output clock signal.
6
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN #
SIGNAL NAME
TYPE
F23
AC26
F24
U23
L23
T24
L4
T3
F3
U4
F4
AC1
RxNEG/LCV0
RxNEG/LCV1
RxNEG/LCV2
RxNEG/LCV3
RxNEG/LCV4
RxNEG/LCV5
RxNEG/LCV6
RxNEG/LCV7
RxNEG/LCV8
RxNEG/LCV9
RxNEG/LCV10
RxNEG/LCV11
O
E24
AC25
J23
V23
K24
T23
K3
T4
J4
V4
E3
AC2
RxCLK0
RxCLK1
RxCLK2
RxCLK3
RxCLK4
RxCLK5
RxCLK6
RxCLK7
RxCLK8
RxCLK9
RxCLK10
RxCLK11
O
DESCRIPTION
Receive Negative Data Output/Line Code Violation
The function of these pins depends on whether the XRT73R12 is configured in
Single Rail or Dual Rail mode.
Dual-Rail Mode - Receive Negative Polarity Data Output
In the Dual-Rail Mode, all negative-polarity data will be output via this pin. The
positive-polarity data will be output via the corresponding RxPOS_n output pin.
In other words, the Receive Section of the corresponding Channel will pulse this
output pin "High" for one period of RxCLK_n anytime it receives a negativepolarity pulse via the RTIP/RRING input pins.
The data output via this pin is updated upon the active edge of the RCLK_n
output clock signal.
Single-Rail Mode - Line Code Violation Indicator Output
In the Single-Rail Mode, this output pin will function as the Line Code Violation
indicator output.
In this configuration, the Receive Section of the Channel will pulse this output
pin "High" for at least one RCLK period whenever it detects either an LCV (Line
Code Violation) or an EXZ (Excessive Zero Event).
The data that is output via this pin is updated upon the active edge of the
RCLK_n output clock signal.
Receive Clock Output
This output pin functions as the Receive or recovered clock signal. All Receive
(or recovered) data will output via the RxPOS_n and RxNEG_n outputs upon
the active edge of this clock signal.
Additionally, if the device/channel has been configured to operate in the SingleRail Mode, then the RNEG_n/LCV_n output pins will also be updated upon the
active edge of this clock signal.
7
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
RECEIVE LINE SIDE PINS
PIN #
SIGNAL NAME
TYPE
B22
AE22
B18
AE18
A14
AF14
D13
AC13
B9
AE9
B5
AE5
RTip0
RTip1
RTip2
RTip3
RTip4
RTip5
RTip6
RTip7
RTip8
RTip9
RTip10
RTip11
I
C22
AD22
C18
AD18
B14
AE14
C13
AD13
C9
AD9
C5
AD5
RRing0
RRing1
RRing2
RRing3
RRing4
RRing5
RRing6
RRing7
RRing8
RRing9
RRing10
RRing11
I
DESCRIPTION
Receive TIP Input
These input pins along with the corresponding RRing_n input pin function as the
Receive DS3/E3/STS-1 Line input signal for a given channel of the XRT73R12.
Cconnect this signal and the corresponding RRING_n input signal to a 1:1
transformer.
Whenever the RTIP/RRING input pins are receiving a positive-polarity pulse
within the incoming DS3, E3 or STS-1 line signal, this input pin will be pulsed to
a higher voltage than its corresponding RRING_n input pin.
Conversely, whenever the RTIP/RRING input pins are receiving a negativepolarity pulse within the incoming DS3, E3 or STS-1 line signal, this input pin
will be pulsed to a lower voltage than its corresponding RRING_n input pin.
Receive Ring Input
These input pins along with the corresponding RTIP_n input pin function as the
Receive DS3/E3/STS-1 Line input signal for a given channel of the XRT73R12.
Connect this signal and the corresponding RTIP_n input signal to a 1:1 transformer. (See Figure 6)
Whenever the RTIP/RRING input pins are receiving a positive-polarity pulse
within the incoming DS3, E3 or STS-1 line signal, then this input pin will be
pulsed to a lower voltage than its corresponding RTIP_n input pin.
Conversely, whenever the RTIP/RRING input pins are receiving a negativepolarity pulse within the incoming DS3, E3 or STS-1 line signal, then this input
pin will be pulsed to a higher voltage than its corresponding RTIP_n input pin.
8
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
CLOCK INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
R5
SFM_EN
I
Single Frequency Mode Enable
This input pin is used to configure the XRT73R12 to operate in the SFM (Single
Frequency Mode).
When this feature is invoked, the SFM Synthesizer will become active. By
applying a 12.288MHz clock signal to the STS-1Clk/12M pin, the XRT73R12 will
generate all of the appropriate clock signals (e.g., 34.368MHz, 44.736MHz or
51.84). The XRT73R12 internal circuitry will route each of these synthesized
clock signals to the appropriate nodes of the corresponding channels in the
XRT73R12.
"Low" - Disables the Single Frequency Mode. In this setting, the user is
required to supply to the E3CLK, DS3CLK or STS-1CLK input pins all of the relevant clock signals that are to be used within the chip.
"High" - Enables the Single-Frequency Mode.
NOTE: This input pin is internally pulled low.
R1
E3Clk
I
E3 Clock Input (34.368 MHz ± 20 ppm)
If any one of the channels is configured in E3 mode, a reference clock of 34.368
MHz ± 20 ppm is applied to this input pin. If the LIU is used in E3 mode only,
this pin must be connected to the DS3Clk input pin to have access to the internal microprocessor.
NOTE: SFM mode negates the need for this clock
T1
DS3Clk
I
DS3 Clock Input (44.736 MHz ± 20 ppm)
If any one of the channels is configured in DS3 mode, a reference clock of
44.736 MHz ± 20 ppm is applied to this input pin.
NOTE: SFM mode negates the need for this clock
U1
STS-1Clk/12M
I
STS-1 Clock Input (51.84 MHz ± 20 ppm)
If any one of the channels is configured in STS-1 mode, a reference clock of
51.84MHz ± 20 ppm is applied to this input pin. If the LIU is used in STS-1
mode only, this pin must be connected to the DS3Clk input pin to have access
to the internal microprocessor.
Single Frequency Mode Clock Input (12.288MHz ± 20 ppm)
In Single Frequency Mode, a reference clock of 12.288 MHz ± 20 ppm is connected to this pin and the internal clock synthesizer generates the appropriate
clock frequencies based on the configuration of the rates (E3, DS3 or STS-1).
C26
W22
K23
W24
J25
V25
J2
V2
K4
W3
C1
W5
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKOUT6
CLKOUT7
CLKOUT8
CLKOUT9
CLKOUT10
CLKOUT11
O
Reference Clock Out
A reference clock pin is provided for each channel that will supply a precise data
rate frequency derived from either the Clock input pin (E3Clk, DS3Clk, or STS1Clk) or the 12.288MHz input in SFM mode. This frequency will be as stable as
the original source. It is designed to provide the attached framer with its appropriate reference clock.
9
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
GENERAL CONTROL PINS
PIN #
SIGNAL NAME
TYPE
P3
TEST
****
DESCRIPTION
Factory Test Mode Input Pin
This pin must be connected to GND for normal operation.
NOTE: This input pin is internally pulled "Low".
AE25
TRST
I
Test Reset
Test Boundary Scan
AB23
TMS
I
Test Mode Select
Test Boundary Scan
AB5
TCK
I
Test Clock
Test Boundary Scan
AB4
TDI
I
Test Data Input
Test Boundary Scan
AE2
TDO
O
Test Data Output
Test Boundary Scan
MICROPROCESSOR PARALLEL INTERFACE PIN #
SIGNAL NAME
TYPE
DESCRIPTION
J26
Pmode
I
This pin controls the Microprocessor Parallel Interface mode.
"High" sets a Synchronous clocked interface mode with a clock from the Host.
"Low" sets an Asynchronous mode where a clock internal to the XRT73R12 will
time the operations.
P24
PCLK
I
High speed clock supplied by the Host to provide timing in the Synchronous
Interface mode. This signal must be a square-wave.
N24
CS
I
Chip Select Input (active low)
Initiates a read or write operation. When "High", no parallel communication is
active between the LIU and the Host.
N22
WR
I
Write Input (active low)
Enables the Host to write data D[7:0] into the LIU register space at address
Addr[7:0].
N23
RD
I
Read Input (active low)
Commands the LIU to transfer the contents of a register specified by Addr[7:0]
to the Host.
N25
RDY
O
Ready Line Output (active low)
Provides a handshake between the LIU and the Host that communicates when
an operation has been completed.
NOTE: This pin must be pulled "High" with a 3kΩ ± 1% resistor.
10
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
MICROPROCESSOR PARALLEL INTERFACE PIN #
SIGNAL NAME
TYPE
DESCRIPTION
K25
M22
M23
M24
K26
L26
M26
N26
Addr0
Addr1
Addr2
Addr3
Addr4
Addr5
Addr6
Addr7
I
An eight bit direct address bus that specifies the source/destination register for
a Read or Write operation.
P22
R26
T26
U26
R25
R24
R23
R22
D0
D1
D2
D3
D4
D5
D6
D7
I/O
An eight bit bi-directional data bus that provides the data into the LIU for a Write
operation or the data out to the Host for a Read operation.
P26
INT
O
Interrupt Active Output (active low)
Normally, this output pin will be pulled "High". However, if the user enables
interrupts within the LIU, and if those conditions occur, the XRT73R12 will signal an interrupt from the Microprocessor by pulling this output pin "Low". The
Host Microprocessor must ascertain the source of the interrupt and service it.
Reading the source of the interupt will clear the flag and the INT pin will go back
high unless another interrupt has gone active.
NOTES:
1. This pin will remain "Low" until the Interrupt has been serviced.
2.
N2
RESET
I
This pin must be pulled "High" with a 3kΩ ± 1% resistor
RESET Input
Pulsing this input "Low" causes the XRT73R12 to reset the contents of the onchip Command Registers to their default values. As a consequence, the
XRT73R12 will then also be operating in its default condition.
For normal operation this input pin should be at a logic "High".
NOTE: This input pin is internally pulled high.
11
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
POWER SUPPLY PINS
PIN NAME
PIN NUMBERS
DESCRIPTION
RVDD0
RVDD1
RVDD2
RVDD3
RVDD4
RVDD5
RVDD6
RVDD7
RVDD8
RVDD9
RVDD10
RVDD11
D22
AC22
D18
AC18
E15
AB15
E12
AB12
A9
AF9
D5
AC5
Receive Analog Power Supply (3.3V ±5%)
RVDD should not be shared with other power supplies. It is recommended
that RVDD be isolated from the digital power supply DVDD and the analog
power supply TVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used.
Each power supply pin should be bypassed to ground through an external
0.1µF capacitor.
TVDD0
TVDD1
TVDD2
TVDD3
TVDD4
TVDD5
TVDD6
TVDD7
TVDD8
TVDD9
TVDD10
TVDD11
B23
AE23
B19
AE19
B15
AE15
B10
AE10
A6
AF6
B4
AE4
Transmit Analog Power Supply (3.3V ±5%)
TVDD can be shared with DVDD. However, it is recommended that TVDD be
isolated from the analog power supply RVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground
through an external 0.1µF capacitor.
AVDD
M25, T25, AB21, AB18,
AF13, AF12, AB9, AB6,
R4, K1, E6, E9, A12, A13,
E18, E21,
Analog Power Supply (3.3V ±5%)
AVDD should be isolated from the digital power supplies. For best results,
use an internal power plane for isolation. If an internal power plane is not
available, a ferrite bead can be used. Each power supply pin should be
bypassed to ground through at least one 0.1µF capacitor.
DVDD
D26, F25, H25, P25, W26,
V24, Y22, AF21, AF20,
AF17, AF16, AD14, AD12,
AF11, AF8, AF7, AF24,
AD6, AF3, Y5, V3, W1, P5,
P2, H2, F2, D1, C6, A7,
A3, A8, A11, C12, C14,
A16, A17, A20, A21, A24
Digital Power Supply (3.3V ±5%)
DVDD should be isolated from the analog power supplies. For best results,
use an internal power plane for isolation. If an internal power plane is not
available, a ferrite bead can be used. Every two DVDD power supply pins
should be bypassed to ground through at least one 0.1µF capacitor.
12
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
GROUND PINS
PIN NAME
PIN NUMBERS
DESCRIPTION
RGND0
RGND1
RGND2
RGND3
RGND4
RGND5
RGND6
RGND7
RGND8
RGND9
RGND10
RGND11
A22
AF22
A18
AF18
E14
AB14
E13
AB13
D9
AC9
A5
AF5
Receive Analog Ground
It’s recommended that all ground pins of this device be tied together.
TGND0
TGND1
TGND2
TGND3
TGND4
TGND5
TGND6
TGND7
TGND8
TGND9
TGND10
TGND11
A23
AF23
A19
AF19
A15
AF15
A10
AF10
B6
AE6
A4
AF4
Transmit Analog Ground
It’s recommended that all ground pins of this device be tied together.
AGND
A1, A2, A25, A26, B1, B2, Analog Ground
B25, B26, C8, C10, C17, It’s recommended that all ground pins of this device be tied together.
C19, C21, D17, D21, E5,
E22, L25, U25, AB22,
AB20, AB17, AB10, AB7,
R3, L1, E7, E10, B12, B13,
E17, E20, T2, U2, AC17,
AC21, AD8, AD10, AD15,
AD17, AD19, AD21, AE1,
AE12, AE13, AE26, AF1,
AF2, AF25, AF26, C15
DGND
E26, F26, H26, P23, , V26, Digital Ground
Y25, V22, AC24, AC20, It’s recommended that all ground pins of this device be tied together.
AC16, AC14, AC12, AC11,
AE8, AE17, AE21, AC7,
AC6, AC3, V5, Y2, V1, R2,
P1, H1, F1, E1, D3, D7,
B8, D6, D11, D12, D14,
D16, B17, D20, B21, D24
13
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 1: LIST BY PIN
NUMBER
PIN
PIN NAME
A1
AGND
A2
AGND
A3
DVDD
A4
TGND10
A5
RGND10
A6
TVDD8
A7
DVDD
A8
DVDD
A9
RVDD8
A10
TGND6
A11
DVDD
A12
AVDD
A13
AVDD
A14
RTip4
A15
TGND4
A16
DVDD
A17
DVDD
A18
RGND2
A19
TGND2
A20
DVDD
A21
DVDD
A22
RGND0
A23
TGND0
A24
DVDD
A25
AGND
A26
AGND
B1
AGND
B2
AGND
B3
TRing10
B4
TVDD10
B5
RTip10
TABLE 1: LIST BY PIN
NUMBER
TABLE 1: LIST BY PIN
NUMBER
TABLE 1: LIST BY PIN
NUMBER
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
B6
TGND8
C12
DVDD
D18
RVDD2
B7
TRing8
C13
RRing6
D19
MTip2
B8
DGND
C14
DVDD
D20
DGND
B9
RTip8
C15
AGND
D21
AGND
B10
TVDD6
C16
TTip4
D22
RVDD0
B11
TRing6
C17
AGND
D23
MRing0
B12
AGND
C18
RRing2
D24
DGND
B13
AGND
C19
AGND
D25
RLOS0
B14
RRing4
C20
TTip2
D26
DVDD
B15
TVDD4
C21
AGND
E1
DGND
B16
TRing4
C22
RRing0
E2
RxPOS10
B17
DGND
C23
MTip0
E3
RxCLK10
B18
RTip2
C24
TRing0
E4
TxPOS10
B19
TVDD2
C25
TxNEG0
E5
AGND
B20
TRing2
C26
CLKOUT0
E6
AVDD
B21
DGND
D1
DVDD
E7
AGND
B22
RTip0
D2
RLOS10
E8
MTip8
B23
TVDD0
D3
DGND
E9
AVDD
B24
TTip0
D4
MRing10
E10
AGND
B25
AGND
D5
RVDD10
E11
MTip6
B26
AGND
D6
DGND
E12
RVDD6
C1
CLKOUT10
D7
DGND
E13
RGND6
C2
TxNEG10
D8
MRing8
E14
RGND4
C3
TTip10
D9
RGND8
E15
RVDD4
C4
MTip10
D10
MRing6
E16
MRing4
C5
RRing10
D11
DGND
E17
AGND
C6
DVDD
D12
DGND
E18
AVDD
C7
TTip8
D13
RTip6
E19
MRing2
C8
AGND
D14
DGND
E20
AGND
C9
RRing8
D15
MTip4
E21
AVDD
C10
AGND
D16
DGND
E22
AGND
C11
TTip6
D17
AGND
E23
TxPOS0
14
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 1: LIST BY PIN
NUMBER
TABLE 1: LIST BY PIN
NUMBER
TABLE 1: LIST BY PIN
NUMBER
TABLE 1: LIST BY PIN
NUMBER
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
E24
RxCLK0
H26
DGND
M2
DMO6
R4
AVDD
E25
RxPOS0
J1
DMO11
M3
DMO7
R5
SFM_EN
E26
DGND
J2
CLKOUT6
M4
DMO8
R22
D7
F1
DGND
J3
RLOS6
M5
DMO9
R23
D6
F2
DVDD
J4
RxCLK8
M22
Addr1
R24
D5
F3
RxNEG/LCV8
J5
TxPOS8
M23
Addr2
R25
D4
F4
RxNEG/LCV10
J22
TxPOS2
M24
Addr3
R26
D1
F5
TxCLK10
J23
RxCLK2
M25
AVDD
T1
DS3Clk
F22
TxCLK0
J24
RLOS4
M26
Addr6
T2
AGND
F23
RxNEG/LCV0
J25
CLKOUT4
N1
DMO3
T3
RxNEG/LCV7
F24
RxNEG/LCV2
J26
Pmode
N2
RESET
T4
RxCLK7
F25
DVDD
K1
AVDD
N3
DMO0
T5
RxPOS7
F26
DGND
K2
DMO10
N4
DMO1
T22
RxPOS5
G1
TxCLK6
K3
RxCLK6
N5
DMO2
T23
RxCLK5
G2
TxPOS6
K4
CLKOUT8
N22
WR
T24
RxNEG/LCV5
G3
RxPOS8
K5
RLOL8
N23
RD
T25
AVDD
G4
RLOS8
K22
RLOL2
N24
CS
T26
D2
G5
RLOL10
K23
CLKOUT2
N25
RDY
U1
STS-1Clk/12M
G22
RLOL0
K24
RxCLK4
N26
Addr7
U2
AGND
G23
RLOS2
K25
Addr0
P1
DGND
U3
RLOS7
G24
RxPOS2
K26
Addr4
P2
DVDD
U4
RxNEG/LCV9
G25
TxPOS4
L1
AGND
P3
TEST
U5
RLOL9
G26
TxCLK4
L2
DMO5
P4
TxON
U22
RLOL3
H1
DGND
L3
RLOL6
P5
DVDD
U23
RxNEG/LCV3
H2
DVDD
L4
RxNEG/LCV6
P22
D0
U24
RLOS5
H3
TxNEG6
L5
RxPOS6
P23
DGND
U25
AGND
H4
TxNEG8
L22
RxPOS4
P24
PCLK
U26
D3
H5
TxCLK8
L23
RxNEG/LCV4
P25
DVDD
V1
DGND
H22
TxCLK2
L24
RLOL4
P26
INT
V2
CLKOUT7
H23
TxNEG2
L25
AGND
R1
E3Clk
V3
DVDD
H24
TxNEG4
L26
Addr5
R2
DGND
V4
RxCLK9
H25
DVDD
M1
DMO4
R3
AGND
V5
DGND
15
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 1: LIST BY PIN
NUMBER
TABLE 1: LIST BY PIN
NUMBER
TABLE 1: LIST BY PIN
NUMBER
TABLE 1: LIST BY PIN
NUMBER
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
PIN
PIN NAME
V22
DGND
AA24
RLOS3
AC4
MRing11
AD10
AGND
V23
RxCLK3
AA25
TxCLK5
AC5
RVDD11
AD11
TTip7
V24
DVDD
AA26
TxPOS5
AC6
DGND
AD12
DVDD
V25
CLKOUT5
AB1
RLOL11
AC7
DGND
AD13
RRing7
V26
DGND
AB2
TxNEG11
AC8
MRing9
AD14
DVDD
W1
DVDD
AB3
TxPOS11
AC9
RGND9
AD15
AGND
W2
RLOL7
AB4
TDI
AC10
MRing7
AD16
TTip5
W3
CLKOUT9
AB5
TCK
AC11
DGND
AD17
AGND
W4
TxNEG9
AB6
AVDD
AC12
DGND
AD18
RRing3
W5
CLKOUT11
AB7
AGND
AC13
RTip7
AD19
AGND
W22
CLKOUT1
AB8
MTip9
AC14
DGND
AD20
TTip3
W23
TxNEG3
AB9
AVDD
AC15
MTip5
AD21
AGND
W24
CLKOUT3
AB10
AGND
AC16
DGND
AD22
RRing1
W25
RLOL5
AB11
MTip7
AC17
AGND
AD23
MTip1
W26
DVDD
AB12
RVDD7
AC18
RVDD3
AD24
TRing1
Y1
TxNEG7
AB13
RGND7
AC19
MTip3
AD25
RLOS1
Y2
DGND
AB14
RGND5
AC20
DGND
AD26
RxPOS1
Y3
RxPOS9
AB15
RVDD5
AC21
AGND
AE1
AGND
Y4
TxCLK9
AB16
MRing5
AC22
RVDD1
AE2
TDO
Y5
DVDD
AB17
AGND
AC23
MRing1
AE3
TRing11
Y22
DVDD
AB18
AVDD
AC24
DGND
AE4
TVDD11
Y23
TxCLK3
AB19
MRing3
AC25
RxCLK1
AE5
RTip11
Y24
RxPOS3
AB20
AGND
AC26
RxNEG/LCV1
AE6
TGND9
Y25
DGND
AB21
AVDD
AD1
RxPOS11
AE7
TRing9
Y26
TxNEG5
AB22
AGND
AD2
RLOS11
AE8
DGND
AA1
TxPOS7
AB23
TMS
AD3
TTip11
AE9
RTip9
AA2
TxCLK7
AB24
TxPOS1
AD4
MTip11
AE10
TVDD7
AA3
RLOS9
AB25
TxNEG1
AD5
RRing11
AE11
TRing7
AA4
TxPOS9
AB26
RLOL1
AD6
DVDD
AE12
AGND
AA5
TxCLK11
AC1
RxNEG/LCV11
AD7
TTip9
AE13
AGND
AA22
TxCLK1
AC2
RxCLK11
AD8
AGND
AE14
RRing5
AA23
TxPOS3
AC3
DGND
AD9
RRing9
AE15
TVDD5
16
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
TABLE 1: LIST BY PIN
NUMBER
TABLE 1: LIST BY PIN
NUMBER
PIN
PIN NAME
PIN
PIN NAME
AE16
TRing5
AF22
RGND1
AE17
DGND
AF23
TGND1
AE18
RTip3
AF24
DVDD
AE19
TVDD3
AF25
AGND
AE20
TRing3
AF26
AGND
AE21
DGND
AE22
RTip1
AE23
TVDD1
AE24
TTip1
AE25
TRST
AE26
AGND
AF1
AGND
AF2
AGND
AF3
DVDD
AF4
TGND11
AF5
RGND11
AF6
TVDD9
AF7
DVDD
AF8
DVDD
AF9
RVDD9
AF10
TGND7
AF11
DVDD
AF12
AVDD
AF13
AVDD
AF14
RTip5
AF15
TGND5
AF16
DVDD
AF17
DVDD
AF18
RGND3
AF19
TGND3
AF20
DVDD
AF21
DVDD
17
REV. 1.0.2
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FUNCTIONAL DESCRIPTION
The XRT73R12 is a twelve channel fully integrated Line Interface Unit featuring EXAR’s R3 Technology
(Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications.
The LIU incorporates 12
independent Receivers and Transmitters in a single 420 Lead TBGA package. Each channel can be
independently programmed to support E3, DS-3 or STS-1 line rates using one input clock reference of
12.288MHz in Single Frequency Mode (SFM). The LIU is responsible for providing the physical connection
between a line interface and an aggregate mapper or framing device. Along with the analog-to-digital
processing, the LIU offers monitoring and diagnostic features to help optimize network design implementation.
A key characteristic within the network topology is Automatic Protection Switching (APS). EXAR’s proven
expertise in providing redundany solutions has paved the way for R3 Technology.
1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY)
Redundancy is used to introduce reliability and protection into network card design. The redundant card in
many cases is an exact replicate of the primary card, such that when a failure occurs the network processor
can automatically switch to the backup card. EXAR’s R3 technology has re-defined E3/DS-3/STS-1 LIU design
for 1:1 and 1+1 redundancy applications. Without relays and one Bill of Materials, EXAR offers multi-port,
integrated LIU solutions to assist high density aggregate applications and framing requirements with reliability.
The following section can be used as a reference for implementing R3 Technology with EXAR’s world leading
line interface units.
1.1
Network Architecture
A common network design that supports 1:1 or 1+1 redundancy consists of N primary cards along with N
backup cards that connect into a mid-plane or back-plane architecture without transformers installed on the
network cards. In addition to the network cards, the design has a line interface card with one source of
transformers, connectors, and protection components that are common to both network cards. With this
design, the bill of materials is reduced to the fewest amount of components. See Figure 2. for a simplified
block diagram of a typical redundancy design.
FIGURE 2. NETWORK REDUNDANCY ARCHITECTURE
GND
37.5Ω
Rx
Framer/
Mapper
0.01µF
LIU
31.6Ω
Tx
31.6Ω
1:1
Line Interface Card
Primary Line Card
0.01µF
Rx
Framer/
Mapper
37.5Ω
1:1
0.01µF
0.01µF
LIU
31.6Ω
Tx
31.6Ω
Redundant Line Card
Back
Plane
or
Mid
Plane
18
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
2.0 CLOCK SYNTHESIZER
The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks
used to drive the LIU. The reference clock used to supply the microprocessor timing is generated from the DS3 or SFM clock input. Therefore, if the chip is configured for STS-1 only or E3 only, then the DS-3 input pin
must be connected to the STS-1 pin or E3 pin respectively. In DS-3 mode or when SFM is used, the STS-1
and E3 input pins can be left unconnected. If SFM is enabled by pulling the SFM_EN pin "High", 12.288MHz is
the only clock reference necessary to generate DS-3, E3, or STS-1 line rates and the microprocessor timing.
A simplified block diagram of the clock synthesizer is shown in Figure 3. Reference clock performance
specifications can be found on Table 2 below.
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR
SFM_EN
STS-1Clk/12M
DS3Clk
E3Clk
CLKOUT_n
Clock Synthesizer
LOL_n
0
µProcessor
1
TABLE 2: REFERENCE CLOCK PERFORMANCE SPECIFICATIONS
SYMBOL
REFDUTY
PARAMETER
MIN
TYP
MAX
UNITS
Reference Clock Duty Cycle
40
60
%
REFE3
E3 Reference Clock Frequency Tolerance1
-20
+20
ppm
REFDS3
DS3 Reference Clock Frequency Tolerance1
-20
+20
ppm
REFSTS1
STS-1 Reference Clock Frequency Tolerance1
-20
+20
ppm
REFSFM
SFM Reference Clock Frequency Tolerance1
-20
+20
ppm
tRISE_REFCLK Reference Clock Rise Time (10% to 90%)
5
ns
tFALL_REFCLK Reference Clock Fall Time (90% to 10%)
5
ns
0.005
UIp2p
CLKJIT
Reference Clock Jitter Stability2
NOTES:
1.
Required to meet Bellcore GR-499 specification on frequency stability requirements. However, the LIU can
functionally operate with ±100 ppm without meeting the required specifications.
2.
Reference clock jitter limits are required for the transmit output to meet ITU-T and Bellcore system level jitter
requirements.
19
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
2.1
Clock Distribution
Network cards that are designed to support multiple line rates which are not configured for single frequency
mode should ensure that a clock is applied to the DS3Clk input pin. For example: If the network card being
supplied to an ISP requires E3 only, the DS-3 input clock reference is still necessary to provide read and write
access to the internal microprocessor. Therefore, the E3 mode requires two input clock references. If
however, multiple line rates will not be supported, i.e. E3 only, then the DS3Clk input pin may be hard wire
connected to the E3Clk input pin.
FIGURE 4. CLOCK DISTRIBUTION CONGIFURED IN E3 MODE WITHOUT USING SFM
DS3Clk
E3Clk
Clock Synthesizer
CLKOUT_n
LOL_n
µProcessor
NOTE: For one input clock reference, the single frequency mode should be used.
20
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
3.0 THE RECEIVER SECTION
The receiver is designed so that the LIU can recover clock and data from an attenuated line signal caused by
cable loss or flat loss according to industry specifications. Once data is recovered, it is processed and
presented at the receiver outputs according to the format chosen to interface with a Framer/Mapper or ASIC.
This section describes the detailed operation of various blocks within the receive path. A simplified block
diagram of the receive path is shown in Figure 5.
FIGURE 5. RECEIVE PATH BLOCK DIAGRAM
Peak Detector
RTIP_n
RRing_n
AGC/
Equalizer
Clock & Data
Recovery
Slicer
HDB3/
B3ZS
Decoder
MUX
LOS
Detector
RxClk_n
RxPOS_n
RxNEG/LCV_n
RLOS_n
Channel n
3.1
Receive Line Interface
Physical Layer devices are AC coupled to a line interface through a 1:1 transformer. The transformer provides
isolation and a level shift by blocking the DC offset of the incoming data stream. The typical medium for the
line interface is a 75Ω coxial cable. Whether using E3, DS-3 or STS-1, the LIU requires the same bill of
materials, see Figure 6.
FIGURE 6. RECEIVE LINE INTERFACECONNECTION
1:1
RTIP_n
75Ω
Receiver
RRing_n
DS-3/E3/STS-1
37.5Ω
37.5Ω
0.01µF
RLOS_n
3.2
Adaptive Gain Control (AGC)
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat
losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The peak
detector provides feedback to the equalizer before slicing occurs.
3.3
Receive Equalizer
The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of
up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the
signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to
generate Positive and Negative data. The equalizer can be disabled by programming the appropriate register.
21
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 7. ACG/EQUALIZER BLOCK DIAGRAM
Peak Detector
RTIP_n
RRing_n
AGC/
Equalizer
Slicer
LOS
Detector
3.3.1
Recommendations for Equalizer Settings
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/
STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,
the Equalizer can be enabled. However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses
(that does not meet the pulse template requirements), it is recommended that the Equalizer be disabled for
cable length less than 300 feet. This would help to prevent over-equalization of the signal and thus optimize
the performance in terms of better jitter transfer characteristics. The Equalizer also contains an additional 20
dB gain stage to provide the line monitoring capability (Receive Monitor Mode) of the resistively attenuated
signals which may have 20dB flat loss. The equalizer and the equalizer gain mode can be enabled by
programming the appropriate register. However, enabling the equalizer gain mode (Receive Monitor Mode)
suppresses the internal LOS circuitry and LOS will never assert nor LOS be declared when operating with
Receive Monitor Mode enabled.
NOTE: The results of extensive testing indicate that even when the Equalizer was enabled, regardless of the cable length,
the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial Temperature.
3.4
Clock and Data Recovery
The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream
and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the
following two modes:
3.4.1
Data/Clock Recovery Mode
In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk_n out pins is the Recovered Clock signal.
3.4.2
Training Mode
In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the
recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of
Lock condition is declared by toggling RLOL_n output pin “High” or setting the RLOL_n bit to “1” in the control
register. Also, the clock output on the RxClk_n pins are the same as the reference channel clock.
3.5
3.5.1
LOS (Loss of Signal) Detector
DS3/STS-1 LOS Condition
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.
When the DLOS condition occurs, the DLOS_n bit is set to “1” in the status control register. DLOS condition is
cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses. Analog Loss of
Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the threshold as shown
in the Table 3.The status of the ALOS condition is reflected in the ALOS_n status control register. RLOS is the
logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled
“High” and the RLOS_n bit is set to “1” in the status control register.
22
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 3: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
REQEN (DS3 AND STS-1 APPLICATIONS)
SIGNAL LEVEL TO DECLARE ALOS
DEFECT
SIGNAL LEVEL TO CLEAR ALOS
DEFECT
0
< 41mVpk
> 102mVpk
1
< 52mVpk
> 117mVpk
0
< 51mVpk
> 114mVpk
1
< 58mVpk
> 133mVpk
APPLICATION REQEN SETTING
DS3
STS-1
3.5.2
Disabling ALOS/DLOS Detection
For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a “1” to both
ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis.
3.5.3
E3 LOS Condition:
If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the
LOS condition is detected. Loss of signal is defined as no transitions for 10 to 255 consecutive zeros. No
transitions is defined as a signal level between 15 and 35 dB below the normal. This is illustrated in Figure 8.
The LOS condition is cleared within 10 to 255 UI after restoration of the incoming line signal. Figure 9 shows
the LOS declaration and clearance conditions.
FIGURE 8. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB
-15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
23
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 9. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.
Actual Occurrence
of LOS Condition
Line Signal
is Restored
RTIP/
RRing
10 UI
255 UI
Time Range for
LOS Declaration
10 UI
255 UI
RLOS Output Pin
0 UI
0 UI
G.775
Compliance
3.5.4
Time Range for
LOS Clearance
G.775
Compliance
Interference Tolerance
For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error free clock and
data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same
recommendation is being used. Figure 10 shows the configuration to test the interference margin for DS3/
STS1. Figure 11 shows the set up for E3.
FIGURE 10. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
Attenuator
N
Sine Wave
Generator
DS3 = 22.368 MHz
STS-1 = 25.92 MHz
DUT
XRT73R12
∑
Test
Equipment
Cable Simulator
Pattern Generator
2 23 -1 PRBS
S
FIGURE 11. INTERFERENCE MARGIN TEST SET UP FOR E3.
Attenuator 1
Sine Wave
Generator
17.184mHz
Attenuator 2
N
∑
DUT
XRT73R12
Test
Equipment
Signal Source
223-1 PRBS
Cable Simulator
S
24
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 4: INTERFERENCE MARGIN TEST RESULTS
MODE
CABLE LENGTH (ATTENUATION)
INTERFERENCE TOLERANCE
Equalizer “IN”
E3
DS3
STS-1
3.5.5
-17 dB
0 dB
12 dB
-14 dB
0 feet
-15 dB
225 feet
-15 dB
450 feet
-14 dB
0 feet
-15 dB
225 feet
-14 dB
450 feet
-14 dB
Muting the Recovered Data with LOS condition:
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the
internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n
pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to “1”.
NOTE: When the LOS condition is cleared, the recovered data is output on RxPOS_n and RxNEG_n pins.
FIGURE 12. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING
tRRX
tFRX
RxClk
tLCVO
LCV
tCO
RPOS or
RNEG
25
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
SYMBOL
RxClk
PARAMETER
Duty Cycle
MIN
TYP
MAX
UNITS
45
50
55
%
RxClk Frequency
E3
34.368
MHz
DS-3
44.736
MHz
STS-1
51.84
MHz
tRRX
RxClk rise time (10% o 90%)
2
4
ns
tFRX
RxClk falling time (10% to 90%)
2
4
ns
tCO
RxClk to RPOS/RNEG delay time
4
ns
tLCVO
3.6
RxClk to rising edge of LCV output delay
2.5
ns
B3ZS/HDB3 Decoder
The decoder block takes the output from the clock and data recovery block and decodes the B3ZS (for DS3 or
STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data
stream. Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or
contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on
the RLCV_n output pins to indicate line code violation.
26
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
4.0 THE TRANSMITTER SECTION
The transmitter is designed so that the LIU can accept serial data from a local device, encode the data
properly, and then output an analog pulse according to the pulse shape chosen in the appropriate registers.
This section describes the detailed operation of various blocks within the transmit path. A simplified block
diagram of the transmit path is shown in Figure 13.
FIGURE 13. TRANSMIT PATH BLOCK DIAGRAM
TTIP_n
TRing_n
MTIP_n
MRing_n
Line
Driver
Device
Monitor
Tx
Pulse
Shaping
Timing
Control
MUX
Tx
Control
TxClk_n
TxPOS_n
TxNEG_n
TxON
DMO_n
4.1
HDB3/
B3ZS
Encoder
Channel n
Transmit Digital Input Interface
The method for applying data to the transmit inputs of the LIU is a serial interface consisting of TxClk, TxPOS,
and TxNEG. For single rail mode, only TxClk and TxPOS are necessary for providing the local data from a
Framer device or ASIC. Data can be sampled on either edge of the input clock signal by programming the
appropriate register. A typical interface is shown in Figure 14.
FIGURE 14. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT73R12 (DUAL-RAIL DATA)
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
TxPOS
TPData
TxNEG
TNData
TxLineClk
TxClk
Transmit
Logic
Block
Exar E3/DS3/STS-1 LIU
27
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 15. TRANSMITTER TERMINAL INPUT TIMING
tRTX
tFTX
TxClk
tTSU
tTHO
TPData or
TNData
TTIP or
TRing
SYMBOL
TxClk
PARAMETER
Duty Cycle
MIN
TYP
MAX
UNITS
30
50
70
%
TxClk Frequency
E3
34.368
MHz
DS-3
44.736
MHz
STS-1
51.84
MHz
tRTX
TxClk Rise Time (10% to 90%)
4
ns
tFTX
TxClk Fall Time (10% to 90%)
4
ns
tTSU
TPData/TNData to TxClk falling set up time
3
ns
tTHO
TPData/TNData to TxClk falling hold time
3
ns
FIGURE 16. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)
Data
0
1
1
TPData
TxClk
28
0
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 17. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED)
Data
0
1
1
0
TPData
TNData
TxClk
4.2
Transmit Clock
The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736
MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle
clock to the pulse shaping circuit. This allows a 30% to 70% duty cycle Transmit Clock to be supplied.
4.3
B3ZS/HDB3 ENCODER
When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS
format (for either DS3 or STS-1) or HDB3 format (for E3).
4.3.1
B3ZS Encoding
An example of B3ZS encoding is shown in Figure 18. If the encoder detects an occurrence of three
consecutive zeros in the data stream, it is replaced with either B0V or 00V, where ‘B’ refers to Bipolar pulse
that is compliant with the Alternating polarity requirement of the AMI (Alternate Mark Inversion) line code and
‘V’ refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of B0V or
00V is made so that an odd number of bipolar pulses exist between any two consecutive violation (V) pulses.
This avoids the introduction of a DC component into the line signal.
FIGURE 18. B3ZS ENCODING FORMAT
TClk
4.3.2
TPDATA
1
0
Line
Signal
1
0
1 1
1
0
0
0
0
0
0
V
0
1
1
1
0
0
0
0
0
V
0
0
0
B
0
V
0
B
0
0
V
HDB3 Encoding
An example of the HDB3 encoding is shown in Figure 19. If the HDB3 encoder detects an occurrence of four
consecutive zeros in the data stream, then the four zeros are substituted with either 000V or B00V pattern. The
substitution code is made in such a way that an odd number of pulses exist between any consecutive V pulses.
This avoids the introduction of DC component into the analog signal.
29
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 19. HDB3 ENCODING FORMAT
TClk
4.4
TPDATA
1
0
Line
Signal
1
0
1 1
1
0
0
0
0
0
0
0
V
1
1
0
0
0
0
0
0
1
0
0
0
0
0
B
0
0
V
V
TRANSMIT PULSE SHAPER
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark
Inversion (AMI) pulse that meets the industry standard mask template requirements for STS-1 and DS3. For
E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped
pulse with very little slope. The Pulse Shaper Block also includes a Transmit Build Out Circuit, which can
either be disabled or enabled by setting the TxLEV_n bit to “1” or “0” in the control register. For DS3/STS-1
rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that transmit pulse
template requirements are met at the Cross-Connect system. The distance between the transmitter output and
the Cross-Connect system can be between 0 to 450 feet. For E3 rate, since the output pulse template is
measured at the secondary of the transformer and since there is no Cross-Connect system pulse template
requirements, the Transmit Build Out Circuit is always disabled. The differential line driver increases the
transmit waveform to appropriate level and drives into the 75Ω load as shown in Figure 20.
FIGURE 20. TRANSMIT PULSE SHAPE TEST CIRCUIT
R1
TxPOS(n)
TxNEG(n)
TxLineClk(n)
TTIP(n)
TPData(n)
TNData(n)
TxClk(n)
TRing(n)
31.6Ω +1%
R2
31.6Ω + 1%
4.4.1
R3
75Ω
1:1
Guidelines for using Transmit Build Out Circuit
If the distance between the transmitter and the DSX3 or STSX-1, Cross-Connect system, is less than 225 feet,
enable the Transmit Build Out Circuit by setting the TxLEV_n control bit to “0”. If the distance between the
transmitter and the DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit.
30
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
4.5
REV. 1.0.2
E3 line side parameters
The XRT73R12 line output at the transformer output meets the pulse shape specified in ITU-T G.703 for
34.368 Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in
Figure 21.
FIGURE 21. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703
17 n s
(14.55 + 2.45)
8.65 n s
V = 100%
N om inal P ulse
50%
14.55ns
12.1ns
(14.55 - 2.45)
10%
0%
10%
20%
31
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 5: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
PARAMETER
MIN
TYP
MAX
UNITS
0.90
1.00
1.10
Vpk
Transmit Output Pulse Amplitude Ratio
0.95
1.00
1.05
Transmit Output Pulse Width
12.5
14.55
16.5
ns
0.02
0.05
UIPP
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
(Measured at secondary of the transformer)
Transmit Intrinsic Jitter
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable)
900
1200
feet
Interference Margin
-20
-14
dB
Jitter Tolerance @ Jitter Frequency 800KHz
0.15
0.28
UIPP
Signal level to Declare Loss of Signal
-35
dB
Signal Level to Clear Loss of Signal
-15
Occurence of LOS to LOS Declaration Time
10
255
UI
Termination of LOS to LOS Clearance Time
10
255
UI
NOTE: The above values are at TA = 250C and VDD = 3.3 V± 5%.
32
dB
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 22. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
ST S-1 Pulse T emplate
1.2
1
Norm a liz e d Am plitude
0.8
0.6
Lower Curve
Upper Curve
0.4
0.2
0
2
3
4
1.
1.
1.
1
1
8
9
0.
0.
1.
6
7
5
0.
0.
4
0.
0.
2
3
0.
0.
0
1
0.
.1
-0
.2
.3
-0
-0
.4
.5
-0
-0
.6
.7
-0
-0
.9
.8
-0
-0
-1
-0.2
Time, in UI
TABLE 6: STS-1 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS
NORMALIZED AMPLITUDE
LOWER CURVE
- 0.03
-0.85 < T < -0.38
-0.38
·
π
T 
0.5 1 + sin  ---  1 + -----------   – 0.03
2
0.18


< T < 0.36
- 0.03
0.36 < T < 1.4
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.26
·
π
T 
0.5 1 + sin  --- 1 + -----------   + 0.03

0.34  
2
0.26 < T < 1.4
0.1 + 0.61 x e-2.4[T-0.26]
33
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 7: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)
PARAMETER
MIN
TYP
MAX
UNITS
0.65
0.75
0.90
Vpk
0.90
1.00
1.10
Vpk
Transmit Output Pulse Width
8.6
9.65
10.6
ns
Transmit Output Pulse Amplitude Ratio
0.90
1.00
1.10
0.02
0.05
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
(measured with TxLEV = 0)
Transmit Output Pulse Amplitude
(measured with TxLEV = 1)
Transmit Intrinsic Jitter
UIpp
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable)
900
Jitter Tolerance @ Jitter Frequency 400 KHz
0.15
1100
feet
UIpp
Signal Level to Declare Loss of Signal
Refer to Table 3
Signal Level to Clear Loss of Signal
Refer to Table 3
NOTE: The above values are at TA = 250C and VDD = 3.3 V ± 5%.
FIGURE 23. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499
DS3 Pulse T emplate
1.2
1
0.6
Lower Curve
Upper Curve
0.4
0.2
0
Tim e , in UI
34
2
3
4
1.
1.
1.
1
1
9
0.
1.
7
8
0.
0.
5
6
0.
0.
3
4
0.
2
0.
0.
0
1
0.
.1
-0
.3
.2
-0
-0
.4
.5
-0
-0
.6
.7
-0
-0
.9
-0
-0
.8
-0.2
-1
Norm a liz e d Am plitude
0.8
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 8: DS3 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS
NORMALIZED AMPLITUDE
LOWER CURVE
- 0.03
-0.85 < T < -0.36
-0.36
·
π
T 
0.5 1 + sin  --- 1 + -----------   – 0.03


2
0.18


< T < 0.36
- 0.03
0.36 < T < 1.4
UPPER CURVE
-0.85 < T < -0.68
0.03
-0.68 < T < 0.36
·
π
T 
0.5 1 + sin  --- 1 + -----------   + 0.03

0.34  
2
0.36 < T < 1.4
0.08 + 0.407 x e-1.84[T-0.36]
TABLE 9: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499)
PARAMETER
MIN
TYP
MAX
UNITS
0.65
0.75
0.85
Vpk
0.90
1.00
1.10
Vpk
Transmit Output Pulse Width
10.10
11.18
12.28
ns
Transmit Output Pulse Amplitude Ratio
0.90
1.00
1.10
0.02
0.05
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
(measured with TxLEV = 0)
Transmit Output Pulse Amplitude
(measured with TxLEV = 1)
Transmit Intrinsic Jitter
UIpp
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable)
900
Jitter Tolerance @ 400 KHz (Cat II)
0.15
1100
UIpp
Signal Level to Declare Loss of Signal
Refer to Table 3
Signal Level to Clear Loss of Signal
Refer to Table 3
NOTE: The above values are at TA = 250C and VDD = 3.3V ± 5%.
35
feet
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
4.6
Transmit Drive Monitor
This feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on
the line or a defective line driver. To activate this function, connect MTIP_n pins to the TTIP_n lines via a 270Ω
resistor and MRing_n pins to TRing_n lines via 270Ω resistor as shown in Figure 24.
FIGURE 24. TRANSMIT DRIVER MONITOR SET-UP.
R1
TTIP(n)
31.6Ω +1%
R3
75Ω
R2
TxPOS(n)
TxNEG(n)
TxLineClk(n)
TRing(n)
TPData(n)
TNData(n)
TxClk(n)
31.6Ω + 1%
1:1
R1
MTIP(n)
270Ω
R2
MRing(n)
270Ω
When the MTIP_n and MRing_n are connected to the TTIP_n and TRing_n lines, the drive monitor circuit
monitors the line for transitions. The DMO_n (Drive Monitor Output) will be asserted “Low” as long as the
transitions on the line are detected via MTIP_n and MRing_n. If no transitions on the line are detected for 128
± 32 TxClk_n periods, the DMO_n output toggles “High” and when the transitions are detected again, DMO_n
toggles “Low”.
NOTE: The Drive Monitor Circuit is only for diagnostic purpose and does not have to be used to operate the transmitter.
4.7
Transmitter Section On/Off
The transmitter section of each channel can either be turned on or off. To turn on the transmitter, set the input
pin TxON to “High” and write a “1” to the TxON_n control bit. When the transmitter is turned off, TTIP_n and
TRing_n are tri-stated.
NOTES:
1.
This feature provides support for Redundancy.
2.
If the XRT73R12 is configured in Host mode, to permit a system designed for redundancy to quickly shut-off the
defective line card and turn on the back-up line card, writing a “1” to the TxON_n control bits transfers the control
to TxON pin.
36
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
5.0 JITTER
There are three fundamental parameters that describe circuit performance relative to jitter
• Jitter Tolerance
• Jitter Transfer
• Jitter Generation
5.1
JITTER TOLERANCE
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 25, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence. Input jitter tolerance requirements are specified in terms of
compliance with jitter mask which is represented as a combination of points. Each point corresponds to a
minimum amplitude of sinusoidal jitter at a given jitter frequency.
FIGURE 25. JITTER TOLERANCE MEASUREMENTS
Pattern
Generator
Data
Error
Detector
DUT
XRT73R12
Clock
Modulation
Freq.
FREQ
Synthesizer
5.1.1
DS3/STS-1 Jitter Tolerance Requirements
Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II.
The jitter tolerance requirement for Category II is the most stringent. Figure 26 shows the jitter tolerance curve
as per GR-499 specification.
37
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
JITTER AMPLITUDE (UIpp)
FIGURE 26. INPUT JITTER TOLERANCE FOR DS3/STS-1
64
GR-253 STS-1
41
15
GR-499 Cat II
GR-499 Cat I
10
XRT73R12
5
1.5
0.3
0.15
0.1
0.01
0.03
0.3
2
20
100
JITTER FREQUENCY (kHz)
5.1.2
E3 Jitter Tolerance Requirements
ITU-T G.823 standard specifies that the clock and data recovery unit must be able to tolerate jitter up to certain
specified limits. Figure 27 shows the tolerance curve.
FIGURE 27. INPUT JITTER TOLERANCE FOR E3
ITU-T G.823
JITTER AMPLITUDE (UI pp)
64
XRT73R12
10
1.5
0.3
0.1
1
10
800
JITTER FREQUENCY (kHz)
As shown in the Figures above, in the jitter tolerance measurement, the dark line indicates the minimum level
of jitter that the E3/DS3/STS-1 compliant component must tolerate. Table 10 below shows the jitter amplitude
versus the modulation frequency for various standards.
38
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 10: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
INPUT JITTER AMPLITUDE (UI P-P)
BIT RATE
(KB/S)
STANDARD
34368
MODULATION FREQUENCY
A1
A2
A3
F1(HZ)
F2(HZ)
F3(KHZ)
F4(KHZ)
F5(KHZ)
ITU-T G.823
1.5
0.15
-
100
1000
10
800
-
44736
GR-499
CORE Cat I
5
0.1
-
10
2.3k
60
300
-
44736
GR-499
CORE Cat II
10
0.3
-
10
669
22.3
300
-
51840
GR-253
CORE Cat II
15
1.5
0.15
10
30
300
2
20
5.2
JITTER TRANSFER
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as
the highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a
low bandwidth loop, typically using a voltage-controlled crystal oscillator (VCXO).
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter.
Table 11 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
TABLE 11: JITTER TRANSFER SPECIFICATION/REFERENCES
E3
DS3
STS-1
ETSI TBR-24
GR-499 CORE section 7.3.2
Category I and Category II
GR-253 CORE section 5.6.2.1
NOTE: The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates.
TABLE 12: JITTER TRANSFER PASS MASKS
RATE
(KBITS)
MASK
F1
(HZ)
F2
(HZ)
F3
(HZ)
F4
(KHZ)
A1(dB)
A2(dB)
34368
G.823
ETSI-TBR-24
100
300
3K
800K
0.5
-19.5
44736
GR-499, Cat I
GR-499, Cat II
GR-253 CORE
10
10
10
10k
56.6k
40
-
15k
300k
15k
0.1
0.1
0.1
-
51840
GR-253 CORE
10
40k
-
400k
0.1
-
39
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
JITTER AMPLITUDE
FIGURE 28. JITTER TRANSFER REQUIREMENTS
A1
A2
F1
F2
F3
F4
J IT T E R F R E Q U E N C Y (k H z )
5.2.1
JITTER GENERATION
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and
data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is
essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set
according to the data rate. In general, the jitter is measured over a band of frequencies.
40
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
6.0 DIAGNOSTIC FEATURES
6.1
PRBS Generator and Detector
The XRT73R12 contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for
diagnostic purpose. With the PRBSEN_n bit = “1”, the transmitter will send out PRBS of 223-1 in E3 rate or
215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detector is also enabled. When the correct
PRBS pattern is detected by the receiver, the RNEG/LCV pin will go “Low” to indicate PRBS synchronization
has been achieved. When the PRBS detector is not in sync the PRBSLS bit will be set to “1” and RNEG/LCV
pin will go “High”.
With the PRBS mode enabled, the user can also insert a single bit error by toggling “INSPRBS” bit. This is
done by writing a “1” to INSPRBS bit. The receiver at RNEG/LCV pin will pulse “High” for one RxClk cycle for
every bit error detected. Any subsequent single bit error insertion must be done by first writing a “0” to
INSPRBS bit and followed by a “1”.
Figure 29 shows the status of RNEG/LCV pin when the XRT73R12 is configured in PRBS mode.
NOTE: In PRBS mode, the device is forced to operate in Single-Rail Mode.
FIGURE 29. PRBS MODE
RxClk
SYNC LOSS
RxNEG/LCV
PRBS SYNC
Single Bit Error
41
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
6.2
LOOPBACKS
The XRT73R12 offers three loopback modes for diagnostic purposes. The loopback modes are selected via
the RLB_n and LLB_n bits n the Channel control registers select the loopback modes.
6.2.1
ANALOG LOOPBACK
In this mode, the transmitter outputs TTIP_n and TRing_n are internally connected to the receiver inputs
RTIP_n and RRing_n as shown in Figure 30. Data and clock are output at RxClk_n, RxPOS_n and RxNEG_n
pins for the corresponding transceiver. Analog loopback exercises most of the functional blocks of the device.
NOTES:
1.
In the Analog loopback mode, data is also output via TTIP_n and TRing_n pins.
2.
Signals on the RTIP_n and RRing_n pins are ignored during analog loopback.
FIGURE 30. ANALOG LOOPBACK
TxClk
TxPOS
HDB3/B3ZS
ENCODER
TxNEG
RxClk
RxPOS
RxNEG
HDB3/B3ZS
DECODER
TIMING
CONTROL
DATA &
CLOCK
RECOVERY
42
TTIP
Tx
TRing
RTIP
Rx
RRing
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
6.2.2
REV. 1.0.2
DIGITAL LOOPBACK
When the Digital Loopback is selected, the transmit clock TxClk_n and transmit data inputs (TxPOS_n &
TxNEG_n are looped back and output onto the RxClk_n, RxPOS_n and RxNEG_n pins as shown in
Figure 31.
FIGURE 31. DIGITAL LOOPBACK
TxCLK
TxPOS
HDB3/B3ZS
ENCODER
TIMING
CONTROL
TxNEG
RxCLK
RxPOS
DATA &
CLOCK
RECOVERY
HDB3/B3ZS
DECODER
RxNEG
6.2.3
TTIP
Tx
TRing
RTIP
Rx
RRing
REMOTE LOOPBACK
With Remote loopback activated as shown in Figure 32, the receive data on RTIP and RRing is looped back
after the Data and Clock Recovery to the transmit path using RxClk as transmit timing. The receive data is
also output via the RxPOS and RxNEG pins.
NOTE: Input signals on TxClk, TxPOS and TxNEG are ignored during Remote loopback.
FIGURE 32. REMOTE LOOPBACK
TxCLK
TxPOS
HDB3/B3ZS
ENCODER
TIMING
CONTROL
TxNEG
TRing
RxCLK
RxPOS
TTIP
Tx
DATA &
CLOCK
RECOVERY
HDB3/B3ZS
DECODER
RxNEG
43
RTIP
Rx
RRing
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
6.3
TRANSMIT ALL ONES (TAOS)
Transmit All Ones (TAOS) can be set by setting the TAOS_n control bits to “1” in the Channel control registers.
When the TAOS is set, the Transmit Section generates and transmits a continuous AMI all “1’s” pattern on
TTIP_n and TRing_n pins. The frequency of this ones pattern is determined by TxClk_n. the TAOS data path
is shown in Figure 33. TAOS does not operate in Analog loopback or Remote loopback modes, however will
function in Digital loopback mode.
FIGURE 33. TRANSMIT ALL ONES (TAOS)
TxCLK
TxPOS
HDB3/B3ZS
ENCODER
TIMING
CONTROL
TxNEG
Tx
TTIP
Transmit All 1's
TRing
TAOS
RxCLK
RxPOS
DATA &
CLOCK
RECOVERY
HDB3/B3ZS
DECODER
RxNEG
44
RTIP
Rx
RRing
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
7.0 MICROPROCESSOR INTERFACE BLOCK
The Microprocessor Interface section supports communication between the local microprocessor (µP) and the
LIU. The XRT73R12 supports a parallel interface asynchronously or synchronously timed to the LIU. The microprocessor interface is selected by the state of the Pmode input pin. Selecting the microprocessor interface
mode is shown in Table 13.
TABLE 13: SELECTING THE MICROPROCESSOR INTERFACE MODE
PMODE
MICROPROCESSOR MODE
"Low"
Asynchronous Mode
"High"
Synchronous Mode
The local µP configures the LIU by writing data into specific addressable, on-chip Read/Write registers. The
µP provides the signals which are required for a general purpose microprocessor to read or write data into
these registers. The µP also supports polled and interrupt driven environments. A simplified block diagram of
the microprocessor is shown in Figure 34.
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK
CS
WR
RD
Addr[7:0]
D[7:0]
PCLK
Microprocessor
Interface
Pmode
RESET
RDY
INT
45
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS
The LIU may be configured into different operating modes and have its performance monitored by software
through a standard microprocessor using data, address and control signals. These interface signals are described below in Table 14. The microprocessor interface can be configured to operate in Asynchronous mode
or Synchronous mode.
TABLE 14: XRT73R12 MICROPROCESSOR INTERFACE SIGNALS
PIN NAME
TYPE
DESCRIPTION
Pmode
I
D[7:0]
I/O
Addr[7:0]
I
Eight-Bit Address Bus Inputs
The XRT73R12 LIU microprocessor interface uses a direct address bus. This address bus is
provided to permit the user to select an on-chip register for Read/Write access.
CS
I
Chip Select Input
This active low signal selects the microprocessor interface of the XRT73R12 LIU and enables
Read/Write operations with the on-chip register locations.
RD
I
Read Signal This active low input functions as the read signal from the local µP. When this
pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read operation has been
requested and begins the process of the read cycle.
WR
I
Write Signal This active low input functions as the write signal from the local µP. When this
pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write operation has been
requested and begins the process of the write cycle.
RDY
O
Ready Output This active low signal is provided by the LIU device. It indicates that the current read or write cycle is complete, and the LIU is waiting for the next command.
INT
O
Interrupt Output This active low signal is provided by the LIU to alert the local mP that a
change in alarm status has occured. This pin is Reset Upon Read (RUR) once the alarm status registers have been cleared.
RESET
I
Reset Input This active low input pin is used to Reset the LIU.
Microprocessor Interface Mode Select Input pin
This pin is used to specify the microprocessor interface mode.
Bi-Directional Data Bus for register "Read" or "Write" Operations.
46
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION
Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The
synchronous mode requires an input clock (PCLK) to be used as the microprocessor timing reference. Read
and Write operations are described below.
Read Cycle (For Pmode = "0" or "1")
Whenever the local µP wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the µP and
the LIU microprocessor interface block.
3. Next, the µP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action enables the bi-directional data bus output drivers of the LIU.
4. After the µP toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inform the µP that the data is available to be read by the µP, and that it is ready for the next command.
5. After the µP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
6. The CS input pin must be pulled "High" before a new command can be issued.
Write Cycle (For Pmode = "0" or "1")
Whenever a local µP wishes to write a byte or word of data into a register within the LIU, it should do the following.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the µP and
the LIU microprocessor interface block.
3. The µP should then place the byte or word that it intends to write into the target register, on the bi-directional data bus D[7:0].
4. Next, the µP should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action enables the bi-directional data bus input drivers of the LIU.
5. After the µP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inform the µP that the data has been written into the internal register location, and that it is ready for the
next command.
6. The CS input pin must be pulled "High" before a new command can be issued.
FIGURE 35. ASYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
WRITE OPERATION
t0
t0
Addr[7:0]
Valid Address
Valid Address
CS
D[7:0]
Valid Data for Readback
Data Available to Write Into the LIU
t1
RD
t3
WR
t2
t4
RDY
47
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 15: ASYNCHRONOUS TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to RD Assert
0
-
ns
t2
RD Assert to RDY Assert
-
65
ns
RD Pulse Width (t2)
70
-
ns
t3
CS Falling Edge to WR Assert
0
-
ns
t4
WR Assert to RDY Assert
-
65
ns
70
-
ns
NA
NA
WR Pulse Width (t4)
FIGURE 36. SYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
WRITE OPERATION
PCLK
t0
t0
Addr[7:0]
Valid Address
Valid Address
CS
D[7:0]
Valid Data for Readback
Data Available to Write Into the LIU
t1
RD
t3
WR
t2
t4
RDY
TABLE 16: SYNCHRONOUS TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to RD Assert
0
-
ns
t2
RD Assert to RDY Assert
-
35
RD Pulse Width (t2)
40
-
ns
t3
CS Falling Edge to WR Assert
0
-
ns
t4
WR Assert to RDY Assert
-
35
WR Pulse Width (t4)
40
-
PCLK Period
15
NA
NA
PCLK Duty Cycle
PCLK "High/Low" time
48
ns, see note 1
ns, see note 1
ns
ns
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
NOTE: 1. This timing parameter is based on the frequency of the synchronous clock (PCLK). To determine the access
time, use the following formula: (PCLKperiod * 2) + 5ns
7.3
Register Map
TABLE 17: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT73R12
ADDRESS
(HEX)
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
0x00
CR0
APST
R/W
REGISTER NAME
APS Transmit Redundancy Control Register 0-5
CHANNEL 0 CONTROL REGISTERS
0x01
CR1
IER0
R/W
Source Level Interrupt Enable Register - Ch 0
0x02
CR2
ISR0
RUR
Source Level Interrupt Status Register Ch 0
0x03
CR3
AS0
R/O
Alarm Status Register - Ch 0
0x04
CR4
TC0
R/W
Transmit Control Register - Ch 0
0x05
CR5
RC0
R/W
Receive Control Register - Ch 0
0x06
CR6
CC0
R/W
Channel Control Register - Ch 0
0x07
CR7
0x08
CR8
APSR
R/W
APS Receive Redundancy Control Register 0-5
0x0A
CR10
EM0
R/W
Error counter MS Byte Ch 0
0x0B
CR11
EL0
R/W
Error counter LS Byte
0x0C
CR12
EH0
R/W
Error counter Holding register
Reserved
0x09
0x0D
0x0E
0x0F
0x10
CHANNEL 1 CONTROL REGISTERS
0x11
CR17
IER1
R/W
Source Level Interrupt Enable Register - Ch 1
0x12
CR18
ISR1
RUR
Source Level Interrupt Status Register - Ch 1
0x13
CR19
AS1
R/O
Alarm Status Register - Ch 1
0x14
CR20
TC0
R/W
Transmit Control Register - Ch 1
0x15
CR21
RC1
R/W
Receive Control Register - Ch 1
0x16
CR22
CC1
R/W
Channel Control Register - Ch 1
0x17
CR23
Reserved
0x18
0x19
0x1A
CR26
EM1
R/W
49
Error counter MSByte Ch 1
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
ADDRESS
(HEX)
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
0x1B
CR27
EL1
R/W
Error counter LSbyte
0x1C
CR28
EH1
R/W
Error counter Holding register
REGISTER NAME
0x1D
0x1E
0x1F
0x20
CHANNEL 2 CONTROL REGISTERS
0x21
CR33
IER2
R/W
Source Level Interrupt Enable Register - Ch 2
0x22
CR34
ISR2
RUR
Source Level Interrupt Status Register - Ch 2
0x23
CR35
AS2
R/O
Alarm Status Register - Ch 2
0x24
CR36
TC2
R/W
Transmit Control Register - Ch 2
0x25
CR37
RC2
R/W
Receive Control Register - Ch 2
0x26
CR38
CC2
R/W
Channel Control Register - Ch 2
0x27
CR39
Reserved
0x28
0x29
0x2A
CR42
EM2
R/W
Error counter MSByte Ch 2
0x2B
CR43
EL2
R/W
Error counter LSbyte
0x2C
CR44
EH2
R/W
Error counter Holding register
0x2D
0x2E
0x2F
0x30
CHANNEL 3 CONTROL REGISTERS
0x31
CR49
IER3
R/W
Source Level Interrupt Enable Register - Ch 3
0x32
CR50
ISR3
RUR
Source Level Interrupt Status Register - Ch 3
0x33
CR51
AS3
R/O
Alarm Status Register - Ch 3
0x34
CR52
TC3
R/W
Transmit Control Register - Ch 3
0x35
CR53
RC3
R/W
Receive Control Register - Ch 3
0x36
CR54
CC3
R/W
Channel Control Register - Ch 3
0x37
CR55
Reserved
0x38
0x39
50
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
ADDRESS
(HEX)
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
0x3A
CR58
EM3
R/W
Error counter MSByte Ch 3
0x3B
CR59
EL3
R/W
Error counter LSbyte
0x3C
CR60
EH3
R/W
Error counter Holding register
REGISTER NAME
0x3D
0x3E
0x3F
0x40
CHANNEL 4 CONTROL REGISTERS
0x41
CR65
IER4
R/W
Source Level Interrupt Enable Register - Ch 4
0x42
CR66
ISR4
RUR
Source Level Interrupt Status Register - Ch 4
0x43
CR67
AS4
R/O
Alarm Status Register - Ch 4
0x44
CR68
TC4
R/W
Transmit Control Register - Ch 4
0x45
CR69
RC4
R/W
Receive Control Register - Ch 4
0x46
CR70
CC4
R/W
Channel Control Register - Ch 4
0x47
CR71
Reserved
0x48
0x49
0x4A
CR74
EM4
R/W
Error counter MSByte Ch 4
0x4B
CR75
EL4
R/W
Error counter LSbyte
0x4C
CR76
EH4
R/W
Error counter Holding register
0x4D
0x4E
0x4F
0x50
CHANNEL 5 CONTROL REGISTERS
0x51
CR81
IER5
R/W
Source Level Interrupt Enable Register - Ch 5
0x52
CR82
ISR5
RUR
Source Level Interrupt Status Register - Ch 5
0x53
CR83
AS5
R/O
Alarm Status Register - Ch 5
0x54
CR84
TC5
R/W
Transmit Control Register - Ch 5
0x55
CR85
RC5
R/W
Receive Control Register - Ch 5
0x56
CR86
CC5
R/W
Channel Control Register - Ch 5
0x57
CR87
Reserved
0x58
51
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
0x5A
CR90
EM5
R/W
Error counter MSByte Ch 5
0x5B
CR91
EL5
R/W
Error counter LSbyte
0x5C
CR92
EH5
R/W
Error counter Holding register
0x60
CR96
CIE
R/W
Channel 0-5 Interrupt Enable flags
0x61
CR97
CIS
R/O
Channel 0-5 Interrupt status flags
0x6E
CR110
PN
R/O
Device Part Number Register
0x6F
CR111
VN
R/O
Chip Revision Number Register
ADDRESS
(HEX)
REGISTER NAME
0x59
0x5D
0x5E
0x5F
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x65
0x69
0x6A
0x6B
0x6C
0x6D
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
52
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADDRESS
(HEX)
REV. 1.0.2
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
REGISTER NAME
CR128
APST
R/W
APS Transmit Redundancy Control Register 6-11
0x75
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
CHANNEL 6 CONTROL REGISTERS
0x81
CR129
IER6
R/W
Source Level Interrupt Enable Register - Ch 6
0x82
CR130
ISR6
RUR
Source Level Interrupt Status Register - Ch 6
0x83
CR131
AS6
R/O
Alarm Status Register - Ch 6
0x84
CR132
TC6
R/W
Transmit Control Register - Ch 6
0x85
CR133
RC6
R/W
Receive Control Register - Ch 6
0x86
CR134
CC6
R/W
Channel Control Register - Ch 6
0x87
CR135
0x88
CR136
APSR
R/W
APS Receive Redundancy Control Register 6-11
0x8A
CR138
EM6
R/W
Error counter MSByte Ch 6
0x8B
CR139
EL6
R/W
Error counter LSbyte
0x8C
CR140
EH6
R/W
Error counter Holding register
Reserved
0x89
0x8D
0x8E
0x8F
0x90
CHANNEL 7 CONTROL REGISTERS
0x91
CR145
IER7
R/W
Source Level Interrupt Enable Register - Ch 7
0x92
CR146
ISR7
RUR
Source Level Interrupt Status Register - Ch 7
0x93
CR147
AS7
R/O
Alarm Status Register - Ch 7
0x94
CR148
TC7
R/W
Transmit Control Register - Ch 7
0x95
CR149
RC7
R/W
Receive Control Register - Ch 7
0x96
CR150
CC7
R/W
Channel Control Register - Ch 7
53
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
ADDRESS
(HEX)
COMMAND REGISTER
(DECIMAL)
0x97
CR151
LABEL
TYPE
REGISTER NAME
Reserved
0x98
0x99
0x9A
CR154
EM7
R/W
Error counter MSByte Ch 7
0x9B
CR155
EL7
R/W
Error counter LSbyte
0x9C
CR156
EH7
R/W
Error counter Holding register
0x9D
0x9E
0x9F
0xA0
CHANNEL 8 CONTROL REGISTERS
0xA1
CR161
IER8
R/W
Source Level Interrupt Enable Register - Ch 8
0xA2
CR162
ISR8
RUR
Source Level Interrupt Status Register - Ch 8
0xA3
CR163
AS8
R/O
Alarm Status Register - Ch 8
0xA4
CR164
TC8
R/W
Transmit Control Register - Ch 8
0xA5
CR165
RC8
R/W
Receive Control Register - Ch 8
0xA6
CR166
CC8
R/W
Channel Control Register - Ch 8
0xA7
CR167
Reserved
0xA8
0xA9
0xAA
CR170
EM8
R/W
Error counter MSByte Ch 8
0xAB
CR171
EL8
R/W
Error counter LSbyte
0xAC
CR172
EH8
R/W
Error counter Holding register
0xAD
0xAE
0xAF
0xB0
CHANNEL 9 CONTROL REGISTERS
0xB1
CR177
IER9
R/W
Source Level Interrupt Enable Register - Ch 9
0xB2
CR178
ISR9
RUR
Source Level Interrupt Status Register - Ch 9
0xB3
CR179
AS9
R/O
Alarm Status Register - Ch 9
0xB4
CR180
TC9
R/W
Transmit Control Register - Ch 9
0xB5
CR181
RC9
R/W
Receive Control Register - Ch 9
54
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADDRESS
(HEX)
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
0xB6
CR182
CC9
R/W
0xB7
CR183
REV. 1.0.2
REGISTER NAME
Channel Control Register - Ch 9
Reserved
0xB8
0xB9
0xBA
CR186
EM9
R/W
Error counter MSByte Ch 9
0xBB
CR187
EL9
R/W
Error counter LSbyte
0xBC
CR188
EH9
R/W
Error counter Holding register
0xBD
0xBE
0xBF
0xC0
CHANNEL 10 CONTROL REGISTERS
0xC1
CR193
IER10
R/W
Source Level Interrupt Enable Register - Ch 10
0xC2
CR194
ISR10
RUR
Source Level Interrupt Status Register - Ch 10
0xC3
CR195
AS10
R/O
Alarm Status Register - Ch 10
0xC4
CR196
TC10
R/W
Transmit Control Register - Ch 10
0xC5
CR197
RC10
R/W
Receive Control Register - Ch 10
0xC6
CR198
CC10
R/W
Channel Control Register - Ch 10
0xC7
CR199
Reserved
0xC8
0xC9
0xCA
CR202
EM10
R/W
Error counter MSByte Ch 10
0xCB
CR203
EL10
R/W
Error counter LSbyte
0xCC
CR204
EH10
R/W
Error counter Holding register
0xCD
0xCE
0xCF
0xD0
CHANNEL 11 CONTROL REGISTERS
0xD1
CR209
IER11
R/W
Source Level Interrupt Enable Register - Ch 11
0xD2
CR210
ISR11
RUR
Source Level Interrupt Status Register - Ch 11
0xD3
CR211
AS11
R/O
Alarm Status Register - Ch 11
0xD4
CR212
TC11
R/W
Transmit Control Register - Ch 11
55
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
ADDRESS
(HEX)
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
REGISTER NAME
0xD5
CR213
RC11
R/W
Receive Control Register - Ch 11
0xD6
CR214
CC11
R/W
Channel Control Register - Ch 11
0xD7
CR215
Reserved
0xD8
0xD9
0xDA
CR218
EM11
R/W
Error counter MSByte Ch 11
0xDB
CR219
EL11
R/W
Error counter LSbyte
0xDC
CR229
EH11
R/W
Error counter Holding register
0xE0
CR224
CIE
R/W
Channel 6-11 Interrupt enable flags
0xE1
CR225
CIS
R/O
Channel 6-11 Interrupt status flags
0xDD
0xDE
0xDF
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE5
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
0xF2
0xF3
0xF4
56
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ADDRESS
(HEX)
COMMAND REGISTER
(DECIMAL)
LABEL
TYPE
0xF5
0xF6
0xF7
0xF8
0xF5
0xF9
0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
57
REV. 1.0.2
REGISTER NAME
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
THE GLOBAL/CHIP-LEVEL REGISTERS
The register set, within the XRT73R12 contains ten global or chip-level registers. These registers control
operations in more than one channel or apply to the complete chip. This section will present detailed
information on the Global Registers.
TABLE 18: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS
ADDRESS
COMMAND
REGISTER
LABEL
TYPE
0x00
CR0
APST
R/W
APS Transmit Redundancy Control Register 0-5
0x08
CR8
APSR
R/W
APS Receive Redundancy Control Register 0-5
0x80
CR128
APST
R/W
APS Transmit Redundancy Control Register 6-11
0x88
CR136
APSR
R/W
APS Receive Redundancy Control Register 6-11
0x60
CR96
CIE
R/W
Channel 0-5 Interrupt Enable flags
0x61
CR97
CIS
R/O
Channel 0-5 Interrupt Status flags
0xE0
CR224
CIE
R/W
Channel 6-11 Interrupt Enable flags
0xE1
CR225
CIS
R/O
Channel 6-11 Interrupt Status flags
0x6E
CR110
PN
ROM
Device Part Number Register
0x6F
CR111
VN
ROM
Chip Revision/Version Number Register
REGISTER NAME
REGISTER DESCRIPTION - GLOBAL REGISTERS
TABLE 19: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
TxON Ch 5
TxON Ch 4
TxON Ch 3
TxON Ch 2
TxON Ch 1
TxON Ch 0
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NUMBER
NAME
7,6
Reserved
5
4
3
2
1
0
TxON Ch 5
TxON Ch 4
TxON Ch 3
TxON Ch 2
TxON Ch 1
TxON Ch 0
TYPE
DESCRIPTION
R/W
Transmit Section ON - Channel n
This READ/WRITE bit-field is used to turn on or turn off the Transmit Driver associated
with Channel n. If the user turns on the Transmit Driver, then Channel n will transmit
DS3, E3 or STS-1 pulses on the line via the TTIP_n and TRING_ n output pins.
Conversely, if the user turns off the Transmit Driver, then the TTIP_n and TRING_n
output pins will be tri-stated.
0 - Shuts off the Transmit Driver associated with Channel n and tri-states the TTIP_n
and TRING_ n output pins.
1 - Turns on the Transmit Driver associated with Channel n.
NOTE: The master TxON control pin(pin # P4) must be in a high state (logic 1) for this
operation to turn on any channel.
58
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 20: APS/REDUNDANCY RECEIVE CONTROL REGISTER - CR8 (ADDRESS LOCATION = 0X08)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
RxON Ch 5
RxON Ch 4
RxON Ch 3
RxON Ch 2
RxON Ch 1
RxON Ch 0
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NUMBER
NAME
7,6
Reserved
5
4
3
2
1
0
RxON Ch 5
RxON Ch 4
RxON Ch 3
RxON Ch 2
RxON Ch 1
RxON Ch 0
TYPE
DESCRIPTION
R/W
Receive Section ON - Channel n
This READ/WRITE bit-field is used to turn on or turn off the Receiver associated with
Channel n on a per channel basis. If the user turns on the Receiver, then Channel n
will Receive DS3, E3 or STS-1 pulses on the line via the RTIP_n and RRING_ n input
pins.
Conversely, if the user turns off the Receiver Driver (for channel n), the RTIP_n and
RRING_n input pins will be in a high impedance state.
0 - Shuts off the Receive Driver associated with Channel n and puts the RTIP_n and
RRING_ n input pins in a high impedance state.
1 - Turns on the Receive Driver associated with Channel n.
TABLE 21: APS/REDUNDANCY TRANSMIT CONTROL REGISTER - CR128 (ADDRESS LOCATION = 0X80)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
TxON Ch 11
TxON Ch 10
TxON Ch 9
TxON Ch 8
TxON Ch 7
TxON Ch 6
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NUMBER
NAME
7,6
Reserved
5
4
3
2
1
0
TxON Ch 11
TxON Ch 10
TxON Ch 9
TxON Ch 8
TxON Ch 7
TxON Ch 6
TYPE
DESCRIPTION
R/W
Transmit Section ON - Channel n
This READ/WRITE bit-field is used to turn on or turn off the Transmit Driver associated
with Channel n. If the user turns on the Transmit Driver, then Channel n will transmit
DS3, E3 or STS-1 pulses on the line via the TTIP_n and TRING_ n output pins.
Conversely, if the user turns off the Transmit Driver, then the TTIP_n and TRING_n
output pins will be tri-stated.
0 - Shuts off the Transmit Driver associated with Channel n and tri-states the TTIP_n
and TRING_ n output pins.
1 - Turns on the Transmit Driver associated with Channel n.
NOTE: The master TxON control pin(pin # P4) must be in a high state (logic 1) for this
operation to turn on any channel.
59
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 22: APS/REDUNDANCY RECEIVE CONTROL REGISTER - CR136 (ADDRESS LOCATION = 0X88)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
RxON Ch 11
RxON Ch 10
RxON Ch 9
RxON Ch 8
RxON Ch 7
RxON Ch 6
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NUMBER
NAME
7,6
Reserved
5
4
3
2
1
0
RxON Ch 11
RxON Ch 10
RxON Ch 9
RxON Ch 8
RxON Ch 7
RxON Ch 6
TYPE
DESCRIPTION
R/W
Receive Section ON - Channel n
This READ/WRITE bit-field is used to turn on or turn off the Receiver associated with
Channel n on a per channel basis. If the user turns on the Receiver, then Channel n
will Receive DS3, E3 or STS-1 pulses on the line via the RTIP_n and RRING_ n input
pins.
Conversely, if the user turns off the Receiver Driver (for channel n), the RTIP_n and
RRING_n input pins will be in a high impedance state.
0 - Shuts off the Receive Driver associated with Channel n and puts the RTIP_n and
RRING_ n input pins in a high impedance state.
1 - Turns on the Receive Driver associated with Channel n.
60
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 37. CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR96 (ADDRESS LOCATION = 0X60)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Channel 5
Interrupt
Enable
Channel 4
Interrupt
Enable
Channel 3
Interrupt
Enable
Channel 2
Interrupt
Enable
Channel 1
Interrupt
Enable
Channel 0
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NUMBER
NAME
7,6
Unused
5
4
3
2
1
0
Channel 5 Interrupt Enable
Channel 4 Interrupt Enable
Channel 3 Interrupt Enable
Channel 2 Interrupt Enable
Channel 1 Interrupt Enable
Channel 0 Interrupt Enable
TYPE
R/W
DESCRIPTION
Channel n Interrupt Enable Bit:
This READ/WRITE bit is used to:
• To enable Channel n for Interrupt Generation at the Channel
Level
• To disable all Interrupts associated with Channel n within the
XRT73R12
This is a "master" enable bit for each channel. This bit allows
control on a per channel basis to signal the Host of selected error
conditions.
If a bit is cleared, no interrupts from that channel will be sent to the
Host via the INT.
If the bit is set (logic 1), any generated interrupt in channel n that
has been enabled in the Interrupt Enable register (IERn) for the
channel will activate the INT pin to the Host.
0 - Disables all Channel n related Interrupts.
1 - Enables Channel n-related Interrupts. The user must enable
individual Channel n related Interrupts at the source level, before
they are can generate an interrupt.
61
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 23: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR224 (ADDRESS LOCATION = 0XE0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Channel 11
Interrupt
Enable
Channel 10
Interrupt
Enable
Channel 9
Interrupt
Enable
Channel 8
Interrupt
Enable
Channel 7
Interrupt
Enable
Channel 6
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
)
BIT
NUMBER
NAME
7,6
Reserved
5
4
3
2
1
0
Channel 11 Interrupt Enable
Channel 10 Interrupt Enable
Channel 9 Interrupt Enable
Channel 8 Interrupt Enable
Channel 7 Interrupt Enable
Channel 6 Interrupt Enable
TYPE
R/W
DESCRIPTION
Channel n Interrupt Enable Bit:
This READ/WRITE bit is used to:
• To enable Channel n for Interrupt Generation at the Channel
Level
• To disable all Interrupts associated with Channel n within the
XRT73R12
This is a "master" enable bit for each channel. This bit allows
control on a per channel basis to signal the Host of selected error
conditions.
If a bit is cleared, no interrupts from that channel will be sent to the
Host via the INT pin.
If the bit is set (logic 1), any generated interrupt in channel n that
has been enabled in the Interrupt Enable register (IERn) for the
channel will activate the INT pin to the Host.
0 - Disables all Channel n related Interrupts.
1 - Enables Channel n-related Interrupts. The user must enable
individual Channel n related Interrupts at the source level, before
they are can generate an interrupt.
62
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 24: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR97 (ADDRESS LOCATION = 0X61)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Channel 5
Interrupt
Status
Channel 4
Interrupt
Status
Channel 3
Interrupt
Status
Channel 2
Interrupt
Status
Channel 1
Interrupt
Status
Channel 0
Interrupt
Status
R/O
R/O
R/O
R/O
R/O
R/O
BIT
NUMBER
NAME
7, 6
Reserved
5
4
3
2
1
0
Channel 5 Interrupt Status
Channel 4 Interrupt Status
Channel 3 Interrupt Status
Channel 2 Interrupt Status
Channel 1 Interrupt Status
Channel 0 Interrupt Status
TYPE
DESCRIPTION
R/O
Channel n Interrupt Status Bit:
This READ-ONLY bit-field indicates whether the XRT73R12 has a pending
Channel n-related interrupt that is awaiting service. The first six channels
are serviced through this location and the other six at address 0xE1.
These two registers are used by the Host to identify the source channel of
an active interrupt.
0 - Indicates that there is NO Channel n-related Interrupt awaiting service.
1 - Indicates that there is at least one Channel n-related Interrupt awaiting
service. In this case, the user's Interrupt Service routine should be written
such that the Microprocessor will now proceed to read out the contents of
the Source Level Interrupt Status Register - Channel n (Address Locations
= 0xn2) to determine the exact source of the interrupt request.
NOTE: Once this bit-field is set to "1", it will not be cleared back to "0" until
the user has read out the contents of the Source-Level Interrupt
Status Register bit, that corresponds to the interrupt request
channel.
63
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 25: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR225 (ADDRESS LOCATION = 0XE1)
BIT 7
BIT 6
Reserved Reserved
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Channel 11
Interrupt
Status
Channel 10
Interrupt
Status
Channel 9
Interrupt
Status
Channel 8
Interrupt
Status
Channel 7
Interrupt
Status
Channel 6
Interrupt
Status
R/O
R/O
R/O
R/O
R/O
R/O
BIT
NUMBER
NAME
7, 6
Reserved
5
4
3
2
1
0
Channel 11 Interrupt Status
Channel 10 Interrupt Status
Channel 9 Interrupt Status
Channel 8 Interrupt Status
Channel 7 Interrupt Status
Channel 6 Interrupt Status
TYPE
DESCRIPTION
R/O
Channel n Interrupt Status Bit:
This READ-ONLY bit-field indicates whether the XRT73R12 has a
pending Channel n-related interrupt that is awaiting service. The last
six channels are serviced through this location and the other six at
address 0x61. These two registers are used by the Host to identify the
source channel of an active interrupt.
0 - Indicates that there is NO Channel n-related Interrupt awaiting service.
1 - Indicates that there is at least one Channel n-related Interrupt
awaiting service. In this case, the user's Interrupt Service routine
should be written such that the Microprocessor will now proceed to
read out the contents of the Source Level Interrupt Status Register Channel n (Address Locations = 0xn2) to determine the exact source
of the interrupt request.
NOTE: Once this bit-field is set to "1", it will not be cleared back to "0"
until the user has read out the contents of the Source-Level
Interrupt Status Register bit, that corresponds to the interrupt
request channel.
TABLE 26: DEVICE/PART NUMBER REGISTER - CR110 (ADDRESS LOCATION = 0X6E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Part Number ID Value
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
1
1
0
1
0
0
0
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
7-0
Part Number ID
Value
R/O
0x68
DESCRIPTION
Part Number ID Value:
This READ-ONLY register contains a unique value for the
XRT73R12. This value will always be 0x68.
64
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 27: CHIP REVISION NUMBER REGISTER - CR111 (ADDRESS LOCATION = 0X6F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Chip Revision Number Value
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
X
X
X
X
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
7-0
Chip Revision
Number Value
R/O
0x0#
DESCRIPTION
Chip Revision Number Value:
This READ-ONLY register contains a value that represents
the current revision of this XRT73R12. This revision number will always be in the form of "0x0#", where "#" is a hexadecimal value that specifies the current revision of the chip.
For example, the very first revision of this chip will contain
the value "0x01".
65
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
THE PER-CHANNEL REGISTERS
The XRT73R12 consists of 120 per-Channel Registers (12 channels and 10 registers per channel). Table 9
presents the overall Register Map with the Per-Channel Registers unshaded.
REGISTER DESCRIPTION - PER CHANNEL REGISTERS
TABLE 28: XRT73R12 REGISTER MAP SHOWING INTERRUPT ENABLE REGISTERS (IER_N) (N = [0:11])
ADDRESS
LOCATION
0
1
2
3
4
5
6
0x0-
APST
IER0
ISR0
AS0
TC0
RC0
CC0
0X1-
IER1
ISR1
AS1
TC1
RC1
0x2-
IER2
ISR2
AS2
TC2
0x3-
IER3
ISR3
AS3
0x4-
IER4
ISR4
0x5-
IER5
ISR5
0x6-
A
B
C
EM0
EL0
EH0
CC1
EM1
EL1
EH1
RC2
CC2
EM2
EL2
EH2
TC3
RC3
CC3
EM3
EL3
EH3
AS4
TC4
RC4
CC4
EM4
EL4
EH4
AS5
TC5
RC5
CC5
EM5
EL5
EH5
CIE
CIS
APST
IER6
ISR6
AS6
TC6
RC6
CC6
0X9-
IER7
ISR7
AS7
TC7
RC7
0xA-
IER8
ISR8
AS8
TC8
0xB-
IER9
ISR9
AS9
0xC-
IER10
ISR10
0xD-
IER11
ISR11
7
8
APSR
9
PN VN
0x70x8-
0xE-
CIE
D E F
EM6
EL6
EH6
CC7
EM7
EL7
EH7
RC8
CC8
EM8
EL8
EH8
TC9
RC9
CC9
EM9
EL9
EH9
AS10
TC10
RC10
CC10
EM10
EL10
EH10
AS11
TC11
RC11
CC11
EM11
EL11
EH11
CIS
0xF-
66
APSR
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 29: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL N ADDRESS LOCATION = 0XM1
(N = [0:11] & M= 0-5 & 8-D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Reserved
BIT NUMBER
NAME
TYPE
7-3
Reserved
R/O
2
Change of LOL
Condition Interrupt
Enable
R/W
BIT 2
BIT 1
BIT 0
Change of LOL
Condition
Interrupt Enable
Ch n
Change of LOS
Condition
Interrupt Enable
Ch n
Change of
DMO Condition
Interrupt Enable
Ch n
R/W
R/W
R/W
DESCRIPTION
Change of Receive LOL (Loss of Lock) Condition Interrupt Enable Channel n:
This READ/WRITE bit-field is used to enable or disable the Change of
Receive LOL Condition Interrupt. If the user enables this interrupt, then the
XRT73R12 will generate an interrupt any time any of the following events
occur.
• Whenever the Receive Section (within Channel n) declares the Loss of
Lock Condition.
• Whenever the Receive Section (within Channel n) clears the Loss of Lock
Condition.
0 - Disables the Change in Receive LOL Condition Interrupt.
1 - Enables the Change in Receive LOL Condition Interrupt.
1
Change of LOS
Condition Interrupt
Enable
R/W
Change of the Receive LOS (Loss of Signal) Defect Condition Interrupt
Enable - Ch 0:
This READ/WRITE bit-field is used to enable or disable the Change of the
Receive LOS Defect Condition Interrupt. If the user enables this interrupt,
then the XRT73R12 will generate an interrupt any time any of the following
events occur.
• Whenever the Receive Section (within Channel n) declares the LOS
Defect Condition.
• Whenever the Receive Section (within Channel n) clears the LOS Defect
condition.
0 - Disables the Change in the LOS Defect Condition Interrupt.
1 - Enables the Change in the LOS Defect Condition Interrupt.
0
Change of DMO
Condition Interrupt
Enable
R/W
Change of Transmit DMO (Drive Monitor Output) Condition Interrupt
Enable - Ch n:
This READ/WRITE bit-field is used to enable or disable the Change of
Transmit DMO Condition Interrupt. If the user enables this interrupt, then
the XRT73R12 will generate an interrupt any time any of the following
events occur.
• Whenever the Transmit Section toggles the DMO output pin (or bit-field)
to "1".
• Whenever the Transmit Section toggles the DMO output pin (or bit-field)
to "0".
0 - Disables the Change in the DMO Condition Interrupt.
1 - Enables the Change in the DMO Condition Interrupt.
67
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 30: XRT73R12 REGISTER MAP SHOWING INTERRUPT STATUS REGISTERS (ISR_N)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Reserved
BIT 2
BIT 1
BIT 0
Change of LOL Change of LOS Change of DMO
Condition
Condition
Condition
Interrupt Status nterrupt Status Interrupt Status
Ch_n
Ch_n
Ch_n
RUR
RUR
RUR
TABLE 31: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM2
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
7-4
Reserved
3
Change of FL Condition Interrupt Status
2
Change of LOL Condition Interrupt Status
TYPE
DESCRIPTION
This bit is reserved.
RUR
Change of Receive LOL (Loss of Lock) Condition Interrupt Status - Ch
n:
This RESET-upon-READ bit-field indicates whether or not the Change of
Receive LOL Condition Interrupt (for Channel n) has occurred since the last
read of this register.
0 - Indicates that the Change of Receive LOL Condition Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Change of Receive LOL Condition Interrupt has
occurred since the last read of this register.
NOTE: The user can determine the current state of the Receive LOL Defect
condition by reading out the contents of Bit 2 (Receive LOL Defect
Declared) within the Alarm Status Register.(n)
68
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 31: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM2
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
1
Change of LOS
Condition Interrupt
Status
RUR
Change of Receive LOS (Loss of Signal) Defect Condition Interrupt
Status:
This RESET-upon-READ bit-field indicates whether or not the Change of the
Receive LOS Defect Condition Interrupt (for Channel n) has occurred since
the last read of this register.
0 - Indicates that the Change of the Receive LOS Defect Condition Interrupt
has NOT occurred since the last read of this register.
1 - Indicates that the Change of the Receive LOS Defect Condition Interrupt
has occurred since the last read of this register.
NOTE: The user can determine the current state of the Receive LOS Defect
condition by reading out the contents of Bit 1 (Receive LOS Defect
Declared) within the Alarm Status Register.(n)
0
Change of DMO
Condition Interrupt
Status
RUR
Change of Transmit DMO (Drive Monitor Output) Condition Interrupt
Status - Ch n:
This RESET-upon-READ bit-field indicates whether or not the Change of the
Transmit DMO Condition Interrupt (for Channel n) has occurred since the
last read of this register.
0 - Indicates that the Change of the Transmit DMO Condition Interrupt has
NOT occurred since the last read of this register.
1 - Indicates that the Change of the Transmit DMO Condition Interrupt has
occurred since the last read of this register.
NOTE:
The user can determine the current state of the Transmit DMO
Condition by reading out the contents of Bit 0 (Transmit DMO
Condition) within the Alarm Status Register.(n)
69
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 32: XRT73R12 REGISTER MAP SHOWING ALARM STATUS REGISTERS (AS_N)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Reserved
Loss of PRBS
Pattern Sync
Digital LOS
Defect
Declared
Analog LOS
Defect
Declared
Reserved
R/O
R/O
R/O
R/O
BIT 2
BIT 1
Receive LOL Receive LOS
Defect
Defect
Declared
Declared
R/O
BIT 0
Transmit
DMO
Condition
R/O
R/O
TABLE 33: ALARM STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM3
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
7
Reserved
6
Loss of PRBS Pattern Lock
TYPE
DESCRIPTION
R/O
Loss of PRBS Pattern Lock Indicator:
This READ-ONLY bit-field indicates whether or not the PRBS Receiver
(within the Receive Section of Channel n) is declaring PRBS Lock within the
incoming PRBS pattern.
If the PRBS Receiver detects a very large number of bit-errors within its
incoming data-stream, then it will declare the Loss of PRBS Lock Condition.
Conversely, if the PRBS Receiver were to detect its pre-determined PRBS
pattern with the incoming DS3, E3 or STS-1 data-stream, (with little or no bit
errors) then the PRBS Receiver will clear the Loss of PRBS Lock condition.
0 - Indicates that the PRBS Receiver is currently declaring the PRBS Lock
condition within the incoming DS3, E3 or STS-1 data-stream.
1 - Indicates that the PRBS Receiver is currently declaring the Loss of PRBS
Lock condition within the incoming DS3, E3 or STs-1 data-stream.
NOTE: This register bit is only valid if all of the following are true.
a. The PRBS Generator block (within the Transmit Section of the Chip is
enabled).
b. The PRBS Receiver is enabled.
c. The PRBS Pattern (that is generated by the PRBS Generator) is
somehow looped back into the Receive Path (via the Line-Side) and
in-turn routed to the receive input of the PRBS Receiver.
70
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 33: ALARM STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM3
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
5
Digital LOS Defect
Declared
R/O
Digital LOS Defect Declared:
This READ-ONLY bit-field indicates whether or not the Digital LOS (Loss of
Signal) detector is declaring the LOS Defect condition.
For DS3 and STS-1 applications, the Digital LOS Detector will declare the
LOS Defect condition whenever it detects an absence of pulses (within the
incoming DS3 or STS-1 data-stream) for 160 consecutive bit-periods.
Further, (again for DS3 and STS-1 applications) the Digital LOS Detector will
clear the LOS Defect condition whenever it determines that the pulse density (within the incoming DS3 or STS-1 signal) is at least 33%.
0 - Indicates that the Digital LOS Detector is NOT declaring the LOS Defect
Condition.
1 - Indicates that the Digital LOS Detector is currently declaring the LOS
Defect condition.
NOTES:
4
Analog LOS Defect
Declared
R/O
1.
LOS Detection (within each channel of the XRT73R12) is
performed by both an Analog LOS Detector and a Digital LOS
Detector. The LOS state of a given Channel is simply a WIREDOR of the LOS Defect Declare states of these two detectors.
2.
The current LOS Defect Condition (for the channel) can be
determined by reading out the contents of Bit 1 (Receive LOS
Defect Declared) within this register.
Analog LOS Defect Declared:
This READ-ONLY bit-field indicates whether or not the Analog LOS (Loss of
Signal) detector is declaring the LOS Defect condition.
For DS3 and STS-1 applications, the Analog LOS Detector will declare the
LOS Defect condition whenever it determines that the amplitude of the
pulses (within the incoming DS3/STS-1 line signal) drops below a certain
Analog LOS Defect Declaration threshold level.
Conversely, (again for DS3 and STS-1 applications) the Analog LOS Detector will clear the LOS Defect condition whenever it determines that the
amplitude of the pulses (within the incoming DS3/STS-1 line signal) has
risen above a certain Analog LOS Defect Clearance threshold level.
It should be noted that, in order to prevent "chattering" within the Analog
LOS Detector output, there is some built-in hysteresis between the Analog
LOS Defect Declaration and the Analog LOS Defect Clearance threshold
levels.
0 - Indicates that the Analog LOS Detector is NOT declaring the LOS Defect
Condition.
1 - Indicates that the Analog LOS Detector is currently declaring the LOS
Defect condition.
NOTES:
1.
LOS Detection (within each channel of the XRT73R12) is
performed by both an Analog LOS Detector and a Digital LOS
Detector. The LOS state of a given Channel is simply a WIREDOR of the LOS Defect Declare states of these two detectors.
2.
The current LOS Defect Condition (for the channel) can be
determined by reading out the contents of Bit 1 (Receive LOS
Defect Declared) within this register.
3
Reserved
71
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 33: ALARM STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM3
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
2
Receive LOL Condition Declared
R/O
Receive LOL (Loss of Lock) Condition Declared:
This READ-ONLY bit-field indicates whether or not the Receive Section
(within Channel_n) is currently declaring the LOL (Loss of Lock) condition.
The Receive Section (of Channel_n) will declare the LOL Condition, if the
frequency of the Recovered Clock signal differs from that of the reference
clock programmed for that channel (from the appropriate oscillator or the
SFM clock synthesizer if in that mode) by 0.5% (or 5000ppm) or more .
0 - Indicates that the Receive Section of Channel_n is NOT currently declaring the LOL Condition.
1 - Indicates that the Receive Section of Channel_n is currently declaring
the LOL Condition and the recovered clock differs by more than 0.5%..
1
Receive LOS Defect
Condition Declared
R/O
Receive LOS (Loss of Signal) Defect Condition Declared:
This READ-ONLY bit-field indicates whether or not the Receive Section
(within Channel_n) is currently declaring the LOS defect condition.
The Receive Section (of Channel_n) will declare the LOS defect condition, if
any one of the following conditions is met.
• If the Digital LOS Detector declares the LOS defect condition (for DS3 or
STS-1 applications)
• If the Analog LOS Detector declares the LOS defect condition (for DS3 or
STS-1 applications)
• If the ITU-T G.775 LOS Detector declares the LOS defect condition (for E3
applications).
0 - Indicates that the Receive Section of Channel_n is NOT currently declaring the LOS Defect Condition.
1 - Indicates that the Receive Section of Channel_n is currently declaring
the LOS Defect condition.
0
Transmit DMO Condition Declared
R/O
Transmit DMO (Drive Monitor Output) Condition Declared:
This READ-ONLY bit-field indicates whether or not the Transmit Section of
Channel_n is currently declaring the DMO Alarm condition.
As configured, the Transmit Section will either internally (via the TTIP_n and
TRING_n ) or externally (via the MTIP_n and MRING_n) check the Transmit
Output DS3/E3/STS-1 Line signal for bipolar pulses. If the Transmit Section
were to detect no bipolar for 128 consecutive bit-periods, then it will declare
the Transmit DMO Alarm condition. This particular alarm can be used to
check for fault conditions on the Transmit Output Line Signal path.
The Transmit Section will clear the Transmit DMO Alarm condition upon
detecting bipolar activity on the Transmit Output Line signal.
0 - Indicates that the Transmit Section of Channel_n is NOT currently declaring the Transmit DMO Alarm condition.
1 - Indicates that the Transmit Section of Channel_n is currently declaring
the Transmit DMO Alarm condition.
72
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 34: XRT73R12 REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_N)
BIT 7
BIT 6
Reserved
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Internal
Transmit
Drive Monitor
Insert PRBS
Error
Reserved
TAOS
TxCLKINV
TxLEV
R/W
R/W
R/W
R/W
R/W
TABLE 35: TRANSMIT CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM4
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-6
Reserved
5
Internal Transmit
Drive Monitor
Enable
R/W
Internal Transmit Drive Monitor Enable - Channel_n:
This READ/WRITE bit-field is used to configure the Transmit Section of
Channel_n to either internally or externally monitor the TTIP_n and
TRING_n output pins for bipolar pulses, in order to determine whether to
declare the Transmit DMO Alarm condition.
If the user configures the Transmit Section to externally monitor the TTIP_n
and TRING_n output pins (for bipolar pulses) then the user must connect
the MTIP_n and MRING_n input pins to their corresponding TTIP_n and
TRING_n output pins (via a 270 ohm series resistor).
If the user configures the Transmit Section to internally monitor the TTIP_n
and TRING_n output pins (for bipolar pulses), the user does NOT need to
conect the MTIP_n and MRING_n input pins. This monitoring will be performed internally at the TTIP_n and TRING_n pads.
0 - Configures the Transmit Drive Monitor to externally monitor the TTIP_n
and TRING_n output pins for bipolar pulses.
1 - Configures the Transmit Drive Monitor to internally monitor the TTIP_n
and TRING_n output pins for bipolar pulses.
4
Insert PRBS Error
R/W
Insert PRBS Error - Channel_n:
A "0 to 1" transition within this bit-field causes the PRBS Generator (within
the Transmit Section of Channel_n) to generate a single bit error within the
outbound PRBS pattern-stream.
NOTES:
3
1.
This bit-field is only active if the PRBS Generator and Receiver
have been enabled within the corresponding Channel.
2.
After writing the "1" into this register, the user must execute a write
operation to clear this particular register bit to "0" in order to
facilitate the next "0 to 1" transition in this bit-field.
Reserved
73
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 35: TRANSMIT CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM4
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
2
TAOS
R/W
Transmit All OneS Pattern - Channel_n:
This READ/WRITE bit-field is used to command the Transmit Section of
Channel_n to generate and transmit an unframed, All Ones pattern via the
DS3, E3 or STS-1 line signal (to the remote terminal equipment).
Whenever the user implements this configuration setting, the Transmit Section will ignore the data that it is accepting from the System-side equipment
and output the "All Ones" Pattern.
0 - Configures the Transmit Section to transmit the data that it accepts from
the System-side Interface.
1 - Configures the Transmit Section to generate and transmit the Unframed,
All Ones pattern.
1
TxCLKINV
R/W
Transmit Clock Invert Select - Channel_n:
This READ/WRITE bit-field is used to select the edge of the TxCLK_n input
that the Transmit Section of Channel_n will use to sample the TxPOS_n and
TxNEG_n input pins, as described below.
0 - Configures the Transmit Section (within the corresponding channel) to
sample the TxPOS_n and TxNEG_n input pins upon the falling edge of
TxCLK_n.
1 - Configures the Transmit Section (within the corresponding channel) to
sample the TxPOS_n and TxNEG_n input pins upon the rising edge of
TxCLK_n.
NOTE: This is done on a per-channel basis.
0
TxLEV
R/W
Transmit Line Build-Out Select - Channel_n:
This READ/WRITE bit-field is used to enable or disable the Transmit Line
Build-Out (e.g., pulse-shaping) circuit within the corresponding channel.
The user should set this bit-field to either "0" or to "1" based upon the following guidelines.
0 - If the cable length between the Transmit Output (of the corresponding
Channel) and the DSX-3/STSX-1 location is 225 feet or less.
1 - If the cable length between the Transmit Output (of the corresponding
Channel) and the DSX-3/STSX-1 location is more than 225 feet .
The user must follow these guidelines in order to insure that the Transmit
Section (of Channel_n) will always generate a DS3 pulse that complies with
the Isolated Pulse Template requirements per Bellcore GR-499-CORE, or
an STS-1 pulse that complies with the Pulse Template requirements per Telcordia GR-253-CORE.
NOTE: This bit-field is ignored if the channel has been configured to operate
in the E3 Mode.
74
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 36: XRT73R12 REGISTER MAP SHOWING RECEIVE CONTROL REGISTERS (RC_N)
BIT 7
BIT 6
Reserved
BIT 5
BIT 4
Disable DLOS Disable ALOS
Detector
Detector
R/W
R/W
BIT 3
BIT 2
BIT 1
BIT 0
RxCLKINV
LOSMUT
Enable
Receive
Monitor Mode
Enable
Receive
Equalizer
Enable
R/W
R/W
R/W
R/W
TABLE 37: RECEIVE CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM5
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
7-6
Reserved
5
Disable DLOS
Detector
TYPE
R/W
DESCRIPTION
Disable Digital LOS Detector - Channel_n:
This READ/WRITE bit-field is used to enable or disable the Digital LOS
(Loss of Signal) Detector within Channel_n, as described below.
0 - Enables the Digital LOS Detector within Channel_n.
1 - Disables the Digital LOS Detector within Channel_n.
NOTE: This bit-field is only active if Channel_n has been configured to
operate in the DS3 or STS-1 Modes.
4
Disable ALOS
Detector
R/W
Disable Analog LOS Detector - Channel_n:
This READ/WRITE bit-field is used to either enable or disable the Analog
LOS (Loss of Signal) Detector within Channel_n, as described below.
0 - Enables the Analog LOS Detector within Channel_n.
1 - Disables the Analog LOS Detector within Channel_n.
NOTE: This bit-field is only active if Channel_n has been configured to
operate in the DS3 or STS-1 Modes.
3
RxCLKINV
R/W
Receive Clock Invert Select - Channel_n:
This READ/WRITE bit-field is used to select the edge of the RxCLK_n output that the Receive Section of Channel_n will use to output the recovered
data via the RxPOS_n and RxNEG_n output pins, as described below.
0 - Configures the Receive Section (within the corresponding channel) to
output the recovered data via the RxPOS_n and RxNEG_n output pins upon
the rising edge of RCLK_n.
1 - Configures the Receive Section (within the corresponding channel) to
output the recovered data via the RxPOS_n and RxNEG_n output pins upon
the falling edge of RCLK_n.
75
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 37: RECEIVE CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM5
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
2
LOSMUT Enable
R/W
Muting upon LOS Enable - Channel_n:
This READ/WRITE bit-field is used to configure the Receive Section (within
Channel_n) to automatically pull their corresponding Recovered Data Output pins (e.g., RxPOS_n and RxNEG_n) to GND for the duration that the
Receive Section declares the LOS defect condition. In other words, this feature (if enabled) will cause the Receive Channel to automatically mute the
Recovered data anytime the Receive Section declares the LOS defect condition.
0 - Disables the Muting upon LOS feature. In this setting the Receive Section will NOT automatically mute the Recovered Data whenever it is declaring the LOS defect condition.
1 - Enables the Muting upon LOS feature. In this setting the Receive Section will automatically mute the Recovered Data whenever it is declaring the
LOS defect condition.
1
Receive Monitor
Mode Enable
R/W
Receive Monitor Mode Enable - Channel_n:
This READ/WRITE bit-field is used to configure the Receive Section of
Channel_n to operate in the Receive Monitor Mode.
If the user configures the Receive Section to operate in the Receive Monitor
Mode, then it will be able to receive a nominal DSX-3/STSX-1 signal that
has been attenuator by 20dB of flat loss along with 6dB of cable loss, in an
error-free manner. However, internal LOS circuitry is suppressed and LOS
will never assert nor LOS be declared when operating under this mode.
0 - Configures the corresponding channel to operate in the Normal Mode.
1 - Configure the corresponding channel to operate in the Receive Monitor
Mode.
0
Receive Equalizer
Enable
R/W
Receive Equalizer Enable - Channel_n:
This READ/WRITE register bit is used to enable or disable the Receive
Equalizer block within the Receive Section of Channel_n, as listed below.
0 - Disables the Receive Equalizer within the corresponding channel.
1 - Enables the Receive Equalizer within the corresponding channel.
NOTE: For virtually all applications, we recommend that the user set this bitfield to "1" (for all channels) and enable the Receive Equalizer.
76
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 38: XRT73R12 REGISTER MAP SHOWING CHANNEL CONTROL REGISTERS (CC_N)
BIT 7
BIT 6
Reserved
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n
STS-1/DS3_n
SR/DR_n
R/W
R/W
R/W
R/W
R/W
R/W
TABLE 39: CHANNEL CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM6
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
7-6
Reserved
5
PRBS Enable
TYPE
DESCRIPTION
R/W
PRBS Generator and Receiver Enable - Channel_n:
This READ/WRITE bit-field is used to enable or disable the PRBS Generator
and Receiver within a given Channel of the XRT73R12.
If the user enables the PRBS Generator and Receiver, then the following will
happen.
1. The PRBS Generator (which resides within the Transmit Section of
the Channel) will begin to generate an unframed, 2^15-1 PRBS
Pattern (for DS3 and STS-1 applications) and an unframed, 2^23-1
PRBS Pattern (for E3 applications).
2. The PRBS Receiver (which resides within the Receive Section of the
Channel) will now be enabled and will begin to search the incoming
data for the above-mentioned PRBS patterns.
0 - Disables both the PRBS Generator and PRBS Receiver within the corresponding channel.
1 - Enables both the PRBS Generator and PRBS Receiver within the corresponding channel.
NOTES:
1.
To check and monitor PRBS Bit Errors, DR (Dual Rail) mode will be
over-ridden and Single Rail mode forced for the duration of this
mode. This will configure the RNEG/LCV_n output pin to function
as a PRBS Error Indicator. All errors will be flagged on this pin.
The errors will also be accumulated in the 16 bit Error counter for
the channel.
2.
If the user enables the PRBS Generator and PRBS Receiver, the
Channel will ignore the data that is being accepted from the
System-side Equipment (via the TxPOS_n and TxNEG_n input
pins) and will overwrite this outbound data with the PRBS Pattern.
3.
The system must provide an accurate and stable data-rate clock to
the TxClk_n pin during this operation.
77
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 39: CHANNEL CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM6
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
4
RLB_n
R/W
Loop-Back Select - RLB Bit - Channel_n:
This READ/WRITE bit-field along with the corresponding LLB_n bit-field is
used to configure a given channel into various loop-back modes ass shown
by the following table.
LLB_n
RLB_n
Loop-back M ode
0
0
Norm al (No Loop-back) Mode
0
1
Rem ote Loop-back Mode
1
0
Analog Local Loop-back Mode
1
1
Digital Local Loop-back Mode
3
LLB_n
R/W
Loop-Back Select - LLB Bit-field - Channel_n:
See the table (above) for RLB_n.
2
E3_n
R/W
E3 Mode Select - Channel_n:
This READ/WRITE bit-field, along with Bit 1 (STS-1/DS3_n) within this register, is used to configure a given channel into either the DS3, E3 or STS-1
Modes.
0 - Configures Channel_n to operate in either the DS3 or STS-1 Modes,
depending upon the state of Bit 1 (STS-1/DS3_n) within this same register.
1- Configures Channel_n to operate in the E3 Mode.
78
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 39: CHANNEL CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM6
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
1
STS-1/DS3_n
R/W
STS-1/DS3 Mode Select - Channel_n:
This READ/WRITE bit-field, along with Bit 2 (E3_n) is used to configure a
given channel into either the DS3, E3 or STS-1 Modes.
This bit-field is ignored if Bit 2 (E3_n) has been set to "1".
If Bit 2 (E3_n) is a 0:
0 - Configures Channel_n to operate in the DS3 Mode.
1 - Configures Channel_n to operate in the STS-1 Mode .
0
SR/DR_n
R/W
Single-Rail/Dual-Rail Select - Channel_n:
This READ/WRITE bit-field is used to configure Channel_n to operate in
either the Single-Rail or Dual-Rail Mode.
If the user configures the Channel to operate in the Single-Rail Mode, the
following will happen.
• The B3ZS/HDB3 Encoder and Decoder blocks (within Channel_n) will be
enabled.
• The Transmit Section of Channel_n will accept all of the outbound data
(from the System-side Equipment) via the TxPOS_n input pin.
• The Receive Section of each channel will output all of the recovered data
(to the System-side Equipment) via the RxPOS_n output pin.
• The corresponding RNEG/LCV_n output pin will now function as the LCV
(Line Code Violation or Excessive Zero Event) indicator output pin for
Channel_n.
If the user configures Channel_n to operate in the Dual-Rail Mode, the following will happen.
• The B3ZS/HDB3 Encoder and Decoder blocks of Channel_n will be
disabled.
• The Transmit Section of Channel_n will be configured to accept positivepolarity data via the TxPOS_n input pin and negative-polarity data via the
TxNEG_n input pin.
• The Receive Section of Channel_n will pulse the RxPOS_n output pin
"High" (for one period of RCLK_n) for each time a positive-polarity pulse is
received via the RTIP_n/RRING_n input pins. Likewise, the Receive
Section of each channel will pulse the RxNEG_n output pin "High" (for
one period of RxCLK_n) for each time a negative-polarity pulse is
received via the RTIP_n/RRING_n input pins.
0 - Configures Channel_n to operate in the Dual-Rail Mode.
1 - Configures Channel_n to operate in the Single-Rail Mode.
79
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 40: XRT73R12 REGISTER MAP SHOWING ERROR COUNTER MSBYTE REGISTERS (EM_N) (N = [0:11])
ADDRESS
LOCATION
0
1
2
3
4
5
6
0x0-
APST
IER0
ISR0
AS0
TC0
RC0
CC0
0X1-
IER1
ISR1
AS1
TC1
RC1
0x2-
IER2
ISR2
AS2
TC2
0x3-
IER3
ISR3
AS3
0x4-
IER4
ISR4
0x5-
IER5
ISR5
7
A
B
C
EM0
EL0
EH0
CC1
EM1
EL1
EH1
RC2
CC2
EM2
EL2
EH2
TC3
RC3
CC3
EM3
EL3
EH3
AS4
TC4
RC4
CC4
EM4
EL4
EH4
AS5
TC5
RC5
CC5
EM5
EL5
EH5
CIE
CIS
APST
IER6
ISR6
AS6
TC6
RC6
CC6
0X9-
IER7
ISR7
AS7
TC7
RC7
0xA-
IER8
ISR8
AS8
TC8
0xB-
IER9
ISR9
AS9
0xC-
IER10 ISR10
0xD-
IER11
0x6-
8
9
APSR
D
E F
PN VN
0x70x8-
0xE-
CIE
ISR11
EM6
EL6
EH6
CC7
EM7
EL7
EH7
RC8
CC8
EM8
EL8
EH8
TC9
RC9
CC9
EM9
EL9
EH9
AS10
TC10
RC10
CC10
EM10
EL10
EH10
AS11
TC11
RC11
CC11
EM11
EL11
EH11
APSR
CIS
0xF-
TABLE 41: ERROR COUNTER MSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMA (M= 0-5 & 8-D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Msb
9th bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TABLE 42: XRT73R12 REGISTER MAP SHOWING ERROR COUNTER LSBYTE REGISTERS (EL_N) (N = [0:11])
ADDRESS
LOCATION
0
1
2
3
4
5
6
0x0-
APST
IER0
ISR0
AS0
TC0
RC0
CC0
0X1-
IER1
ISR1
AS1
TC1
RC1
0x2-
IER2
ISR2
AS2
TC2
0x3-
IER3
ISR3
AS3
0x4-
IER4
ISR4
0x5-
IER5
ISR5
A
B
C
EM0
EL0
EH0
CC1
EM1
EL1
EH1
RC2
CC2
EM2
EL2
EH2
TC3
RC3
CC3
EM3
EL3
EH3
AS4
TC4
RC4
CC4
EM4
EL4
EH4
AS5
TC5
RC5
CC5
EM5
EL5
EH5
80
7
8
APSR
9
D E F
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 42: XRT73R12 REGISTER MAP SHOWING ERROR COUNTER LSBYTE REGISTERS (EL_N) (N = [0:11])
ADDRESS
LOCATION
0
1
0x6-
CIE
CIS
APST
IER6
ISR6
AS6
TC6
RC6
CC6
0X9-
IER7
ISR7
AS7
TC7
RC7
0xA-
IER8
ISR8
AS8
TC8
0xB-
IER9
ISR9
AS9
0xC-
IER10 ISR10
0xD-
IER11 ISR11
2
3
4
5
6
7
8
9
A
B
C
D E F
PN VN
0x70x8-
0xE-
CIE
EM6
EL6
EH6
CC7
EM7
EL7
EH7
RC8
CC8
EM8
EL8
EH8
TC9
RC9
CC9
EM9
EL9
EH9
AS10
TC10
RC10
CC10
EM10
EL10
EH10
AS11
TC11
RC11
CC11
EM11
EL11
EH11
APSR
CIS
0xF-
TABLE 43: ERROR COUNTER LSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMB (M= 0-5 & 8-D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
8th bit
Ls bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TABLE 44: XRT73R12 REGISTER MAP SHOWING ERROR COUNTER HOLDING REGISTERS (EH_N) (N = [0:11])
ADDRESS
LOCATION
0
1
2
3
4
5
6
0x0-
APST
IER0
ISR0
AS0
TC0
RC0
CC0
0X1-
IER1
ISR1
AS1
TC1
RC1
0x2-
IER2
ISR2
AS2
TC2
0x3-
IER3
ISR3
AS3
0x4-
IER4
ISR4
0x5-
IER5
ISR5
0x6-
A
B
C
EM0
EL0
EH0
CC1
EM1
EL1
EH1
RC2
CC2
EM2
EL2
EH2
TC3
RC3
CC3
EM3
EL3
EH3
AS4
TC4
RC4
CC4
EM4
EL4
EH4
AS5
TC5
RC5
CC5
EM5
EL5
EH5
CIE
CIS
APST
IER6
ISR6
AS6
TC6
RC6
CC6
0X9-
IER7
ISR7
AS7
TC7
RC7
0xA-
IER8
ISR8
AS8
TC8
0xB-
IER9
ISR9
AS9
0xC-
IER10
ISR10
0xD-
IER11
ISR11
7
8
APSR
9
PN VN
0x70x8-
D E F
EM6
EL6
EH6
CC7
EM7
EL7
EH7
RC8
CC8
EM8
EL8
EH8
TC9
RC9
CC9
EM9
EL9
EH9
AS10
TC10
RC10
CC10
EM10
EL10
EH10
AS11
TC11
RC11
CC11
EM11
EL11
EH11
81
APSR
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 44: XRT73R12 REGISTER MAP SHOWING ERROR COUNTER HOLDING REGISTERS (EH_N) (N = [0:11])
ADDRESS
LOCATION
0
1
0xE-
CIE
CIS
2
3
4
5
6
7
8
9
A
B
C
D E F
0xF-
TABLE 45: ERROR COUNTER HOLDING REGISTER - CHANNEL N ADDRESS LOCATION = 0XMC (M= 0-5 & 8-D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Msb
R/W
BIT 0
Ls bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each channel contains a dedicated 16 bit PRBS error counter. When enabled this counter will accumulate
PRBS errors (as well as excess zeros and LCVs). The LS byte will "carry" a one over to the MS byte each time
it rolls over from 255 to zero until the MS byte also reaches 255. When both counters reach 255, no further
errors will be accumulated and "all ones" will signify an overflow condition.
The counter can be read while in the active count mode. Either register may be read "on the fly" and the other
byte will be simultaneously transferred into the channel’s Error Holding register. The holding register may then
be read to supply the Host with a correct 16 bit count (as of the instant of reading). With this mechanism, the
Host could rapidly cycle thru reading all twelve counters in order (storing the read byte in scratch RAM) and
then come back and read the second byte from each holding register to form the 16 bit accumulation in the
Host system.
82
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
8.0 ELECTRICAL CHARACTERISTICS
TABLE 46: ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
MIN
MAX
UNITS
COMMENTS
VDD
Supply Voltage
-0.5
6.0
V
Note 1
VIN
Input Voltage at any Pin
-0.5
5.5
V
Note 1
IIN
Input current at any pin
100
mA
Note 1
STEMP
Storage Temperature
-65
150
0
C
Note 1
ATEMP
Ambient Operating Temperature
-40
85
0C
linear airflow 0 ft./min
Theta JA
Thermal Resistance
C/W
linear air flow 200ft/min
7.5
0
(See Note 3 below)
MLEVL
Exposure to Moisture
5
level
EIA/JEDEC
JESD22-A112-A
ESD
ESD Rating
2000
V
Note 2
NOTES:
1.
Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair
reliability of the device.
2.
ESD testing method is per MIL-STD-883D,M-3015.7
3.
Linear Air flow of 200 ft/min recommended for Industrial Applications. Theta JA = 9.4°C/W with 0 Lft /min, Theta JA
= 7.1 °C/W with 400Lft/min.
83
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 47: DC ELECTRICAL CHARACTERISTICS:
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
DVDD
Digital Supply Voltage
3.135
3.3
3.465
V
AVDD
Analog Supply Voltage
3.135
3.3
3.465
V
ICC_DS3
DS3 current consumption using PRBS 223-1 pattern
1016
1117
mA
ICC_E3
E3 current consumption using PRBS 223-1 pattern
1040
1140
mA
ICC_STS1
STS1 current consumption using PRBS 223-1 pattern
1100
1210
mA
PCC_DS3
DS3 Power Consumption 3
3.35
3.87
W
PCC_E3
E3 Power Consumption 3
3.43
3.95
W
STS1 Power Consumption 3
3.63
4.19
W
0.8
V
5.5
V
0.4
V
PCC_STS1
VIL
Input Low Voltage2
VIH
Input High Voltage2
VOL
Output Low Voltage, IOUT = - 4mA
VOH
Output High Voltage, IOUT = 4 mA
2.0
2.4
V
IL
Input Leakage Current1
±10
µA
CI
Input Capacitance
10
pF
CL
Load Capacitance
10
pF
NOTES:
1.
Not applicable for pins with pull-up or pull-down resistors.
2.
The Digital inputs are TTL 5V compliant.
3.
These values are not a measure of Power Dissipation. These values represent the Total Power Consumption.
i.e. PCC Consumption = PDD Dissipation + PLD Delivered to Load
84
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT73R12IB
420 TBGA
-40°C to +85°C
PACKAGE DIMENSIONS -
E
420 Tape Ball Grid Array
(35 mm x 35 mm, TBGA)
Rev. 1.00
26
24
25
22
23
20
21
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
A1
FEATURE/MARK
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
D
N
D1
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
e
D1
D
(A1 corner feature is mfger option)
SYMBOL
A
A1
A2
D
D1
b
e
P
INCHES
MIN
MAX
0.051
0.067
0.020
0.028
0.031
0.039
1.370
1.386
1.5000 BSC
0.024
0.035
0.0500 BSC
0.006
0.012
85
MILLIMETERS
MIN
MAX
1.30
1.70
0.50
0.70
0.80
1.00
34.80
35.20
38.10 BSC
0.60
0.90
1.27 BSC
0.15
0.30
XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
REVISION HISTORY
REVISION
DATE
P1.0.0
08/19/03
Original
P1.0.1
09/19/03
Changed MTip/MRing circuit in the Transmit Drive Monitor Diagram.
P1.0.2
10/23/03
Removed Jitter Attenuator references in the register map.
P1.0.3
10/30/03
Added Pull-Up resistor description for RDY and INT.
1.0.0
COMMENTS
April 2006 1. Added current and power consumption on Table 47, “DC Electrical Characteristics:,” on
page 84.
2. Revised Receive Monitor Enable Bit functional description and Section 3.3.1 description.
3. Updated Table 3, “The ALOS (Analog LOS) Declaration and Clearance Thresholds for a
given setting of REQEN (DS3 and STS-1 Applications),” on page 23.
4. Minor corrections on Transmitter Section of Features Summary on page 2.
5. Minor typo corrections in STS1Clk/12M pin description and in Section 1.0, 3.3, and 4.5,
Table 7 and Table 9.
6. Added Table 2, “Reference Clock Performance Specifications,” on page 19.
1.0.1
12/07/06
Corrrected package thermal resistance specification.
1.0.2
6/27/07
1. Corrected global register 0x08 and added global registers 0x80 & 0x88.
2. Added (N = [0:11] & M = 0-5 & 8-D) to channelized register titles.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2007 EXAR Corporation
Datasheet June 2007.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
86