XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S March 2007 Rev 2.0.0 GENERAL DESCRIPTION FEATURES The XRT94L33 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/de-mapping functions from either the STS-3 or STM-1 data stream. The XRT94L33 interfaces directly to the optical transceiver • Provides DS3/ E3 mapping/de-mapping for up to 3 tributaries through SONET STS-1 or SDH AU3 and/or TUG-3/AU-4 containers • Generates and terminates SONET/SDH section, line and path layers • Integrated SERDES with Clock Recovery Circuit • Provides SONET descrambling • Integrated Clock Synthesizer that generates 155 MHz and 77.76 MHz clock from an external 12.96/19.44/77.76 MHz reference clock The XRT94L33 uses the internal E3/DS3 DeSynchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as to remove the jitter due to mapping and pointer movements. These De-Synchronizer circuits do not need any external clock reference for its operation. • Integrated 3 E3/DS3/STS-1 De-Synchronizer circuit that de-jitter gapped clock to meet 0.05UIpp jitter requirements • Access to Line or Section DCC • Level 2 Performance Monitoring for E3 and DS3 The SONET/SDH transmit blocks allow flexible insertion of TOH and POH bytes through both Hardware and Software. Individual POH bytes for the transmitted SONET/SDH signal are mapped either from the XRT94L33 memory map or from external interface. A1, A2 framing pattern, C1 byte and H1, H2 pointer byte are generated. • Supports mixing of STS-1E and DS3 or E3 and DS3 tributaries • UTOPIA Level 2 interface for ATM or level 2P for Packets • E3 and DS3 framers for both Transmit and Receive directions The SONET/SDH receive blocks receive SONET STS-3 signal or SDH STM-1 signal and perform the necessary transport and path overhead processing. • Complete Transport/Section Overhead Processing and generation per Telcordia and ITU standards The XRT94L33 provides a line side APS (Automatic Protection Switching) interface by offering redundant receive serial interface to be switched at the frame boundary. • Single PHY and Multi-PHY operations supported • Full line APS applications The XRT94L33 provides 3 Mappers for performing STS-1/VC-3 to STS-1/DS3/E3 mapping function, one for each STS-1/DS3/E3 framers. • Loopback support for both SONET/SDH as well as E3/DS3/STS-1 • Boundary scan capability with JTAG IEEE 1149 • 8-bit microprocessor interface • 3.3 V ± 5% Power Supply; 5 V input signal tolerance APPLICATIONS • -40°C to +85°C Operating Temperature Range • Network switches • Available in a 504 Ball TBGA package • Add/Drop Multiplexer • W-DCS Digital Cross Connect Systems The XRT94L33 processes the section, line and path overhead in the SONET/SDH data stream and also performs ATM and PPP PHY-layer processing. The processing of path overhead bytes within the STS-1s or TUG-3s includes 64 bytes for storing the J1 bytes. Path overhead bytes can be accessed through the microprocessor interface or via serial interface. A PRBS test pattern generation and detection is implemented to measure the bit-error performance. A general-purpose microprocessor interface is included for control, configuration and monitoring. frame support scrambling for and redundancy E Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * Fax (510) 668-7017 * www.exar.com XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Block Diagram of the XRT94L33 To OC3 Telecom Bus Interface To F.O. OC3 TxRx SONET/SDH TOH SONET/SDH POH To DS3/E3 STS-1 Telecom Bus/ T3/E3/HDLC Intf Telecom Bus Interface SDH MUX Microprocessor Interface DS3/E3 Mapper Jitter Attenuator & Clock Sm oothing DS3/E3 Fram er ATM Processor PLCP PPP Processor Pointer Justify STS-1 Tx/Rx TO H & POH Telecom Bus Interface DS3/E3 Mapper STS-1 Channel 0 Jitter Attenuator & Clock Sm oothing DS3/E3 Fram er ATM Processor PLCP PPP Processor Pointer Justify UTOPIA II/IIp Interface HDLC Controller STS-1 Tx/Rx TOH & POH SO NET/SDH PO H To DS3/E3 STS-1 Telecom Bus/ T3/E3/HDLC Intf Boundry Scan HDLC Controller SO NET/SDH PO H To DS3/E3 STS-1 Telecom Bus/ T3/E3/HDLC Intf SONET/SDH POH Telecom Bus Interface DS3/E3 Mapper STS-1 Channel 1 Jitter Attenuator & Clock Sm oothing DS3/E3 Fram er ATM Processor PLCP PPP Processor Pointer Justify HDLC Controller STS-1 Tx/Rx TOH & POH STS-1 Channel 2 ORDERING INFORMATION PART NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRT94L33IB 27 x 27 504 Lead TBGA -40°C to +85°C 2 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.0 XRT94L33 REGISTERS FOR SONET 1.1 THE OVERALL REGISTER MAP WITHIN THE XRT94L33 The XRT94L33 employs a direct Addressing Scheme. The Address Locations for each of the “Register Groups” (or Register pages) is presented in the Table below. Table 1: The Address Register Map for the XRT94L33 ADDRESS LOCATION REGISTER NAME DEFAULT VALUE OPERATION CONTROL BLOCK REGISTERS 0x0000 – 0x00FF Reserved 0x0100 Operation Control Register – Byte 3 0x00 0x0101 Operation Control Register – Byte 2 0x00 0x0102 Reserved 0x00 0x0103 Operation Control Register – Byte 0 0x00 0x0104 Operation Status Register – Byte 3 (Device ID) 0xE3 0x0105 Operation Status Register – Byte 2 (Revision ID) 0x01 Reserved 0x00 Operation Interrupt Status Register – Byte 0 0x00 Reserved 0x00 Operation Interrupt Enable Register – Byte 0 0x00 Reserved 0x00 0x0112 Operation Block Interrupt Status Register – Byte 1 0x00 0x0113 Operation Block Interrupt Status Register – Byte 0 0x00 Reserved 0x00 0x0116 Operation Block Interrupt Enable Register – Byte 1 0x00 0x0117 Operation Block Interrupt Enable Register – Byte 0 0x00 0x0118 – 0x0119 Reserved 0x00 0x011A Reserved 0x00 0x011B Mode Control Register – Byte 0 0x00 Reserved 0x00 0x011F Loop-back Control Register – Byte 0 0x00 0x0120 Channel Interrupt Indicator Register – Receive SONET POH Processor Block 0x00 0x0121 Reserved 0x00 0x0122 Channel Interrupt Indicator Register – DS3/E3 framer Block 0x00 0x0123 Channel Interrupt Indicator Register – Receive STS-1 POH Processor Block 0x00 0x0124 Channel Interrupt Indicator Register – Receive STS-1 TOH Processor Block 0x00 0x0106 – 0x010A 0x010B 0x010C – 0x010E 0x010F 0x0110 – 0x0111 0x0114 – 0x0115 0x011C – 0x011E 3 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 0x0125 Reserved 0x00 0x0126 Channel Interrupt Indicator Register – STS-1/DS3/E3 Mapper Block 0x00 0x0127 – 0x0129 Reserved 0x00 0x012A – 0x012F Reserved 0x00 0x0130 – 0x0131 Reserved 0x11 0x0132 Interface Control Register – Byte 1 0x00 0x0133 Interface Control Register – Byte 0 0x00 0x0134 STS-3/STM-1 Telecom Bus Control Register – Byte 3 0x00 0x0135 STS-3/STM-1 Telecom Bus Control Register – Byte 2 0x00 0x0136 Reserved 0x00 0x0137 STS-3/STM-1 Telecom Bus Control Register – Byte 0 0x00 0x0138 Reserved 0x00 0x0139 Interface Control Register – Byte 2 – STS-3 Telecom Bus 2 0x00 0x013A Interface Control Register – Byte 1 – STS-3 Telecom Bus 1 0x00 0x013B Interface Control Register – Byte 0 – STS-3 Telecom Bus 0 0x00 0x013C Interface Control Register – STS-1 Telecom Bus Interrupt Register 0x00 0x013D Interface Control Register – STS-1 Telecom Bus Interrupt Status Register 0x00 0x013E Interface Control Register – STS-1 Telecom Bus Interrupt Register # 2 0x00 0x013F Interface Control Register – STS-1 Telecom Bus Interrupt Enable Register 0x00 Reserved 0x00 Operation General Purpose Input/Output Register 0x00 Reserved 0x00 Operation General Purpose Input/Output Direction Register – Byte 0 0x00 Reserved 0x00 Operation Output Control Register – Byte 1 0x00 Reserved 0x00 0x0153 Operation Output Control Register – Byte 0 0x00 0x0154 Operation Slow Speed Port Control Register – Byte 1 0x00 Reserved 0x00 0x0157 Operation Slow Speed Port Control Register –Byte 0 0x00 0x0158 Operation – DS3/E3/STS-1 Clock Frequency Out of Range Detection – Direction Register 0x00 0x0159 Reserved 0x00 0x015A Operation – DS3/E3/STS-1 Clock Frequency – DS3 Out of Range Detection 0x00 0x0140 – 0x0146 0x0147 0x0148 – 0x014A 0x014B 0x014C –0x014F 0x0150 0x0151 –0x0152 0x0155 – 0x0156 4 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Threshold Register 0x015B Operation – DS3/E3/STS-1 Clock Frequency – STS-1/E3 Out of Range Detection Threshold Register 0x00 0x015C Reserved 0x00 0x015D Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Enable Register – Byte 0 0x00 0x015E Reserved 0x00 0x015F Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Status Register – Byte 0 0x00 Reserved 0x00 0x0180 APS Mapping Register 0x00 0x0181 APS Control Register 0x00 Reserved 0x00 0x0194 APS Status Register 0x00 0x0195 Reserved 0x00 0x0196 APS Status Register 0x00 0x0197 APS Status Register 0x00 0x0198 APS Interrupt Register 0x00 0x0199 Reserved 0x00 0x019A APS Interrupt Register 0x00 0x019B APS Interrupt Register 0x00 0x019C APS Interrupt Register 0x00 0x019D Reserved 0x00 0x019E APS Interrupt Enable Register 0x00 0x019F APS Interrupt Enable Register 0x00 Reserved 0x00 0x0160 – 0x017F 0x0182 – 0x0193 0x01A0 – 0x01FF LINE INTERFACE CONTROL REGISTERS 0x0302 Receive Line Interface Control Register – Byte 1 0x00 0x0303 Receive Line Interface Control Register – Byte 0 0x00 Reserved 0x00 Receive Line Status Register 0x00 Reserved 0x00 Receive Line Interrupt Register 0x00 Reserved 0x00 Receive Line Interrupt Enable Register 0x00 0x0304 – 0x0306 0x0307 0x0308 -0x030A 0x030B 0x030C – 0x030E 0x030F 5 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0x0310 – 0x0382 0x0383 Rev222...000...000 Reserved 0x00 Transmit Line Interface Control Register 0x00 RECEIVE STS-3 TOH PROCESSOR BLOCK CONTROL REGISTERS 0x1000 – 0x1102 0x1103 Reserved Receive STS-3 Transport Control Register – Byte 0 0x00 Reserved 0x00 0x1106 Receive STS-3 Transport Status Register – Byte 1 0x00 0x1107 Receive STS-3 Transport Status Register – Byte 0 0x02 0x1108 Reserved 0x00 0x1109 Receive STS-3 Transport Interrupt Status Register – Byte 2 0x00 0x110A Receive STS-3 Transport Interrupt Status Register – Byte 1 0x00 0x110B Receive STS-3 Transport Interrupt Status Register – Byte 0 0x00 0x110C Reserved 0x00 0x110D Receive STS-3 Transport Interrupt Enable Register – Byte 2 0x00 0x110E Receive STS-3 Transport Interrupt Enable Register – Byte 1 0x00 0x110F Receive STS-3 Transport Interrupt Enable Register – Byte 0 0x00 0x1110 Receive STS-3 Transport B1 Byte Error Count – Byte 3 0x00 0x1111 Receive STS-3 Transport B1 Byte Error Count – Byte 2 0x00 0x1112 Receive STS-3 Transport B1 Byte Error Count – Byte 1 0x00 0x1113 Receive STS-3 Transport B1 Byte Error Count – Byte 0 0x00 0x1114 Receive STS-3 Transport B2 Byte Error Count – Byte 3 0x00 0x1115 Receive STS-3 Transport B2 Byte Error Count – Byte 2 0x00 0x1116 Receive STS-3 Transport B2 Byte Error Count – Byte 1 0x00 0x1117 Receive STS-3 Transport B2 Byte Error Count – Byte 0 0x00 0x1118 Receive STS-3 Transport REI-L Event Count – Byte 3 0x00 0x1119 Receive STS-3 Transport REI-L Event Count – Byte 2 0x00 0x111A Receive STS-3 Transport REI-L Event Count – Byte 1 0x00 0x111B Receive STS-3 Transport REI-L Event Count – Byte 0 0x00 0x111C Reserved 0x00 0x111D - 0 x111E Reserved 0x1104 – 0x1105 0x111F 0x1120 – 0x1122 0x1123 0x00 Receive STS-3 Transport K1 Byte Value Register 0x00 Reserved 0x00 Receive STS-3 Transport K2 Byte Value Register 0x00 6 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0x1124 – 0x1126 Reserved 0x00 Receive STS-3 Transport S1 Byte Value Register 0x00 Reserved 0x00 Receive STS-3 Transport – In-Sync Threshold Value Register 0x00 Reserved 0x00 0x112E Receive STS-3 Transport – LOS Threshold Value – MSB 0xFF 0x112F Receive STS-3 Transport – LOS Threshold Value – LSB 0xFF 0x1130 Reserved 0x00 0x1131 Receive STS-3 Transport – SF Set Monitor Interval – Byte 2 0x00 0x1132 Receive STS-3 Transport – SF Set Monitor Interval – Byte 1 0x00 0x1133 Receive STS-3 Transport – SF Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0x1136 Receive STS-3 Transport – SF Set Threshold – Byte 1 0x00 0x1137 Receive STS-3 Transport – SF Set Threshold – Byte 0 0x00 Reserved 0x00 0x113A Receive STS-3 Transport – SF Clear Threshold – Byte 1 0x00 0x113B Receive STS-3 Transport – SF Clear Threshold – Byte 0 0x00 0x113C Reserved 0x00 0x113D Receive STS-3 Transport – SD Set Monitor Interval – Byte 2 0x00 0x113E Receive STS-3 Transport – SD Set Monitor Interval – Byte 1 0x00 0x113F Receive STS-3 Transport – SD Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0x1142 Receive STS-3 Transport – SD Set Threshold – Byte 1 0x00 0x1143 Receive STS-3 Transport – SD Set Threshold – Byte 0 0x00 Reserved 0x00 0x1146 Receive STS-3 Transport – SD Clear Threshold – Byte 1 0x00 0x1147 Receive STS-3 Transport – SD Clear Threshold – Byte 0 0x00 Reserved 0x00 Receive STS-3 Transport – Force SEF Condition 0x00 Reserved 0x00 Receive STS-3 Transport – Receive Section Trace Message Buffer Control Register 0x00 Reserved 0x00 Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 1 0x00 0x1127 0x1128 – 0x112A 0x112B 0x112C, 0x112D 0x1134 – 0x1135 0x1138, 0x1139 0x1140, 0x1141 0x1144, 0x1145 0x1148 – 0x114A 0x114B 0x114C, 0x114E 0x114F 0x1150, 0x1151 0x1152 7 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0x1153 Rev222...000...000 Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 0 0x00 Reserved 0x00 0x1156 Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 1 0x00 0x1157 Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 0 0x00 0x1158 Reserved 0x00 0x1159 Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 2 0xFF 0x115A Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1 0xFF 0x115B Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0 0xFF 0x115C Reserved 0x00 0x115D Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2 0xFF 0x115E Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1 0xFF 0x115F Receive STS-3 Transport – Receive SF Clear Monitor – Byte 0 0xFF Reserved 0x00 Receive STS-3 Transport – Auto AIS Control Register 0x00 Reserved 0x00 Receive STS-3 Transport – Serial Port Control Register 0x00 Reserved 0x00 Receive STS-3 Transport – Auto AIS (in Downstream STS-1s) Control Register 0x000 Reserved 0x00 0x117A Receive STS-3 Transport – TOH Capture Indirect Address 0x00 0x117B Receive STS-3 Transport – TOH Capture Indirect Address 0x00 0x117C Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x117D Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x117E Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x117F Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x1180 Reserved 0x00 0x1154, 0x1155 0x1160 – 0x1162 0x1163 0x1164 – 0x1166 0x1167 0x1168 – 0x116A 0x116B 0x116C – 0x1179 RECEIVE STS-3C POH PROCESSOR BLOCK 0x1181 Reserved 0x00 0x1182 Receive STS-3c Path – Control Register – Byte 1 0x00 0x1183 Receive STS-3c Path – Control Register – Byte 0 0x00 Reserved 0x00 0x1186 Receive STS-3c Path – Status Register – Byte 1 0x00 0x1187 Receive STS-3c Path – Status Register – Byte 0 0x00 0x1184 – 0x1185 8 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0x1188 Reserved 0x00 0x1189 Receive STS-3c Path – Interrupt Status Register – Byte 2 0x00 0x118A Receive STS-3c Path – Interrupt Status Register – Byte 1 0x00 0x118B Receive STS-3c Path – Interrupt Status Register – Byte 0 0x00 0x118C Reserved 0x00 0x118D Receive STS-3c Path – Interrupt Enable Register – Byte 2 0x00 0x118E Receive STS-3c Path – Interrupt Enable Register – Byte 1 0x00 0x118F Receive STS-3c Path – Interrupt Enable Register – Byte 0 0x00 Reserved 0x00 Receive STS-3c Path – SONET Receive RDI-P Register 0x00 Reserved 0x00 0x1196 Receive STS-3c Path – Receive Path Label Byte (C2) Byte Register 0x00 0x1197 Receive STS-3c Path – Expected Path Label Byte (C2) Byte Register 0x00 0x1198 Receive STS-3c Path – B3 Byte Error Count Register – Byte 3 0x00 0x1199 Receive STS-3c Path – B3 Byte Error Count Register – Byte 2 0x00 0x119A Receive STS-3c Path – B3 Byte Error Count Register – Byte 1 0x00 0x119B Receive STS-3c Path – B3 Byte Error Count Register – Byte 0 0x00 0x119C Receive STS-3c Path – REI-P Event Count Register – Byte 3 0x00 0x119D Receive STS-3c Path – REI-P Event Count Register – Byte 2 0x00 0x119E Receive STS-3c Path – REI-P Event Count Register – Byte 1 0x00 0x119F Receive STS-3c Path – REI-P Event Count Register – Byte 0 0x00 Reserved 0x00 Receive STS-3c Path – Receive Path Trace Message Byte Control Register 0x00 Reserved 0x00 0x11A6 Receive STS-3c Path – Pointer Value Register – Byte 1 0x00 0x11A7 Receive STS-3c Path – Pointer Value Register – Byte 0 0x00 Reserved 0x00 Receive STS-3c Path – Loss of Pointer – Concatenation Status Register 0x00 Reserved 0x00 Receive STS-3c Path – AIS – Concatenation Status Register 0x00 Reserved 0x00 Receive STS-3c Path – Auto AIS Control Register 0x00 Reserved 0x00 0x1190 – 0x1192 0x1193 0x1194 – 0x1195 0x11A0 – 0x11A2 0x11A3 0x11A4 – 0x11A5 0x11A8 – 0x11AA 0x11AB 0x11AC – 0x11B2 0x11B3 0x11B4 – 0x11BA 0x11BB 0x11BC – 0x11BE 9 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0x11BF 0x11C0 – 0x11C2 0x11C3 0x11C4 –0x11D2 0x11D3 0x11D4 – 0x11D6 0x11D7 0x11D8 – 0x11DA 0x11DB 0x11DC – 0x11DE 0x11DF 0x11E0 – 0x11E2 0x11E3 0x11E4 – 0x11E6 0x11E7 0x11E8 – 0x11EA 0x11EB 0x11EC – 0x11EE 0x11EF 0x11F0 – 0x11F2 0x11F3 0x11F4 – 0x12FF Rev222...000...000 Receive STS-3c Path – Serial Port Control Register 0x00 Reserved 0x00 Receive STS-3c Path - Receive SONET Auto Alarm Register – Byte 0 0x00 Reserved 0x00 Receive STS-3c Path – Receive J1 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive B3 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive C2 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive G1 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive F2 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive H4 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive Z3 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive Z4 (K3) Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive Z5 Byte Capture Register 0x00 Reserved 0x00 RECEIVE STS-3/STM-1 TOH PROCESSOR BLOCK – RECEIVE J0 (SECTION) TRACE MESSAGE BUFFER 0x1300 – 0x133F Receive STS-3/STM-1 TOH Processor Block – Receive J0 (Section) Trace Message Buffer – Expected and Received 0x00 0x1340 – 0x13FF Reserved 0x00 RECEIVE STS-3C POH PROCESSOR BLOCK – RECEIVE J1 (PATH) TRACE MESSAGE BUFFER – STS-3C 0x1500 – 0x153F Receive STS-3c POH Processor Block – Receive J1 (Path) Trace Message Buffer 0x00 0x1540 – 0x15FF Reserved 0x00 REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK CONTROL REGISTERS 0x1600 – 0x1702 0x1703 0x1704 – 0x1705 0x1706 Reserved Redundant Receive STS-3 Transport Control Register – Byte 0 0x00 Reserved 0x00 Redundant Receive STS-3 Transport Status Register – Byte 1 0x00 10 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0x1707 Redundant Receive STS-3 Transport Status Register – Byte 0 0x02 0x1708 Reserved 0x00 0x1709 Redundant Receive STS-3 Transport Interrupt Status Register – Byte 2 0x00 0x170A Redundant Receive STS-3 Transport Interrupt Status Register – Byte 1 0x00 0x170B Redundant Receive STS-3 Transport Interrupt Status Register – Byte 0 0x00 0x170C Reserved 0x00 0x170D Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 2 0x00 0x170E Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 1 0x00 0x170F Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 0 0x00 0x1710 Redundant Receive STS-3 Transport B1 Byte Error Count – Byte 3 0x00 0x1711 Redundant Receive STS-3 Transport B1 Byte Error Count – Byte 2 0x00 0x1712 Redundant Receive STS-3 Transport B1 Byte Error Count – Byte 1 0x00 0x1713 Redundant Receive STS-3 Transport B1 Byte Error Count – Byte 0 0x00 0x1714 Redundant Receive STS-3 Transport B2 Byte Error Count – Byte 3 0x00 0x1715 Redundant Receive STS-3 Transport B2 Byte Error Count – Byte 2 0x00 0x1716 Redundant Receive STS-3 Transport B2 Byte Error Count – Byte 1 0x00 0x1717 Redundant Receive STS-3 Transport B2 Byte Error Count – Byte 0 0x00 0x1718 Redundant Receive STS-3 Transport REI-L Event Count – Byte 3 0x00 0x1719 Redundant Receive STS-3 Transport REI-L Event Count – Byte 2 0x00 0x171A Redundant Receive STS-3 Transport REI-L Event Count – Byte 1 0x00 0x171B Redundant Receive STS-3 Transport REI-L Event Count – Byte 0 0x00 Reserved 0x00 Redundant Receive STS-3 Transport K1 Byte Value Register 0x00 Reserved 0x00 Redundant Receive STS-3 Transport K2 Byte Value Register 0x00 Reserved 0x00 Redundant Receive STS-3 Transport S1 Byte Value Register 0x00 Reserved 0x00 Redundant Receive STS-3 Transport – In-Sync Threshold Value 0x00 Reserved 0x00 0x172E Redundant Receive STS-3 Transport – LOS Threshold Value – MSB 0xFF 0x172F Redundant Receive STS-3 Transport – LOS Threshold Value – LSB 0xFF 0x1730 Reserved 0x00 0x171C 0 x171E 0x171F 0x1720 – 0x1722 0x1723 0x1724 – 0x1726 0x1727 0x1728 – 0x172A 0x172B 0x172C, 0x172D 11 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 0x1731 Redundant Receive STS-3 Transport – SF Set Monitor Interval – Byte 2 0x00 0x1732 Redundant Receive STS-3 Transport – SF Set Monitor Interval – Byte 1 0x00 0x1733 Redundant Receive STS-3 Transport – SF Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0x1736 Redundant Receive STS-3 Transport – SF Set Threshold – Byte 1 0x00 0x1737 Redundant Receive STS-3 Transport – SF Set Threshold – Byte 0 0x00 Reserved 0x00 0x173A Redundant Receive STS-3 Transport – SF Clear Threshold – Byte 1 0x00 0x173B Redundant Receive STS-3 Transport – SF Clear Threshold – Byte 0 0x00 0x173C Reserved 0x00 0x173D Redundant Receive STS-3 Transport – SD Set Monitor Interval – Byte 2 0x00 0x173E Redundant Receive STS-3 Transport – SD Set Monitor Interval – Byte 1 0x00 0x173F Redundant Receive STS-3 Transport – SD Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0x1742 Redundant Receive STS-3 Transport – SD Set Threshold – Byte 1 0x00 0x1743 Redundant Receive STS-3 Transport – SD Set Threshold – Byte 0 0x00 Reserved 0x00 0x1746 Redundant Receive STS-3 Transport – SD Clear Threshold – Byte 1 0x00 0x1747 Redundant Receive STS-3 Transport – SD Clear Threshold – Byte 0 0x00 Reserved 0x00 Redundant Receive STS-3 Transport – Force SEF Condition 0x00 Reserved 0x00 0x1752 Redundant Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 1 0x00 0x1753 Redundant Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 0 0x00 Reserved 0x00 0x1756 Redundant Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 1 0x00 0x1757 Redundant Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 0 0x00 0x1758 Reserved 0x00 0x1759 Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 2 0xFF 0x175A Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1 0xFF 0x1734 – 0x1735 0x1738, 0x1739 0x1740, 0x1741 0x1744, 0x1745 0x1748 – 0x174A 0x174B 0x174C, 0x1751 0x1754, 0x1755 12 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0x175B Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0 0xFF 0x175C Reserved 0x00 0x175D Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2 0xFF 0x175E Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1 0xFF 0x175F Redundant Receive STS-3 Transport – Receive SF Clear Monitor – Byte 0 0xFF Reserved 0x00 Redundant Receive STS-3 Transport – Serial Port Control Register 0x00 Reserved 0x00 0x177A Redundant Receive STS-3 Transport – TOH Capture Indirect Address 0x00 0x177B Redundant Receive STS-3 Transport – TOH Capture Indirect Address 0x00 0x177C Redundant Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x177D Redundant Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x177E Redundant Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x177F Redundant Receive STS-3 Transport – TOH Capture Indirect Data 0x00 Reserved 0x00 0x1760 – 0x1766 0x1767 0x1768 – 0x1779 0x1780 – 0x17FF TRANSMIT STS-3 TOH PROCESSOR BLOCK CONTROL REGISTERS 0x1800 – 0x1901 Reserved 0x00 0x1902 Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 0x00 0x1903 Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3 Transport – Transmit A1 Error Mask – Low Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3 Transport – Transmit A2 Error Mask – Low Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3 Transport – B1 Byte Error Mask Register 0x00 Reserved 0x00 Transmit STS-3 Transport – Transmit B2 Byte Error Mask Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3 Transport – Transmit B2 Bit Error Mask Register – Byte 0 0x00 Reserved 0x00 0x192E Transmit STS-3 Transport – K1K2 (APS) Byte Value Register – Byte 1 0x00 0x192F Transmit STS-3 Transport – K1K2 (APS) Byte Value Register – Byte 0 0x00 0x1904 – 0x1916 0x1917 0x1918 – 0x191E 0x191F 0x1920 – 0x1921 0x1923 0x1924 – 0x1926 0x1927 0x1928 – 0x192A 0x192B 0x192C – 0x192D 13 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0x1930 – 0x1931 Rev222...000...000 Reserved 0x00 Transmit STS-3 Transport – RDI-L Control Register 0x00 Reserved 0x00 Transmit STS-3 Transport – M0M1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3 Transport – S1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3 Transport – F1 Byte Value Register 0x00 0x1940 – 0x1942 Reserved 0x00 0x1943 – 0x1946 Transmit STS-3 Transport – E1 Byte Value Register 0x00 0x1947 Transmit STS-3 Transport – E2 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3 Transport – J0 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3 Transport – J0 Byte Control Register 0x00 Reserved 0x00 Transmit STS-3 Transport – Serial Port Control Register 0x00 Reserved 0x00 0x1933 0x1934 – 0x1936 0x1937 0x1938 – 0x193A 0x193B 0x193C – 0x193E 0x193F 0x1948 – 0x194A 0x194B 0x194C – 0x194E 0x194F 0x1950 – 0x1952 0x1953 0x1954 –0x1980 TRANSMIT STS-3C POH PROCESSOR BLOCK 0x1981 Reserved 0x00 0x1982 Transmit STS-3c Path – SONET Control Register – Byte 1 0x00 0x1983 Transmit STS-3c Path – SONET Control Register- Byte 0 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit J1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – B3 Byte Mask Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit C2 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit G1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit F2 Byte Value Register 0x00 Reserved 0x00 0x1984 – 0x1992 0x1993 0x1994 – 0x1996 0x1997 0x1998 – 0x199A 0x199B 0x199C – 0x199E 0x199F 0x19A0 – 0x19A2 0x19A3 0x19A4 –0x19A6 14 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0x19A7 Transmit STS-3c Path – Transmit H4 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Z3 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Z4 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Z5 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Path Control Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3c Path- Transmit J1 Byte Control Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Arbitrary H1 Byte Pointer Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Arbitrary H2 Byte Pointer Register 0x00 Reserved 0x00 0x19C6 Transmit STS-3c Path – Transmit Pointer Byte Register –Byte 1 0x00 0x19C7 Transmit STS-3c Path – Transmit Pointer Byte Register – Byte 0 0x00 0x19C8 Reserved 0x00 0x19C9 Transmit STS-3c Path – RDI-P Control Register – Byte 2 0x00 0x19CA Transmit STS-3c Path –RDI-P Control Register – Byte 1 0x00 0x19CB Transmit STS-3c Path – RDI-P Control Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Path Serial Port Control Register 0x00 Reserved 0x00 0x19A8 – 0x19AA 0x19AB 0x19AC – 0x19AE 0x19AF 0x19B0 – 0x19B2 0x19B3 0x19B4 – 0x19B6 0x19B7 0x19B8 – 0x19BA 0x19BB 0x19BC –0x19BE 0x19BF 0x19C0 – 0x19C2 0x19C3 0x19C4 – 0x19C5 0x19CC –0x19CE 0x19CF 0x19D0 – 0x1AFF TRANSMIT STS-3 TOH PROCESSOR BLOCK – TRANSMIT J0 (SECTION) TRACE MESSAGE BUFFER 0x1B00 – 0x1B3F Transmit STS-3 TOH Processor Block – Transmit J0 (Section) Trace Message Buffer 0x00 0x1B40 – 0x1BFF Reserved 0x00 TRANSMIT STS-3C POH PROCESSOR BLOCK – TRANSMIT J1 (PATH) TRACE MESSAGE BUFFER 0x1D00 – 0x1D3F Transmit STS-3c POH Processor Block –Transmit J1 (Path) Trace Message Buffer 0x00 0x1D40 – 0x1DFF Reserved 0x00 RECEIVE SONET POH PROCESSOR BLOCK CONTROL REGISTERS Note: N represents the “Channel Number” and ranges in value from 0x02 to 0x04 15 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0xN000 – 0xN181 Rev222...000...000 Reserved 0x00 0xN182 Receive SONET Path – Control Register – Byte 1 0x00 0xN183 Receive SONET Path – Control Register – Byte 0 0x00 Reserved 0x00 0xN186 Receive SONET Path – Status Register – Byte 1 0x00 0xN187 Receive SONET Path – Status Register – Byte 0 0x00 0xN188 Reserved 0x00 0xN189 Receive SONET Path – Interrupt Status Register – Byte 2 0x00 0xN18A Receive SONET Path – Interrupt Status Register – Byte 1 0x00 0xN18B Receive SONET Path – Interrupt Status Register – Byte 0 0x00 0xN18C Reserved 0x00 0xN18D Receive SONET Path – Interrupt Enable Register – Byte 2 0x00 0xN18E Receive SONET Path – Interrupt Enable Register – Byte 1 0x00 0xN18F Receive SONET Path – Interrupt Enable Register – Byte 0 0x00 Reserved 0x00 Receive SONET Path – SONET Receive RDI-P Register 0x00 Reserved 0x00 0xN196 Receive SONET Path – Received Path Label Register 0x00 0xN197 Receive SONET Path – Expected Path Label Register 0x00 0xN198 Receive SONET Path – B3 Byte Error Count Register – Byte 3 0x00 0xN199 Receive SONET Path – B3 Byte Error Count Register – Byte 2 0x00 0xN19A Receive SONET Path – B3 Byte Error Count Register – Byte 1 0x00 0xN19B Receive SONET Path – B3 Byte Error Count Register – Byte 0 0x00 0xN19C Receive SONET Path – REI-P Event Count Register – Byte 3 0x00 0xN19D Receive SONET Path – REI-P Event Count Register – Byte 2 0x00 0xN19E Receive SONET Path – REI-P Event Count Register – Byte 1 0x00 0xN19F Receive SONET Path – REI-P Event Count Register – Byte 0 0x00 Reserved 0x00 0xN1A3 Receive SONET Path – Receiver Path Trace Message Control Register 0x00 0xN1A4, 0xN1A5 Reserved 0xN1A6 Receive SONET Path – Pointer Value – Byte 1 0x00 0xN1A7 Receive SONET Path – Pointer Value – Byte 0 0x00 Reserved 0x00 0xN184, 0xN185 0xN190 – 0xN192 0xN193 0xN194, 0xN195 0xN1A0 – 0xN1A2 0xN1A8 – 0xN1AA 16 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0xN1AB 0xN1AC – 0xN1B2 0xN1B3 0xN1B4 – 0xN1BA 0xN1BB 0xN1BC – 0xN1BE 0xN1BF 0xN1C0 – 0xN1C2 0xN1C3 0xN1C4 – 0xN1D2 0xN1D3 0xN1D4 – 0xN1D6 0xN1D7 0xN1D8 – 0xN1DA 0xN1DB 0xN1DC – 0xN1DE 0xN1DF 0xN1E0 – 0xN1E2 0xN1E3 0xN1E4 – 0xN1E6 0xN1E7 0xN1E8 – 0xN1EA 0xN1EB 0xN1EC – 0xN1EE 0xN1EF 0xN1F0 – 0xN1F2 0xN1F3 0xN1F4 – 0xN2FF Receive SONET Path – Loss of Pointer – Concatenation Status Register 0x00 Reserved 0x00 Receive SONET Path – AIS - Concatenation Status Register 0x00 Reserved 0x00 Receive SONET Path – AUTO AIS Control Register 0x00 Reserved 0x00 Receive SONET Path – Serial Port Control Register 0x00 Reserved 0x00 Receive SONET Path – SONET Receive Auto Alarm Register – Byte 0 0x00 Reserved 0x00 Receive SONET Path – Receive J1 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive B3 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive C2 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive G1 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive F2 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive H4 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive Z3 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive Z4 (K3) Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive Z5 Byte Capture Register 0x00 Reserved DS3/E3 FRAMER BLOCK REGISTERS Note: N represents the “Channel Number” and ranges in value from 0x02 to 0x04 0xN300 Operating Mode Register 0x23 0xN301 I/O Control Register 0xA0 17 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0xN302 – 0xN303 Rev222...000...000 Reserved 0x00 0xN304 Block Interrupt Enable Register 0x00 0xN305 Block Interrupt Status Register 0x00 Reserved 0x00 0xN30C Test Register 0x00 0xN30D Payload HDLC Control Register 0x00 Reserved 0x00 RxDS3 Configuration and Status Register 0x02 0xN306 – 0xN30B 0xN30E – 0xN30F 0xN310 RxE3 Configuration and Status Register # 1 – G.832 RxE3 Configuration and Status Register # 2 – G.751 0xN311 0x67 RxDS3 Status Register RxE3 Configuration and Status Register # 2 – G.832 RxE3 Configuration and Status Register # 2 – G.751 0xN312 0x00 RxDS3 Interrupt Enable Register RxE3 Interrupt Enable Register # 1 – G.832 RxE3 Interrupt Enable Register # 1 – G.751 0xN313 0x00 RxDS3 Interrupt Status Register RxE3 Interrupt Enable Register # 2 – G.832 RxE3 Interrupt Enable Register # 2 – G.751 0xN314 0x00 RxDS3 Sync Detect Enable Register RxE3 Interrupt Status Register # 1 – G.832 RxE3 Interrupt Status Register # 1 – G.751 0xN315 RxE3 Interrupt Status Register # 2 – G.832 0x00 RxE3 Interrupt Status Register # 2 – G.751 0xN316 RxDS3 FEAC Register 0x7E 0xN317 RxDS3 FEAC Interrupt Enable/Status Register 0x00 0xN318 RxDS3 LAPD Control Register 0x00 RxE3 LAPD Control Register 0xN319 0x00 RxDS3 LAPD Status Register RxE3 LAPD Status Register 0xN31A 0x00 RxE3 NR Byte Register – G.832 RxE3 Service Bit Register –G.751 0xN31B RxE3 GC Byte Register – G.832 0x00 0xN31C RxE3 TTB-0 Register – G.832 0x00 0xN31D RxE3 TTB-1 Register – G.832 0x00 18 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0xN31E RxE3 TTB-2 Register – G.832 0x00 0xN31F RxE3 TTB-3 Register –G.832 0x00 0xN320 RxE3 TTB-4 Register –G.832 0x00 0xN321 RxE3 TTB-5 Register –G.832 0x00 0xN322 RxE3 TTB-6 Register – G.832 0x00 0xN323 RxE3 TTB-7 Register – G.832 0x00 0xN324 RxE3 TTB-8 Register – G.832 0x00 0xN325 RxE3 TTB-9 Register – G.832 0x00 0xN326 RxE3 TTB-10 Register – G.832 0x00 0xN327 RxE3 TTB-11 Register –G.832 0x00 0xN328 RxE3 TTB-12 Register – G.832 0x00 0xN329 RxE3 TTB-13 Register – G.832 0x00 0xN32A RxE3 TTB-14 Register – G.832 0x00 0xN32B RxE3 TTB-15 Register –G.832 0x00 0xN32C RxE3 SSM Register –G.832 0x00 Reserved 0x00 0xN32F RxDS3 Pattern Register 0x00 0xN330 TxDS3 Configuration Register 0x00 0xN32D – 0xN32E TxE3 Configuration Register – G.832 TxE3 Configuration Register – G.751 0xN331 TxDS3 FEAC Configuration and Status Register 0x00 0xN332 TxDS3 FEAC Register 0x7E 0xN333 TxDS3 LAPD Configuration Register 0x08 TxE3 LAPD Configuration Register 0xN334 TxDS3 LAPD Status/Interrupt Register 0x00 TxE3 LAPD Status/Interrupt Register 0xN335 0x00 TxDS3 M-Bit Mask Register TxE3 GC Byte Register – G.832 TxE3 Service Bits Register – G.751 0xN336 0x00 TxDS3 F-Bit Mask # 1 Register TxE3 MA Byte Register – G.832 0xN337 0x00 TxDS3 F-Bit Mask # 2 Register TxE3 NR Byte Register – G.832 0xN338 0x00 TxDS3 F-Bit Mask # 3 Register TxE3 TTB-0 Register – G.832 19 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0xN339 Rev222...000...000 0x00 TxDS3 F-Bit Mask # 4 Register TxE3 TTB-1 Register – G.832 0xN33A TxE3 TTB-2 Register – G.832 0x00 0xN33B TxE3 TTB-3 Register – G.832 0x00 0xN33C TxE3 TTB-4 Register – G.832 0x00 0xN33D TxE3 TTB-5 Register – G.832 0x00 0xN33E TxE3 TTB-6 Register – G.832 0x00 0xN33F TxE3 TTB-7 Register – G.832 0x00 0xN340 TxE3 TTB-8 Register –G.832 0x00 0xN341 TxE3 TTB-9 Register – G.832 0x00 0xN342 TxE3 TTB-10 Register – G.832 0x00 0xN343 TxE3 TTB-11 Register – G.832 0x00 0xN344 TxE3 TTB-12 Register – G.832 0x00 0xN345 TxE3 TTB-13 Register – G.832 0x00 0xN346 TxE3 TTB-14 Register – G.832 0x00 0xN347 TxE3 TTB-15 Register –G.832 0x00 0xN348 TxE3 FA1 Error Mask Register – G.832 0x00 TxE3 FAS Error Mask Upper Register – G.751 0xN349 TxE3 FA2 Error Mask Register – G.832 0x00 TxE3 FAS Error Mask Lower Register – G.751 0xN34A 0x00 TxE3 BIP-8 Mask Register – G.832 TxE3 BIP-4 Mask Register – G.751 0xN34B Tx SSB Register – G.832 0x00 0xN34C TxDS3 Pattern Register 0x0C 0xN34D Receive DS3/E3 AIS/PDI-P Alarm Enable Register 0x00 0xN34E PMON Excessive Zero Count Register - MSB 0x00 0xN34F PMON Excessive Zero Count Register- LSB 0x00 0xN350 PMON LCV Event Count Register - MSB 0x00 0xN351 PMON LCV Event Count Register - LSB 0x00 0xN352 PMON Framing Bit/Byte Error Count Register - MSB 0x00 0xN353 PMON Framing Bit/Byte Error Count Register - LSB 0x00 0xN354 PMON Parity Error Event Count Register - MSB 0x00 0xN355 PMON Parity Error Event Count Register - LSB 0x00 0xN356 PMON FEBE Event Count Register- MSB 0x00 20 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0xN357 PMON FEBE Event Count Register – LSB 0x00 0xN358 PMON CP-Bit Error Count Register - MSB 0x00 0xN359 PMON CP-Bit Error Count Register - LSB 0x00 Reserved 0x00 0xN368 PMON PRBS Bit Error Count Register - MSB 0x00 0xN369 PMON PRBS Bit Error Count Register - LSB 0x00 Reserved 0x00 0xN36C PMON Holding Register 0x00 0xN36D One Second Error Status Register 0x00 0xN36E One Second – LCV Count Accumulator Register - MSB 0x00 0xN36F One Second – LCV Count Accumulator Register - LSB 0x00 0xN370 One Second – Parity Error Accumulator Register - MSB 0x00 0xN371 One Second – Parity Error Accumulator Register - LSB 0x00 0xN372 One Second – CP Bit Error Accumulator Register - MSB 0x00 0xN373 One Second – CP Bit Error Accumulator Register - LSB 0x00 Reserved 0x00 0xN380 Line Interface Drive Register 0x00 0xN381 Reserved 0x00 0xN382 Reserved 0x00 0xN383 Transmit LAPD Byte Count Register 0x00 0xN384 Receive LAPD Byte Count Register 0x00 Reserved 0x00 0xN3B0 Transmit LAPD Memory InAddress LocationRegister 0x00 0xN3B1 Transmit LAPD Memory Indirect Data Register 0x00 0xN3B2 Receive LAPD Memory InAddress LocationRegister 0x00 0xN3B3 Receive LAPD Memory Indirect Data Register 0x00 Reserved 0x00 0xN3F0 Receive DS3/E3 Configuration Register – Secondary Frame Synchronizer Block – Byte 1 0x10 0xN3F1 Receive DS3/E3 Configuration Register – Secondary Frame Synchronizer Block – Byte 0 0x10 0xN3F2 Receive DS3/E3 AIS/PDI-P Alarm Enable Register – Secondary Frame Synchronizer Block 0x00 Reserved 0x00 Receive DS3/E3 Interrupt Enable Register – Secondary Frame Synchronizer 0x00 0xN35A – 0xN367 0xN36A – 0xN36B 0xN374 – 0xN37F 0xN385 – 0xN3AF 0xN3B4 – 0xN3EF 0xN3F3 – 0xN3F7 0xN3F8 21 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Block 0xN3F9 0xN3FA – 0xN4FF Receive DS3/E3 Interrupt Status Register – Secondary Frame Synchronizer Block 0x00 Reserved 0x00 RECEIVE SONET POH PROCESSOR BLOCK – RECEIVE J1 (PATH) TRACE MESSAGE BUFFER Note: N represents the “Channel Number” and ranges in value from 0x02 to 0x04 0xN500 – 0xN53F Receive SONET POH Processor Block – Receive J1 (Path) Trace Message Buffer – Expected and Received 0x00 0xN540 – 0xN7FF Reserved 0x00 TRANSMIT SONET POH PROCESSOR BLOCK REGISTERS Note: N represents the “Channel Number” and ranges in value from 0x02 to 0x04) 0xN800 – 0xN981 Reserved 0x00 0xN982 Transmit SONET Path – SONET Control Register – Byte 1 0x00 0xN983 Transmit SONET Path – SONET Control Register – Byte 0 0x00 Reserved 0x00 Transmit SONET Path – Transmitter J1 Byte Value Register 0x00 Reserved 0x00 0xN996 Transmit SONET Path – B3 Byte Control Register 0x00 0xN997 Transmit SONET Path – B3 Byte Mask Register 0x00 Reserved 0x00 Transmit SONET Path – Transmit C2 Byte Value Register 0x00 Reserved 0x00 Transmit SONET Path – Transmit G1 Byte Value Register 0x00 Reserved 0x00 Transmit SONET Path – Transmit F2 Byte Value Register 0x00 Reserved 0x00 Transmit SONET Path – Transmit H4 Byte Value Register 0x00 Reserved 0x00 Transmit SONET Path – Transmit Z3 Byte Value Register 0x00 Reserved 0x00 Transmit SONET Path – Transmit Z4 Byte Value Register 0x00 Reserved 0x00 Transmit SONET Path – Transmit Z5 Byte Value Register 0x00 Reserved 0x00 0xN984 – 0xN8992 0xN993 0xN994 – 0xN995 0xN998 – 0xN99A 0xN99B 0xN99C – 0xN99E 0xN99F 0xN9A0 – 0xN9A2 0xN9A3 0xN9A4 – 0xN9A6 0xN9A7 0xN9A8 – 0xN9AA 0xN9AB 0xN9AC – 0xN9AE 0xN9AF 0xN9B0 – 0xN9B2 0xN9B3 0xN9B4 – 0xN9B6 22 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0xN9B7 Transmit SONET Path – Transmit Path Control Register – Byte 0 0x00 Reserved 0x00 Transmit SONET Path – Transmit Path Trace Message Control Register 0x00 Reserved 0x00 Transmit SONET Path – Transmit Arbitrary H1 Byte Pointer Register 0x94 Reserved 0x00 Transmit SONET Path – Transmit Arbitrary H2 Byte Pointer Register 0x00 Reserved 0x00 0xN9C6 Transmit SONET Path – Transmit Pointer Byte Register – Byte 1 0x02 0xN9C7 Transmit SONET Path – Transmit Pointer Byte Register – Byte 0 0x0A 0xN9C8 Reserved 0x00 0xN9C9 Transmit SONET Path – RDI-P Control Register – Byte 2 0x40 0xN9CA Transmit SONET Path – RDI-P Control Register – Byte 1 0xC0 0xN9CB Transmit SONET Path – RDI-P Control Register – Byte 0 0xA0 Reserved 0x00 Transmit SONET Path – Transmit Path Serial Port Control Register 0x00 Reserved 0x00 0xN9B8 – 0xN9BA 0xN9BB 0xN9BC – 0xN9BE 0xN9BF 0xN9C0 – 0xN9C2 0xN9C3 0xN9C4 – 0xN9C5 0xN9CC – 0xN9CE 0xN9CF 0xN9D0 – 0xN9FF DS3/E3 MAPPER BLOCK REGISTER Note: N represents the “Channel Number” and ranges in value from 0x02 to 0x04 0xNA00 – 0xNB00 Unused 0x00 0xNB01 Mapper Control Register – Byte 2 0x00 0xNB02 Mapper Control Register – Byte 1 0x03 0xNB03 Mapper Control Register – Byte 0 0x80 Unused 0x00 0xNB06 Receive Mapper Status Register – Byte 1 0x03 0xNB07 Receive Mapper Status Register – Byte 0 0x00 Unused 0x00 Receive Mapper Interrupt Status Register – Byte 0 0x00 Unused 0x00 Receive Mapper Interrupt Enable Register – Byte 0 0x00 Unused 0x00 T3/E3 Routing Register Byte 0x00 0xNB04, 0xNB05 0xNB08 – 0xNB0A 0xNB0B 0xNB0C – 0xNB0E 0xNB0F 0xNB10 – 0xNB12 0xNB13 23 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0xNB14 – 0xNB16 0xNB17 0xNB18 – 0xNCFF Rev222...000...000 Reserved 0x00 Jitter Attenuator – Clock Smoother/Routing Register 0x00 Reserved 0x00 TRANSMIT SONET POH PROCESSOR BLOCK – TRANSMIT J1 (PATH) TRACE MESSAGE BUFFER Note: N represents the “Channel Number” and ranges in value from 0x02 to 0x04 0xND00 – 0xND3F Transmit SONET POH Processor Block – Transmit J1 (Path) Trace Message Buffer 0x00 0xND40 – 0xNEFF Reserved 0x00 RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK REGISTERS Note: N represents the “Channel Number” and ranges in value from 0x05 to 0x07 0xN000 – 0xN102 Reserved 0x00 Receive STS-1 Transport Control Register – Byte 0 0x00 Reserved 0x00 0xN106 Receive STS-1 Transport Status Register – Byte 1 0x00 0xN107 Receive STS-1 Transport Status Register – Byte 0 0x02 0xN108 Reserved 0x00 0xN109 Receive STS-1 Transport Interrupt Status Register – Byte 2 0x00 0xN10A Receive STS-1 Transport Interrupt Status Register – Byte 1 0x00 0xN10B Receive STS-1 Transport Interrupt Status Register – Byte 0 0x00 0xN10C Reserved 0x00 0xN10D Receive STS-1 Transport Interrupt Enable Register – Byte 2 0x00 0xN10E Receive STS-1 Transport Interrupt Enable Register – Byte 1 0x00 0xN10F Receive STS-1 Transport Interrupt Enable Register – Byte 0 0x00 0xN110 Receive STS-1 Transport B1 Byte Error Count – Byte 3 0x00 0xN111 Receive STS-1 Transport B1 Byte Error Count – Byte 2 0x00 0xN112 Receive STS-1 Transport B1 Byte Error Count – Byte 1 0x00 0xN113 Receive STS-1 Transport B1 Byte Error Count – Byte 0 0x00 0xN114 Receive STS-1 Transport B2 Byte Error Count – Byte 3 0x00 0xN115 Receive STS-1 Transport B2 Byte Error Count – Byte 2 0x00 0xN116 Receive STS-1 Transport B2 Byte Error Count – Byte 1 0x00 0xN117 Receive STS-1 Transport B2 Byte Error Count – Byte 0 0x00 0xN118 Reserved 0x00 0xN119 Receive STS-1 Transport REI-L Event Count – Byte 3 0x00 0xN11A Receive STS-1 Transport REI-L Event Count – Byte 2 0x00 0xN103 0xN104 – 0xN105 24 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0xN11B Receive STS-1 Transport REI-L Event Count – Byte 1 0x00 0xN11C Receive STS-1 Transport REI-L Event Count – Byte 0 0x00 Reserved 0x00 Receive STS-1 Transport – Received K1 Byte Value Register 0x00 Reserved 0x00 Receive STS-1 Transport – Received K2 Byte Value Register 0x00 Reserved 0x00 Receive STS-1 Transport – Received S1 Byte Value Register 0x00 Reserved 0x00 0xN12E Receive STS-1 Transport – LOS Threshold Value – MSB 0xFF 0xN12F Receive STS-1 Transport – LOS Threshold Value – LSB 0xFF 0xN130 Reserved 0x00 0xN131 Receive STS-1 Transport – Receive SF Set Monitor Interval – Byte 2 0x00 0xN132 Receive STS-1 Transport – Receive SF Set Monitor Interval – Byte 1 0x00 0xN133 Receive STS-1 Transport – Receive SF Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0xN136 Receive STS-1 Transport – Receive SF Set Threshold – Byte 1 0x00 0xN137 Receive STS-1 Transport – Receive SF Set Threshold – Byte 0 0x00 Reserved 0x00 0xN13A Receive STS-1 Transport – Receive SF Clear Threshold – Byte 1 0x00 0xN13B Receive STS-1 Transport – Receive SF Clear Threshold – Byte 0 0x00 0xN13C Reserved 0x00 0xN13D Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte 2 0x00 0xN13E Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte 1 0x00 0xN13F Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0xN142 Receive STS-1 Transport – Receive SD Set Threshold – Byte 1 0x00 0xN143 Receive STS-1 Transport – Receive SD Set Threshold – Byte 0 0x00 Reserved 0x00 0xN146 Receive STS-1 Transport – Receive SD Clear Threshold – Byte 1 0x00 0xN147 Receive STS-1 Transport – SD Clear Threshold – Byte 0 0x00 Reserved 0x00 Receive STS-1 Transport – Force SEF Condition 0x00 0xN11D – 0xN11E 0xN11F 0xN120 – 0xN122 0xN123 0xN124 – 0xN126 0xN127 0xN128 – 0xN12D 0xN134, 0xN135 0xN138 – 0xN139 0xN140 – 0xN141 0xN144, 0xN145 0xN14B – 0xN14A 0xN14B 25 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0xN14C – 0xN14E 0xN14F 0xN150 – 0xN151 Rev222...000...000 Reserved 0x00 Receive STS-1 Transport – Receive Section Trace Message Buffer Control Register 0x00 Reserved 0xN152 Receive STS-1 Transport – Receive SD Burst Error Count Tolerance – Byte 1 0x00 0xN153 Receive STS-1 Transport – Receive SD Burst Error Count Tolerance – Byte 0 0x00 Reserved 0x00 0xN156 Receive STS-1 Transport – Receive SF Burst Error Count Tolerance – Byte 1 0x00 0xN157 Receive STS-1 Transport – Receive SF Burst Error Count Tolerance – Byte 0 0x00 0xN158 Reserved 0x00 0xN159 Receive STS-1 Transport – Receive SD Clear Monitor Interval – Byte 2 0x00 0xN15A Receive STS-1 Transport – Receive SD Clear Monitor Interval – Byte 1 0x00 0xN15B Receive STS-1 Transport – Receive SD Clear Monitor Interval – Byte 0 0x00 0xN15C Reserved 0x00 0xN15D Receive STS-1 Transport – Receive SF Clear Monitor Interval – Byte 2 0x00 0xN15E Receive STS-1 Transport – Receive SF Clear Monitor Interval – Byte 1 0x00 0xN15F Receive STS-1 Transport – Receive SF Clear Monitor Interval – Byte 0 0x00 Reserved 0x00 Receive STS-1 Transport – Auto AIS Control Register 0x00 Reserved 0x00 Receive STS-1 Transport – Auto AIS (in Downstream STS-1s) Control Register 0x00 Reserved 0x00 Receive STS-1 Path – Control Register – Byte 2 0x00 Reserved 0x00 0xN154, 0xN155 0xN160 – 0xN162 0xN163 0xN164 – 0xN16A 0xN16B 0xN16C – 0xN182 0xN183 0xN184 - 0xN185 0xN186 Receive STS-1 Path – Control Register – Byte 1 0xN187 Receive STS-1 Path – Status Register – Byte 0 0x00 0xN188 Reserved 0x00 0xN189 Receive STS-1 Path – Interrupt Status Register – Byte 2 0x00 0xN18A Receive STS-1 Path – Interrupt Status Register – Byte 1 0x00 0xN18B Receive STS-1 Path – Interrupt Status Register – Byte 0 0x00 0xN18C Reserved 0x00 0xN18D Receive STS-1 Path – Interrupt Enable Register – Byte 2 0x00 0xN18E Receive STS-1 Path – Interrupt Enable Register – Byte 1 0x00 26 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0xN18F Receive STS-1 Path – Interrupt Enable Register – Byte 0 0x00 Reserved 0x00 Receive STS-1 Path – SONET Receive RDI-P Register 0x00 Reserved 0x00 0xN196 Receive STS-1 Path – Received Path Label Value (C2 Byte) Register 0x00 0xN197 Receive STS-1 Path – Expected Path Label Value (C2 Byte) Register 0x00 0xN198 Receive STS-1 Path – B3 Byte Error Count Register – Byte 3 0x00 0xN199 Receive STS-1 Path – B3 Byte Error Count Register – Byte 2 0x00 0xN19A Receive STS-1 Path – B3 Byte Error Count Register – Byte 1 0x00 0xN19B Receive STS-1 Path – B3 Byte Error Count Register – Byte 0 0x00 0xN19C Receive STS-1 Path – REI-P Event Count Register – Byte 3 0x00 0xN19D Receive STS-1 Path – REI-P Event Count Register – Byte 2 0x00 0xN19E Receive STS-1 Path – REI-P Event Count Register – Byte 1 0x00 0xN19F Receive STS-1 Path – REI-P Event Count Register – Byte 0 0x00 Reserved 0x00 0xN1A6 Receive STS-1 Path – Pointer Value Register – Byte 1 0x00 0xN1A7 Receive STS-1 Path – Pointer Value Register – Byte 0 0x00 Reserved 0x00 Receive STS-1 Path – AUTO AIS Control Register 0x00 Reserved 0x00 Receive STS-1 Path – Serial Port Control Register 0x00 Reserved 0x00 Receive STS-1 Path – SONET Receive Auto Alarm Register – Byte 0 0x00 Reserved 0x00 Receive STS-1 Path – Receive J1 Byte Capture Register 0x00 Reserved 0x00 Receive STS-1 Path – Receive B3 Byte Capture Register 0x00 Reserved 0x00 Receive STS-1 Path – Receive C2 Byte Capture Register 0x00 Reserved 0x00 Receive STS-1 Path – Receive G1 Byte Capture Register 0x00 Reserved 0x00 0xN190 – 0xN192 0xN193 0xN194, 0xN195 0xN1A0 – 0xN1A5 0xN1A8 – 0xN1BA 0xN1BB 0xN1BC – 0xN1BE 0xN1BF 0xN1C0 – 0xN1C2 0xN1C3 0xN1C4 –0xN1D2 0xN1D3 0xN1D4 – 0xN1D6 0xN1D7 0xN1D8 – 0xN1DA 0xN1DB 0xN1DC – 0xN1DE 0xN1DF 0xN1E0 – 0xN1E2 27 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0xN1E3 0xN1E4 – 0xN1E6 0xN1E7 0xN1E8 – 0xN1EA 0xN1EB 0xN1EC – 0xN1EE 0xN1EF 0xN1F0 – 0xN1F2 0xN1F3 0xN1F4 – 0xN1FF Rev222...000...000 Receive STS-1 Path – Receive F2 Byte Capture Register 0x00 Reserved 0x00 Receive STS-1 Path – Receive H4 Byte Capture Register 0x00 Reserved 0x00 Receive STS-1 Path – Receive Z3 Byte Capture Register 0x00 Reserved 0x00 Receive STS-1 Path – Receive Z4 (K3) Byte Capture Register 0x00 Reserved 0x00 Receive STS-1 Path – Receive Z5 Byte Capture Register 0x00 Reserved 0x00 RECEIVE STS-1 TOH PROCESSOR BLOCK – RECEIVE J0 (SECTION) TRACE MESSAGE BUFFER Note: N represents the “Channel Number” and ranges in value from 0x05 to 0x07 0xN300 – 0xN33F Receive STS-1 POH Processor Block – Receive J0 (Section) Trace Message Buffer – Expected and Received 0x00 0xN340 – 0xN3FF Reserved 0x00 RECEIVE STS-1 POH PROCESSOR BLOCK – RECEIVE J1 (PATH) TRACE MESSAGE BUFFER Note: N represents the “Channel Number” and ranges in value from 0x05 to 0x07 0xN500 – 0xN53F Receive STS-1 POH Processor Block – Receive J1 (Path) Trace Message Buffer – Expected and Received 0x00 0xN540 – 0xN5FF Reserved 0x00 TRANSMIT STS-1 TOH AND POH PROCESSOR BLOCK REGISTERS Note: N represents the “Channel Numbers” and ranges in value from 0x05 to 0x07) 0xN800 – 0xN901 Reserved 0x00 0xN902 Transmit STS-1 Transport – SONET Transmit Control Register – Byte 1 0x00 0xN903 Transmit STS-1 Transport – SONET Transmit Control Register – Byte 0 0x00 Reserved 0x00 Transmit STS-1 Transport – B1 Byte Error Mask Register 0x00 Reserved 0x00 Transmit STS-1 Transport – Transmit B2 Bit Error Mask Register – Byte 0 0x00 Reserved 0x00 0xN92E Transmit STS-1 Transport – K1K2 (APS) Byte Value Register – Byte 1 0x00 0xN92F Transmit STS-1 Transport – K1K2 (APS) Byte Value Register – Byte 0 0x00 Reserved 0x00 Transmit STS-1 Transport – RDI-L Control Register 0x00 0xN904 – 0xN922 0xN923 0xN924 – 0xN92A 0xN92B 0xN92C – 0xN92D 0xN930 – 0xN932 0xN933 28 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0xN934 – 0xN936 Reserved 0x00 Transmit STS-1 Transport – M0M1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Transport – S1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Transport – F1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Transport – E1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Transport – E2 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Transport – J0 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Transport – Section Trace Message Control Register 0x00 Reserved 0x00 0xN982 Transmit STS-1 Path – SONET Control Register – Byte 1 0x00 0xN983 Transmit STS-1 Path – SONET Control Register – Byte 0 0x00 Reserved 0x00 Transmit STS-1 Path – Transmitter J1 Byte Value Register 0x00 Reserved 0x00 0xN996 Transmit STS-1 Path – B3 Byte Control Register 0x00 0xN997 Transmit STS-1 Path – B3 Byte Mask Register 0x00 Reserved 0x00 Transmit STS-1 Path – Transmit C2 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Path – Transmit G1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Path – Transmit F2 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Path – Transmit H4 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Path – Transmit Z3 Byte Value Register 0x00 Reserved 0x00 0xN937 0xN938 - 0xN93A 0xN93B 0xN93C – 0xN93E 0xN93F 0xN940 – 0xN942 0xN943 0xN944 – 0xN946 0xN947 0xN948 – 0xN94A 0xN94B 0xN94C – 0xN94E 0xN94F 0xN950 – 0xN981 0xN984 – 0xN992 0xN993 0xN994 – 0xN995 0xN998 – 0xN99A 0xN99B 0xN99C – 0xN99E 0xN99F 0xN9A0 – 0xN9A2 0xN9A3 0xN9A4 – 0xN9A6 0xN9A7 0xN9A8 – 0xN9AA 0xN9AB 0xN9AC – 0xN9AE 29 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 0xN9AF Rev222...000...000 Transmit STS-1 Path – Transmit Z4 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Path – Transmit Z5 Byte Value Register 0x00 Reserved 0x00 Transmit STS-1 Path – Transmit Path Control Register – Byte 0 0x00 Reserved 0x00 Transmit STS-1 Path – Transmit Path Trace Message Control Register 0x00 Reserved 0x00 Transmit STS-1 Path – Transmit Arbitrary H1 Byte Pointer Register 0x94 Reserved 0x00 Transmit STS-1 Path – Transmit Arbitrary H2 Byte Pointer Register 0x00 Reserved 0x00 0xN9C6 Transmit STS-1 Path – Transmit Pointer Byte Register – Byte 1 0x02 0xN9C7 Transmit STS-1 Path – Transmit Pointer Byte Register – Byte 0 0x0A 0xN9C8 Reserved 0x00 0xN9C9 Transmit STS-1 Path – RDI-P Control Register – Byte 2 0x40 0xN9C2 Transmit STS-1 Path – RDI-P Control Register – Byte 1 0xC0 0xN9CB Transmit STS-1 Path – RDI-P Control Register – Byte 0 0xA0 Reserved 0x00 Transmit STS-1 Path – Transmit Path Serial Port Control Register 0x00 Reserved 0x00 0xN9B0 – 0xN9B2 0xN9B3 0xN9B4 – 0xN9B6 0xN9B7 0xN9B8 – 0xN9BA 0xN9BB 0xN9BC – 0xN9BE 0xN9BF 0xN9C0 – 0xN9C2 0xN9C3 0xN9C4 – 0xN9C5 0xN9CC – 0xN9CE 0xN9CF 0xN9D0 –0xN9FF TRANSMIT STS-1 TOH PROCESSOR BLOCK – TRANSMIT J0 (PATH) TRACE MESSAGE BUFFER Note: N represents the “Channel Number” and ranges in value from 0x05 to 0x07 0xNB00 – 0xNB3F Transmit STS-1 POH Processor Block – Transmit J0 (Path) Trace Message Buffer 0x00 0xNB40 – 0xNBFF Reserved 0x00 TRANSMIT STS-1 POH PROCESSOR BLOCK – TRANSMIT J1 (PATH) TRACE MESSAGE BUFFER Note: N represents the “Channel Number” and ranges in value from 0x05 to 0x07 0xND00 – 0xND3F 0xND40 – 0xNDFF Transmit STS-1 POH Processor Block – Transmit J1 (Path) Trace Message Buffer 0x00 Reserved 0x00 30 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.2 THE OPERATION CONTROL BLOCK The Operation Control Block is responsible for the following functions. • Control of the Interrupt Structure (at the Highest Level within the XRT94L33) • Control of the Clock Synthesizer block • Control of the STS-3/STM-1 Telecom Bus Interface • Control of the STS-1 Telecom Bus Interfaces The register map for the Operation Control block is presented in the Table below. Additionally, a detailed description of each of the “Operation Control” Block registers is presented below. 1.2.1 OPERATION CONTROL BLOCK REGISTER Table 2: Operation Control Register Address Map ADDRESS LOCATION 0x0000 – 0x00FF REGISTER NAME DEFAULT VALUE Reserved 0x00 0x0100 Operation Control Register – Byte 3 0x00 0x0101 Operation Control Register – Byte 2 0x00 0x0102 Reserved 0x00 0x0103 Operation Control Register – Byte 0 0x00 0x0104 Operation Status Register – Byte 3 (Device ID) 0xE3 0x0105 Operation Status Register – Byte 2 (Revision ID) 0x01 Reserved 0x00 Operation Interrupt Status Register – Byte 0 0x00 Reserved 0x00 Operation Interrupt Enable Register – Byte 0 0x00 Reserved 0x00 0x0112 Operation Block Interrupt Status Register – Byte 1 0x00 0x0113 Operation Block Interrupt Status Register – Byte 0 0x00 Reserved 0x00 0x0116 Operation Block Interrupt Enable Register – Byte 1 0x00 0x0117 Operation Block Interrupt Enable Register – Byte 0 0x00 0x0118 – 0x0119 Reserved 0x00 0x0111A Reserved 0x00 0x011B Mode Control Register – Byte 0 0x00 Reserved 0x00 0x011F Loop-back Control Register – Byte 0 0x00 0x0120 Channel Interrupt Indicator – Receive SONET POH Processor Block 0x00 0x0106 – 0x010A 0x010B 0x010C – 0x010E 0x010F 0x0110 – 0x0111 0x0114 – 0x0115 0x011C – 0x011E 31 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM ADDRESS LOCATION REGISTER NAME Rev222...000...000 DEFAULT VALUE 0x0121 Reserved 0x00 0x0122 Channel Interrupt Indicator – DS3/E3 framer Block 0x00 0x0123 Channel Interrupt Indicator – Receive STS-1 POH Processor Block 0x00 0x0124 Channel Interrupt Indicator – Receive STS-1 TOH Processor Block 0x00 0x0125 Reserved 0x00 0x0126 Channel Interrupt Indicator – STS-1/DS3/E3 Mapper Block 0x00 0x0127 Reserved 0x00 0x0128 Reserved 0x00 0x0129 Reserved 0x00 0x012A Reserved 0x00 Unused 0x00 0x012E Reserved 0x00 0x012F Reserved 0x00 0x0130 Reserved 0x00 0x0131 Reserved 0x00 0x0132 Interface Control Register – Byte 1 0x00 0x0133 Interface Control Register – Byte 0 0x00 0x0134 STS-3/STM-1 Telecom Bus Control Register – Byte 3 0x00 0x0135 STS-3/STM-1 Telecom Bus Control Register – Byte 2 0x00 0x0136 Reserved 0x00 0x0137 STS-3/STM-1 Telecom Bus Control Register – Byte 0 0x00 0x0138 Reserved 0x00 0x0139 Interface Control Register – Byte 2 – STS-1 Telecom Bus 2 0x00 0x013A Interface Control Register – Byte 1 – STS-1 Telecom Bus 1 0x00 0x013B Interface Control Register – Byte 0 – STS-1 Telecom Bus 0 0x00 0x013C Interface Control Register – STS-1 Telecom Bus Interrupt Register 0x00 0x013D Interface Control Register – STS-1 Telecom Bus Interrupt Status Register 0x00 0x013E Interface Control Register – STS-1 Telecom Bus Interrupt Register # 2 0x00 0x013F Interface Control Register – STS-1 Telecom Bus Interrupt Enable Register 0x00 0x0140 – 0x0145 Reserved 0x00 0x0146 Reserved 0x00 0x0147 Operation General Purpose Input/Output Register 0x00 0x012B – 0x012F 32 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S ADDRESS LOCATION REGISTER NAME DEFAULT VALUE 0x0148 – 0x0149 Reserved 0x00 0x014A Reserved 0x00 0x014B Operation General Purpose Input/Output Direction Register 0x00 Reserved 0x00 Operation Output Control Register – Byte 1 0x00 Reserved 0x00 0x0153 Operation Output Control Register – Byte 0 0x00 0x0154 Operation Slow Speed Port Control Register – Byte 1 0x00 Reserved 0x00 0x0157 Operation Slow Speed Port Control Register –Byte 0 0x00 0x0158 Operation – DS3/E3/STS-1 Clock Frequency Out of Range Detection – Direction Register 0x00 0x0159 Reserved 0x00 0x015A Operation – DS3/E3/STS-1 Clock Frequency – DS3 Out of Range Detection Threshold Register 0x00 0x015B Operation – DS3/E3/STS-1 Clock Frequency – STS-1/E3 Out of Range Detection Threshold Register 0x00 0x015C Reserved 0x00 0x015D Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Enable Register – Byte 0 0x00 0x015E Reserved 0x00 0x015F Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Status Register – Byte 0 0x00 Reserved 0x00 0x0180 APS Mapping Register 0x00 0x0181 APS Control Register 0x00 Reserved 0x00 0x0194 APS Status Register 0x00 0x0195 Reserved 0x00 0x0196 APS Status Register 0x00 0x0197 APS Status Register 0x00 0x0198 APS Interrupt Register 0x00 0x0199 Reserved 0x00 0x019A APS Interrupt Register 0x00 0x019B APS Interrupt Register 0x00 0x014C – 0x014F 0x0150 0x0151 –0x0152 0x0155 – 0x0156 0x0160 – 0x017F 0x0182 – 0x0193 33 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM ADDRESS LOCATION REGISTER NAME Rev222...000...000 DEFAULT VALUE 0x019C APS Interrupt Register 0x00 0x019D Reserved 0x00 0x019E APS Interrupt Enable Register 0x00 0x019F APS Interrupt Enable Register 0x00 Reserved 0x00 0x01A0 – 0x01FF 34 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.2.2 OPERATION CONTROL REGISTER DESCRIPTION Table 3: Operation Control Register – Byte 3 (Address Location= 0x0100) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 R/O R/O R/O R/O R/O R/W R/W R/W 0 0 0 0 0 0 0 0 Unused BIT 0 Configuration Control BIT NUMBER NAME TYPE DESCRIPTION Bit 7 – Bit 2 Unused R/O Please set to “0” for normal operation. Bit 1 – Bit 0 Configuration Control R/W Configuration Control: These two READ/WRITE bit-fields permits the user to specify the mode/configuration that the XRT94L33 device should operate in. Please set to “01” for Mapper applications. 35 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 4: Operation Control Register – Byte 2 (Address Location= 0x0101) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 Interrupt Write Clear/RUR Enable Interrupt Clear Interrupt Enable R/O R/O R/O R/O R/O R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION Bit 7 – Bit 3 Unused R/O Please set to “0” for normal operation. Bit 2 Interrupt Write to Clear/RUR R/W Interrupt – Write to Clear/RUR Select: This READ/WRITE bit-field permits the user to configure all of the “SourceLevel” Interrupt Status bits (within the XRT94L33) to either be “Write to Clear” (WTC) or “Reset-upon-Read” (RUR) bits. 0 – Configures all “Source-Level” Interrupt Status register bits to function as “Reset-upon-Read” (RUR). 1 – Configures all “Source-Level” Interrupt Status register bits to function as “Write-to-Clear” (WTC). Bit 1 Enable Interrupt Clear R/W Enable Auto-Clear of Interrupts Select: This READ/WRITE bit-field permits the user to configure the XRT94L33 to automatically disable all interrupts that are activated. 0 – Configures the chip to NOT automatically disable any Interrupts following their activation. 1 – Configures the chip to automatically disable all Interrupts following their activation. Bit 0 Interrupt Enable R/W Interrupt Enable: This READ/WRITE bit-field permits the user to configure the XRT94L33 to generate interrupt requests to the Microprocessor. 0 – Configures the chip to NOT generate interrupt to the Microprocessor. All interrupts are disabled and the Microprocessor must poll the register bits. 1 – Configures the chip to generate interrupts the Microprocessor. 36 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 5: Operation Control Register – Byte 0 (Address Location= 0x0103) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Reserved BIT 0 SW RESET R/W R/W R/O R/O R/W R/O R/O R/W 1 1 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION Bits 7 - 1 Unused R/O Please set to “0” for normal operation Bit 0 SW Reset R/W Software Reset – SONET Block: This READ/WRITE bit-field permits the user to command a software reset to the SONET/SDH block. If the user invokes a software reset to the SONET/SDH blocks then all of the internal state machines will be reset to their default conditions; and each of the Receive STS-1/STS-3 TOH Processor blocks will undergo a re-frame operation. A “0” to “1” transition, within this bit-field commands this Software Reset. Notes: This Software Reset does not reset the command registers to their default state. This can only be achieved by executing a “Hardware RESET” (e.g., by pulling the RESET_L* input pin “LOW”). This Software Reset does not affect the DS3/E3 Framer blocks. The Software Reset bit-field, for the DS3/E3 Framer block can be found in each of the 3 “DS3/E3 Operating Mode” registers (Address Location= 0xNF00). 37 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 6: Operation Status Register – Byte 3 (Address Location= 0x0104) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Device ID Value R/O R/O R/O R/O R/O R/O R/O R/O 1 1 1 0 0 0 1 1 BIT NUMBER NAME TYPE 7–0 Device ID Value R/O DESCRIPTION Device ID Value: This READ-ONLY bit-field is set to the value “0xE3” and permits the user’s software code to uniquely identify this device as being the XRT94L33. Table 7: Operation Status Register – Byte 2 (Address Location= 0x0105) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Revision Number Value R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 1 BIT NUMBER NAME TYPE 7–0 Revision Number Value R/O DESCRIPTION Revision NumberValue: This READ-ONLY bit-field is set to the value that corresponds to its revision number. Revision A silicon will be set to the value “0x01”. This register permits the user’s software code to uniquely identify the revision number of this device. 38 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 8: Operation Interrupt Status Register – Byte 0 (Address Location= 0x010B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Unused BIT 0 TB Parity Error Interrupt Status R/O R/O R/O R/O R/O R/O R/O RUR/WTC 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE Bit 7 – Bit 1 Unused R/O Bit 0 TB Parity Error Interrupt Status RUR/ WTC DESCRIPTION Please set to “0” for normal operation Telecom Bus Parity Error Interrupt Status: This “RESET-upon-READ” bit-field indicates whether or not the “Detection of 155.52Mbps Telecom Bus – Parity Error” interrupt has occurred since the last read of this register bit. 0 – Indicates that the “Detection of 155.52Mbps Telecom Bus – Parity Error” interrupt has NOT occurred since the last read of this register bit. 1 – Indicates that the “Detection of 155.52Mbps Telecom Bus – Parity Error” interrupt has occurred since the last of this register bit. Note: This register bit is only active if the 155.52Mbps port is configured to operate via the Telecom Bus. Table 9: Operation Interrupt Enable Register – Byte 0 (Address Location= 0x010F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Unused BIT 0 Telecom Bus Parity Error Interrupt Enable R/O R/O R/O R/O R/O R/O R/O R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION Bit 7 – Bit 1 Unused R/O Please set to “0” for normal operation Bit 0 TB Parity Error Interrupt Enable R/W Telecom Bus Parity Error Interrupt Enable: This “READ/WRITE” bit-field permits the user to either enable or disable the “Detection of 155.52Mbps Telecom Bus – Parity Error” interrupt. 0 – Disables the “Detection of 155.52Mbps Telecom Bus – Parity Error” interrupt. 1 – Enables the “Detection of 155.52Mbps Telecom Bus – Parity Error” interrupt. Note: This register bit is only active if the 155.52Mbps port is configured to operate via the Telecom Bus. 39 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 10: Operation Block Interrupt Status Register – Byte 1 (Address Location= 0x0112) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Operation Control Block Interrupt Status DS3/E3 Mapper Block Interrupt Status Unused Receive STS-1 TOH Processor Block Interrupt Status Receive STS-1 POH Processor Block Interrupt Status DS3/E3 Framer Block Interrupt Status Receive Line Interface Block Interrupt Status Unused R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Operation Control Block Interrupt Status R/O DESCRIPTION Operation Control Block Interrupt Status: This READ-ONLY bit-field indicates whether or not an Operation Control Block-related Interrupt is awaiting service. 0 – Indicates that no Operation Control Block Interrupts are awaiting service. 1 – Indicates that at least one “Operation Control Block” Interrupt is awaiting service. 6 DS3/E3 Mapper Block Interrupt Status R/O DS3/E3 Mapper Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a DS3/E3 Mapper Block-related Interrupt is awaiting service. 0 – Indicates that no DS3/E3 Mapper Block interrupt is awaiting service. 1 – Indicates that at least one “DS3/E3 Mapper Block” Interrupt is awaiting service. 5 Unused R/O 4 Receive STS-1 TOH Processor Block Interrupt Status R/O Receive STS-1 TOH Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not an “Receive STS-1 TOH Processor” Block Interrupt is awaiting service. 0 – Indicates that no “Receive STS-1 TOH Processor” block interrupt is awaiting service. 1 – Indicates that at least one “Receive STS-1 TOH Processor” block interrupt is awaiting service. 3 Receive STS-1 POH Processor Block Interrupt Status R/O Receive STS-1 Path Overhead (POH) Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not an “Receive STS-1 POH Processor” Block Interrupt is awaiting service. 0 – Indicates that no “Receive STS-1 POH Processor” block interrupt is awaiting service. 1 – Indicates that at least one “Receive STS-1 POH Processor” block interrupt is awaiting service. 2 DS3/E3 Framer Block Interrupt Status R/O DS3/E3 Framer Block Interrupt Status This READ-ONLY bit-field indicates whether or not a “DS3/E3 Framer Block” interrupt is awaiting service. 40 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0 – Indicates that no “DS3/E3 Framer” block interrupt is awaiting service. 1 – Indicates that at least one “DS3/E3 Framer” block interrupt is awaiting service. Receive Line Interface Block Interrupt Status 1 R/O Receive Line Interface Block Interrupt Status This READ-ONLY bit-field indicates whether or not a “Receive Line Interface Block” interrupt is awaiting service. 0 – Indicates that no “Receive Line Interface” block interrupt is awaiting service. 1 – Indicates that at least one “Receive Line Interface” block interrupt is awaiting service. 0 Unused R/O Table 11: Operation Block Interrupt Status Register – Byte 0 (Address Location= 0x0113) BIT 7 BIT 6 BIT 5 Unused Receive STS-3 TOH Processor Block Interrupt Status Receive SONET POH Processor Block Interrupt Status R/O R/O R/O R/O R/O 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Receive STS-3 TOH Processor Block Interrupt Status R/O BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O 0 0 0 Unused DESCRIPTION Receive STS-3 TOH Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a “Receive STS-3 TOH Processor Block” interrupt is awaiting service. 0 – Indicates that no “Receive STS-3 TOH Processor Block” Interrupt is awaiting service. 1 – Indicates that at least one “Receive STS-3 TOH Processor Block” interrupt is awaiting service. 5 Receive SONET POH Processor Block Interrupt Status R/O Receive SONET POH Processor Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a “Receive SONET POH Processor Block” interrupt is awaiting service. 0 – Indicates that no “Receive SONET POH Processor Block” Interrupt is awaiting service. 1 – Indicates that at least one “Receive SONET POH Processor Block” Interrupt is awaiting service. 4-0 Unused R/O 41 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 12: Operation Block Interrupt Enable Register – Byte 1 (Address Location= 0x0116) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Operation Control Block Interrupt Enable DS3/E3 Mapper Block Interrupt Enable Unused Receive STS-1 TOH Processor Block Interrupt Enable Receive STS-1 POH Processor Block Interrupt Enable DS3/E3 Framer Block Interrupt Enable Receive Line Interface Block Interrupt Enable Unused R/W R/W R/O R/W R/W R/W R/W R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Operation Control Block Interrupt Enable R/W DESCRIPTION Operation Control Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the Operation Control Block for interrupt generation. If the user writes a “0” into this register bit and disables the “Operation Control Block, then all “Operation Control Block” interrupts will be disabled for interrupt generation. If the user writes a “1” into this register bit, he/she will still need to enable the individual “Operation Control Block” interrupt(s) at the “Source Level” in order to enable that particular interrupt. 0 – Disables all “Operation Control Block” interrupts within the device. 1 – Enables the “Operation Control Block” at the “Block-Level” for interrupt generation 6 DS3/E3 Mapper Block Interrupt Enable R/W DS3/E3 Mapper Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the DS3/E3 Mapper Block for interrupt generation. If the user writes a “0” into this register bit, then all “DS3/E3 Mapper Block” interrupts will be disabled for interrupt generation. If the user writes a “1” into this register bit, he/she will still need to enable the individual “DS3/E3 Mapper Block” interrupt(s) at the “Source Level” in order to enable that particular interrupt. 0 – Disables all “DS3/E3 Mapper Block” interrupts within the device. 1 – Enables the “DS3/E3 Mapper Block” at the “Block-Level” 5 Unused R/O 4 Receive STS-1 TOH Block Interrupt Enable R/W Receive STS-1 TOH (Transport Overhead) Processor Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the Receive STS-1 TOH Processor Block for interrupt generation. If the user writes a “0” to this register bit and disables the “Receive STS-1 TOH Processor Block” (for interrupt generation), then all “Receive STS-1 TOH Processor Block” interrupts will be disabled for interrupt generation. If the user writes a “1” to this register bit, he/she will still need to enable the individual “Receive STS-1 TOH Processor Block” interrupt(s) at the “Source Level” in order to enable that particular interrupt. 0 – Disables all “Receive STS-1 TOH Processor Block” interrupts within the device. 1 – Enables the “Receive STS-1 TOH Processor Block” at the “Block-Level”. Note: This bit-field is inactive if the XRT94L33 has been configured to operate in the SDH Mode. 42 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 3 Receive STS-1 POH Block Interrupt Enable R/W Receive STS-1 POH (Path Overhead) Processor Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the Receive STS-1 POH Processor Block for interrupt generation. If the user writes a “0” to this register bit and disables the “Receive STS-1 POH Processor Block” (for interrupt generation), then all “Receive STS-1 POH Processor Block” interrupts will be disabled for interrupt generation. If the user writes a “1” to this register bit, he/she will still need to enable the individual “Receive STS-1 POH Processor Block” interrupt(s) at the “Source Level” in order to enable that particular interrupt. 0 – Disables all “Receive STS-1 POH Processor Block” interrupts within the device. 1 – Enables the “Receive STS-1 POH Processor Block” at the “Block-Level”. Note: 2 DS3/E3 Framer Block Interrupt Enable R/W This bit-field is inactive if the XRT94L33 has been configured to operate in the SDH Mode. DS3/E3 Framer Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the DS3/E3 Framer Block for interrupt generation. If the user writes a “0” to this register bit and disables the “DS3/E3 Framer Block” (for interrupt generation), then all “DS3/E3 Framer Block” interrupts will be disabled for interrupt generation. If the user writes a “1” to this register bit, he/she will still need to enable the individual “DS3/E3 Framer Block” interrupt(s) at the “Source Level” in order to enable that particular interrupt. 0 – Disables all “DS3/E3 Framer Block” interrupts within the device. 1 – Enables the “DS3/E3 Framer Block” at the “Block-Level”. 1 Receive Line Interface Block Interrupt Enable R/W Receive Line Interface Block Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the Receive Line Interface Block for interrupt generation. If the user writes a “0” to this register bit and disables the “Receive Line Interface Block” (for interrupt generation), then all “Receive Line Interface Block” interrupts will be disabled for interrupt generation. If the user writes a “1” to this register bit, he/she will still need to enable the individual “Receive Line Interface Block” interrupt(s) at the “Source Level” in order to enable that particular interrupt. 0 – Disables all “Receive Line Interface Block” interrupts within the device. 1 – Enables the “Receive Line Interface Block” at the “Block-Level”. 0 Unused R/O 43 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 13: Operation Block Interrupt Enable Register – Byte 0 (Address Location= 0x0117) BIT 7 BIT 6 BIT 5 Unused Receive STS-3 TOH Block Interrupt Enable Receive SONET POH Block Interrupt Enable R/O R/W R/W R/O R/O 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Receive STS-3 TOH Block Interrupt Enable R/W BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O 0 0 0 Unused DESCRIPTION Receive STS-3 TOH Processor Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Receive STS-3 TOH Processor Block” for interrupt generation. If the user writes a “0” to this register bit and disables the “Receive STS-3 TOH Processor Block” (for interrupt generation), then all “Receive STS-3 TOH Processor Block” interrupts will be disabled for interrupt generation. If the user writes a “1” to this register bit, he/she will still need to enable the individual “Receive STS-3 TOH Processor Block” interrupt(s) at the “Source Level” in order to enable that particular interrupt. 0 – Disables all “Receive STS-3 TOH Processor Block” interrupts within the device. 1 – Enables the “Receive STS-3 TOH Processor Block” at the “Block Level” for interrupt generation. 5 Receive SONET POH Block Interrupt Enable R/W Receive SONET POH Processor Block Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Receive SONET POH Processor Block” for interrupt generation. If the user writes a “0” into this register bit and disables the “Receive SONET POH Processor Block” (for interrupt generation), then all “Receive SONET Processor Block” interrupts will be disabled for interrupt generation. If the user writes a “1” to this register bit, then he/she will still need to enable the individual “Receive SONET POH Processor Block” Interrupt(s) at the “Source Level” in order to enable that particular interrupt. 0 – Disables all “Receive SONET POH Processor Block” Interrupts within the device. 1 – Enables the “Receive SONET POH Processor Block” at the “Block Level” for interrupt generation. 4-0 Unused R/O 44 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 14: Mode Control Register – Byte 0 (Address Location= 0x011B) BIT 7 BIT 6 BIT 5 BIT 4 Disable Jitter Attenuator Fast Lock TBUS0_IS_ SDH V1_PULSE_ EN TBUS0_MA STER R/W R/W R/W R/W R/O R/O R/O R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 DISFASTLOCK R/W BIT 3 BIT 2 BIT 1 BIT 0 AU-3/TUG-3* Mapping Select Reserved DESCRIPTION Disable Jitter Attenuator Fast lock: This READ/WRITE bit field is used to disable the fast lock feature for the Jitter Attenuator block 0 – Fast Lock feature is enabled 1 – Fast Lock feature is disabled Note: 6 TBUS0_IS_SDH To configure the XRT94L33 such that it will comply with the Telcordia GR-253-CORE APS Recovery time requirements of 50ms, then the “Fast Lock” feaure MUST be enabled within the Jitter Attenuator block, by setting this bit-field to “0” Telecom Bus 0 operating in SDH Mode This bit is used to qualify and process a Highrate SDH signal for Subrate Telecom Bus 0 operation. 0 - Clearing this bit will disable SDH format signal validation on Telecom Bus 0. Subrate Telecom Bus 0 RxD[7:0] data bus ouput will be disabled. 1 - Setting this bit will enable SDH format signal validation on Telecom Bus 0. It enables RxD[7:0] data bus output upon reception of a valid SDH signal format structure. Note: 5 V1_PULSE_EN This bit must be enabled in SDH mode for Subrate Telecom Bus 0 operation. This bit is ignored and does not apply in SONET mode of operation. V1 Pulse Enable This bit provides the option of using an additional pulse on the Telecom Drop Bus RxD_C1J1 output pin and Telecom Add Bus TxA_C1J1 pin to denote the location or onset of V1 Byte within the Synchronous Payload Envelope/Virtual Container of the SONET/SDH frame whenever the Telecom Bus is processing the Virtual Tributary Group/Virtual Container multi-frame boundary 0 - Telecom Bus 0 in STS-3/STM-1 mode will not indicate a V1 pulse on RxD_CIJ1V1 output pin and TxA_C1J1V1 pin to indicate VT/VC multi-frame boundary. 1 - Telecom Bus 0 in STS-3/STM-1 mode has V1 pulse added on RxD_CIJ1V1 output pin and TxA_C1J1V1 pin to indicate VT/VC multi-frame boundary 4 TBUS0_MASTER Select Phase Timing Reference This bit selects TxA_C1J1V1 and TxA_PL phase timing reference when operating the Subrate Add Telecom Bus 0 in Rephase OFF mode. 0 - Add Telecom Bus 0 timing in Slave Mode. TxA_C1J1V1 and TxA_PL 45 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 pins are inputs. 1 - Add Telecom Bus 0 timing in Master Mode. TxA_C1J1V1 and TxA_PL pins are outputs. 3-1 Unused R/O Reserved 0 AU-3/TUG-3* R/W AU-3/TUG-3 Mapping Select: This READ/WRITE bit-field is used to to specify how the DS3/E3 data, associated with Channels 0, 1 and 2 are mapped into an SDH signal, as indicated below. 0 – DS3/E3 Channels are mapped into a VC-3, a TU-3, and then finally a TUG-3 structure, when being mapped into an STM-1 signal. 1 – DS3/E3 Channels are mapped into a VC-3 and then an AU-3 when being mapped into an STM-1 signal. Note: This register bit is only active if the XRT94L33 has been configured to operate in the SDH Mode. 46 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 15: Loop-back Control Register – Byte 0 (Address Location= 0x011F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 Loop-back[3:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Unused R/O 3-0 Loop-back[3:0] R/W DESCRIPTION Loop-back Mode[3:0] These four READ/WRITE bits-fields permit the user to configure the XRT94L33 to operate in a variety of loop-back modes, as is tabulated below. Loop-back[3:0] Resulting Loop-back Mode 0000 Normal Mode (e.g., No Loop-back Mode) 0001 Remote Line Loop-back: In this mode, all data that is received by the “Receive STS-3 TOH Processor” block will be routed to the “Transmit STS-3 TOH Processor block. Note: 0010 If the user invokes this loop-back, then he/she must configure the Transmit STS-3/STM-1 circuitry to operate in the Loop-timing mode by setting Bit 6 (STS-3 Loop-Timing Mode) within the Receive Line Interface Control Register – Byte 1, to “1” (Address Location: 0x0302). Local Transport Loop-back: In this mode, all data that is being output via the “Transmit STS-3 TOH Processor” block will also be internally routed to the “Receive STS-3 TOH Processor” block. NOTES: 0011 1. If the user configures the XRT94L33 device to operate in the “Local Transport Loop-back” Mode, then, in addition to “routing” the Transmit Output STS-3 data back into the “Receive Path”, the Transmit Output STS-3 data is still output via either the Transmit STS-3 PECL Interface or the Transmit STS-3 Telecom Bus Interface. 2. The user must disable all “Automatic Transmission of AIS-P/AIS indicator upon Defects” features (within the chip) in order to permit this loop-back to function properly. Local Path Loop-back: In this mode, all data that is output by the 47 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Transmit SONET POH Processor block (e.g., towards the “Transmit STS-3 TOH Processor” block) will be internally routed to the “Receive SONET POH Processor” block. NOTES: 0100 - 1111 48 1. This setting applies to all 3 Transmit SONET POH Processor and Receive SONET POH Processor blocks within the XRT94L33 device. 2. The user must disable all “Automatic Transmission of AIS-P/AIS indicator upon Defects” features (within the chip) in order to permit this loop-back to function properly. Reserved – Do Not Use XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 16: Channel Interrupt Indicator – Receive SONET POH Processor Block (Address Location= 0x0120) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Receive STS-3c POH Processor Block Interrupt Receive AU-4 Mapper/ VC-3 POH Block Interrupt Receive SONET POH Block Interrupt Ch 2 Receive SONET POH Block Interrupt Ch 1 Receive SONET POH Block Interrupt Ch 0 R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-5 Unused 4 Receive STS-3c POH Block Interrupt R/O DESCRIPTION Receive STS-3c POH Processor Block Interrupt: This READ/ONLY bit-field indicates whether or not the “Receive STS-3c POH Processor” block is current requesting interrupt service, as described below. 0 – Indicates that the Receive STS-3c POH Processor block is NOT declaring an Interrupt. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring an Interrupt. Note: 3 Receive AU-4 Mapper/VC-3 POH Block Interrupt R/O This register bit is only active if the XRT94L33 has been configured to support an STS-3c signal via Channel 0. Receive AU-4 Mapper/VC-3 POH Processor Block Interrupt: This READ/ONLY bit-field indicates whether or not the “Receive AU-4 Mapper/VC-3 POH Processor” block is currently requesting Interrupt service, as described below. 0 – Indicates that the Receive AU-4 Mapper/VC-3 POH Processor block is NOT currenty declaring an Interrupt. 1 – Indicates that the Receive AU-4 Mapper/VC-3 POH Processor block is currently declaring an interrupt. Note: 2 Receive SONET POH Block Interrupt Channel 2 R/O This register bit is only if the XRT94L33 device has been configured to operate in the SDH/TUG-3 Mapper Mode. Receive SONET POH Processor Block Interrupt – Channel 2: This READ/ONLY bit-field indicates whether or not the “Receive SONET POH Processor” block, associated with Channel 2 is declaring an Interrupt, as described below. 0 – The Receive SONET POH Processor block, associated with Channel 2 is NOT currently declaring an Interrupt. 1 – The Receive SONET POH Processor block, associated with Channel 2 is currently declaring an interrupt. 1 Receive SONET POH Block Interrupt Channel 1 R/O Receive SONET POH Processor Block Interrupt – Channel 1: This READ/ONLY bit-field indicates whether or not the “Receive SONET POH Processor” block, associated with Channel 1 is declaring an Interrupt, as described below. 0 – The Receive SONET POH Processor block, associated with Channel 9 49 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 is NOT declaring an Interrupt. 1 – The Receive SONET POH Processor block, associated with Channel 9 is currently declaring an interrupt. 0 Receive SONET POH Block Interrupt Channel 0 R/O Receive SONET POH Processor Block Interrupt – Channel 0: This READ/ONLY bit-field indicates whether or not the “Receive SONET POH Processor” block, associated with Channel 0 is declaring an Interrupt, as described below. 0 – The Receive SONET POH Processor block, associated with Channel 0 is NOT declaring an Interrupt. 1 – The Receive SONET POH Processor block, associated with Channel 0 is currently declaring an interrupt. 50 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 17: Channel Interrupt Indicator – DS3/E3 Framer Block (Address Location= 0x0122) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 DS3/E3 Framer Block Interrupt Ch 2 DS3/E3 Framer Block Interrupt Ch 1 DS3/E3 Framer Block Interrupt Ch 0 R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 –3 Unused R/O 2 DS3/E3 Framer Block Interrupt Ch 2 R/O DESCRIPTION DS3/E3 Framer Block Interrupt – Channel 2: This READ/ONLY bit-field indicates whether or not the “DS3/E3 Framer” block, associated with Channel 2 is declaring an Interrupt, as described below. 0 – The DS3/E3 Framer block, associated with Channel 2 is NOT currently declaring an Interrupt. 1 – The DS3/E3 Framer block, associated with Channel 2 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 2 has been configured to operate in the DS3/E3 Mode. 1 DS3/E3 Framer Block Interrupt Ch 1 R/O DS3/E3 Framer Block Interrupt – Channel 1: This READ/ONLY bit-field indicates whether or not the “DS3/E3 Framer” block, associated with Channel 1 is declaring an Interrupt, as described below. 0 – The DS3/E3 Framer block, associated with Channel 1 is NOT declaring an Interrupt. 1 – The DS3/E3 Framer block, associated with Channel 1 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 1 has been configured to operate in the DS3/E3 Mode. 0 DS3/E3 Framer Block Interrupt Ch 0 R/O DS3/E3 Framer Block Interrupt – Channel 0: This READ/ONLY bit-field indicates whether or not the “DS3/E3 Framer” block, associated with Channel 0 is declaring an Interrupt, as described below. 0 – The DS3/E3 Framer block, associated with Channel 0 is NOT declaring an Interrupt. 1 – The DS3/E3 Framer block, associated with Channel 0 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 0 has been configured to operate in the DS3/E3 Mode. 51 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 18: Channel Interrupt Indicator – Receive STS-1 POH Processor Block (Address Location= 0x0123) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 Receive STS-1 POH Block Interrupt Ch 2 Receive STS1 POH Block Interrupt Ch 1 Receive STS-1 POH Block Interrupt Ch 0 R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–3 Unused R/O 2 Receive STS-1 POH Block Interrupt Channel 2 R/O DESCRIPTION Receive STS-1 POH Processor Block Interrupt – Channel 2: This READ/ONLY bit-field indicates whether or not the “Receive STS-1 POH Processor” block, associated with Channel 2 is declaring an Interrupt, as described below. 0 – The Receive STS-1 POH Processor block, associated with Channel 2 is NOT declaring an Interrupt. 1 – The Receive STS-1 POH Processor block, associated with Channel 2 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 2 has been configured to operate in the STS-1 Mode. 1 Receive STS-1 POH Block Interrupt Channel 1 R/O Receive STS-1 POH Processor Block Interrupt – Channel 1: This READ/ONLY bit-field indicates whether or not the “Receive STS-1 POH Processor” block, associated with Channel 1 is declaring an Interrupt, as described below. 0 – The Receive STS-1 POH Processor block, associated with Channel 1 is NOT declaring an Interrupt. 1 – The Receive STS-1 POH Processor block, associated with Channel 1 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 1 has been configured to operate in the STS-1 Mode. 0 Receive STS-1 POH Block Interrupt Channel 0 R/O Receive STS-1 POH Processor Block Interrupt – Channel 0: This READ/ONLY bit-field indicates whether or not the “Receive STS-1 POH Processor” block, associated with Channel 0 is declaring an Interrupt, as described below. 0 – The Receive STS-1 POH Processor block, associated with Channel 0 is NOT declaring an Interrupt. 1 – The Receive STS-1 POH Processor block, associated with Channel 0 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 0 has been configured to operate in the STS-1 Mode. 52 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 19: Channel Interrupt Indicator – Receive STS-1 TOH Processor Block (Address Location= 0x0124) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 Receive STS-1 TOH Block Interrupt Ch 2 Receive STS-1 TOH Block Interrupt Ch 1 Receive STS-1 TOH Block Interrupt Ch 0 R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–3 Unused R/O 2 Receive STS-1 TOH Block Interrupt Channel 2 R/O DESCRIPTION Receive STS-1 TOH Processor Block Interrupt – Channel 2: This READ/ONLY bit-field indicates whether or not the “Receive STS-1 TOH Processor” block, associated with Channel 2 is declaring an Interrupt, as described below. 0 – The Receive STS-1 TOH Processor block, associated with Channel 2 is NOT declaring an Interrupt. 1 – The Receive STS-1 TOH Processor block, associated with Channel 2 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 2 has been configured to operate in the STS-1 Mode. 1 Receive STS-1 TOH Block Interrupt Channel 1 R/O Receive STS-1 TOH Processor Block Interrupt – Channel 1: This READ/ONLY bit-field indicates whether or not the “Receive STS-1 TOH Processor” block, associated with Channel 1 is declaring an Interrupt, as described below. 0 – The Receive STS-1 TOH Processor block, associated with Channel 1 is NOT declaring an Interrupt. 1 – The Receive STS-1 TOH Processor block, associated with Channel 1 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 1 has been configured to operate in the STS-1 Mode. 0 Receive STS-1 TOH Block Interrupt Channel 0 R/O Receive STS-1 TOH Processor Block Interrupt – Channel 0: This READ/ONLY bit-field indicates whether or not the “Receive STS-1 TOH Processor” block, associated with Channel 0 is declaring an Interrupt, as described below. 0 – The Receive STS-1 TOH Processor block, associated with Channel 0 is NOT declaring an Interrupt. 1 – The Receive STS-1 TOH Processor block, associated with Channel 0 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 0 has been configured to operate in the STS-1 Mode. 53 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 20: Channel Interrupt Indicator –DS3/E3 Mapper Block (Address Location= 0x0126) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 DS3/E3 Mapper Block Interrupt Ch 2 DS3/E3 Mapper Block Interrupt Ch 1 DS3/E3 Mapper Block Interrupt Ch 0 R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–3 Unused R/O 2 DS3/E3 Mapper Block Interrupt Channel 2 R/O DESCRIPTION DS3/E3 Mapper Block Interrupt – Channel 2: This READ/ONLY bit-field indicates whether or not the “DS3/E3 Mapper” block, associated with Channel 2 is declaring an Interrupt, as described below. 0 – The DS3/E3 Mapper block, associated with Channel 2 is NOT declaring an Interrupt. 1 – The DS3/E3 Mapper block, associated with Channel 2 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 2 has been configured to operate in the DS3/E3 Mode. 1 DS3/E3 Mapper Block Interrupt Channel 1 R/O DS3/E3 Mapper Block Interrupt – Channel 1: This READ/ONLY bit-field indicates whether or not the “DS3/E3 Mapper” block, associated with Channel 1 is declaring an Interrupt, as described below. 0 – The DS3/E3 Mapper block, associated with Channel 1 is NOT declaring an Interrupt. 1 – The DS3/E3 Mapper block, associated with Channel 1 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 1 has been configured to operate in the DS3/E3 Mode. 0 DS3/E3 Mapper Block Interrupt Channel 0 R/O DS3/E3 Mapper Block Interrupt – Channel 0: This READ/ONLY bit-field indicates whether or not the “DS3/E3 Mapper” block, associated with Channel 0 is declaring an Interrupt, as described below. 0 – The DS3/E3 Mapper block, associated with Channel 0 is NOT declaring an Interrupt. 1 – The DS3/E3 Mapper block, associated with Channel 0 is currently declaring an interrupt. NOTE: This bit-field is only active if Channel 0 has been configured to operate in the DS3/E3 Mode. 54 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 21: Interface Control Register – Byte 1 (Address Location= 0x0132) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Receive STS-3/STM-1 Line Select[1:0] Unused BIT 2 BIT 1 BIT 0 Transmit STS-3/STM-1 Line Select[1:0] Unused R/O R/O R/W R/W R/O R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–6 Unused R/O 5–4 Receive STS3/STM-1 Line Select[1:0] R/W DESCRIPTION Receive STS-3/STM-1 Line Select[1:0]: These two READ/WRITE bit-fields permit the user to configure the Receive STS-3 TOH Processor block to either accept its STS-3/STM-1 data from the Receive STS-3/STM-1 Telecom Bus Interface, or from the Receive STS-3/STM-1 PECL Interface. 0, 0 – Configures the Receive STS-3 TOH Processor block to accept the incoming STS-3/STM-1 data via the Receive STS-3/STM-1 PECL Interface block 0, 1 – Configures the Receive STS-3 TOH Processor block to accept the incoming STS-3/STM-1 data via the Receive STS-3/STM-1 Telecom Bus Interface block 1, 0 and 1, 1 – Do not use. 3–2 Unused R/O 1–0 Transmit STS3/STM-1 Line Select[1:0] R/W Transmit STS-3/STM-1 Line Select[1:0]: These two READ/WRITE bit-fields permit the user to configure the Transmit STS-3 TOH Processor block to output its outbound STS-3/STM1 data to either the Transmit STS-3/STM-1 Telecom Bus Interface, or to the Transmit STS-3/STM-1 PECL Interface. 0, 0 – Configures the Transmit STS-3 TOH Processor block to output the outbound STS-3/STM-1 data via the Transmit STS-3/STM-1 PECL Interface block 0, 1 – Configures the Transmit STS-3 TOH Processor block to output the outbound STS-3/STM-1 data via the Transmit STS-3/STM-1 Telecom Bus Interface block 1, 0 and 1, 1 – Do not use. 55 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 22: Interface Control Register – Byte 0 (Address Location= 0x0133) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SBSYNC_Delay[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 SBSYNC_Delay[7:0] R/W DESCRIPTION STS-1 Telecom Bus – Sync Delay: The Transmit STS-1 Telecom Bus is aligned to the “TxSBFP_in” input pin. The user is expected to apply a pulse (with the period of a 6.48MHz clock signal) at a rate of 8kHz to the “TxSBFP_in input (pin number G4). Each Transmit STS-1 Telecom Bus will align its transmission of the very first byte of a new STS-1 frame, with a pulse at this input pin. These READ/WRITE bit-fields permit the user to specify the amount of delay (in terms of 6.48MHz clock periods) that will exist between the rising edge of “TxSBFP_in” and the transmission of the very first byte, within a given STS-1 via the Transmit STS-1 Telecom Bus. Setting this register to “0x00” configures each of the Transmit STS-1 Telecom Bus Interfaces to transmit the very first byte of a new STS-1 frame, upon detection of the rising edge of the “TxSBFP_in”. Setting this register to “0x01” configures each of the Transmit STS-1 Telecom Bus Interfaces to delay its transmission of the very first byte of a new STS-1 frame, by one 6.48MHz clock period, and so on. Note: This register is only active if at least one of the three STS-1 Telecom Bus Interfaces are enabled. 56 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 23: STS-3/STM-1 Telecom Bus Control Register – Byte 3 (Address Location= 0x0134) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 HRSYNC_Delay[15:8] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 HRSYNC_Delay[15:8] R/W DESCRIPTION STS-3 Telecom Bus – Sync Delay – Upper Byte: The Transmit STS-3 TOH Processor block will generate the outbound STS-3/STM-1 frames in alignment with the 8kHz pulse that is being applied to the “TxSBFP_in” input pin. The user is expected to apply a pulse (with the period of a 19.44MHz clock signal) at a rate of 8kHz to the “TxSBFP_in input (pin number G4). The Transmit STS-3/STM-1 Telecom Bus will align its transmission of the very first byte of a new STS-3/STM-1 frame, with a pulse at this input pin. These READ/WRITE bit-fields permit the user to specify the amount of delay (in terms of 19.44MHz clock periods) that will exist between the rising edge of “TxSBFP_in” and the transmission of the very first byte, within a given STS-3 via the Transmit STS-3/STM-1 Telecom Bus. Setting these two registers to “0x0000” configures each of the Transmit STS-3/STM-1 Telecom Bus Interfaces to transmit the very first byte of a new STS-3 frame, upon detection of the rising edge of the “TxSBFP_in”. Setting these register to “0x0001” configures each of the Transmit STS3 Telecom Bus Interfaces to delay its transmission of the very first byte of a new STS-3 frame, by one 19.44MHz clock period, and so on. Note: This register is also active if the user has configured the XRT94L33 device to transmit its outbound STS-3/STM-1 data via the Transmit STS-3/STM-1 PECL Interface block. As a consequence, the user can configure the XRT94L33 device to align its transmission of STS-3/STM-1 frames (via the Transmit STS-3/STM-1 PECL Interface) to the 8kHz signal that is being applied to the “TxSBFP_in” input pin. 57 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 24: STS-3/STM-1 Telecom Bus Control Register – Byte 2 (Address Location= 0x0135) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 HRSYNC_Delay[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 HRSYNC_Delay[7:0] R/W DESCRIPTION STS-3 Telecom Bus – Sync Delay – Lower Byte: The Transmit STS-3 TOH Processor block will generate the outbound STS-3/STM-1 frame in alignment with the 8KHz pulse that is being applied to the “TxSBFP_in” input pin. The user is expected to apply a pulse (with the period of a 19.44MHz clock signal) at a rate of 8kHz to the “TxSBFP_in input (pin number G4). The Transmit STS-3/STM-1 Telecom Bus will align its transmission of the very first byte of a new STS-3/STM-1 frame, with a pulse at this input pin. These READ/WRITE bit-fields (along with that within the “Interface Control Register – Byte 3) permit the user to specify the amount of delay (in terms of 19.44MHz clock periods) that will exist between the rising edge of “TxSBFP_in” and the transmission of the very first byte, within a given STS-3 via the Transmit STS-3/STM-1 Telecom Bus. Setting this register to “0x0000” configures each of the Transmit STS3/STM-1 Telecom Bus Interfaces to transmit the very first byte of a new STS-3 frame, upon detection of the rising edge of the “TxSBFP_in”. Setting this register to “0x0001” configures each of the Transmit STS-3 Telecom Bus Interfaces to delay its transmission of the very first byte of a new STS-3 frame, by one 19.44MHz clock period, and so on. Note: This register is also active if the user has configured the XRT94L33 device to transmit its outbound STS-3/STM-1 data via the Transmit STS-3/STM-1 PECL Interface block. As a consequence, the user can configure the XRT94L33 device to align its transmission of STS-3/STM-1 frames (via the Transmit STS-3/STM-1 PECL Interface) to the 8KHz signal that is being applied to the TxSBFP_in input pin. 58 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 25: STS-3/STM-1 Telecom Bus Control Register – Byte 0 (Address Location= 0x0137) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STS-3/STM1 Telecom Bus ON Telecom Bus Disable Is STS-3 Payload Telecom Bus Parity Type Telecom Bus J1 Only Telecom Bus Parity Odd Telecom Bus Parity Disable STS-3 Rephase OFF R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE Bit 7 STS-3/STM-1 Telecom Bus ON R/W DESCRIPTION STS-3/STM-1 Telecom Bus Interface Enable: This READ/WRITE permits the user to either enable or disable the STS3/STM-1 Telecom Bus Interface, as described below. 0 – Disables the STS-3/STM-1 Telecom Bus Interface is Disabled: STS-3/STM-1 data will “Clock/Data” Interface. output via “Interleave/De-Interleave” or 1 – Telecom Bus Interface is Enabled: In this selection, the STS-3/STM-1 Transmit and Receive Telecom Bus Interface will be enabled. Bit 6 Telecom Bus TriState R/W Telecom Bus Tri-state: This READ/WRITE bit-field permits the user to “tri-state” the Telecom Bus Interface. 0 – Telecom Bus Interface is NOT tri-stated. 1 – Telecom Bus Interface is tri-stated. Note: Bit 5 Is STS-3 Payload R/W This READ/WRITE bit-field is ignored if the STS-3/STM-1 Transmit and Receive STS-3 Telecom Bus Interface is disabled. Is STS-3 Payload: This READ/WRITE bit-field permits the user to configure STS-1 Telecom Bus Interface # 0 to support the STS-3 rate, as described below. 0 – Configures all three STS-1 Telecom Bus Interfaces to operate in the STS-1 Mode. 1 – Configures STS-1 Telecom Bus Interface # 0 to operate in the STS-3 Mode. In this configuration setting, only STS-1 Telecom Bus Interface # 0 will be active and will be operating at a rate of 19.44MHz. STS-1 Telecom Bus Interfaces # 1 and 2 will be disabled. Bit 4 Telecom Bus Parity Type R/W Telecom Bus Parity Type: This READ/WRITE bit-field permits the user to define the parameters, over which “Telecom Bus” parity will be computed. 0 – Parity is computed/verified over the STS-3/STM-1 Transmit and Receive Telecom Bus – data bus pins (e.g., TXA_D[7:0] and RXD_D[7:0]). If the user implements this selection, then the following will happen. a. The STS-3/STM-1 Transmit Telecom Bus Interface will compute and output parity (via the “TXA_DP” output pin) based upon and coincident with the data being output via the “TXA_D[7:0]” output pins. 59 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM b. Rev222...000...000 The STS-3/STM-1 Receive Telecom Bus Interface will compute and verify the parity data (which is input via the “RXD_DP” input pin) based upon the data which is being input (and latched) via the “RXD_D[7:0]” input pins. 1 – Parity is computed/verified over the STS-3/STM-1 Transmit and Receive Telecom Bus – data bus pins (e.g., TXA_D[7:0] and RXD_D[7:0]); the C1J1 and PL input/output pins. If the user implements this selection, then the following will happen. a. The STS-3/STM-1 Transmit Telecom Bus Interface will compute and output parity (via the “TXA_DP” output) based upon and coincident with (1) the data being output via the “TXA_D[7:0]” output pins, (2) the state of the “TXA_PL” output pin, and (3) the state of the “TXA_C1J1” output pin. b. The STS-3/STM-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the “RXD_DP” input pin) based upon (1) the data which is being input (and latched) via the “RXD_D[7:0]” input pins, (2) the state of the “RXD_PL” input pin, and (3) the state of the “RXD_C1J1” input pin. Note: Bit 3 Telecom Bus J1 Only R/W This bit-field is disabled if the STS-3/STM-1 Telecom Bus is disabled. The user can configure the STS-3/STM-1 Telecom Bus to compute with either even or odd parity, by writing the appropriate data into Bit 2 (Telecom Bus Parity – Odd), within this register. Telecom Bus – J1 Indicator Only: This READ/WRITE bit-field permits the user to configure how the STS3/STM-1 Transmit and Receive Telecom Bus interface handles the “TXA_C1J1” and RXD_C1J1” signals, as described below. 0 – C1 and J1 Bytes This selection configures the following. c. The STS-3/STM-1 Transmit Telecom Bus to pulse the “TXA_C1J1” output coincident to whenever the C1 and J1 bytes are being output via the “TXA_D[7:0]” output pins. d. The STS-3/STM-1 Receive Telecom Bus will expect the “RXD_C1J1” input to pulse “high” coincident to whenever the C1 and J1 bytes are being sampled via the “RXD_D[7:0]” input pins. 1 – J1 Bytes Only This selection configures the following. Bit 2 Telecom Bus Parity Odd R/W e. The STS-3/STM-1 Transmit Telecom Bus Interface to only pulse the “TXA_C1J1” output pin coincident to whenever the J1 byte is being output via the “TXA_D[7:0]” output pins. Note: The “TXA_C1J1” output pin will NOT be pulsed “high” whenever the C1 byte is being output via the “TXA_D[7:0]” output pins f. The STS-3/STM-1 Receive Telecom Bus Interface will expect the “RXD_C1J1” input to only pulse “high” coincident to whenever the J1 byte is being sampled via the “RXD_D[7:0]” input pins. Note: The “RXD_C1J1” input pin will NOT be pulsed “high” whenever the C1 byte is being input via the “RXD_D[7:0]” input pins Telecom Bus Parity – ODD Parity Select: This READ/WRITE bit-field permits the user to configure the STS-3/STM1 Telecom Bus Interface to do the following. 60 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S In the Transmit (Drop) Direction The STS-3/STM-1 Telecom Bus to compute either the EVEN or ODD parity over the contents of the (1) TxD_D[7:0] output pins, or (2) TxD_D[7:0] output pins, the states of the TxD_PL and TxD_C1J1 output pins (depending upon user setting for Bit 3). In the Receive (Add) Direction Receive STS-3/STM-1 Telecom Bus to compute and verify the EVEN or ODD parity over the contents of the (1) RxA_D[7:0] input pins, or (2) RxA_D[7:0] input pins, the states of the RxA_PL and RxA_C1J1 input pins (depending upon user setting for Bit 3). 0 – Configures Transmit (Drop) Telecom Bus to compute EVEN parity and configures the Receive (Add) Telecom Bus to verify EVEN parity. 1 – Configures Transmit (Drop) Telecom Bus to compute ODD parity and configures the Receive (Add) Telecom Bus to verify ODD parity. Bit 1 Telecom Bus Parity Disable R/W Telecom Bus Parity Disable: This READ/WRITE bit-field permits the user to either enable or disable parity calculation and placement via the “TxA_DP” output pin. This bit field also permits the user to enable or disable parity verification by the Receive Telecom Bus. 0 – Enables Parity Calculation (on the Transmit Telecom Bus) and Disables Parity Verification (on the Receive Telecom Bus. 1 – Disables Parity Calculation and Verification Bit 0 Rephase OFF Only R/W Telecom Bus – Rephase Disable: This READ/WRITE bit-field permits the user to configure the Receive STS-3/STM-1 Telecom Bus to internally compute the Pointer Bytes, based upon the data that it receives via the “RxD_D[7:0] input pins. Note: If the Receive STS-3/STM-1 Telecom Bus is being provided with pulses denoting the C1 and J1 bytes (via the “RxD_C1J1” input pin), then this feature is unnecessary. 1 – Disables Rephase 0 – Enables Rephase 61 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 26: Interface Control Register – Byte 2 – STS-1/STM-0 Telecom Bus Interface – Channel 2 (Address Location= 0x0139) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STS-1 Telecom Bus ON Channel 2 STS-1 Telecom Bus TriState Channel 2 Unused STS-1 Telecom Bus Parity Type Channel 2 STS-1 Telecom Bus J1 ONLY STS-1 Telecom Bus Parity Odd STS-1 Telecom Bus Parity Disable STS-1 REPHASE OFF R/W R/W R/O R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE Bit 7 STS-1 Telecom Bus ON – Channel 2 R/W DESCRIPTION STS-1 Telecom Bus ON – Channel 2: This READ/WRITE bit-field permits the user to either enable or disable the STS-1 Telecom Bus Interface associated with Channel 2. If this particular STS-1 Telecom Bus Interface is enabled, then all of the following events will occur. • The Transmit STS-1 Telecom Bus Interface (associated with Channel 2) will accept an STS-1 signal (in the Ingress Direction) and the XRT94L33 device will map this signal into an STS-3 signal. • The XRT94L33 device will de-map out the STS-1 signal (associated with Channel 2) and will output this STS-1 data-stream via the Receive STS-1 Telecom Bus Interface (associated with Channel 2). If the STS-1 Telecom Bus Interface associated with Channel 2 is disabled, then Channel 2 will support the mapping (de-mapping) of DS3, E3 or STS-1 data into (from) the STS-3 signal via the “LIU Interface”. 0 – Disables the STS-1 Telecom Bus Interface associated with Channel 2. In this mode, the LIU Interface (associated with Channel 2) will now be enabled. Depending upon user’s selection, the following functional blocks (within Channel 2) will now be enabled. If Channel 2 is configured to operate in the DS3/E3 Mode: • DS3/E3 Framer Block • DS3/E3 Mapper Block • DS3/E3 Jitter Attenuator/De-Sync Block If Channel 2 is configured to operate in the STS-1 Mode • Receive STS-1 TOH Processor Block • Receive STS-1 POH Processor Block • Transmit STS-1 POH Processor Block • Transmit STS-1 TOH Processor Block 1 – Enables the STS-1 Telecom Bus Interface, associated with Channel 2. In this mode, all DS3/E3 Framer block and STS-1 TOH/POH Processor block circuitry associated with Channel 2 will be disabled. Bit 6 STS-1 Telecom Bus Tri-State # 2 R/W STS-1 Telecom Bus Tri-state – Channel 2: This READ/WRITE bit-field permits the user to “tri-state” the Telecom Bus Interface associated with Channel 2 62 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Interface associated with Channel 2. 0 – Telecom Bus Interface is NOT tri-stated. 1 – Telecom Bus Interface is tri-stated. Note: Bit 5 Unused R/W Bit 4 STS-1 Telecom Bus Parity Type – Channel 2 R/W This READ/WRITE bit-field is ignored if the Transmit and Receive STS-1 Telecom Bus Interface (associated with Channel 2) is disabled. STS-1 Telecom Bus Parity Type – Channel 2: This READ/WRITE bit-field permits the user to define the parameters, over which “Telecom Bus” parity will be computed. 0 – Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus – data bus pins (e.g., STS1TXA_D_2[7:0] and STS1RXD_D_2[7:0]). If the user implements this selection, then the following will happen. g. The Receive STS-1 Telecom Bus Interface will compute and output parity (via the “STS1RXD_DP_2” output pin) based upon and coincident with the data being output via the “STS1RXD_2_D[7:0]” output pins. h. The Transmit STS-1 Telecom Bus Interface will compute and verify the parity data (which is input via the “STS1TXA_DP_2” input pin) based upon the data which is being input (and latched) via the “STS1TXA_2_D[7:0]” input pins. 1 – Parity is computed/verified over the Transmit and Receive STS-1 Telecom Bus – data bus pins (e.g., STS1TXA_2_D[7:0] and STS1RXD_2_D[7:0]); the STS1TXA_C1J1_2, STS1RXD_C1J1_2, STS1TXA_PL_2 and STS1RXD_PL_2 input/output pins. If the user implements this selection, then the following will happen. a. The Receive STS-1 Telecom Bus Interface will compute and output parity (via the “RXD_DP_2” output) based upon and coincident with (1) the data being output via the “STS1RXD_2_D[7:0]” output pins, (2) the state of the “STS1RXD_PL_2” output pin, and (3) the state of the “STS1RXD_C1J1_2” output pin. b. The Transmit STS-1 Telecom Bus Interface will compute and verify the parity data (which is input via the “STS1TXA_DP_2” input pin) based upon (1) the data which is being input (and latched) via the “STS1TXA_2_D[7:0]” input pins, (2) the state of the “STS1TXA_PL_2” input pin, and (3) the state of the “STS1TXA_C1J1_2” input pin. Note: Bit 3 STS-1 Telecom Bus J1 ONLY R/W This bit-field is disabled if the STS-1 Telecom Bus is disabled. The user can configure the STS-1 Telecom Bus to compute with either even or odd parity, by writing the appropriate data into Bit 2 (Telecom Bus Parity – Odd), within this register. STS-1 Telecom Bus Interface – J1 Indicator Only – Channel 2: This READ/WRITE bit-field permits the user to configure how the Transmit and Receive STS-1 Telecom Bus interface handles the “STS1TXA_C1J1_2” and STS1RXD_C1J1_2” signals, as described below. 0 – C1 and J1 Bytes This selection configures the following. a. The Receive STS-1 Telecom Bus Interface to pulse the 63 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 “STS1RXD_C1J1_2” output coincident to whenever the C1 and J1 bytes are being output via the “STS1RXD_2_D[7:0]” output pins. b. The Transmit STS-1 Telecom Bus Interface will expect the “STS1TXA_C1J1_2” input to be pulsed “high” coincident to whenever the C1 and J1 bytes are being sampled via the “STS1TXA_2_D[7:0]” input pins. 1 – J1 Bytes Only This selection configures the following. a. The Receive STS-1 Telecom Bus Interface to only pulse the “STS1RXD_C1J1_2” output pin coincident to whenever the J1 byte is being output via the “STSRXD_2_D[7:0]” output pins. Note: In this setting, the “STS1RXD_C1J1_2” output pin will NOT be pulsed “high” whenever the C1 byte is being output via the “STS1RXD_D_2[7:0]” output pins b. The Transmit STS-1 Telecom Bus Interface will expect the “STS1TXA_C1J1_2” input to only be pulsed “high” coincident to whenever the J1 byte is being sampled via the “STS1TXA_2_D[7:0]” input pins. Note: Bit 2 STS-1 Telecom Bus Parity Odd R/W In this setting, the “STS1TXA_C1J1_2” input pin will NOT be pulsed “high” whenever the C1 byte is being input via the “STS1TXA_2_D[7:0]” input pins STS-1 Telecom Bus Interface Parity – ODD Parity Select – Channel 2: This READ/WRITE bit-field permits the user to configure the STS-1 Telecom Bus Interface, associated with Channel 2 to do the following. In the Receive (Drop) Direction Receive STS-1 Telecom Bus Interface will compute either the EVEN or ODD parity over the contents of the (1) STS1RxD_2_D[7:0] output pins, or (2) STS1RxD_2_D[7:0] output pins, the states of the STS1RxD_PL_2 and STS1RxD_C1J1_2 output pins (depending upon user setting for Bit 3). In the Transmit (Add) Direction Transmit STS-1 Telecom Bus Interface will compute and verify the EVEN or ODD parity over the contents of the (1) STS1TxA_2_D[7:0] input pins, or (2) STS1TxA_2_D[7:0] input pins, the states of the STS1TxA_PL_2 and STS1TxA_C1J1_2 input pins (depending upon user setting for Bit 3). 0 – Configures Receive STS-1 (Drop) Telecom Bus Interface to compute EVEN parity and configures the Transmit STS-1 (Add) Telecom Bus Interface to verify EVEN parity. 1 – Configures Receive STS-1 (Drop) Telecom Bus Interface to compute ODD parity and configures the Transmit STS-1 (Add) Telecom Bus Interface to verify ODD parity. Bit 1 STS-1 Telecom Bus Parity Disable R/W STS-1 Telecom Bus Interface - Parity Disable – Channel 2: This READ/WRITE bit-field permits the user to either enable or disable parity calculation and placement via the “STSRxD_DP_2” output pin. Further, this bit-field also permits the user to enable or disable parity verification via the “STS1TxA_DP_2” input pin by the Transmit Telecom Bus. 1 – Disables Parity Calculation (on the Receive Telecom Bus) and Disables Parity Verification (on the Transmit Telecom Bus. 0 – Enables Parity Calculation and Verification Bit 0 STS-1 REPHASE OFF R/W STS-1 Telecom Bus Interface – Rephase Disable – Channel 2: This READ/WRITE bit-field permits the user to configure the Receive STS-1 64 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 OFF Telecom Bus to internally compute the Pointer Bytes, based upon the data that it receives via the “RxD_D[7:0] input pins. Note: If the Receive STS-1 Telecom Bus is being provided with pulses denoting the C1 and J1 bytes (via the “RxD_C1J1” input pin), then this feature is unnecessary. 1 – Disable Rephase If the user implements this selection, then the Transmit STS-1 Telecom Bus Interface (associated with Channel 2) will rely on the signaling that is provided via the “STS1TXA_C1J1_2” and “STS1TXA_PL_2” input pins, in order to determine the location of the STS-1 SPE (within the Ingress Direction STS-1 signal) with respect to the STS-1 frame boundaries. 0 – Enable Rephase If the user implements this selection, then the Transmti STS-1 Telecom Bus Interface (associated with Channel 2) will NOT rely on the signaling that is provided via the “STS1TXA_C1J1_2” and the “STS1TXA_PL_2” input pins in order to determine the location of the STS-1 SPE (within the Ingress Direction STS-1 signal) with respectg to the STS-1 frame boundaries. In this case the Transmit STS-1 TOH and POH Processor blocks (will be enabled) and will take on the role of locating the STS-1 SPE within the Ingress Direction STS-1 signal. 65 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 27: Interface Control Register – Byte 1 – STS-1/STM-0 Telecom Bus Interface - Channel 1 (Address Location= 0x013A) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STS-1 Telecom Bus ON Channel 1 STS-1 Telecom Bus TriState Channel 1 Unused STS-1 Telecom Bus Parity Type Channel 1 STS-1 Telecom Bus J1 ONLY STS-1 Telecom Bus Parity ODD STS-1 Telecom Bus Parity Disable STS-1 REPHASE OFF R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE Bit 7 STS-1 Telecom Bus ON - Channel 1 R/W DESCRIPTION STS-1 Telecom Bus ON – Channel 1: This READ/WRITE bit-field permits the user to either enable or disable the STS-1 Telecom Bus Interface associated with Channel 1. If this particular STS-1 Telecom Bus Interface is enabled, then all of the following events will occur. • The Transmit STS-1 Telecom Bus Interface (associated with Channel 1) will accept an STS-1 signal (in the Ingress Direction) and the XRT94L33 device will map this signal into an STS-3 signal. • The XRT94L33 device will de-map out the STS-1 signal (associated with Channel 1) and will output this STS-1 data-stream via the Receive STS-1 Telecom Bus Interface (associated with Channel 1). If the STS-1 Telecom Bus Interface associated with Channel 1 is disabled, then Channel 1 will support the mapping (de-mapping) of DS3, E3 or STS-1 data into (from) the STS-3 signal via the “LIU Interface”. 0 – Disables the STS-1 Telecom Bus Interface associated with Channel 1. In this mode, the LIU Interface (associated with Channel 1) will now be enabled. Depending upon user’s selection, the following functional blocks (within Channel 1) will now be enabled. If Channel 1 is configured to operate in the DS3/E3 Mode: • DS3/E3 Framer Block • DS3/E3 Mapper Block • DS3/E3 Jitter Attenuator/De-Sync Block If Channel 1 is configured to operate in the STS-1 Mode: • Receive STS-1 TOH Processor Block • Receive STS-1 POH Processor Block • Transmit STS-1 POH Processor Block • Transmit STS-1 TOH Processor Block 1 – Enabes the STS-1 Telecom Bus Interface, associated with Channel 1. In this mode, all DS3/E3 Framer block and STS-1 TOH/POH Processor block circuitry associated with Channel 1 will be disabled. 66 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Bit 6 STS-1 Telecom Bus Tri-State # 1 R/W STS-1 Telecom Bus Tri-state – Channel 1: This READ/WRITE bit-field permits the user to “tri-state” the Telecom Bus Interface. 0 – Telecom Bus Interface is NOT tri-stated. 1 – Telecom Bus Interface is tri-stated. Note: Bit 5 Unused R/O Bit 4 STS-1 Telecom Bus Parity Type # 1 R/W This READ/WRITE bit-field is ignored if the STS-1 Transmit and Receive Telecom Bus Interface is disabled. STS-1 Telecom Bus Parity Type – Channel 1: This READ/WRITE bit-field permits the user to define the parameters, over which “Telecom Bus” parity will be computed. 0 – Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus – data bus pins (e.g., STS1TXA_D_1[7:0] and STS1RXD_D_1[7:0]). If the user implements this selection, then the following will happen. a. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the “STS1RXD_DP_1” output pin) based upon and coincident with the data being output via the “STS1RXD_D_1[7:0]” output pins. b. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the “STS1TXA_DP_1” input pin) based upon the data which is being input (and latched) via the “STS1TXA_D_1[7:0]” input pins. 1 – Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus – data bus pins (e.g., STS1TXA_D_1[7:0] and STS1RXD_D_1[7:0]); the STS1TXA_C1J1_1, STS1RXD_C1J1_1, STS1TXA_PL_1 and STS1RXD_PL_1 input/output pins. If the user implements this selection, then the following will happen. Bit 3 STS-1 Telecom Bus J1 ONLY R/W a. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the “STS1RXD_DP_1” output) based upon and coincident with (1) the data being output via the “STS1RXD_D_1[7:0]” output pins, (2) the state of the “STS1RXD_PL_1” output pin, and (3) the state of the “STS1RXD_C1J1_1” output pin. b. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the “STS1TXA_DP_1” input pin) based upon (1) the data which is being input (and latched) via the “STS1TXA_D_1[7:0]” input pins, (2) the state of the “STS1TXA_PL_1” input pin, and (3) the state of the “STS1TXA_C1J1_1” input pin. Note: This bit-field is disabled if the STS-1 Telecom Bus is disabled. The user can configure the STS-1 Telecom Bus to compute/verify with either even or odd parity, by writing the appropriate data into Bit 2 (Telecom Bus Parity – Odd), within this register. Telecom Bus – J1 Indicator Only – Channel 1: This READ/WRITE bit-field permits the user to configure how the STS-1 Transmit and Receive Telecom Bus interface handles the “STS1TXA_C1J1_1” and STS1RXD_C1J1_1” signals, as described below. 0 – C1 and J1 Bytes This selection configures the following. 67 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 a. The STS-1 Receive Telecom Bus to pulse the “STS1RXD_C1J1_1” output coincident to whenever the C1 and J1 bytes are being output via the “STS1RXD_D_1[7:0]” output pins. b. The STS-1 Transmit Telecom Bus will expect the “STS1TXA_C1J1_1” input to pulse “high” coincident to whenever the C1 and J1 bytes are being sampled via the “STS1TXA_D_1[7:0]” input pins. 1 – J1 Bytes Only This selection configures the following. Bit 2 STS-1 Telecom Bus Parity Odd R/W i. The STS-1 Receive Telecom Bus Interface to only pulse the “STS1RXD_C1J1_1” output pin coincident to whenever the J1 byte is being output via the “STS1RXD_D_1[7:0]” output pins. Note: The “STS1RXD_C1J1_1” output pin will NOT be pulsed “high” whenever the C1 byte is being output via the “STS1RXD_D_1[7:0]” output pins). j. The STS-1 Transmit Telecom Bus Interface will expect the “STS1TXA_C1J1_1” input to only pulse “high” coincident to whenever the J1 byte is being sampled via the “STS1TXA_D_1[7:0]” input pins. Note: The “STS1TXA_C1J1_1” input pin will NOT be pulsed “high” whenever the C1 byte is being input via the “STS1TXA_D_1[7:0]” input pins). Telecom Bus Parity – ODD Parity Select – Channel 1: This READ/WRITE bit-field permits the user to configure the STS-1 Telecom Bus Interface, associated with Channel 1 to do the following. In the Receive (Drop) Direction Receive STS-1 Telecom Bus to compute either the EVEN or ODD parity over the contents of the (1) STS1RxD_D_1[7:0] output pins, or (2) STS1RxD_D_1[7:0] output pins, the states of the STS1RxD_PL_1 and “STS1RxD_C1J1_1 output pins (depending upon user setting for Bit 3). In the Transmit (Add) Direction Transmit STS-1 Telecom Bus to compute and verify the EVEN or ODD parity over the contents of the (1) STS1TxA_D_1[7:0] input pins, or (2) STS1TxA_D_1[7:0] input pins, the states of the STS1TxA_PL_1 and STS1TxA_C1J1_1 input pins (depending upon user setting for Bit 3).0 – Configures Receive (Drop) Telecom Bus to compute EVEN parity and configures the Transmit (Add) Telecom Bus to verify EVEN parity1 – Configures Receive (Drop) Telecom Bus to compute ODD parity and configures the Transmit (Add) Telecom Bus to verify ODD parity. Bit 1 STS-1 Telecom Bus Parity Disable R/W STS-1 Telecom Bus Parity Disable – Channel 1: This READ/WRITE bit-field permits the user to either enable or disable parity calculation and placement via the “STSRxD_DP_1” output pin. Further, this bit field also permits the user to enable or disable parity verification via the “STS1TxA_DP_1” input pin by the Transmit Telecom Bus.1 – Disables Parity Calculation (on the Receive Telecom Bus) and Disables Parity Verification (on the Transmit Telecom Bus. 0 – Enables Parity Calculation and Verification Bit 0 STS-1 REPHASE OFF R/W STS-1 Telecom Bus – Rephase Disable – Channel 1: This READ/WRITE bit-field permits the user to configure the Receive STS-1 Telecom Bus to internally compute the Pointer Bytes, based upon the data that it receives via the “RxD_D[7:0] input pins.If the Receive STS-1 Telecom Bus is being provided with pulses denoting the C1 and J1 bytes 68 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S (via the “RxD_C1J1” input pin), then this feature is unnecessary.1 – Disables Rephase 0 – Enables Rephase 69 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 28: Interface Control Register – Byte 0 – STS-1/STM-0 Telecom Bus 0 (Address Location= 0x013B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STS-1 Telecom Bus ON #0 STS-1 Telecom Bus TriState # 0 STS-3c REPHASE OFF STS-1 Telecom Bus Parity Type # 0 STS-1 Telecom Bus J1 ONLY STS-1 Telecom Bus Parity Odd STS-1 Telecom Bus Parity Disable STS-1 REPHASE OFF R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE Bit 7 STS-1 Telecom Bus ON # 0 R/W DESCRIPTION STS-1 Telecom Bus ON – Channel 0: This READ/WRITE bit-field permits the user to either enable or disable the Telecom Bus associated with STS-1 Telecom Bus # 0. If the STS-1 Telecom Bus is enabled, then an STS-1 signal will be mapped into (demapped from) the STS-3 signal. If STS-1 Telecom Bus Interface – Channel 3 is disabled, then Channel 0 will support the mapping of DS3, E3 or STS-1 into the STS-3 signal. 0 – STS-1 Telecom Bus # 0 is disabled. In this mode, DS3/E3/STS-1 Channel 0 will now be enabled. Depending upon user’s selection, the following functional blocks (within Channel 0) will now be enabled. If DS3/E3 Framing is supported • DS3/E3 Framer Block • DS3/E3 Mapper Block • DS3/E3 Jitter Attenuator/De-Sync Block If STS-1 Framing is supported • Receive STS-1 TOH Processor Block • Receive STS-1 POH Processor Block • Transmit STS-1 POH Processor Block • Transmit STS-1 TOH Processor Block 1 – STS-1 Telecom Bus # 0 is enabled. In this mode, all DS3/E3 Framer block and STS-1 circuitry associated with Channel 0 will be disabled. Bit 6 STS-1 Telecom Bus Tri-State # 0 R/W STS-1 Telecom Bus Tri-state – Channel 0: This READ/WRITE bit-field permits the user to “tri-state” the Telecom Bus Interface. 0 – Telecom Bus Interface is NOT tri-stated. 1 – Telecom Bus Interface is tri-stated. Note: Bit 5 STS-3c REPHASE OFF R/O This READ/WRITE bit-field is ignored if the STS-1 Transmit and Receive Telecom Bus Interface is disabled. STS-3c While Rephase Off: This READ/WRITE bit-field permits the user to configure the STS-1 Telecom Bus # 0 to process STS-3c data while the “Rephase” feature is disabled. If 70 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 the user configures the STS-1 Telecom Bus Interface to process STS-3c data then the following functional blocks (within the XRT94L33 device) will now become active. • The Transmit STS-3c POH Processor block • The Receive STS-3c POH Processor block 0 – Configures STS-1 Telecom Bus # 0 to process STS-3 data. 1 – Configures STS-1 Telecom Bus # 0 to process STS-3c data. Note: Bit 4 STS-1 Telecom Bus Parity Type # 0 R/W This bit-field is only active if STS-1 Telecom Bus Interface # 0 has been configured to support “STS-3” Operation. This bit-field ignored if STS-1 Telecom Bus Interface # 0 has been configured to operate in the STS-1 Mode. STS-1 Telecom Bus Parity Type – Channel 0: This READ/WRITE bit-field permits the user to define the parameters, over which “Telecom Bus” parity will be computed. 0 – Parity is computed/verified over the Transmit and Receive STS-1 Telecom Bus – data bus pins (e.g., STS1TXA_D_0[7:0] and STS1RXD_D_0[7:0]). If the user implements this selection, then the following will happen. a. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the “STS1RXD_DP_0” output pin) based upon and coincident with the data being output via the “STS1RXD_D_0[7:0]” output pins. b. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the “STS1TXA_DP_0” input pin) based upon the data which is being input (and latched) via the “STS1TXA_D_0[7:0]” input pins. 1 – Parity is computed/verified over the STS-1 Transmit and Receive Telecom Bus – data bus pins (e.g., STS1TXA_D_0[7:0] and STS1RXD_D_0[7:0]); the STS1TXA_C1J1_0, STS1RXD_C1J1_0, STS1TXA_PL_0 and STS1RXD_PL_0 input/output pins. If the user implements this selection, then the following will happen. Bit 3 STS-1 Telecom Bus J1 ONLY R/W a. The STS-1 Receive Telecom Bus Interface will compute and output parity (via the “STS1RXD_DP_0” output) based upon and coincident with (1) the data being output via the “STS1RXD_D_0[7:0]” output pins, (2) the state of the “STS1RXD_PL_0” output pin, and (3) the state of the “STS1RXD_C1J1_0” output pin. b. The STS-1 Transmit Telecom Bus Interface will compute and verify the parity data (which is input via the “STS1TXA_DP_0” input pin) based upon (1) the data which is being input (and latched) via the “STS1TXA_D_0[7:0]” input pins, (2) the state of the “STS1TXA_PL_0” input pin, and (3) the state of the “STS1TXA_C1J1_0” input pin. Note: This bit-field is disabled if the STS-1 Telecom Bus is disabled. The user can configure the STS-1 Telecom Bus to compute/verify with either even or odd parity, by writing the appropriate data into Bit 2 (Telecom Bus Parity – Odd), within this register. Telecom Bus – J1 Indicator Only – Channel 0: This READ/WRITE bit-field permits the user to configure how the STS-1 Transmit and Receive Telecom Bus interface handles the “STS1TXA C1J1 0” and STS1RXD C1J1 0” signals as described below 71 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 “STS1TXA_C1J1_0” and STS1RXD_C1J1_0” signals, as described below. 0 – C1 and J1 Bytes This selection configures the following. a. The STS-1 Receive Telecom Bus to pulse the “STS1RXD_C1J1_0” output coincident to whenever the C1 and J1 bytes are being output via the “STS1RXD_D_0[7:0]” output pins. b. The STS-1 Transmit Telecom Bus will expect the “STS1TXA_C1J1_0” input to pulse “high” coincident to whenever the C1 and J1 bytes are being sampled via the “STS1TXA_D_0[7:0]” input pins. 1 – J1 Bytes Only This selection configures the following. Bit 2 STS-1 Telecom Bus Parity Odd R/W k. The STS-1 Receive Telecom Bus Interface to only pulse the “STS1RXD_C1J1_0” output pin coincident to whenever the J1 byte is being output via the “STS1RXD_D_0[7:0]” output pins. Note: The “STS1RXD_C1J1_0” output pin will NOT be pulsed “high” whenever the C1 byte is being output via the “STS1RXD_D_0[7:0]” output pins l. The STS-1 Transmit Telecom Bus Interface will expect the “STS1TXA_C1J1_0” input to only pulse “high” coincident to whenever the J1 byte is being sampled via the “STS1TXA_D_0[7:0]” input pins. Note: The “STS1TXA_C1J1_0” input pin will NOT be pulsed “high” whenever the C1 byte is being input via the “STS1TXA_D_0[7:0]” input pins Telecom Bus Parity – ODD Parity Select – Channel 0: This READ/WRITE bit-field permits the user to configure the STS-1 Telecom Bus Interface, associated with Channel 0 to do the following. In the Receive (Drop) Direction Receive STS-1 Telecom Bus to compute either the EVEN or ODD parity over the contents of the (1) STS1RxD_D_0[7:0] output pins, or (2) STS1RxD_D_0[7:0] output pins, the states of the STS1RxD_PL_0 and “STS1RxD_C1J1_0 output pins (depending upon user setting for Bit 3). In the Transmit (Add) Direction Transmit STS-1 Telecom Bus to compute and verify the EVEN or ODD parity over the contents of the (1) STS1TxA_D_0[7:0] input pins, or (2) STS1TxA_D_0[7:0] input pins, the states of the STS1TxA_PL_0 and STS1TxA_C1J1_0 input pins (depending upon user setting for Bit 3). 0 – Configures Receive (Drop) Telecom Bus to compute EVEN parity and configures the Transmit (Add) Telecom Bus to verify EVEN parity 1 – Configures Receive (Drop) Telecom Bus to compute ODD parity and configures the Transmit (Add) Telecom Bus to verify ODD parity. Bit 1 STS-1 Telecom Bus Parity Disable R/W STS-1 Telecom Bus Parity Disable – Channel 0: This READ/WRITE bit-field permits the user to either enable or disable parity calculation and placement via the “STSRxD_DP_0” output pin. Further, this bit field also permits the user to enable or disable parity verification via the “STS1TxA_DP_0” input pin by the Transmit Telecom Bus. 1 – Disables Parity Calculation (on the Receive Telecom Bus) and Disables Parity Verification (on the Transmit Telecom Bus. 72 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0 – Enables Parity Calculation and Verification Bit 0 STS-1 REPHASE OFF R/W STS-1 Telecom Bus – Rephase Disable – Channel 0: This READ/WRITE bit-field permits the user to configure the Transmit STS1 Telecom Bus (associated with Channel 0) to internally compute the Pointer Bytes, based upon the data that it receives via the “STS1TxA_D[7:0] input pins. Note: If the Transmit STS-1 Telecom Bus is being provided with pulses denoting the C1 and J1 bytes (via the “STS1TxA_C1J1” input pin), then this feature is unnecessary. 1 – Disables Rephase 0 – Enables Rephase 73 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 29: Interface Control Register – STS-1/STM-0 Telecom Bus Interrupt Enable/Status Register (Address Location= 0x013C) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused STS-1 Telecom Bus # 2 RxParity Error Interrupt Status TB1 RxParity Error Interrupt Status TB0 RxParity Error Interrupt Status Unused TB2 RxParity Error Interrupt Enable TB1 RxParity Error Interrupt Enable TB0 RxParity Error Interrupt Enable R/O RUR RUR RUR R/O R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Telecom Bus # 2 Receive Parity Error Interrupt Status RUR DESCRIPTION STS-1 Telecom Bus # 2 – Receive Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or “STS-1 Telecom Bus – Channel 2” has declared a “Receive Parity Error” Interrupt since the last read of this register. 0 – The “Receive Parity Error” Interrupt has not occurred since the last read of this register. 1 – The “Receive Parity Error” Interrupt has occurred since the last read of this register. Note: 5 Telecom Bus # 1 Receive Parity Error Interrupt Status RUR This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has been enabled. STS-1 Telecom Bus # 1 – Receive Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or “STS-1 Telecom Bus – Channel 1” has declared a “Receive Parity Error” Interrupt since the last read of this register. 0 – The “Receive Parity Error” Interrupt has not occurred since the last read of this register. 1 – The “Receive Parity Error” Interrupt has occurred since the last read of this register. Note: 4 Telecom Bus # 0 Receive Parity Error Interrupt Status RUR This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has been enabled. STS-1 Telecom Bus # 0 – Receive Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or “STS-1 Telecom Bus – Channel 3” has declared a “Receive Parity Error” Interrupt since the last read of this register. 0 – The “Receive Parity Error” Interrupt has not occurred since the last read of this register. 1 – The “Receive Parity Error” Interrupt has occurred since the last read of this register. Note: 3 Unused This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has been enabled. R/O 74 XRT94L33 Rev222...000...000 2 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Telecom Bus # 2 – Receive Parity Error Interrupt Enable R/W STS-1 Telecom Bus # 2 – Receive Parity Error Interrupt Enable This READ/WRITE bit-field permits the user to either enable or disable the “Receive Parity Error” Interrupt for STS-1 Telecom Bus – Channel 2. If the user enables this interrupt, then STS-1 Telecom Bus – Channel 2 will generate an interrupt anytime the “Receive STS-1 Telecom Bus” detects a parity error within the incoming STS-1 data. 0 – Disables the “Receive Parity Error” Interrupt. 1 – Enables the “Receive Parity Error” Interrupt. Note: 1 Telecom Bus # 1 – Receive Parity Error Interrupt Enable R/W This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has been enabled. STS-1 Telecom Bus # 1 – Receive Parity Error Interrupt Enable This READ/WRITE bit-field permits the user to either enable or disable the “Receive Parity Error” Interrupt for STS-1Telecom Bus – Channel 1. If the user enables this interrupt, then STS-1 Telecom Bus – Channel 1 will generate an interrupt anytime the “Receive STS-1 Telecom Bus” detects a parity error within the incoming STS-1 data. 0 – Disables the “Receive Parity Error” Interrupt. 1 – Enables the “Receive Parity Error” Interrupt. Note: 0 Telecom Bus # 0 – Receive Parity Error Interrupt Enable R/W This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has been enabled. STS-1 Telecom Bus # 0 – Receive Parity Error Interrupt Enable This READ/WRITE bit-field permits the user to either enable or disable the “Receive Parity Error” Interrupt for STS-1 Telecom Bus – Channel 0. If the user enables this interrupt, then STS-1 Telecom Bus – Channel 0 will generate an interrupt anytime the “Receive STS-1 Telecom Bus” detects a parity error within the incoming STS-1 data. 0 – Disables the “Receive Parity Error” Interrupt. 1 – Enables the “Receive Parity Error” Interrupt. Note: This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has been enabled. 75 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 30: Interface Control Register – STS-1/STM-0 Telecom Bus FIFO Status Register (Address Location = 0x013D) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Unused STS-1 Telecom Bus Tx Overrun Bus 2 STS-1 Telecom Bus Tx Underrun Bus 2 STS-1 Telecom Bus Tx Overrun Bus 1 STS-1 Telecom Bus Tx Underrun Bus 1 STS-1 Telecom Bus Tx Overrun Bus 0 STS-1 Telecom Bus Tx Underrun Bus 0 R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Unused R/O 5 STS-1 Telecom Bus – TxFIFO Overrun # 2 R/O DESCRIPTION STS-1 Telecom Bus – Transmit FIFO Overrun Indicator – Channel 2: This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus – Channel 2” is currently declaring a “Transmit FIFO Overrun” condition. 0 – Indicates that “STS-1 Telecom Bus – Channel 2” is NOT declaring a “Transmit FIFO Overrun” condition. 1 – Indicates that “STS-1 Telecom Bus – Channel 2” is currently declaring a “Transmit FIFO Overrun” condition. Note: 4 STS-1 Telecom Bus – TxFIFO Underrun # 2 R/O This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has been enabled. STS-1 Telecom Bus – Transmit FIFO Underrun Indicator – Channel 2: This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus – Channel 3” is currently declaring a “Transmit FIFO Underrun” condition. 0 – Indicates that “STS-1 Telecom Bus – Channel 2” is NOT declaring a “Transmit FIFO Underrun” condition. 1 – Indicates that “STS-1 Telecom Bus – Channel 2” is currently declaring a “Transmit FIFO Underrun” condition. Note: 3 STS-1 Telecom Bus – TxFIFO Overrun # 1 R/O This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has been enabled. STS-1 Telecom Bus – Transmit FIFO Overrun Indicator – Channel 1: This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus – Channel 1” is currently declaring a “Transmit FIFO Overrun” condition. 0 – Indicates that “STS-1 Telecom Bus – Channel 1” is NOT declaring a “Transmit FIFO Overrun” condition. 1 – Indicates that “STS-1 Telecom Bus – Channel 1” is currently declaring a “Transmit FIFO Overrun” condition. Note: 2 STS-1 Telecom Bus – TxFIFO Underrun # 1 R/O This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has been enabled. STS-1 Telecom Bus – Transmit FIFO Underrun Indicator – Channel 1: This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus – Channel 1” is currently declaring a “Transmit FIFO Underrun” condition. 0 – Indicates that “STS-1 Telecom Bus – Channel 1” is NOT declaring a 76 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 “Transmit FIFO Underrun” condition. 1 – Indicates that “STS-1 Telecom Bus – Channel 1” is currently declaring a “Transmit FIFO Underrun” condition. Note: 1 STS-1 Telecom Bus – TxFIFO Overrun # 0 R/O This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has been enabled. STS-1 Telecom Bus – Transmit FIFO Overrun Indicator – Channel 0: This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus – Channel 0” is currently declaring a “Transmit FIFO Overrun” condition. 0 – Indicates that “STS-1 Telecom Bus – Channel 0” is NOT declaring a “Transmit FIFO Overrun” condition. 1 – Indicates that “STS-1 Telecom Bus – Channel 0” is currently declaring a “Transmit FIFO Overrun” condition. Note: 0 STS-1 Telecom Bus – TxFIFO Underrun # 0 R/O This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has been enabled. STS-1 Telecom Bus – Transmit FIFO Underrun Indicator – Channel 0: This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus – Channel 0” is currently declaring a “Transmit FIFO Underrun” condition. 0 – Indicates that “STS-1 Telecom Bus – Channel 0” is NOT declaring a “Transmit FIFO Underrun” condition. 1 – Indicates that “STS-1 Telecom Bus – Channel 0” is currently declaring a “Transmit FIFO Underrun” condition. Note: This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has been enabled. 77 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 31: Interface Control Register – STS-1/STM-0 Telecom Bus FIFO Interrupt Status Register (Address Location= 0x013E) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Unused STS-1 Telecom Bus # 2 Tx Overrun Interrupt Status STS-1 Telecom Bus # 2 Tx Underrun Interrupt Status STS-1 Telecom Bus # 1 Tx Overrun Interrupt Status STS-1 Telecom Bus # 1 Tx Underrun Interrupt Status STS-1 Telecom Bus # 0 Tx Overrun Interrupt Status STS-1 Telecom Bus # 0 Tx Underrun Interrupt Status R/O R/O RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Unused R/O 5 STS-1 Telecom Bus # 2 – TxFIFO Overrun Interrupt Status RUR DESCRIPTION STS-1 Telecom Bus – TxFIFO Overrun Interrupt Status – Channel 2: This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom Bus – Channel 2” has declared a “TxFIFO Overrun” Interrupt since the last read of this register. 0 – Indicates that “STS-1 Telecom Bus – Channel 2” has NOT declared a “TxFIFO Overrun” Interrupt since the last read of this register. 1 – Indicates that “STS-1 Telecom Bus – Channel 2” has declared a “TxFIFO Overrun” Interrupt since the last read of this register. Note: 4 STS-1 Telecom Bus # 2 – TxFIFO Underrun Interrupt Status RUR This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has been enabled. STS-1 Telecom Bus – TxFIFO Underrun Interrupt Status – Channel 2: This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom Bus – Channel 2” has declared a “TxFIFO Underrun” Interrupt since the last read of this register. 0 – Indicates that “STS-1 Telecom Bus – Channel 2” has NOT declared a “TxFIFO Underrun” Interrupt since the last read of this register. 1 – Indicates that “STS-1 Telecom Bus – Channel 2” has declared a “TxFIFO Overrun” Interrupt since the last read of this register. Note: 3 STS-1 Telecom Bus # 1 – TxFIFO Overrun Interrupt Status RUR This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has been enabled. STS-1 Telecom Bus – TxFIFO Overrun Interrupt Status – Channel 1: This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom Bus – Channel 1” has declared a “TxFIFO Overrun” Interrupt since the last read of this register. 0 – Indicates that “STS-1 Telecom Bus – Channel 1” has NOT declared a “TxFIFO Overrun” Interrupt since the last read of this register. 1 – Indicates that “STS-1 Telecom Bus – Channel 1” has declared a “TxFIFO Overrun” Interrupt since the last read of this register. Note: 2 STS-1 Telecom Bus # 1 – RUR This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has been enabled. STS-1 Telecom Bus – TxFIFO Underrun Interrupt Status – Channel 1: 78 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 TxFIFO Underrun Interrupt Status This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom Bus – Channel 1” has declared a “TxFIFO Underrun” Interrupt since the last read of this register. 0 – Indicates that “STS-1 Telecom Bus – Channel 1” has NOT declared a “TxFIFO Underrun” Interrupt since the last read of this register. 1 – Indicates that “STS-1 Telecom Bus – Channel 1” has declared a “TxFIFO Overrun” Interrupt since the last read of this register. Note: 1 STS-1 Telecom Bus # 0 – TxFIFO Overrun Interrupt Status RUR This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has been enabled. STS-1 Telecom Bus – TxFIFO Overrun Interrupt Status – Channel 0: This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom Bus – Channel 0” has declared a “TxFIFO Overrun” Interrupt since the last read of this register. 0 – Indicates that “STS-1 Telecom Bus – Channel 0” has NOT declared a “TxFIFO Overrun” Interrupt since the last read of this register. 1 – Indicates that “STS-1 Telecom Bus – Channel 0” has declared a “TxFIFO Overrun” Interrupt since the last read of this register. Note: 0 STS-1 Telecom Bus # 0 – TxFIFO Underrun Interrupt Status RUR This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has been enabled. STS-1 Telecom Bus – TxFIFO Underrun Interrupt Status – Channel 0: This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom Bus – Channel 0” has declared a “TxFIFO Underrun” Interrupt since the last read of this register. 0 – Indicates that “STS-1 Telecom Bus – Channel 0” has NOT declared a “TxFIFO Underrun” Interrupt since the last read of this register. 1 – Indicates that “STS-1 Telecom Bus – Channel 0” has declared a “TxFIFO Overrun” Interrupt since the last read of this register. Note: This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has been enabled. 79 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 32: Interface Control Register – STS-1/STM-0 Telecom Bus FIFO Interrupt Enable Register (Address Location= 0x013F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Unused STS-1 Telecom Bus # 2 Tx Overrun Interrupt Enable STS-1 Telecom Bus # 2 Tx Underrun Interrupt Enable STS-1 Telecom Bus # 1 Tx Overrun Interrupt Enable STS-1 Telecom Bus # 1 Tx Underrun Interrupt Enable STS-1 Telecom Bus # 0 Tx Overrun Interrupt Enable STS-1 Telecom Bus # 0 Tx Underrun Interrupt Enable R/O R/O R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Unused R/O 5 STS-1 Telecom Bus # 2 TxFIFO Overrun Interrupt Enable DESCRIPTION STS-1 Telecom Bus – TxFIFO Overrun Interrupt Enable – Channel 2: This READ/WRITE bit-field permits the user to either enable or disable the “TxFIFO Overrun” Interrupt, associated with STS-1 Telecom Bus – Channel 2. If the user enables this interrupt, then the “STS-1 Telecom Bus – Channel 2” will generate an interrupt anytime it declares the “TxFIFO Overrun” condition. 0 – Disables the “TxFIFO Overrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 2. 1 – Enables the “TxFIFO Overrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 2. Note: 4 STS-1 Telecom Bus # 2 TxFIFO Underrun Interrupt Enable R/W This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has been enabled. STS-1 Telecom Bus – TxFIFO Underrun Interrupt Enable – Channel 2: This READ/WRITE bit-field permits the user to either enable or disable the “TxFIFO Underrun” Interrupt, associated with STS-1 Telecom Bus – Channel 2. If the user enables this interrupt, then the “STS-1 Telecom Bus – Channel 2” will generate an interrupt anytime it declares the “TxFIFO Underrun” condition. 0 – Disables the “TxFIFO Underrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 2. 1 – Enables the “TxFIFO Underrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 2. Note: 3 STS-1 Telecom Bus # 1 TxFIFO Overrun Interrupt Enable R/W This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has been enabled. STS-1 Telecom Bus – TxFIFO Overrun Interrupt Enable – Channel 1: This READ/WRITE bit-field permits the user to either enable or disable the “TxFIFO Overrun” Interrupt, associated with STS-1 Telecom Bus – Channel 1. If the user enables this interrupt, then the “STS-1 Telecom Bus – Channel 1” will generate an interrupt anytime it declares the “TxFIFO Overrun” condition. 0 – Disables the “TxFIFO Overrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 1. 1 – Enables the “TxFIFO Overrun” Interrupt, associated with “STS-1 80 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Telecom Bus – Channel 1. Note: 2 STS-1 Telecom Bus # 1 TxFIFO Underrun Interrupt Enable R/W This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has been enabled. STS-1 Telecom Bus – TxFIFO Underrun Interrupt Enable – Channel 1: This READ/WRITE bit-field permits the user to either enable or disable the “TxFIFO Underrun” Interrupt, associated with STS-1 Telecom Bus – Channel 1. If the user enables this interrupt, then the “STS-1 Telecom Bus – Channel 1” will generate an interrupt anytime it declares the “TxFIFO Underrun” condition. 0 – Disables the “TxFIFO Underrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 1. 1 – Enables the “TxFIFO Underrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 1. Note: 1 STS-1 Telecom Bus # 0 TxFIFO Overrun Interrupt Enable R/W This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has been enabled. STS-1 Telecom Bus – TxFIFO Overrun Interrupt Enable – Channel 0: This READ/WRITE bit-field permits the user to either enable or disable the “TxFIFO Overrun” Interrupt, associated with STS-1 Telecom Bus – Channel 0. If the user enables this interrupt, then the “STS-1 Telecom Bus – Channel 0” will generate an interrupt anytime it declares the “TxFIFO Overrun” condition. 0 – Disables the “TxFIFO Overrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 0. 1 – Enables the “TxFIFO Overrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 0. Note: 0 STS-1 Telecom Bus # 0 TxFIFO Underrun Interrupt Enable R/W This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has been enabled. STS-1 Telecom Bus – TxFIFO Underrun Interrupt Enable – Channel 0: This READ/WRITE bit-field permits the user to either enable or disable the “TxFIFO Underrun” Interrupt, associated with STS-1 Telecom Bus – Channel 3. If the user enables this interrupt, then the “STS-1 Telecom Bus – Channel 0” will generate an interrupt anytime it declares the “TxFIFO Underrun” condition. 0 – Disables the “TxFIFO Underrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 0. 1 – Enables the “TxFIFO Underrun” Interrupt, associated with “STS-1 Telecom Bus – Channel 0. Note: This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has been enabled. 81 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 33: Operation General Purpose Input/Output Register – Byte 0 (Address Location= 0x0147) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GPIO_7 GPIO_6 GPIO_5 GPIO_4 GPIO_3 GPIO_2 GPIO_1 GPIO_0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 GPIO_7 R/W DESCRIPTION General Purpose Input/Output Pin # 7: The exact function of this READ/WRITE bit-field depends upon whether the “GPIO_7” pin is configured to be an input or an output pin. If GPIO_7 is configured to be an input pin: If GPIO_7 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the “GPIO_7” (pin number AA25) input pin. If the “GPIO_7” input pin is pulled to a logic “HIGH”, then this register bit will be set to “1”. Conversely, if the “GPIO_7” input pin is pulled to a logic “LOW”, then this register bit will be set to “0”. If GPIO_7 is configured to be an output pin: If GPIO_7 is configured to be an output pin, then the user can control the logic level of “GPIO_7” by writing the appropriate value into this bit-field. Setting this bit-field to “0” causes the GPIO_7 output pin to be driven “LOW”. Conversely, setting this bit-field to “1” causes the GPIO_7 output pin to be driven “HIGH”. Note: 6 GPIO_6 R/W This register bit-field is only active if STS-1 Telecom Bus – Channel 2 is enabled. General Purpose Input/Output Pin # 6: The exact function of this READ/WRITE bit-field depends upon whether the “GPIO_6” pin is configured to be an input or an output pin. If GPIO_6 is configured to be an input pin: If GPIO_6 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the “GPIO_6” (pin number W24) input pin. If the “GPIO_6” input pin is pulled to a logic “HIGH”, then this register bit will be set to “1”. Conversely, if the “GPIO_6” input pin is pulled to a logic “LOW”, then this register bit will be set to “0”. If GPIO_6 is configured to be an output pin: If GPIO_6 is configured to be an output pin, then the user can control the logic level of “GPIO_6” by writing the appropriate value into this bit-field. Setting this bit-field to “0” causes the GPIO_6 output pin to be driven “LOW”. Conversely, setting this bit-field to “1” causes the GPIO_6 output pin to be driven “HIGH”. Note: 5 GPIO_5 R/W This register bit-field is only active if STS-1 Telecom Bus – Channel 2 is enabled. General Purpose Input/Output Pin # 5: The exact function of this READ/WRITE bit-field depends upon whether the “GPIO_5” pin is configured to be an input or an output pin. 82 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 If GPIO_5 is configured to be an input pin: If GPIO_5 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the “GPIO_5” (pin number AC26) input pin. If the “GPIO_5” input pin is pulled to a logic “HIGH”, then this register bit will be set to “1”. Conversely, if the “GPIO_5” input pin is pulled to a logic “LOW”, then this register bit will be set to “0”. If GPIO_5 is configured to be an output pin: If GPIO_5 is configured to be an output pin, then the user can control the logic level of “GPIO_5” by writing the appropriate value into this bit-field. Setting this bit-field to “0” causes the GPIO_5 output pin to be driven “LOW”. Conversely, setting this bit-field to “1” causes the GPIO_5 output pin to be driven “HIGH”. Note: 4 GPIO_4 R/W This register bit-field is only active if STS-1 Telecom Bus – Channel 1 is enabled. General Purpose Input/Output Pin # 4: The exact function of this READ/WRITE bit-field depends upon whether the “GPIO_4” pin is configured to be an input or an output pin. If GPIO_4 is configured to be an input pin: If GPIO_4 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the “GPIO_4” (pin number Y25) input pin. If the “GPIO_4” input pin is pulled to a logic “HIGH”, then this register bit will be set to “1”. Conversely, if the “GPIO_4” input pin is pulled to a logic “LOW”, then this register bit will be set to “0”. If GPIO_4 is configured to be an output pin: If GPIO_4 is configured to be an output pin, then the user can control the logic level of “GPIO_4” by writing the appropriate value into this bit-field. Setting this bit-field to “0” causes the GPIO_4 output pin to be driven “LOW”. Conversely, setting this bit-field to “1” causes the GPIO_4 output pin to be driven “HIGH”. Note: 3 GPIO_3 R/W This register bit-field is only active if STS-1 Telecom Bus – Channel 1 is enabled. General Purpose Input/Output Pin # 3: The exact function of this READ/WRITE bit-field depends upon whether the “GPIO_3” pin is configured to be an input or an output pin. If GPIO_3 is configured to be an input pin: If GPIO_3 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the “GPIO_3” (pin number AB26) input pin. If the “GPIO_3” input pin is pulled to a logic “HIGH”, then this register bit will be set to “1”. Conversely, if the “GPIO_3” input pin is pulled to a logic “LOW”, then this register bit will be set to “0”. If GPIO_3 is configured to be an output pin: If GPIO_3 is configured to be an output pin, then the user can control the logic level of “GPIO_3” by writing the appropriate value into this bit-field. Setting this bit-field to “0” causes the GPIO_3 output pin to be driven “LOW”. Conversely, setting this bit-field to “1” causes the GPIO_3 output pin to be driven “HIGH”. 83 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Note: 2 GPIO_2 R/W Rev222...000...000 This register bit-field is only active if STS-1 Telecom Bus – Channel 1 is enabled. General Purpose Input/Output Pin # 2: The exact function of this READ/WRITE bit-field depends upon whether the “GPIO_2” pin is configured to be an input or an output pin. If GPIO_2 is configured to be an input pin: If GPIO_2 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the “GPIO_2” (pin number V23) input pin. If the “GPIO_2” input pin is pulled to a logic “HIGH”, then this register bit will be set to “1”. Conversely, if the “GPIO_2” input pin is pulled to a logic “LOW”, then this register bit will be set to “0”. If GPIO_2 is configured to be an output pin: If GPIO_2 is configured to be an output pin, then the user can control the logic level of “GPIO_2” by writing the appropriate value into this bit-field. Setting this bit-field to “0” causes the GPIO_2 output pin to be driven “LOW”. Conversely, setting this bit-field to “1” causes the GPIO_2 output pin to be driven “HIGH”. Note: 1 GPIO_1 R/W This register bit-field is only active if STS-1 Telecom Bus – Channel 0 is enabled. General Purpose Input/Output Pin # 1: The exact function of this READ/WRITE bit-field depends upon whether the “GPIO_1” pin is configured to be an input or an output pin. If GPIO_1 is configured to be an input pin: If GPIO_1 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the “GPIO_1” (pin number AC27) input pin. If the “GPIO_1” input pin is pulled to a logic “HIGH”, then this register bit will be set to “1”. Conversely, if the “GPIO_1” input pin is pulled to a logic “LOW”, then this register bit will be set to “0”. If GPIO_1 is configured to be an output pin: If GPIO_1 is configured to be an output pin, then the user can control the logic level of “GPIO_1” by writing the appropriate value into this bit-field. Setting this bit-field to “0” causes the GPIO_1 output pin to be driven “LOW”. Conversely, setting this bit-field to “1” causes the GPIO_1 output pin to be driven “HIGH”. Note: 0 GPIO_0 R/W This register bit-field is only active if STS-1 Telecom Bus – Channel 0 is enabled. General Purpose Input/Output Pin # 0: The exact function of this READ/WRITE bit-field depends upon whether the “GPIO_0” pin is configured to be an input or an output pin. If GPIO_0 is configured to be an input pin: If GPIO_0 is configured to be an input pin, then this register bit operates as a READ-ONLY bit-field that reflects the state of the “GPIO_0” (pin number W25) input pin. If the “GPIO_0” input pin is pulled to a logic “HIGH”, then this register bit will be set to “1”. Conversely, if the “GPIO_0” input pin is pulled to a logic “LOW”, then this register bit will be set to “0”. 84 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S If GPIO_0 is configured to be an output pin: If GPIO_0 is configured to be an output pin, then the user can control the logic level of “GPIO_0” by writing the appropriate value into this bit-field. Setting this bit-field to “0” causes the GPIO_0 output pin to be driven “LOW”. Conversely, setting this bit-field to “1” causes the GPIO_0 output pin to be driven “HIGH”. Note: This register bit-field is only active if STS-1 Telecom Bus – Channel 0 is enabled. 85 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 34: Operation General Purpose Input/Output Direction Register 0 (Address Location= 0x014B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GPIO_DIR[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 GPIO_DIR[7] R/W DESCRIPTION GPIO_7 Direction Select: This READ/WRITE bit-field permits the user to configure the “GPIO_7” pin (pin number AA25) to function as either an input or an output pin. 0 – Configures GPIO_7 to function as an input pin. 1 – Configures GPIO_7 to function as an output pin. Note: 6 GPIO_DIR[6] R/W This register bit-field is only active if STS-1 Telecom Bus Interface – Channel 2 is enabled. GPIO_6 Direction Select: This READ/WRITE bit-field permits the user to configure the “GPIO_6” pin (pin number W24) to function as either an input or an output pin. 0 – Configures GPIO_6 to function as an input pin. 1 – Configures GPIO_6 to function as an output pin. Note: 5 GPIO_DIR[5] R/W This register bit-field is only active if STS-1 Telecom Bus Interface – Channel 2 is enabled. GPIO_5 Direction Select: This READ/WRITE bit-field permits the user to configure the “GPIO_5” pin (pin number AC26) to function as either an input or an output pin. 0 – Configures GPIO_5 to function as an input pin. 1 – Configures GPIO_5 to function as an output pin. Note: 4 GPIO_DIR[4] R/W This register bit-field is only active if STS-1 Telecom Bus Interface – Channel 1 is enabled. GPIO_4 Direction Select: This READ/WRITE bit-field permits the user to configure the “GPIO_4” pin (pin number Y25) to function as either an input or an output pin. 0 – Configures GPIO_4 to function as an input pin. 1 – Configures GPIO_4 to function as an output pin. Note: 3 GPIO_DIR[3] R/W This register bit-field is only active if STS-1 Telecom Bus Interface – Channel 1 is enabled. GPIO_3 Direction Select: This READ/WRITE bit-field permits the user to configure the “GPIO_3” pin (pin number AB26) to function as either an input or an output pin. 0 – Configures GPIO_3 to function as an input pin. 1 – Configures GPIO_3 to function as an output pin. Note: This register bit-field is only active if STS-1 Telecom Bus Interface – Channel 1 is enabled. 86 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 2 GPIO_DIR[2] R/W GPIO_2 Direction Select: This READ/WRITE bit-field permits the user to configure the “GPIO_2” pin (pin number V23) to function as either an input or an output pin. 0 – Configures GPIO_2 to function as an input pin. 1 – Configures GPIO_2 to function as an output pin. Note: 1 GPIO_DIR[1] R/W This register bit-field is only active if STS-1 Telecom Bus Interface – Channel 0 is enabled. GPIO_1 Direction Select: This READ/WRITE bit-field permits the user to configure the “GPIO_1” pin (pin number AC27) to function as either an input or an output pin. 0 – Configures GPIO_1 to function as an input pin. 1 – Configures GPIO_1 to function as an output pin. Note: 0 GPIO_DIR[0] R/W This register bit-field is only active if STS-1 Telecom Bus Interface – Channel 0 is enabled. GPIO_0 Direction Select: This READ/WRITE bit-field permits the user to configure the “GPIO_0” pin (pin number W25) to function as either an input or an output pin. 0 – Configures GPIO_0 to function as an input pin. 1 – Configures GPIO_0 to function as an output pin. Note: This register bit-field is only active if STS-1 Telecom Bus Interface – Channel 0 is enabled. 87 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 35: Operation Output Control Register – Byte 1 (Address Location= 0x0150) BIT 7 BIT 6 BIT 5 8kHz or STUFF Out Enable 8kHz OUT Select Egress Direction Monitored – STUFF Output R/W R/W R/W R/O R/O 0 0 0 0 0 BIT NUMBER NAME TYPE 7 8kHz or STUFF Out Enable R/W BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O 0 0 0 Unused DESCRIPTION 8kHz or STUFF Output Enable – LOF Output Pin: This READ/WRITE bit-field, along with Bit 6 (8kHz OUT Select) permits the user to define the role of the LOF output pin (pin AD11). The relationship between the states of these bit-fields and the corresponding role of the LOF output pin is presented below. Bit 7 (8kHz or STUFF Out Enable) Bit 6 (8kHz OUT Select) Role of LOF output pin 0 0 LOF or AIS-L Indicator 0 1 LOF or AIS-L Indicator 1 0 Bit Stuff Indicator Output 1 1 8kHz Output Note: 1. If Bit 7 is set to “0”, then Bit 1 (AIS-L Output Enable) within the “Receive STS-3 Transport – Auto AIS (in Downstream STS-1s) Control Register (Address Location= 0x116B) will indictate whether or not pin AD11 is the “LOF” or the “AIS-L” output indicator. 2. If Bit 1 (AIS-L Output Enable) is set to “0”, then pin AD11 will function as the LOF output indicator. 3. If Bit 1 (AIS-L Output Enable) is set to “1”, then pin AD11 will function as the AIS-L output indicator. 6 8kHz OUT Select R/W 8kHz OUT – LOF Output Pin: This READ/WRITE bit-field, along with Bit 6 (8kHz OUT Select) permits the user to define the role of the LOF output pin (pin AD11). The relationship between the states of these bit-fields and the corresponding role of the LOF output pin is presented below. Bit 7 (8kHz or STUFF Out Enable) Bit 6 (8kHz OUT Select) 0 0 LOF or AIS-L Indicator 0 1 LOF or AIS-L Indicator 1 0 Bit Stuff Indicator Output 1 1 8kHz Output 88 Role of LOF output pin XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 5 Egress Direct Monitored –STUFF Output R/W Egress Direction Monitored – STUFF Output: If the LOF output pin has been configured to function as a “STUFF Indicator” output, then it can be configured to reflect the current stuff opportunities of the channel designated by Bits 7 through 4 (Stuff Indicator Channel Select[3:0]) within the Operation Output Control Register – Byte 0. This READ/WRITE bit-field permits the user to configure the LOF output pin to either reflect the “current stuff opportunities” for the Ingress or Egress Path of the selected channel. 0 – Configures the LOF output pin to reflect the “current stuff opportunity” of the Ingress Path of the “selected” channel. 1 – Configures the LOF output pin to reflect the “current stuff opportunity” of the Egress Path of the “selected” channel. Note: 4–0 Unused This bit-field will be ignored if the “selected” channel has been configured to operate in the STS-1 Mode. R/O 89 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 36: Operation Output Control Register – Byte 0 (Address Location= 0x0153) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Stuff Indicator Channel Select[1:0] Unused BIT 2 BIT 1 BIT 0 8kHz Source Channel Select[1:0] Unused R/O R/O R/W R/W R/O R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–6 Unused R/O 5–4 Stuff Indicator Channel Select[1:0] R/W DESCRIPTION Stuff Indicator – Channel Select[1:0]: These two (2) READ/WRITE bit-fields permit the user to identify which of the 3 channels should have their “bit-stuff opportunity” status reflected on the LOF output pin. Setting these bit-fields to [0, 0] configures the LOF output pin to reflect the bit-stuff opportunity status of Channel 0. Likewise, setting these bitfields to [1, 0] configures the LOF output pin to reflect the bit-stuff opportunity status of Channel 2. Note: These bit-fields are ignored if any of the following are true. 1. If the corresponding channel has been configured to operate in the STS-1 Mode. 2. If the LOF output pin has been configured to function as the LOF or AIS-L indicator output. 3. If the LOF output pin has been configured to function as an 8kHz output pin. 3–2 Unused R/O 1–0 8kHz Source Channel Select[1:0] R/W 8kHz Source Channel Select[1:0]: If the LOF output pin has been configured to output an 8kHz clock output signal, then the XRT94L33 will derive this 8kHz clock signal, from the Ingress DS3/E3 or Receive STS-1 signal of the “Selected” channel. These two(2) READ/WRITE bit-fields permit the user to specify the “Selected” channel. Setting these bit-fields to [0, 0] configures the LOF output pin to output an 8kHz clock signal, that is derived from the Ingress DS3/E3 or Receive STS-1 input signal of Channel 0. Likewise, setting these bitfields to [1, 0] configures the LOF output pin to reflect the bit-stuff opportunity status of Channel 2. Note: These bit-fields are ignored if any of the following are true. 1. If the LOF output pin has been configured to function as the LOF or AIS-L indicator output. 2. If the LOF output pin has been configured to function as the “Stuff Indicator” output pin. 90 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 37: Operation Slow Speed Port Control Register – Byte 1 (Address Location= 0x0154) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SSI Port Enable SSI Port – Insert Direction SSI Port Force All Zeros Pattern Unused SSE Port Enable SSE Port – Insert Direction SSE Port Force All Zeros Pattern Unused R/W R/W R/W R/O R/W R/W R/W R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 SSI Port Enable R/W DESCRIPTION Slow-Speed Ingress – Interface Port Enable: This READ/WRITE bit-field permits the user to enable or disable the SSI (Slow-Speed Ingress) Interface Port. If the SSI Interface port is enabled, then it can be used to do either of the following. • To monitor (e.g., to drop out a replica of) the DS3, E3 or STS-1 signal, that is traveling in the Ingress Direction DS3/E3 or Receive STS-1 path of the “Selected” channel within the XRT94L33 device. • To insert (e.g., to add-in) and overwrite the DS3, E3 or STS-1 signal, that is traveling in the Ingress Direction DS3/E3 or Receive STS-1 path of the “Selected” Channel within the XRT94L33 device. 0 – Disables the SSI Interface Port. 1 – Enables the SSI Interface Port. 6 SSI Port – Insert Direction R/W Slow-Speed Ingress – Interface Port – Insert Direction: This READ/WRITE bit-field permits the user to configure the SSI Interface port to either monitor (e.g., extract) an “Ingress Direction DS3/E3” or “Receive STS-1” signal, or to replace (e.g., insert) a DS3, E3 or STS-1 signal into the Ingress DS3/E3 or Receive STS-1 path of the “Selected” channel. If the user configures the SSI Interface port to monitor a given DS3, E3 or STS-1 signal, then the SSI Interface will then be configured to be an “output” interface. In this case, the SSI Interface port will consist of an “SSI_POS”, “SSI_NEG” and “SSI_CLK” output signals. Additionally, a copy of the Selected Ingress Direction DS3/E3 or Receive STS-1 signal will be output via this output port. If the user configures the SSI Interface port to replace (e.g., insert) an “Ingress DS3/E3” or Receive STS-1 signal, then the SSI Interface will then be configured to be an “input” interface. In this case, the SSI Interface port will consist of an “SSI_POS”, “SSI_NEG” and “SSI_CLK” input signals. Additionally, the DS3, E3 or STS-1 signal that is applied at this input port will overwrite that of the selected “Ingress Direction DS3/E3” or the Receive STS-1 signal. 0 – Configures the SSI Interface as an output port that will permit the user to monitor the “selected” Ingress DS3/E3 or Receive STS-1 signal. 1 – Configures the SSI Interface as an input port. In this configuration, the DS3, E3 or STS-1 signal that is input via this port will replace/overwrite the “Ingress” DS3/E3 or Receive STS-1 signal, within the “selected” channel, prior to being mapped into STS-3. Note: This bit-field will be ignored if the SSI Interface port is disabled. 91 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 5 SSI Port - Force All Zeros Pattern R/W Rev222...000...000 Slow Speed Ingress – Interface Port – Force All Zeros Pattern: This READ/WRITE bit-field permits the user to force the Ingress DS3/E3 or Receive STS-1 signal, within the “selected” channel to an “All Zeros” pattern. 0 – Configures the Selected Ingress Direction DS3/E3 or Receive STS-1 signal (within the “selected” channel) to flow to the DS3/E3 Mapper Block or to the Transmit SONET POH Processor block, in a normal manner. 1 – Forces the data, within the Selected Ingress Direction DS3/E3 or Receive STS-1 signal (within the “selected” channel) to an “All Zeros” pattern. Note: 4 Unused R/O 3 SSE Port Enable R/W This bit-field will be ignored if the SSI Interface port is disabled. Slow-Speed Egress – Interface Port Enable: This READ/WRITE bit-field permits the user to enable or disable the SSE (Slow Speed Egress) Interface Port. If the SSE Interface port is enabled, then it can be used to do either of the following. • To monitor (e.g., to drop out a replica of) the DS3, E3 or STS-1 signal, that is traveling in the Egress Direction DS3/E3 or Transmit STS-1 path of the “Selected” channel within the XRT94L33 device. • To insert (e.g., to add in) and overwrite the DS3, E3 or STS-1 signal, that is traveling in the Engress Direction DS3/E3 or Transmit STS-1 path of the “Selected” Channel within the XRT94L33 device. 0 – Disables the SSE Interface Port 1 – Enables the SSE Interface Port. 2 SSE Port – Insert Direction R/W Slow Speed Egress – Interface Port – Insert Direction: This READ/WRITE bit-field permits the user to configure the SSE Interface port to either monitor (e.g., extract) an “Egress Direction DS3/E3” or “Transmit STS-1” signal, or to replace (e.g., insert) a DS3, E3 or STS-1 signal into the Egress Direction DS3/E3 or Transmit STS-1 path of the “Selected” channel. If the user configures the SSE Interface port to monitor a given DS3, E3 or STS-1 signal, then the SSE Interface wil then be configured to be an “output” interface. In this case, the SSE Interface port will consist of an “SSE_POS”, “SSE_NEG” and “SSE_CLK” output signals. Additionally, a copy of the Selected Egress Direction DS3/E3 or Transmit STS-1 signal will be output via this output port. If the user configures the SSE Interface port to replace (e.g., insert) an “Egress DS3/E3” or Transmit STS-1 signal, then the SSE Interface will then be configured to be an “input” interface. In this case, the SSE Interface port will consist of an “SSE_POS”, “SSE_NEG” and “SSE_CLK” input signals. Additionally, the DS3, E3 or STS-1 signal, that is applied at this input port will overwrite that of the selected “Egress Direction DS3/E3” or the Transmit STS-1 signal. 0 – Configures the SSE Interface as an output port that will permit the user to monitor the “selected” Egress DS3/E3 or Transmit STS-1 signal.. 1 – Configures the SSE Interface as an input port. In this configuration, the DS3, E3 or STS-1 signal that is input via this port will replace/overwrite the “Egress” DS3/E3 or Transmit STS-1 signal, within the “selected” channel, prior to being mapped into STS-3. 92 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Note: 1 SSE Port - Force All Zeros Pattern R/W This bit-field will be ignored if the SSE Interface port is disabled. Slow Speed Egress – Interface Port – Force to All Zeros: This READ/WRITE bit-field permits the user to force the Egress DS3/E3 or Transmit STS-1 signal, within the “selected” channel to an “All Zeros” pattern. 0 – Configures the Selected Egress Direction DS3/E3 or Transmit STS-1 signal (within the “selected” channel) to flow to the DS3/E3/STS-1 LIU IC in a normal manner. 1 – Forces the data, within the Selected Egress Direction DS3/E3 or Transmit STS-1 signal (within the “selected” channel) to an “All Zeros” pattern. Note: 0 Unused This bit-field will be ignored if the SSE Interface port is disabled. R/O 93 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 38: Operation Slow Speed Port Control Register – Byte 0 (Address Location= 0x0157) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 SSI_Channel_Select[1:0] BIT 2 Unused BIT 1 BIT 0 SSE_Channel_Select[1:0] R/O R/O R/W R/W R/O R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–6 Unused R/O 5–4 SSI_Channel_Select[ 1:0]: R/W DESCRIPTION Slow-Speed Ingress – Interface Port – Channel Select[1:0]: These READ/WRITE bit-fields permit the user to select which of the 3 Ingress Direction DS3/E3 or Receive STS-1 signals will be processed via the SSI Interface port. Setting SSI_Channel_Select[1:0] to [0, 0] configures the SSI Interface port to process the Ingress Direction DS3/E3 or Receive STS-1 signal associated with Channel 0. Likewise, setting SSI_Channel_Select[1:0] to [1, 0] configures the SSI Interface port to process the Ingress DS3/E3 or Receive STS-1 signal associated with Channel 2. Note: 3 –2 Unused R/O 1–0 SSE_Channel_Select [1:0] R/W These bit-fields are ignored if the SSI Interface port is disabled. Slow Speed Egress – Interface Port – Channel Select[1:0]: These READ/WRITE bit-fields permit the user to select which of the 3 Egress Direction DS3/E3 or Receive STS-1 signals will be processed via the SSE Interface port. Setting SSE_Channel_Select[1:0] to [0, 0] configures the SSE Interface port to process the Egress Direction DS3/E3 or Transmit STS-1 signal associated with Channel 0. Likewise, setting SSE_Channel_Select[1:0] to [1, 0] configures the SSE Interface port to process the Egress DS3/E3 or Transmit STS-1 signal associated with Channel 2. Note: These bit-fields are ignored if the SSE Interface port is disab led. 94 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 39: Operation – DS3/E3/STS-1 Clock Frequency Out of Range Detection – Direction Register (Address Location= 0x0158) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ON_EGRESS DIRECTION Unused R/O R/O R/O R/O R/O R/O R/O R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–1 Unused R/O 0 ON_EGRESS_DIRECTION R/W DESCRIPTION Frequency Out of Range Detection on Egress Direction: This READ/WRITE bit-field permits the user to configure the “DS3/E3/STS-1 Clock Frequency – Out of Range Detector” to operate in either the Ingress or Egress direction. 0 – Configures the DS3/E3/STS-1 Clock Frequency – Out of Range Detector” to operate on the DS3, E3 or STS-1 clock signals in the Ingress Direction. 1 – Configures the DS3/E3/STS-1 Clock Frequency – Out of Range Detector” to operate on the DS3, E3 or STS-1 clock signals in the Egress Direction. Table 40: Operation – DS3/E3/STS-1Clock Frequency – DS3 Out of Range Detection Threshold Register (Address Location= 0x015A) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DS3_OUT_OF_RANGE_DETECTION_THRESHOLD[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 DS3_OUT_OF_RANGE_ DETECTION_THR R/W DESCRIPTION DS3 Out of Range – Detection Threshold[7:0]: These eight READ/WRITE bit-fields permit the user to define (in terms of ppm) the frequency difference that must exist between a given DS3 signal (in either the Ingress or Egress direction) and that of the REFCLK45 input clock signal; before the XRT94L33 will declare a “DS3 Clock Frequency – Out of Range” condition. 95 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 41: Operation – DS3/E3/STS-1Clock Frequency – STS-1/E3 Out of Range Detection Threshold Registers (Address Location= 0x015B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 STS-1/E3_OUT_OF_RANGE_DETECTION_THRESHOLD[7:0] BIT NUMBER NAME TYPE 7–0 STS1/E3_OUT_OF_RAN GE_DETECTION_THR R/W DESCRIPTION STS-1/E3 Out of Range – Detection Threshold[7:0]: These eight READ/WRITE bit-fields permit the user to define (in terms of ppm) the frequency difference that must exist between a given STS-1 or E3 signal (in either the Ingress or Egress direction) and that of the REFCLK51/REFCLK34 input clock signal; before the XRT94L33 will declare a “STS-1/E3 Clock Frequency – Out of Range” condition. Table 42: Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Enable Register – Byte 0 (Address Location=0x015D) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 Out of Range – Channel 2 Interrupt enable Out of Range – Channel 1 Interrupt Enable Out of Range – Channel 0 Interrupt Enable R/O R/O R/O R/O R/O R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-3 Unused R/O 2 Out of Range – Channel 2 Interrupt Enable R/W DESCRIPTION DS3/E3/STS-1 Frequency – Out of Range – Channel 2 – Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 2. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the frequency of the DS3, E3 or STS-1 signal (in the selected direction – Ingress or Egress) within Channel 2, differs from its corresponding Reference Clock signal (e.g., REFCLK45, REFCLK34 or REFCLK51) by its “Out of Range Detection Threshold” (in terms of ppm) or more. 0 – Disables the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 2. 1 – Enables the “DS3/E3/STS-1 Frequency Interrupt for Channel 2. 1 Out of Range – Channel 1 Interrupt Enable R/W - Out of Range” DS3/E3/STS-1 Frequency – Out of Range – Channel 1 – Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt 96 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S for Channel 1. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the frequency of the DS3, E3 or STS-1 signal (in the selected direction – Ingress or Egress) within Channel 1, differs from its corresponding Reference Clock signal (e.g., REFCLK45, REFCLK34 or REFCLK51) by its “Out of Range Detection Threshold” (in terms of ppm) or more. 0 – Disables the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 1. 1 – Enables the “DS3/E3/STS-1 Frequency Interrupt for Channel 1. 0 Out of Range – Channel 0 Interrupt Enable R/W - Out of Range” DS3/E3/STS-1 Frequency – Out of Range – Channel 0 – Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 0. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the frequency of the DS3, E3 or STS-1 signal (in the selected direction – Ingress or Egress) within Channel 0, differs from its corresponding Reference Clock signal (e.g., REFCLK45, REFCLK34 or REFCLK51) by its “Out of Range Detection Threshold” (in terms of ppm) or more. 0 – Disables the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 0. 1 – Enables the “DS3/E3/STS-1 Frequency Interrupt for Channel 0. 97 - Out of Range” XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 43: Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Status Register – Byte 0 (Address Location=0x015F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 Out of Range – Channel 2 Interrupt Status Out of Range – Channel 1 Interrupt Status Out of Range – Channel 0 Interrupt Status R/O R/O R/O R/O R/O RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-3 Unused R/O 2 Out of Range – Channel 2 Interrupt Status RUR DESCRIPTION DS3/E3/STS-1 Frequency – Out of Range – Channel 2 – Interrupt Status: This RESET-Upon-READ bit-field indicates whether or not the XRT94L33 has declares the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 2, since the last read of this register. 0 – Indicates that the “DS3/E3/STS-1 Frequency - Out of Range” Interrupt for Channel 2 has NOT occurred since the last read of this register. 1 – Indicates that the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 2 has occurred since the last read of this register. 1 Out of Range – Channel 1 Interrupt Status RUR DS3/E3/STS-1 Frequency – Out of Range – Channel 1 – Interrupt Status: This RESET-Upon-READ bit-field indicates whether or not the XRT94L33 has declares the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 1, since the last read of this register. 0 – Indicates that the “DS3/E3/STS-1 Frequency - Out of Range” Interrupt for Channel 1 has NOT occurred since the last read of this register. 1 – Indicates that the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 1 has occurred since the last read of this register. 0 Out of Range – Channel 0 Interrupt Status RUR DS3/E3/STS-1 Frequency – Out of Range – Channel 0 – Interrupt Status: This RESET-Upon-READ bit-field indicates whether or not the XRT94L33 has declares the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 0, since the last read of this register. 0 – Indicates that the “DS3/E3/STS-1 Frequency - Out of Range” Interrupt for Channel 0 has NOT occurred since the last read of this register. 1 – Indicates that the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for Channel 0 has occurred since the last read of this register. 98 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 44: APS Mapping Register (Address Location= 0x0180) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Protection Channel[3:0] BIT 1 BIT 0 Working Channel[3:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Protection Channel[3:0] R/W Working Channel[3:0] R/W 3-0 DESCRIPTION Protection Channel[3:0]: These register bits are only active if the XRT94L33 device has been configured to operate in either the ATM UNI or PPP over the STS-3c Mode. These register bits are not active for Aggregation Applications. Working Channel[3:0]: These register bits are only active if the XRT94L33 device has been configured to operate in either the ATM UNI or PPP over the STS-3c Mode. These register bits are not active for Aggregation Applications. Table 45: APS Control Register - 1:1 & 1:N Protection Map (Address Location= 0x0181) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 APS Group Enable Invoke Payload APS Protection Channel Timing Source Receive Payload Bypass APS Group Reset Line Port In Use Line APS Auto Switch Enable Line APS Switch R/W R/W R/W R/W R/W R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 APS Group Enable R/W Invoke Payload APS R/W Protection Channel Timing Source R/W Receive Payload Bypass R/W 6 5 4 DESCRIPTION APS Group Enable: This register bit is only active if the XRT94L33 device has been configured to operate in either the ATM UNI or PPP over STS-3c Mode. This register bit is not active for Aggregation Applications. Invoke Payload APS: This register bit is only active if the XRT94L33 device has been configured to operate in either the ATM UNI or PPP over STS-3c Mode. This register bit is not active for Aggregation Applications. Protection Channel Timing Source: This register bit is only active if the XRT94L33 device has been configured to operate in either the ATM UNI over PPP over STS-3c Mode. This register bit is not active for Aggregation Applications. Receive Payload Bypass: This READ/WRITE bit-field permits the user to bypass the receive payload of protection channel. 0 – Receive payload is not bypassed. 1 – Receive payload is bypassed. 99 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 3 2 APS Group Reset R/W Line Port In Use R/O Rev222...000...000 APS Group Reset: This register bit is only active if the XRT94L33 device has been configured to operate in either the ATM UNI or PPP over STS-3c Mode. This register bit is not active for Aggregation Applications. Line Port In Use: This READ-ONLY bit-field permits the user to check and identify which Receive STS-3/STM-1 PECL Interface Port is currently being used to receive the incoming STS-3/STM-1 data 0 – Indicates that the Primary Receive STS-3/STM-1 PECL Interface Port is the “current port in use”. 1 – Indicates that the Redundant Receive STS-3/STM-1 PECL Interface Port is the “current port in use.” 1 Line APS Auto Switch Enable R/W Line APS Auto Switch Enable: This READ/WRITE bit-field permits the user to configure the XRT94L33 to automatically switch from the “Primary” to the “Redundant” port, whenever the Primary Receive STS-3 TOH Processor block declares the LOS (Loss of Signal) defect condition. 0 – Disables the APS Auto Switch feature. In this mode, the XRT94L33 will not automatically switch from the “Primary” port to the “Redundant” port, whenever the Primary Receive STS-3 TOH Processor block declares the LOS defect condition. 1 – Enables the APS Auto Switch feature. In this mode, the XRT94L33 device will automatically switch from the “Primary” port to the “Redundant” port, whenever the Primary STS-3 TOH Processor block declares the LOS defect condition. NOTE: This “APS Auto Switch” feature cannot be used to support “revertive” switching (e.g., switching from the Redundant to the Primary Port whenever the Redundant Receive STS-3 TOH Processor block declares the LOS defect condition). 0 Line APS Switch R/W Line APS Switch: This READ/WRITE bit-field permits the user to command a Line APS switch (from one port to the other) via software control. 0 – Configures each of the three (3) Receive SONET POH Processor blocks to accept the incoming SONET traffic from the Primary Receive STS-3 TOH Processor block. 1 – Configures each of the three (3) Receive SONET POH Processor blocks to accept the incoming SONET traffic from the Redundant Receive STS-3 TOH Processor block. 100 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 46: APS Status Register (Address Location= 0x0194) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Receive APS Parity Check Enable Receive APS Parity - ODD Transmit APS Parity Check Enable Transmit APS Parity - ODD Transmit APS Parity Error Detected Receive APS Parity Error Detected R/O R/O R/W R/W R/W R/W R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-6 Unused R/O 5 Receive APS Parity Check Enable R/W Receive APS Parity – ODD R/W Transmit APS Parity Check Enable R/W Transmit APS Parity ODD R/W Transmit APS Parity Error Detected R/O Receive APS Parity Error Detected R/O 4 3 2 1 0 DESCRIPTION Receive APS Parity Check Enable: This register bit is only active if the XRT94L33 device has been configured to operate in the “ATM UNI” or “PPP over STS-3c” Mode. This register bit is NOT active for Aggregation Applications. Receive APS Parity - ODD: This register bit is only active if the XRT94L33 device has been configured to operate in the “ATM UNI” or “PPP over STS-3c” Mode. This register bit is NOT active for Aggregation Applications. Transmit APS Parity Check Enable: This register bit is only active if the XRT94L33 device has been configured to operate in the “ATM UNI” or “PPP over STS-3c” Mode. This register bit is NOT active for Aggregation Applications. Transmit APS Parity - ODD: This register bit is only active if the XRT94L33 device has been configured to operate in the “ATM UNI” or “PPP over STS-3c” Mode. This register bit is NOT active for Aggregation Applications. Transmit APS Parity Error Detected: This register bit is only active if the XRT94L33 device has been configured to operate in the “ATM UNI” or “PPP over STS-3c” Mode. This register bit is NOT active for Aggregation Applications. Receive APS Parity Error Detected: This register bit is only active if the XRT94L33 device has been configured to operate in the “ATM UNI” or “PPP over STS-3c” Mode. This register bit is NOT active for Aggregation Applications. 101 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 47: APS Status Register (Address Location= 0x0196) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 APS Group FIFO Overflow Status Unused R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-1 Unused R/O 0 APS Group FIFO Overflow Status R/O DESCRIPTION APS Group FIFO Overflow Status: This register bit is only active if the XRT94L33 device has been configured to operate in the “ATM UNI” or “PPP over STS-3c” Mode. This register bit is NOT active for Aggregation Applications. Table 48: APS Status Register (Address Location= 0x0197) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 APS Group FIFO Underflow Status Unused R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-1 Unused R/O 0 APS Group FIFO Underflow Status R/O DESCRIPTION APS Group FIFO Underflow Status: This register bit is only active if the XRT94L33 device has been configured to operate in the “ATM UNI” or “PPP over STS-3c” Mode. This register bit is NOT active for Aggregation Applications. 102 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 49: APS Interrupt Register (Address Location= 0x0198) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 Transmit APS Parity Error Interrupt Status Receive APS Parity Error Interrupt Status R/O R/O R/O R/O R/O R/O RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-2 Unused R/O 1 Transmit APS Parity Error Interrupt Status RUR DESCRIPTION Transmit APS Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the transmit APS module has declared a “Transmit APS Parity Error” Interrupt since the last read of this register. 0 – The “Transmit APS Parity Error” Interrupt has not occurred since the last read of this register. 1 - The “Transmit APS Parity Error” Interrupt has occurred since the last read of this register. 7-0 Receive APS Parity Error Interrupt Status RUR Receive APS Parity Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the receive APS module has declared a “Receive APS Parity Error” Interrupt since the last read of this register. 0 – The “Receive APS Parity Error” Interrupt has not occurred since the last read of this register. 1 - The “Receive APS Parity Error” Interrupt has occurred since the last read of this register 103 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 50: APS Interrupt Register (Address Location= 0x019A) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Group Overflow Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Group Overflow Interrupt Status RUR DESCRIPTION Group Overflow Interrupt Status: This RESET-upon-READ bit-field indicates whether or not group n (0-7) APS protection channel has declared a “FIFO overflow” Interrupt since the last read of this register. 0 – The “FIFO overflow” Interrupt has not occurred since the last read of this register. 1 - The “FIFO overflow” Interrupt has occurred since the last read of this register. Table 51: APS Interrupt Register (Address Location= 0x019B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Group Underflow Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Group Underflow Interrupt Status RUR DESCRIPTION Group Underflow Interrupt Status: This RESET-upon-READ bit-field indicates whether or not group n (07) APS protection channel has declared a “FIFO underflow” Interrupt since the last read of this register. 0 – The “FIFO underflow” Interrupt has not occurred since the last read of this register. 1 - The “FIFO underflow” Interrupt has occurred since the last read of this register. 104 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 52: APS Interrupt Enable Register (Address Location= 0x019C) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 Transmit APS Parity Error Interrupt Enable Receive APS Parity Error Interrupt Enable R/O R/O R/O R/O R/O R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-2 Unused R/O 1 Transmit APS Parity Error Interrupt Enable R/W DESCRIPTION Transmit APS Parity Error Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the “Transmit APS Parity Error” Interrupt in Transmit APS module 0 – Disables the “Transmit APS Parity Error” Interrupt 1 – Enables the “Transmit APS Parity Error” Interrupt 7-0 Receive APS Parity Error Interrupt Enable R/W Receive APS Parity Error Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the “Receive APS Parity Error” Interrupt in Receive APS module 0 – Disables the “Receive APS Parity Error” Interrupt 1 – Enables the “Receive APS Parity Error” Interrupt Table 53: APS Interrupt Enable Register (Address Location= 0x019E) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Group Overflow Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Group Overflow Interrupt Enable R/W DESCRIPTION Group Overflow Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the “FIFO overflow” interrupt in group n APS protection channel. 0 – Disables “FIFO overflow” interrupt . 1 – Enables “FIFO overflow” Interrupt 105 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 54: APS Interrupt Enable Register (Address Location= 0x019F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Group Underflow Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Group Underflow Interrupt Enable R/W DESCRIPTION Group Underflow Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the “FIFO underflow” interrupt in group n APS protection channel. 0 – Disables “FIFO underflow” interrupt . 1 – Enables “FIFO underflow” Interrupt 106 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.3 LINE INTERFACE CONTROL BLOCK The register map for the Line Interface Control block is presented in the Table below. Additionally, a detailed description of each of the “Line Interface Control” Block registers is presented below. The Line Interface Control Block registers provide the user with “Command and Control” over the following functional blocks. • The Transmit STS-3/STM-1 PECL Interface block • The Receive STS-3/STM-1 PECL Interface block • The Clock Synthesizer Block In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33 device, with each of these “above-mentioned” functional blocks “highlighted” is presented below in Figure 1. Figure 1: Illustration of the Functional Block Diagram of the XRT94L33 (whenever it has been configured to operate in the 3-Channel DS3/STS-1 to STS-3 Mapper Mode, with the Line-Interfacerelated blocks “High-lighted”. Tx TxSTS-3 STS-3 TOH TOHProcessor Processor Block Block Rx RxSTS-3 STS-3TOH TOH Processor Rx STS-3 Processor Rx STS-3TOH TOH Block Processor Block Block Processor Block (Primary) (Primary) STS-3 STS-3 Telecom TelecomBus Bus Block Block Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (Primary) (Primary) Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (APS) (APS) Tx TxSONET SONET POH POH Processor Processor Block Block Rx RxSONET SONET POH POH Processor Processor Block Block Rx RxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block Tx TxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block Rx RxSTS-1 STS-1 POH POH Block Block Rx RxSTS-1 STS-1 TOH TOH Block Block Tx TxSTS-1 STS-1 POH POH Block Block Tx TxSTS-1 STS-1 TOH TOH Block Block DS3/E3 DS3/E3 Jitter Jitter Attenuator Attenuator Block Block DS3/E3 DS3/E3 Framer Framer Block Block Channel 1 To Channels 2 – 3 From Channels 2 – 3 Clock ClockSynthesizer SynthesizerBlock Block Microprocessor MicroprocessorInterface Interface 107 JTAG JTAGTest TestPort Port XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1.3.1 Rev222...000...000 LINE INTERFACE CONTROL REGISTER Table 55: Line Interface Control Register – Address Map ADDRESS LOCATION REGISTER NAME DEFAULT VALUES 0x0302 Receive Line Interface Control Register – Byte 1 0x00 0x0303 Receive Line Interface Control Register – Byte 0 0x00 Reserved 0x00 Receive Line Status Register 0x00 Reserved 0x00 Receive Line Interrupt Register 0x00 Reserved 0x00 Receive Line Interrupt Enable Register 0x00 Reserved 0x00 Transmit Line Interface Control Register 0x00 0x0304 – 0x0306 0x0307 0x0308 -0x030A 0x030B 0x030C – 0x030E 0x030F 0x0310 – 0x0382 0x0383 108 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 LINE INTERFACE CONTROL REGISTER DESCRIPTION 1.3.2 Table 56: Receive Line Interface Control Register – Byte 1 (Address Location= 0x0302) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused STS-3 Loop-timing Mode Split Loop Back Unused Remote Serial Loop Back Unused Analog Local Loop Back Enable Digital Local Loop Back Enable R/W R/W R/W R/O R/W R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 STS-3 Loop Timing Mode R/W DESCRIPTION STS-3 Loop-Timing Mode: This READ/WRITE bit-field permits the user to configure the 94L33 to operate in the Loop-timing Mode. If the user implements this configuration, then the following Transmit STS-3-related functional blocks will use the “Recovered Clock” (Receive STS-3 timing) as its timing source. • All three (3) Transmit SONET POH Processor blocks • The Transmit STS-3c POH Processor block (if enabled) • The Transmit STS-3 TOH Processor block • The Transmit STS-3 PECL Interface block • The Transmit STS-3 Telecom Bus Interface Block. 0 – Configures all of the Transmit STS-3 circuitry to operate in the “LocalTiming” Mode (e.g., the above-mentioned functional blocks will use the Clock Synthesizer block as its timing source). 1 – Configures the Transmit STS-3 circuitry to operate in the “Loop-Timing” Mode. 5 Split Loop Back R/W Split Loop-back Enable: This READ/WRITE bit-field permits the user to configure the 94L33 to operate in the “Split Loop-back” Mode. If the user implements this configuration, then two types of loop-backs will exist within the chip simultaneously. a. A Local Loop-back This loop-back path will originate from the Transmit STS-3 TOH Processor block. It will be routed through a portion of the “Transceiver circuitry” (through the “Transmit Parallel-to-Serial Converter” block) and then back to the “Receive Serial-to-Parallel Converter” block, before being routed to the Receive STS-3 TOH Processor block. b. A Remote Loop-back This loop-back path will originate from the Receive STS-3/STM-1 PECL Interface input. It will be routed through the CDR (Clock & Data Recovery) block; before being routed to the Transmit STS-3/STM-1 PECL Interface output. 0 – Configures the 94L33 to NOT operate in the Split Loop-back Mode 1 – Configures the 94L33 to operate in the Split Loop-back Mode 109 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 4 Unused 3 Remote Serial Loop Back Rev222...000...000 R/W Remote Serial Loop-back Enable: This READ/WRITE bit-field permits the user to configure the 94L33 to operate in the “Remote Serial Loop-back” Mode. In this mode, the incoming (Received Data) will enter the device via the Receive STS3/STM-1 PECL Interface Input. This signal will then be processed via the CDR (Clock and Data Recovery) Block. At this point, this input signal will proceed via two paths in parallel. In one path, the signal will proceed onto the “Receive Serial-to-Parallel” Converter and then the Receive STS-3 TOH Processor block (and so on). The other path will not proceed through the “Receive Serial-to Parallel” Converter block. Instead this signal will proceed on towards the “Transmit STS-3/STM-1 PECL Interface Output, thereby completing the loop-back path. 0 – Configures the 94L33 to NOT operate in the Remote Serial Loop-back Mode. 1 – Configures the 94L33 to operate in the Remote Serial Loop-back Mode. 2 Unused R/O 1 Analog Local Loop Back Enable R/W Analog Local Loop Back: This READ/WRITE bit field permits the user to configure the 94L33 to operate in the “Analog Local Loop Back” Mode. If the user implements this configuration, analog local loop back including data and clock recovery will be enabled. 0 – Analog local loop back is disabled 1 – Analog local loop back is enabled 0 Digital Local Loop Back Enable R/W Digital Local Loop Back: This READ/WRITE bit field permits the user to configure the 94L33 to operate in the “Digital Local Loop Back” Mode. If the user implements this configuration, digital local loop back NOT including data and clock recovery will be enabled. 0 – Digital local loop back is disabled 1 – Digital local loop back is enabled 110 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 57: Receive Line Interface Control Register – Byte 0 Address Location= 0x0303) BIT 7 BIT 6 BIT 5 Primary Receive STS3/STM-1 PECL Interface Module Power Down Redundant Receive STS3/STM-1 PECL Interface Module Power Down Force Training Mode Upon LOS R/W R/W R/W R/O R/O 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Primary Receive STS-3/STM-1 PECL Interface Module Power Down R/W BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/W 0 0 0 Unused DESCRIPTION Primary Receive STS-3/STM-1 PECL Interface Module Power Down: This READ/WRITE bit field permits the user to power down the Primary Receive STS-3/STM-1 PECL Interface Port as described below. 0 – Powers on Primary Receive STS-3/STM-1 PECL Interface block. 1 – Powers down the Primary Receive STS-3/STM-1 PECL Interface block. In this mode, the user will not be able to receive STS-3/STM-1 data via the Primary Receive PECL Interface port. NOTE: If the user wishes to configure the XRT94L33 device to receive STS-3/STM-1 data via the Primary Receive STS-3/STM-1 PECL Interface port, then he/she MUSTset this bit-field to “0”. 6 Redundant Receive STS3/STM-1 PECL Interface Module Power Down R/W Redudant Receive STS-3/STM-1 PECL Interface Module Power Down: This READ/WRITE bit field permits the user to power down the Redundant Receive STS-3/STM-1 PECL Interface Port as described below. 0 – Powers on the Redundant Receive STS-3/STM-1 PECL Interface block. 1 – Powers down the Redundant Receive STS-3/STM-1 PECL Interface block. In this mode, the user will not be able to receive STS-3/STM-1 data via the Redundant Receive PECL Interface port. NOTE: If the user wishes to configure the XRT94L33 device to receive STS-3/STM-1 data via the Redundant Receive STS-3/STM-1 PECL Interface port, then he/she MUST set this bit-field to “0”. 5 Force Training Mode Upon LOS R/W Force Training Mode Upon LOS: This READ/WRITE bit field permits the user to configure the Receive STS3/STM-1 PECL Interface – CDR (Clock and Data Recovery) phase lock loop to stay in training mode as long as the external LOS is asserted. If the user implements this feature, then the Receive STS-3/STM-1 PECL Interface block CDR PLL will lock onto a clock signal that is ultimately derived from the REFCLK input pin and remain locked onto this signal for the duration that the Receive STS-3/STM-1 PECL Interface block is declaring the LOS_Detect condition. 0 – Receive Line Interface PLL will NOT stay in training mode 1 – Receive Line Interface PLL will stay in training mode 4-0 Unused R/O 111 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 58: Receive Line Interface Status Register (Address Location= 0x0307) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 Clock Lock Status Loss of Signal Status Redundant Receiver Clock Lock Status Redundant Receiver Loss of Signal Status R/W R/O R/O R/O RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Unused R/O 3 Clock Lock Status RUR DESCRIPTION Clock Lock Status: This RESET-upon-READ bit field indicates whether or not the clock lock status is detected by transceiver 0 – Indicates clock lock is NOT detected by transceiver 1 – Indicates clock lock is detected by transceiver 2 Loss of Signal Status RUR Loss of Signal Status: This RESET-upon-READ bit field indicates whether or not the loss of signal status is detected by transceiver 0 – Indicates loss of signal is NOT detected by transceiver 1 – Indicates loss of signal is detected by transceiver 1 Redundant Receiver Clock Lock Status RUR Redundant Receiver Clock Lock Status: This RESET-upon-READ bit field indicates whether or not the clock lock status is detected by redundant receiver 0 – Indicates clock lock is NOT detected by redundant receiver 1 – Indicates clock lock is detected by redundant receiver 0 Redundant Receiver Loss of Signal Status RUR Redundant Receiver Loss of Signal Status: This RESET-upon-READ bit field indicates whether or not the loss of signal status is detected by redundant receiver 0 – Indicates loss of signal is NOT detected by redundant receiver 1 – Indicates loss of signal is detected by redundant receiver 112 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 59: Receive Line Interface Interrupt Register (Address Location= 0x030B) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 Clock Lock Interrupt Loss of Signal Interrupt Redundant Receiver Clock Lock Interrupt Redundant Receiver Loss of Signal Interrupt R/W R/O R/O R/O RUR RUR R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Unused R/O 3 Clock Lock Interrupt RUR DESCRIPTION Clock Lock Interrupt: This RESET-upon-READ bit field indicates whether or not a clock lock interrupt has occurred. A clock lock interrupt occurs when the signal “Clock Lock Status” (address location: 0x0307) makes a “0” to “1” or “1” to “0” transition. 0 – Indicates clock lock interrupt is NOT declared. 1 – Indicates clock lock is declared 2 Loss of Signal Interrupt RUR Loss of Signal Interrupt: This RESET-upon-READ bit field indicates whether or not a loss of signal interrupt has occurred. A clock lock interrupt occurs when the signal “Loss of Signal Status” (Address Location: 0x0307) makes a “0” to “1” or “1” to “0” transition. 0 – Indicates a loss of signal interrupt is NOT declared. 1 – Indicates a loss of signal is declared 1 Redundant Receiver Clock Lock Interrupt RUR Redundant Receiver Clock Lock Interrupt: This RESET-upon-READ bit field indicates whether or not a clock lock interrupt has occurred in the redundant receiver block. A clock lock interrupt occurs when the signal “Clock Lock Status” (address location: 0x0307) makes a “0” to “1” or “1” to “0” transition. 0 – Indicates clock lock interrupt is NOT declared. 1 – Indicates clock lock is declared 0 Redundant Receiver Loss of Signal Interrupt RUR Redundant Receiver Loss of Signal Interrupt: This RESET-upon-READ bit field indicates whether or not a loss of signal interrupt has occurred in the redundant receiver block. A clock lock interrupt occurs when the signal “Loss of Signal Status” (Address Location: 0x0307) makes a “0” to “1” or “1” to “0” transition. 0 – Indicates a loss of signal interrupt is NOT declared. 1 – Indicates a loss of signal is declared 113 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 60: Receive Line Interface Interrupt Register (Address Location= 0x030F) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 Clock Lock Interrupt Enable Loss of Signal Interrupt Enable Redundant Receiver Clock Lock Interrupt Enable Redundant Receiver Loss of Signal Interrupt Enable R/W R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Unused R/O 3 Clock Lock Interrupt Enable R/W DESCRIPTION Clock Lock Interrupt Enable: This READ/WRITE bit field disables or enables the clock lock interrupt. 0 – Disables clock lock interrupt 1 – Enables clock lock interrupt 2 Loss of Signal Interrupt R/W Loss of Signal Interrupt Enable: This READ/WRITE bit field disables or enables the loss of signal interrupt. 0 – Disables loss of signal interrupt 1 – Enables loss of signal interrupt 1 Redundant Receiver Clock Lock Interrupt Enable R/W Redundant Receiver Clock Lock Interrupt Enable: This READ/WRITE bit field disables or enables the clock lock interrupt for the redundant receiver block. 0 – Disables clock lock interrupt 1 – Enables clock lock interrupt 0 Redundant Receiver Loss of Signal Interrupt R/W Redundant Receiver Loss of Signal Interrupt Enable: This READ/WRITE bit field disables or enables the loss of signal interrupt for the redundant receiver block. 0 – Disables loss of signal interrupt 1 – Enables loss of signal interrupt 114 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 61: Transmit Line Interface Control Register (Address Location= 0x0383) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Primary Transmit STS-3/STM1 PECL Interface Enable Transmit Clock Enable Clock Synthesizer Block as Timing Source Redundant Transmit STS-3/STM1 PECL Interface Block Enable Unused Unused R/W R/W R/W R/W R/O R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Primary Transmit STS-3/STM-1 PECL Interface Enable R/W BIT 1 BIT 0 REFCLKSEL[1:0] DESCRIPTION Primary Transmit STS-3/STM-1 PECL Interface Enable: This READ/WRITE bit field permits the user to enable or disable the Transmit STS-3/STM-1 PECL Interface output drivers as described below. 0 – Disables the Transmit STS-3/STM-1 PECL Interface output drivers. 1 – Enables the Transmit STS-3/STM-1 PECL Interface output drivers. NOTE: The user MUST set this bit-field to “1” in order to transmit any traffic via the Transmit STS-3/STM-1 PECL Interface output. 6 Transmit Clock Enable R/W Transmit Clock Enable: This READ/WRITE bit field permits the user to enable or disable the transmitter clock output. 0 – Disables transmitter clock output 1 – Enables transmitter clock output 5 Clock Synthesizer as Timing Source R/W Clock Synthesizer as Timing Source: This READ/WRITE bit field permits the user to select either the Clock Synthesizer block or the signal applied at the REFTTL input as the source of the Transmit 19.44MHz clock. 0 – This setting configures the “Transmit SONET” circuitry to by-pass the Clock Synthesizer block and to directly use the 19.44MHz clock signal (that is provided to the REFTTL input pin) as its timing source. In this case, the “Clock Synthesizer” block is by-passed. 1 – This setting configures the “Transmit SONET” circuitry to use the output of the Clock Synthesizer block as its timing source. NOTE: If the user opts to by-pass the Clock Synthesizer (by setting this register bit to “0”) then he/she MUST apply a 19.44MHz clock signal to the REFTTL input pin. 4 Redundant Transmit STS3/STM-1 PECL Interface Enable R/W Redundant Transmit STS-3/STM-1 PECL Interface Enable: This READ/WRITE bit field permits the user to enable or disable the Redundant Transmit STS-3/STM-1 PECL Interface output pads. If the user enables the “Redundant Transmit STS-3/STM-1 PECL Interface” block, then it will begin to transmit the exact same data as is the “Primary Transmit STS-3/STM-1 PECL Interface” block. 0 – Disables the Redundant Transmit STS-3/STM-1 PECL Interface block 1 – Enables the Redundant Transmit STS-3/STM-1 PECL Interface block 115 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 NOTE: If the user wishes to use the “Line APS” features within the XRT94L33 device, then he/she MUST enable the “Redundant Transmit STS-3/STM-1PECL Interface block. 3 Unused R/W Serial Loopback: This READ/WRITE bit field permits the user to enable or disable serial loopback. 0 – Disables Serial loopback 1 – Enables Serial loopback 2 Unused R/O 1-0 Clock Synthesizer Block Frequency Select[1:0] R/W Clock Synthesizer Block Frequency Select[1:0]: This READ/WRITE bit field permits the user to select the desired reference clock speed as follows: 00 = 19.44 MHz 01 = 38.88 MHz 10 = 51.85 MHz 11 = 77.76 MHz 116 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.4 RECEIVE STS-3 TOH PROCESSOR BLOCK The register map for the Receive STS-3 TOH Processor Block is presented in the Table below. Additionally, a detailed description of each of the “Receive STS-3 TOH Processor” Block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the “Receive STS-3 TOH Processor Block “highlighted” is presented below in Figure 2 Figure 2: Illustration of the Functional Block Diagram of the XRT94L33 (whenever it has been configured to operate in the 3-Channel DS3/STS-1 to STS-3 Mapper Mode), with the Receive STS-3 TOH Processor Block “High-lighted”. Tx TxSTS-3 STS-3 TOH TOHProcessor Processor Block Block Rx RxSTS-3 STS-3TOH TOH Processor Rx STS-3 Processor Rx STS-3TOH TOH Block Processor Block Block Processor Block (Primary) (Primary) STS-3 STS-3 Telecom TelecomBus Bus Block Block Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (Primary) (Primary) Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (APS) (APS) Tx TxSONET SONET POH POH Processor Processor Block Block Rx RxSONET SONET POH POH Processor Processor Block Block Rx RxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block Tx TxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block Rx RxSTS-1 STS-1 POH POH Block Block Rx RxSTS-1 STS-1 TOH TOH Block Block Tx TxSTS-1 STS-1 POH POH Block Block Tx TxSTS-1 STS-1 TOH TOH Block Block DS3/E3 DS3/E3 Jitter Jitter Attenuator Attenuator Block Block DS3/E3 DS3/E3 Framer Framer Block Block Channel 1 To Channels 2 – 3 From Channels 2 – 3 Clock ClockSynthesizer SynthesizerBlock Block Microprocessor MicroprocessorInterface Interface 117 JTAG JTAGTest TestPort Port XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTERS Table 62: Receive STS-3 TOH Processor Block Control Register – Address Map ADDRESS LOCATION 0x1000 – 0x1102 0x1103 REGISTER NAME DEFAULT VALUES Reserved Receive STS-3 Transport Control Register – Byte 0 0x00 Reserved 0x00 0x1106 Receive STS-3 Transport Status Register – Byte 1 0x00 0x1107 Receive STS-3 Transport Status Register – Byte 0 0x02 0x1108 Reserved 0x00 0x1109 Receive STS-3 Transport Interrupt Status Register – Byte 2 0x00 0x110A Receive STS-3 Transport Interrupt Status Register – Byte 1 0x00 0x110B Receive STS-3 Transport Interrupt Status Register – Byte 0 0x00 0x110C Reserved 0x00 0x110D Receive STS-3 Transport Interrupt Enable Register – Byte 2 0x00 0x110E Receive STS-3 Transport Interrupt Enable Register – Byte 1 0x00 0x110F Receive STS-3 Transport Interrupt Enable Register – Byte 0 0x00 0x1110 Receive STS-3 Transport - B1 Byte Error Count Register – Byte 3 0x00 0x1111 Receive STS-3 Transport - B1 Byte Error Count Register – Byte 2 0x00 0x1112 Receive STS-3 Transport - B1 Byte Error Count Register – Byte 1 0x00 0x1113 Receive STS-3 Transport - B1 Byte Error Count Register – Byte 0 0x00 0x1114 Receive STS-3 Transport - B2 Byte Error Count Register – Byte 3 0x00 0x1115 Receive STS-3 Transport - B2 Byte Error Count Register – Byte 2 0x00 0x1116 Receive STS-3 Transport - B2 Byte Error Count Register – Byte 1 0x00 0x1117 Receive STS-3 Transport - B2 Byte Error Count Register – Byte 0 0x00 0x1118 Receive STS-3 Transport - REI-L Event Count Register – Byte 3 0x00 0x1119 Receive STS-3 Transport - REI-L Event Count Register – Byte 2 0x00 0x111A Receive STS-3 Transport - REI-L Event Count Register – Byte 1 0x00 0x111B Receive STS-3 Transport - REI-L Event Count Register – Byte 0 0x00 0x111E Reserved 0x00 0x111F Receive STS-3 Transport K1 Byte Value Register 0x00 Reserved 0x00 Receive STS-3 Transport K2 Byte Value Register 0x00 Reserved 0x00 Receive STS-3 Transport S1 Byte Value Register 0x00 0x1104 – 0x1105 0x1120 – 0x1122 0x1123 0x1124 – 0x1126 0x1127 118 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S ADDRESS LOCATION 0x1128 – 0x112A REGISTER NAME DEFAULT VALUES Reserved 0x00 Receive STS-3 Transport – In-Sync Threshold Value Register 0x00 Reserved 0x00 0x112E Receive STS-3 Transport – LOS Threshold Value – MSB 0xFF 0x112F Receive STS-3 Transport – LOS Threshold Value – LSB 0xFF 0x1130 Reserved 0x00 0x1131 Receive STS-3 Transport – SF Set Monitor Interval – Byte 2 0x00 0x1132 Receive STS-3 Transport – SF Set Monitor Interval – Byte 1 0x00 0x1133 Receive STS-3 Transport – SF Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0x1136 Receive STS-3 Transport – SF Set Threshold – Byte 1 0x00 0x1137 Receive STS-3 Transport – SF Set Threshold – Byte 0 0x00 Reserved 0x00 0x113A Receive STS-3 Transport – SF Clear Threshold – Byte 1 0x00 0x113B Receive STS-3 Transport – SF Clear Threshold – Byte 0 0x00 0x113C Reserved 0x00 0x113D Receive STS-3 Transport – SD Set Monitor Interval – Byte 2 0x00 0x113E Receive STS-3 Transport – SD Set Monitor Interval – Byte 1 0x00 0x113F Receive STS-3 Transport – SD Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0x1142 Receive STS-3 Transport – SD Set Threshold – Byte 1 0x00 0x1143 Receive STS-3 Transport – SD Set Threshold – Byte 0 0x00 Reserved 0x00 0x1146 Receive STS-3 Transport – SD Clear Threshold – Byte 1 0x00 0x1147 Receive STS-3 Transport – SD Clear Threshold – Byte 0 0x00 Reserved 0x00 Receive STS-3 Transport – Force SEF Condition 0x00 Reserved 0x00 Receive STS-3 Transport – Receive Section Trace Message Buffer Control Register 0x00 Reserved 0x00 0x1152 Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 1 0x00 0x1153 Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 0 0x00 0x112B 0x112C, 0x112D 0x1134 – 0x1135 0x1138, 0x1139 0x1140, 0x1141 0x1144, 0x1145 0x1148 – 0x114A 0x114B 0x114C, 0x114E 0x114F 0x1150, 0x1151 119 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM ADDRESS LOCATION 0x1154, 0x1155 REGISTER NAME Rev222...000...000 DEFAULT VALUES Reserved 0x00 0x1156 Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 1 0x00 0x1157 Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 0 0x00 0x1158 Reserved 0x00 0x1159 Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 2 0xFF 0x115A Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1 0xFF 0x115B Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0 0xFF 0x115C Reserved 0x00 0x115D Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2 0xFF 0x115E Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1 0xFF 0x115F Receive STS-3 Transport – Receive SF Clear Monitor – Byte 0 0xFF Reserved 0x00 Receive STS-3 Transport – Auto AIS Control Register 0x00 Reserved 0x00 Receive STS-3 Transport – Serial Port Control Register 0x00 Reserved 0x00 Receive STS-3 Transport – Auto AIS (in Downstream STS-1s) Control Register 0x000 0x1160 – 0x1162 0x1163 0x1164 – 0x1166 0x1167 0x1168 – 0x116A 0x116B 0x116C – 0x1179 Reserved 0x117A Receive STS-3 Transport – TOH Capture Indirect Address 0x00 0x117B Receive STS-3 Transport – TOH Capture Indirect Address 0x00 0x117C Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x117D Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x117E Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x117F Receive STS-3 Transport – TOH Capture Indirect Data 0x00 Reserved 0x00 0x1180 – 0x11FF 120 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.4.1 RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER DESCRIPTION Table 63: Receive STS-3 Transport Control Register – Byte 0 (Address Location= 0x1103) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STS-N OH Extract SF Defect Condition Detect Enable SD Defect Condition Detect Enable Descramble Disable SDH/ SONET* REI-L Error Type B2 Error Type B1 Error Type R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 STS-N OH Extract R/W DESCRIPTION STS-N Overhead Extract (Revision C Silicon Only): This READ/WRITE bit-field permits the user to configure the RxTOH output port to output the TOH for all lower-tributary STS-1s within the incoming STS-3 signal. 0 – Disables this feature. In this mode, the RxTOH output port will only output the TOH for the first STS-1 within the incoming STS-3 signal. 1 – Enables this feature. 6 SF Defect Condition Detect Enable R/W Signal Failure (SF) Defect Condition Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SF Defect Declaration and Clearance by the Receive STS-3 TOH Processor Block, as described below. 0 – Configures the Receive STS-3 TOH Processor block to NOT declare nor clear the SF defect condition per the “user-specified” SF defect declaration and clearance criteria. 1 – Configures the Receive STS-3 TOH Processor block to declare and clear the SF defect condition per the “user-specified” SF defect declaration and clearance” criteria. NOTE: The user must set this bit-field to “1” in order to permit the Receive STS-3 TOH Processor block to declare and clear the SF defect condition. 5 SD Defect Condition Detect Enable R/W Signal Degrade (SD) Defect Condition Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SD Declaration and Clearance by the Receive STS-3 TOH Processor Block as described below. 0 – Configures the Receive STS-3 TOH Processor blolck to NOT declare nor clear the SD defect condition per the “user-specified” SD defect declaration and clearance criteria.. 1 – Configures the Receive STS-3 TOH Processor block to declare and clear the SD defect condition per the “user-specified SD defect declaration and clearance” critieria. NOTE: The user must set this bit-field to “1” in order to permit the Receive STS-3 TOH Processor block to declare and clear the SD defect condition. 4 Descramble Disable R/W De-Scramble Disable: This READ/WRITE bit-field permits the user to either enable or disable descrambling by the Receive STS-3 TOH Processor block. 0 – De-Scrambling is enabled. 121 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 1 – De-Scrambling is disabled. 3 SDH/SONET* R/W SDH/SONET Select: This READ/WRITE bit-field permits the user to configure the XRT94L33 device to operate in either the SONET or SDH Mode. 0 – Configures the XRT94L33 device to operate in the SONET Mode. 1 – Configures the XRT94L33 device to operate in the SDH Mode. 2 REI-L Error Type R/W REI-L (Line – Remote Error Indicator) Error Type: This READ/WRITE bit-field permits the user to specify how the Receive STS-3 TOH Processor block will count (or tally) REI-L events, for Performance Monitoring purposes. The user can configure the Receive STS-3 TOH Processor block to increment REI-L events on etiher a “per-bit” or “per-frame” basis. If the user configures the Receive STS-3 TOH Processor block to increment REI-L events on a “per-bit” basis, then it will increment the “Receive STS-3 Transport REI-L Event Count” register by the contents within the M1 byte of the incoming STS-3 data-stream. If the user configures the Receive STS-3 TOH Processor block to increment REI-L events on a “per-frame” basis, then it will increment the “Receive STS-3 Transport REI-L Event Count” register each time it receives an STS-3 frame, in which the M1 byte is set to a “non-zero” value. 0 – Configures the Receive STS-3 TOH Processor block to count or tally REI-L events on a per-bit basis. 1 – Configures the Receive STS-3 TOH Processor block to count or tally REI-L events on a per-frame basis. 1 B2 Error Type R/W B2 Error Type: This READ/WRITE bit-field permits the user to specify how the “Receive STS-3 TOH Processor block will count (or tally) B2 byte errors, for Performance Monitoring purposes. The user can configure the Receive STS-3 TOH Processor block to increment B2 byte errors on either a “perbit” or a “per-frame” basis. If the user configures the Receive STS-3 TOH Processor block to increment B2 byte errors on a “per-bit” basis, then it will increment the Receive STS-3 Transport - B2 Byte Error Count” register by the number of bits (within each of the three B2 byte values) that is in error. If the user configures the Receive STS-3 TOH Processor block to increment B2 byte errors on a “per-frame” basis, then it will increment the “Receive STS-3 Transport - B2 Byte Error Count” Register, each time it receives an STS-3 frame that contains at least one erred B2 byte. 0 – Configures the Receive STS-3 TOH Processor block to count B2 byte errors on a “per-bit” basis. 1 – Configures the Receive STS-3 TOH Processor block to count B2 byte errors on a “per-frame” basis. 0 B1 Error Type R/W B1 Error Type: This READ/WRITE bit-field permits the user to specify how the Receive STS-3 TOH Processor block will count (or tally) B1 byte errors, for Performance Monitoring purposes. The user can configure the Receive STS-3 TOH Processor block to increment B1 byte errors on either a “perbit” or “per-frame” basis. If the user configures the Receive STS-3 TOH Processor block to increment B1 byte errors on a “per-bit” basis, then it will increment the “Receive Transport B1 Error Count” register by the number of bits (within the B1 byte value) that is in error. If the user configures the Receive STS-3 TOH Processor block to increment B1 byte errors on a “per-frame” basis, then it will increment the 122 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S “Receive STS-3 Transport - B1 Byte Error Count” Register each time it receives an STS-3 frame that contains an erred B1 byte. 0 – Configures the Receive STS-3 TOH Processor block to count B1 byte errors on a “per-bit” basis. 1 – Configures the Receive STS-3 TOH Processor block to count B1 byte errors on a “per-frame” basis. 123 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 64: Receive STS-3 Transport Status Register – Byte 1 (Address Location= 0x1106) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 Section Trace Message Mismatch Defect Declared Section Trace Message Unstable Defect Declared AIS-L Defect Declared R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–3 Unused R/O 2 Section Trace Message Mismatch Defect Declared R/O DESCRIPTION Section Trace Message Mismatch Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the Section Trace Mismatch defect condition within the incoming STS-3 data-stream. The Receive STS-3 TOH Processor block will declare the Section Trace Message Mismatch defect condition, whenever it accepts a Section Trace Message (via the J0 byte, within the incoming STS-3 data-stream) that differs from the “Expected Section Trace Message”. 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the Section Trace Message Mismatch Defect Condition. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring the Section Trace Message Mismatch Defect Condition. 1 Section Trace Message Unstable Defect Declared R/O Section Trace Message Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the Section Trace Message Unstable Defect condition. The Receive STS-3 TOH Processor block will declare the Section Trace Message Unstable defect condition, whenever the “Section Trace Message Unstable” counter reaches the value 8. The Receive STS-3 TOH Processor block will increment the “Section Trace Message Unstable” counter each time that it receives a Section Trace message that differs from the previously received Section Trace Message”. The Receive STS-3 TOH Processor block will clear the “Section Trace Message Unstable” counter to “0” whenever it has received a given Section Trace Message 3 (or 5) consecutive times. Note: The Receive STS-3 TOH Processor block will also clear the “Section Trace Message Unstable” defect condition” once it has received a given Section Trace Message 3 (or 5) consecutive times. 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the Section Trace Message Unstable defect condition. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring the Section Trace Message Unstable defect condition. 0 AIS-L Defect Declared R/O AIS-L Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the AIS-L (Line AIS) defect condition within the incoming STS-3 data stream. The Receive STS-3 TOH Processor block will declare the AIS-L defect condition within the incoming STS-3 data stream if bits 6, 7 and 8 (e.g., the Least Significant Bits, within the K2 byte) are set to the value “[1, 1, 1]” for five consecutive STS-3 124 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S frames. 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the AIS-L defect condition. 1 – Indicates that the Receive STS-3 TOH Processor block currently declaring the AIS-L defect condition. 125 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 65: Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1107) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RDI-L Defect Declared S1 Byte Unstable Defect Declared K1, K2 Byte Unstable Defect Declared SF Defect Declared SD Defect Declared LOF Defect Declared SEF Defect Declared LOS Defect Declared R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 RDI-L Defect Declared R/O DESCRIPTION RDI-L (Line Remote Defect Indicator) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the RDI-L defect condition within the incoming STS-3 signal. The Receive STS-3 TOH Processor block will declare the RDI-L defect condition whenever it determines that bits 6, 7 and 8 (e.g., the three least significant bits) of the K2 byte contains the “1, 1, 0” pattern in 5 consecutive incoming STS-3 frames. 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the RDI-L defect condition. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring the RDI-L defect condition. 6 S1 Byte Unstable Defect Declared R/O S1 Byte Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the “S1 Byte Unstable” defect condition. The Receive STS-3 TOH Processor block will declare the “S1 Byte Unstable” defect condition whenever the “S1 Byte Unstable Counter” reaches the value 32. The Receive STS-3 TOH Processor block will increment the “S1 Byte Unstable Counter” each time that it receives an STS-3 frame that contains an S1 byte that differs from the previously received S1 byte. The Receive STS-3 TOH Processor block will clear the contents of the “S1 Byte Unstable Counter” to “0” whenever it receives the same S1 byte for 8 consecutive STS-3 frames. 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the “S1 Byte Unstable Defect Condition. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring “S1 Byte Unstable Defect Condition. 5 K1, K2 Byte Unstable Defect Declared R/O K1, K2 Byte Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the “K1, K2 Byte Unstable” defect condition. The Receive STS-3 TOH Processor block will declare the “K1, K2 Byte Unstable” defect condition whenever it fails to receive the same set of K1, K2 bytes, in 12 consecutive STS-3 frames. The Receive STS-3 TOH Processor block will clear the “K1, K2 Byte Unstable” defect condition whenever it receives a given set of K1, K2 byte values within three consecutive STS-3 frames. 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the K1, K2 Byte Unstable Defect Condition. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring the K1, K2 Byte Unstable Defect Condition. 4 SF Defect Declared R/O SF (Signal Failure) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH 126 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Processor block is currently declaring the SF defect condition. The Receive STS-3 TOH Processor block will declare the SF defect condition anytime it has determined that the number of B2 byte errors (measured over a user-selected period of time) exceeds a certain “user-specified B2 Byte Error” threshold. 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the SF Defect condition. This bit is set to “0” when the number of B2 byte errors (accumulated over a given interval of time) does not exceed the “SF Defect Declaration” threshold. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring the SF Defect condition. This bit is set to “1” when the number of B2 byte errors (accumulated over a given interval of time) does exceed the “SF Defect Declaration” threshold. 3 SD Defect Declared R/O SD (Signal Degrade) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the SD defect condition. The Receive STS-3 TOH Processor block will declare the SD defect condition anytime it has determined that the number of B2 byte errors (measured over a user-selected period of time) exceeds a certain “user-specified B2 Byte Error” threshold. 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the SD Defect condition. This bit is set to “0” when the number of B2 byte errors (accumulated over a given interval of time) does not exceed the “SD Defect Declaration” threshold. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring the SD Defect condition. This bit is set to “1” when the number of B2 byte errors (accumulated over a given interval of time) does exceed the “SD Defect Declaration” threshold. 2 LOF Defect Declared R/O LOF (Loss of Frame) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the LOF defect condition. The Receive STS-3 TOH Processor block will declare the LOF defect condition, if it has been declaring the SEF (Severely Errored Frame) defect condition for 3ms (or 24 SONET frame periods). 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the LOF defect condition. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring the LOF defect condition. 1 SEF Defect Declared R/O SEF (Severely Errored Frame) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the SEF defect condition. The Receive STS-3 TOH Processor block will declare the SEF defect condition if the “SEF Declaration Criteria”; per the settings of the FRPATOUT[1:0] bits, within the Receive STS-3 Transport – In-Sync Threshold Value Register (Address Location= 0x112B) are met. 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the SEF defect condition. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring the SEF defect condition. 0 LOS Defect Declared R/O LOS (Loss of Signal) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH Processor block is currently declaring the LOS (Loss of Signal) defect condition. The Receive STS-3 TOH Processor block will declare the LOS defect condition if 127 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 it detects “LOS_THRESHOLD[15:0]” consecutive “All Zero” bytes in the incoming STS-3 data stream. Note: The user can set the “LOS_THRESHOLD[15:0]” value by writing the appropriate data into the “Receive STS-3 Transport – LOS Threshold Value” Register (Address Location= 0x112E and 0x112F). 0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently declaring the LOS defect condition. 1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring the LOS defect condition. 128 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 66: Receive STS-3 Transport Interrupt Status Register – Byte 2 (Address Location= 0x1109) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 Change of AIS-L Defect Condition Interrupt Status Change of RDI-L Defect Condition Interrupt Status R/O R/O R/O R/O R/O R/O RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-2 Unused R/O 1 Change of AIS-L Defect Condition Interrupt Status RUR DESCRIPTION Change of AIS-L (Line AIS) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of AIS-L Defect Condition” interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following occurrences. • Whenever the Receive STS-3 TOH Processor block declares the AIS-L defect condition. • Whenever the Receive STS-3 TOH Processor block clears the AIS-L defect condition. 0 – Indicates that the “Change of AIS-L Defect Condition” interrupt has not occurred since the last read of this register. 1 – Indicates that the “Change of AIS-L Defect Condition” interrupt has occurred since the last read of this register. Note: 0 Change of RDI-L Defect Condition Interrupt Status RUR The user can determine if the Receive STS-3 TOH Processor block is currently declaring the AIS-L defect condition by reading the contents of Bit 0 (AIS-L Defect Declared) within the “Receive STS3 Transport Status Register – Byte 1” (Address Location = 0x1106). Change of RDI-L (Line - Remote Defect Indicator) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of RDI-L Defect Condition” interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following occurrences. • Whenever the Receive STS-3 TOH Processor block declares the RDI-L defect condition. • Whenever the Receive STS-3 TOH Processor block clears the RDI-L defect condition. 0 – Indicate that the “Change of RDI-L Defect Condition” interrupt has not occurred since the last read of this register. 1 – Indicates that the “Change of RDI-L Defect Condition” interrupt has occurred since the last read of this register. Note: The user can determine if the Receive STS-3 TOH Processor block is currently declaring the RDI-L defect condition by reading out the state of Bit 7 (RDI-L Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0” (Address Location = 0x1107). I 129 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 67: Receive STS-3 Transport Interrupt Status Register – Byte 1 (Address Location = 0x110A) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 New S1 Byte Interrupt Status Change in S1 Byte Unstable Defect Condition Interrupt Status Change in Section Trace Message Unstable Defect Condition Interrupt Status New Section Trace Message Interrupt Status Change in Section Trace Message Mismatch Defect Condition Interrupt Status Receive TOH CAP DONE Interrupt Status Change in K1, K2 Bytes Unstable Defect Condition Interrupt Status NEW K1K2 Byte Value Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 New S1 Byte Value Interrupt Status RUR DESCRIPTION New S1 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New S1 Byte Value” Interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate the “New S1 Byte Value” Interrupt, anytime it has “accepted” a new S1 byte, from the incoming STS-3 data-stream. 0 – Indicates that the “New S1 Byte Value” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New S1 Byte Value” interrupt has occurred since the last read of this register. Note: 6 Change in S1 Byte Unstable Defect Condition Interrupt Status RUR The user can obtain the value for this most recently accepted value of the S1 byte by reading the “Receive STS-3 Transport S1 Byte Value” register (Address Location= 0x1127). Change in S1 Byte Unstable Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in S1 Byte Unstable Defect Condition” Interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the “S1 Byte Unstable” defect condition. • Whenever the Receive STS-3 TOH Processor block clears the “S1 Byte Unstable” defect condition. 0 – Indicates that the “Change in S1 Byte Unstable Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in S1 Byte Unstable Defect Condition” Interrupt has occurred since the last read of this register. Note: 5 Change in Section Trace Message Unstable Defect Condition Interrupt Status RUR The user can determine if the Receive STS-3 TOH Processor block is currently declaring the “S1 Byte Unstable” Defect condition by reading the contents of Bit 6 (S1 Byte Unstable Condition Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0” (Address Location = 0x1107). Change in Section Trace Message Unstable Defect condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in Section Trace Message Unstable” defect condition interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor 130 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Interrupt Status block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the “Section Trace Message Unstable” defect condition. • Whenever the Receive STS-3 TOH Processsor block clears the “Section Trace Message Unstable” defect condition. 0 – Indicates that the “Change in Section Trace Message Unstable defect” condition interrupt has not occurred since the last read of this register. 1 – Indicates that the “Change in Section Trace Message Unstable defect” condition interrupt has occurred since the last read of this register. 4 New Section Trace Message Interrupt Status RUR New Section Trace Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New Section Trace Message” interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt anytime it has accepted a new “Section Trace” Message within the incoming STS-3 data-stream. 0 – Indicates that the “New Section Trace Message Interrupt” has not occurred since the last read of this register. 1 – Indicates that the “New Section Trace Message Interrupt” has occurred since the last read of this register. Note: 3 Change in Section Trace Message Mismatch Defect Condition Interrupt Status RUR The user can read out the contents of the “Receive Section Trace Message Buffer”, which is located at Address location 0x1300 through 0x133F. Change in Section Trace Message Mismatch Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in Section Trace Message Mismatch Defect Condition” interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the “Section Trace Message Mismatch” defect condition. • Whenever the Receive STS-3 TOH Processor block clears the “Section Trace Message Mismatch” defect condition. 0 – Indicates that the “Change in Section Trace Message Mismatch Defect Condition” interrupt has not occurred since the last read of this register. 1 – Indicates that the “Change in Section Trace Message Mismatch Defect Condition” interrupt has occurred since the last read of this register. Note: 2 Receive TOH CAP DONE Interrupt Status RUR The user can determine whether the Receive STS-3 TOH Processor block is currently declaring the “Section Trace Message Mismatch” defect condition by reading the state of Bit 2 (Section Trace Message Mismatch Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 1 (Address Location = 0x1106). Receive TOH Capture DONE – Interrupt Status: This RESET-upon-READ bit-field indicates whether the “Receive TOH Data Capture” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3 TOH Processor block will generate an interrupt anytime it has captured the last TOH byte into the Capture Buffer. Note: Once the TOH (of a given STS-3 frame) has been captured and loaded into the “Receive TOH Capture” buffer, it will remain there 131 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 for one SONET frame period. 0 – Indicates that the “Receive TOH Data Capture” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Receive TOH Data Capture” Interrupt has occurred since the last read of this register. 1 Change in K1, K2 Byte Unstable Defect Condition Interrupt Status RUR Change of K1, K2 Byte Unstable Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in K1, K2 Byte Unstable Defect Condition” interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the “K1, K2 Byte Unstable Defect” condition. • Whenever the Receive STS-3 TOH Processor block clears the “K1, K2 Byte Unstable Defect” condition. 0 – Indicates that the “Change of K1, K2 Byte Unstable Defect Condition” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of K1, K2 Byte Unstable Defect Condition” interrupt has occurred since the last read of this register. Note: 0 New K1, K2 Byte Value Interrupt Status RUR The user can determine if the Receive STS-3 TOH Processor block is currently declaring the “K1, K2 Byte Unstable Defect Condition” by reading out the contents of Bit 5 (K1, K2 Byte Unstable Defect Declared), within the “Receive STS-3 Transport Status Register – Byte 0” (Address Location = 0x1107). New K1, K2 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New K1, K2 Byte Value” Interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt whenever it has “accepted” a new set of K1, K2 byte values from the incoming STS-3 data-stream. 0 – Indicates that the “New K1, K2 Byte Value” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New K1, K2 Byte Value” Interrupt has occurred since the last read of this register. Note: The user can obtain the contents of the new K1 byte by reading out the contents of the “Receive STS-3 Transport K1 Byte Value” Register (Address Location= 0x111F). Further, the user can also obtain the contents of the new K2 byte by reading out the contents of the “Receive STS-3 Transport K2 Byte Value” Register (Address Location= 0x1123). 132 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 68: Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address Location= 0x110B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Change in SF Defect Condition Interrupt Status Change in SD Defect Condition Interrupt Status Detection of REI-L Event Interrupt Status Detection of B2 Byte Error Interrupt Status Detection of B1 Byte Error Interrupt Status Change of LOF Defect Condition Interrupt Status Change of SEF Defect Condition Interrupt Status Change of LOS Defect Condition Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Change in SF Defect Condition Interrupt Status RUR DESCRIPTION Change of Signal Failure (SF) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of SF Defect Condition Interrupt” has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the SF Defect Condition. • Whenever the Receive STS-3 TOH Processor block clears the SF Defect Condition. 0 – Indicates that the “Change of SF Defect Condition Interrupt” has NOT occurred since the last read of this register. 1 – Indicates that the “Change of SF Defect Condition Interrupt” has occurred since the last read of this register. Note: 6 Change of SD Defect Condition Interrupt Status RUR The user can determine whether or not the Receive STS-3 TOH Processor block is currently declaring the “SF” defect condition by reading out the state of Bit 4 (SF Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1107). Change of Signal Degrade (SD) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of SD Defect Condition Interrupt” has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the SD Defect Condition. • Whenever the Receive STS-3 TOH Processor block clears the SD Defect Condition. 0 - Indicates that the “Change of SD Defect Condition Interrupt” has NOT occurred since the last read of this register. 1 – Indicates that the “Change of SD Defect Condition Interrupt” has occurred since the last read of this register. Note: 5 Detection of REIL Event Interrupt Status RUR The user can determine whether or not the Receive STS-3 TOH Processor block is declaring the “SD” defect condition by reading out the state of Bit 3 (SD Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1107). Detection of REI-L (Line – Remote Error Indicator) Event Interrupt Status: 133 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Status Rev222...000...000 This RESET-upon-READ bit-field indicates whether or not the “Detection of REI-L Event” Interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt anytime it detects an REI-L event within the incoming STS-3 data-stream. 0 – Indicates that the “Detection of REI-L Event” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of Line – REI-L Event” Interrupt has occurred since the last read of this register. 4 Detection of B2 Byte Error Interrupt Status RUR Detection of B2 Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of B2 Byte Error Interrupt” has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt anytime it detects a B2 byte error within the incoming STS-3 data-stream. 0 – Indicates that the “Detection of B2 Byte Error Interrupt” has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of B2 Byte Error Interrupt” has occurred since the last read of this register. 3 Detection of B1 Byte Error Interrupt Status RUR Detection of B1 Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of B1 Byte Error Interrupt” has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt anytime it detects a B1 byte error within the incoming STS-3 data-stream. 0 – Indicates that the “Detection of B1 Byte Error Interrupt” has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of B1 Byte Error Interrupt” has occurred since the last read of this register 2 Change of LOF Defect Condition Interrupt Status RUR Change of Loss of Frame (LOF) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of LOF Defect Condition” interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the LOF defect condition. • Whenever the Receive STS-3 TOH Processor block clears the LOF defect condition. 0 – Indicates that the “Change of LOF Defect Condition” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of LOF Defect Condition” interrupt has occurred since the last read of this register. Note: 1 Change of SEF Defect Condition Interrupt Status RUR The user can determine whether or not the Receive STS-3 TOH Processor block is currently declaring the LOF defect condition by reading out the state of Bit 2 (LOF Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1107). Change of SEF Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of SEF” Defect Condition Interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the SEF 134 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S defect condition. • Whenever the Receive STS-3 TOH Processor block clears the SEF defect condition. 0 – Indicates that the “Change of SEF Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of SEF Defect Condition” Interrupt has occurred since the last read of this register. Note: 0 Change of LOS Defect Condition Interrupt Status RUR The user can determine whether or not the Receive STS-3 TOH Processor block is currently declaring the SEF defect condition by reading out the state of Bit 1 (SEF Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1107). Change of Loss of Signal (LOS) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of LOS Defect Condition” interrupt has occurred since the last read of this register. The Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the LOS defect condition. • Whenever the Receive STS-3 TOH Processor block clears the LOS defect condition. 0 – Indicates that the “Change of LOS Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of LOS Defect Condition” Interrupt has occurred since the last read of this register. Note: The user can determine whether or not the Receive STS-3 TOH Processor block is currently declaring the LOS defect condition by reading out the contents of Bit 0 (LOS Defect Declared) within the Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1107). 135 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 69: Receive STS-3 Transport Interrupt Enable Register – Byte 2 (Address Location= 0x110D) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 Change of AIS-L Defect Condition Interrupt Enable Change of RDI-L Defect Condition Interrupt Enable R/O R/O R/O R/O R/O R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–2 Unused R/O 1 Change of AIS-L Defect Condition Interrupt Enable R/W DESCRIPTION Change of AIS-L (Line AIS) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of AIS-L Defect Condition” interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3 TOH Processor block declares the “AIS-L” defect condition. • Whenever the Receive STS-3 TOH Processor block clears the “AIS-L” defect condition. 0 – Disables the “Change of AIS-L Defect Condition” Interrupt. 1 – Enables the “Change of AIS-L Defect Condition” Interrupt. Note: 0 Change of RDI-L Defect Condition Interrupt Enable R/W The user can determine if the Receive STS-3 TOH Processor block is currently declaring the AIS-L defect condition by reading out the state of Bit 0 (AIS-L Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 1” (Address Location= 0x1106). Change of RDI-L (Line Remote Defect Indicator) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of RDI-L Defect Condition” interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3 TOH Processor block declares the “RDI-L” defect condition. • Whenever the Receive STS-3 TOH Processor block clears the “RDI-L” defect condition. 0 – Disables the “Change of RDI-L Defect Condition” Interrupt. 1 – Enables the “Change of RDI-L Defect Condition” Interrupt. 136 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 70: Receive STS-3 Transport Interrupt Enable Register – Byte 1 (Address Location= 0x110E) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 New S1 Byte Interrupt Enable Change in S1 Byte Unstable Defect Condition Interrupt Enable Change in Section Trace Message Unstable State Interrupt Enable New Section Trace Message Interrupt Enable Change in Section Trace Message Mismatch Defect Condition Interrupt Enable Receive TOH CAP DONE Interrupt Enable Change in K1, K2 Byte Unstable Defect Condition Interrupt Enable NEW K1K2 Byte Value Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 New S1 Byte Value Interrupt Enable R/W DESCRIPTION New S1 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the “New S1 Byte Value” Interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new S1 byte value. The Receive STS-3 TOH Processor block will accept a new S1 byte after it has received it for 8 consecutive STS-3 frames. 0 – Disables the “New S1 Byte Value” Interrupt. 1 – Enables the “New S1 Byte Value” Interrupt. 6 Change in S1 Unstable Defect Condition Interrupt Enable R/W Change in S1 Byte Unstable Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in S1 Byte Unstable Defect Condition” Interrupt. If the user enables this bit-field, then the Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3 TOH Processor block declares the “S1 Byte Unstable” defect condition. • Whenever the Receive STS-3 TOH Processor block clears the “S1 Byte Unstable” defect condition. 0 – Disables the “Change in S1 Byte Unstable Defect Condition” Interrupt. 1 – Enables the “Change in S1 Byte Unstable Defect Condition” Interrupt. 5 Change in Section Trace Message Unstable Defect Condition Interrupt Enable R/W Change in Section Trace Message Unstable defect condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in Section Trace Message Unstable Defect Condition” Interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3 TOH Processor block declares the “Section Trace Message Unstable” defect condition. • Whenever the Receive STS-3 TOH Processor block clears the “Section Trace Message Unstable” defect condition. 0 – Disables the “Change in Section Trace Message Unstable Defect Condition” Interrupt. 1 – Enables the “Change in Section Trace Message Unstable Defect Condition” Interrupt. 4 New Section R/W New Section Trace Message Interrupt Enable: 137 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Trace Message Interrupt Enable Rev222...000...000 This READ/WRITE bit-field permits the user to enable or disable the “New Section Trace Message” interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new Section Trace Message. The Receive STS-3 TOH Processor block will accept a new Section Trace Message after it has received it 3 (or 5) consecutive times via the J0 byte within the incoming STS-3 data-stream. 0 – Disables the “New Section Trace Message” Interrupt. 1 – Enables the “New Section Trace Message” Interrupt. 3 Change in Section Trace Message Mismatch Defect Condition Interrupt Enable R/W Change in “Section Trace Message Mismatch Defect Condition” interrupt enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in Section Trace Message Mismatch Defect condition” interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the “Section Trace Message Mismatch” defect condition. • Whenever the Receive STS-3 TOH Processor block clears the “Section Trace Message Mismatch” defect condition. Note: 2 Receive TOH CAP DONE Interrupt Enable R/W The user can determine whether or not the Receive STS-3 TOH Processor block is currently declaring the “Section Trace Message Mismatch” defect condition by reading the state of Bit 2 (Section Trace Message Mismatch Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 1 (Address Location= 0x1106). Receive TOH Capture DONE – Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Receive TOH Data Capture” interrupt, within the Receive STS-3 TOH Processor Block. If this interrupt is enabled, then the Receive STS-3 TOH Processor block will generate an interrupt anytime it has captured the last TOH byte into the Capture Buffer. Note: Once the TOH (of a given STS-3 frame) has been captured and loaded into the “Receive TOH Capture” buffer, it will remain there for one SONET frame period. 0 – Disables the “Receive TOH Capture” Interrupt. 1 – Enables the “Receive TOH Capture” Interrupt. 1 Change in K1, K2 Byte Unstable Defect Condition Interrupt Enable R/W Change of K1, K2 Byte Unstable Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of K1, K2 Byte Unstable defect condition” interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate an Interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the “K1, K2 Byte Unstable defect” condition. • Whenever the Receive STS-3 TOH Processor block clears the “K1, K2 Byte Unstable defect” condition. 0 – Disables the “Change in K1, K2 Byte Unstable Defect Condition” Interrupt 1 – Enables the “Change in K1, K2 Byte Unstable Defect Condition” Interrupt 0 New K1K2 Byte Interrupt Enable R/W New K1, K2 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “New K1, K2 Byte Value” Interrupt. If the user enables this interrupt, then the Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new K1, K2 byte value. The Receive STS-3 TOH Processor block will accept a new 138 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S K1, K2 byte value, after it has received it within 3 (or 5) consecutive STS-3 frames. 0 – Disables the “New K1, K2 Byte Value” Interrupt. 1 – Enables the “New K1, K2 Byte Value” Interrupt. 139 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 71: Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address Location= 0x110F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Change of SF Defect Condition Interrupt Enable Change of SD Defect Condition Interrupt Enable Detection of REI-L Event Interrupt Enable Detection of B2 Byte Error Interrupt Enable Detection of B1 Byte Error Interrupt Enable Change of LOF Defect Condition Interrupt Enable Change of SEF Defect Condition Interrupt Enable Change of LOS Defect Condition Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Change of SF Defect Condition Interrupt Enable R/W DESCRIPTION Change of Signal Failure (SF) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of Signal Failure (SF) Defect Condition” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to any of the following events. • Whenever the Receive STS-3 TOH Processor block declares the SF defect condition. • Whenever the Receive STS-3 TOH Processor block clears the SF defect condition. 0 – Disables the “Change of SF Defect Condition Interrupt”. 1 – Enables the “Change of SF Defect Condition Interrupt”. 6 Change of SD Defect Condition Interrupt Enable R/W Change of Signal Degrade (SD) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of Signal Degrade (SD) Defect Condition” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following events. • Whenever the Receive STS-3 TOH Processor block declares the SD defect condition. • Whenever the Receive STS-3 TOH Processor block clears the SD defect condition. 0 – Disables the “Change of SD Defect Condition Interrupt”. 1 – Enables the “Change of SD Defect Condition Interrupt”. 5 Detection of REI-L Event Interrupt Enable R/W Detection of REI-L (Line – Remote Error Indicator) Event Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of REI-L Event interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH Processor block detects an “REI-L” event, within the incoming STS-3 datastream. 0 – Disables the “Detection of REI-L Event” Interrupt. 1 – Enables the “Detection of REI-L Event” Interrupt. 4 Detection of B2 Byte Error Interrupt Enable R/W Detection of B2 Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of B2 Byte Error” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH Processor block detects a B2 byte error within the incoming STS-3 data- 140 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 stream. 0 – Disables the “Detection of B2 Byte Error Interrupt”. 1 – Enables the “Detection of B2 Byte Error Interrupt”. 3 Detection of B1 Byte Error Interrupt Enable R/W Detection of B1 Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of B1 Byte Error” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH Processor block detects a B1 byte error within the incoming STS-3 datastream. 0 – Disables the “Detection of B1 Byte Error Interrupt”. 1 – Enables the “Detection of B1 Byte Error Interrupt”. 2 Change of LOF Defect Condition Interrupt Enable R/W Change of Loss of Frame (LOF) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of LOF Defect Condition” interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3 TOH Processor block declares the “LOF” defect condition. • Whenever the Receive STS-3 TOH Processor clears the “LOF” defect condition. 0 – Disables the “Change of LOF Defect Condition Interrupt. 1 – Enables the “Change of LOF Defect Condition” Interrupt. 1 Change of SEF Defect Condition Interrupt Enable R/W Change of SEF Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of SEF Defect Condition” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3 TOH Processor block declares the “SEF” defect condition. • Whenever the Receive STS-3 TOH Processor block clears the ”SEF” defect condition. 0 – Disables the “Change of SEF Defect Condition Interrupt”. 1 – Enables the “Change of SEF Defect Condition Interrupt”. 0 Change of LOS Defect Condition Interrupt Enable R/W Change of Loss of Signal (LOS) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of LOF Defect Condition” interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3 TOH Processor block declares the “LOF” defect condition. • Whenever the Receive STS-3 TOH Processor block clears the “LOF” defect condition. 0 – Disables the “Change of LOF Defect Condition Interrupt. 1 – Enables the “Change of LOF Defect Condition” Interrupt. 141 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 72: Receive STS-3 Transport – B1 Byte Error Count Register – Byte 3 (Address Location= 0x1110) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B1 Byte Error Count[31:24] BIT NUMBER NAME TYPE 7-0 B1_Byte_Error_ Count[31:24] RUR DESCRIPTION B1 Byte Error Count – MSB: This RESET-upon-READ register, along with “Receive STS-3 Transport – B1 Byte Error Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B1 byte error within the STS-3 data-stream. Note: 1.If the Receive STS-3 TOH Processor block is configured to count B1 Byte Errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B1 byte (of each incoming STS-3 frame) that are in error. 2.If the Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains an erred B1 byte. Table 73: Receive STS-3 Transport – B1 Byte Error Count Register – Byte 2 (Address Location= 0x1111) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B1_Byte_Error_Count[23:16] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 B1_Byte_Error_ Count [23:16] RUR DESCRIPTION B1 Byte Error Count (Bits 23 through 16): This RESET-upon-READ register, along with “Receive STS-3 Transport – B1 Byte Error Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1.If the Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B1 byte (of each incoming STS-3 frame) that are in error. 2.If the Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains an erred B1 byte. 142 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 74: Receive STS-3 Transport – B1 Byte Error Count Register – Byte 1 (Address Location= 0x1112) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 RUR RUR RUR RUR RUR 0 0 0 0 0 BIT 2 BIT 1 BIT 0 RUR RUR RUR 0 0 0 B1_Byte_Error_Count[15:8] BIT NUMBER NAME TYPE DESCRIPTION 7-0 B1_Byte_Error_ Count [15:8] RUR B1 Byte Error Count – (Bits 15 through 8) This RESET-upon-READ register, along with “Receive STS-3 Transport – B1 Byte Error Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1.If the Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B1 byte (of each incoming STS-3 frame) that are in error. 2.If the Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains an erred B1 byte. Table 75: Receive STS-3 Transport – B1 Byte Error Count Register – Byte 0 (Address Location= 0x1113) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B1_Byte _Error_Count[7:0] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 B1_Byte_Error_ Count [7:0] RUR DESCRIPTION B1 Byte Error Count – LSB: This RESET-upon-READ register, along with “Receive STS-3 Transport – B1 Byte Error Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1.If the Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B1 byte (of each incoming STS-3 frame) that are in error. 2.If the Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains an erred B1 byte. 143 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 76: Receive STS-3 Transport – B2 Byte Error Count Register – Byte 3 (Address Location= 0x1114) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT NUMBER NAME TYPE 7-0 B2_Byte_Error_ Count [31:24] RUR BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B2_Byte_Error_Count[31:24] DESCRIPTION B2 Byte Error Count – MSB: This RESET-upon-READ register, along with “Receive STS-3 Transport – B2 Byte Error Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B2 byte error within the incoming STS-3 data-stream. Note: 1.If the Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B2 bytes (of each incoming STS-3 frame) that are in error. 2.If the Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains at least one erred B2 byte. 144 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 77: Receive STS-3 Transport – B2 Byte Error Count Register – Byte 2 Address Location= 0x1115) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7-0 B2_Byte Error_Count [23:16] RUR B2 Byte Error Count (Bits 23 through 16): B2_ Byte_ Error_Count[23:16] This RESET-upon-READ register, along with “Receive STS-3 Transport – B2 Byte Error Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1.If the Receive STS-3 TOH Processor block is configured to count B2 Byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B2 bytes (of each incoming STS-3 frame) that are in error. 2.If the Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains at least one erred B2 byte. 145 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 78: Receive STS-3 Transport – B2 Byte Error Count Register – Byte 1 (Address Location= 0x1116) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7-0 B2_Byte Error_Count [15:8] RUR B2 Byte Error Count – (Bits 15 through 8) B2_Byte_Error_Count[15:8] This RESET-upon-READ register, along with “Receive STS-3 Transport – B2 Byte Error Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B2 byte error within the incoming STS-3 data-stream. Note: 1. If the Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B2 bytes (of each incoming STS-3 frame) that are in error. 2. If the Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains at least one erred B2 byte. 146 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 79: Receive STS-3 Transport – B2 Byte Error Count Register – Byte 0 (Address Location= 0x1117) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B2_Byte_Error_Count[7:0] BIT NUMBER NAME TYPE 7-0 B2_Byte Error_Count[7:0] RUR DESCRIPTION B2 Byte Error Count – LSB: This RESET-upon-READ register, along with “Receive STS-3 Transport – B2 Byte Error Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1. If the Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B2 bytes (of each incoming STS-3 frame) that are in error. 2. If the Receive STS-3 TOH Processor block is configured to count B2 Byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that is receives an STS-3 frame that contains at least one erred B2 byte. 147 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 80: Receive STS-3 Transport – REI-L Event Count Register – Byte 3 (Address Location= 0x1118) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REI-L_Event_Count[31:24] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 REI-L_Event_Count [31:24] RUR DESCRIPTION REI-L Event Count – MSB: This RESET-upon-READ register, along with “Receive STS-3 Transport – REI-L Event Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a Line - Remote Error Indicator event within the incoming STS-3 data-stream. Note: 1. If the Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-bit” basis, then it will increment this 32 bit counter by the value within the REI-L fields of the M1 byte within each incoming STS-3 frame. 2. If the Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains a “non-zero” M1 byte value. 148 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 81: Receive STS-3 Transport – REI-L Event Count Register – Byte 2 (Address Location= 0x1119) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-L_Event_Count[23:16] BIT NUMBER NAME TYPE 7-0 REI-L_Event_Count [23:16] RUR DESCRIPTION REI-L Event Count (Bits 23 through 16): This RESET-upon-READ register, along with “Receive STS-3 Transport – REI-L Event Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a Line – Remote Error Indicator event within the incoming STS-3 data-stream. Note: 1. If the Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-bit” basis, then it will increment this 32 bit counter by the value within the REI-L fields of the M1 byte within each incoming STS-3 frame. 2. If the Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-frame” baiss, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains a non-zero M1 byte value. 149 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 82: Receive STS-3 Transport – REI-L Event Count Register – Byte 1 (Address Location= 0x111A) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REI-L_Event_Count[15:8] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 REI-L_Event_Count[15:8] RUR DESCRIPTION REI-L Event Count – (Bits 15 through 8) This RESET-upon-READ register, along with “Receive STS-3 Transport – REI-L Event Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a Line –Remote Error Indicator event within the incoming STS-3 data-stream. Note: 1. If the Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-bit” basis, then it will increment this 32 bit counter by the value within the REI-L fields of the M1 byte within each incoming STS-3 frame. 2. If the Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-bit” basis, then it will increment this 32 bit counter each that it receives an STS-3 frame that contains a non-zero M1 byte. 150 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 83: Receive STS-3 Transport – REI-L Event Count Register – Byte 0 (Address Location= 0x111B) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-L_Event_Count[7:0] BIT NUMBER NAME TYPE 7-0 REIL_Event_Count[7:0] RUR DESCRIPTION REI-L Event Count – LSB: This RESET-upon-READ register, along with “Receive STS-3 Transport – REI-L Event Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3 TOH Processor block detects a Line – Remote Error Indicator event within the incoming STS-3 data-stream. Note: 1. If the Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-bit” basis, then it will increment this 32 bit counter by the value within the REI-L fields of the M1 byte within each incoming STS-3 frame. 2. If the Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-frame” baiss, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains a “non-zero” M1 byte value. 151 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 84: Receive STS-3 Transport – Received K1 Byte Value Register (Address Location= 0x111F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Filtered_K1_Byte_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Filtered_K1_Byte Value[7:0] R/O DESCRIPTION Filtered/Accepted K1 Byte Value: These READ-ONLY bit-fields contain the value of the most recently “filtered” K1 byte value that the Receive STS-3 TOH Processor block has received. The Receive STS-3 TOH Processor block will “accept” a given K1 byte, once it has received this particular K1 byte value within 3 consecutive STS-3 frames. This register should be polled by Software in order to determine various APS codes. Table 85: Receive STS-3 Transport – Receive K2 Byte Value Register (Address Location= 0x1123) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Filtered_K2_Byte_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Filtered_K2_Byte_Value[7:0] R/O DESCRIPTION Filtered/Accepted K2 Byte Value: These READ-ONLY bit-fields contain the value of the most recently “filtered” K2 Byte value that the Receive STS-3 TOH Processor block has received. The Receive STS-3 TOH Processor block will “accept” a given K2 byte, once it has received this particular K2 byte value within 3 consecutive STS-3 frames. This register should be polled by Software in order to determine various APS codes. 152 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 86: Receive STS-3 Transport – Received S1 Byte Value Register (Address Location= 0x1127) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Filtered_S1_Byte_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Filtered_S1_Byte_Value[7:0] R/O DESCRIPTION Filtered/Accepted S1 Byte Value: These READ-ONLY bit-fields contain the value of the most recently “filtered” S1 byte value that the Receive STS-3 TOH Processor block has received. The Receive STS-3 TOH Processor block will “accept” a given S1 byte, once it has received this particular S1 byte value within 8 consecutive STS-3 frames. Table 87: Receive STS-3 Transport – In-Sync Threshold Value (Address Location=0x112B) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 FRPATOUT[1:0] BIT 1 FRPATIN[1:0] BIT 0 Unused R/O R/O R/O R/W R/W R/W R/W R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–5 Unused R/O 4–3 FRPATOUT [1:0] R/W DESCRIPTION Framing Pattern – SEF Declaration Criteria: These two READ/WRITE bit-fields permit the user to define the SEF Defect Declaration criteria for the Receive STS-3 TOH Processor block. The relationship between the state of these bit-fields and the corresponding SEF Defect Declaration Criteria are presented below. FRPATOUT[1:0] SEF Defect Declaration Criteria 00 The Receive STS-3 TOH Processor block will declare the SEF defect condition if either of the following conditions are true for four consecutive SONET frame periods. 01 • If the last (of the 3) A1 bytes, in the STS-3 data stream is erred, or • If the first (of the 3) A2 bytes, in the STS-3 data stream, is erred. Hence, for this selection, a total of 16 bits are evaluated for SEF defect declaration. 10 The Receive STS-3 TOH Processor block will declare the SEF defect condition if either of the following conditions are true for four consecutive SONET frame periods. • If the last two (of the 3) A1 bytes, in the STS-3 data stream, are erred, or • If the first two (of the 3) A2 bytes, in the STS-3 data stream, are erred. Hence, for this selection, a total of 32 bits are evaluated for SEF defect declaration. 153 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 11 Rev222...000...000 The Receive STS-3 TOH Processor block will declare the SEF defect condition if either of the following conditions are true for four consecutive SONET frame periods. • If the last three (of the 3) A1 bytes, in the STS-3 data stream, are erred, or • If the first three (of the 3) A2 bytes, in the STS-3 data stream, are erred. Hence, for this selection, a total of 48 bits are evaluated for SEF defect declaration. 2-1 FRPATIN [1:0] R/W Framing Pattern – SEF Defect Clearance Criteria: These two READ/WRITE bit-fields permit the user to define the “SEF Defect Clearance” criteria for the Receive STS-3 TOH Processor block. The relationship between the state of these bit-fields and the corresponding SEF Defect Clearance Criteria are presented below. FRPATIN[1:0] SEF Defect Clearance Criteria 00 The Receive STS-3 TOH Processor block will clear the SEF defect condition if both of the following conditions are true for two consecutive SONET frame periods. 01 • If the last (of the 3) A1 bytes, in the STS-3 data stream is un-erred, and • If the first (of the 3) A2 bytes, in the STS-3 data stream, is un-erred. Hence, for this selection, a total of 16 bits/frame are evaluated for SEF defect clearance. 10 The Receive STS-3 TOH Processor block will clear the SEF defect condition if both of the following conditions are true for two consecutive SONET frame periods. • If the last two (of the 3) A1 bytes, in the STS-3 data stream, are un-erred, and • If the first two (of the 3) A2 bytes, in the STS-3 data stream, are un-erred. Hence, for this selection, a total of 32 bits/frame are evaluated for SEF defect clearance. 11 The Receive STS-3 TOH Processor block will clear the SEF defect condition if both of the following conditions are true for two consecutive SONET frame periods. • If the last three (of the 3) A1 bytes, in the STS-3 datastream, are un-erred, and • If the first three (of the 3) A2 bytes, in the STS-3 data stream, are un-erred. Hence, for this selection, a total of 48 bits/frame are evaluated for SEF defect declaration. 0 Unused R/O 154 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 88: Receive STS-3 Transport – LOS Threshold Value - MSB (Address Location= 0x112E) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LOS_THRESHOLD[15:8] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 BIT NUMBER NAME TYPE 7-0 LOS_THRESHOLD[15:8] R/W DESCRIPTION LOS Threshold Value – MSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – LOS Threshold Value – LSB” register specify the number of consecutive (All Zero) bytes that the Receive STS-3 TOH Processor block must detect before it can declare the LOS defect condition. Table 89: Receive STS-3 Transport – LOS Threshold Value - LSB (Address Location= 0x112F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LOS_THRESHOLD[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 BIT NUMBER NAME TYPE 7-0 LOS_THRESHOLD[7:0] R/W DESCRIPTION LOS Threshold Value – LSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – LOS Threshold Value – MSB” register specify the number of consecutive (All Zero) bytes that the Receive STS-3 TOH Processor block must detect before it can declare the LOS defect condition. 155 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 90: Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 2 (Address Location= 0x1131) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_SET_MONITOR_WINDOW[23:16] BIT NUMBER NAME TYPE DESCRIPTION 7-0 SF_SET_MONITOR_ WINDOW [23:16] R/W SF_SET_MONITOR_INTERVAL – MSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SF SET Monitor Interval – Byte 1 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) Defect Declaration. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the user-specified “SF Defect Declaration monitoring period”. If, during this “SF Defect Declaration Monitoring Period”, the Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Receive STS-3 Transport SF SET Threshold” register, then the Receive STS-3 TOH Processor block will declare the SF defect condition. NOTES: o The value that the user writes into these three (3) “SF Set Monitor Window” registers specifies the duration of the “SF Defect Declaration Monitoring Period”, in terms of ms. o This particular register byte contains the “MSB” (most significant byte) value of the three registers that specify the “SF Defect Declaration Monitoring Period”. 156 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 91: Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 1 (Address Location= 0x1132) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_SET_MONITOR_WINDOW[15:8] BIT NUMBER NAME TYPE 7-0 SF_SET_MONITOR_WINDOW [15:8] R/W DESCRIPTION SF_SET_MONITOR_INTERVAL (Bits 15 through 8): These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SF SET Monitor Interval – Byte 2 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) Defect Declaration When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the user specified “SF Defect Declaration Monitoring Period”. If, during this “SF Defect Declaration Monitoring Period” the Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Receive STS-3 Transport SF SET Threshold” register, then the Receive STS-3 TOH Processor block will declare the SF defect condition. NOTE: The value that the user writes into these three (3) “SF Set Monitor Window” Registers specifes the duration of the “SF Defect Declaration” Monitoring Period, in terms of ms. 157 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 92: Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 0 (Address Location= 0x1133) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_SET_MONITOR_WINDOW[7:0] BIT NUMBER NAME TYPE 7-0 SF_SET_MONITOR_WINDOW[7:0] R/W DESCRIPTION SF_SET_MONITOR_INTERVAL – LSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SF SET Monitor Interval – Byte 2 and Byte 1” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) Defect Declaration. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the userspecified “SF Defect Declaration Monitoring Period”. If, during this “SF Defect Declaration Monitoring Period”, the Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Receive STS-3 Transport SF SET Threshold” register, then the Receive STS-3 TOH Processor block will declare the SF defect condition. NOTES: 158 1. The value that the user writes into these three (3) “SF Set Monitor Window” registers, specifies the duration of the “SF Defect Declaration” Monitoring Period, in terms of ms. 2. This particular register byte contains the “LSB” (least significant byte) value of the three registers that specify the “SF Defect Declaration Monitoring period”. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 93: Receive STS-3 Transport – Receive SF SET Threshold – Byte 1 (Address Location= 0x1136) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_SET_THRESHOLD[15:8] BIT NUMBER NAME TYPE 7-0 SF_SET_THRESHOLD[15:8] R/W DESCRIPTION SF_SET_THRESHOLD – MSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SF SET Threshold – Byte 0” registers permit the user to specify the number of B2 byte errors that will cause the Receive STS-3 TOH Processor block to declare the SF (Signal Failure) Defect condition. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the “SF Defect Declaration Monitoring Period”. If the number of accumulated B2 byte errors exceeds that value, which is programmed into this and the “Receive STS-3 Transport SF SET Threshold – Byte 0” register, then the Receive STS-3 TOH Processor block will declare the SF defect condition. NOTE: This particular register functions as the MSB (Most Signficant byte) of the “16-bit” expression for the “SF Defect Declaration B2 Byte Error” Threshold. 159 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 94: Receive STS-3 Transport – Receive SF SET Threshold – Byte 0 Address Location= 0x1137) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SF_SET_THRESHOLD[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 BIT NUMBER NAME TYPE 7-0 SF_SET_THRESHOLD[7: 0] R/W DESCRIPTION SF_SET_THRESHOLD – LSB: These READ/WRITE bits, along the contents of the “Receive STS3 Transport – SF SET Threshold – Byte 1” registers permit the user to specify the number of B2 byte errors that will cause the Receive STS-3 TOH Processor block to declare the SF (Signal Failure) defect condition. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the “SF Defect Monitoring Period”. If the number of accumulated B2 byte errors exceeds that which has been programmed into this and the “Receive STS-3 Transport SF SET Threshold – Byte 1” register, then the Receive STS-3 TOH Processor block will declare the SF defect condition. NOTE: This particular register functions as the LSB (Least Signficant byte) of the “16-bit” expression for the “SF Defect Declaration B2 Byte Error” Threshold. 160 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 95: Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 1 (Address Location= 0x113A) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_CLEAR_THRESHOLD[15:8] BIT NUMBER NAME TYPE 7-0 SF_CLEAR_THRESHOLD [15:8] R/W DESCRIPTION SF_CLEAR_THRESHOLD – MSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SF CLEAR Threshold – Byte 0” registers permit the user to specify the upper limit for the number of B2 byte errors that will cause the Receive STS-3 TOH Processor block to clear the SF (Signal Failure) defect condition. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condition, it will accumulate B2 byte errors throughout the “SF Defect Clearance Monitoring Period”. If the number of accumulated B2 byte errors is less than that programmed into this and the “Receive STS-3 Transport SF CLEAR Threshold – Byte 0” register, then the Receive STS-3 TOH Processor block will clear the SF defect condition. NOTE: This particular register functions as the MSB (Most Significant Byte) of the “16-bit” expression for the “SF Defect Clearance B2 Byte Error” Threshold. 161 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 96: Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 0 (Address Location= 0x113B) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_CLEAR_THRESHOLD[7:0] BIT NUMBER NAME TYPE 7-0 SF_CLEAR_THRESHOLD [7:0] R/W DESCRIPTION SF_CLEAR_THRESHOLD – LSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SF CLEAR Threshold – Byte 1” registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Receive STS-3 TOH Processor block to clear the SF (Signal Failure) defect condition. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condtiion, it will accumulate B2 byte errors throughout the “SF Defect Clearance Monitoring Period”. If the number of accumulated B2 byte errors is less than that programmed into this and the “Receive STS-3 Transport SF CLEAR Threshold – Byte 1” register, then the Receive STS-3 TOH Processor block will clear the SF defect condition. NOTE: This particular register functions as the LSB (Least Significant Byte) of the “16-bit” expression for the “SF Defect Clearance B2 Byte Error” Threshold. 162 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 97: Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 2 (Address Location= 0x113D) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 SD_SET_MONITOR_WINDOW[23:16] BIT NUMBER NAME TYPE 7-0 SD_SET_MONITOR_WINDOW [23:16] R/W DESCRIPTION SD_SET_MONITOR_INTERVAL – MSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SD SET Monitor Interval – Byte 1 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect declaration. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal, in order to determine if it should declare the SD defect condition, it will accumulate B2 byte errors throughout the userspecified “SD Defect Declaration monitoring period”. If, during this “SD Defect Declaration Monitoring period”, the Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Receive STS-3 Transport SD SET Threshold” register, then the Receive STS-3 TOH Processor block will declare the SD defect condition. NOTES: 163 1. The value that the user writes into these three (3) “SD Set Monitor Window” registers, specifies the duration of the “SD Defect Declaration Monitoring Period”, in terms of ms. 2. This particular register byte contains the “MSB” (Most Significant Byte) value of the three registers that specify the “SD Defect Declaration Monitoring Period”. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 98: Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 1 (Address Location= 0x113E) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 SD_SET_MONITOR_WINDOW[15:8] BIT NUMBER NAME TYPE DESCRIPTION 7-0 SD_SET_MONITOR_WINDOW[15:8] R/W SD_SET_MONITOR_INTERVAL – Bits 15 through 8: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SD SET Monitor Interval – Byte 2 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect declaration. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine it it should declare the SD defect condition, it will accumulate B2 byte errors throughout the userspecified “SD Defect Declaration Monitoring Period”. If, during this “SD Defect Declaration Monitoring Period” the Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Receive STS-3 Transport SD SET Threshold” register, then the Receive STS-3 TOH Processor block will declare the SD defect condition. NOTE: The value that the user writes into these three (3) “SD Set Monitor Window” registers, specifies the duration of the “SD Defect Declaration” Monitoring Period, in terms of ms. 164 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 99: Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 0 (Address Location= 0x113F) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 SD_SET_MONITOR_WINDOW[7:0] BIT NUMBER NAME TYPE 7-0 SD_SET_MONITOR_WINDOW[ 7:0] R/W DESCRIPTION SD_SET_MONITOR_INTERVAL – LSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SD SET Monitor Interval – Byte 2 and Byte 1” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect declaration. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SD defect condition, it will accumulate B2 byte errors throughout the user-specified “SD Defect Declaration Monitoring Period”. If, during this “SD Defect Declaration Monitoring Period”, the Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Receive STS-3 Transport SD SET Threshold” register, then the Receive STS-3 TOH Processor block will declare the SD defect condition. NOTES: 165 1. The value that the user writes into these three (3) “SD Set Monitor Window” registers, specifies the duration of the “SD Defect Declaration” Monitoring Period, in terms of ms. 2. This particular register byte contains the “LSB” (least significant byte) value of the three registers that specify the “SD Defect Declaration Monitoring period”. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 100: Receive STS-3 Transport – Receive SD SET Threshold – Byte 1 (Address Location= 0x1142) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SD_SET_THRESHOLD[15:8] BIT NUMBER NAME TYPE 7-0 SD_SET_THRESHOLD[15:8] R/W DESCRIPTION SD_SET_THRESHOLD – MSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SD SET Threshold – Byte 0” registers permit the user to specify the number of B2 byte errors that will cause the Receive STS-3 TOH Processor block to declare the SD (Signal Degrade) defect condition. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SD defect condition, it will accumulate B2 byte errors throughout the “SD Defect Declaration Monitoring Period”. If the number of accumulated B2 byte errors exceeds that value, which is programmed into this and the “Receive STS-3 Transport SD SET Threshold – Byte 0” register, then the Receive STS-3 TOH Processor block will declare the SD defect condition. Table 101: Receive STS-3 Transport – Receive SD SET Threshold – Byte 0 (Address Location= 0x1143) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 1 1 1 1 1 BIT 2 BIT 1 BIT 0 R/W R/W R/W 1 1 1 SD_SET_THRESHOLD[7:0] BIT NUMBER NAME TYPE 7-0 SD_SET_THRESHOLD[7:0] R/W DESCRIPTION SD_SET_THRESHOLD – LSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SD SET Threshold – Byte 1” registers permit the user to specify the number of B2 byte errors that will cause the Receive STS-3 TOH Processor block to declare the SD (Signal Degrade) defect condition. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SD defect condition, it will accumulate B2 byte errors throughout the “SD Defect Monitoring Period”. If the number of accumulated B2 byte errors exceeds that which has been programmed into this and the “Receive STS-3 Transport SD SET Threshold – Byte 1” register, then the Receive STS-3 TOH Processor block will declare the SD defect condition. 166 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 102: Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 1 (Address Location= 0x1146) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SD_CLEAR_THRESHOLD[15:8] BIT NUMBER NAME TYPE 7-0 SD_CLEAR_THRESHOLD[15:8] R/W DESCRIPTION SD_CLEAR_THRESHOLD – MSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SD CLEAR Threshold – Byte 0” registers permit the user to specify the upper limit for the number of B2 byte errors that will cause the Receive STS-3 TOH Processor block to clear the SD (Signal Degrade) defect condition. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors throughout the “SD Defect Clearance Monitoring Period”. If the number of accumulated B2 byte errors is less than that programmed into this and the “Receive STS-3 Transport SD CLEAR Threshold – Byte 0” register, then the Receive STS-3 TOH Processor block will clear the SD defect condition. 167 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 103: Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 1 (Address Location= 0x1147) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SD_CLEAR_THRESHOLD[7:0] BIT NUMBER NAME TYPE 7-0 SD_CLEAR_THRESHOLD[7:0] R/W DESCRIPTION SD_CLEAR_THRESHOLD – LSB: These READ/WRITE bits, along the contents of the “Receive STS-3 Transport – SD CLEAR Threshold – Byte 1” registers permit the user to specify the upper limit for the number of B2 byte errors that will cause the Receive STS-3 TOH Processor block to clear the SD (Signal Degrade) defect condition. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors, throughout the “SD Defect Clearance Monitoring Period”. If the number of accumulated B2 byte errors is less than that programmed into this and the “Receive STS-3 Transport SD CLEAR Threshold – Byte 1” register, then the Receive STS-3 TOH Processor block will clear the SD defect condition. 168 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 104: Receive STS-3 Transport – Force SEF Condition Register (Address Location= 0x114B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Unused BIT 0 SEF FORCE R/O R/O R/O R/O R/O R/O R/O R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–1 Unused R/O 0 SEF FORCE R/W DESCRIPTION SEF Force: This READ/WRITE bit-field permits the user to force the Receive STS-3 TOH Processor block to declare the SEF defect condition. The Receive STS-3 TOH Processor block will then attempt to reacquire framing. Writing a “1” into this bit-field configures the Receive STS-3 TOH Processor block to declare the SEF defect condition. The Receive STS-3 TOH Processor block will automatically set this bit-field to “0” once it has reacquired framing (e.g., has detected two consecutive STS-3 frames with the correct A1 and A2 bytes). 169 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 105: Receive STS-3 Transport – Receive Section Trace Message Buffer Control Register (Address Location= 0x114F) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Receive Section Trace Message Buffer Read Select Receive Section Trace Message Accept Threshold Section Trace Message Alignment Type BIT 1 BIT 0 Receive Section Trace Message Length[1:0] R/O R/O R/O R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–5 Unused R/O 4 Receive Section Trace Message Buffer Read Select R/W DESCRIPTION Receive Section Trace Message Buffer Read Selection: This READ/WRITE bit-field permits the user to specify which of the following Receive Section Trace Message buffer segments that the Microprocessor will read out, whenever it reads out the contents of the Receive Section Trace Message Buffer address space. a. The “Actual” Receive Section Trace Message Buffer. The “Actual” Receive Section Trace Message Buffer contains the contents of the most recently received (and accepted) Section Trace Message via the incoming STS-3 data-stream. b. The “Expected” Receive Section Trace Message Buffer. The “Expected” Receive Section Trace Message Buffer contains the contents of the Section Trace Message that the user “expects” to receive. The contents of this particular buffer is usually specified by the user. 0 – Executing a READ operation to the Receive Section Trace Message Buffer address space will return contents within the “Actual” Receive Section Trace Message” buffer. 1 – Executing a READ operation to the Receive Section Trace Message Buffer address space will return contents within the “Expected” Receive Section Trace Message Buffer”. Note: 3 Receive Section Trace Message Accept Threshold R/W In the case of the Receive STS-3 TOH Processor block, the “Receive Section Trace Message Buffer” is located at Address location 0x1300 through 0x133F. Receive Section Trace Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Receive STS-3 TOH Processor block must receive a given Section Trace Message, before it is accepted, as described below. Once a given “Section Trace Message” has been accepted then it can be read out of the “Actual Receive Section Trace Message” Buffer. 0 – Configures the Receive STS-3 TOH Processor block to accept the incoming Section Trace Message after it has received it the third time in succession. 1 – Configures the Receive STS-3 TOH Processor block to accept the incoming Section Trace Message after it has received it the fifth time in succession. 170 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 2 Section Trace Message Alignment Type R/W Section Trace Message Alignment Type: This READ/WRITE bit-field permits a user to specify how the Receive STS-3 TOH Processor block will locate the boundary of the incoming Section Trace Message within the incoming STS-3 data-stream, as indicated below. 0 – Configures the Receive STS-3 TOH Processor block to expect the Section Trace Message boundary to be denoted by a “Line Feed” character. 1 – Configures the Receive STS-3 TOH Processor block to expect the Section Trace Message boundary to be denoted by the presence of a “1” in the MSB (most significant bit) of the very first byte (within the incoming Section Trace Message). In this case, all of the remaining bytes (within the incoming Section Trace Message) will each have a “0” within their MSBs. 1-0 Receive Section Trace Message Length[1:0] R/W Receive Section Trace Message Length[1:0]: These READ/WRITE bit-fields permit the user to specify the length of the Section Trace Message that the Receive STS-3 TOH Processor block will accept and load into the “Actual” Receive Section Trace Message Buffer. The relationship between the content of these bit-fields and the corresponding Receive Section Trace Message Length is presented below. Receive Section Trace Message Length[1:0] Resulting Section Trace Message Length (in terms of bytes) 00 1 Byte 01 16 Bytes 10/11 64 Bytes 171 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 106: Receive STS-3 Transport – Receive SD Burst Error Tolerance – Byte 1 (Address Location= 0x1152) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 1 1 1 1 1 BIT 2 BIT 1 BIT 0 R/W R/W R/W 1 1 1 SD_BURST_TOLERANCE[15:8] BIT NUMBER NAME TYPE 7-0 SD_BURST_TOLERANCE [15:8] R/W DESCRIPTION SD_BURST_TOLERANCE – MSB: These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SD BURST Tolerance – Byte 0” registers permit the user to specify the maximum number of B2 bit errors that the Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare the SD (Signal Degrade) defect condition. Note: 172 The purpose of this feature is to permit the user to provide some level of B2 byte error burst filtering, when the Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Receive STS-3 TOH Processor block to detect B2 bit errors in multiple “Sub-Interval” periods before it will declare the SD defect condition. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 107: Receive STS-3 Transport – Receive SD Burst Error Tolerance – Byte 0 (Address Location= 0x1153) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SD_BURST_TOLERANCE[7:0] BIT NUMBER NAME TYPE 7-0 SD_BURST_TOLERANCE [7:0] R/W DESCRIPTION SD_BURST_TOLERANCE – LSB: These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SD BURST Tolerance – Byte 1” registers permit the user to specify the maximum number of B2 bit errors that the Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare the SD (Signal Degrade) defect condition. Note: 173 The purpose of this feature is to permit the user to provide some level of B2 byte error burst filtering, when the Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Receive STS-3 TOH Processor block to detect B2 bit errors in multiple “SubInterval” periods before it will declare the SD defect condition. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 108: Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 1 (Address Location= 0x1156) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SF_BURST_TOLERANCE[15:8] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 BIT NUMBER NAME TYPE 7-0 SF_BURST_TOLERANCE[15:8] R/W DESCRIPTION SF_BURST_TOLERANCE – MSB: These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SF BURST Tolerance – Byte 0” registers permit the user to specify the maximum number of B2 bit errors that the Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare the SF (Signal Failure) defect condition. Note: 174 The purpose of this feature is to permit the user to provide some level of B2 byte error burst filtering, when the Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Receive STS3 TOH Processor block to detect B2 bit errors in multiple “Sub-Interval” periods before it will declare the SF defect condition. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 109: Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 0 (Address Location= 0x1157) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_BURST_TOLERANCE[7:0] BIT NUMBER NAME TYPE 7-0 SF_BURST_TOLERANCE[7:0] R/W DESCRIPTION SF_BURST_TOLERANCE – LSB: These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SF BURST Tolerance – Byte 1” registers permit the user to specify the maximum number of B2 bit errors that the Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare the SF (Signal Failure) defect condition. Note: 175 The purpose of this feature is to permit the user to provide some level of B2 byte error burst filtering, when the Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Receive STS-3 TOH Processor block to detect B2 bit errors in multiple “Sub-Interval” periods before it will declare the SF defect condition. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 110: Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 2 (Address Location= 0x1159) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 1 1 1 1 1 BIT 2 BIT 1 BIT 0 R/W R/W R/W 1 1 1 SD_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER NAME TYPE 7-0 SD_CLEAR_MONITOR_ WINDOW[23:16] R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL – MSB: These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SD Clear Monitor Interval – Byte 1 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect clearance. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors throughout the user-specified “SD Defect Clearance” Monitoring period. If, during this “SD Defect Clearance Monitoring” period, the Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Receive STS-3 Transport SD Clear Threshold” register, then the Receive STS-3 TOH Processor block will clear the SD defect condition. NOTES: 1. The value that the user writes into these three (3) “SD Clear Monitor Window” Registers, specifies the duration of the “SD Defect Clearance Monitoring Period”, in terms of ms. 2. This particular register byte contains the “MSB” (Most Significant Byte) value of the three registers that specify the “SD Defect Clearance Monitoring” period. 176 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 111: Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1 (Address Location= 0x115A) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SD_CLEAR_MONITOR_WINDOW[15:8] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 BIT NUMBER NAME TYPE 7-0 SD_CLEAR_MONITOR_WINDOW[15:8] R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL through 8: – Bits 15 These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SD Clear Monitor Interval – Byte 2 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect clearance. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors throughout the userspecified “SD Defect Clearance” Monitoring period. If, during this “SD Defect Clearance Monitoring Period” the Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Receive STS-3 Transport SD Clear Threshold” register, then the Receive STS-3 TOH Processor block will clear the SD defect condition. NOTE: The value that the user writes into these three (3) “SD Clear Monitor Window” Registers, specifies the duration of the “SD Defect Clearance Monitoring Period”, in terms of ms. 177 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 112: Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0 (Address Location= 0x115B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 1 1 1 1 1 BIT 2 BIT 1 BIT 0 R/W R/W R/W 1 1 1 SD_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER NAME TYPE 7-0 SD_CLEAR_MONITOR_WINDOW[ 7:0] R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL – LSB: These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SD Clear Monitor Interval – Byte 2 and Byte 1” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect clearance. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors throughout the user-specified “SD Defect Clearance” Monitoring period. If, during this “SD Defect Clearance Monitoring” period, the Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Receive STS-3 Transport SD Clear Threshold” register, then the Receive STS-3 TOH Processor block will clear the SD defect condition. NOTES: 1. The value that the user writes into these three (3) “SD Clear Monitor Window” Registers, specifies the duration of the “SD Defect Clearance Monitoring Period”, in terms of ms. 2. This particular register byte contains the “LSB” (least significant byte) value of the three registers that specify the “SD Defect Clearance Monitoring” period. 178 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 113: Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2 (Address Location= 0x115D) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 1 1 1 1 1 BIT 2 BIT 1 BIT 0 R/W R/W R/W 1 1 1 SF_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER NAME TYPE 7-0 SF_CLEAR_MONITOR_WINDO W [23:16] R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL – MSB: These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SF Clear Monitor Interval – Byte 1 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) defect clearance. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condition, it will accumulate B2 byte errors throughout the user-specified “SF Defect Clearance” Monitoring period. If, during this “SF Defect Clearance” Monitoring period, the Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Receive STS-3 Transport SF Clear Threshold” register, then the Receive STS-3 TOH Processor block will clear the SF defect condition. NOTES: 179 1. The value that the user writes into these three (3) “SF Clear Monitor Window Registers”, specifies the duration of the “SF Defect Clearance Monitoring Period”, in terms of ms. 2. This particular register byte contains the “MSB” (most significant byte) value fo the three registers that specify the “SF Defect Clearance Monitoring” period. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 114: Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1 (Address Location= 0x115E) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER NAME TYPE DESCRIPTION 7-0 SF_CLEAR_MONITOR_WINDOW [15:8] R/W SF_CLEAR_MONITOR_INTERVAL – Bits 15 through 8: These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SF Clear Monitor Interval – Byte 2 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) defect clearance. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condition, it will accumulate B2 byte errors throughout the userspecified “SF Defect Clearance” Monitoring period. If, during this “SF Defect Clearance” Monitoring period, the Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Receive STS-3 Transport SF Clear Threshold” register, then the Receive STS-3 TOH Processor block will clear the SF defect condition. NOTES: The value that the user writes into these three (3) “SF Clear Monitor Window” Registers, specifies the duration of the “SF Defect Clearance Monitoring Period”, in terms of ms. 180 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 115: Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 0 (Address Location= 0x115F) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER NAME TYPE 7-0 SF_CLEAR_MONITOR_WINDOW [7:0] R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL – LSB: These READ/WRITE bits, along with the contents of the “Receive STS-3 Transport – SF Clear Monitor Interval – Byte 2 and Byte 1” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) defect clearance. When the Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condition, it will accumulate B2 byte errors throughout the userspecified “SF Defect Clearance” Monitoring period. If, during this “SF Defect Clearance Monitoring” period, the Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Receive STS-3 Transport SF Clear Threshold” register, then the Receive STS-3 TOH Processor block will clear the SF defect condition. NOTES: 181 1. The value that the user writes into these three (3) “SF Clear Monitor Window” Registers, specifies the duration of the “SF Defect Clearance Monitoring” period, in terms of ms. 2. This particular register byte contains the “LSB” (Least Significant byte) value of the three registers that specify the “SF Defect Clearance Monitoring” period. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 116: Receive STS-3 Transport – Auto AIS Control Register (Address Location= 0x1163) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit AIS-P (Downstream) Upon Section Trace Message Unstable Transmit AIS-P (Downstream) Upon Section Trace Message Mismatch Transmit AIS-P (Downstream) Upon SF Transmit AIS-P (Downstream) Upon SD Transmit AIS-P (Downstream) upon Loss of Optical Carrier AIS Transmit AIS-P (Downstream) upon LOF Transmit AIS-P (Downstream) upon LOS Transmit AIS-P (Downstream) Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER 7 NAME TYPE DESCRIPTION Transmit AIS-P (Down-stream) upon Section Trace Message Unstable R/W Transmit Path AIS upon Declaration of the Section Trace Message Unstable Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards each of the three Receive SONET POH Processor blocks), anytime (and for the duration that) it declares the Section Trace Message Unstable defect condition within the “incoming” STS-3 data-stream. 0 – Does not configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever (and for the duration that) it declares the “Section Trace Message Unstable” defect condition. 1 – Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards each of the three Receive SONET POH Processor blocks) whenever (and for the duration that) it declares the “Section Trace Message Unstable” defect condition. Note: 6 Transmit AIS-P (Down-stream) Upon Section Trace Message Mismatch R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (AIS-P) upon Declaration of the Section Trace Message Mismatch Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards each of the three Receive SONET POH Processor blocks), anytime it declares the Section Trace Message Mismatch defect condition within the “incoming” STS-3 data stream. 0 – Does not configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever (and for the duration that) it declares the “Section Trace Message Mismatch” defect condition. 1 – Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards each of the three Receive SONET POH Processor blocks) whenever (and for the duration that) it declares the “Section Trace Message Mismatch” defect condition. 182 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Note: 5 Transmit AIS-P (Down-stream) upon SF R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS upon declaration of the Signal Failure (SF) defect condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards each of the three Receive SONET POH Processor blocks), anytime it declares the SF defect condition. 0 – Does not configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever (and for the duration that) it declares the SF defect condition. 1 – Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards each of the three Receive SONET POH Processor blocks) whenever (and for the duration that) it declares the SF defect condition. Note: 4 Transmit AIS-P (Down-stream) upon SD R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS upon declaration of the Signal Degrade (SD) defect condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards each of the three Receive SONET POH Processor blocks), anytime it declares the SD defect condition. 0 – Does not configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever (and for the duration that) it declares the SD defect condition. 1 – Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards each of the three Receive SONET POH Processor blocks) whenever (and for the duration that) it declares the SD defect condition. Note: 3 Transmit AIS-P (Down-stream) upon Loss of Optical Carrier R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS upon Loss of Optical Carrier condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards each of the three Receive SONET POH Processor blocks), anytime it detects the “Loss of Optical Carrier” defect condition. 0 – Does not configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever (and for the duration that) it declares the “Loss of Optical Carrier” defect condition. 1 – Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards each of the three Receive SONET POH Processor blocks) whenever (and for the duration that) it declares the “Loss of Optical 183 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Carrier” defect condition. Note: 2 Transmit AIS-P (Down-stream) upon LOF R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS upon declaration of the Loss of Frame (LOF) defect condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards each of the three Receive SONET POH Processor block), anytime it declares the LOF defect condition. 0 – Does not configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever (and for the duration that) it declares the LOF defect condition. 1 – Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards each of the three Receive SONET POH Processor blocks) whenever (and for the duration that) it declares the LOF defect condition. Note: 1 Transmit AIS-P (Down-stream) upon LOS R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS upon Loss of Signal (LOS): This READ/WRITE bit-field permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards each of the three Receive SONET POH Processor block), anytime it declares the LOS defect condition. 0 – Does not configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever (and for the duration that) it declares the LOS defect condition. 1 – Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards each of the three Receive SONET POH Processor blocks) whenever (and for the duration that) it declares the LOS defect condition. Note: 0 Transmit AIS-P (Down-stream) Enable R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field serves two purposes. It permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit the Path AIS (AIS-P) indicator, via the downstream traffic (e.g., towards each of the three Receive SONET POH Processor blocks), upon declaration of either the SF, SD, Section Trace Message Mismatch, Section Trace Message Unstable, LOF, LOS or Loss of Optical Carrier defect conditions. It also permits the user to configure the Receive STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the 184 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S “downstream” traffic (e.g., towards each of the three Receive SONET POH Processor blocks) anytime (and for the duration that) it declares the AIS-L defect condition within the “incoming “ STS-3 data-stream. 0 – Configures the Receive STS-3 TOH Processor block to NOT automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever the Receive STS-3 TOH Processor block declares the AIS-L or any other of the “above-mentioned” defect conditions. 1 – Configures the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards each of the three Receive SONET POH Processor blocks) whenever (and for the duration that) the Receive STS-3 TOH Processor block declares the AIS-L, SD, SF, LOF, LOS, Section Trace Message Mismatch, Section Trace Message Unstable or Loss of Optical Carrier defect condition). Note: The user must also set the corresponding bit-fields (within this register) to “1” in order to configure the Receive STS-3 TOH Processor block to automatically transmit the AIS-P indicator upon detection of a given alarm/defect condition. 185 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 117: Receive STS-3 Transport – Serial Port Control Register (Address Location= 0x1167) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 RxTOH_CLOCK_SPEED[3:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Unused R/O 3-0 RxTOH_CLOCK_SPEED[7:0] R/W DESCRIPTION RxTOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permit the user to specify the frequency of the “RxTOHClk output clock signal. The formula that relates the contents of these register bits to the “RxTOHClk” frequency is presented below. FREQ = 19.44 /[2 * (RxTOH_CLOCK_SPEED + 1) Note: 186 For STS-3/STM-1 applications, the frequency of the RxTOHClk output signal must be in the range of 0.6075MHz to 9.72MHz XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 118: Receive STS-3 Transport – Auto AIS (in Downstream STS-1s) Control Register (Address Location= 0x116B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Unused Transmit AIS-P/AIS (via Downstream STS-1s/ DS3s) upon LOS Transmit AIS-P/AIS (via Downstream STS-1s/ DS3s) upon LOF Transmit AIS-P/AIS (via Downstream STS-1s/ DS3s) upon SD Transmit AIS-P/AIS (via Downstream STS-1s/ DS3s) upon SF AIS-L Output Enable Transmit AIS-P/AIS (via Downstream STS-1s/ DS3s) Enable R/O R/O R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-6 Unused R/O 5 Transmit AIS-P/AIS (via Downstream STS1s/DS3s) upon LOS R/W DESCRIPTION Transmit AIS-P (via Downstream STS-1s) upon declaration of the LOS (Loss of Signal) defect condition/Transmit DS3 AIS (via Downstream DS3s) upon declaration of the LOS Defect condition: The exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle STS-1 or DS3 signals, on the “lowspeed” side of the chip, as described below. For those channels that are configured to operate in the STS-1 Mode: This READ/WRITE bit-field permits the user to configure all of the active Transmit STS-1 POH Processor blocks (within the XRT94L33 device) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the LOS defect condition. 0 – Does not configure all “activated” Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the LOS defect condition. 1 – Configures all “activated” Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the LOS defect condition. Note: 1. In the “long-run” the function of this bit-field is exactly the same as that of Bit 1 (Transmit AIS-P Down-stream – Upon LOS), within the Receive STS-3 Transport – Auto AIS Control Register (Address Location= 0x1163). The only difference is that this register bit will cause each of the “downstream” Transmit STS-1 POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-3 TOH Processor block declares the LOS defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOS defect. 2. In the case of Bit 1 (Transmit AIS-P Downstream – Upon LOS), several SONET frame periods are required (after the Receive STS-3 187 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 TOH Processor block has declared the LOS defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to “1”, the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. For those channels that are configured to operate in the DS3 Mode: This READ/WRITE bit-field permits the user to configure all of the active DS3/E3 Framer blocks (within the XRT94L33 device) to automatically transmit the DS3 AIS indicator via their “downstream” (or Egress Direction) DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the LOS defect condition. 0 – Does not configure all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS indicator via their “downstream” DS3 signals, anytime the Receive STS-3 TOH Processor block declares the LOS defect condition. 1 – Configures all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS Indicator via their “downstream” DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the LOS defect condition. NOTE: In addition to setting this bit-field to “1”, the user must also set Bit 0 (Transmit AIS-P/AIS via Downstream STS-1s/DS3s Enable) within this register, in order to enable this feature. 4 Transmit AIS-P/AIS (via Downstream STS1s/DS3s) upon LOF R/W Transmit AIS-P (via Downstream STS-1s) upon declaration of the LOF (Loss of Frame) defect condition/Transmit DS3 AIS (via Downstream DS3s) upon declaration of the LOF defect condition: The exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle STS-1 or DS3 signals, on the “lowspeed” side of the chip, as described below. For those channels that are configured to operate in the STS-1 Mode: This READ/WRITE bit-field permits the user to configure all of the active Transmit STS-1 POH Processor blocks (within the XRT94L33 device) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the LOF defect condition. 0 – Does not configures all “activated” Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the LOF defect condition. 1 – Configures all “activated” Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the LOF defect condition. Note: 1. In the “long-run” the function of this bit-field is exactly the same as that of Bit 2 (Transmit AIS-P Down-stream – Upon LOF), within the Receive STS-3 Transport – Auto AIS Control Register (Address Location= 0x1163). The only difference is that this register bit will cause each of the “downstream” Transmit STS-1 POH Processor blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-3 TOH Processor block declares the LOF defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream 188 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S within 125us of the NE declaring the LOF defect. 2. In the case of Bit 2 (Transmit AIS-P Downstream – Upon LOF), several SONET frame periods are required (after the Receive STS-3 TOH Processor block has declared the LOS defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to “1”, the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. For those channels that are configured to operate in the DS3 Mode: This READ/WRITE bit-field permits the user to configure all of the active DS3/E3 Framer blocks (within the XRT94L33 device) to automatically transmit the DS3 AIS indicator via the “downstream” (or Egress Direction) DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the LOF defect condition. 0 – Does not configure all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS indicator via the “downstream” DS3 signals, anytime the Receive STS-3 TOH Processor block declares the LOF defect condition. 1 – Configures all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS Indicator via the “downstream” DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the LOF defect condition. NOTE: In addition to setting this bit-field to “1”, the user must also set Bit 0 (Transmit AIS-P/AIS via Downstream STS-1s/DS3s Enable) within this register, in order to enable this feature. 3 Transmit AIS-P/AIS (via Downstream STS1s/DS3s) upon SD R/W Transmit AIS-P (via Downstream STS-1s) upon declaration of the SD (Signal Degrade) defect condition/Transmit DS3 AIS (via Downstream DS3s) upon declaration of the SD defect condition: The exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle STS-1 or DS3 signals, on the “lowspeed” side of the chip, as described below. For those channels that are configured to operate in the STS-1 Modes: This READ/WRITE bit-field permits the user to configure all of the active Transmit STS-1 POH Processor blocks (within the XRT94L33 device) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the SD defect condition. 0 – Does not configures all “activated” Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the SD defect condition. 1 – Configures all “activated” Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the SD defect condition. Note: 1. In the “long-run” the function of this bit-field is exactly the same as that of Bit 4 (Transmit AIS-P Down-stream – Upon SD), within the Receive STS-3 Transport – Auto AIS Control Register (Address Location= 0x1163). The only difference is that this register bit will cause each of the “downstream” Transmit STS-1 POH Processor blocks to 189 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 IMMEDIATELY begin to transmit the AIS-P condition whenever the Receive STS-3 TOH Processor block declares the SD defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the LOS defect. 2. In the case of Bit 1 (Transmit AIS-P Downstream – Upon LOF), several SONET frame periods are required (after the Receive STS-3 TOH Processor block has declared the SD defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to “1”, the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. For those channels that are configured to operate in the DS3 Mode: This READ/WRITE bit-field permits the user to configure all of the active DS3/E3 Framer blocks (within the XRT94L33 device) to automatically transmit the DS3 AIS indicator via the “downstream” (or Egress Direction) DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the SD defect condition. 0 – Does not configure all “active” DS3/E3 Framer block s to automatically transmit the DS3 AIS indicator via the “downstream” DS3 signals, anytime the Receive STS-3 TOH Processor block declares the SD defect condition. 1 – Configures all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS Indicator via the “downstream” DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the SD defect condition. NOTE: In addition to setting this bit-field to “1” the user must also set Bit 0 (Transmit AIS-P/AIS via Downstream STS-1s/DS3s Enable) within this register, in order to enable this feature. 2 Transmit AIS-P/AIS (via Downstream STS1s/DS3s) upon SF R/W Transmit AIS-P (via Downstream STS-1s) upon declaration of the Signal Failure (SF) defect condition/Transmit DS3 AIS (via Downstream DS3s) upon declaration of the SF defect condition: The exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle STS-1 or DS3 signals, on the “lowspeed” side of the chip, as described below. For those channels that are configured to operate in the STS-1 Mode: This READ/WRITE bit-field permits the user to configure all of the active Transmit STS-1 POH Processor blocks (within the XRT94L33 device) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the SF defect condition. 0 – Does not configures all “activated” Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3 TOH Processor block declares the SF defect condition. 1 – Configures all “activated” Transmit STS-1POH Processor blocks to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the SF defect condition. NOTES: 1. In the “long-run” the function of this bit-field is exactly the same as that 190 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S of Bit 5 (Transmit AIS-P Down-stream – Upon SF), within the Receive STS-3 Transport – Auto AIS Control Register (Address Location= 0x1163). The only difference is that this register bit will cause each of the “downstream” Transmit STS-1 POH Processor blocks to IMMEDIATELY begin transmit the AIS-P condition whenever the Receive STS-3 TOH Processor block declares the SF defect. This will permit the user to easily comply with the Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P indicator downstream within 125us of the NE declaring the SF defect. 2. In the case of Bit 5 (Transmit AIS-P Downstream – Upon SF), several SONET frame periods are required (after the Receive STS-3 TOH Processor block has declared the SF defect), before the Transmit STS-1 POH Processor blocks will begin the process of transmitting the AIS-P indicators. 3. In addition to setting this bit-field to “1”, the user must also set Bit 0 (Transmit AIS-P via Downstream STS-1s Enable) within this register, in order enable this feature. For those channels that are configured to operate in the DS3 Mode: This READ/WRITE bit-field permits the user to configure all of the active DS3/E3 Framer blocks (within the XRT94L33 device) to automatically transmit the DS3 AIS indicator via the “downstream” (or Egress Direction) DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the SF defect condition. 0 – Does not configure all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS indicator via the “downstream” DS3 signals, anytime the Receive STS-3 TOH Processor block declares the SF defect condition. 1 – Configures all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS indicator via the “downstream” DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the SF defect condition. NOTE: In addition to setting this bit-field to “1”, the user must also set Bit 0 (Transmit AIS-P/AIS via Downstream STS-1s/DS3s Enable) within this register, in order to enable this feature. 1 AIS-L Output Enable R/W AIS-L Output Enable: This READ/WRITE bit-field, along with Bits 7 (8kHz or STUFF Out Enable) within the “Operation Output Control Register – Byte 1” (Address Location= 0x0150) permit the user to configure the “AIS-L” indicator to be output via the “LOF” output pin (pin AD11). If Bit 7 (within the “Operation Output Control Register – Byte 1”) is set to “0”, then setting this bit-field to “1” configures pin AD11 to function as the AIS-L output indicator. If Bit 7 (within the “Operation Output Control Register – Byte 1”) is set to “0”, then setting this bit-field to “0” configures pin AD11 to function as the LOF output indicator. If Bit 7 (within the “Operation Output Control Register – Byte 1) is set to “1”, then this register bit is ignored. 0 Transmit AIS-P/AIS (via Downstream STS-1s/ DS3s) Enable R/W Automatic Transmission of AIS-P/AIS (via the downstream STS-1s or DS3s) Enable: The exact function of this bit-field depends upon whether the XRT94L33 device has been configured to handle STS-1 or DS3 signals, on the “lowspeed” side of the chip, as described below. For those channels that are configured to operate in the STS-1 191 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Mode: This READ/WRITE bit-field permits the user to configure all “activated” Transmit STS-1 POH Processor blocks to automatically transmit the AISP indicator, via its “outbound” STS-1 signals, upon detection of an SF, SD, LOS, LOF and AIS-L defect conditions. 0 – Does not configure the “activated” Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P indicator, whenever (and for the duration that) the Receive STS-3 TOH Processor block declares either the LOS, LOF, SD, SF or AIS defect condition. 1 – Configures the “activated” Transmit STS-1 POH Processor blocks to automatically transmit the AIS-P indicator (via their downstream signal paths), whenever (and for the duration that) the Receive STS-3 TOH Processor block declares either the LOS, LOF, SD, SF or AIS-L defect conditions. NOTES: 1. The user must also set the corresponding bit-fields (within this register) to “1” in order to configure all “active” Transmit STS-1 TOH Processor blocks to automatically transmit the AIS-P indicator (downstream) whenever (and for the duration that) the Receive STS-3 TOH Processor block declares the LOS, LOF, SD or SF defect conditions. 2. Setting this particular bit-field to “1” will also configure all “active” Transmit STS-1 TOH Processor blocks to automatically transmit the AIS-P indicator (downstream) whenever (and for the duration that) the Receive STS-3 TOH Processor block declares the AIS-L defect condition. For those channels that are configured to operate in the DS3 Mode: This READ/WRITE bit-field permits the user to configure all of the active DS3/E3 Framer blocks (within the XRT94L33 device) to automatically transmit the DS3 AIS indicator via the “downstream” (or Egress Direction) DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares the LOS, LOF, SD, SF or AIS-L defect conditions. 0 – Does not configure all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS indicator via their “downstream” DS3 signals, anytime the Receive STS-3 TOH Processor block declares either the LOS, LOF, SD, SF or AIS-L defect conditions. 1 – Configures all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS indicator via their “downstream” DS3 signals, anytime (and for the duration that) the Receive STS-3 TOH Processor block declares either the LOS, LOF, SD, SF or AIS-L defect conditions. NOTES: 1. The user must also set the corresponding bit-fields (within this register) to “1” in order to configure all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS indicator (downstream) whenever (and for the duration that) the Receive STS-3 TOH Processor block declares the LOS, LOF, SD or SF defect conditions. 2. Setting this particular bit-field to “1” will also configure all “active” DS3/E3 Framer blocks to automatically transmit the DS3 AIS indicator (downstream) whenever (and for the duration that) the Receive STS-3 TOH Processor block declares the AISL defect condition. 192 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.5 RECEIVE STS-3C POH PROCESSOR BLOCK The register map for the Receive STS-3c POH Processor Block is presented in the Table below. Additionally, a detailed description of each of the “Receive STS-3c POH Processor” block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the “Receive STS-3c POH Processor Block “highlighted” is presented below in Figure 2. It should be noted that for Mapper Aggregation Applications, the Receive STS-3c POH Processor block is only active if the user has configured the XRT94L33 device to handle STS-3c data via STS-1 Telecom Bus Interface # 1. The Receive STS-3c POH Processor block is also active if the user configures the XRT94L33 device to operate in the “ATM UNI” or “PPP Packet over STS-3c” Mode. For details on XRT94L33 device operate in the ATM or PPP Mode, the user should consult the “XRT94L33 Register Map/Description for ATM/PPP Applications” document. Figure 2: Illustration of the Functional Block Diagram of the XRT94L33, with the Receive STS-3c POH Processor Block “High-lighted”. Channel 0 Receive ReceiveSTS-1 STS-1 Telecom TelecomBus Bus Interface Interface Block Block Clock Clock Synthesizer Synthesizer Block Block From Channels 1&2 Transmit Transmit STS-3 STS-3PECL PECL Interface Interface Block Block Receive Receive STS-1 STS-1TOH TOH Processor Processor Block Block Receive Receive STS-1 STS-1POH POH Processor Processor Block Block Transmit Transmit SONET SONETPOH POH Processor Processor Block Block Transmit Transmit STS-3 STS-3TOH TOH Processor Processor Block Block Transmit TransmitSTS-3 STS-3 Telecom TelecomBus Bus Interface Interface Block Block Transmit Transmit STS-1 STS-1TOH TOH Processor Processor Block Block Transmit Transmit STS-1 STS-1POH POH Processor Processor Block Block Receive Receive SONET SONETPOH POH Processor Processor Block Block Receive Receive STS-3 STS-3TOH TOH Processor Processor Block Block Clock Clock&& Data Data Recovery Recovery Block Block Transmit TransmitSTS-1 STS-1 Telecom TelecomBus Bus Interface Interface Block Block DS3/E3 DS3/E3 Framer Framer Block Block Receive ReceiveSTS-3 STS-3 Telecom TelecomBus Bus Interface Interface Block Block DS3/E3 DS3/E3Jitter Jitter Attenuator Attenuator Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block To Channels 1 & 2 193 Receive Receive STS-3 STS-3PECL PECL Interface Interface Block Block XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1.5.1 Rev222...000...000 RECEIVE STS-3C POH PROCESSOR BLOCK REGISTER Table 119: Receive STS-3c POH Processor Block Register - Address Map ADDRESS LOCATION 0x1000 – 0x1181 REGISTER NAME DEFAULT VALUES Reserved 0x00 0x1182 Receive STS-3c Path – Control Register – Byte 1 0x00 0x1183 Receive STS-3c Path – Control Register – Byte 0 0x00 Reserved 0x00 0x1186 Receive STS-3c Path – Status Register – Byte 1 0x00 0x1187 Receive STS-3c Path – Status Register – Byte 0 0x00 0x1188 Reserved 0x00 0x1189 Receive STS-3c Path – Interrupt Status Register – Byte 2 0x00 0x118A Receive STS-3c Path – Interrupt Status Register – Byte 1 0x00 0x118B Receive STS-3c Path – Interrupt Status Register – Byte 0 0x00 0x118C Reserved 0x00 0x118D Receive STS-3c Path – Interrupt Enable Register – Byte 2 0x00 0x118E Receive STS-3c Path – Interrupt Enable Register – Byte 1 0x00 0x118F Receive STS-3c Path – Interrupt Enable Register – Byte 0 0x00 Reserved 0x00 Receive STS-3c Path – SONET Receive RDI-P Register 0x00 Reserved 0x00 0x1196 Receive STS-3c Path – Received Path Label Byte (C2) Register 0x00 0x1197 Receive STS-3c Path – Expected Path Label Byte (C2) Register 0x00 0x1198 Receive STS-3c Path – B3 Error Count Register – Byte 3 0x00 0x1199 Receive STS-3c Path – B3 Error Count Register – Byte 2 0x00 0x119A Receive STS-3c Path – B3 Error Count Register – Byte 1 0x00 0x119B Receive STS-3c Path – B3 Error Count Register – Byte 0 0x00 0x119C Receive STS-3c Path – REI-P Error Count Register – Byte 3 0x00 0x119D Receive STS-3c Path – REI-P Error Count Register – Byte 2 0x00 0x119E Receive STS-3c Path – REI-P Error Count Register – Byte 1 0x00 0x119F Receive STS-3c Path – REI-P Error Count Register – Byte 0 0x00 Reserved 0x00 Receive STS-3c Path – Receive J1 Byte Control Register 0x00 0x1184, 0x1185 0x1190 – 0x1192 0x1193 0x1194, 0x1195 0x11A0 – 0x11A2 0x11A3 194 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S ADDRESS LOCATION REGISTER NAME DEFAULT VALUES 0x11A4, 0x11A5 Reserved 0x00 0x11A6 Receive STS-3c Path – Pointer Value Register – Byte 1 0x00 0x11A7 Receive STS-3c Path – Pointer Value Register – Byte 0 0x00 Reserved 0x00 Receive STS-3c Path – Loss of Pointer – Concatenation Status Register 0x00 Reserved 0x00 Receive STS-3c Path – AIS - Concatenation Status Register 0x00 Reserved 0x00 Receive STS-3c Path – AUTO AIS Control Register 0x00 Reserved 0x00 Receive STS-3c Path – Serial Port Control Register 0x00 Reserved 0x00 Receive STS-3c Path – SONET Receive Auto Alarm Register – Byte 0 0x00 Reserved 0x00 Receive STS-3c Path – Receive J1 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive B3 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive C2 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive G1 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive F2 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive H4 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive Z3 Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive Z4 (K3) Byte Capture Register 0x00 Reserved 0x00 Receive STS-3c Path – Receive Z5 Byte Capture Register 0x00 0x11A8 – 0x11AA 0x11AB 0x11AC – 0x11B2 0x11B3 0x11B4 – 0x11BA 0x11BB 0x11BC – 0x11BE 0x11BF 0x11C0 – 0x11C2 0x11C3 0x11C4 – 0x11D2 0x11D3 0x11D4 – 0x11D6 0x11D7 0x11D8 – 0x11DA 0x11DB 0x11DC – 0x11DE 0x11DF 0x11E0 – 0x11E2 0x11E3 0x11E4 – 0x11E6 0x11E7 0x11E8 – 0x11EA 0x11EB 0x11EC – 0x11EE 0x11EF 0x11F0 – 0x11F2 0x11F3 195 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM ADDRESS LOCATION 0x11F4 – 0x11FF REGISTER NAME Reserved 196 Rev222...000...000 DEFAULT VALUES XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.5.2 RECEIVE STS-3C POH PROCESSOR BLOCK REGISTER DESCRIPTION Table 120: Receive STS-3c Path – Control Register – Byte 0 (Address Location= 0x1183) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 Check Stuff RDI-P Type REI-P Error Type B3 Error Type R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–4 Unused R/O 3 Check Stuff R/W DESCRIPTION Check (Pointer Adjustment) Stuff Select: This READ/WRITE bit-field permits the user to enable/disable the SONET standard recommendation that a pointer increment or decrement operation, detected within 3 SONET frames of a previous pointer adjustment operation (e.g., negative stuff, positive stuff) is ignored. 0 – Disables this SONET standard implementation. In this mode, all pointer-adjustment operations that are detected will be accepted. 1 – Enables this “SONET standard” implementation. In this mode, all pointer-adjustment operations that are detected within 3 SONET frame periods of a previous pointer-adjustment operation will be ignored. 2 RDI-P Type R/W Path – Remote Defect Indicator Type Select: This READ/WRITE bit-field permits the user to configure the Receive STS3c POH Processor block to support either the “Single-Bit” or the “Enhanced” RDI-P form of signaling, as described below. 0 – Configures the Receive STS-3c POH Processor block to support the Single-Bit RDI-P. In this mode, the Receive STS-3c POH Processor block will only monitor Bit 5, within the G1 byte (of incoming SPE data), in order to declare and clear the RDI-P defect condition. 1 – Configures the Receive STS-3c POH Processor block to support the Enhanced RDI-P (ERDI-P). In this mode, the Receive STS-3c POH Processor block will monitor bits 5, 6 and 7, within the G1 byte, in order to declare and clear the RDI-P defect condition. 1 REI-P Error Type R/W REI-P Error Type: This READ/WRITE bit-field permits the user to specify how the “Receive STS-3c POH Processor block will count (or tally) REI-P events, for Performance Monitoring purposes. The user can configure the Receive STS-3c POH Processor block to increment REI-P events on either a “perbit” or “per-frame” basis. If the user configures the Receive STS-3c POH Processor block to increment REI-P events on a “per-bit” basis, then it will increment the Receive STS-3c Path REI-P Error Count” register by the value of the lower nibble within the G1 byte of the incoming STS-3c datastream. If the user configure the Receive STS-3c POH Processor block to increment REI-P events on a “per-frame” basis, then it will increment the “Receive STS-3c Path – REI-P Error Count” register each time it receives an STS-3c SPE, in which the lower-nibble of the G1 byte (bits 1 through 4) are set to a “non-zero” value. 0 – Configures the Receive STS-3c POH Processor block to count or tally REI-P events on a per-bit basis. 197 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 1 – Configures the Receive STS-3c POH Processor block to count or tally REI-P events on a “per-frame” basis. 0 B3 Error Type R/W B3 Error Type: This READ/WRITE bit-field permits the user to specify how the “Receive STS-3c POH Processor block will count (or tally) B3 byte errors, for Performance Monitoring purposes. The user can configure the Receive STS-3c POH Processor block to increment B3 byte errors on either a “perbit” or “per-frame” basis. If the user configures the Receive STS-3c POH Processor block to increment B3 byte errors on a “per-bit” basis, then it will increment the “Receive STS-3c Path - B3 Byte Error Count” register by the number of bits (within the B3 byte value of the incoming STS-3c datastream) that is in error. If the user configures the Receive STS-3c POH Processor block to increment B3 byte errors on a “per-frame” basis, then it will increment the “Receive STS-3c Path – B3 Byte Error Count” Register each time that it receives an STS-3c SPE that contains an erred B3 byte. 0 – Configures the Receive STS-3c POH Processor block to count B3 byte errors on a “per-bit” basis. 1 – Configures the Receive STS-3c POH Processor block to count B3 byte errors on a “per-frame” basis. 198 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 121: Receive STS-3c Path – Receive Status Register – Byte 1 (Address Location= 0x1186) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Path Trace Message Unstable Defect Declared Unused R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–1 Unused R/O 0 Path Trace Message Unstable Defect Declared R/O DESCRIPTION Path Trace Message Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the Path Trace Message Unstable defect condition. The Receive STS-3c POH Processor block will declare the Path Trace Message Unstable defect condition, whenever the “Path Trace Message Unstable” counter reaches the value “8”. The “Path Trace Message Unstable” counter will be incremented for each time that it receives a Path Trace message that differs from the previously received message. The “Path Trace Message Unstable” counter is cleared to “0” whenever the Receive STS-3c POH Processor block has received a given Path Trace Message 3 (or 5) consecutive times. Note: Receiving a given Path Trace Message 3 (or 5) consecutive times also sets this bit-field to “0”. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the Path Trace Message Unstable defect condition. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the Path Trace Message Unstable defect condition. 199 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 122: Receive STS-3c Path – SONET Receive Status Register – Byte 0 (Address Location= 0x1187) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TIM-P Defect Declared C2 Byte Unstable Defect Declared UNEQ-P Defect Declared PLM-P Defect Declared RDI-P Defect Declared RDI-P Unstable Condition LOP-P Defect Declared AIS-P Defect Declared R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 TIM-P Defect Declared R/O DESCRIPTION Trace Identification Mismatch (TIM-P) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the “Path Trace Identification Mismatch” (TIM-P) defect condition. The Receive STS-3c POH Processor block will declare the “TIM-P” defect condition, when none of the received 64-byte string (received via the J1 byte, within the incoming STS-3c data-stream) matches the expected 1, 16 or 64byte message. The Receive STS-3c POH Processor block will clear the “TIM-P” defect condition, when 80% of the received 1, 16 or 64-byte string (received via the J1 byte) matches the expected 1, 16 or 64-byte message. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the TIM-P defect condition. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the TIM-P defect condition. 6 C2 Byte Unstable Defect Declared R/O C2 Byte (Path Signal Label Byte) Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the “Path Signal Label Byte” Unstable defect condition. The Receive STS-3c POH Processor block will declare the C2 (Path Signal Label Byte) Unstable defect condition, whenever the “C2 Byte Unstable” counter reaches the value “5”. The “C2 Byte Unstable” counter will be incremented for each time that it receives an STS-3c SPE with a C2 byte value that differs from the previously received C2 byte value. The “C2 Byte Unstable” counter is cleared to “0” whenever the Receive STS-3c POH Processor block has received 3 (or 5) consecutive STS-3c SPEs that each contain the same C2 byte value. Note: Receiving a given C2 byte value in 3 (or 5) consecutive SPEs also sets this bit-field to “0”. 0 – Indicates that the Receive STS-3c POH Processor block is currently NOT declaring the C2 (Path Signal Label Byte) Unstable defect condition. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the C2 (Path Signal Label Byte) Unstable defect condition. 5 UNEQ-P Defect Declared R/O Path – Unequipped Indicator (UNEQ-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the UNEQ-P defect condition. The Receive STS-3c POH Processor block will declare the UNEQ-P defect condition anytime that it receives at least five (5) consecutive STS-3c frames, in which the C2 byte was set to 0x00 (which indicates that the STS-3c SPE is 200 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 “Unequipped”). The Receive STS-3c POH Processor block will clear the UNEQ-P defect condition, if it receives at least five (5) consecutive STS-3c frames, in which the C2 byte was set to a value other than 0x00. 0 – Indicates that the Receive STS-3c POH Processor block is currently NOT declaring the UNEQ-P defect condition. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the UNEQ-P defect condition. Note: 1. The Receive STS-3c POH Processor block will not declare the UNEQ-P defect condition if it configured to expect to receive STS-3c frames with C2 bytes being set to “0x00” (e.g., if the “Receive STS-3c Path – Expected Path Label Value” Register is set to “0x00”). 2. The Address Locations of the “Receive STS-3c Path – Expected Path Label Value” Register is 0x1197 4 PLM-P Defect Declared R/O Path Payload Mismatch Indicator (PLM-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the PLM-P defect condition. The Receive STS-3c POH Processor block will declare the PLM-P defect condition, if it receives at least five (5) consecutive STS-3c frames, in which the C2 byte was set to a value other than that which it is expecting to receive. Whenever the Receive STS-3c POH Processor block is determining whether or not it should declare the PLM-P defect, it will check the contents of the following two registers. • The “Receive STS-3c Path – Received Path Label Value” Register (Address Location = 0x1196) • The “Receive STS-3c Path – Expected Path Label Value” Register (Address Location = 0x1197) The “Receive STS-3c Path – Expected Path Label Value” Register contains the value of the C2 bytes, that the Receive STS-3c POH Processor blocks expects to receive. The “Receive STS-3c Path – Received Path Label Value” Register contains the value of the C2 byte, that the Receive STS-3c POH Processor block has most received “validated” (by receiving this same C2 byte in five consecutive SONET frames). The Receive STS-3c POH Processor block will declare the PLM-P defect condition if the contents of these two register do not match. The Receive STS-3c POH Processor block will clear the PLM-P defect condition if whenever the contents of these two registers do match. 0 – Indicates that the Receive STS-3c POH Processor block is currently NOT declaring the PLM-P defect condition. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the PLM-P defect condition. Note: 3 RDI-P Defect Declared R/O The Receive STS-3c POH Processor block will clear the PLM-P defect, upon declaring the UNEQ-P defect condition. Path Remote Defect Indicator (RDI-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the RDI-P defect condition. If the Receive STS-3c POH Processor block is configured to support the “Single-bit RDI-P” function, then it will declare the RDI-P defect condition if Bit 5 (within the G1 byte of the incoming STS-3c frame) is set to “1” for “RDI- 201 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 P_THRD” number of incoming consecutive STS-3c SPEs. If the Receive STS-3c POH Processor block is configured to support the Enhanced RDI-P” (ERDI-P) function, then it will declare the RDI-P defect condition if Bits 5, 6 and 7 (within the G1 byte of the incoming STS-3c frame) are set to [0, 1, 0], [1, 0, 1] or [1, 1, 0] for “RDI-P_THRD” number of consecutive STS-3c SPEs. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the RDI-P defect condition. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the RDI-P defect condition. Note: 1. The user can specify the value for “RDI-P_THRD” by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the “Receive STS3c Path – SONET Receive RDI-P Register. 2. The Address Location of the “Receive STS-3c Path – SONET Receive RDI-P Registers is 0x1193 2 RDI-P Unstable Defect Declared R/O RDI-P (Path – Remote Defect Indicator) Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the “RDI-P Unstable” defect condition. The Receive STS-3c POH Processor block will declare a “RDI-P Unstable” defect condition whenever the “RDI-P Unstable Counter” reaches the value “RDI-P THRD”. The “RDI-P Unstable” counter is incremented for each time that the Receive STS-3c POH Processor block receives an RDI-P value that differs from that of the previous STS-3c frame. The “RDI-P Unstable” counter is cleared to “0” whenever the same RDI-P value is received in “RDIP_THRD” consecutive STS-3c frames. Note: Receiving a given RDI-P value, in “RDI-P_THRD” consecutive STS3c frames also clears this bit-field to “0”. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the “RDI-P Unstable” defect condition. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the “RDI-P Unstable” defect condition. Note: 1. The user can specify the value for “RDI-P_THRD” by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the “Receive STS3c Path – SONET Receive RDI-P Register. 2. The Address Location of the Receive STS-3c Path – SONET Receive RDIP Registers is 0x1193 1 LOP-P Defect Declared R/O Loss of Pointer Indicator (LOP-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the LOP-P (Loss of Pointer) defect condition. The Receive STS-3c POH Processor block will declare the LOP-P defect condition, if it cannot detect a valid pointer (H1 and H2 bytes, within the TOH) within 8 to 10 consecutive SONET frames. Further, the Receive STS-3c POH Processor block will declare the LOP-P defect condition, if it detects 8 to 10 consecutive NDF events. The Receive STS-3c POH Processor block will clear the LOP-P defect condition, whenever the Receive STS-3c POH Processor detects valid pointer bytes (e.g., the H1 and H2 bytes, within the TOH) and normal NDF value for three consecutive incoming STS-3c frames. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently 202 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 declaring the LOP-P defect condition. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the LOP-P defect condition. 0 AIS-P Defect Declared R/O Path AIS (AIS-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is currently declaring the AIS-P defect condition. The Receive STS-3c POH Processor block will declare the AIS-P defect condition if it detects all of the following conditions within three consecutive incoming STS-3c frames. a. The H1, H2 and H3 bytes are set to an “All Ones” pattern. b. The entire SPE is set to an “All Ones” pattern. The Receive STS-3c POH Processor block will clear the AIS-P defect condition when it detects a valid STS-3c pointer (H1 and H2 bytes) and a “set” or “normal” NDF for three consecutive STS-3c frames. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the AIS-P defect condition. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the AIS-P defect condition. Note: The Receive STS-3c POH Processor block will NOT declare the LOP-P defect condition if it detects an “All Ones” pattern in the H1, H2 and H3 bytes. It will, instead, declare the AIS-P defect condition. 203 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 123: Receive STS-3c Path – SONET Receive Path Interrupt Status – Byte 2 (Address Location= 0x1189) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Change in AIS-C Defect Condition Interrupt Status Change in LOP-C Defect Condition Interrupt Status Detection of AIS Pointer Interrupt Status Detection of Pointer Change Interrupt Status POH Capture Interrupt Status Change in TIM-P Defect Condition Interrupt Status Change in Path Trace Message Unstable Defect Condition Interrupt Status R/O RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Change in AIS-C Defect Condition Interrupt Status RUR DESCRIPTION Change in AIS-C (AIS Concatenation) Defect Condition Interrupt Status: This RESET-upon-READ bit-field permits indicates whether or not the “Change in AIS-C Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then an interrupt will be generated in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares the AIS-C defect condition with one of the STS-1 time-slots”; within the incoming STS-3c signal. b. Whenever the Receive STS-3c POH Processor block clears the AIS-C defect condition with one of the “STS-1 time-slots”; within the incoming STS-3c signal. 0 – Indicates that the “Change in AIS-C Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in AIS-C Defect Condition” Interrupt has occurred since the last read of this register. Note: 5 Change in LOP-C Defect Condition Interrupt Status RUR The user can determine the current state of AIS-C by reading out the contents of the “Receive STS-3c Path – AIS-C Status” Register (Address Locations: 0x11B3). Change in LOP-C (Loss of Pointer - Concatenation) Defect Condition Interrupt Status: This RESET-upon-READ bit-field permits indicates whether or not the “Change in LOP-C Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then an interrupt will be generated in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares the LOP-C defect condition with one of the “STS-1 time-slots”; within the incoming STS-3c signal. b. Whenever the Receive STS-3c POH Processor block clears the LOP-C defect condition with one of the “STS-1 timeslots”; within the incoming STS-3c signal. 204 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S 0 – Indicates that the “Change in LOP-C Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in LOP-C Defect Condition” Interrupt has occurred since the last read of this register. Note: 4 Detection of AIS Pointer Interrupt Status RUR The user can determine the current state of the LOP-C defect by reading out the contents of the “Receive STS-3c Path – LOP-C Status” Register (Address Locations: 0x11AB). Detection of AIS Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of AIS Pointer” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate this interrupt anytime it detects an “AIS Pointer” in the incoming STS-3c data stream. Note: An “AIS Pointer” is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an “All Ones” pattern. 0 – Indicates that the “Detection of AIS Pointer” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of AIS Pointer” interrupt has occurred since the last read of this register. 3 Detection of Pointer Change Interrupt Status RUR Detection of Pointer Change Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Pointer Change” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it accepts a new pointer value (e.g., H1 and H2 bytes, in the TOH bytes). 0 – Indicates that the “Detection of Pointer Change” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of Pointer Change” Interrupt has occurred since the last read of this register. 2 POH Capture Interrupt Status RUR Path Overhead Data Capture Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “POH Capture” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt once the Z5 byte (e.g., the last POH byte) has been loaded into the POH Capture Buffer. The contents of the POH Capture Buffer will remain intact for one SONET frame period. Afterwards, the POH data, for the next SPE will be loaded into the “POH Capture” buffer. 0 – Indicates that the “POH Capture” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “POH Capture” Interrupt has occurred since the last read of this register. Note: 205 The user can obtain the contents of the POH, within the most recently received SPE by reading out the contents of address locations “0xN0D3” through “0xN0F3”). XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1 Change in TIM-P Defect Condition Interrupt Status RUR Rev222...000...000 Change in TIM-P (Trace Identification Mismatch) Defect Condition Interrupt. This RESET-upon-READ bit-field indicates whether or not the “Change in TIM-P” Defect Condition interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive STS-3c POH Processor block declares theTIM-P defect condition. • Whenever the Receive STS-3c POH Processor block clears the TIM-P defect condition. 0 – Indicates that the “Change in TIM-P Defect Condition” Interrupt has not occurred since the last read of this register. 1 – Indicates that the “Change in TIM-P Defect Condition” Interrupt has occurred since the last read of this register. 0 Change in Path Trace Message Unstable Defect Condition Interrupt Status RUR Change in Path Trace Identification Message Unstable Defect Condition” Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in Path Trace Message Unstable Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate this interrupt in response to either of the following events. • Whenever the Receive STS-3c POH Processor block declare the “Path Trace Message Unstable” Defect Condition. • Whenever the Receive STS-3c POH Processor block clears the “Path Trace Message Unstable” defect condition. 0 – Indicates that the “Change in Path Trace Message Unstable Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in Path Trace Message Unstable Defect Condition” Interrupt has occurred since the last read of this register. 206 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 124: Receive STS-3c Path – SONET Receive Path Interrupt Status – Byte 1 (Address Location= 0x118A) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 New Path Trace Message Interrupt Status Detection of REI-P Event Interrupt Status Change in UNEQ-P Defect Condition Interrupt Status Change in PLM-P Defect Condition Interrupt Status New C2 Byte Interrupt Status Change in C2 Byte Unstable Defect Condition Interrupt Status Change in RDI-P Unstable Defect Condition Interrupt Status New RDI-P Value Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 New Path Trace Message Interrupt Status RUR DESCRIPTION New Path Trace Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New Path Trace Message” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted (or validated) and new Path Trace Message. 0 – Indicates that the “New Path Trace Message” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New Path Trace Message” Interrupt has occurred since the last read of this register. 6 Detection of REI-P Event Interrupt Status RUR Detection of REI-P Event Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of REI-P Event” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects an REI-P event within the incoming STS-3c data-stream. 0 – Indicates that the “Detection of REI-P Event” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of REI-P Event” Interrupt has occurred since the last read of this register. 5 Change in UNEQP Defecft Condition Interrupt Status RUR Change in UNEQ-P (Path – Unequipped) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in UNEQ-P Defect Condition” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3c POH Processor block declares the UNEQ-P Defect Condition. • Whenever the Receive STS-3c POH Processor block clears the UNEQP Defect Condition. 0 – Indicates that the “Change in UNEQ-P Defecft Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in UNEQ-P Defect Condition” Interrupt has 207 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 occurred since the last read of this register. Note: 1. The user can determine the current state of the UNEQ-P defect condition by reading out the state of Bit 5 (UNEQ-P Defect Declared) within the “Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register. 2. The Address Location of the Receive STS-3c Path – SONET Receive POH Status – Byte 0” Registers is 0x1187 4 Change in PLM-P Defect Condition Interrupt Status RUR Change in PLM-P (Path – Payload Mismatch) Defect Condition Interrupt Status: This RESET-upon-READ bit indicates whether or not the “Change in PLMP Defect Condition” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. • When the Receive STS-3c POH Processor block declares the “PLM-P” Defect Condition. • When the Receive STS-3c POH Processor block clears the “PLM-P” Defect Condition. 0 – Indicates that the “Change in PLM-P Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in PLM-P Defect Condition” Interrupt has occurred since the last read of this register. 3 New C2 Byte Interrupt Status RUR New C2 Byte Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New C2 Byte” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 – Indicates that the “New C2 Byte” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New C2 Byte” Interrupt has occurred since the last read of this register. 2 Change in C2 Byte Unstable Defect Condition Interrupt Status RUR Change in C2 Byte Unstable Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in C2 Byte Unstable Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. • When the Receive STS-3c POH Processor block declares the “C2 Byte Unstable” defect condition. • When the Receive STS-3c POH Processor block clears the “C2 Byte Unstable” defect condition. 0 – Indicates that the “Change in C2 Byte Unstable Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in C2 Byte Unstable Defect Condition” Interrupt has occurred since the last read of this register. Note: 1. The user can determine the current state of “C2 Byte Unstable Defect Condition” by reading out the state of Bit 6 (C2 Byte Unstable Defect 208 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Declared) within the “Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register. 2. The Address Location of the Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register is 0x1187 1 Change in RDI-P Unstable Defect Condition Interrupt Status RUR Change in RDI-P Unstable Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in RDI-P Unstable Condition” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. • When the Receive STS-3c POH Processor block declares an “RDI-P Unstable” defect condition. • When the Receive STS-3c POH Processor block clears the “RDI-P Unstable” defect condition. 0 – Indicates that the “Change in RDI-P Unstable Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in RDI-P Unstable Defect Condition” Interrupt has occurred since the last read of this register. Note: 1. The user can determine the current state of “RDI-P Unstable Defectg condition” by reading out the state of Bit 2 (RDI-P Unstable Defect Declared) within the “Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register. 2. The Address Location of the Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register is 0x1187 0 New RDI-P Value Interrupt Status RUR New RDI-P Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New RDI-P Value” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate this interrupt anytime it receives and “validates” a new RDI-P value. 0 – Indicates that the “New RDI-P Value” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New RDI-P Value” Interrupt has occurred since the last read of this register. Note: 1. The user can obtain the “New RDI-P Value” by reading out the contents of the “RDI-P ACCEPT[2:0]” bit-fields. These bit-fields are located in Bits 6 through 4, within the “Receive STS-3c Path – SONET Receive RDI-P Register”. 2. The Address Location of the Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register is 0x1193 209 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 125: Receive STS-3c Path – SONET Receive Path Interrupt Status – Byte 0 (Address Location= 0x118B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Detection of B3 Byte Error Interrupt Status Detection of New Pointer Interrupt Status Detection of Unknown Pointer Interrupt Status Detection of Pointer Decrement Interrupt Status Detection of Pointer Increment Interrupt Status Detection of NDF Pointer Interrupt Status Change of LOP-P Defect Condition Interrupt Status Change of AIS-P Defect Condition Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Detection of B3 Byte Error Interrupt Status RUR DESCRIPTION Detection of B3 Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of B3 Byte Error” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a B3 byte error in the incoming STS-3c data stream. 0 – Indicates that the “Detection of B3 Byte Error” Interrupt has NOT occurred since the last read of this interrupt. 1 – Indicates that the “Detection of B3 Byte Error” Interrupt has occurred since the last read of this interrupt. 6 Detection of New Pointer Interrupt Status RUR Detection of New Pointer Interrupt Status: This RESET-upon-READ indicates whether the “Detection of New Pointer” interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-3c frame. Note: Pointer Adjustments with NDF will not generate this interrupt. 0 – Indicates that the “Detection of New Pointer” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of New Pointer” Interrupt has occurred since the last read of this register. 5 Detection of Unknown Pointer Interrupt Status RUR Detection of Unknown Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Unknown Pointer” interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime that it detects a “pointer” that does not fit into any of the following categories. • An Increment Pointer • A Decrement Pointer • An NDF Pointer • An AIS (e.g., All Ones) Pointer • New Pointer 0 – Indicates that the “Detection of Unknown Pointer” interrupt has NOT 210 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 occurred since the last read of this register. 1 – Indicates that the “Detection of Unknown Pointer” interrupt has occurred since the last read of this register. 4 Detection of Pointer Decrement Interrupt Status RUR Detection of Pointer Decrement Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Pointer Decrement” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a “Pointer Decrement” event. 0 – Indicates that the “Detection of Pointer Decrement” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of Pointer Decrement” interrupt has occurred since the last read of this register. 3 Detection of Pointer Increment Interrupt Status RUR Detection of Pointer Increment Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Pointer Increment” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a “Pointer Increment” event. 0 – Indicates that the “Detection of Pointer Increment” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of Pointer Increment” interrupt has occurred since the last read of this register. 2 Detection of NDF Pointer Interrupt Status RUR Detection of NDF Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of NDF Pointer” interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 – Indicates that the “Detection of NDF Pointer” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of NDF Pointer” interrupt has occurred since the last read of this register. 1 Change of LOPP Defect Condition Interrupt Status RUR Change of LOP-P Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in LOP-P Defect Condition” interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares the “LOP-P” defect condition. b. Whenever the Receive “STS-3c POH Processor” block clears the LOP-P defect condition. 0 – Indicates that the “Change in LOP-P Defect Condition” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in LOP-P Defect Condition” interrupt has occurred since the last read of this register. 211 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Note: 1. The user can determine if the Receive STS-3c POH Processor block is currently declaring the LOP-P defect condition by reading out the state of Bit 1 (LOP-P Defect Declared) within the “Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register. 2. The Address Location of the “Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register is 0x1187 0 Change of AISP Defect Condition Interrupt Status RUR Change of AIS-P Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of AIS-P Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive STS-3c POH Processor block declares the AISP defect condition. • Whenever the Receive STS-3c POH Processor block clears the AIS-P defect condition. 0 – Indicates that the “Change of AIS-P Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of AIS-P Defect Condition” Interrupt has occurred since the last read of this register. Note: 1. The user can determine if the Receive STS-3c POH Processor block is currently declaring the AIS-P defect condition by reading out the state of Bit 0 (AIS-P Defect Declared) within the “Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register. 2. The Address Location of the Receive STS-3c Path – SONET Receive POH Status – Byte 0” Registers is 0x1187 212 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 126: Receive STS-3c Path – SONET Receive Path Interrupt Enable – Byte 2 (Address Location= 0x118D) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 New K3 Byte Interrupt Enable Change in AIS-C Defect Condition Interrupt Enable Change in LOP-C Defect Condition Interrupt Enable Detection of AIS Pointer Interrupt Enable Detection of Pointer Change Interrupt Enable POH Capture Interrupt Enable Change in TIM-P Defect Condition Interrupt Enable Change in Path Trace Message Unstable Defect Condition Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 New K3 Byte Interrupt Enable R/W DESCRIPTION New K3 Byte Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “New K3 Byte” Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted (or validated) and new K3 Byte. 0 – Disables the “New K3 Byte” Interrupt. 1 – Enables the “New K3 Byte” Interrupt. 6 Change in AIS-C Defect Condition Interrupt Enable R/W Change in AIS-C (AIS Concatenation) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in AIS-C Defect Condition” Interrupt. If this interrupt is enabled, then an interrupt will generated in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares the AIS-C defect condition within one of the STS-1 time-slots; within the incoming STS-3c signal. b. Whenever the Receive STS-3c POH Processor block clears the AIS-C defect condition with one of the STS-1 time-slots; within the incoming STS-3c signal. 0 – Disables the “Change in AIS-C Defect Condition” Interrupt. 1 – Enables the “Change in AIS-C Defect Condition” Interrupt Note: This bit-field is only valid if the XRT94L33 is receiving an STS-3c signal. This bit-field is only valid for the following Address Locations: “0x118D” (for STS-3c ) 5 Change in LOP-C Condition Interrupt Enable R/W Change in LOP-C (Loss of Pointer - Concatenation) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in LOP-C Defect Condition” Interrupt. If this interrupt is enabled, then an interrupt will generated in response to either of the following events. 213 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 a. Whenever the Receive STS-3c POH Processor block declares the LOP-C defect condition with one of the STS-1 timeslots; within the incoming STS-3c signal. b. Whenever the Receive STS-3c POH Processor block clears the LOP-C defect condition with one of the STS-1 timeslots; within the incoming STS-3c signal. 0 – Disables the “Change in LOP-C Defect Condition” Interrupt. 1 – Enables the “Change in LOP-C Defect Condition” Interrupt Note: This bit-field is only valid if the XRT94L33 is receiving an STS-3c signal. This bit-field is only valid for the following Address Locations: “0x118D” (for STS-3c) 4 Detection of AIS Pointer Interrupt Enable R/W Detection of AIS Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of AIS Pointer” interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects an “AIS Pointer”, in the incoming STS-3c data stream. Note: An “AIS Pointer” is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an “All Ones” Pattern. 0 – Disables the “Detection of AIS Pointer” Interrupt. 1 – Enables the “Detection of AIS Pointer” Interrupt. 3 Detection of Pointer Change Interrupt Enable R/W Detection of Pointer Change Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of Pointer Change” Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted a new pointer value. 0 – Disables the “Detection of Pointer Change” Interrupt. 1 – Enables the “Detection of Pointer Change” Interrupt. 2 POH Capture Interrupt Enable R/W Path Overhead Data Capture Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “POH Capture” Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt once the Z5 byte (e.g., the last POH byte) has been loaded into the POH Capture Buffer. The contents of the POH Capture Buffer will remain intact for one SONET frame period. Afterwards, the POH data for the next SPE will be loaded into the “POH Capture” Buffer. 0 – Disables the “POH Capture” Interrupt 1 – Enables the “POH Capture” Interrupt. 1 Change in TIM-P Defect Condition Interrupt Enable R/W Change in TIM-P Condition Interrupt: (Trace Identification Mismatch) Defect This READ/WRITE bit-field permits the user to either enable or disable the “Change in TIM-P Condition” interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor 214 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S block will generate an interrupt in response to either of the following events. • Whenever the Receive STS-3c POH Processor block declares the TIM-P defect condition. • Whenever the Receive STS-3c POH Processor block clears the TIM-P defect condition. 0 – Disables the “Change in TIM-P Condition” Interrupt. 1 – Enables the “Change in TIM-P Condition” Interrupt. 0 Change in Path Trace Message Unstable Defect Condition Interrupt Enable R/W Change in “Path Trace Message Unstable Defect Condition” Interrupt Status: This READ/WRITE bit-field permits the user to either enable or disable the “Change in Path Trace Message Unstable Defect Condition” Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive STS-3c POH Processor block declares the “Path Trace Message Unstable” defect Condition. • Whenever the Receive STS-3c POH Processor block clears the “Path Trace Message Unstable” defect Condition. 0 – Disables the “Change in Path Trace Message Unstable Defect Condition” interrupt. 1 – Enables the “Change in Path Trace Message Unstable Defect Condition” interrupt. 215 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 127: Receive STS-3c Path – SONET Receive Path Interrupt Enable – Byte 1 (Address Location= 0x118E) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 New Path Trace Message Interrupt Enable Detection of REI-P Event Interrupt Enable Change in UNEQ-P Defect Condition Interrupt Enable Change in PLM-P Defect Condition Interrupt Enable New C2 Byte Interrupt Enable Change in C2 Byte Unstable Defect Condition Interrupt Enable Change in RDI-P Unstable Defect Condition Interrupt Enable New RDI-P Value Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 New Path Trace Message Interrupt Enable R/W DESCRIPTION New Path Trace Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “New Path Trace Message” Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted (or validated) and new Path Trace Message. 0 – Disables the “New Path Trace Message” Interrupt. 1 – Enables the “New Path Trace Message” Interrupt. 6 Detection of REI-P Event Interrupt Enable R/W Detection of REI-P Event Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of REI-P Event” Interrupt. If this interrupt is enabled, then he Receive STS-3c POH Processor block will generate an interrupt anytime it detects an REI-P event within the coming STS-3c data-stream. 0 – Disables the “Detection of REI-P Event” Interrupt. 1 – Enables the “Detection of REI-P Event” Interrupt. 5 Change in UNEQ-P Defect Condition Interrupt Enable R/W Change in UNEQ-P (Path – Unequipped) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in UNEQ-P Defect Condition” interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3c POH Processor block declares the UNEQ-P Defect Condition. • Whenever the Receive STS-3c POH Processor block clears the UNEQP Defect Condition. 0 – Disables the “Change in UNEQ-P Defect Condition” Interrupt. 1 – Enables the “Change in UNEQ-P Defect Condition” Interrupt. 4 Change in PLMP Defect Condition Interrupt Enable R/W Change in PLM-P (Path – Payload Label Mismatch) Defect Condition Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the “Change in PLM-P Defect Condition” interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block 216 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3c POH Processor block declares the “PLM-P” Defect Condition. • Whenever the Receive STS-3c POH Processor block clears the “PLMP” Defect Condition. 0 – Disables the “Change in PLM-P Defect Condition” Interrupt. 1 – Enables the “Change in PLM-P Defect Condition” Interrupt. 3 New C2 Byte Interrupt Enable R/W New C2 Byte Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “New C2 Byte” Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 – Disables the “New C2 Byte” Interrupt. 1 – Enables the “New C2 Byte” Interrupt. Note: 1. The user can obtain the value of this “New C2” byte by reading the contents of the “Receive STS-3c Path – Received Path Label Value” Register. 2. The Address Location of the Receive STS-3c Path – Received Path Label Value” Register is 0x1196 2 Change in C2 Byte Unstable Defect Condition Interrupt Enable R/W Change in C2 Byte Unstable Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in C2 Byte Unstable Defect Condition” Interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive STS-3c POH Processor block declares the “C2 Byte Unstable” defect condition. • Whenever the Receive STS-3c POH Processor block clears the “C2 Byte Unstable” defect condition. 0 – Disables the “Change in C2 Byte Unstable Condition” Interrupt. 1 – Enables the “Change in C2 Byte Unstable Condition” Interrupt. 1 Change in RDIP Unstable Defect Condition Interrupt Enable R/W Change in RDI-P Unstable Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in RDI-P Unstable Defect Condition” interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive STS-3c POH Processor block declares an “RDIP Unstable defect” condition. • Whenever the Receive STS-3c POH Processor block clears the “RDI-P Unstable defect” condition. 0 – Disables the “Change in RDI-P Unstable Defect Condition” Interrupt. 1 – Enables the “Change in RDI-P Unstable Defect Condition” Interrupt. 0 New RDI-P Value Interrupt Enable R/W New RDI-P Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “New RDI-P Value” interrupt. If this interrupt is enabled, then the Receive STS-3c POH Processor block 217 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 will generate this interrupt anytime it receives and “validates” a new RDI-P value. 0 – Disables the “New RDI-P Value” Interrupt. 1 – Enable the “New RDI-P Value” Interrupt. 218 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 128: Receive STS-3c Path – SONET Receive Path Interrupt Enable – Byte 0 (Address Location= 0x118F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Detection of B3 Byte Error Interrupt Enable Detection of New Pointer Interrupt Enable Detection of Unknown Pointer Interrupt Enable Detection of Pointer Decrement Interrupt Enable Detection of Pointer Increment Interrupt Enable Detection of NDF Pointer Interrupt Enable Change of LOP-P Defect Condition Interrupt Enable Change of AIS-P Defect Condition Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Detection of B3 Byte Error Interrupt Enable R/W DESCRIPTION Detection of B3 Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of B3 Byte Error” Interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a B3-byte error in the incoming STS-3c datastream. 0 – Disables the “Detection of B3 Byte Error” interrupt. 1 – Enables the “Detection of B3 Byte Error” interrupt. 6 Detection of New Pointer Interrupt Enable R/W Detection of New Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of New Pointer” interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-3c frame. Note: Pointer Adjustments with NDF will not generate this interrupt. 0 – Disables the “Detection of New Pointer” Interrupt. 1 – Enables the “Detection of New Pointer” Interrupt. 5 Detection of Unknown Pointer Interrupt Enable R/W Detection of Unknown Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of Unknown Pointer” interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a “Pointer Adjustment” that does not fit into any of the following categories. • An Increment Pointer. • A Decrement Pointer • An NDF Pointer • AIS Pointer • New Pointer. 0 – Disables the “Detection of Unknown Pointer” Interrupt. 1 – Enables the “Detection of Unknown Pointer” Interrupt. 4 Detection of Pointer Decrement Interrupt Enable R/W Detection of Pointer Decrement Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the “Detection of Pointer Decrement” Interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an 219 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 interrupt anytime it detects a “Pointer-Decrement” event. 0 – Disables the “Detection of Pointer Decrement” Interrupt. 1 – Enables the “Detection of Pointer Decrement” Interrupt. 3 Detection of Pointer Increment Interrupt Enable R/W Detection of Pointer Increment Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of Pointer Increment” Interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects a “Pointer Increment” event. 0 – Disables the “Detection of Pointer Increment” Interrupt. 1 – Enables the “Detection of Pointer Increment” Interrupt. 2 Detection of NDF Pointer Interrupt Enable R/W Detection of NDF Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of NDF Pointer” Interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 – Disables the “Detection of NDF Pointer” interrupt. 1 – Enables the “Detection of NDF Pointer” interrupt. 1 Change of LOPP Defect Condition Interrupt Enable R/W Change of LOP-P Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in LOP (Loss of Pointer)” Defect Condition interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor will generate an interrupt in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares the LOP-P defect condition. b. Whenever the Receive STS-3c POH Processor block clears the LOP-P defect condition. 0 – Disable the “Change of LOP-P Defect Condition” Interrupt. 1 – Enables the “Change of LOP-P Defect Condition” Interrupt. Note: 1. The user can determine if the Receive STS-3c POH Processor block is currently declaring the LOP-P defect condition by reading out the contents of Bit 1 (LOP-P Defect Declared) within the “Receive STS-3c Path – SONET Receive POH Status – Byte 0”. 2. The Address Location of the Receive STS-3c Path – SONET Receive POH Status Byte 0” Register is 0x1187 0 Change of AIS-P Defect Condition Interrupt Enable R/W Change of AIS-P Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of AIS-P (Path AIS) Defect Condition” interrupt. If the user enables this interrupt, then the Receive STS-3c POH Processor block will generate an interrupt in response to either of the following events. a. Whenever the Receive STS-3c POH Processor block declares the “AIS-P” defect condition. b. Whenever the Receive STS-3c POH Processor block clears the “AIS-P” defect condition. 0 – Disables the “Change of AIS-P Defect Condition” Interrupt. 1 – Enables the “Change of AIS-P Defect Condition” Interrupt. Note: 220 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S 1. The user can determine if the Receive STS-3c POH Processor block is currently declaring the AIS-P defect condition by reading out the contents of Bit 0 (AIS-P Defect Declared) within the “Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register. 2. The Address Location of the Receive STS-3c Path – SONET Receive POH Status – Byte 0” Register is 0x1187 221 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 129: Receive STS-3c Path – SONET Receive RDI-P Register (Address Location= 0x1193) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 RDI-P_ACCEPT[2:0] BIT 2 BIT 1 BIT 0 RDI-P THRESHOLD[3:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6–4 RDIP_ACCEPT[2:0] R/O DESCRIPTION Accepted RDI-P Value: These READ-ONLY bit-fields contain the value of the most recently “accepted” RDI-P (e.g., bits 5, 6 and 7 within the G1 byte) value that has been accepted by the Receive STS-3c POH Processor block. Note: 3–0 RDI-P THRESHOLD[3:0] R/W A given RDI-P value will be “accepted” by the Receive STS-3c POH Processor block, if this RDI-P value has been consistently received in “RDI-P THRESHOLD[3:0]” number of SONET frames. RDI-P Threshold[3:0]: These READ/WRITE bit-fields permit the user to defined the “RDI-P Acceptance Threshold” for the Receive STS-3c POH Processor Block. The “RDI-P Acceptance Threshold” is the number of consecutive SONET frames, in which the Receive STS-3c POH Processor block must receive a given RDI-P value, before it “accepts” or “validates” it. The most recently “accepted” RDI-P value is written into the “RDI-P ACCEPT[2:0]” bit-fields, within this register. 222 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 130: Receive STS-3c Path – Received Path Label Value (Address Location= 0x1196) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Received_C2_Byte_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 1 1 1 1 1 1 1 1 BIT NUMBER NAME TYPE 7–0 Received C2 Byte Value[7:0] R/O DESCRIPTION Received “Filtered” C2 Byte Value: These READ-ONLY bit-fields contain the value of the most recently “accepted” C2 byte, via the Receive STS-3c POH Processor block. The Receive STS-3c POH Processor block will “accept” a C2 byte value (and load it into these bit-fields) if it has received a consistent C2 byte, in five (5) consecutive SONET frames. Note: 1. The Receive STS-3c POH Processor block uses this register, along the “Receive STS-3c Path – Expected Path Label Value” Register, when declaring or clearing the UNEQ-P and PLM-P defect conditions. 2. The Address Location of the Receive STS-3c Path – Expected Path Label Value” Register is 0x1197 Table 131: Receive STS-3c Path – Expected Path Label Value (Address Location= 0x1197) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 Expected_C2_Byte_Value[7:0] BIT NUMBER NAME TYPE 7–0 Expected C2 Byte Value[7:0] R/W DESCRIPTION Expected C2 Byte Value: These READ/WRITE bit-fields permits the user to specify the C2 (Path Label Byte) value, that the Receive STS-3c POH Processor block should expect when declaring or clearing the UNEQ-P and PLM-P defect conditions. If the contents of the “Received C2 Byte Value[7:0]” (see “Receive STS-3c Path – Received Path Label Value” register) matches the contents in these register, then the Receive STS3c POH will not declare any defect conditions. NOTE: The Receive STS-3c POH Processor block uses this register, along with the “Receive STS-3c Path – Receive Path Label Value” Register (Address Location = 0x1196), when declaring or clearing the UNEQ-P and PLM-P defect conditions. 223 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 132: Receive STS-3c Path – B3 Byte Error Count Register – Byte 3 (Address Location= 0x1198) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B3_Byte_Error_Count[31:24] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 B3_Byte_Error_Count[31:24] RUR DESCRIPTION B3 Byte Error Count – MSB: This RESET-upon-READ register, along with “Receive STS-3c Path – B3 Byte Error Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a B3 byte error. Note: 1. If the Receive STS-3c POH Processor block is configured to count B3 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B3 byte (of each incoming STS-3c SPE) that are in error. 2. If the Receive STS-3c POH Processor block is configured to count B3 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3c SPE that contains an erred B3 byte. Table 133: Receive STS-3c Path – B3 Byte Error Count Register – Byte 2 (Address Location= 0x1199) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B3_Byte_Error_Count[23:16] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 B3_Byte_Error_Count[23:16] RUR DESCRIPTION B3 Byte Error Count (Bits 23 through 16): This RESET-upon-READ register, along with “Receive STS-3c Path – B3 Byte Error Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a B3 byte error. Note: 1. If the Receive STS-3c POH Processor block is configured to count B3 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B3 byte (of each incoming STS-3c SPE) that are in error. 2. If the Receive STS-3c POH Processor block is configured to count B3 byte errors on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3c SPE that contains an erred B3 byte. 224 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 134: Receive STS-3c Path – B3 Byte Error Count Register – Byte 1 (Address Location= 0x119A) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B3_Byte_Error_Count[15:8] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 B3_Byte_ Error_Count[15:8] RUR DESCRIPTION B3 Byte Error Count – (Bits 15 through 8): This RESET-upon-READ register, along with “Receive STS-3c Path – B3 Byte Error Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a B3 byte error. Note: 1. If the Receive STS-3c POH Processor block is configured to count B3 byte errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B3 byte (of each incoming STS-3c SPE) that are in error. 2. If the Receive STS-3c POH Processor block is configured to count B3 byte errors on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3c SPE that contains an erred B3 byte. Table 135: Receive STS-3c Path – B3 Byte Error Count Register – Byte 0 (Address Location= 0x119B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B3_Byte_Error_Count[7:0] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 B3_Byte_Error_Count[7:0] RUR DESCRIPTION B3 Byte Error Count – LSB: This RESET-upon-READ register, along with “Receive STS-3c Path – B3 Byte Error Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a B3 byte error. Note: 1. If the Receive STS-3c POH Processor block is configured to count B3 byte errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B3 byte (or each incoming STS-3c SPE) that are in error. 2. If the Receive STS-3c POH Processor block is configured to count B3 byte errors on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3c SPE that contains an erred B3 byte. 225 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 136: Receive STS-3c Path – REI-P Event Count Register – Byte 3 (Address Location= 0x119C) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REI-P_Event_Count[31:24] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 REI-P_Event_Count[31:24] RUR DESCRIPTION REI-P Event Count – MSB: This RESET-upon-READ register, along with “Receive STS-3c Path – REI-P Event Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a Path – Remote Error Indicator event within the incoming STS-3c SPE data-stream. Note: 1. If the Receive STS-3c POH Processor block is configured to count REI-P events on a “per-bit” basis, then it will increment this 32-bit counter by the nibble-value within the REI-P field of the incoming G1 byte within each incoming STS-3c SPE. 2. If the Receive STS-3c POH Processor block is configured to count REI-P events on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3c SPE that contains a “non-zero” REI-P value. Table 137: Receive STS-3c Path – REI-P Event Error Count Register – Byte 2 (Address Location= 0x119D) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REI-P_Event_Count[23:16] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 REI-P_Event_Count[23:16] RUR DESCRIPTION REI-P Event Count (Bits 23 through 16): This RESET-upon-READ register, along with “Receive STS-3c Path – REI-P Event Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS3c POH Processor block detects a Path – Remote Error Indicator event within the incoming STS-3c SPE data-stream. Note: 1. If the Receive STS-3c POH Processor block is configured to count REI-P events on a “per-bit” basis, then it will increment this 32-bit counter by the nibble-value within the REI-P field of the incoming G1 byte within each incoming STS-3c frame. 2. If the Receive STS-3c POH Processor block is configured to count REI-P events on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3c SPE that contains a “non-zero” REI-P value. 226 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 138: Receive STS-3c Path – REI-P Event Count Register – Byte 1 (Address Location=0x119E) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REI-P_Event_Count[15:8] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 REI-P_Event_Count[15:8] RUR DESCRIPTION REI-P Event Count – (Bits 15 through 8) This RESET-upon-READ register, along with “Receive STS-3c Path – REI-P Event Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive STS3c POH Processor block detects a Path –Remote Error Indicator event within the incoming STS-3c SPE data-stream. Note: 1. If the Receive STS-3c POH Processor block is configured to count REI-P events on a “per-bit” basis, then it will increment this 32-bit counter by the nibble-value within the REI-P field of the incoming G1 byte within the incoming STS-3c SPE. 2. If the Receive STS-3c POH Processor block is configured to count REI-P events on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3c SPE that contains a non-zero REI-P value. 227 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 139: Receive STS-3c Path – REI-P Event Count Register – Byte 0 (Address Location= 0x119F) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-P_Event_Count[7:0] BIT NUMBER NAME TYPE 7–0 REI-P_Event_Count[7:0] RUR DESCRIPTION REI-P Event Count – LSB: This RESET-upon-READ register, along with “Receive STS-3c Path – REI-P Event Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive STS-3c POH Processor block detects a Path – Remote Error Indicator event within the incoming STS-3c SPE data-stream. Note: 1. If the Receive STS-3c POH Processor block is configured to count REI-P events on a “per-bit” basis, then it will increment this 32-bit counter by the nibble-value within the REI-P field of the incoming G1 byte. 2. If the Receive STS-3c POH Processor block is configured to count REI-P events on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3c SPE that contains a “non-zero” REI-P value. 228 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 140: Receive STS-3c Path – Receive Path Trace Message Buffer Control Register (Address Location=0x11A3) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 BIT 2 New Message Ready Receive Path Trace Message Buffer Read Select Receive Path Trace Message Accept Threshold Path Trace Message Alignment Message Type BIT 1 BIT 0 Receive Path Trace Message Length[1:0] R/O R/O R/O R/W R/W R/W R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–5 Unused R/O 5 New Message Ready R/O DESCRIPTION New Message Ready: This READ/WRITE bit-field indicates whether or not the Receive STS-3c POH Processor block has (1) accepted a new Receive Path Trace Message, and (2) has loaded this new message into the Receive Path Trace Message buffer, since the last read of this register. 0 – Indicates that the Receive STS-3c POH Processor block has (1) NOT accepted a new Path Trace Message, nor (2) has the Receive STS-3c POH Processor block loaded any new messages into the Receive Path Trace Message buffer, since the last read of this register. 1 – Indicates that the Receive STS-3c POH Processor block has (1) accepted a new Path Trace Message, and (2) has loaded this new message into the Receive Path Trace Message buffer, since the last read of this register. 4 Received Path Trace Message Buffer Read Select R/W Receive Path Trace Message Buffer Read Selection: This READ/WRITE bit-field permits a user to specify which of the following Receive Path Trace Message buffer segments that the Microprocessor will read out, whenever it reads out the contents of the Receive Path Trace Message Buffer. a. The “Actual” Receive Path Trace Message Buffer. The “Actual” Receive Path Trace Message Buffer contains the contents of the most recently received (and accepted) Path Trace Message via the incoming STS-3c data-stream. b. The “Expected” Receive Path Trace Message Buffer. The “Expected” Receive Path Trace Message Buffer contains the contents of the Path Trace Message that the user “expects” to receive. The contents of this particular buffer are usually specified by the user. 0 – Executing a READ to the Receive Path Trace Message Buffer, will return contents within the “Actual” Receive Path Trace Message” buffer. 1 – Executing a READ to the Receive Path Trace Message Buffer will return contents within the “Expected” Receive Path Trace Message Buffer”. Note: 3 Path Trace Message Accept Threshold R/W In the case of the Receive STS-3c POH Processor block, the “Receive Path Trace Message Buffer” is located at Address Location = 0x1500 through 0x153F Path Trace Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Receive STS-3c POH Processor block must receive a given Receive Path Trace Message, before it is accepted and loaded into the 229 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 “Actual” Receive Path Trace Message Buffer, as described below. 0 – Configures the Receive STS-3c POH Processor block to accept the incoming Path Trace Message after it has received it the third time in succession. 1 – Configures the Receive STS-3c POH Processor block to accept the incoming Path Trace Message after it has received in the fifth time in succession. 2 Path Trace Message Alignment Type R/O Path Trace Message Alignment Type: This READ/WRITE bit-field permits a user to specify how the Receive STS-3c POH Processor block will locate the boundary of the incoming Path Trace Message (within the incoming STS-3c data-stream), as indicated below. 0 – Configures the Receive STS-3c POH Processor block to expect the Path Trace Message boundary to be denoted by a “Line Feed” character. 1 – Configures the Receive STS-3c POH Processor block to except the Path Trace Message boundary to be denoted by the presence of a “1” in the MSB (most significant bit) of the first byte (within the incoming Path Trace Message). In this case, all of the remaining bytes (within the incoming Path Trace Message) will each have a “0” within their MSBs. 1–0 Path Trace Message Length[1:0] R/W Path Trace Message Length[1:0]: These READ/WRITE bit-fields permit the user to specify the length of the Receive Path Trace Message that the Receive STS-3c POH Processor block will accept and load into the “Actual” Receive Path Trace Message Buffer. The relationship between the content of these bit-fields and the corresponding Receive Path Trace Message Length is presented below. MSG LENGTH[1:0] Resulting Path Trace Message Length 00 1 Byte 01 16 Bytes 10/11 64 Bytes 230 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 141: Receive STS-3c Path – Pointer Value – Byte 1 (Address Location= 0x11A6) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Unused BIT 0 Current_Pointer Value MSB[9:8] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-2 Unused R/O 1–0 Current_Pointer_Value_MSB[1:0] R/O DESCRIPTION Current Pointer Value – MSB: These READ-ONLY bit-fields, along with that from the “Receive STS-3c Path – Pointer Value – Byte 0” Register combine to reflect the current value of the pointer that the “Receive STS-3c POH Processor” block is using to locate the STS-3c SPE within the incoming STS-3c data stream. Note: These register bits comprise the significant bits of the Pointer Value. two-most Table 142: Receive STS-3c Path – Pointer Value – Byte 0 (Address Location=0x11A7) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Current_Pointer_Value_LSB[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Current_Pointer_Value_LSB[7:0] R/O DESCRIPTION Current Pointer Value – LSB: These READ-ONLY bit-fields, along with that from the “Receive STS-3c Path – Pointer Value – Byte 1” Register combine to reflect the current value of the pointer that the “Receive STS-3c POH Processor” block is using to locate the STS-3c SPE within the incoming STS-3c data stream. Note: 231 These register bits comprise the Lower Byte value of the Pointer Value. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 143: Receive STS-3c Path – LOP-C Status Register (Address Location=0x11AB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 LOP-C Defect Declared STS1 time-slot # 3 LOP-C Defect Declared STS1 time-slot # 2 Unused R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-3 Unused R/O 2 LOP-C Defect Declared – STS-1 Time-Slot # 3 R/O DESCRIPTION Loss of Pointer – Concatenation Defect Declared – STS-1 Time-Slot # 3: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is declaring the LOP-C (Loss of Pointer – Concatenation) defect condition with STS-1 time-slot # 3 (within the incoming STS-3c signal). The Receive STS-3c POH Processor block will declare the LOPC defect condition, with STS-1 time-slot # 3; if it does not receive the “Concatenation Indicator” value of “0x93FF” in the H1, H2 bytes (associated with STS-1 time-slot # 3) for 8 consecutive STS-3c frames. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the LOP-C defect condition with STS-1 time-slot # 3 within the incoming STS-3c data-stream. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the LOP-C defect condition with STS-1 timeslot # 3 within the incoming STS-3c data-stream. Note: 1 LOP-C Defect Declared – STS-1 Time-Slot # 2 R/O This bit-field is only valid if the XRT94L33 is receiving and processing an STS-3c signal. Loss of Pointer – Concatenation Defect Declared – STS-1 Time-Slot # 2: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is declaring the LOP-C (Loss of Pointer – Concatenation) defect condition with STS-1 time-slot # 2 (within the incoming STS-3c signal). The Receive STS-3c POH Processor block will declare the LOPC defect condition, with STS-1 time-slot # 2; if it does not receive the “Concatenation Indicator” value of “0x93FF” in the H1, H2 bytes (associated with STS-1 time-slot # 2) for 8 consecutive STS-3c frames. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the LOP-C defect condition with STS-1 time-slot # 2 within the incoming STS-3c data-stream. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the LOP-C defect condition with STS-1 timeslot # 2 within the incoming STS-3c data-stream. Note: 0 Unused R/O 232 This bit-field is only valid if the XRT94L33 is receiving and processing an STS-3c signal. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 144: Receive STS-3c Path – AIS-C Status Register (Address Location=0x11B3) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 AIS-C Defect Declared STS1 time-slot # 3 AIS-C Defect Declared STS1 time-slot # 2 Unused R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-3 Unused R/O 2 AIS-C Defect Declared – STS-1 Time-Slot # 3 R/O DESCRIPTION AIS – Concatenation Defect Declared – STS-1 Time-Slot # 3: This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is declaring the AIS-C (AIS – Concatenation) defect condition with STS-1 timeslot # 3 (within the incoming STS-3c signal). The Receive STS-3c POH Processor block will declare the AISC defect condition, with STS-1 time-slot # 3; if it receives an “All Ones” string; in the H1, H2 bytes (associated with STS-1 timeslot # 3) for 3 consecutive STS-3c frames. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the AIS-C defect condition with STS-1 time-slot # 3. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the AIS-C defect condition with STS-1 timeslot # 3. Note: 1 AIS-C Defect Declared – STS-1 Time-Slot # 2 R/O This bit-field is only valid if the XRT94L33 is receiving and processing an STS-3c signal. AIS – Concatenation Defect Declared – STS-1 Time-Slot # 2 This READ-ONLY bit-field indicates whether or not the Receive STS-3c POH Processor block is declaring the AIS-C (Loss of Pointer – Concatenation) defect condition with STS-1 time-slot # 2 (within the incoming STS-3c signal). The Receive STS-3c POH Processor block will declare the AISC defect condition, with STS-1 time-slot # 2; if it receives an “All Ones” string in the H1, H2 bytes (associated with STS-1 timeslot # 2) for 3 consecutive STS-3c frames. 0 – Indicates that the Receive STS-3c POH Processor block is NOT currently declaring the AIS-C defect condition with STS-1 time-slot # 2. 1 – Indicates that the Receive STS-3c POH Processor block is currently declaring the AIS-C defect condition with STS-1 timeslot # 2. Note: 0 Unused R/O 233 This bit-field is only valid if the XRT94L33 is receiving and processing an STS-3c signal. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 145: Receive STS-3c Path – AUTO AIS Control Register (Address Location= 0x11BB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Transmit AIS-P (Downstream) Upon C2 Byte Unstable Transmit AIS-P (Downstream) Upon UNEQ-P Transmit AIS-P (Downstream) Upon PLMP Transmit AIS-P (Downstream) Upon Path Trace Message Unstable Transmit AIS-P (Downstream) Upon TIM-P Transmit AIS-P (Downstream) upon LOP-P Transmit AIS-P (Downstream) Enable R/O R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Transmit AIS-P (Downstream) upon C2 Byte Unstable R/W DESCRIPTION Transmit Path AIS (Downstream, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) upon Declaration of the Unstable C2 Byte Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit the Path AIS (AIS-P) Indicator via the “downstream” STS-3c traffic (e.g., towards Receive STS-1/STM-0 Telecom Bus Interface # 0), anytime (and for the duration that) it declares Unstable C2 Byte defect condition within the “incoming” STS-3c data-stream. 0 – Does not configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever it declares “Unstable C2 Byte” defect condition. 1 – Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic) whenever (and for the duration that) it declares the “Unstable C2 Byte” defect condition. Note: 5 Transmit AIS-P (Downstream) upon UNEQ-P R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (Downstream, towards the Receive STS1/STM-0 Telecom Bus Interface # 0) upon Declaration of the UNEQ-P (Path-Unequipped) Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit the Path AIS (AIS-P) Indicator via the “downstream” traffic (e.g., towards Receive STS-1/STM-0 Telecom Bus Interface # 0), anytime (and for the duration that) it declares the UNEQ-P defect condition. 0 – Does not configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever it declares the UNEQ-P defect condition. 1 – Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever (and for the duration that) it declares the UNEQ-P defect condition. Note: The user must also set Bit 0 (Transmit AIS-P Enable) to “1” 234 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. 4 Transmit AIS-P (Downstream) upon PLM-P R/W Transmit Path AIS (Downstream, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) upon Declaration of the PLM-P (PathPayload Label Mismatch) Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit the Path AIS (AIS-P) Indicator via the “downstream” traffic (e.g., towards Receive STS-1/STM-0 Telecom Bus Interface # 0), anytime (and for the duration that) it declares the PLM-P defect condition. 0 – Does not configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever it declares the PLM-P defect condition. 1 – Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever (and for the duration that) it declares the PLM-P defect condition. Note: 3 Transmit AIS-P (Downstream) upon Path Trace Message Unstable R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (Downstream, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) upon Declaration of the Path-Trace Message Unstable Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit the Path AIS (AIS-P) Indicator via the “downstream” traffic (e.g., towards Receive STS-1/STM-0 Telecom Bus Interface # 0), anytime (and for the duration that) it declares the Path Trace Message Unstable defect condition within the “incoming” STS-3c data-stream. 0 – Does not configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever it declares the “Path Trace Message Unstable” defect condition. 1 – Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever (and for the duration that) it declares the “Path Trace Message Unstable” defect condition. Note: 2 Transmit AIS-P (Downstream) upon TIM-P R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (Downstream towards Receive STS-1/STM-0 Telecom Bus Interface # 0) upon Detection of the TIM-P (PathTrace Identification Message Mismatch Defect) defect condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit a Path AIS (AIS-P) Indicator via the “downstream” traffic (e.g., towards Receive STS-1/STM-0 Telecom Bus Interface # 0), anytime (and for the duration that) it declares the TIM-P defect condition, within the 235 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 incoming STS-3c data-stream. 0 – Does not configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever it declares the TIM-P defect condition. 1 – Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever (and for the duration that) it declares the TIM-P defect condition, within the incoming STS-3c data-stream. Note: 1 Transmit AIS-P (Downstream) upon LOP-P R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (Downstream, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) upon Detection of Loss of Pointer (LOP-P) Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive STS-3c POH Processor block to automatically transmit the Path AIS (AIS-P) Indicator via the “downstream” traffic (e.g., towards Receive STS-3/STM-1 Telecom Bus Interface # 0), anytime (and for the duration that) it declares the LOP-P defect condition within the incoming STS-3c data-stream. 0 – Does not configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever it declares the LOP-P defect condition. 1 – Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever (and for the duration that) it declares the LOP-P defect condition. Note: 0 Transmit AIS-P (Downstream) Enable R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field serves two purposes. It permits the user to configure the Receive STS-3c POH Processor block to automatically transmit the Path AIS (AIS-P) indicator, via the down-stream traffic (e.g., towards Receive STS-1/STM-0 Telecom Bus Interface # 0), whenever (and for the duration that) it declares either the UNEQ-P, PLM-P, TIM-P, LOP-P, or Path Trace Message Unstable defect conditions. It also permits the user to configure the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator via the “downstream” traffic (e.g., towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever (and for the duration that) it declares the AIS-P defect condition, within the incoming STS-3c data-stream. 0 – Configures the Receive STS-3c POH Processor block to NOT automatically transmit the AIS-P indicator (via the “downstream” traffic) upon detection of any of the “above-mentioned” defect conditions. 1 – Configures the Receive STS-3c POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” 236 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S traffic, towards Receive STS-1/STM-0 Telecom Bus Interface # 0) whenever (and for the duration that) it declares any of the “abovementioned” defect condition. Note: The user must also set the corresponding bit-fields (within this register) to “1” in order to configure the Receive STS3c POH Processor block to automatically transmit the AISP indicator upon detection of a given alarm/defect condition. 237 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 146: Receive STS-3c Path – Serial Port Control Register (Address Location= 0x11BF) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 RxPOH_CLOCK_SPEED[7:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Unused R/O 3-0 RxPOH_CLOCK_SPEED[7:0] R/W DESCRIPTION RxPOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permit the user to specify the frequency of the “RxPOHClk output clock signal. The formula that relates the contents of these register bits to the “RxPOHClk” frequency is presented below. FREQ = 19.44 /[2 * (RxPOH_CLOCK_SPEED) Note: 238 For STS-3/STM-1 applications, the frequency of the RxPOHClk output signal must be in the range of 0.304MHz to 9.72MHz XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 147: Receive STS-3c Path – SONET Receive Auto Alarm Register – Byte 0 (Address Location= 0x11C3) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit AIS-P (via Downstream STS-3c) upon LOP-P Unused Transmit AIS-P (via Downstream STS-3cs) upon PLM-P Unused Transmit AIS-P (via Downstream STS-3c) upon UNEQ-P Transmit AIS-P (via Downstream STS-3c) upon TIM-P Transmit AIS-P (via Downstream STS-3c) upon AIS-P Unused R/W R/O R/W R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Transmit AIS-P (via Downstream STS-3c) upon LOP-P R/W DESCRIPTION Transmit AIS-P (via Downstream STS-3c) upon LOP-P This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-3c signal, anytime the Receive STS-3c POH Processor block declares the LOP-P defect. 0 – Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-3c signals, anytime the Receive STS-3c POH Processor block declares the LOP-P defect. 1 – Configures the corresponding Transmit STS-3c POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-3c signals, anytime the Receive STS-3c POH Processor block declares the LOP-P defect. 6 Unused R/O 5 Transmit AIS-P (via Downstream STS-1s) upon PLM-P R/W Transmit AIS-P (via Downstream STS-1s) upon PLM-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signal, anytime the Receive STS3c POH Processor block declares the PLM-P defect. 0 – Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3c POH Processor block declares the PLM-P defect. 1 – Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3c POH Processor block declares the PLM-P defect. 4 Unused R/O 3 Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P R/W Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signal, anytime the Receive STS3c POH Processor block declares the UNEQ-P defect. 239 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 0 – Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3c POH Processor block declares the UNEQ-P defect. 1 – Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3c POH Processor block declares the UNEQ-P defect. 2 Transmit AIS-P (via Downstream STS-1s) upon TIM-P R/W Transmit AIS-P (via Downstream STS-1s) upon TIM-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signal, anytime the Receive STS3c POH Processor block declares the TIM-P defect. 0 – Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3c POH Processor block declares the TIM-P defect. 1 – Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3c POH Processor block declares the TIM-P defect. 1 Transmit AIS-P (via Downstream STS-1s) upon AIS-P R/W Transmit AIS-P (via Downstream STS-1s) upon AIS-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signal, anytime the Receive STS3c POH Processor block declares the AIS-P defect. 0 – Does not configure the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signals, anytime the Receive STS-3c POH Processor block declares the AIS-P defect. 1 – Configures the corresponding Transmit STS-1 POH Processor block to automatically transmit the AIS-P Indicator via the “downstream” STS-1 signal, anytime the Receive STS-3c POH Processor block declares the AIS-P defect. 0 Unused R/O 240 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 148: Receive STS-3c Path – Receive J1 Byte Value Capture Register (Address Location= 0x11D3) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 J1_Byte_Captured_Value[7:0] BIT NUMBER NAME TYPE 7–0 J1_Byte_Captured_Value[7:0] R/O DESCRIPTION Receive J1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the J1 byte, within the most recently received STS-3c frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new J1 byte value. Table 149: Receive STS-3c Path – Receive B3 Byte Value Capture Register (Address Location= 0x11D7) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B3_Byte_Captured_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 B3_Byte_Captured_Value[7:0] R/O DESCRIPTION Receive B3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the B3 byte, within the most recently received STS-3c frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new B3 byte value. 241 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 150: Receive STS-3c Path – Receive C2 Byte Value Capture Register 0x11DB) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 (Address Location= BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 C2_Byte_Captured_Value[7:0] BIT NUMBER NAME TYPE 7–0 C2_Byte_Captured_Value[7:0] R/O DESCRIPTION Received C2 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the C2 byte, within the most recently received STS-3c frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new C2 byte value. Table 151: Receive STS-3c Path – Receive G1 Byte Value Capture Register 0x11DF) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 (Address Location= BIT 2 BIT 1 BIT 0 G1_Byte_Captured_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 G1_Byte_Captured_Value[7:0] R/O DESCRIPTION Receive G1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the G1 byte, within the most recently received STS-3c frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new G1 byte value. 242 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 152: Receive STS-3c Path – Receive F2 Byte Value Capture Register (Address Location=0x11E3) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 F2_Byte_Captured_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 F2_Byte_Captured_Value[7:0] R/O DESCRIPTION Receive F2 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the F2 byte, within the most recently received STS-3c frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new F2 byte value. Table 153: Receive Location=0x11E7) BIT 7 STS-3c BIT 6 Path BIT 5 – Receive BIT 4 H4 Byte BIT 3 Value Capture Register (Address BIT 2 BIT 1 BIT 0 H4_Byte_Captured_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 H4_Byte_Captured_Value[7:0] R/O DESCRIPTION Receive H4 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the H4 byte, within the most recently received STS-3c frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new H4 byte value. 243 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Table 154: Receive Location=0x11EB) STS-3c Path – Receive BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 Z3 Byte Value BIT 3 Rev222...000...000 Capture Register (Address BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 Z3_Byte_Captured_Value[7:0] BIT NUMBER NAME TYPE 7–0 Z3_Byte_Captured_Value[7:0] R/O DESCRIPTION Receive Z3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z3 byte, within the most recently received STS-3c frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new Z3 byte value. Table 155: Receive STS-3c Path – Receive Z4 (K3) Byte Value Capture Register (Address Location= 0x11EF) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Z4(K3)_Byte_Captured_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Z4(K3)_Byte_Captured_Value[7:0] R/O DESCRIPTION Receive Z4 (K3) Byte Value Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z4 (K3) byte, within the most recently received STS-3c frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new Z4 (K3) byte value. 244 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 156: Receive STS-3c Path – Receive Z5 Byte Value Capture Register 0x11F3) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 (Address Location= BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 Z5_Byte_Captured_Value[7:0] BIT NUMBER NAME TYPE 7–0 Z5_Byte_Captured_Value[7:0] R/O DESCRIPTION Receive Z5 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z5 byte, within the most recently received STS-3c frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new Z5 byte value. 245 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1.6 Rev222...000...000 REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK The register map for the Redundant Receive STS-3 TOH Processor Block is presented in the Table below. Additionally, a detailed description of each of the “Redundant Receive STS-3 TOH Processor” Block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the “Redundant Receive STS-3 TOH Processor Block “highlighted” is presented below in Figure 3. NOTE: The Redundant Receive STS-3 TOH Processor block is only active if the user has configured the XRT94L33 device to support Line APS Applications. Figure 3: Illustration of the Functional Block Diagram of the XRT94L33 (whenever it has been configured to operate in the 3-Channel DS3/STS-1 to STS-3 Mapper Mode), with the Redundant Receive STS-3 TOH Processor Block “High-lighted”. Tx TxSTS-3 STS-3 TOH TOHProcessor Processor Block Block Rx RxSTS-3 STS-3TOH TOH Processor Rx STS-3 Processor Rx STS-3TOH TOH Block Processor Block Block Processor Block (Primary) (Primary) STS-3 STS-3 Telecom TelecomBus Bus Block Block Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (Primary) (Primary) Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (APS) (APS) Tx TxSONET SONET POH POH Processor Processor Block Block Rx RxSONET SONET POH POH Processor Processor Block Block Rx RxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block Tx TxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block Rx RxSTS-1 STS-1 POH POH Block Block Rx RxSTS-1 STS-1 TOH TOH Block Block Tx TxSTS-1 STS-1 POH POH Block Block Tx TxSTS-1 STS-1 TOH TOH Block Block DS3/E3 DS3/E3 Jitter Jitter Attenuator Attenuator Block Block DS3/E3 DS3/E3 Framer Framer Block Block Channel 1 To Channels 2 – 3 From Channels 2 – 3 Clock ClockSynthesizer SynthesizerBlock Block Microprocessor MicroprocessorInterface Interface 246 JTAG JTAGTest TestPort Port XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER Table 157: Redundant Receive STS-3 TOH Processor Block Control Register – Address Map ADDRESS LOCATION REGISTER NAME DEFAULT VALUES Redundant Receive STS-3 Transport Control Register – Byte 0 0x00 Reserved 0x00 0x1706 Redundant Receive STS-3 Transport Status Register – Byte 1 0x00 0x1707 Redundant Receive STS-3 Transport Status Register – Byte 0 0x02 0x1708 Reserved 0x00 0x1709 Redundant Receive STS-3 Transport Interrupt Status Register – Byte 2 0x00 0x170A Redundant Receive STS-3 Transport Interrupt Status Register – Byte 1 0x00 0x170B Redundant Receive STS-3 Transport Interrupt Status Register – Byte 0 0x00 0x170C Reserved 0x00 0x170D Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 2 0x00 0x170E Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 1 0x00 0x170F Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 0 0x00 0x1710 Redundant Receive STS-3 Transport B1 Error Count – Byte 3 0x00 0x1711 Redundant Receive STS-3 Transport B1 Error Count – Byte 2 0x00 0x1712 Redundant Receive STS-3 Transport B1 Error Count – Byte 1 0x00 0x1713 Redundant Receive STS-3 Transport B1 Error Count – Byte 0 0x00 0x1714 Redundant Receive STS-3 Transport B2 Error Count – Byte 3 0x00 0x1715 Redundant Receive STS-3 Transport B2 Error Count – Byte 2 0x00 0x1716 Redundant Receive STS-3 Transport B2 Error Count – Byte 1 0x00 0x1717 Redundant Receive STS-3 Transport B2 Error Count – Byte 0 0x00 0x1600 – 0x1702 0x1703 0x1704 – 0x1705 Reserved 247 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 ADDRESS LOCATION REGISTER NAME DEFAULT VALUES 0x1718 Redundant Receive STS-3 Transport REI-L Error Count – Byte 3 0x00 0x1719 Redundant Receive STS-3 Transport REI-L Error Count – Byte 2 0x00 0x171A Redundant Receive STS-3 Transport REI-L Error Count – Byte 1 0x00 0x171B Redundant Receive STS-3 Transport REI-L Error Count – Byte 0 0x00 0x171C Reserved 0x00 0x171D - 0x171E Reserved 0x00 Redundant Receive STS-3 Transport K1 Byte Value 0x00 Reserved 0x00 Redundant Receive STS-3 Transport K2 Byte Value 0x00 Reserved 0x00 Redundant Receive STS-3 Transport S1 Byte Value 0x00 Reserved 0x00 Redundant Receive STS-3 Transport – In-Sync Threshold Value 0x00 Reserved 0x00 0x172E Redundant Receive STS-3 Transport – LOS Threshold Value – MSB 0xFF 0x172F Redundant Receive STS-3 Transport – LOS Threshold Value – LSB 0xFF 0x1730 Reserved 0x00 0x1731 Redundant Receive STS-3 Transport – SF Set Monitor Interval – Byte 2 0x00 0x1732 Redundant Receive STS-3 Transport – SF Set Monitor Interval – Byte 1 0x00 0x1733 Redundant Receive STS-3 Transport – SF Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0x1736 Redundant Receive STS-3 Transport – SF Set Threshold – Byte 1 0x00 0x1737 Redundant Receive STS-3 Transport – SF Set Threshold – Byte 0 0x00 Reserved 0x00 Redundant Receive STS-3 Transport – SF Clear Threshold – Byte 1 0x00 0x171F 0x1720 – 0x1722 0x1723 0x1724 – 0x1726 0x1727 0x1728 – 0x172A 0x172B 0x172C, 0x172D 0x1734 – 0x1735 0x1738, 0x1739 0x173A 248 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 ADDRESS LOCATION REGISTER NAME DEFAULT VALUES 0x173B Redundant Receive STS-3 Transport – SF Clear Threshold – Byte 0 0x00 0x173C Reserved 0x00 0x173D Redundant Receive STS-3 Transport – SD Set Monitor Interval – Byte 2 0x00 0x173E Redundant Receive STS-3 Transport – SD Set Monitor Interval – Byte 1 0x00 0x173F Redundant Receive STS-3 Transport – SD Set Monitor Interval – Byte 0 0x00 Reserved 0x00 0x1742 Redundant Receive STS-3 Transport – SD Set Threshold – Byte 1 0x00 0x1743 Redundant Receive STS-3 Transport – SD Set Threshold – Byte 0 0x00 Reserved 0x00 0x1746 Redundant Receive STS-3 Transport – SD Clear Threshold – Byte 1 0x00 0x1747 Redundant Receive STS-3 Transport – SD Clear Threshold – Byte 0 0x00 Reserved 0x00 0x1740, 0x1741 0x1744, 0x1745 0x1748 – 0x174A 0x174B 0x174C, 0x174E Redundant Condition Receive STS-3 Transport – Force SEF 0x00 Reserved 0x00 Redundant Receive STS-3 Transport – Receive J0 Trace Buffer Control 0x00 Reserved 0x00 0x1752 Redundant Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 1 0x00 0x1753 Redundant Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 0 0x00 Reserved 0x00 0x1756 Redundant Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 1 0x00 0x1757 Redundant Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 0 0x00 0x1758 Reserved 0x00 0x1759 Redundant Receive STS-3 Transport –Receive SD Clear Monitor Interval – Byte 2 0xFF 0x175A Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1 0xFF 0x174F 0x1750, 0x1751 0x1754, 0x1755 249 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 ADDRESS LOCATION REGISTER NAME DEFAULT VALUES 0x175B Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0 0xFF 0x175C Reserved 0x00 0x175D Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2 0xFF 0x175E Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1 0xFF 0x5F 0x175F Redundant Receive STS-3 Transport – Receive SF Clear Monitor – Byte 0 0xFF Reserved 0x00 Redundant Receive STS-3 Transport – Auto AIS Control Register 0x00 Reserved 0x00 Redundant Receive STS-3 Transport – Serial Port Control Register 0x00 Reserved 0x00 Redundant Receive STS-3 Transport – Auto AIS (in Downstream STS-1s) Control Register 0x000 0x60 – 0x62 0x1760 – 0x1762 0x63 0x1763 0x64 – 0x66 0x1764 – 0x1766 0x67 0x1767 0x68 – 0x6A 0x1768 – 0x176A 0x6B 0x176B 0x6C – 0x79 0x176C – 0x1779 Reserved 0x7A 0x117A Redundant Receive STS-3 Transport – TOH Capture Indirect Address 0x00 0x7B 0x117B Redundant Receive STS-3 Transport – TOH Capture Indirect Address 0x00 0x7C 0x117C Redundant Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x7D 0x117D Redundant Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x7E 0x117E Redundant Receive STS-3 Transport – TOH Capture Indirect Data 0x00 0x7F 0x117F Redundant Receive STS-3 Transport – TOH Capture Indirect Data 0x00 Reserved 0x00 0x80 – 0xFF 0x1780 – 0x17FF 250 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.6.1 REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER DESCRIPTION Table 158: Redundant Receive STS-3 Transport Control Register – Byte 0 (Address Location= 0x1703) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STS-N OH Extract SF Detect Condition Detect Enable SD Detect Condition Defect Enable Descramble Disable Unused REI-L Error Type B2 Error Type B1 Error Type R/W R/W R/W R/W R/O R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 STS-N OH Extract R/W DESCRIPTION STS-N Overhead Extract: This READ/WRITE bit-field permits the user to configure the RxTOH output port to output the TOH for all lower-tributary STS-1s within the incoming STS-3 signal. 0 – Disables this feature. In this mode, the RxTOH output port will only output the TOH for the first STS-1 within the incoming STS-3 signal. 1 – Enables this feature. 6 SF Defect Condition Detect Enable R/W Signal Failure (SF) Defect Condition Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SF Defect Declaration and Clearance by the Redundant Receive STS-3 TOH Processor Block, as described below. 0 – Configures the Redundant Receive STS-3 TOH Processor block to NOT declare nor clear the SF defect condition per the “user-specified” SF defect declaration and clearance criteria. 1 – Configures the Redundant Receive STS-3 TOH Processor block to declare and clear the SF defect condition per the “user-specified” SF defect declaration and clearance” critieria. NOTE: The user must set this bit-field to “1” in order to permit the Redundant Receive STS-3 TOH Processor block to declare and clear the SF defect condition. 5 SD Defect Condition Detect Enable R/W Signal Degrade (SD) Defect Condition Detect Enable: This READ/WRITE bit-field permits the user to enable or disable SD Defect Declaration and Clearance by the Redundant Receive STS-3 TOH Processor Block as described below. 0 – Configures the Redundant Receive STS-3 TOH Processro block to NOT declare nor clear the SD defect condition per the “user-specified” SD defect declaration and clearance criteria. 1 – Configures the Receive STS-3 TOH Processor block to declare and clear the SD defect condition per the “user-specified” SD defect declaration and clearance” criteria. NOTE: The user must set this bit-field to “1” in order to permit the Redundant Receive STS-3 TOH Processro block to declare and clear the SD defect condition, 4 Descramble Disable R/W De-Scramble Disable: This READ/WRITE bit-field permits the user to either enable or disable descrambling by the Redundant Receive STS-3 TOH Processor block. 251 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 0 – De-Scrambling is enabled. 1 – De-Scrambling is disabled. 3 Unused R/O 2 REI-L Error Type R/W REI-L (Line – Remote Error Indicator) Error Type: This READ/WRITE bit-field permits the user to specify how the “Redundant Receive STS-3 TOH Processor block will count (or tally) REI-L events, for Performance Monitoring purposes. The user can configure the Redundant Receive STS-3 TOH Processor block to increment REI-L events on either a “per-bit” or “per-frame” basis. If the user configures the Redundant Receive STS-3 TOH Processor block to increment REI-L events on a “perbit” basis, then it will increment the “Redundant Receive STS-3 Transport REI-L Event Count” registers by the contents within the M1 byte of the incoming STS-3 data-stream If the user configures the Redundant Receive STS-3 TOH Processor block to increment REI-L events on a “per-frame” basis, then it will increment the “Redundant Receive STS-3 Transport REI-L Event Count” register each time it receives an STS-3 frame, in which the M1 byte is set to a “non-zero” value. 0 – Configures the Redundant Receive STS-3 TOH Processor block to count or tally REI-L events on a per-bit basis. 1 – Configures the Redundant Receive STS-3 TOH Processor block to count or tally REI-L events on a per-frame basis. 1 B2 Error Type R/W B2 Error Type: This READ/WRITE bit-field permits the user to specify how the “Redundant Receive STS-3 TOH Processor block will count (or tally) B2 byte errors, for Performance Monitoring purposes. The user can configure the Redundant Receive STS-3 TOH Processor block to increment B2 byte errors on either a “per-bit” or “per-frame” basis. If the user configures the Redundant Receive STS-3 TOH Processor block to increment B2 byte errors on a “per-bit” basis, then it will increment the Redundant Receive STS-3 Transport - B2 Byte Error Count” register by the number of bits (within each of the three B2 byte values) that is in error. If the user configures the Redundant Receive STS-3 TOH Processor block to increment B2 byte errors on a “per-frame” basis, then it will increment the “Redundant Receive STS-3 Transport – B2 Byte Error Count” Register, each time it receives an STS-3 frame that contains at least one erred B2 byte. 0 – Configures the Redundant Receive STS-3 TOH Processor block to count B2 byte errors on a “per-bit” basis. 1 – Configures the Redundant Receive STS-3 TOH Processor block to count B2 byte errors on a “per-frame” basis. 0 B1 Error Type R/W B1 Error Type: This READ/WRITE bit-field permits the user to specify how the “Redundant Receive STS-3 TOH Processor block will count (or tally) B1 byte errors, for Performance Monitoring purposes. The user can configure the Redundant Receive STS-3 TOH Processor block to increment B1 byte errors on either a “per-bit” or “per-frame” basis. If the user configures the Redundant Receive STS-3 TOH Processor block to increment B1 byte errors on a “per-bit” basis, then it will increment the “Redundant Receive STS-3 Transport - B1 Byte Error Count” register by the number of bits (within the B1 byte value) that is in error. If the user configures the Redundant Receive STS-3 TOH Processor block to increment B1 byte errors on a “per-frame” basis, then it will increment the “Redundant Receive STS-3 Transport – B1 Byte Error Count” Register 252 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S each time it receives an STS-3 frame that contains an erred B1 byte. 0 – Configures the Redundant Receive STS-3 TOH Processor block to count B1 byte errors on a “per-bit” basis. 1 – Configures the Redundant Receive STS-3 TOH Processor block to count B2 byte errors on a “per-frame” basis. 253 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 159: Redundant Receive STS-3 Transport Status Register – Byte 1 (Address Location= 0x1706) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Unused BIT 0 AIS-L Defect Declared R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–1 Unused R/O 0 AIS-L Defect Declared R/O DESCRIPTION AIS-L Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS-3 TOH Processor block is currently declaring the AIS-L (Line AIS) defect condition within the incoming STS-3 data stream. The Redundant Receive STS-3 TOH Processor block will declare the AIS-L defect condition within the incoming STS-3 data-stream if bits 6, 7 and 8 (e.g., the Least Significant Bits, within the K2 byte) are set to the value “[1, 1, 1]” for five consecutive STS-3 frames. 0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring the AIS-L defect condition. 1 – Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring the AIS-L defect condition. 254 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 160: Redundant Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1707) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RDI-L Defect Declared S1 Byte Unstable Defect Declared K1, K2 Byte Unstable Defect Declared SF Defect Declared SD Defect Declared LOF Defect Declared SEF Defect Declared LOS Defect Declared R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 RDI-L Defect Declared R/O DESCRIPTION RDI-L (Line Remote Defect Indicator) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the RDI-L defect condition within the incoming STS-3 signal. The Redundant Receive STS-3 TOH Processor block will declare the RDI-L defect condition whenever it determines that bits 6, 7 and 8 (e.g., the three least significant bits) of the K2 byte contains the “1, 1, 0” pattern within 5 consecutive incoming STS-3 frames. 0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring the RDI-L defect condition. 1 – Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring the RDI-L defect condition. 6 S1 Byte Unstable Defect Declared R/O S1 Byte Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the “S1 Byte Unstable” defect condition. The Redundant Receive STS-3 TOH Processor block will declare the “S1 Byte Unstable” defect condition whenever the “S1 Byte Unstable Counter” reaches the value 32. The Redundant Receive STS-3 TOH Processor block will increment the “S1 Byte Unstable Counter” each time that it receives an STS-3 frame that contains an S1 byte that differs from the previously received S1 byte. The Redundant Receive STS-3 TOH Processor block will clear the contents of the “S1 Byte Unstable Counter” is cleared to “0” whenever it receives the same S1 byte for 8 consecutive STS-3 frames. 0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring the “S1 Byte Unstable” Defect Condition. 1 – Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring the S1 Byte Unstable” Defect Condition. 5 K1, K2 Byte Unstable Defect Declared R/O K1, K2 Byte Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the “K1, K2 Byte Unstable” defect condition. The Redundant Receive STS-3 TOH Processor block will declare the “K1, K2 Byte Unstable” defect condition whenever it fails to receive the same set of K1, K2 bytes, in 12 consecutive STS-3 frames. The Redundant Receive STS-3 TOH Processor block will clear the “K1, K2 Byte Unstable” defect condition whenever it receives a given set of K1, K2 byte values within three consecutive STS-3 frames. 0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring the K1, K2 Unstable Defect Condition. 1 – Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring the K1, K2 Unstable Defect Condition. 4 SF Defect Declared R/O SF (Signal Failure) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS- 255 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 3 TOH Processor block is currently declaring the SF defect condition. The Redundant Receive STS-3 TOH Processor block will declare the SF defect condition anytime it has determined that the number of B2 byte errors (measured over a user-selected period of time) exceeds a certain “user-specified” B2 Byte Error” threshold. 0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring the SF Defect condition. This bit is set to “0” when the number of B2 byte errors (accumulated over a given interval of time) does not exceed the “SF Defect Declaration” threshold. 1 – Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring the SF Defect condition. This bit is set to “1” when the number of B2 byte errors (accumulated over a given interval of time) does exceed the “SF Defect Declaration” threshold. 3 SD Defect Declared R/O SD (Signal Degrade) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the SD defect condition. The Redundant Receive STS-3 TOH Processor block will declare the SD defect condition anytime it has determined that the number of B2 byte errors (measured over a “user-specified” period of time) exceeds a certain “user-specified” B2 Byte Error” threshold. 0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring the SD Defect condition. This bit is set to “0” when the number of B2 byte errors (accumulated over a given interval of time) does not exceed the “SD Defect Declaration” threshold. 1 – Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring the SD Defect condition. This bit is set to “1” when the number of B2 byte errors (accumulated over a given interval of time) does exceed the “SD Defect Declaration” threshold. 2 LOF Defect Declared R/O LOF (Loss of Frame) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the LOF defect condition. The Redundant Receive STS-3 TOH Processor block will declare the LOF defect condition, if it has been declaring the SEF (Severely Errored Frame) defect condition for 3ms (or 24 SONET frame periods). 0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring the LOF defect condition. 1 – Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring the LOF defect condition. 1 SEF Defect Declared R/O SEF (Severely Errored Frame) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the SEF defect condition. The Redundant Receive STS-3 TOH Processor block will declare the SEF defect condition, if the “SEF Declaration Criteria”; per the settings of the FRPATOUT[1:0] bits, within the Redundant Receive STS-3 Transport – In-Sync Threshold Value Register (Address Location= 0x172B) are met. 0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring the SEF defect condition. 1 – Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring the SEF defect condition. 0 LOS Defect Declared R/O LOS (Loss of Signal) Defect Declared: This READ-ONLY bit-field indicates whether or not the Redundant Receive STS- 256 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Declared 3 TOH Processor block is currently declaring the LOS (Loss of Signal) defect condition. The Redundant Receive STS-3 TOH Processor block will declare the LOS defect condition if it detects “LOS_THRESHOLD[15:0]” consecutive “All Zero” bytes in the incoming STS-3 data stream. Note: The user can set the “LOS_THRESHOLD[15:0]” value by writing the appropriate data into the “Redundant Receive STS-3 Transport – LOS Threshold Value” Register (Address Location= 0x172E and 0x172F). 0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT currently declaring the LOS defect condition. 1 – Indicates that the Redundant Receive STS-3 TOH Processor block is currently declaring the LOS defect condition. 257 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 161: Redundant Receive STS-3 Transport Interrupt Status Register – Byte 2 (Address Location= 0x1709) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 Change of AIS-L Defect Condition Interrupt Status Change of RDI-L Defect Condition Interrupt Status R/O R/O R/O R/O R/O R/O RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-2 Unused R/O 1 Change of AIS-L Defect Condition Interrupt Status RUR DESCRIPTION Change of AIS-L (Line AIS) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of AIS-L Defect Condition” interrupt has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following occurrences. • Whenever the Redundant Receive STS-3 TOH Processor block declares the AIS-L defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the AIS-L defect condition. 0 – Indicates that the “Change of AIS-L Defect Condition” interrupt has not occurred since the last read of this register. 1 – Indicates that the “Change of AIS-L Defect Condition” interrupt has occurred since the last read of this register. Note: 0 Change of RDI-L Defect Condition Interrupt Status RUR The user can determine if the Redundant Receive STS-3 TOH Processor block is currently declaring the AIS-L defect condition by reading the contents of Bit 0 (AIS-L Defect Declared) within the “Redundant Receive STS-3 Transport Status Register – Byte 1” (Address Location= 0x1706). Change of RDI-L (Line - Remote Defect Indicator) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of RDI-L Defect Condition” interrupt has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following occurrences. • Whenever the Redundant Receive STS-3 TOH Processor block declares the RDI-L defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the RDI-L defect condition 0 – Indicates that the “Change of RDI-L Defect Condition” interrupt has not occurred since the last read of this register. 1 – Indicates that the “Change of RDI-L Defect Condition” interrupt has occurred since the last read of this register. Note: The user can determine if the Redundant Receive STS-3 TOH Processor block is currently declaring the RDI-L defect condition by reading out the state of Bit 7 (RDI-L Defect Declared) within the “Redundant Receive STS-3 Transport Status Register – Byte 0” (Address Location = 0x1707). 258 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 162: Redundant Receive STS-3 Transport Interrupt Status Register – Byte 1 (Address Location = 0x170A) BIT 7 BIT 6 BIT 5 BIT 4 New S1 Byte Interrupt Status Change in S1 Byte Unstable Defect Condition Interrupt Status RUR RUR R/O R/O 0 0 0 0 BIT NUMBER NAME TYPE 7 New S1 Byte Value Interrupt Status RUR BIT 3 BIT 2 BIT 1 BIT 0 Receive TOH CAP DONE Interrupt Status Change in K1, K2 Bytes Unstable Defect Condition Interrupt Status NEW K1K2 Byte Value Interrupt Status R/O RUR RUR RUR 0 0 0 0 Unused DESCRIPTION New S1 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New S1 Byte Value” Interrupt has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate the “New S1 Byte Value” Interrupt anytime it has “accepted” a new S1 byte, from the incoming STS-3 data-stream. 0 – Indicates that the “New S1 Byte Value” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New S1 Byte Value” interrupt has occurred since the last read of this register. Note: 6 Change in S1 Byte Unstable Defect Condition Interrupt Status RUR The user can obtain the value for this most recently accepted value of the S1 byte by reading the “Redundant Receive STS-3 Transport S1 Value” register (Address Location= 0x1727). Change in S1 Byte Unstable Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in S1 Byte Unstable Defect Condition” Interrupt has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the “S1 Byte Unstable” defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the “S1 Byte Unstable” defect condition. 0 – Indicates that the “Change in S1 Byte Unstable Defect Condition” Interrupt has occurred since the last read of this register. 1 – Indicates that the “Change in S1 Byte Unstable Defect Condition” Interrupt has not occurred since the last read of this register. Note: 5–3 2 The user can determine if the Redundant Receive STS-3 TOH Processor block is currently declaring the “S1 Byte Unstable” defect condition by reading the contents of Bit 6 (S1 Byte Unstable Defect Declared) within the “Redundant Receive STS-3 Transport Status Register – Byte 0” (Address Location = 0x1707). R/O Receive TOH CAP DONE Interrupt Status RUR Receive TOH Capture DONE – Interrupt Status: This RESET-upon-READ bit-field indicates whether the “Receive TOH Data Capture” Interrupt has occurred since the last read of this register 259 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Capture” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Redundant Receive STS-3 TOH Processor block will generate an interrupt anytime it has captured the last TOH byte into the Capture Buffer. Note: Once the TOH (of a given STS-3 frame) has been captured and loaded into the “Receive TOH Capture” buffer, it will remain there for one SONET frame period. 0 – Indicates that the “Receive TOH Data Capture” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Receive TOH Data Capture” Interrupt has occurred since the last read of this register. 1 Change in K1, K2 Byte Unstable Defect Condition Interrupt Status RUR Change of K1, K2 Byte Unstable Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in K1, K2 Byte Unstable Defect Condition” interrupt has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the “K1, K2 Byte Unstable Defect” condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the “K1, K2 Byte Unstable” defect condition. 0 – Indicates that the “Change of K1, K2 Byte Unstable Defect Condition” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of K1, K2 Byte Unstable Defect Condition” interrupt has occurred since the last read of this register. Note: 0 NEW K1, K2 Byte Value Interrupt Status RUR The user can determine if the Redundant Receive STS-3 TOH Processor block is currently declaring the “K1, K2 Unstable Defect Condition” by reading out the contents of Bit 5 (K1, K2 Byte Unstable Defect Declared), within the “Redundant Receive STS-3 Transport Status Register – Byte 0” (Address Location = 0x1707). New K1, K2 Byte Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New K1, K2 Byte Value” Interrupt has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt whenever it has “accepted” a new set of K1, K2 byte values from the incoming STS-3 data-stream. 0 – Indicates that the “New K1, K2 Byte Value” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New K1, K2 Byte Value” Interrupt has occurred since the last read of this register. Note: The user can obtain the contents of the new K1 byte by reading out the contents of the “Redundant Receive STS-3 Transport K1 Byte Value” Register (Address Location= 0x171F). Further, the user can also obtain the contents of the new K2 byte by reading out the contents of the “Redundant Receive STS-3 Transport K2 Byte Value” Register (Address Location= 0x1723). 260 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 163: Redundant Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address Location= 0x170B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Change in SF Defect Condition Interrupt Status Change in SD Defect Condition Interrupt Status Detection of REI-L Event Interrupt Status Detection of B2 Byte Error Interrupt Status Detection of B1 Byte Error Interrupt Status Change of LOF Defect Condition Interrupt Status Change of SEF Defect Condition Interrupt Status Change of LOS Defect Condition Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Change in SF Defect Condition Interrupt Status RUR DESCRIPTION Change of Signal Failure (SF) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of SF Defect Condition Interrupt” has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the SF defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the SF defect condition. 0 – Indicates that the “Change of SF Defect Condition Interrupt” has NOT occurred since the last read of this register. 1 – Indicates that the “Change of SF Defect Condition Interrupt” has occurred since the last read of this register. Note: 6 Change of SD Defect Condition Interrupt Status RUR The user can determine if the Redundant Receive STS-3 TOH Processor block is currently declaring the “SF” defect condition by reading out the state of Bit 4 (SF Defect Declared) within the “Redundant Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1707). Change of Signal Degrade (SD) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of SD Defect Condition Interrupt” has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the SD Defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the SD Defect condition. 0 – Indicates that the “Change of SD Defect Condition Interrupt” has NOT occurred since the last read of this register. 1 – Indicates that the “Change of SD Defect Condition Interrupt” has occurred since the last read of this register. Note: 5 Detection of REI- RUR The user can determine the whether or not the Redundant Receive STS-3 TOH Processor block is currently declaring the SD defect condition by reading out the state of Bit 3 (SD Defect Declared) within the “Redundant Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1707). Detection of REI-L (Line – Remote Error Indicator) Event Interrupt 261 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Status: L Event Interrupt Status This RESET-upon-READ bit-field indicates whether or not the “Declaration of REI-L Event” Interrupt has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt anytime it detects an REI-L event within the incoming STS-3 datastream. 0 - Indicates that the “Detection of REI-L Event” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of REI-L Event” Interrupt has occurred since the last read of this register. 4 Detection of B2 Byte Error Interrupt Status RUR Detection of B2 Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of B2 Byte Error Interrupt” has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt anytime it detects a B2 byte error within the incoming STS-3 datastream. 0 – Indicates that the “Detection of B2 Byte Error Interrupt” has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of B2 Byte Error Interrupt” has occurred since the last read of this register. 3 Detection of B1 Byte Error Interrupt Status RUR Detection of B1 Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of B1 Byte Error Interrupt” has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt anytime it detects a B1 byte within the incoming STS-3 datastream. 0 – Indicates that the “Detection of B1 Byte Error Interrupt” has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of B1 Byte Error Interrupt” has occurred since the last read of this register 2 Change of LOF Defect Condition Interrupt Status RUR Change of Loss of Frame (LOF) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of LOF Defect Condition” interrupt has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the LOF defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the LOF defect condition. 0 – Indicates that the “Change of LOF Defect Condition” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of LOF Defect Condition” interrupt has occurred since the last read of this register. Note: 1 Change of SEF Defect Condition Interrupt Status RUR The user can determine whether the Redundant Receive STS-3 TOH Processor block is currenly declaring the LOF defect condition by reading out the state of Bit 2 (LOF Defect Declared) within the “Redundant Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1707). Change of SEF Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of SEF” Defect Condition Interrupt has occurred since the last read of this 262 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the SEF defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the SEF defect condition. 0 – Indicates that the “Change of SEF Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of SEF Defect Condition” Interrupt has occurred since the last read of this register. Note: 0 Change of LOS Defect Condition Interrupt Status RUR The user can determine whether or not the Redundant Receive STS-3 TOH Processor block is currently declaring the SEF defect condition by reading out the state of Bit 1 (SEF Defect Declared) within the “Redundant Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1707). Change of Loss of Signal (LOS) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of LOS Defect Condition” interrupt has occurred since the last read of this register. The Redundant Receive STS-3 TOH Processor block will generate this interrupt in response to either of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the LOS defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the LOS defect condition. 0 – Indicates that the “Change of LOS Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of LOS Defect Condition” Interrupt has occurred since the last read of this register. Note: The user can determine whether the Redundant Receive STS-3 TOH Processor block is currently declaring the LOS defect condition by reading out the contents of Bit 0 (LOS Defect Declared) within the Redundant Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1707). 263 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 164: Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 2 (Address Location= 0x170D) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 Change of AIS-L Defect Condition Interrupt Enable Change of RDI-L Defect Condition Interrupt Enable R/O R/O R/O R/O R/O R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–2 Unused R/O 1 Change of AIS-L Defect Condition Interrupt Enable R/W DESCRIPTION Change of AIS-L (Line AIS) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of AIS-L Defect Condition” interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Redundant Receive STS-3 TOH Processor block declares the “AIS-L” defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the “AIS-L” defect condition. 0 – Disables the “Change of AIS-L Defect Condition” Interrupt. 1 – Enables the “Change of AIS-L Defect Condition” Interrupt. Note: 0 Change of RDI-L Defect Condition Interrupt Enable R/W The user can determine if the Redundant Receive STS-3 TOH Processor block is currently declaring the AIS-L defect condition by reading out the state of Bit 0 (AIS-L Defect Declared) within the “Redundant Receive STS-3 Transport Status Register – Byte 1” (Address Location= 0x1706). Change of RDI-L (Line Remote Defect Indicator) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of RDI-L Defect Condition” interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Redundant Receive STS-3 TOH Processor block declares the “RDI-L” defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the “RDI-L” defect condition. 0 – Disables the “Change of RDI-L Defect Condition” Interrupt. 1 – Enables the “Change of RDI-L Defect Condition” Interrupt. 264 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 165: Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 1 (Address Location= 0x170E) BIT 7 BIT 6 BIT 5 BIT 4 New S1 Byte Interrupt Enable Change in S1 Byte Unstable Defect Condition Interrupt Enable R/W R/W R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 Receive TOH CAP DONE Interrupt Enable Change in K1, K2 Byte Unstable Defect Condition Interrupt Enable NEW K1K2 Byte Value Interrupt Enable R/O R/W R/W R/W 0 0 0 0 Unused BIT NUMBER NAME TYPE 7 New S1 Byte Value Interrupt Enable R/W DESCRIPTION New S1 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the “New S1 Byte Value” Interrupt. If the user enables this interrupt, then the Redundant Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new S1 byte value. The Redundant Receive STS-3 TOH Processor block will accept a new S1 byte after it has received it for 8 consecutive STS-3 frames. 0 – Disables the “New S1 Byte Value” Interrupt. 1 – Enables the “New S1 Byte Value” Interrupt. 6 Change in S1 Unstable State Interrupt Enable R/W Change in S1 Byte Unstable Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in S1 Byte Unstable Defect Condition” Interrupt. If the user enables this bit-field, then the Redundant Receive STS-3 TOH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Redundant Receive STS-3 TOH Processor block declares the “S1 Byte Unstable” defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the “S1 Byte Unstable” defect condition. 0 – Disables the “Change in S1 Byte Unstable Defect Condition” Interrupt. 1 – Enables the “Change in S1 Byte Unstable Defect Condition” Interrupt. 5-3 Unused R/O 2 Receive TOH CAP DONE Interrupt Enable R/W Receive TOH Capture DONE – Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Receive TOH Data Capture” interrupt, within the Redundant Receive STS-3 TOH Processor Block. If this interrupt is enabled, then the Redundant Receive STS-3 TOH Processor block will generate an interrupt anytime it has captured the last TOH byte into the Capture Buffer. Note: Once the TOH (of a given STS-3 frame) has been captured and loaded into the “Receive TOH Capture” buffer, it will remain there for one SONET frame period. 0 – Disables the “Receive TOH Capture” Interrupt. 1 – Enables the “Receive TOH Capture” Interrupt. 265 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1 Change in K1, K2 Byte Unstable Defect Condition Interrupt Enable R/W Rev222...000...000 Change of K1, K2 Byte Unstable Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of K1, K2 Byte Unstable defect condition” interrupt. If the user enables this interrupt, then the Redundant Receive STS-3 TOH Processor block will generate an Interrupt in response to either of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the “K1, K2 Byte Unstable defect” condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the “K1, K2 Byte Unstable defect” condition. 0 – Disables the “Change in K1, K2 Byte Unstable Defect Condition” Interrupt 1 – Enables the “Change in K1, K2 Byte Unstable Defect Condition” Interrupt 0 New K1K2 Byte Interrupt Enable R/W New K1, K2 Byte Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “New K1, K2 Byte Value” Interrupt. If the user enables this interrupt, then the Redundant Receive STS-3 TOH Processor block will generate this interrupt anytime it receives and accepts a new K1, K2 byte value. The Redundant Receive STS-3 TOH Processor block will accept a new K1, K2 byte value, after it has received it within 3 (or 5) consecutive STS-3 frames. 0 – Disables the “New K1, K2 Byte Value” Interrupt. 1 – Enables the “New K1, K2 Byte Value” Interrupt. 266 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 166: Redundant Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address Location= 0x170F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Change of SF Defect Condition Interrupt Enable Change of SD Defect Condition Interrupt Enable Detection of REI-L Event Interrupt Enable Detection of B2 Byte Error Interrupt Enable Detection of B1 Byte Error Interrupt Enable Change of LOF Defect Condition Interrupt Enable Change of SEF Defect Condition Interrupt Enable Change of LOS Defect Condition Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Change of SF Defect Condition Interrupt Enable R/W DESCRIPTION Change of Signal Failure (SF) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of Signal Failure (SF) Defect Condition” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to any of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the SF defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the SF defect condition. 0 – Disables the “Change of SF Defect Condition Interrupt”. 1 – Enables the “Change of SF Defect Condition Interrupt”. 6 Change of SD Defect Condition Interrupt Enable R/W Change of Signal Degrade (SD) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of Signal Degrade (SD) Defect Condition” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following events. • Whenever the Redundant Receive STS-3 TOH Processor block declares the SD defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the SD defect condition. 0 – Disables the “Change of SD Defect Condition Interrupt”. 1 – Enables the “Change of SD Defect Condition Interrupt”. 5 Detection of REI-L Event Interrupt Enable R/W Detection of REI-L (Line – Remote Error Indicator) Event Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of Line – REI-L Event” interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Redundant Receive STS-3 TOH Processor block detects an “REI-L” event, within the incoming STS-3 data-stream. 0 – Disables the “Detection of REI-L Event” Interrupt. 1 – Enables the “Detection of REI-L Event” Interrupt. 4 Detection of B2 Byte Error Interrupt Enable R/W Detection of B2 Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of B2 Byte Error” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Redundant Receive 267 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 STS-3 TOH Processor block detects a B2 byte error within the incoming STS-3 data-stream. 0 – Disables the “Detection of B2 Byte Error Interrupt”. 1 – Enables the “Detection of B2 Byte Error Interrupt”. 3 Detection of B1 Byte Error Interrupt Enable R/W Detection of B1 Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of B1 Byte Error” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt anytime the Redundant Receive STS-3 TOH Processor block detects a B1 byte error within the incoming STS-3 data-stream. 0 – Disables the “Detection of B1 Byte Error Interrupt”. 1 – Enables the “Detection of B1 Byte Error Interrupt”. 2 Change of LOF Defect Condition Interrupt Enable R/W Change of Loss of Frame (LOF) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of LOF Defect Condition” interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Redundant Receive STS-3 TOH Processor block declares the “LOF” defect condition. • Whenever the Redundant Receive STS-3 TOH Processor clears the “LOF” defect condition. 0 – Disables the “Change of LOF Defect Condition Interrupt. 1 – Enables the “Change of LOF Defect Condition” Interrupt. 1 Change of SEF Defect Condition Interrupt Enable R/W Change of SEF Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of SEF Defect Condition” Interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Redundant Receive STS-3 TOH Processor block declares the “SEF” defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the ”SEF” defect condition. 0 – Disables the “Change of SEF Defect Condition Interrupt”. 1 – Enables the “Change of SEF Defect Condition Interrupt”. 0 Change of LOS Defect Condition Interrupt Enable R/W Change of Loss of Signal (LOS) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of LOF Defect Condition” interrupt. If the user enables this interrupt, then the XRT94L33 will generate an interrupt in response to either of the following conditions. • Whenever the Redundant Receive STS-3 TOH Processor block declares the “LOF” defect condition. • Whenever the Redundant Receive STS-3 TOH Processor block clears the “LOF” defect condition. 0 – Disables the “Change of LOF Defect Condition Interrupt. 1 – Enables the “Change of LOF Defect Condition” Interrupt. 268 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 167: Redundant Receive STS-3 Transport – B1 Byte Error Count Register – Byte 3 (Address Location= 0x1710) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B1_Byte_Error_Count[31:24] BIT NUMBER NAME TYPE 7-0 B1_Byte_Error_ Count[31:24] RUR DESCRIPTION B1 Byte Error Count – MSB: This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – B1 Byte Error Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count B1 Byte Errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B1 byte (of each incoming STS-3 frame) that are in error. 2. If the Redundant Receive STS-3 TOH Processor block is configured to count B1 byte error on a “per-frame” basis, then it will increment this 32-bit counter each time that receives an STS-3 frame that contains an erred B1 byte. 269 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 168: Redundant Receive STS-3 Transport – B1 Byte Error Count Register – Byte 2 (Address Location= 0x1711) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B1_Byte_Error_Count[23:16] BIT NUMBER NAME TYPE 7-0 B1_Byte Error_Count [23:16] RUR DESCRIPTION B1 Byte Error Count (Bits 23 through 16): This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – B1 Byte Error Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B1 byte (of each incoming STS-3 frame) that are in error. 2. If the Redundant Receive STS-3 TOH Processro block is configured to count B1 byte errors on “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3 frame that contains an erred B1 byte. 270 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 169: Redundant Receive STS-3 Transport – B1 Byte Error Count Register – Byte 1 (Address Location= 0x1712) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 RUR RUR RUR RUR RUR 0 0 0 0 0 BIT 2 BIT 1 BIT 0 RUR RUR RUR 0 0 0 B1_Byte Error_Count[15:8] BIT NUMBER NAME TYPE DESCRIPTION 7-0 B1_Byte_Error_ Count [15:8] RUR B1 Byte Error Count – (Bits 15 through 8) This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – B1 Byte Error Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B1 byte error Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B1 byte (of each incoming STS-3 frame) that are in error. 2. If the Redundant Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-frame” basis, then it will increment this 32-bit counter by the number of frames that contain erred B1 bytes. 271 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 170: Redundant Receive STS-3 Transport – B1 Byte Error Count Register – Byte 0 (Address Location= 0x1713) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT NUMBER NAME TYPE 7-0 B1_Byte_Error_ Count [7:0] RUR BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B1_Byte Error_Count[7:0] DESCRIPTION B1 Byte Error Count – LSB: This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – B1 Byte Error Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B1 byte error. Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B1 byte (of each incoming STS-3 frame) that are in error. 2. If the Redundant Receive STS-3 TOH Processor block is configured to count B1 byte errors on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3 frame that contains an erred B1 byte. 272 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 171: Redundant Receive STS-3 Transport – B2 Byte Error Count Register – Byte 3 (Address Location= 0x1714) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT NUMBER NAME TYPE 7-0 B2_Byte_Error_ Count [31:24] RUR BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B2_Byte_Error_Count[31:24] DESCRIPTION B2 Byte Error Count – MSB: This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – B2 Byte Error Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B2 byte error within the incoming STS-3 data-stream. Note: 1. If the Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B2 bytes (of each incoming STS-3 frame) that are in error. 2. If the Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3 frame that contains at least one erred B2 byte. 273 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 172: Redundant Receive STS-3 Transport – B2 Byte Error Count Register – Byte 2 Address Location= 0x1715) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7-0 B2_Byte_Error_ Count [23:16] RUR B2 Byte Error Count (Bits 23 through 16): B2_Byte_Error_Count[23:16] This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – B2 Byte Error Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B2 byte error. Note: 1. If the Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B2 byte (of each incoming STS-3 frame) that are in error. 2. If the Redundant Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3 frame that contains at least one erred B2 byte. 274 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 173: Redundant Receive STS-3 Transport – B2 Byte Error Count Register – Byte 1 (Address Location= 0x1716) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7-0 B2_Byte_Error_ Count [15:8] RUR B2 Byte Error Count – (Bits 15 through 8) B2_Byte_Error_Count[15:8] This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – B2 Byte Error Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B2 byte error within the incoming STS-3 data-stream. Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B2 bytes (of each incoming STS-3 frame) that are in error. 2. If the Redundant Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-3 frame that contains at least one erred B2 byte. 275 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 174: Redundant Receive STS-3 Transport – B2 Byte Error Count Register – Byte 0 (Address Location= 0x1717) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B2_Byte Error_Count[7:0] BIT NUMBER NAME TYPE 7-0 B2_Byte Error_Count[7:0] RUR DESCRIPTION B2 Byte Error Count – LSB: This RESET-upon-READ register, along with “Redundant STS-3 Receive Transport – B2 Byte Error Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a B2 byte error within the incoming STS-3 data-stream. Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-bit” basis, then it will increment this 32-bit counter by the number of bits, within the B2 bytes (of each incoming STS-3 frame) that are in error. 2. If the Redundant Receive STS-3 TOH Processor block is configured to count B2 byte errors on a “per-frame” basis, then it will increment this 32bit counter each time that it receives an STS-3 frame that contains at least one erred B2 bytes. 276 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 175: Redundant Receive STS-3 Transport – REI-L Event Count Register – Byte 3 (Address Location= 0x1718) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-L_Event_Count[31:24] BIT NUMBER NAME TYPE 7-0 REI-L_Event_Count [31:24] RUR DESCRIPTION REI-L Event Count – MSB: This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – REI-L Event Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a Line Remote Error Indicator event within the incoming STS-3 datastream. Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-bit” basis, then it will increment this 32 bit counter by the value within the REI-L fields of the M1 byte within the each incoming STS-3 frame. 2. If the Redundant Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains a “non-zero” M1 byte value. 277 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 176: Redundant Receive STS-3 Transport – REI-L Event Count Register – Byte 2 (Address Location= 0x1719) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-L_Event_Count[23:16] BIT NUMBER NAME TYPE DESCRIPTION 7-0 REI-L_Event_Count [23:16] RUR REI-L Event Count (Bits 23 through 16): This RESET-upon-READ register, along with “Redundant Receive STS3 Transport – REI-L Event Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a Line – Remote Error Indicator event within the incoming STS-3 data-stream. Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-bit” basis, then it will increment this 32 bit counter by the value within the REI-L fields of the M1 byte within each incoming STS-3 frame. 2. If the Redundant Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-frame” basis then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains a non-zero M1 byte value. 278 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 177: Redundant Receive STS-3 Transport – REI-L Event Count Register – Byte 1 (Address Location= 0x171A) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-L_Event_Count[15:8] BIT NUMBER NAME TYPE 7-0 REI-L Event_Count[15:8] RUR DESCRIPTION REI-L Event Count – (Bits 15 through 8) This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – REI-L Error Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a Line – Remote Error Indicator event within the incoming STS-3 datastream. Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-bit” basis, then it will increment this 32 bit counter by the value within the REI-L fields of the M1 byte within each incoming STS-3 frame. 2. If the Redundant Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains a non-zero M1 byte value. 279 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 178: Redundant Receive STS-3 Transport – REI-L Event Count Register – Byte 0 (Address Location= 0x171B) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-L_Event_Count[7:0] BIT NUMBER NAME TYPE 7-0 REI-L_Event_Count [7:0] RUR DESCRIPTION REI-L Event Count – LSB: This RESET-upon-READ register, along with “Redundant Receive STS-3 Transport – REI-L Error Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Redundant Receive STS-3 TOH Processor block detects a Line – Remote Error Indicator event within the incoming STS-3 data-stream. Note: 1. If the Redundant Receive STS-3 TOH Processor block is configured to count REI-L events on a “per-bit” basis, then it will increment this 32 bit counter by the value within the REI-L fields of the M1 byte within each incoming STS-3 frame. 2. If the Redundant Receive STS-3 TOH Processor blolck is configured to count REI-L events on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-3 frame that contains a nonzero M1 byte value. 280 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 179: Redundant Receive STS-3 Transport – Received K1 Byte Value Register (Address Location= 0x171F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Filtered_K1_Byte_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Filtered_K1_Byte_Value[7:0] R/O DESCRIPTION Filtered/Accepted K1 Byte Value: These READ-ONLY bit-fields contain the value of the most recently “filtered” K1 byte value, that the Redundant Receive STS-3 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-3 frames. This register should be polled by Software in order to determine various APS codes. Table 180: Redundant Receive STS-3 Transport – Receive K2 Byte Value Register (Address Location= 0x1723) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Filtered_K2_Byte_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Filtered_K2_Byte_Val ue [7:0] R/O DESCRIPTION Filtered/Accepted K2 Byte Value: These READ-ONLY bit-fields contain the value of the most recently “filtered” K2 Byte value, that the Redundant Receive STS-3 TOH Processor block has received. These bit-fields are valid if the K1/K2 pair (to which it belongs) has been received for 3 consecutive STS-3 frames. This register should be polled by Software in order to determine various APS codes. 281 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 181: Redundant Receive STS-3 Transport – Received S1 Byte Value Register (Address Location= 0x1727) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 Filtered_S1_Value[7:0] BIT NUMBER NAME TYPE 7–0 Filtered_S1_Value[7:0] R/O DESCRIPTION Filtered/Accepted S1 Value: These READ-ONLY bit-fields contain the value of the most recently “filtered” S1 byte value that the Redundant Receive STS-3 TOH Processor block has received. These bit-fields are valid if it has been received for 8 consecutive STS-3 frames. 282 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 182: Redundant Location=0x172B) BIT 7 BIT 6 Receive STS-3 BIT 5 BIT 4 Unused Transport BIT 3 – In-Sync Threshold BIT 2 FRPATOUT[1:0] Value BIT 1 FRPATIN[1:0] (Address BIT 0 Unused R/O R/O R/O R/W R/W R/W R/W R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–5 Unused R/O 4–3 FRPATOUT[1:0] R/W DESCRIPTION Framing Pattern – SEF Declaration Criteria: These two READ/WRITE bit-fields permit the user to define the SEF Defect Declaration criteria for the Redundant Receive STS-3 TOH Processor block. The relationship between the state of these bit-fields and the corresponding SEF Defect Declaration Criteria are presented below. FRPATOUT[1:0] SEF Defect Declaration Criteria 00 The Redundant Receive STS-3 TOH Processor block will declare the SEF defect condition if either of the following conditions are true for four consecutive SONET frame periods. 01 • If the last (of the 3) A1 bytes, in the STS-3 data stream is erred, or • If the first (of the 3) A2 bytes, in the STS-3 data stream, is erred. Hence, for this selection, a total of 16 bits are evaluated for SEF defect declaration. 10 The Redundant Receive STS-3 TOH Processor block will declare the SEF defect condition if either of the following conditions are true for four consecutive SONET frame periods. • If the last two (of the 3) A1 bytes, in the STS-3 data stream, are erred, or • If the first two (of the 3) A2 bytes, in the STS-3 data stream, are erred. Hence, for this selection, a total of 32 bits are evaluated for SEF defect declaration. 11 The Redundant Receive STS-3 TOH Processor block will declare the SEF defect condition if either of the following conditions are true for four consecutive SONET frame periods. • If the last three (of the 3) A1 bytes, in the STS3 data stream, are erred, or • If the first three (of the 3) A2 bytes, in the STS3 data stream, are erred. Hence, for this selection, a total of 48 bits are evaluated for SEF defect declaration. 2-1 FRPATIN[1:0] R/W Framing Pattern – SEF Defect Clearance Criteria: 283 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 These two READ/WRITE bit-fields permit the user to define the “SEF Defect Clearance” criteria for the Redundant Receive STS-3 TOH Processor block. The relationship between the state of these bit-fields and the corresponding SEF Defect Clearance Criteria are presented below. FRPATIN[1:0] SEF Defect Clearance Criteria 00 The Redundant Receive STS-3 TOH Processor block will clear the SEF defect condition if both of the following conditions are true for two consecutive SONET frame periods. 01 • If the last (of the 3) A1 bytes, in the STS-3 data stream is un-erred, and • If the first (of the 3) A2 bytes, in the STS-3 data stream, is un-erred. Hence, for this selection, a total of 16 bits/frame are evaluated for SEF defect clearance. 10 The Redundant Receive STS-3 TOH Processor block will clear the SEF defect condition if both of the following conditions are true for two consecutive SONET frame periods. • If the last two (of the 3) A1 bytes, in the STS-3 data stream, are un-erred, and • If the first two (of the 3) A2 bytes, in the STS-3 data stream, are un-erred. Hence, for this selection, a total of 32 bits/frame are evaluated for SEF defect clearance. 11 The Redundant Receive STS-3 TOH Processor block will clear the SEF defect condition if both of the following conditions are true for two consecutive SONET frame periods. • If the last three (of the 3) A1 bytes, in the STS-3 data-stream, are un-erred, and • If the first three (of the 3) A2 bytes, in the STS3 data stream, are un-erred. Hence, for this selection, a total of 48 bits/frame are evaluated for SEF defect declaration. 0 Unused R/O 284 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 183: Redundant Receive STS-3 Transport – LOS Threshold Value - MSB (Address Location= 0x172E) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 LOS_THRESHOLD[15:8] BIT NUMBER NAME TYPE 7-0 LOS_THRESHOLD[15:8] R/W DESCRIPTION LOS Threshold Value – MSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – LOS Threshold Value – LSB” register specify the number of consecutive (All Zero) bytes that the Redundant Receive STS-3 TOH Processor block must detect before it can declare the LOS defect condition. Table 184: Redundant Receive STS-3 Transport – LOS Threshold Value - LSB (Address Location= 0x172F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LOS_THRESHOLD[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 BIT NUMBER NAME TYPE 7-0 LOS_THRESHOLD[7:0] R/W DESCRIPTION LOS Threshold Value – LSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – LOS Threshold Value – MSB” register specify the number of consecutive (All Zero) bytes that the Redundant Receive STS-3 TOH Processor block must detect before it can declare the LOS defect condition. 285 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 185: Redundant Receive STS-3 Transport –Receive SF SET Monitor Interval – Byte 2 (Address Location= 0x1731) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_SET_MONITOR_WINDOW[23:16] BIT NUMBER NAME TYPE DESCRIPTION 7-0 SF_SET_MONITOR_ WINDOW [23:16] R/W SF_SET_MONITOR_INTERVAL – MSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF SET Monitor Interval – Byte 1 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) Defect Declaration. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the user-specified “SF Defect Declaration monitoring period”. If, during this “SF Defect Declaration Monitoring Period”, the Redundant Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Redundant Receive STS-3 Transport SF SET Threshold” register, then the Redundant Receive STS-3 TOH Processor block will declare the SF defect condition. NOTES: 1. The value that the user writes into these three (3) “SF Set Monitor Window” registers, specifies the duration of the “SF Defect Declaration Monitoring Period, in terms of ms. 2. This particular register byte contains the “MSB” (most significant byte) value of the three registers that specify the “SF Defect Declaration Monitoring Period”. 286 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 186: Redundant Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 1 (Address Location= 0x1732) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_SET_MONITOR_WINDOW[15:8] BIT NUMBER NAME TYPE 7-0 SF_SET_MONITOR_WINDOW [15:8] R/W DESCRIPTION SF_SET_MONITOR_INTERVAL (Bits 15 through 8): These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF SET Monitor Interval – Byte 2 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) Defect Declaration. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the user specified “SF Defect Declaration Monitoring Period”. If, during this “SF Defect Declaration Monitoring Period” the Redundant Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Redundant Receive STS-3 Transport SF SET Threshold” register, then the Redundant Receive STS-3 TOH Processor block will declare the SF defect condition. NOTE: The value that the user writes into these three (3) “SF Set Monitor Window” Registers, specifies the duration of the “SF Defect Declaration” Monitoring Period, in terms of ms. 287 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 187: Redundant Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 0 (Address Location= 0x1733) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_SET_MONITOR_WINDOW[7:0] BIT NUMBER NAME TYPE 7-0 SF_SET_MONITOR_WINDOW[7:0] R/W DESCRIPTION SF_SET_MONITOR_INTERVAL – LSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF SET Monitor Interval – Byte 2 and Byte 1” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) Defect Declaration. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the userspecified “SF Defect Declaration Monitoring Period”. If, during this “SF Defect Declaration Monitoring Period”, the Redundant Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Redundant Receive STS-3 Transport SF SET Threshold” register, then the Redundant Receive STS-3 TOH Processor block will declare the SF defect condition. NOTES: 288 1. The value that the user writes into these three (3) “SF Set Monitor Window” registers, specifies the duration of the “SF Defect Declaration” Monitoring Period, in terms of ms. 2. This particular register byte contains the “LSB” (least significant byte) value of the three registers that specify the “SF Defect Declaration Monitoring period”. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 188: Redundant Receive STS-3 Transport – Receive SF SET Threshold – Byte 1 (Address Location= 0x1736) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_SET_THRESHOLD[15:8] BIT NUMBER NAME TYPE 7-0 SF_SET_THRESHOLD[15:8] R/W DESCRIPTION SF_SET_THRESHOLD – MSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF SET Threshold – Byte 0” registers permit the user to specify the number of B2 byte errors that will cause the Redundant Receive STS-3 TOH Processor block to declare the SF (Signal Failure) Defect condition. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal, in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the “SF Defect Declaration Monitoring Period”. If the number of accumulated B2 byte errors exceeds that value, which is of programmed into this and the “Redundant Receive STS-3 Transport SF SET Threshold – Byte 0” register, then the Redundant Receive STS-3 TOH Processor block will declare the SF defect condition. 289 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 189: Redundant Receive STS-3 Transport – Receive SF SET Threshold – Byte 0 Address Location= 0x1737) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_SET_THRESHOLD[7:0] BIT NUMBER NAME TYPE 7-0 SF_SET_THRESHOLD[7: 0] R/W DESCRIPTION SF_SET_THRESHOLD – LSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF SET Threshold – Byte 1” registers permit the user to specify the number of B2 byte errors that will cause the Redundant Receive STS-3 TOH Processor block to declare the SF (Signal Failure) defect condition. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SF defect condition, it will accumulate B2 byte errors throughout the “SF Defect Monitoring Period”. If the number of accumulated B2 byte errors exceeds that which has been programmed into this and the “Redundant Receive STS-3 Transport SF SET Threshold – Byte 1” register, then the Redundant Receive STS-3 TOH Processor block will declares the SF defect condition. 290 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 190: Redundant Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 1 (Address Location= 0x173A) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_CLEAR_THRESHOLD[15:8] BIT NUMBER NAME TYPE 7-0 SF_CLEAR_THRESHOLD [15:8] R/W DESCRIPTION SF_CLEAR_THRESHOLD – MSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF CLEAR Threshold – Byte 0” registers permit the user to specify the upper limit for the number of B2 byte errors that will cause the Redundant Receive STS-3 TOH Processor block to clear the SF (Signal Failure) defect condition. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condition, it will accumulate B2 byte errors throughout the “SF Defect Clearance Monitoring Period”. If the number of accumulated B2 byte errors is less than that programmed into this and the “Redundant Receive STS-3 Transport SF CLEAR Threshold – Byte 0” register, then the Redundant Receive STS-3 TOH Processor block will clear the SF defect condition. 291 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 191: Redundant Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 0 (Address Location= 0x173B) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_CLEAR_THRESHOLD[7:0] BIT NUMBER NAME TYPE 7-0 SF_CLEAR_THRESHOLD [7:0] R/W DESCRIPTION SF_CLEAR_THRESHOLD – LSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF CLEAR Threshold – Byte 1” registers permit the user to specify the upper limit for the number of B2 bit errors that will cause the Redundant Receive STS-3 TOH Processor block to clear the SF (Signal Failure) defect condition. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condition, it will accumulate B2 byte errors throughout the “SF Defect Clearance Monitoring Period”. If the number of accumulated B2 byte errors is less than that programmed into this and the “Redundant Receive STS-3 Transport SF CLEAR Threshold – Byte 1” register, then the Redundant Receive STS-3 TOH Processor block will clear the SF defect condition. 292 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 192: Redundant Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 2 (Address Location= 0x173D) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 SD_SET_MONITOR_WINDOW[23:16] BIT NUMBER NAME TYPE 7-0 SD_SET_MONITOR_WINDOW [23:16] R/W DESCRIPTION SD_SET_MONITOR_INTERVAL – MSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF SET Monitor Interval – Byte 1 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect declaration. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal, in order to determine if it should declare SD defect condition, it will accumulate B2 byte errors throughout the userspecified “SD Defect Declaration monitoring period”. If, during this “SD Defect Declaration Monitoring period”, the Redundant Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Redundant Receive STS-3 Transport SD SET Threshold” register, then the Redundant Receive STS-3 TOH Processor block will declare the SD defect condition. NOTES: 293 1. The value that the user writes into these three (3) “SD Set Monitor Window” registers, specifies the duration of the “SD Defect Declaration Monitoring Period”, in terms of ms. 2. This particular register byte contains the “MSB” (Most Signficant Byte) value of the three registers that specify the “SD Defect Declaration Monitoring Period”. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 193: Redundant Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 1 (Address Location= 0x173E) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 SD_SET_MONITOR_WINDOW[15:8] BIT NUMBER NAME TYPE DESCRIPTION 7-0 SD_SET_MONITOR_WINDOW[15:8] R/W SD_SET_MONITOR_INTERVAL – Bits 15 through 8: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SD SET Monitor Interval – Byte 2 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect declaration. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SD defect condition, it will accumulate B2 byte errors throughout the userspecified “SD Defect Declaration Monitoring Period”. If, during this “SD Defect Declaration Monitoring Period” the Redundant Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Redundant Receive STS-3 Transport SD SET Threshold” register, then the Redundant Receive STS-3 TOH Processor block will declare the SD defect condition. NOTE: The value that the user writes into these three (3) “SD Set Monitor Window” registers, specifies the duration of the “SD Defect Declaration” Monitoring Period, in terms of ms. 294 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 194: Redundant Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 0 (Address Location= 0x173F) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 SD_SET_MONITOR_WINDOW[7:0] BIT NUMBER NAME TYPE 7-0 SD_SET_MONITOR_WINDOW[ 7:0] R/W DESCRIPTION SD_SET_MONITOR_INTERVAL – LSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SD SET Monitor Interval – Byte 2 and Byte 1” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect declaration. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SD defect condition, it will accumulate B2 byte errors throughout the userspecified “SD Defect Declaration Monitoring Period”. If, during the “SD Defect Declaration Monitoring Period”, the Redundant Receive STS-3 TOH Processor block accumulates more B2 byte errors than that specified within the “Redundant Receive STS-3 Transport SD SET Threshold” register, then the Redundant Receive STS-3 TOH Processor block will declare the SD defect condition. NOTES: 295 1. The value that the user writes into these three (3) “SD Set Monitor Window” Registers, specifies the duration of the “SD Defect Declaration” Monitoring Period, in terms of ms. 2. This particular register byte contains the “LSB” (least significant byte) value of the three registers that specify the “SD Defect Declaration Monitoring period”. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 195: Redundant Receive STS-3 Transport – Receive SD SET Threshold – Byte 1 (Address Location= 0x1742) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SD_SET_THRESHOLD[15:8] BIT NUMBER NAME TYPE 7-0 SD_SET_THRESHOLD[15:8] R/W DESCRIPTION SD_SET_THRESHOLD – MSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SD SET Threshold – Byte 0” registers permit the user to specify the number of B2 byte errors that will cause the Redundant Receive STS-3 TOH Processor block to declare the SD (Signal Degrade) defect condition. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SD defect condition, it will accumulate B2 byte errors throughout the “SD Defect Declaration Monitoirng Period”. If the number of accumulated B2 byte errors exceeds that value, which is programmed into this and the “Redundant Receive STS-3 Transport SD SET Threshold – Byte 0” register, then the Redundant Receive STS-3 TOH Processor block will declare the SD defect condition. 296 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 196: Redundant Receive STS-3 Transport – Receive SD SET Threshold – Byte 0 (Address Location= 0x1743) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 1 1 1 1 1 BIT 2 BIT 1 BIT 0 R/W R/W R/W 1 1 1 SD_SET_THRESHOLD[7:0] BIT NUMBER NAME TYPE 7-0 SD_SET_THRESHOLD[7:0] R/W DESCRIPTION SD_SET_THRESHOLD – LSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SD SET Threshold – Byte 1” registers permit the user to specify the number of B2 byte errors that will cause the Redundant Receive STS-3 TOH Processor block to declare the SD (Signal Degrade) defect condition. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should declare the SD defect condition, it will accumulate B2 byte errors throughout the “SD Defect Monitoring Period”. If the number of accumulated B2 byte errors exceeds that which has been programmed into this and the “Redundant Receive STS-3 Transport SD SET Threshold – Byte 1” register, then the Redundant Receive STS-3 TOH Processor block will declare the SD defect condition. 297 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 197: Redundant Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 1 (Address Location= 0x1746) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SD_CLEAR_THRESHOLD[15:8] BIT NUMBER NAME TYPE 7-0 SD_CLEAR_THRESHOLD[15:8] R/W DESCRIPTION SD_CLEAR_THRESHOLD – MSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SD CLEAR Threshold – Byte 0” registers permit the user to specify the upper limit for the number of B2 byte errors that will cause the Redundant Receive STS-3 TOH Processor block to clear the SD (Signal Degrade) defect condition. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors throughout the “SD Defect Clearance Monitoring Period”. If the number of accumulated B2 byte errors is less than that programmed into this and the “Redundant Receive STS-3 Transport SD CLEAR Threshold – Byte 0” register, then the Redundant Receive STS-3 TOH Processor block will clear the SD defect condition. 298 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 198: Redundant Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 1 (Address Location= 0x1747) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SD_CLEAR_THRESHOLD[7:0] BIT NUMBER NAME TYPE 7-0 SD_CLEAR_THRESHOLD[7:0] R/W DESCRIPTION SD_CLEAR_THRESHOLD – LSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SD CLEAR Threshold – Byte 1” registers permit the user to specify the upper limit for the number of B2 byte errors that will cause the Redundant Receive STS-3 TOH Processor block to clear the SD (Signal Degrade) defect condition. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors, throughout the “SD Defect Clearance Monitoring Period”. If the number of accumulated B2 byte errors is less than that programmed into this and the “Redundant Receive STS-3 Transport SD CLEAR Threshold – Byte 1” register, then the Redundant Receive STS-3 TOH Processor block will clear the SD defect condition. 299 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 199: Redundant Receive STS-3 Transport – Force SEF Condition Register (Address Location= 0x174B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Unused BIT 0 SEF FORCE R/O R/O R/O R/O R/O R/O R/O R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–1 Unused R/O 0 SEF FORCE R/W DESCRIPTION SEF Force: This READ/WRITE bit-field permits the user to force the Redundant Receive STS-3 TOH Processor block to declare the SEF defect condition. The Redundant Receive STS-3 TOH Processor block will then attempt to reacquire framing. Writing a “1” into this bit-field configures the Redundant Receive STS-3 TOH Processor block to declare the SEF defect. The Redundant Receive STS-3 TOH Processor block will automatically set this bit-field to “0” once it has reacquired framing (e.g., has detected two consecutive STS-3 frames with the correct A1 and A2 bytes). 300 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 200: Redundant Receive STS-3 Transport – Receive SD Burst Error Tolerance – Byte 1 (Address Location= 0x1752) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 1 1 1 1 1 BIT 2 BIT 1 BIT 0 R/W R/W R/W 1 1 1 SD_BURST_TOLERANCE[15:8] BIT NUMBER NAME TYPE 7-0 SD_BURST_ TOLERANCE [15:8] R/W DESCRIPTION SD_BURST_TOLERANCE – MSB: These READ/WRITE bits, along with the contents of the “Redundant Receive STS-3 Transport – SD BURST Tolerance – Byte 0” registers permit the user to specify the maximum number of B2 bit errors that the Redundant Receive STS-3 TOH Processor block can accumulate during a single SubInterval period (e.g., an STS-3 frame period), when determining whether or not to declare the SD (Signal Degrade) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 byte error burst filtering, when the Redundant Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Redundant Receive STS-3 TOH Processor block to detect B2 bit errors in multiple “SubInterval” periods before it will declare the SD defect condition. 301 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 201: Redundant Receive STS-3 Transport – Receive SD Burst Error Tolerance – Byte 0 (Address Location= 0x1753) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SD_BURST_TOLERANCE[7:0] BIT NUMBER NAME TYPE 7-0 SD_BURST_ TOLERANCE [7:0] R/W DESCRIPTION SD_BURST_TOLERANCE – LSB: These READ/WRITE bits, along with the contents of the “Redundant Receive STS-3 Transport – SD BURST Tolerance – Byte 1” registers permit the user to specify the maximum number of B2 bit errors that the Redundant Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare the SD (Signal Degrade) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 byte error burst filtering, when the Redundant Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SD defect condition. The user can implement this feature in order to configure the Redundant Receive STS-3 TOH Processor block to detect B2 bit errors in multiple “Sub-Interval” periods before it will declare the SD defect condition. 302 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 202: Redundant Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 1 (Address Location= 0x1756) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SF_BURST_TOLERANCE[15:8] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 BIT NUMBER NAME TYPE 7-0 SF_BURST_ TOLERANCE [15:8] R/W DESCRIPTION SF_BURST_TOLERANCE – MSB: These READ/WRITE bits, along with the contents of the “Redundant Receive STS-3 Transport – SF BURST Tolerance – Byte 0” registers permit the user to specify the maximum number of B2 bit errors that the Redundant Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare the SF (Signal Failure) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 byte error burst filtering, when the Redundant Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Redundant Receive STS-3 TOH Processor block to detect B2 bit errors in multiple “Sub-Interval” periods before it will declare the SF defect condition. Table 203: Redundant Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 0 (Address Location= 0x1757) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_BURST_TOLERANCE[7:0] BIT NUMBER NAME TYPE 7-0 SF_BURST_ TOLERANCE [7:0] R/W DESCRIPTION SF_BURST_TOLERANCE – LSB: These READ/WRITE bits, along with the contents of the “Redundant Receive STS-3 Transport – SF BURST Tolerance – Byte 1” registers permit the user to specify the maximum number of B2 bit errors that the Redundant Receive STS-3 TOH Processor block can accumulate during a single Sub-Interval period (e.g., an STS-3 frame period), when determining whether or not to declare the SF (Signal Failure) defect condition. Note: The purpose of this feature is to permit the user to provide some level of B2 byte error burst filtering, when the Redundant Receive STS-3 TOH Processor block is accumulating B2 byte errors in order to declare the SF defect condition. The user can implement this feature in order to configure the Redundant Receive STS-3 TOH Processor block to detect B2 bit errors in multiple “Sub-Interval” periods before it will declare the SF defect condition. Table 204: Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 2 (Address Location= 0x1759) 303 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Rev222...000...000 BIT 1 BIT 0 SD_CLEAR_MONITOR_WINDOW[23:16] R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 BIT NUMBER NAME TYPE 7-0 SD_CLEAR_MONITOR_WINDOW[23: 16] R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL – MSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SD Clear Monitor Interval – Byte 1 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect clearance. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors throughout the userspecified “SD Defect Clearance” Monitoring period. If, during this “SD Defect Clearance Monitoring” period, the Redundant Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Redundant Receive STS-3 Transport SD Clear Threshold” register, then the Redundant Receive STS-3 TOH Processor block will clear the SD defect condition. NOTES: 304 1. The value that the user writes into these three (3) “SD Clear Monitor Window” Registers, specifies the duration of the “SD Defect Clearance Monitoring Period” in terms of ms. 2. This particular register byte contains the “MSB” (Most Significant Byte) value of the three registers that specify the “SD Defect Clearance Monitoring” period. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 205: Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1 (Address Location= 0x175A) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SD_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER NAME TYPE 7-0 SD_CLEAR_MONITOR_WINDOW[15:8] R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL through 8: – Bits 15 These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SD Clear Monitor Interval – Byte 2 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect clearance. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors throughout the user-specified “SD Defect Clearance” Monitoring period. If, during this “SD Defect Clearance Monitoring Period” the Redundant Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Redundant Receive STS-3 Transport SD Clear Threshold” register, then the Redundant Receive STS-3 TOH Processor block will clear the SD defect condition. NOTE: The value that the user writes into these three (3) “SD Clear Monitor Window” Registers, specifies the duration of the “SD Defect Clearance Monitoring Period”, in terms of ms. 305 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 206: Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0 (Address Location= 0x175B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 1 1 1 1 1 BIT 2 BIT 1 BIT 0 R/W R/W R/W 1 1 1 SD_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER NAME TYPE 7-0 SD_CLEAR_MONITOR_WINDOW[ 7:0] R/W DESCRIPTION SD_CLEAR_MONITOR_INTERVAL – LSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SD Clear Monitor Interval – Byte 2 and Byte 1” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SD (Signal Degrade) defect clearance. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SD defect condition, it will accumulate B2 byte errors throughout the user-specified “SD Defect Clearance” Monitoring period. If, during this “SD Defect Clearance Monitoring” period, the Redundant Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Redundant Receive STS-3 Transport SD Clear Threshold” register, then the Redundant Receive STS-3 TOH Processor block will clear the SD defect condition. NOTES: 306 1. The value that the user writes into these three (3) “SD Clear Monitor Window” Registers, specifies the duration of the “SD Defect Clearance Monitoring Period”, in terms of ms. 2. This particular register byte contains the “LSB” (least significant byte) value of the three registers that specify the “SD Defect Clearance Monitoring” period. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 207: Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2 (Address Location= 0x175D) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 1 1 1 1 1 BIT 2 BIT 1 BIT 0 R/W R/W R/W 1 1 1 SF_CLEAR_MONITOR_WINDOW[23:16] BIT NUMBER NAME TYPE 7-0 SF_CLEAR_MONITOR_WINDO W [23:16] R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL – MSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF Clear Monitor Interval – Byte 1 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) defect clearance. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condition, it will accumulate B2 byte errors throughout the user-specified “SF Defect Clearance” Monitoring period. If, during the “SF Defect Clearance” Monitoring period, the Redundant Receive STS3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Redundant Receive STS-3 Transport SF Clear Threshold” register, then the Redundant Receive STS-3 TOH Processor block will clear the SF defect condition. NOTES: 307 3. The value that the user writes into these three (3) “SF Clear Monitor Window Registers”, specifies the duration of the “SF Defect Clearance Monitoring Period”, in terms of ms. 4. This particular register byte contains the “MSB” (most significant byte) value fo the three registers that specify the “SF Defect Clearance Monitoring” period. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 208: Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1 (Address Location= 0x175E) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_CLEAR_MONITOR_WINDOW[15:8] BIT NUMBER NAME TYPE DESCRIPTION 7-0 SF_CLEAR_MONITOR_WINDOW [15:8] R/W SF_CLEAR_MONITOR_INTERVAL – Bits 15 through 8: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF Clear Monitor Interval – Byte 2 and Byte 0” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) defect clearance. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condition, it will accumulate B2 byte errors throughout the userspecified “SF Defect Clearance” Monitoring period. If, during this “SF Defect Clearance” Monitoring period, the Redundant Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Redundant Receive STS-3 Transport SF Clear Threshold” register, then the Redundant Receive STS3 TOH Processor block will clear the SF defect condition. NOTES: The value that the user writes into these three (3) “SF Clear Monitor Window” Registers, specifies the duration of the “SF Defect Clearance Monitoring Period”, in terms of ms. 308 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 209: Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 0 (Address Location= 0x175F) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 SF_CLEAR_MONITOR_WINDOW[7:0] BIT NUMBER NAME TYPE 7-0 SF_CLEAR_MONITOR_WINDOW [7:0] R/W DESCRIPTION SF_CLEAR_MONITOR_INTERVAL – LSB: These READ/WRITE bits, along the contents of the “Redundant Receive STS-3 Transport – SF Clear Monitor Interval – Byte 2 and Byte 1” registers permit the user to specify the length of the “monitoring period” (in terms of ms) for SF (Signal Failure) defect clearance. When the Redundant Receive STS-3 TOH Processor block is checking the incoming STS-3 signal in order to determine if it should clear the SF defect condition, it will accumulate B2 byte errors throughout the userspecified “SF Defect Clearance” Monitoring period. If, during this “SF Defect Clearance Monitoring” period, the Redundant Receive STS-3 TOH Processor block accumulates less B2 byte errors than that programmed into the “Redundant Receive STS-3 Transport SF Clear Threshold” register, then the Redundant Receive STS3 TOH Processor block will clear the SF defect condition. NOTES: 309 3. The value that the user writes into these three (3) “SF Clear Monitor Window” Registers, specifies the duration of the “SF Defect Clearance Monitoring” period, in terms of ms. 4. This particular register byte contains the “LSB” (Least Significant byte) value of the three registers that specify the “SF Defect Clearance Monitoring” period. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 210: Redundant Receive STS-3 Transport – Serial Port Control Register (Address Location= 0x1767) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 RxTOH_CLOCK_SPEED[7:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Unused R/O 3-0 RxTOH_CLOCK_SPEED[7:0] R/W DESCRIPTION RxTOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permit the user to specify the frequency of the “RxTOHClk output clock signal. The formula that relates the contents of these register bits to the “RxTOHClk” frequency is presented below. FREQ = 19.44 /[2 * (RxTOH_CLOCK_SPEED + 1) Note: 310 For STS-3/STM-1 applications, the frequency of the RxTOHClk output signal must be in the range of 0.6075MHz to 9.72MHz XRT94L33 Rev222...000...000 1.7 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S TRANSMIT STS-3 TOH PROCESSOR BLOCK The register map for the Transmit STS-3 TOH Processor Block is presented in the Table below. Additionally, a detailed description of each of the “Transmit STS-3 TOH Processor” block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the “Transmit STS-3 TOH Processor Block “highlighted” is presented below in Figure 4 Figure 4: Illustration of the Functional Block Diagram of the XRT94L33, with the Transmit STS-3 TOH Processor Block “High-lighted”. Tx TxSTS-3 STS-3 TOH TOHProcessor Processor Block Block Rx RxSTS-3 STS-3TOH TOH Processor Rx STS-3 Processor Rx STS-3TOH TOH Block Processor Block Block Processor Block (Primary) (Primary) STS-3 STS-3 Telecom TelecomBus Bus Block Block Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (Primary) (Primary) Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (APS) (APS) Tx TxSONET SONET POH POH Processor Processor Block Block Rx RxSONET SONET POH POH Processor Processor Block Block Rx RxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block Tx TxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block Rx RxSTS-1 STS-1 POH POH Block Block Rx RxSTS-1 STS-1 TOH TOH Block Block Tx TxSTS-1 STS-1 POH POH Block Block Tx TxSTS-1 STS-1 TOH TOH Block Block DS3/E3 DS3/E3 Jitter Jitter Attenuator Attenuator Block Block DS3/E3 DS3/E3 Framer Framer Block Block Channel 1 To Channels 2 – 3 From Channels 2 – 3 Clock ClockSynthesizer SynthesizerBlock Block Microprocessor MicroprocessorInterface Interface 311 JTAG JTAGTest TestPort Port XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 TRANSMIT STS-3 TOH PROCESSOR BLOCK REGISTER Table 211: Transmit STS-3 TOH Processor Block Registers – Address Map ADDRESS LOCATION 0x1800 – 0x1901 REGISTER NAME DEFAULT VALUES Reserved 0x00 0x1902 Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 0x00 0x1903 Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 0x00 0x1904 – 0x1915 Reserved 0x00 0x1916 Reserved 0x00 0x1917 Transmit STS-3 Transport – Transmit A1 Byte Error Mask – Low Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3 Transport – Transmit A2 Byte Error Mask – Low Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3 Transport – B1 Byte Error Mask Register 0x00 Reserved 0x00 Transmit STS-3 Transport – Transmit B2 Byte Error Mask Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3 Transport – Transmit B2 Byte - Bit Error Mask Register – Byte 0 0x00 Reserved 0x00 0x192E Transmit STS-3 Transport – K1K2 Byte (APS) Value Register – Byte 1 0x00 0x192F Transmit STS-3 Transport – K1K2 Byte (APS) Value Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3 Transport – RDI-L Control Register 0x00 Reserved 0x00 Transmit STS-3 Transport – M1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3 Transport – S1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3 Transport – F1 Byte Value Register 0x00 Reserved 0x00 0x1943 Transmit STS-3 Transport – E1 Byte Value Register 0x00 0x1944 Transmit STS-3 Transport – E2 Byte Control Register 0x00 0x1945 Reserved 0x00 0x1918 – 0x191E 0x191F 0x1920 – 0x1921 0x1923 0x1924 – 0x1926 0x1927 0x1928 – 0x192A 0x192B 0x192C – 0x192D 0x1930 – 0x1931 0x1933 0x1934 – 0x1936 0x1937 0x1938 – 0x193A 0x193B 0x193C – 0x193E 0x193F 0x40 – 0x42 0x1940 – 0x1942 312 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S ADDRESS LOCATION REGISTER NAME DEFAULT VALUES 0x1946 Transmit STS-3 Transport – E2 Byte Pointer Register 0x00 0x1947 Transmit STS-3 Transport – E2 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3 Transport – Transmit J0 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3 Transport – Transmit J0 Byte Control Register 0x00 Reserved 0x00 Transmit STS-3 Transport – Serial Port Control Register 0x00 Reserved 0x00 0x1948 – 0x194A 0x194B 0x194C – 0x194E 0x194F 0x1950 – 0x1952 0x1953 0x1954 –0x19FF 313 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1.7.1 Rev222...000...000 TRANSMIT STS-3 TOH PROCESSOR BLOCK REGISTER DESCRIPTION Table 212: Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 (Address Location= 0x1902) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Reserved STS-N Overhead Insert E2 Byte Insert Method E1 Byte Insert Method F1 Byte Insert Method S1 Byte Insert Method K1K2 Byte Insert Method M1 Byte Insert Method[1] R/O R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 STS-N Overhead Insert R/W DESCRIPTION STS-N Overhead Insert: This READ/WRITE bit-field permits the user to configure the TxTOH input port to insert the TOH for all lower-tributary STS-1s within the outbound STS-3 signal. 0 – Disables this feature. In this mode, the TxTOH input port will only accept the TOH for the first STS-1 within the outbound STS-3 signal. 1 – Enables this feature. 5 E2 Byte Insert Method R/W E2 Byte Insert Method: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to use either the contents within the “Transmit STS-3 Transport – E2 Byte Value” Register or the TxTOH input port as the source for the E2 byte, within the outbound STS-3 datastream, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to accept externally supplied data (via the “TxTOH serial input port) and to insert this data into the E2 byte position within each outbound STS-3 frame. 1 – Configures the Transmit STS-3 TOH Processor block to insert the contents within the “Transmit STS-3 Transport – E2 Byte Value” register (Address Location = 0x1947) into the E2 byte-position, within each outbound STS-3 frame. This configuration selection permits the user to have software control over the value of the E2 byte within the “Transmit Output” STS-3 data-stream. 4 E1 Byte Insert Method R/W E1 Byte Insert Method: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to use either the contents within the “Transmit STS-3 Transport – E1 Byte Value” Register or the TxTOH Input port as the source for the E1 byte, within the outbound STS-3 datastream, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to accept externally supplied data (via the “TxTOH serial input port) and to insert this data into the E1 byte position within each outbound STS-3 frame. 1 – Configures the Transmit STS-3 TOH Processor block to insert the contents within the “Transmit STS-3 Transport – E1 Byte Value” register (Address Location = 0x1943) into the E1 byte-position, within each outbound STS-3 frame. This configuration selection permits the user to have software control over the value of the E1 byte within the “Transmit Output” STS-3 data-stream. 314 XRT94L33 Rev222...000...000 3 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S F1 Byte Insert Method R/W F1 Byte Insert Method: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to use either the contents within the “Transmit STS-3 Transport – F1 Byte Value” Register or the TxTOH Input port as the source for the F1 byte, within the outbound STS-3 datastream, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to accept externally supplied data (via the “TxTOH” serial input port) and to insert this data into the F1 Byte position within each outbound STS-3 frame. 1 – Configures the Transmit STS-3 TOH Processor block to insert the contents within the “Transmit STS-3 Transport – F1 Byte Value” register (Address Location = 0x193F) into the F1 byte-position, within each outbound STS-3 frame. This configuration selection permits the user to have software control over the value of the F1 byte within the “Transmit Output” STS-3 data-stream. 2 S1 Byte Insert Method R/W S1 Byte Insert Method: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to use either the contents within the “Transmit STS-3 Transport – S1 Byte Value” Register or the TxTOH Input port as the source for the E1 byte, within the outbound STS-3 datastream, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to accept externally supplied data (via the “TxTOH” serial input port) and to insert this data into the S1 Byte position within each outbound STS-3 frame. 1 – Configures the Transmit STS-3 TOH Processor block to insert the contents within the “Transmit STS-3 Transport – S1 Byte Value” register (Address Location = 0x193B). This configuration selection permits the user to have software control over the value of the S1 byte within the “Transmit Output” STS-3 data-stream. 1 K1K2 Byte Insert Method R/W K1K2 Byte Insert Method: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to use either the contents within the “Transmit STS-3 Transport – K1 Byte Value” and “Transmit STS-3 Transport – K2 Byte Value” registers or the “TxTOH Input port as the source for the K1 and K2 bytes, within the outbound STS-3 data-stream, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to accept externally supplied data (via the “TxTOH” serial input port) and to insert this data into the K1 and K2 Byte positions within each outbound STS-3 frame. 1 – Configures the Transmit STS-3 TOH Processor block to insert the contents within the “Transmit STS-3 Transport – K1 Byte Value” Register (Address Location = 0x192E) and the “Transmit STS-3 Transport – K2 Byte Value” register (Address Location = 0x192F) into the K1 and K2 byte-positions, within each outbound STS-3 frame. This configuration selection permits the user to have software control over the value of the K1 and K2 bytes within the “Transmit Output” STS-3 data-stream. 0 M1 Byte Insert Method[1] R/W M1 Byte Insert Method – Bit 1: This READ/WRITE bit-field, along with the “M1 Insert Method[0]” bit-field (located in the “Transmit STS-3 Transport – SONET Control Register – Byte 0”) permits the user to specify the source of the contents of the M1 byte, within the “transmit” output STS-3 data stream. The relationship between these two bit-fields and the corresponding source of the M1 byte (within each outbound STS-3 frame) is presented 315 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 below. M1 Byte Insert Method[1:0] Source of M1 Byte 0 0 Functions as the REI-L indicator (based upon the number of B2 byte errors that have been detected by the Receive STS-3 TOH Processor block) 0 1 The M1 byte value is obtained from the contents of the “Transmit STS-3 Transport – M1 Byte Value” register (Address Location = 0x1937). NOTE: This configuration selection permits the user to exercise software control over the contents within the M1 byte, of each outbound STS-3 frame. 1 0 The M1 byte value is obtained from the “TxTOH” Serial Input Port. 1 1 Functions as the REI-L bit-field (based upon the number of B2 byte errors that have been detected by the Receive STS-3 TOH Processor block). 316 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 213: Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 M1 Byte Insert Method[0] Unused Force Transmission of RDI-L Force Transmission of AIS-L Force Tranmission of LOS Patttern Scrambler Enable B2 Byte Error Insert A1A2 Byte Error Insert R/W R/O R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 M1 Byte Insert Method[0] R/W DESCRIPTION M1 Byte Insert Method – Bit 0: This READ/WRITE bit-field, along with the “M1 Insert Method[1]” bitfield (located in the “Transmit STS-3 Transport – SONET Control Register – Byte 1”) permits the user to specify the source of the contents of the M1 byte, within the “transmit” output STS-3 data stream. The relationship between these two bit-fields and the corresponding source of the M1 byte (within each outbound STS-3 frame) is presented below. M1 Insert Method[1:0] Source of M1 Byte 0 0 Functions as the REI-L indicator (based upon the number of B2 byte errors that have been detected by the Receive STS-3 TOH Processor block) 0 1 The M1 byte value is obtained from the contents of the “Transmit STS-3 Transport – M1 Byte Value” register (Address Location= 0x1937). NOTE: This configuration selection permits the user to exercise software control over the contents within the M1 byte of each outbound STS-3 frame. 6 Unused R/O 5 Force Transmission of RDI-L R/W 1 0 The M1 byte value is obtained from the “TxTOH” Serial Input Port. 1 1 Functions as the REI-L bit-field (based upon the number of B2 byte errors that have been detected by the Receive STS-3 TOH Processor block. Force Transmission of RDI-L (Line - Remote Defect Indicator): This READ/WRITE bit-field permits the user to (by software control) force the Transmit STS-3 TOH Processor block to generate and transmit the RDI-L indicator to the remote terminal equipment as described below. 0 – Does not configure the Transmit STS-3 TOH Processor block to generate and transmit the RDI-L indicator. In this setting, the Transmit STS-3 TOH Processor block will only generate and transmit the RDI-L indicator whenever the Receive STS-3 TOH Processor block is 317 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 declaring a defect condition. 1 – Configures the Transmit STS-3 TOH Processor block to generate and transmit the RDI-L indicator to the remote terminal equipment. In this case, the STS-3 Transmitter will force bits 6, 7 and 8 (of the K2 byte) to the value “1, 1, 0”. Note: 4 Force Transmission of AIS-L R/W This bit-field is ignored if the Transmit STS-3 TOH Processor block is transmitting the Line AIS (AIS-L) indicator or the LOS pattern. Force Transmission of AIS-L (Line AIS) Indicator: This READ/WRITE bit-field permits the user to (by software control) force the Transmit STS-3 TOH Processor block to generate and transmit the AIS-L indicator to the remote terminal equipment, as described below. 0 – Does not configure the Transmit STS-3 TOH Processor block to generate and transmit the AIS-L indicator. In this case, the Transmit STS-3 TOH Processor block will continue to transmit normal traffic to the remote terminal equipment. 1 – Configures the Transmit STS-3 TOH Processor block to generate and transmit the AIS-L indicator to the remote terminal equipment. In this case, the Transmit STS-3 TOH Processor block will force all bits (within the “outbound” STS-3 frame) with the exception of the Section Overhead Bytes to an “All Ones” pattern. Note: 3 Force Transmission of LOS Pattern R/W This bit-field is ignored if the Transmit STS-3 TOH Processor block is transmitting the LOS pattern. Force Transmission of LOS Pattern: This READ/WRITE bit-field permits the user to (by software control) force the Transmit STS-3 TOH Processor block to transmit the LOS (Loss of Signal) pattern to the remote terminal equipment, as described below. 0 – Does not configure the Transmit STS-3 TOH Processor block to generate and transmit the LOS pattern. In this case, the Transmit STS3 TOH Processor block will continue to transmit “normal” traffic to the remote terminal equipment. 1 – Configures the Transmit STS-3 TOH Processor block to transmit the LOS pattern to the remote terminal equipment. In this case, the Transmit STS-3 TOH Processor block will force all bytes (within the “outbound” SONET frame) to an “All Zeros” pattern. 2 Scrambler Enable R/W Scrambler Enable: This READ/WRITE bit-field permits the user to either enable or disable the Scrambler, within the Transmit STS-3 TOH Processor block circuitry 0 – Disables the Scrambler. 1 – Enables the Scrambler. 1 B2 Byte Error Insert R/W Transmit B2 Byte Error Insert Enable: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to insert errors into the “outbound” B2 bytes, per the contents within the “Transmit STS-3 Transport – Transmit B2 Byte Error Mask Registers” as described below. 0 – Configures the Transmit STS-3 TOH Processor block to NOT insert errors into the B2 bytes, within the outbound STS-3 signal. 1 – Configures the Transmit STS-3 TOH Processor block to insert errors into the B2 bytes (per the contents within the “Transmit B2 Byte 318 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Error Mask Registers”). 0 A1A2 Byte Error Insert R/W Transmit A1A2 Byte Error Insert Enable: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to insert errors into the “outbound” A1 and A2 bytes, per the contents within the “Transmit STS-3 Transport – Transmit A1 Byte Error Mask” and Transmit A2 Byte Error Mask” Registers. 0 – Configures the Transmit STS-3 TOH Processor block to NOT insert errors into the A1 and A2 bytes, within the outbound STS-3 datastream. 1 – Configures the Transmit STS-3 TOH Processor block to insert errors into the A1 and A2 bytes (per the contents within the “Transmit A1 Byte Error Mask” and “Transmit A2 Byte Error Mask” Registers. 319 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 214: Transmit STS-3 Transport – Transmit A1 Byte Error Mask – Low Register – Byte 0 (Address Location= 0x1917) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 A1 Byte Error in STS-1 # 2 A1 Byte Error in STS-1 # 1 A1 Byte Error in STS-1 # 0 R/O R/O R/O R/O R/O R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-3 Unused R/O 2 A1 Byte Error in STS-1 # 2 R/W DESCRIPTION A1 Byte Error in STS-1 # 2, within outbound STS-3 signal: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 # 2 within the outbound STS-3 signal, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A1 byte, within STS-1 Channel 2. 1 – Configures the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 Channel 2. In this configuration setting, the state of each bit (within this particular A1 byte) will be inverted. Hence all 8-bits within this particular A1 byte will be erred. Note: 1 A1 Byte Error in STS-1 # 1 R/W This bit-field is only valid if Bit 0 (A1A2 Byte Error Insert), within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) to “1”. A1 Byte Error in STS-1 # 1, within outbound STS-3 signal: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 # 1 within the outbound STS-3 signal, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A1 byte, within STS-1 Channel 1. 1 – Configures the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 Channel 1. In this configuration setting, the state of each bit (within this particular A1 byte) will be inverted. Hence all 8-bits within this particular A1 byte will be erred. Note: 0 A1 Byte Error in STS-1 # 0 R/W This bit-field is only valid if Bit 0 (A1A2 Byte Error Insert), within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) to “1”. A1 Byte Error in STS-1 # 0, within outbound STS-3 signal: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 # 0 within the outbound STS-3 signal, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A1 byte, within STS-1 Channel 0. 1 – Configures the Transmit STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1 Channel 0. In this configuration setting, the state of each bit (within this particular A1 byte) will be inverted. Hence, all 8-bits within this particular A1 byte will be erred. Note: This bit-field is only valid if Bit 0 (A1A2 Byte Error Insert), within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) to “1”. 320 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 215: Transmit STS-3 Transport – Transmit A2 Byte Error Mask – Low Register – Byte 0 (Address Location= 0x191F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 A2 Byte Error in STS-1 # 2 A2 Byte Error in STS-1 # 1 A2 Byte Error in STS-1 # 0 R/O R/O R/O R/O R/O R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME 7-3 Unused 2 A2 Byte Error in STS-1 # 2 TYPE DESCRIPTION R/O R/W A2 Byte Error in STS-1 # 2, within outbound STS-3 signal: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 # 2 within the outbound STS-3 signal, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A2 byte, within STS-1 Channel 2. 1 – Configures the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 2. In this configuration settting, the state of bit (within this particular A2 byte) will be inverted. Hence all 8-bits within this particular A2 byte will be erred. Note: 1 A2 Byte Error in STS-1 # 1 R/W This bit-field is only valid if Bit 0 (A1A2 Byte Error Insert), within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) to “1”. A2 Byte Error in STS-1 # 1, within outbound STS-3 signal: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 # 1 within the outbound STS-3 signal, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A2 byte, within STS-1 Channel 1. 1 – Configures the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 1. In this configuration setting, the state of each bit (within this particular A2 byte) will be inverted. Hence all 8-bits within this particular A2 byte will be erred. Note: 0 A2 Byte Error in STS-1 # 0 R/W This bit-field is only valid if Bit 0 (A1A2 Byte Error Insert), within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) to “1”. A2 Byte Error in STS-1 # 0, within the outbound STS-3 signal: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 # 0 within the outbound STS-3 signal, as described below. 0 – Configures the Transmit STS-3 TOH Processor block to NOT transmit an erred A2 byte, within STS-1 Channel 0. 1 – Configures the Transmit STS-3 TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 0. In this configuration setting, the state of each bit (within this particular A2 byte) will be inverted. Hence, all 8-bits within this particular A2 byte will be erred. Note: This bit-field is only valid if Bit 0 (A1A2 Byte Error Insert), within the 321 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) to “1”. 322 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 216: Transmit STS-3 Transport – B1 Byte Error Mask Register (Address Location= 0x1923) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B1_Byte_Error_Mask[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 B1_Byte_Error_Mask [7:0] R/W DESCRIPTION B1 Byte Error Mask[7:0]: These READ/WRITE bit-fields permit the user to insert bit errors into the B1 bytes, within the outbound STS-3 data stream. The Transmit STS-3 TOH Processor block will perform an XOR operation with the contents of the B1 byte (within each outbound STS-3 frame), and the contents within this register. The results of this calculation will be inserted into the B1 byte position within the “outbound” STS-3 data stream. For each bit-field (within this register) that is set to “1”, the corresponding bit, within the B1 byte will be in error. Note: 323 For normal operation, the user should set this register to 0x00. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 217: Transmit STS-3 Transport – Transmit B2 Byte Error Mask Register – Byte 0 (Address Location= 0x1927) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 B2 Byte Error in STS-1 Channel 2 B2 Byte Error in STS-1 Channel 1 B2 Byte Error in STS-1 Channel 0 R/O R/O R/O R/O R/O R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-3 Unused R/O 2 B2 Byte Error in STS-1 Channel # 2 R/W DESCRIPTION B2 Byte Error in STS-1 Channel # 2: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred B2 byte, within STS-1 Channel 2. If the user enables this feature, then the Transmit STS-3 TOH Processor block will perform an XOR operation of the contents of the B2 byte (within STS-1 Channel 2) and the contents of the “Transmit STS-3 Transport – Transmit B2 Bit Error Mask Register – Byte 0 (Address Location= 0x192B). The results of this calculation will be written back into the “B2 byte” position, within STS-1 Channel 2, prior to transmission to the remote terminal. 0 – Configures the Transmit STS-3 TOH Processor block to NOT insert errors into this particular B2 byte, within STS-1 Channel 2. 1 – Configures the Transmit STS-3 TOH Processor block to insert errors into the B2 byte, within STS-1 Channel 2. Note: 1 B2 Byte Error in STS-1 Channel # 1 R/W This bit-field is only valid if Bit 1 (B2 Byte Error Insert), within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address = 0x1903) to “1”. B2 Byte Error in STS-1 Channel # 1: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred B2 byte, within STS-1 Channel 1. If the user enables this feature, then the Transmit STS-3 TOH Processor block will perform an XOR operation of the contents of the B2 byte (within STS-1 Channel 1) and the contents of the “Transmit STS-3 Transport – Transmit B2 Bit Error Mask Register – Byte 0 (Address Location= 0x192B). The results of this calculation will be written back into the “B2 byte” position, within STS-1 Channel 1, prior to transmission to the remote terminal. 0 – Configures the Transmit STS-3 TOH Processor block to NOT insert errors into this particular B2 byte, within STS-1 Channel 1. 1 – Configures the Transmit STS-3 TOH Processor block to insert errors into the B2 byte, within STS-1 Channel 1. Note: 0 B2 Byte Error in STS-1 Channel # 0 R/W This bit-field is only valid if Bit 1 (B2 Byte Error Insert), within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) to “1”. B2 Byte Error in STS-1 Channel # 0: 324 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S STS-1 Channel # 0 This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to transmit an erred B2 byte, within STS-1 Channel 0. If the user enables this feature, then the Transmit STS-3 TOH Processor block will perform an XOR operation of the contents of the B2 byte (within STS-1 Channel 0) and the contents of the “Transmit STS-3 Transport – Transmit B2 Bit Error Mask Register – Byte 0 (Address Location= 0x192B). The results of this calculation will be written back into the “B2 byte” position, within STS-1 Channel 0, prior to transmission to the remote terminal. 0 – Configures the Transmit STS-3 TOH Processor block to NOT insert errors into the B2 byte, within STS-1 Channel 0. 1 – Configures the Transmit STS-3 TOH Processor block to insert errors into this particular B2 byte, within STS-1 Channel 0. Note: This bit-field is only valid if Bit 1 (B2 Byte Error Insert), within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) to “1”. 325 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 218: Transmit STS-3 Transport – Transmit B2 Bit Error Mask Register – Byte 0 (Address Location= 0x192B) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 Transmit_B2_Error_Mask[7:0] BIT NUMBER NAME TYPE 7–0 Transmit_B2_Error_Mask[7:0] R/W DESCRIPTION Transmit B2 Error Mask Byte: These READ/WRITE bit-fields permit the user to specify exact which bits, within the “selected” B2 byte (within the outbound STS-3 signal) will be erred. If the user configures the Transmit STS-3 TOH Processor block to transmit one or more erred B2 bytes, then the Transmit STS-3 TOH Processor block will perform an XOR operation of the contents of the B2 byte (within the “selected” STS-1 Channel) and the contents of this register. The results of this calculation will be written back into the “B2 byte” position within the “selected” STS-1 Channel, (within the outbound STS-3 signal) prior to transmission to the remote terminal. The user can select which STS-1 channels (within the outbound STS-3 signal) will contain the “erred” B2 byte, by writing the appropriate data into the “Transmit STS-3 Transport – Transmit B2 Byte Error Mask Register – Bytes 1 and 0 (Address Location= 0x1927). Note: 326 This bit-field is only valid if Bit 1 (B2 Error Insert), within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location= 0x1903) to “1”. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 219: Transmit STS-3 Transport – K1K2 (APS) Value Register – Byte 1 (Address Location= 0x192E) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/W R/W R/W R/W R/W 0 0 0 0 0 BIT 2 BIT 1 BIT 0 R/W R/W R/W 0 0 0 Transmit_K2_Byte_Value[7:0] BIT NUMBER NAME TYPE 7–0 Transmit_K2_Byte_Value[7:0] R/W DESCRIPTION Transmit K2 Byte Value: If the user has configured the Transmit STS-3 TOH Processor Block to use the contents of the “Transmit K2 Byte Value” Register as the source for the K2 byte value (within the outbound STS-3 data-stream), then these READ/WRITE bitfields will permit the user to specify the contents of the K2 byte, within the “outbound” STS-3 signal. If Bit 1 (K1K2 Byte Insert Method) within the Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 (Address Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH Processor block will load the contents of this register into the “K2” byte-field, within each outbound STS-3 frame. Note: 327 These register bits are ignored if Bit 1 (K1K2 Insert Method) is set to “0”. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 220: Transmit STS-3 Transport – K1K2 (APS) Value Register – Byte 0 (Address Location= 0x192F) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 Transmit_K1_Byte_Value[7:0] BIT NUMBER NAME TYPE 7–0 Transmit_K1_Byte_Value[7:0] R/W DESCRIPTION Transmit K1 Byte Value: If the user has configured the Transmit STS-3 TOH Processor block to use the contents of the “Transmit K1 Byte Value” Register as the source for the K1 byte value (within the outbound STS-3 data-stream), then these READ/WRITE bit-fields will permit the user to specify the contents of the K1 byte, within the “outbound” STS-3 signal. If Bit 1 (K1K2 Byte Insert Method) within the Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 (Address Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH Processor block will load the contents of this register into the “K1” byte-field, within each outbound STS-3 frame. Note: 328 These register bits are ignored if Bit 1 (K1K2 Insert Method) is set to “0”. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 221: Transmit STS-3 Transport – RDI-L Control Register (Address Location= 0x1933) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 External RDI-L Enable Transmit RDI-L upon AIS-L Transmit RDI-L upon LOF Transmit RDI-L upon LOS R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–4 Unused R/O 3 External RDI-L Enable R/W DESCRIPTION External RDI-L Insertion Enable: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor to accept data via the “TxTOH” input pin, when transmitting the RDI-L indicator to the remote terminal equipment. 0 – Configures the Transmit STS-3 TOH Processor block to internally generate the RDI-L indicator based upon defect conditions that are being declared by the Receive STS-3 TOH Processor block. 1 – Configure the Transmit STS-3 TOH Processor block accept external data via the “TxTOH” input port and to load this value into Bits 6, 7 and 8 (within the K2 byte) within each outbound STS-3 data-stream. 2 Transmit RDI-L upon AIS-L R/W Transmit Line Remote Defect Indicator (RDI-L) upon Declaration of the AIS-L defect condition: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator to the remote LTE anytime (and for the duration) that the Receive STS-3 TOH Processor is declaring the Line AIS (AIS-L) defect condition as described below. 0 – Configures the Transmit STS-3 TOH Processor block to NOT automatically transmit the RDI-L indicator, whenever (and for the duration that) the Receive STS-3 TOH Processor block is declares the AIS-L defect condition. 1 – Configures the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator, whenever (and for the duration that) the Receive STS-3 TOH Processor block declares the AIS-L defect condition. 1 Transmit RDI-L upon LOF R/W Transmit Line Remote Defect Indicator (RDI-L) upon Declaration of the LOF defect condition: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator to the remote LTE anytime (and for the duration) that the Receive STS-3 TOH Processor block is declaring the LOF defect condition as described below. 0 – Configures the Transmit STS-3 TOH Processor to NOT automatically transmit the RDI-L indicator, whenever the Receive STS-3 TOH Processor block declares the LOF defect condition. 1 – Configures the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator, whenever (and for the duration that) the Receive STS-3 TOH Processor block declares 329 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 the LOF defect condition. 0 Transmit RDI-L upon LOS R/W Transmit Line Remote Defect Indicator (RDI-L) upon Declaration of the LOS defect condition: This READ/WRITE bit-field permits the user to configure the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator to the remote LTE anytime (and for the duration) that the Receive STS-3 TOH Processor block declares the LOS defect condition. 0 – Configures the Transmit STS-3 TOH Processor block to NOT automatically transmit the RDI-L indicator, whenever the Receive STS-3 TOH Processor block declares the LOS defect condition. 1 – Configures the Transmit STS-3 TOH Processor block to automatically transmit the RDI-L indicator, whenever (and for the duration that) the Receive STS-3 TOH Processor block declares the LOS defect condition. 330 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 222: Transmit STS-3 Transport – M1 Byte Value Register (Address Location= 0x1937) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_M1_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Transmit_M1_Byte_Value [7:0] R/W DESCRIPTION Transmit M1 Byte Value: If the appropriate “M1 Byte Insert Method” is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the M1 byte, within the “outbound” STS-3 signal. If Bit 0 (M1 Byte Insert Method – Bit 1) within the Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 (Address Location= 0x1902) and Bit 7 (M1 Byte Insert Method – Bit 0) within the Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location = 0x1903) is set to “[0, 1]”, then the Transmit STS-3 TOH Processor block will load the contents of this register into the “M1” byte-field, within each outbound STS-3 frame. Note: These register bits are ignored if the M1 Byte Insert Method[1:0] bits are set to any value other than “[0, 1]”. Table 223: Transmit STS-3 Transport – S1 Byte Value Register (Address Location= 0x193B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_S1_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Transmit_S1_Byte_Value[7:0] R/W DESCRIPTION Transmit S1 Byte Value: If the appropriate “S1 Insert Method” is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the S1 byte, within the “outbound” STS-3 signal. If Bit 2 (S1 Byte Insert Method) within the Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 (Address Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH Processor block will load the contents of this register into the “S1” byte-field, within each outbound STS-3 frame. Note: 331 These register bits are ignored if Bit 2 (S1 Byte Insert Method) is set to “0”. XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 224: Transmit STS-3 Transport – F1 Byte Value Register (Address Location= 0x193F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_F1_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Transmit_F1_Byte_Value[7:0] R/W DESCRIPTION Transmit F1 Byte Value: If the appropriate “F1 Byte Insert Method” is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the F1 byte, within the “outbound” STS-3 signal. If Bit 3 (F1 Byte Insert Method) within the Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 (Address Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH Processor block will load the contents of this register into the “F1” byte-field, within each outbound STS-3 frame. Note: These register bits are ignored if Bit 3 (F1 Byte Insert Method) is set to “0”. Table 225: Transmit STS-3 Transport – E1 Byte Value Register (Address Location= 0x1943) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 Transmit_E1_Byte_Value[7:0] BIT NUMBER NAME TYPE 7–0 Transmit_E1_Byte_Value[7:0] R/W DESCRIPTION Transmit E1 Byte Value: If the appropriate “E1 Byte Insert Method” is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the E1 byte, within the “outbound” STS-3 signal. If Bit 4 (E1 Byte Insert Method) within the Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 (Address Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH Processor block will load the contents of this register into the “E1” byte-field, within each outbound STS-3 frame. Note: 332 These register bits are ignored if Bit 4 (E1 Byte Insert Method) is set to “0”. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 226: Transmit STS-3 Transport – E2 Byte Control Register (Address Location= 0x1944) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Enable All STS-1s BIT 2 BIT 1 BIT 0 Unused R/W R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Enable All STS-1s R/W DESCRIPTION Enable All STS-1s: This READ/WRITE bit-field permits the user to implement either of the following configurations options for software control of the E2 byte value, within the outbound STS-3 signal. 0 – Configures the Transmit STS-3 TOH Processor block to read out the contents of the “Transmit STS-3 Transport – E2 Byte Value” register and load that value into the E2 byte (within STS-1 # 1) within the outbound STS-3 signal. 1 – Configures the Transmit STS-3 TOH Processor block to read out the contents of the 3 “shadow” registers, and to load these values into the E2 byte positions, within each corresponding STS-1 signal; within the outbound STS-3 signal. Note: 6-0 Unused This register bit is ignored if Bit 5 (E2 Byte Insert Method) within the “Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1” (Address Location= 0x1902) is set to “0”. R/O 333 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 227: Transmit STS-3 Transport – E2 Pointer Register (Address Location= 0x1946) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Unused BIT 0 E2_Pointer[1:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–2 Unused R/O 1-0 E2_Pointer[1:0] R/W DESCRIPTION E2 Pointer[3:0]: These READ/WRITE bit-fields permit the user to uniquely identify one of the 3 STS-1 E2 byte “shadow” registers, when performing read or write operations to these registers. If the user has set Bit 7 (Enable All STS-1s), within this register to “1”, then the contents of these four register bits, act as a pointer to a given “shadow” register. Once the user specifies this pointer value; then he/she completes the read or write operation (to or from the “shadow” register) by performing a read or write to the “Transmit STS-3 Transport – E2 Byte Value” register (Address Location= 0x1947). Valid “shadow” pointer values range from “0x00” to “0x02” (where the pointer value of “0x00” corresponds to the E2 “shadow” register, corresponding to STS-1 # 1; and so on). Note: This register bit is ignored if Bit 7 (Enable All STS-1s) is set to “1”; or if Bit 5 (E2 Byte Insert Method) within the “Transmit STS3 Transport – SONET Transmit Control Register – Byte 1” (Address Location= 0x1902) is set to “0”. 334 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 228: Transmit STS-3 Transport – E2 Byte Value Register (Address Location=0x1947) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_E2_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Transmit_E2_Byte_Value[7:0] R/W DESCRIPTION Transmit E2 Byte Value: The exact function of these register bits depends upon whether Bit 7 (Enable All STS-1s) within the “Transmit STS-3 Transport – E2 Byte Control” Register (Address Location= 0x1944) has been set to “0” or “1”; as described below. If “Enable All STS-1s” is set to “0” If the appropriate “E2 Insert Method” is selected, then these READ/WRITE bit-fields will permit the user to specify the contents of the E2 byte, within the “outbound” STS-3 signal. More specifically, this value will be loaded into the E2 byte position, within STS-1 # 1 (within the outbound STS-3 signal). If Bit 5 (E2 Insert Method) within the Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 (Address Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH Processor block will load the contents of this register into the “E2” byte-field, within each outbound STS-3 frame. If “Enable All STS-1s” is set to “1” In this mode, these register bit permit the user to have direct READ/WRITE access of the “STS-1 E2 Byte shadow” register; that is being pointed at by the “E2 Pointer[1:0]” value. These register bits are ignored if Bit 5 (E2 Byte Insert Method) is set to “0”. 335 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 229: Transmit STS-3 Transport – J0 Byte Value Register (Address Location= 0x194B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_J0_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Transmit_J0_Value[7:0] R/W DESCRIPTION Transmit J0 Byte Value[7:0]: If the user has configured the Transmit STS-3 TOH Processor block to use the “Transmit J0 Byte Value” Register as the “source” of the “outbound” Section Trace Message, then these READ/WRITE bits will permit the user to specify the contents within the J0 byte of each outbound STS-3 frame. Note: 336 This register is only valid if the Transmit STS-3 TOH Processor block is configured to read out the contents from this register and insert it into the J0 byte-field within each outbound STS-3 frame. The user accomplishes this by setting the “Transmit Section Trace Message Source[1:0]” bit-fields (within the Transmit STS-3 Transport – Transmit Section Trace Message Control Register – Address = 0x194F) to “1, 0”.. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 230: Transmit STS-3 Transport – Transmit Section Trace Message Control Register (Address Location= 0x194F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Transmit Section Trace Messsage Length[1:0] Unused BIT 0 Transmit Section Trace Message Source[1:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 1 1 0 0 BIT NUMBER NAME TYPE 7–4 Unused R/O 3–2 Transmit Section Trace Message Length[1:0] R/W 1–0 Transmit Section Trace Message Source[1:0] DESCRIPTION Transmit Section Trace Message Length[1:0]: These two READ/WRITE bit-fields permit the user to specify the length of the Section Trace message that the Transmit STS-3 TOH Processor block will repeatedly transmit to the remote LTE. The relationship between the contents of these bit-fields and the corresponding Transmit Section Trace Message Length is presented below. R/W Transmit Section Trace Message Length[1:0] Resulting Section Trace Message Length (in terms of bytes) 00 1 Byte 01 16 Bytes 10 or 11 64 Bytes Transmit Section Trace Message Source[1:0]: These two READ/WRITE bit-fields permit the user to specify the source of the “outbound” Section Trace message that will be transported via the J0 byte channel within the outbound STS-3 data-stream, as depicted below. Transmit Section Trace Message Source[1:0] Resulting Source of the Section Trace Message. Fixed Value: 00 The Transmit STS-3 TOH Processor block will automatically set the J0 Byte, in each “outbound” STS-3 frame to the value “0x01”. The “Transmit Buffer”. 01 Section Trace Message The Transmit STS-3 TOH Processor block will read out the contents within the Transmit Section Trace Message Buffer, and will transmit this message to the remote LTE. The “Transmit STS-3 TOH Processor block Transmit Section Trace Message Buffer” Memory is located at Address Location 0x1B00 through 0x1B3F. From the “Transmit J0 Value[7:0]” Register. 10 337 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 From the “TxTOH” Input pin (pin F8). 11 In this configuration setting, the Transmit STS-3 TOH Processor block will externally accept the contents of the “Section Trace Message” via the “TxTOH Input Port” and it will transport this message (via the J0 byte-channel) to the remote LTE. Table 231: Transmit STS-3 Transport – Serial Port Control Register (Address Location= 0x1953) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Unused BIT 2 BIT 1 BIT 0 TxTOH_CLOCK_SPEED[7:0] BIT NUMBER NAME TYPE 7-4 Unused R/O 3-0 TxTOH_CLOCK_SPEED[7:0] R/W DESCRIPTION TxTOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permits the user to specify the frequency of the “TxTOHClk output clock signal. The formula that relates the contents of these register bits to the “TxTOHClk” frequency is presented below. FREQ = 19.44 /[2 * (TxTOH_CLOCK_SPEED + 1) Note: 338 For STS-3/STM-1 applications, the frequency of the TxTOHClk output signal must be in the range of 0.6075MHz to 9.72MHz XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.8 TRANSMIT STS-3C POH PROCESSOR BLOCK REGISTERS The register map for the Transmit STS-3c POH Processor Block is presented in the Table below. Additionally, a detailed description of each of the “Transmit STS-3c POH Processor” block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the “Transmit STS-3c POH Processor Block “highlighted” is presented below in Figure 5. Figure 5: Illustration of the Functional Block Diagram of the XRT94L33, with the Transmit STS-3c POH Processor Block “High-lighted”. Channel 0 Receive ReceiveSTS-1 STS-1 Telecom TelecomBus Bus Interface Interface Block Block Clock Clock Synthesizer Synthesizer Block Block From Channels 1&2 Transmit Transmit STS-3 STS-3PECL PECL Interface Interface Block Block Receive Receive STS-1 STS-1TOH TOH Processor Processor Block Block Receive Receive STS-1 STS-1POH POH Processor Processor Block Block Transmit Transmit SONET SONETPOH POH Processor Processor Block Block Transmit Transmit STS-3 STS-3TOH TOH Processor Processor Block Block Transmit TransmitSTS-3 STS-3 Telecom TelecomBus Bus Interface Interface Block Block Transmit Transmit STS-1 STS-1TOH TOH Processor Processor Block Block Transmit Transmit STS-1 STS-1POH POH Processor Processor Block Block Receive Receive SONET SONETPOH POH Processor Processor Block Block Receive Receive STS-3 STS-3TOH TOH Processor Processor Block Block Clock Clock&& Data Data Recovery Recovery Block Block Transmit TransmitSTS-1 STS-1 Telecom TelecomBus Bus Interface Interface Block Block DS3/E3 DS3/E3 Framer Framer Block Block Receive ReceiveSTS-3 STS-3 Telecom TelecomBus Bus Interface Interface Block Block DS3/E3 DS3/E3Jitter Jitter Attenuator Attenuator Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block To Channels 1 & 2 339 Receive Receive STS-3 STS-3PECL PECL Interface Interface Block Block XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1.8.1 Rev222...000...000 TRANSMIT STS-3C POH PROCESSOR BLOCK REGISTERS Table 232: Transmit STS-3c POH Processor Block - Register Address Map ADDRESS LOCATION 0x1900 – 0x1981 REGISTER NAME DEFAULT VALUES Reserved 0x00 0x1982 Transmit STS-3c Path – SONET Control Register – Byte 1 0x00 0x1983 Transmit STS-3c Path – SONET Control Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit J1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – B3 Byte Mask Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit C2 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit G1 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit F2 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit H4 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Z3 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Z4 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Z5 Byte Value Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Path Control Register – Byte 0 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit J1 Control Register 0x00 Reserved 0x00 Transmit STS-3c Path – Transmit Arbitrary H1 Byte Pointer Register 0x94 Reserved 0x00 Transmit STS-3c Path – Transmit Arbitrary H2 Byte Pointer Register 0x00 Reserved 0x00 0x1984 – 0x1992 0x1993 0x1994 – 0x1996 0x1997 0x1998 – 0x199A 0x199B 0x199C – 0x199E 0x199F 0x19A0 – 0x19A2 0x19A3 0x19A4 – 0x19A6 0x19A7 0x19A8 – 0x19AA 0x19AB 0x19AC – 0x19AE 0x19AF 0x19B0 – 0x19B2 0x19B3 0x19B4 – 0x19B6 0x19B7 0x19B8 – 0x19BA 0x19BB 0x19BC – 0x19BE 0x19BF 0x19C0 – 0x19C2 0x19C3 0x19C4 – 0x19C5 340 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S ADDRESS LOCATION REGISTER NAME DEFAULT VALUES 0x19C6 Transmit STS-3c Path – Transmit Pointer Byte Register – Byte 1 0x02 0x19C7 Transmit STS-3c Path – Transmit Pointer Byte Register – Byte 0 0x0A 0x19C8 Reserved 0x00 0x19C9 Transmit STS-3c Path – RDI-P Control Register – Byte 2 0x40 0x19CA Transmit STS-3c Path – RDI-P Control Register – Byte 1 0xC0 0x19CB Transmit STS-3c Path – RDI-P Control Register – Byte 0 0xA0 Reserved 0x00 Transmit STS-3c Path – Transmit Path Serial Port Control Register 0x00 Reserved 0x00 0x19CC – 0x19CE 0x19CF 0x19D0 – 0x19FF 341 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1.8.2 Rev222...000...000 TRANSMIT STS-3C POH PROCESSOR BLOCK REGISTER DESCRIPTION Table 233: Transmit STS-3c Path – SONET Control Register – Byte 1 (Address Location= 0x1982) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 Z5 Byte Insertion Type Z4 Byte Insertion Type Z3 Byte Insertion Type H4 Byte Insertion Type R/W R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–4 Unused R/O 3 Z5 Byte Insertion Type R/W DESCRIPTION Z5 Byte Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS3c POH Processor block to use either the contents within the “Transmit STS-3c Path – Transmit Z5 Byte Value” Register or the TPOH input pin as the source for the Z5 byte, in the outbound STS-3c SPE data-stream, as described below. 0 – Configures the Transmit STS-3c POH Processor block to insert the contents within the “Transmit STS-3c Path – Transmit Z5 Byte Value” Register into the Z5 byte position within each outbound STS-3c SPE. 1 – Configures the Transmit STS-3c POH Processor block to accept externally supplied data (via the “TPOH” input port) and to insert this data into the Z5 byte position within each outbound STS-3c SPE. Note: 2 Z4 Byte Insertion Type R/W The Address Location of the Transmit STS-3c POH Processor Block - Transmit Z5 Byte Value Register is 0x19B3 Z4 Byte Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS3c POH Processor block to use either the contents within the “Transmit STS-3c Path – Transmit Z4 Byte Value” Register or the TxPOH input pin as the source for the Z4 byte, in the outbound STS-3c SPE data-stream, as described below. 0 – Configures the Transmit STS-3c POH Processor block to insert the contents within the “Transmit STS-3c Path – Transmit Z4 Byte Value” Register into the Z4 byte position within each outbound STS-3c SPE. 1 – Configures the Transmit STS-3c POH Processor block to accept externally supplied data (via the “TxPOH” input port) and to insert this data into the Z4 byte position within each outbound STS-3c SPE. Note: 1 Z3 Byte Insertion Type R/W The address location of the Transmit STS-3c POH Processor block -Transmit Z4 Byte Value Register is 0x19AF Z3 Byte Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS3c POH Processor block to use either the contents within the “Transmit STS-3c Path – Transmit Z3 Byte Value” Register or the TxPOH input pin as the source for the Z3 byte, in the outbound STS-3c SPE data-stream, as described below. 0 – Configures the Transmit STS-3c POH Processor block to insert the contents within the “Transmit STS-3c Path – Transmit Z3 Byte Value” Register into the Z3 byte position within each outbound STS-3c SPE. 1 – Configures the Transmit STS-3c POH Processor block to accept 342 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 externally supplied data (via the “TxPOH” input port) and to insert this data into the Z3 byte position within each outbound STS-3c SPE. Note: 0 H4 Byte Insertion Type R/W The Address Location of the Transmit STS-3c POH Processor block - Transmit Z3 Byte Value Register is 0x19AB H4 Byte Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS3c POH Processor block to use either the contents within the “Transmit STS-3c Path – Transmit H4 Byte Value” Register or the TxPOH input pin as the source for the H4 byte, in the outbound STS-3c SPE data-stream, as described below. 0 – Configures the Transmit STS-3c POH Processor block to insert the contents within the “Transmit STS-3c Path – Transmit H4 Byte Value” Register into the H4 byte position within each outbound STS-3c SPE. 1 – Configures the Transmit STS-3c POH Processor block to accept externally supplied data (via the “TPOH” input port) and to insert this data into the H4 byte position within each outbound STS-3c SPE. Note: The Address Location of the Transmit STS-3c POH Processor block -Transmit H4 Byte Value Register is 0x19A7 343 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 234: Transmit STS-3c Path – SONET Control Register – Byte 0 (Address Location= 0x1983) BIT 7 F2 Byte Insertion Type BIT 6 BIT 5 BIT 4 REI-P Insertion Type[1:0] BIT 3 RDI-P Insertion Type[1:0] BIT 2 BIT 1 BIT 0 C2 Byte Insertion Type Unused Force Transmission of AIS-P R/W R/W R/W R/W R/W R/W R/O R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 F2 Byte Insertion Type R/W DESCRIPTION F2 Byte Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to use either the contents within the “Transmit STS-3c Path – Transmit F2 Byte Value” Register or the TxPOH input pin as the source for the F2 byte, in the outbound STS-3c SPE data-stream, as described below. 0 – Configures the Transmit STS-3c POH Processor block to insert the contents within the “Transmit STS-3c Path – Transmit F2 Byte Value” Register into the F2 byte position within each outbound STS-3c SPE. 1 – Configures the Transmit STS-3c POH Processor block to accept externally supplied data (via the “TPOH” input port) and to insert this data into the F2 byte position within each outbound STS-3c SPE. Note: 6-5 REI-P Insertion Type[1:0] R/W The Address Location of the Transmit STS-3c POH Processor block Transmit F2 Byte Value Register is 0x19A3 REI-P Insertion Type[1:0]: These two READ/WRITE bit-fields permit the user to configure the Transmit STS-3c POH Processor block to use one of the three following sources for the REI-P bit-fields (e.g., bits 1 through 4, within the G1 byte) within each outbound STS-3c SPE. • From the Receive STS-3c POH Processor block (e.g., the Transmit STS-3c POH Processor block will set the REI-P bit-fields to the appropriate value, based upon the number of B3 byte errors that the Receive STS-3c POH Processor block detects and flags, within its incoming STS-3c SPE datastream). • From the “Transmit G1 Byte Value” Register. In this case, the Transmit STS3c POH Processor block will insert the contents of Bits 7 through 4 within the “Transmit STS-3c POH Processor block – Transmit G1 Byte Value” Register into the REI-P bit-fields within each outbound STS-3c SPE. • From the “TPOH” input pin. In this case, the Transmit STS-3c POH Processor block will accept externally supplied data (via the “TPOH” input port) and it will insert this data into the REI-P bit-fields within each outbound STS-3c SPE. 00/11 – Configures the Transmit STS-3c POH Processor block to set Bits 1 through 4 (in the G1 byte of the outbound SPE) based upon the number of B3 byte errors that the Receive STS-3c POH Processor block detects and flags within the incoming STS-3c data-stream. 01 – Configures the Transmit STS-3c POH Processor block to set Bits 1 through 4 (in the G1 byte of the outbound SPE) based upon the contents within the “Transmit STS-3c POH Processor block - Transmit G1 Byte Value” register. 10 – Configures the Transmit STS-3c POH Processor block to accept externally supplied data (via the TPOH input port) and to insert this data into the REI-P bitpositions within each outbound STS-3c SPE. Note: The address location of the Transmit STS-3c POH Processor block - 344 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Transmit G1 Byte Value Register is 0x199F 4-3 RDI-P Insertion Type[1:0] R/W RDI-P Insertion Type[1:0]: These two READ/WRITE bit-fields permit the user to configure the Transmit STS-3c POH Processor block to use one of the three following sources for the RDI-P bit-fields (e.g., bits 5 through 7, within the G1 byte) within each outbound STS-3c SPE. • From the corresponding Receive STS-3c POH Processor block (e g., the Transmit STS-3c POH Processor block will set the RDI-P bit-fields to the appropriate value, based upon which defect conditions are being declared by the Receive STS-3c POH Processor block, within its incoming STS-3c SPE data-stream). • From the “Transmit G1 Byte Value” Register. In this case, the Transmit STS3c POH Processor blolck will insert the content of bits 2 through 0 within the “Transmit STS-3c POH Processor block – Transmit G1 Byte Value” Register into the RDI-P bit-fields within each outbound STS-3c SPE. • From the “TPOH” input pin. In this case, the Transmit STS-3c POH Processor block will accept externally supplied data (via the “TPOH” input port) and it will insert this data into the RDI-P bit-fields within each outbound STS-3c SPE. 00/11 – Configures the Transmit STS-3c POH Processor block to set Bits 5 through 7 (in the G1 byte of the outbound SPE) based upon the defects conditions that the Receive STS-3c POH Processor block is currently declaring within the incoming STS-3c data-stream. 01 – Configures the Transmit STS-3c POH Processor block to set Bits 5 through 7 (in the G1 byte of the outbound SPE) based upon the contents within the “Transmit STS-3c POH Processor block - Transmit G1 Byte Value” register. 10 – Configures the Transmit STS-3c POH Processor block to accept externally supplied data (via the TPOH input port) and to insert this data into the RDI-P bitpositions within each outbound STS-3c SPE. Note: 2 C2 Byte Insertion Type R/W The address location of the Transmit STS-3c POH Processor block Transmit G1 Byte Value Register is 0x199F C2 Byte Insertion Type: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to use either the contents within the “Transmit STS-3c Path – Transmit C2 Byte Value” Register or the TPOH input pin as the source for the C2 byte, in the outbound STS-3c SPE data-stream, as described below. 0 – Configures the Transmit STS-3c POH Processor block to insert the contents within the “Transmit STS-3c Path – Transmit C2 Byte Value” Register into the C2 byte-position within each outbound STS-3c SPE. 1 – Configures the Transmit STS-3c POH Processor block to accept externally supplied data (via the “TPOH” input port) and to insert this data into the C2 byte position within each outbound STS-3c SPE. Note: 1 Unused R/O 0 Force Transmission of AIS-P R/W The address location of the Transmit STS-3c POH Processor block Transmit C2 Byte Value Register is 0x199B Force Transmission of AIS-P: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to (via software control) transmit the AIS-P indicator to the remote PTE. If this feature is enabled, then the Transmit STS-3c POH Processor block will automatically set the H1, H2, H3 and all the “outbound” STS-3c SPE bytes to an “All Ones” pattern, prior to routing this data to the Transmit STS-3 TOH 345 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Processor block. 0 – Configures the Transmit STS-3c POH Processor block to NOT transmit the AIS-P indicator to the remote PTE. In this case, the Transmit STS-3c POH Processor block will transmit “normal” traffic to the remote PTE. 1 – Configures the Transmit STS-3c POH Processor block to transmit the AIS-P indicator to the remote PTE. 346 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 235: Transmit STS-3c Path – Transmitter J1 Byte Value Register (Address Location= 0x1993) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_J1_Byte[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Transmit J1 Byte Value[7:0] R/W DESCRIPTION Transmit J1 Byte Value: These READ/WRITE bit-fields permit the user to have software control over the value of the J1 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the J1 byte, then it will automatically write the contents of this register into the J1 byte location, within each “outbound” STS-3c SPE. This feature is enabled whenever the user writes the value “[1, 0]” into Bits 1 and 0 (Transmit Path Trace Message Source[1:0]) within the “Transmit STS3c Path – SONET Path Trace Message Control Register” register. Note: The Address Location of the Transmit STS-3c Path – SONET J1 Byte Control Register is 0x19BB Table 236: Transmit STS-3c Path – Transmitter B3 Byte Error Mask Register (Address Location= 0x1997) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 Transmit_B3_Byte_Error_Mask[7:0] BIT NUMBER NAME TYPE 7-0 Transmit B3 Byte Error_Mask[7:0] R/W DESCRIPTION Transmit B3 Byte Error Mask[7:0]: This READ/WRITE bit-field permits the user to insert errors into the B3 byte within each “outbound” STS-3c SPE, prior to transmission to the Transmit STS-3 TOH Processor block. The Transmit STS-3c POH Processor block will perform an XOR operation with the contents of this register, and its “locally-computed” B3 byte value. The results of this operation will be written back into the B3 byte-position within each “outbound” STS-3c SPE. If the user sets a particular bit-field, within this register, to “1”, then that corresponding bit, within the “outbound” B3 byte will be in error. Note: For normal operation, the user should set this register to 0x00. 347 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 237: Transmit STS-3c Path – Transmit C2 Byte Value Register (Address Location= 0x199B) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_C2_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Transmit C2 Byte Value[7:0] R/W DESCRIPTION Transmit C2 Byte Value: These READ/WRITE bit-fields permit the user to have software control over the value of the C2 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the C2 byte, then it will automatically write the contents of this register into the C2 byte location, within each “outbound” STS-3c SPE. This feature is enabled whenever the user writes a “0” into Bit 2 (C2 Byte Insertion Type) within the “Transmit STS-3c Path – SONET Control Register – Byte 0” register. Note: The Address Location of the Transmit STS-3c Path – SONET Control Register – Byte 0” Register is 0x1983 Table 238: Transmit STS-3c Path – Transmit G1 Byte Value Register (Address Location= 0x199F) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_G1_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Transmit G1 Byte Value[7:0] R/W DESCRIPTION Transmit G1 Byte Value: These READ/WRITE bit-fields permit the user to have software control over the contents of the RDI-P and REI-P bit-fields, within each G1 byte in the “outbound” STS-3c SPE. If the users sets “REI-P_Insertion_Type[1:0]” and “RDIP_Insertion_Type[1:0]” bits to the value [0, 1], then contents of the REI-P and the RDI-P bit-fields (within each G1 byte of the “outbound” STS-3c SPE) will be dictated by the contents of this register. Note: 1. The “REI-P_Insertion_Type[1:0]” and “RDI-P_Insertion_Type[1:0]” bitfields are located in the “Transmit STS-3c Path – SONET Control Register – Byte 0” Register. 2. The Address Location of the Transmit STS-3c Path – SONET Control Register – Byte 0” Register is 0x1983 348 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 239: Transmit STS-3c Path – Transmit F2 Byte Value Register (Address Location= 0x19A3) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_F2_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Transmit F2 Byte Value[7:0] R/W DESCRIPTION Transmit F2 Byte Value: These READ/WRITE bit-fields permit the user to have software control over the value of the F2 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the F2 byte, then it will automatically write the contents of this register into the F2 byte location, within each “outbound” STS-3c SPE. This feature is enabled whenever the user writes a “0” into Bit 7 (F2 Insertion Type) within the “Transmit STS-3c Path – SONET Control Register – Byte 0” register. Note: The Address Location of the Transmit STS-3c Path – SONET Control Register is 0x1983 Table 240: Transmit STS-3c Path – Transmit H4 Byte Value Register (Address Location= 0x19A7) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_H4_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Transmit H4 Byte Value[7:0] R/W DESCRIPTION Transmit H4 Byte Value: These READ/WRITE bit-fields permit the user to have software control over the value of the H4 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the H4 byte, then it will automatically write the contents of this register into the H4 byte location, within each “outbound” STS-3c SPE. This feature is enabled whenever the user writes a “0” into Bit 0 (H4 Insertion Type) within the “Transmit STS-3c Path – SONET Control Register – Byte 1” register. Note: The Address Location for the “Transmit STS-3c Path – SONET Control Register – Byte 1” register is 0x1982 349 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 241: Transmit STS-3c Path – Transmit Z3 Byte Value Register (Address Location= 0x19AB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_Z3_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Transmit Z3 Byte Value[7:0] R/W DESCRIPTION Transmit Z3 Byte Value: These READ/WRITE bit-fields permit the user to have software control over the value of the Z3 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the Z3 byte, then it will automatically write the contents of this register into the Z3 byte location, within each “outbound” STS-3c SPE. This feature is enabled whenever the user writes a “0” into Bit 1 (Z3 Insertion Type) within the “Transmit STS-3c Path – SONET Control Register – Byte 1” register. Note: The Address Location for the “Transmit STS-3c Path – SONET Control Register – Byte 1” register is 0x1982 Table 242: Transmit STS-3c Path – Transmit Z4 Byte Value Register (Address Location= 0x19AF) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_Z4_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Transmit Z4 Byte Value[7:0] R/W DESCRIPTION Transmit Z4 Byte Value: These READ/WRITE bit-fields permit the user to have software control over the value of the Z4 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the Z4 byte, then it will automatically write the contents of this register into the Z4 byte location, within each “outbound” STS-3c SPE. This feature is enabled whenever the user writes a “0” into Bit 2 (Z4 Insertion Type) within the “Transmit STS-3c Path – SONET Control Register – Byte 0” register. Note: The Address Location of the Transmit STS-3c Path – SONET Control Register – Byte 0” Register is 0x1982 350 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 243: Transmit STS-3c Path – Transmit Z5 Byte Value Register (Address Location= 0x19B3) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit_Z5_Byte_Value[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 Transmit Z5 Byte Value[7:0] R/W DESCRIPTION Transmit Z5 Byte Value: These READ/WRITE bit-fields permit the user to have software control over the value of the Z5 byte, within each outbound STS-3c SPE. If the user configures the Transmit STS-3c POH Processor block to this register as the source of the Z5 byte, then it will automatically write the contents of this register into the Z5 byte location, within each “outbound” STS-3c SPE. This feature is enabled whenever the user writes a “0” into Bit 3 (Z5 Insertion Type) within the “Transmit STS-3c Path – SONET Control Register – Byte 0” register. Note: The Address Location of the Transmit STS-3c Path – SONET Control Register – Byte 0” register is 0x1982 351 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 244: Transmit STS-3c Path – Transmit Path Control Register (Address Location= 0x19B7) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Pointer Force Check Stuff Insert Negative Stuff Insert Positive Stuff Insert Continuous NDF Events Insert Single NDF Event R/O R/O R/W R/W W W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-6 Unused R/O 5 Pointer Force R/W DESCRIPTION Pointer Force: This READ/WRITE bit-field permits the user to load the values contained within the “Transmit STS-3c POH Arbitrary H1 Pointer Byte” and “Transmit STS-3c POH Arbitrary H2 Pointer Byte” registers into the H1 and H2 bytes (within the outbound STS-3c data stream). Note: The actual location of the SPE will NOT be adjusted, per the value of H1 and H2 bytes. Hence, this feature should cause the remote terminal to declare an “Invalid Pointer” condition. 0 – Configures the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to transmit STS-3c/STS-3 data with normal and correct H1 and H2 bytes. 1 – Configures the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to overwrite the values of the H1 and H2 bytes (in the outbound STS3c/STS-3 data-stream) with the values in the “Transmit STS-3c POH Arbitrary H1 and H2 Pointer Byte” registers. Note: 1. The Address Location of the Transmit STS-3c Arbitrary H1 Pointer Byte register is 0x19BF 2. The Address Location of the Transmit STS-3c Arbitrary H2 Pointer Byte register is 0x19C3 4 Check Stuff R/W Check Stuff Monitoring: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to only execute a “Positive”, “Negative” or “NDF” event (via the “Insert Positive Stuff”, “Insert Negative Stuff”, “Insert Continuous or Single NDF” options, via software command) if no pointer adjustment (NDF or otherwise) has occurred during the last 3 SONET frame periods. 0 – Disables this feature. In this mode, the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks will execute a “software-commanded” pointer adjustment event, independent of whether a pointer adjustment event has occurred in the last 3 SONET frame periods. 1 – Enables this feature. In this mode, the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks will ONLY execute a “software-commanded” pointer adjustment event, if no pointer adjustment event has occurred during the last 3 SONET frame periods. 3 Insert Negative Stuff R/W Insert Negative Stuff: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c 352 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 POH and Transmit STS-3 TOH Processor blocks to insert a negative-stuff into the outbound STS-3c/STS-3 data stream. This command, in-turn will cause a “Pointer Decrementing” event at the remote terminal. Writing a “0” to “1” transition into this bit-field causes the following to happen. • A negative-stuff will occur (e.g., a single payload byte will be inserted into the H3 byte position within the outbound STS-1/STS-3 data stream). • The “D” bits, within the H1 and H2 bytes will be inverted (to denote a “Decrementing” Pointer Adjustment event). • The contents of the H1 and H2 bytes will be decremented by “1”, and will be used as the new pointer from this point on. Note: 2 Insert Positive Stuff R/W Once the user writes a “1” into this bit-field, the XRT94L33 will automatically clear this bit-field. Hence, there is no need to subsequently reset this bit-field to “0”. Insert Positive Stuff: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to insert a positive-stuff into the outbound STS-3c/STS-3 data stream. This command, in-turn will cause a “Pointer Incrementing” event at the remote terminal. Writing a “0” to “1” transition into this bit-field causes the following to happen. • A positive-stuff will occur (e.g., a single stuff-byte will be inserted into the STS-3c/STS-3 data-stream, immediately after the H3 byte position within the outbound STS-3c/STS-3 data stream). • The “I” bits, within the H1 and H2 bytes will be inverted (to denote a “Incrementing” Pointer Adjustment event). • The contents of the H1 and H2 bytes will be incremented by “1”, and will be used as the new pointer from this point on. Note: 1 Insert Continuous NDF Events R/W Once the user writes a “1” into this bit-field, the XRT94L33 will automatically clear this bit-field. Hence, there is no need to subsequently reset this bit-field to “0”. Insert Continuous NDF Events: This READ/WRITE bit-field permits the user configure the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to continuously insert a New Data Flag (NDF) pointer adjustment into the outbound STS-3c/STS-3 data stream. Note: As the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks insert the NDF event into the STS-1/STS-3 data stream, it will proceed to load in the contents of the “Transmit STS-3c POH Arbitrary H1 Pointer” and “Transmit STS-3c POH Arbitrary H2 Pointer” registers into the H1 and H2 bytes (within the outbound STS-3c/STS-3 data stream). 0 – Configures the “Transmit STS-3c TOH and Transmit STS-3 POH Processor” blocks to not continuously insert NDF events into the “outbound” STS-3c/STS-3 data stream. 1- Configures the “Transmit STS-3c TOH and Transmit STS-3 POH Processor” blocks to continuously insert NDF events into the “outbound” STS3c/STS-3 data stream. 0 Insert Single NDF Event R/W Insert Single NDF Event: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH and Transmit STS-3 TOH Processor blocks to insert a New Data Flag (NDF) pointer adjustment into the outbound STS-3c/STS-3 data stream. 353 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Writing a “0” to “1” transition into this bit-field causes the following to happen. • The “N” bits, within the H1 byte will set to the value “1001” • The ten pointer-value bits (within the H1 and H2 bytes) will be set to new pointer value per the contents within the “Transmit STS-3c POH – Arbitrary H1 Pointer” and “Transmit STS-3c POH Arbitrary H2 Pointer” registers (Address Location= 0xN9BF and 0xN9C3). • Afterwards, the “N” bits will resume their normal value of “0110”; and this new pointer value will be used as the new pointer from this point on. Note: 1. Once the user writes a “1” into this bit-field, the XRT94L33 will automatically clear this bit-field. Hence, there is no need to subsequently reset this bit-field to “0”. 2. The Address Location of the Transmit STS-3c Arbitrary H1 Pointer Byte register is 0x19BF 3. The Address Location of the Transmit STS-3c Arbitrary H2 Pointer Byte register is 0x19C3 354 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 245: Transmit STS-3c Path – Transmit Path Trace Message Control Register (Address Location= 0x19BB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Transmit Path Trace Message_Length[1:0] Unused BIT 0 Transmit Path Trace Message Source[1:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–4 Unused R/O 3-2 Transmit Path Trace Message_Length[1:0] R/W 1-0 Transmit Path Trace Message Source[1:0] DESCRIPTION Transmit Path Trace Message Length[1:0]: These READ/WRITE bit-fields permit the user to specify the length of the Path Trace Message, that the Transmit STS-3c POH Processor block will repeatedly transmit to the remote PTE. The relationship between the content of these bit-fields and the corresponding Path Trace Message Length is presented below. R/W Transmit Path Trace Message Length[1:0] Resulting Path Trace Message Length (in terms of bytes) 00 1 Byte 01 16 Bytes 10/11 64 Bytes Transmit Path Trace Message Source[1:0]: These READ/WRITE bit-fields permit the user to specify the source of the “outbound” Path Trace Message that will be transported via the J1 byte channel within the outbound STS-3c data-stream, as depicted below. Transmit Path Trace Message Source[1:0] 00 Resulting Source of the Path Trace Message Fixed Value: The Transmit STS-3c POH Processor block will automatically set the J1 byte, within each outbound STS-3c SPE to the value “0x00”. 01 The Transmit Path Trace Message Buffer: The Transmit STS-3c POH Processor block will read out the contents within the Transmit Path Trace Message buffer, and will transmit this message to the remote PTE. The Transmit STS-3c POH Processor block – Transmit Path Trace Message Buffer Memory is located at Address Location 0x1D00 through 0x1D3F. 10 From the “Transmit J1 Byte Value[7:0]” Register: In this setting, the Transmit STS-3c POH Processor block will read out the contents of 355 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 the “Transmit STS-3c Path – Transmit J1 Byte Value Register, and will insert this value into the J1 byte-position within each outbound STS-3c SPE. 11 From the “TxPOH” Input pin: In this configuration setting, the Transmit STS-3c POH Processor block will externally accept the contents of the “Path Trace Message” via the “TxPOH Input Port” and it will transport this message (via the J1 bytechannel) to the remote PTE. 356 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 246: Transmit STS-3c Path – Transmit Arbitrary H1 Byte Pointer Register (Address Location= 0x19BF) BIT 7 BIT 6 R/W R/W 0 0 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 NDF Bits SS Bits BIT NUMBER NAME TYPE 7-4 NDF Bits R/W BIT 0 H1 Pointer Value DESCRIPTION NDF (New Data Flag) Bits: These READ/WRITE bit-fields permit the user provide the value that will be loaded into the “NDF” bit-field (of the H1 byte), whenever a “0 to 1” transition occurs in Bit 5 (Pointer Force) within the “Transmit STS-3c Path – Transmit Path Control” Register. Note: 3-2 SS Bits R/W The Address Location of the Transmit STS-3c Path – Transmit Path Control register is 0x19B7 SS Bits These READ/WRITE bit-fields permits the user to provide the value that will be loaded into the “SS” bit-fields (of the H1 byte) whenever a “0 to 1” transition occurs in Bit 5 (Pointer Force) within the “Transmit STS-3c Path – Transmit Path Control” Register. Note: 1. For SONET Applications, the “SS” bits have no functional value, within the H1 byte. 2. The Address Location of the Transmit STS-3c Path – Transmit Path Control register is 0x19B7 1-0 H1 Pointer Value[1:0] R/W H1 Pointer Value[1:0]: These two READ/WRITE bit-fields, along with the constants of the “Transmit STS-3c Path – Transmit Arbitrary H2 Byte Pointer” Register (Address Location= 0xN9C3) permit the user to provide the contents of the 10-bit Pointer Word. These two READ/WRITE bit-fields permit the user to define the value of the two most significant bits within the Pointer word. Whenever a “0 to 1” transition occurs in Bit 5 (Pointer Force) within the Transmit STS-3c Path – Transmit Path Control” Register, the values of these two bits will be loaded into the two most significant bits within the Pointer Word. Note: The Address Location of the Transmit STS-3c Path – Transmit Path Control register is 0x19B7 357 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 247: Transmit STS-3c Path – Transmit Arbitrary H2 Byte Pointer Register (Address Location= 0x19C3) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 H2 Pointer Value[7:0] BIT NUMBER NAME TYPE 7-0 H2 Pointer Value[7:0] R/W DESCRIPTION H2 Pointer Value[1:0]: These eight READ/WRITE bit-fields, along with the constants of bits 1 and 0 within the “Transmit STS-3c Path – Transmit Arbitrary H1 Pointer” Register permit the user to provide the contents of the 10-bit Pointer Word. These two READ/WRITE bit-fields permit the user to define the value of the eight least significant bits within the Pointer word. Whenever a “0 to 1” transition occurs in Bit 5 (Pointer Force) within the Transmit STS-3c Path – Transmit Path Control” Register, the values of these eight bits will be loaded into the H2 byte, within the outbound STS-3c/STS-3 data stream. Note: 1. The Address Location of the Transmit STS-3c Path – Transmit Arbitrary H1 Pointer” register is 0x19C3 2. The Address Location of the Transmit STS-3c Path – Transmit Path Control register is 0x19B7 Table 248: Transmit STS-3c Path – Transmit Current Pointer Byte Register – Byte 1 (Address Location= 0x19C6) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 Tx_Pointer_High[1:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 1 0 BIT NUMBER NAME TYPE 7–2 Unused R/O 1-0 Tx_Pointer_ High[1:0] R/O DESCRIPTION Transmit Pointer Word – High[1:0]: These two READ-ONLY bits, along with the contents of the “Transmit STS-3c Path – Transmit Current Pointer Byte Register – Byte 0” reflect the current value of the pointer (or offset of the STS-3c SPE within the outbound STS-3c frame). These two bits contain the two most significant bits within the “10-bit pointer” word. Note: The Address Location of the Transmit STS-3c Path – Transmit Current Pointer Byte – Byte 0 register is 0x19C7 358 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 249: Transmit STS-3c Path – Transmit Current Pointer Byte Register – Byte 0 (Address Location= 0x19C7) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 1 0 1 0 Tx_Pointer_Low[7:0] BIT NUMBER NAME TYPE 7–0 Tx_Pointer_ Low[7:0] R/O DESCRIPTION Transmit Pointer Word – Low[7:0]: These two READ-ONLY bits, along with the contents of the “Transmit STS-3c Path – Transmit Current Pointer Byte Register – Byte 1” reflect the current value of the pointer (or offset of the STS-3c SPE within the output STS-3c frame). These two bits contain the eight least significant bits within the “10-bit pointer” word. Note: The Address Location of the Transmit STS-3c Path – Transmit Current Pointer Byte – Byte 0 register is 0x19C6 359 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 250: Transmit STS-3c Path – RDI-P Control Register – Byte 2 (Address Location= 0x19C9) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 Transmit RDI-P upon PLM-P PLM-P RDI-P Code[2:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–4 Unused R/O 3-1 PLM-P RDI-P Code[2:0] R/W DESCRIPTION PLM-P (Path – Payload Mismatch) Defect – RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within each “outbound” STS-3c SPE), whenever (and for the duration that) the Receive STS3c POH Processor block detects and declares the PLM-P defect condition. Note: 0 Transmit RDI-P upon PLM-P R/W In order to enable this feature, the user must set Bit 0 (Transmit RDI-P upon PLM-P) within this register to “1”. Transmit the RDI-P Indicator upon declaration of the PLM-P defect condition: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P Code (as configured in Bits 3 through 1 – within this register) towards the remote PTE whenever (and for the duration that) the Receive STS-3c POH Processor block declares the PLM-P defect condition. 0 – Configures the Transmit STS-3c POH Processor block to NOT automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the PLM-P defect condition. 1 – Configures the Transmit STS-3c POH Processor block to automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the PLM-P defect condition. NOTE: The Transmit STS-3c POH Processor block will transmit the RDI-P indicator (in response to the Receive STS-3c POH Processor block declaring the PLM-P defect condition) by setting the RDI-P bitfields (within each outbound STS-3c SPE) to the contents within the “PLM-P RDI-P Code[2:0]” bit-fields within this register. 360 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 251: Transmit STS-3c Path – RDI-P Control Register – Byte 1 (Address Location= 0x19CA) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Transmit RDI-P upon TIM-P TIM-P RDI-P Code[2:0] BIT 2 BIT 1 UNEQ-P RDI-P Code[2:0] BIT 0 Transmit RDI-P upon UNEQ-P R/W R/W R/W R/W R/W R/W R/W R/W 1 1 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7-5 TIM-P RDI-P Code[2:0] R/W TIM-P (Path – Trace Identification Mismatch) Defect – RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within each “outbound” STS-3c SPE), whenever (and for the duration that) the Receive STS3c POH Processor block detects and declares the TIM-P defect condition. Note: 4 Transmit RDI-P upon TIM-P R/W In order to enable this feature, the user must set Bit 4 (Transmit RDI-P upon TIM-P) within this register to “1”. Transmit the RDI-P Indicator upon declaration of the TIM-P defect condition: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P Code (as configured in Bits 7 through 5 – within this register) towards the remote PTE whenever (and for the duration that) the Receive STS-3c POH Processor block declares the TIM-P defect condition. 0 – Configures the Transmit STS-3c POH Processor block to NOT automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the TIM-P defect condition. 1 – Configures the Transmit STS-3c POH Processor block to automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the TIM-P defect condition. NOTE: The Transmit STS-3c POH Processor block will transmit the RDI-P indicator (in response to the Receive STS-3c POH Processor block declaring the TIM-P defect condition) by setting the RDI-P bitfields (within each outbound STS-3c SPE) to the contents within the “TIM-P RDI-P Code[2:0]” bit-fields within this register. 3-1 UNEQ-P RDI-P Code[2:0] R/W UNEQ-P (Path – Unequipped) Defect – RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within each “outbound” STS-3c SPE), whenever (and for the duration that) the Receive STS3c POH Processor block detects and declares the UNEQ-P defect condition. Note: 0 Transmit RDI-P upon UNEQ-P R/W In order to enable this feature, the user must set Bit 0 (Transmit RDI-P upon UNEQ-P) within this register to “1”. Transmit the RDI-P indicator upon declaration of the UNEQ-P defect condition: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P 361 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Code (as configured in Bits 7 through 5 – within this register) towards the remote PTE whenever (and for the duration that) the Receive STS-3c POH Processor block declares the UNEQ-P defect condition. 0 – Configures the Transmit STS-3c POH Processor block to NOT automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the UNEQ-P defect condition. 1 – Configures the Transmit STS-3c POH Processor block to automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the UNEQ-P defect condition. NOTE: The Transmit STS-3c POH Processor block will transmit the RDI-P indicator (in response to the Receive STS-3c POH Processor block declaring the UNEQ-P defect condition) by setting the RDI-P bit-fields (within each outbound STS-3c SPE) to the contents within the “UNEQ-P RDI-P Code[2:0]” bit-fields within this register. 362 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 252: Transmit STS-3c Path – RDI-P Control Register – Byte 1 (Address Location= 0x19CB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Transmit RDI-P upon LOP-P LOP-P RDI-P Code[2:0] BIT 2 BIT 1 AIS-P RDI-P Code[2:0] BIT 0 Transmit RDI-P upon AIS-P R/W R/W R/W R/W R/W R/W R/W R/W 1 1 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-5 LOP-P RDI-P Code[2:0] R/W DESCRIPTION LOP-P (Path – Loss of Pointer) Defect – RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within each “outbound” STS-3c SPE), whenever (and for the duration that) the Receive STS3c POH Processor block detects and declares the LOP-P defect condition. Note: 4 Transmit RDI-P upon LOP-P R/W In order to enable this feature, the user must set Bit 4 (Transmit RDI-P upon LOP-P) within this register to “1”. Transmit the RDI-P Indicator upon declaration of the LOP-P defect condition: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P Code (as configured in Bits 7 through 5 – within this register) towards the remote PTE whenever (and for the duration that) the Receive STS-3c POH Processor block declares the LOP-P defect condition. 0 – Configures the Transmit STS-3c POH Processor block to NOT automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the LOP-P defect condition. 1 – Configures the Transmit STS-3c POH Processor block to automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the LOP-P defect condition. NOTE: The Transmit STS-3c POH Processor block will transmit the RDI-P indicator (in response to the Receive STS-3c POH Processor block declaring the LOP-P defect condition) by setting the RDI-P bitfields (within each outbound STS-3c SPE) to the contents within the “LOP-P RDI-P Code[2:0]” bit-fields within this register. 3-1 AIS-P RDI-P Code[2:0] R/W AIS-P (Path – AIS) Defect – RDI-P Code: These three READ/WRITE bit-fields permit the user to specify the value that the Transmit STS-3c POH Processor block will transmit, within the RDI-P bit-fields of the G1 byte (within the “outbound” STS3c SPE), whenever (and for the duration that) the Receive STS-3c POH Processor block detects and declares the AIS-P defect condition. Note: 0 Transmit RDI-P upon AIS-P R/W In order to enable this feature, the user must set Bit 0 (Transmit RDI-P upon AIS-P) within this register to “1”. Transmit the RDI-P Indicator upon declaration of the AIS-P defect condition: This READ/WRITE bit-field permits the user to configure the Transmit STS-3c POH Processor block to automatically transmit the RDI-P 363 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Code (as configured in Bits 7 through 5 – within this register) towards the remote PTE whenever (and for the duration that) the Receive STS-3c POH Processor block declares the AIS-P defect condition. 0 – Configures the Transmit STS-3c POH Processor block to NOT automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the AIS-P defect condition. 1 – Configures the Transmit STS-3c POH Processor block to automatically transmit the RDI-P indicator whenever (and for the duration that) the Receive STS-3c POH Processor block declares the AIS-P defect condition. NOTE: The Transmit STS-3c POH Processor block will transmit the RDI-P indicator (in response to the Receive STS-3c POH Processor block declaring the AIS-P defect condition) by setting the RDI-P bitfield (within each outbound STS-3c SPE) to the contents within the “AIS-P RDI-P Code[2:0]” bit-fields within this register. 364 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 253: Transmit STS-3c Path – Serial Port Control Register (Address Location= 0x19CF) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 TxPOH Clock Speed [3:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–4 Unused R/O 3–0 TxPOH Clock Speed [3:0] R/W DESCRIPTION TxPOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permit the user to specify the frequency of the “TxPOHClk output clock signal. The formula that relates the contents of these register bits to the “TxPOHClk” frequency is presented below. FREQ = 19.44/[2 * (TxPOH_CLOCK_SPEED + 1) Note: For STS-3/STM-1 applications, the frequency of the RxPOHClk output signal must be in the range of 0.304MHz to 9.72MHz 365 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1.9 Rev222...000...000 RECEIVE SONET POH PROCESSOR BLOCK The register map for the Receive SONET POH Processor Block is presented in the Table below. Additionally, a detailed description of each of the “Receive SONET POH Processor” block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the “Receive SONET POH Processor Block “highlighted” is presented below in Figure 6 Figure 6: Illustration of the Functional Block Diagram of the XRT94L33, with the Receive SONET POH Processor Block “High-lighted”. Tx TxSTS-3 STS-3 TOH TOHProcessor Processor Block Block Rx RxSTS-3 STS-3TOH TOH Processor Rx STS-3 Processor Rx STS-3TOH TOH Block Processor Block Block Processor Block (Primary) (Primary) STS-3 STS-3 Telecom TelecomBus Bus Block Block Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (Primary) (Primary) Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (APS) (APS) Tx TxSONET SONET POH POH Processor Processor Block Block Rx RxSONET SONET POH POH Processor Processor Block Block Rx RxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block Tx TxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block Rx RxSTS-1 STS-1 POH POH Block Block Rx RxSTS-1 STS-1 TOH TOH Block Block Tx TxSTS-1 STS-1 POH POH Block Block Tx TxSTS-1 STS-1 TOH TOH Block Block DS3/E3 DS3/E3 Jitter Jitter Attenuator Attenuator Block Block DS3/E3 DS3/E3 Framer Framer Block Block Channel 1 To Channels 2 – 3 From Channels 2 – 3 Clock ClockSynthesizer SynthesizerBlock Block Microprocessor MicroprocessorInterface Interface 366 JTAG JTAGTest TestPort Port XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S RECEIVE SONET POH PROCESSOR BLOCK REGISTER Table 254: Receive SONET POH Processor Block Register - Address Map ADDRESS LOCATION 0xN000 – 0xN181 REGISTER NAME DEFAULT VALUES Reserved 0x00 0xN182 Receive SONET Path – Control Register – Byte 1 0x00 0xN183 Receive SONET Path – Control Register – Byte 0 0x00 Reserved 0x00 0xN186 Receive SONET Path – Status Register – Byte 1 0x00 0xN187 Receive SONET Path – Status Register – Byte 0 0x00 0xN188 Reserved 0x00 0xN189 Receive SONET Path – Interrupt Status Register – Byte 2 0x00 0xN18A Receive SONET Path – Interrupt Status Register – Byte 1 0x00 0xN18B Receive SONET Path – Interrupt Status Register – Byte 0 0x00 0xN18C Reserved 0x00 0xN18D Receive SONET Path – Interrupt Enable Register – Byte 2 0x00 0xN18E Receive SONET Path – Interrupt Enable Register – Byte 1 0x00 0xN18F Receive SONET Path – Interrupt Enable Register – Byte 0 0x00 Reserved 0x00 Receive SONET Path – SONET Receive RDI-P Register 0x00 Reserved 0x00 0xN196 Receive SONET Path – Received Path Label Byte (C2) Register 0x00 0xN197 Receive SONET Path – Expected Path Label Byte (C2) Register 0x00 0xN198 Receive SONET Path – B3 Byte Error Count Register – Byte 3 0x00 0xN199 Receive SONET Path – B3 Byte Error Count Register – Byte 2 0x00 0xN19A Receive SONET Path – B3 Byte Error Count Register – Byte 1 0x00 0xN19B Receive SONET Path – B3 Byte Error Count Register – Byte 0 0x00 0xN19C Receive SONET Path – REI-P Event Count Register – Byte 3 0x00 0xN19D Receive SONET Path – REI-P Event Count Register – Byte 2 0x00 0xN19E Receive SONET Path – REI-P Event Count Register – Byte 1 0x00 0xN19F Receive SONET Path – REI-P Event Count Register – Byte 0 0x00 Reserved 0x00 Receive SONET Path – Receiver J1 Byte Control Register 0x00 0xN184, 0xN185 0xN190 – 0xN192 0xN193 0xN194, 0xN195 0xN1A0 – 0xN1A2 0xN1A3 0xN1A4, 0xN1A5 0xN1A6 Reserved Receive SONET Path – Pointer Value Register– Byte 1 367 0x00 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM ADDRESS LOCATION 0xN1A7 0xN1A8 – 0xN1BA 0xN1BB 0xN1BC – 0xN1BE 0xN1BF 0xN1C0 – 0xN1C2 0xN1C3 0xN1C4 – 0xN1D2 0xN1D3 0xN1D4 – 0xN1D6 0xN1D7 0xN1D8 – 0xN1DA 0xN1DB 0xN1DC – 0xN1DE 0xN1DF 0xN1E0 – 0xN1E2 0xN1E3 0xN1E4 – 0xN1E6 0xN1E7 0xN1E8 – 0xN1EA 0xN1EB 0xN1EC – 0xN1EE 0xN1EF 0xN1F0 – 0xN1F2 0xN1F3 0xN1F4 – 0xN1FF REGISTER NAME Rev222...000...000 DEFAULT VALUES Receive SONET Path – Pointer Value Register – Byte 0 0x00 Reserved 0x00 Receive SONET Path – AUTO AIS Control Register 0x00 Reserved 0x00 Receive SONET Path – Serial Port Control Register 0x00 Reserved 0x00 Receive SONET Path – SONET Receive Auto Alarm Register – Byte 0 0x00 Reserved 0x00 Receive SONET Path – Receive J1 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive B3 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive C2 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive G1 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive F2 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive H4 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive Z3 Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive Z4 (K3) Byte Capture Register 0x00 Reserved 0x00 Receive SONET Path – Receive Z5 Byte Capture Register 0x00 Reserved 0x00 368 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.9.1 RECEIVE SONET POH PROCESSOR BLOCK REGISTER DESCRIPTION Table 255: Receive SONET Path – Control Register – Byte 1 (Address Location= 0xN182, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Unused BIT 0 DS3 AIS upon Async PDI-P or AIS-P R/O R/O R/O R/O R/O R/O R/O R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–1 Unused R/O 0 DS3 AIS upon Async PDI-P or AIS-P R/W DESCRIPTION DS3 AIS upon Async PDI-P or AIS-P: This READ/WRITE bit-field permits the user to configure the Receive SONET POH Processor block to automatically command the DS3/E3 Framer Block to transmit the DS3 AIS indicator (to downstream circuitry) whenever (and for the duration that) it (the Receive SONET POH Processor block) declares the Async PDI-P or AIS-P defect condition within the incoming STS-1 SPE data-stream. 0 – Configures the Receive SONET POH Processor block to NOT automatically command the DS3/E3 Framer block to automatically transmit the DS3 AIS indicator (via the Egress Direction) upon declaration of either the AIS-P or the Async PDI-P defect conditions. 1 – Configures the Receive SONET POH Processor block to automatically command the DS3/E3 Framer block to automatically transmit the DS3 AIS indicator whenever (and for the duration that) it declares either the AIS-P or the PDI-P defect condition. Note: Note: This register bit is only valid if the incoming STS-1 signal is transporting an asynchronous DS3 signal; and if the corresponding channel (on the “Low-Speed” Side of the chip) is configured to operate in the DS3 Mode. Whenever an STS-1 signal is transporting an asynchronously-mapped DS3 signal, then a given PTE will recognize and declare the PDI-P defect condition whenever it “accepts” the C2 byte to the value “0xFC”. 369 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 256: Receive SONET Path – Control Register – Byte 0 (Address Location= 0xN183, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 Check Stuff RDI-P Type REI-P Error Type B3 Error Type R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–4 Unused R/O 3 Check Stuff R/W DESCRIPTION Check (Pointer Adjustment) Stuff Select: This READ/WRITE bit-field permits the user to enable/disable the SONET standard recommendation that a pointer increment or decrement operation, detected within 3 SONET frames of a previous pointer adjustment operation (e.g., negative stuff, positive stuff) is ignored. 0 – Disables this SONET standard implementation. In this mode, all pointeradjustment operations that are detected will be accepted. 1 – Enables this “SONET standard” implementation. In this mode, all pointer-adjustment operations that are detected within 3 SONET frame periods of a previous pointer-adjustment operation, will be ignored. 2 RDI-P Type R/W Path – Remote Defect Indicator Type Select: This READ/WRITE bit-field permits the user to configure the Receive SONET POH Processor block to support either the “Single-Bit” or the “Enhanced” RDI-P form of signaling, as described below. 0 – Configures the Receive SONET POH Processor block to support the Single-Bit RDI-P. In this mode, the Receive SONET POH Processor block will only monitor Bit 5, within the G1 byte (of incoming SPE data), in order to declare and clear the RDI-P defect condition. 1 – Configures the Receive SONET POH Processor block to support the Enhanced RDI-P (ERDI-P). In this mode, the Receive SONET POH Processor block will monitor bits 5, 6 and 7, within the G1 byte, in order to declare and clear the RDI-P defect condition. 1 REI-P Error Type R/W REI-P Error Type: This READ/WRITE bit-field permits the user to specify how the “Receive SONET POH Processor block will count (or tally) REI-P events, for Performance Monitoring purposes. The user can configure the Receive SONET POH Processor block to increment REI-P events on either a “per-bit” or “per-frame” basis. If the user configures the Receive SONET POH Processor block to increment REI-P events on a “per-bit” basis, then it will increment the “Receive SONET Path REI-P Event Count” register by the value of the lower nibble within the G1 byte of the incoming STS-1 datastream. If the user configures the Receive SONET POH Processor block to increment REI-P events on a “per-frame” basis, then it will increment the “Receive SONET Path REI-P Event Count” Register each time it receives an STS-1 frame, in which the lower nibble of the G1 byte (bits 1 through 4) are set to a “non-zero” value. 0 – Configures the Receive SONET POH Processor block to count or tally REI-P events on a per-bit basis. 1 – Configures the Receive SONET POH Processor block to count or tally 370 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 REI-P events on a per-bit basis. 0 B3 Error Type R/W B3 Error Type: This READ/WRITE bit-field permits the user to specify how the “Receive SONET POH Processor block will count (or tally) B3 byte errors, for Performance Monitoring purposes. The user can configure the Receive SONET POH Processor block to increment B3 byte errors on either a “perbit” or “per-frame” basis. If the user configures the Receive SONET POH Processor block to increment B3 byte errors on a “per-bit” basis, then it will increment the “Receive SONET Path B3 Byte Error Count” register by the number of bits (within the B3 byte value of the incoming STS-1 data-stream) that is in error. If the user configures the Receive SONET POH Processor block to increment B3 byte errors on a “per-frame” basis, then it will increment the “Receive SONET Path – B3 Byte Error Count” register each time it receives an STS-1 SPE that contains an erred B3 byte. 0 – Configures the Receive SONET POH Processor block to count B3 byte errors on a “per-bit” basis. 1 – Configures the Receive SONET POH Processor block to count B3 byte errors on a “per-frame” basis. 371 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 257: Receive SONET Path – Control Register – Byte 0 (Address Location= 0xN186, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 DS3 Async PDI-P Defect Declared Path Trace Message Unstable Defect Declared R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–2 Unused R/O 1 DS3 Async PDI-P Defect Declared R/O DESCRIPTION Asynchronously-Mapped DS3 PDI-P (Payload Defect Indicator) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the “Asynchronous DS3 PDI-P defect condition. The Receive SONET POH Processor will declare the “Asynchronous DS3 PDI-P” defect condition for the duration that it has “accepted” the C2 byte value of “0xFC”. 0 – Indicates that the Receive SONET POH Processor block is NOT currently declaring the “Asynchronous DS3 PDI-P” defect condition. 1 – Indicates that the Receive SONET POH Processor block is currently declaring the “Asynchronous DS3 PDI-P” defect condition. Notes: This register bit is only valid if the incoming STS-1 signal is transporting an asynchronously-mapped DS3 signal; and if the corresponding channel (on the “low-speed” side of the chip) is configured to operate in the DS3 Mode. 0 Path Trace Message Unstable Defect Declared R/O Path Trace Message Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the Path Trace Message Unstable defect condition. The Receive SONET POH Processor block will declare the Path Trace Message Unstable defect condition, whenever the “Path Trace Message Unstable” counter reaches the value “8”. The Receive SONET POH Processor block will increment the “Path Trace Message Unstable“ counter each time that it receives a Path Trace message that differs from the previously received message. The Receive SONET POH Processor block will clear the “Path Trace Message Unstable” counter whenever it has received a given Path Trace Message 3 (or 5) consecutive times. 0 – Indicates that the Receive SONET POH Processor block is NOT currently declaring the “Path Trace Message Unstable” defect condition. 1 – Indicates that the Receive SONET POH Processor block is currently declaring the Path Trace Message Unstable defect condition. 372 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 258: Receive SONET Path – SONET Receive POH Status – Byte 0 (Address Location= 0xN187, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TIM-P Defect Declared C2 Byte Unstable Defect Declared UNEQ-P Defect Declared PLM-P Defect Declared RDI-P Defect Declared RDI-P Unstable Condition LOP-P Defect Declared AIS-P Defect Declared R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 TIM-P Defect Declared R/O DESCRIPTION Trace Identification Mismatch (TIM-P) Defect Indicator: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the “Path Trace Identification Mismatch” (TIM-P) defect condition. The Receive SONET POH Processor block will declare the “TIM-P” defect condition, when none of the Path Trace Message bytes within the most recently Path Trace Message (received via the incoming STS-1 data-stream) matches the contents of the “expected” Path Trace message. The Receive SONET POH Processor block will clear the “TIM-P” defect condition, when at least 80% of the received Path Trace Message bytes (within the most recently received Path Trace Message) matches the contents of the “expected” Path Trace message. 0 – Indicates that the Receive SONET POH Processor block is NOT currently declaring the TIM-P defect condition. 1 – Indicates that the Receive SONET POH Processor block is currently declaring the TIM-P defect condition. 6 C2 Byte Unstable Defect Declared R/O C2 Byte (Path Signal Label Byte) Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the “C2 Byte Unstable” defect condition. The Receive SONET POH Processor block will declare the “C2 Byte Unstable” defect condition, whenever the “C2 Byte Unstable” counter reaches the value of “5”. The Receive SONET POH Processor block will increment the “C2 Unstable” counter each time that it receives an SPE with a C2 byte value that differs from the previously received C2 byte value. The Receive SONET POH Processor block will clear the contents of the “C2 Unstable” counter to “0” whenever it has received 3 (or 5) consecutive SPEs of the same C2 byte value. 0 – Indicates that the Receive SONET POH Processor block is NOT currently declaring the C2 (Path Signal Label Byte) Unstable defect condition is NOT declared. 1 – Indicates that the Receive SONET POH Processor block is currently declaring the C2 (Path Signal Label Byte) Unstable defect condition. 5 UNEQ-P Defect Declared R/O Path – Unequipped (UNEQ-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the UNEQ-P defect condition. The Receive SONET POH Processor block will declare the UNEQ-P defect condition, anytime that it, unexpectedly receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set to the value “0x00” (which indicates that the SPE is “Unequipped”). The Receive SONET POH Processor block will clear the UNEQ-P defect 373 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 condition, if it receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set to a value other than 0x00. 0 – Indicates that the Receive SONET POH Processor block is NOT declaring the UNEQ-P defect condition. 1 – Indicates that the Receive SONET POH Processor block is currently declaring the UNEQ-P defect condition. Note: 4 PLM-P Defect Declared R/O The Receive SONET POH Processor block will not declare the UNEQP defect condition if it configured to expect to receive SONET frames with C2 bytes being set to “0x00” (e.g., if the “Receive SONET Path – Expected Path Label Value” Register –Address Location= 0xN197) is set to “0x00”. Path Payload Mismatch (PLM-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the PLM-P defect condition. The Receive SONET POH Processor block will declare the PLM-P defect condition, if it receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set to a value other than that which it is expecting to receive. Whenever the Receive SONET POH Processor block is checking in order to determine whether or not it should declare the PLM-P defect, it will check the contents of the following two registers. • The “Receive SONET Path – Received Path Label Value” Register (Address Location= 0xN196). • The “Receive SONET Path – Expected Path Label Value” Register (Address Location= 0xN197). The “Receive SONET Path – Expected Path Label Value” Register contains the value of the C2 bytes, that the Receive SONET POH Processor blocks expects to receive. The “Receive SONET Path – Received Path Label Value” Register contains the value of the C2 byte, that the Receive SONET POH Processor block has most recently “accepted” or “validated” (by receiving this same C2 byte in five consecutive SONET frames). The Receive SONET POH Processor block will declare a PLM-P defect condition; if the contents of these two register do not match. The Receive SONET POH Processor block will clear the PLM-P defect condition if whenever the contents of these two registers do match. 0 – Indicates that the Receive SONET POH Processor block is NOT currently declaring the PLM-P defect condition. 1 – Indicates that the Receive SONET POH Processor block is currently declaring the PLM-P defect condition. NOTES: 3 RDI-P Defect Declared R/O 1. The Receive SONET POH Processor block will clear the PLM-P defect condition, upon declaring the UNEQ-P defect condition. 2. If the Receive SONET POH Processor block unexpectedly accepts the C2 byte value of “0x00”, then it will NOT declare the PLM-P defect condition. In this case, the Receive SONET POH Processor block will declare the UNEQ-P defect condition Path Remote Defect Indicator (RDI-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the RDI-P defect condition. If the Receive SONET POH Processor block is configured to support the “Single-bit RDI-P” function, then it will declare the RDI-P defect condition if Bit 5 374 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 (within the G1 byte of the incoming STS-1 frame) is set to “1” for “RDI-P_THRD” number of incoming consecutive STS-1 SPEs. If the Receive SONET POH Processor block is configured to support the Enhanced RDI-P” (ERDI-P) function, then it will declare the RDI-P defect condition if Bits 5, 6 and 7 (within the G1 byte of the incoming STS-1 frame) are set to either [0, 1, 0], [1, 0, 1] or [1, 1, 0] for “RDI-P_THRD” number of consecutive STS-1 frames. 0 – Indicates that the Receive SONET POH Processor block is NOT declaring the RDI-P defect condition. 1 – Indicates that the Receive SONET POH Processor block is currently declaring the RDI-P defect condition. Note: 2 RDI-P Unstable Defect Declared R/O The user can specify the value for “RDI-P_THRD” by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the “Receive SONET Path – SONET Receive RDI-P Register (Address Location= 0xN193). RDI-P (Path – Remote Defect Indicator) Unstable Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the “RDI-P Unstable” defect condition. The Receive SONET POH Processor block will declare the “RDI-P Unstable” defect condition whenever the “RDI-P Unstable Counter” reaches the value “RDI-P THRD”. The Receive SONET POH Processor block will increment the “RDI-P Unstable” counter each time that it receives an RDI-P value that differs from that of the previous STS-1 frame. The Receive SONET POH Processor block will clear the “RDI-P Unstable” counter to “0” whenever it has received the same RDI-P value is received in “RDI-P_THRD” consecutive STS-1 frames. 0 – Indicates that the Receive SONET POH Processor block is NOT currently declaring the RDI-P Unstable defect condition. 1 – Indicates that the Receive SONET POH Processor block is currently declaring the RDI-P Unstable defect condition. Note: 1 LOP-P Defect Declared R/O The user can specify the value for “RDI-P_THRD” by writing the appropriate data into Bits 3 through 0 (RDI-P THRD) within the “Receive SONET Path – SONET Receive RDI-P Register (Address Location= 0xN193). Loss of PointerDefect Indicator (LOP-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the LOP-P (Loss of Pointer) defect condition. The Receive SONET POH Processor block will declare the LOP-P defect condition, if it cannot detect a valid pointer (H1 and H2 bytes, within the TOH) within 8 to 10 consecutive SONET frames. Further, the Receive SONET POH Processor block will declare the LOP-P defect condition, if it detects 8 to 10 consecutive NDF events. The Receive SONET POH Processor block will clear the LOP-P defect condition, whenever it detects valid pointer bytes (e.g., the H1 and H2 bytes, within the TOH) and normal NDF value for three consecutive incoming SONET frames. 0 – Indicates that the Receive SONET POH Processor block is NOT currently declaring the LOP-P defect condition. 1 – Indicates that the Receive SONET POH Processor block is currently declaring the LOP-P defect condition. 0 AIS-P Defect Declared R/O Path AIS (AIS-P) Defect Declared: This READ-ONLY bit-field indicates whether or not the Receive SONET POH Processor block is currently declaring the AIS-P defect condition. The Receive 375 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 SONET POH Processor block will declare the AIS-P defect condition if it detects all of the following conditions within three consecutive incoming STS-1 frames. • The H1, H2 and H3 bytes are set to an “All Ones” pattern. • The entire SPE is set to an “All Ones” pattern. The Receive SONET POH Processor block will clear the AIS-P defect condition whenever it detects a valid STS-1 pointer (H1 and H2 bytes) and a “set” of “normal” NDF for three consecutive STS-1 frames. 0 – Indicates that the Receive SONET POH Processor block is NOT currently declaring the AIS-P defect condition. 1 – Indicates that the Receive SONET POH Processor block s currently declaring the AIS-P defect condition. Note: The Receive SONET POH Processor block will NOT declare the LOPP defect condition if it detects an “All Ones” pattern in the H1, H2 and H3 bytes. It will, instead, declare the AIS-P defect condition. 376 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 259: Receive SONET Path – SONET Receive Path Interrupt Status – Byte 2 (Address Location= 0xN189, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 Change in PDI-P Defect Condition Interrupt Status BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Detection of AIS Pointer Interrupt Status Detection of Pointer Change Interrupt Status POH Capture Interrupt Status Change in TIM-P Defect Condition Interrupt Status Change in Path Trace Message Unstable Defect Condition Interrupt Status RUR R/O R/O RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Change in PDI-P Defect Condition Interrupt Status: RUR DESCRIPTION Change in PDI-P Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in PDI-P Defect Condition” Interrupt condition has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive SONET POH Processor block declares the DS3 Asynchronous PDI-P Defect Condition (e.g., whenever the Receive SONET POH Processor block accepts” a C2 byte value of “0xFC”). • Whenever the Receive SONET POH Processor block clears the DS3 Asynchronous PDI-P Defect Condition (e.g., whenever the Receive SONET POH Processor block has “removed” the C2 byte value of “0xFC” by accepting a different C2 byte value). 0 – Indicates that the “Change in PDI-P Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in PDI-P Defect Condition” Interrupt has occurred since the last read of this register. NOTES: 1. This register bit is only valid if the incoming STS-1 signal is transporting an asynchronous DS3 signal; and if the corresponding channel (on the “low-speed” side of the XRT94L33 device) is configured to operate in the DS3 Mode. 2. The user can determine whether or not the Receive SONET POH Processor block is currently declaring the PDI-P defect condition by reading out the state of Bit 1 (DS3 Asynch PDI-P Defect Declared) within the “Receive SONET Path – Control Register – Byte 0” (Address = 0xN186). 6-5 Unused R/O 4 Detection of AIS Pointer Interrupt Status RUR Detection of AIS Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of AIS Pointer” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate this interrupt anytime it detects an “AIS Pointer” in the 377 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 incoming STS-1 data stream. Note: An “AIS Pointer” is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an “All Ones” pattern. 0 – Indicates that the “Detection of AIS Pointer” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of AIS Pointer” interrupt has occurred since the last read of this register. 3 Detection of Pointer Change Interrupt Status RUR Detection of Pointer Change Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Pointer Change” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it accepts a new pointer value (e.g., H1 and H2 bytes, in the TOH bytes). 0 – Indicates that the “Detection of Pointer Change” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of Pointer Change” Interrupt has occurred since the last read of this register. 2 POH Capture Interrupt Status RUR Path Overhead Data Capture Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “POH Capture” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt once the Z5 byte (e.g., the last POH byte) has been loaded into the POH Capture Buffer. The contents of the POH Capture Buffer will remain intact for one SONET frame period. Afterwards, the POH data, for the next SPE will be loaded into the “POH Capture” buffer. 0 – Indicates that the “POH Capture” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “POH Capture” Interrupt has occurred since the last read of this register. Note: 1 Change in TIM-P Defect Condition Interrupt Status RUR The user can obtain the contents of the POH, within the most recently received SPE by reading out the contents of address locations “0xN0D3” through “0xN0F3”). Change in TIM-P (Trace Identification Mismatch) Defect Condition Interrupt. This RESET-upon-READ bit-field indicates whether or not the “Change in TIM-P” Defect Condition interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declares the TIMP defect condition. • Whenever the Receive SONET POH Processor block clears the TIM-P defect condition. 0 – Indicates that the “Change in TIM-P Defect Condition” Interrupt has not occurred since the last read of this register. 1 – Indicates that the “Change in TIM-P Defect Condition” Interrupt has occurred since the last read of this register. 378 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S NOTE: The user can determine whether or not the Receive SONET POH Processor block is currently declaring the TIM-P defect condition by reading out the state of Bit 7 (TIM-P Defect Declared) within the “Receive SONET Path – Receive SONET POH Status Register – Byte 0 (Address = 0xN187). 0 Change in Path Trace Message Unstable Defect Condition Interrupt Status RUR Change in Path Trace Identification Message Unstable Defect Condition” Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in Path Trace Identification Message Unstable Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declare the “Path Trace Message Unstable” Defect Condition. • Whenever the Receive SONET POH Processor block clears the “Path Trace Message Unstable” Defect condition. 0 – Indicates that the “Change in Path Trace Message Unstable Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in Path Trace Message Unstable Defect Condition” Interrupt has occurred since the last read of this register. 379 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 260: Receive SONET Path – SONET Receive Path Interrupt Status – Byte 1 (Address Location= 0xN18A, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 New Path Trace Message Interrupt Status Detection of REI-P Event Interrupt Status Change in UNEQ-P Defect Condition Interrupt Status Change in PLM-P Defect Condition Interrupt Status New C2 Byte Interrupt Status Change in C2 Byte Unstable Defect Condition Interrupt Status Change in RDI-P Unstable Defect Condition Interrupt Status New RDI-P Value Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 New Path Trace Message Interrupt Status RUR DESCRIPTION New Path Trace Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New Path Trace Message” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it has accepted (or validated) and new Path Trace Message. 0 – Indicates that the “New Path Trace Message” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New Path Trace Message” Interrupt has occurred since the last read of this register. 6 Detection of REIP Event Interrupt Status RUR Detection of REI-P Event Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of REI-P Event” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it detects an REI-P event within the incoming STS-1 data-stream. 0 – Indicates that the “Detection of REI-P Event” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of REI-P Event” Interrupt has occurred since the last read of this register. 5 Change in UNEQ-P Defect Condition Interrupt Status RUR Change in UNEQ-P (Path – Unequipped) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in UNEQ-P Defect Condition” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive SONET POH Processor block declares the UNEQ-P Defect Condition. • Whenever the Receive SONET POH Processor block clears the UNEQ-P Defect Condition. 0 – Indicates that the “Change in UNEQ-P Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in UNEQ-P Defect Condition” Interrupt has 380 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 occurred since the last read of this register. Note: 4 Change in PLMP Defect Condition Interrupt Status RUR The user can determine if the Receive SONET POH Processor block is currently declaring the UNEQ-P defect condition by reading out the state of Bit 5 (UNEQ-P Defect Declared) within the “Receive SONET Path – SONET Receive POH Status – Byte 0” Register (Address Location= 0xN187). Change in PLM-P (Path – Payload Mismatch) Defect Condition Interrupt Status: This RESET-upon-READ bit indicates whether or not the “Change in PLM-P Defect Condition” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive SONET POH Processor block declares the “PLMP” Defect Condition. • Whenever the Receive SONET POH Processor block clears the “PLM-P” Defect Condition. 0 – Indicates that the “Change in PLM-P Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in PLM-P Defect Condition” Interrupt has occurred since the last read of this register. NOTE: The user can determine if the Receive SONET POH Processor block is currently declaring the PLM-P defect condition by reading out the state of Bit 4 (PLM-P Defect Declared) within the “Receive SONET Path – SONET Receive POH Status – Byte 0” Register (Address Location = 0xN187). 3 New C2 Byte Interrupt Status RUR New C2 Byte Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New C2 Byte” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 – Indicates that the “New C2 Byte” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New C2 Byte” Interrupt has occurred since the last read of this register. NOTE: Once the Receive SONET POH Processor block has “accepted” a new C2 byte value, it will load the value of this byte into the “Receive SONET Path – Receive Path Label Value” Register (Address = 0xN196). 2 Change in C2 Byte Unstable Defect Condition Interrupt Status RUR Change in C2 Byte Unstable Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in C2 Byte Unstable Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declares the “C2 Byte Unstable” defect condition. • Whenever the Receive SONET POH Processor block clears the “C2 Byte Unstable” defect condition. 0 – Indicates that the “Change in C2 Byte Unstable Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in C2 Byte Unstable Defect Condition” 381 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Interrupt has occurred since the last read of this register. Note: 1 Change in RDI-P Unstable Defect Condition Interrupt Status RUR The user can determine whether or not the Receive SONET POH Processor block is currently declaring the “C2 Byte Unstable Defect Condition” by reading out the state of Bit 6 (C2 Byte Unstable Defect Declared) within the “Receive SONET Path – SONET Receive POH Status – Byte 0” Register (Address Location= 0xN187). Change in RDI-P Unstable Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in RDI-P Unstable Defect Condition” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive SONET POH Processor block declares the “RDI-P Unstable” defect condition. • When the Receive SONET POH Processor block clears the “RDI-P Unstable” defect condition. 0 – Indicates that the “Change in RDI-P Unstable Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in RDI-P Unstable Defect Condition” Interrupt has occurred since the last read of this register. Note: 0 New RDI-P Value Interrupt Status RUR The user can determine whether or not the Receive SONET POH Processor block is currnelty declaring the “RDI-P Unstable Defect Condition” by reading out the state of Bit 2 (RDI-P Unstable Defect Condition) within the “Receive SONET Path – SONET Receive POH Status – Byte 0” Register (Address Location= 0xN187). New RDI-P Value Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “New RDI-P Value” interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate this interrupt anytime it receives and “validates” a new RDI-P value. 0 – Indicates that the “New RDI-P Value” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “New RDI-P Value” Interrupt has occurred since the last read of this register. Note: The user can obtain the “New RDI-P Value” by reading out the contents of the “RDI-P ACCEPT[2:0]” bit-fields. These bit-fields are located in Bits 6 through 4, within the “Receive SONET Path – SONET Receive RDI-P Register” (Address Location=0xN193). 382 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 261: Receive SONET Path – SONET Receive Path Interrupt Status – Byte 0 (Address Location= 0xN18B, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Detection of B3 Byte Error Interrupt Status Detection of New Pointer Interrupt Status Detection of Unknown Pointer Interrupt Status Detection of Pointer Decrement Interrupt Status Detection of Pointer Increment Interrupt Status Detection of NDF Pointer Interrupt Status Change of LOP-P Defect Condition Interrupt Status Change of AIS-P Defect Condition Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Detection of B3 Byte Error Interrupt Status RUR DESCRIPTION Detection of B3 Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of B3 Byte Error” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it detects a B3 byte error in the incoming STS-1 data stream. 0 – Indicates that the “Detection of B3 Byte Error” Interrupt has NOT occurred since the last read of this interrupt. 1 – Indicates that the “Detection of B3 Byte Error” Interrupt has occurred since the last read of this interrupt. 6 Detection of New Pointer Interrupt Status RUR Detection of New Pointer Interrupt Status: This RESET-upon-READ indicates whether the “Detection of New Pointer” interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-1 frame. Note: Pointer Adjustments with NDF will not generate this interrupt. 0 – Indicates that the “Detection of New Pointer” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of New Pointer” Interrupt has occurred since the last read of this register. 5 Detection of Unknown Pointer Interrupt Status RUR Detection of Unknown Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Unknown Pointer” interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime that it detects a “pointer” that does not fit into any of the following categories. • An Increment Pointer • A Decrement Pointer • An NDF Pointer • An AIS (e.g., All Ones) Pointer • New Pointer 0 – Indicates that the “Detection of Unknown Pointer” interrupt has NOT 383 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 occurred since the last read of this register. 1 – Indicates that the “Detection of Unknown Pointer” interrupt has occurred since the last read of this register. 4 Detection of Pointer Decrement Interrupt Status RUR Detection of Pointer Decrement Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Pointer Decrement” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it detects a “Pointer Decrement” event. 0 – Indicates that the “Detection of Pointer Decrement” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of Pointer Decrement” interrupt has occurred since the last read of this register. 3 Detection of Pointer Increment Interrupt Status RUR Detection of Pointer Increment Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Pointer Increment” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it detects a “Pointer Increment” event. 0 – Indicates that the “Detection of Pointer Increment” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of Pointer Increment” interrupt has occurred since the last read of this register. 2 Detection of NDF Pointer Interrupt Status RUR Detection of NDF Pointer Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of NDF Pointer” interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 – Indicates that the “Detection of NDF Pointer” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of NDF Pointer” interrupt has occurred since the last read of this register. 1 Change of LOPP Defect Condition Interrupt Status RUR Change of LOP-P Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in LOP-P Defect Condition” interrupt has occurred since the last read of this register. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declares the LOP-P defect condition. • Whenever the Receive “SONET POH Processor” block clears the LOP-P defect condition. 0 – Indicates that the “Change in LOP-P Defect Condition” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in LOP-P Defect Condition” interrupt has occurred since the last read of this register. Note: The user can determine if the Receive SONET POH Processor block is currently declaring the LOP-P defect condition by reading out the state of Bit 1 (LOP-P Defect Declared) within the “Receive 384 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S SONET Path – SONET Receive POH Status – Byte 0” Register (Address Location= 0xN187). 0 Change of AIS-P Defect Condition Interrupt Status RUR Change of AIS-P Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of AIS-P Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declares the AIS-P defect condition. • Whenever the Receive SONET POH Processor block clears the AIS-P defect condition. 0 – Indicates that the “Change of AIS-P Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of AIS-P Defect Condition” Interrupt has occurred since the last read of this register. Note: The user can determine if the Receive SONET POH Processor block is currently declaring the AIS-P defect condition by reading out the state of Bit 0 (AIS-P Defect Declared) within the “Receive SONET Path – SONET Receive POH Status – Byte 0” Register (Address Location= 0xN187). 385 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 262: Receive SONET Path – SONET Receive Path Interrupt Enable – Byte 2 (Address Location= 0xN18D, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 Change in PDI-P Defect Condition Interrupt Enable BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Detection of AIS Pointer Interrupt Enable Detection of Pointer Change Interrupt Enable POH Capture Interrupt Enable Change in TIM-P Defect Condition Interrupt Enable Change in Path Trace Message Unstable Defect Condition Interrupt Enable R/W R/O R/O R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Change in PDI-P Defect Condition Interrupt Enable R/W DESCRIPTION Change in PDI-P Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in PDI-P Defect Condition” Interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive SONET POH Processor block declares the DS3 Asynchronous PDI-P defect condition (e.g, whenever it accepts a C2 byte value of “0xFC”). • Whenever the Receive SONET POH Processor block clears the DS3 Asychronous PDI-P defect condition (e.g., whenever it has “removed” the C2 byte value of “0xFC” by accepting a different C2 byte value). 0 – Disables the “Change in PDI-P Defect Condition” Interrupt. 1 – Enables the “Change in PDI-P Defect Condition” Interrupt. NOTES: 6-5 Unused R/O 4 Detection of AIS Pointer Interrupt Enable R/W 1. This register bit is only valid if the incoming STS-1 signal is transporting an asynchronously-mapped DS3 signal; and if the corresponding channel (on the “low-speed” side of the XRT94L33 device) is configured to operate in the DS3 Mode. 2. The user can determine whether or not the Receive SONET POH Processor block is currently declaring the PDI-P defect condition by reading out the state of Bit 1 (DS3 Async PDI-P Defect Declared) within the Receive SONET Path – Control Register – Byte 0 (Address = 0xN186). Detection of AIS Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of AIS Pointer” interrupt. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime it detects an “AIS Pointer”, in the incoming STS-1 data stream. Note: An “AIS Pointer” is defined as a condition in which both the H1 and H2 bytes (within the TOH) are each set to an “All Ones” Pattern. 0 – Disables the “Detection of AIS Pointer” Interrupt. 386 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S 1 – Enables the “Detection of AIS Pointer” Interrupt. 3 Detection of Pointer Change Interrupt Enable R/W Detection of Pointer Change Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of Pointer Change” Interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it has accepted a new pointer value. 0 – Disables the “Detection of Pointer Change” Interrupt. 1 – Enables the “Detection of Pointer Change” Interrupt. 2 POH Capture Interrupt Enable R/W Path Overhead Data Capture Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “POH Capture” Interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt once the Z5 byte (e.g., the last POH byte) has been loaded into the POH Capture Buffer. The contents of the POH Capture Buffer will remain intact for one SONET frame period. Afterwards, the POH data for the next SPE will be loaded into the “POH Capture” Buffer. 0 – Disables the “POH Capture” Interrupt 1 – Enables the “POH Capture” Interrupt. 1 Change in TIM-P Defect Condition Interrupt Enable R/W Change in TIM-P (Trace Identification Mismatch) Defect Condition Interrupt: This READ/WRITE bit-field permits the user to either enable or disable the “Change in TIM-P Defect Condition” interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declares the TIMP defect condition. • Whenever the Receive SONET POH Processor block clears the TIM-P defect condition. 0 – Disables the “Change in TIM-P Defect Condition” Interrupt. 1 – Enables the “Change in TIM-P Defect Condition” Interrupt. NOTE: The user can determine whether or not the Receive SONET POH Processor block is currently declaring the TIM-P defect condition by reading out the state of Bit 7 (TIM-P Defect Declared) within the “Receive SONET Path – Receive SONET POH Status Register – Byte 0 (Address = 0xN187). 0 Change in Path Trace Message Unstable Condition Interrupt Enable R/W Change in “Path Trace Message Unstable Defect Condition” Interrupt Status: This READ/WRITE bit-field permits the user to either enable or disable the “Change in Path Trace Message Unstable Defect Condition” Interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declares the “Path Trace Message Unstable” defect Condition. • Whenever the Receive SONET POH Processor block clears the “Path Trace Message Unstable” defect Condition. 0 – Disables the “Change in Path Trace Message Unstable Defect Condition” interrupt. 387 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 1 – Enables the “Change in Path Trace Message Unstable Defect Condition” interrupt. 388 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 263: Receive SONET Path – SONET Receive Path Interrupt Enable – Byte 1 (Address Location= 0xN18E, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 New Path Trace Message Interrupt Enable Detection of REI-P Event Interrupt Enable Change in UNEQ-P Defect Condition Interrupt Enable Change in PLM-P Defect Condition Interrupt Enable New C2 Byte Interrupt Enable Change in C2 Byte Unstable Defect Condition Interrupt Enable Change in RDI-P Unstable Defect Condition Interrupt Enable New RDI-P Value Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 NEW Path Trace Message Interrupt Enable R/W DESCRIPTION New Path Trace Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “New Path Trace Message” Interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it has accepted (or validated) and new Path Trace Message. 0 – Disables the “New Path Trace Message” Interrupt. 1 – Enables the “New Path Trace Message” Interrupt. 6 Detection of REI-P Event Interrupt Enable R/W Detection of REI-P Event Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of REI-P Event” Interrupt. If this interrupt is enabled, then he Receive SONET POH Processor block will generate an interrupt anytime it detects an REI-P event within the coming STS-1 data-stream. 0 – Disables the “Detection of REI-P Event” Interrupt. 1 – Enables the “Detection of REI-P Event” Interrupt. 5 Change in UNEQ-P Defect Condition Interrupt Enable R/W Change in UNEQ-P (Path – Unequipped) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in UNEQ-P Defect Condition” interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive SONET POH Processor block declares the UNEQ-P Defect Condition. • Whenever the Receive SONET POH Processor block clears the UNEQ-P Defect Condition. 0 – Disables the “Change in UNEQ-P Defect Condition” Interrupt. 1 – Enables the “Change in UNEQ-P Defect Condition” Interrupt. 4 Change in PLM-P Defect Condition Interrupt Enable R/W Change in PLM-P (Path – Payload Label Mismatch) Defect Condition Interrupt Enable: This READ/WRITE bit permits the user to either enable or disable the “Change in PLM-P Defect Condition” interrupt. 389 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive SONET POH Processor block declares the “PLM-P” Defect Condition. • Whenever the Receive SONET POH Processor block clears the “PLMP” Defect Condition. 0 – Disables the “Change in PLM-P Defect Condition” Interrupt. 1 – Enables the “Change in PLM-P Defect Condition” Interrupt. 3 New C2 Byte Interrupt Enable R/W New C2 Byte Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “New C2 Byte” Interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt anytime it has accepted a new C2 byte. 0 – Disables the “New C2 Byte” Interrupt. 1 – Enables the “New C2 Byte” Interrupt. Note: 2 Change in C2 Byte Unstable Defect Condition Interrupt Enable R/W The user can obtain the value of this “New C2” byte by reading the contents of the “Receive SONET Path – Received Path Label Value” Register (Address Location= 0xN196). Change in C2 Byte Unstable Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in C2 Byte Unstable Defect Condition” Interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declares the “C2 Byte Unstable” defect condition. • Whenever the Receive SONET POH Processor block clears the “C2 Byte Unstable” defect condition. 0 – Disables the “Change in C2 Byte Unstable Defect Condition” Interrupt. 1 – Enables the “Change in C2 Byte Unstable Defect Condition” Interrupt. 1 Change in RDI-P Unstable Defect Condition Interrupt Enable R/W Change in RDI-P Unstable Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in RDI-P Unstable Defect Condition” interrupt. If this interrupt is enabled, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following conditions. • Whenever the Receive SONET POH Processor block declares the “RDI-P Unstable” defect condition. • Whenever the Receive SONET POH Processor block clears the “RDI-P Unstable” defect condition. 0 – Disables the “Change in RDI-P Unstable Defect Condition” Interrupt. 1 – Enables the “Change in RDI-P Unstable Defect Condition” Interrupt. 0 New RDI-P Value Interrupt Enable R/W New RDI-P Value Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “New RDI-P Value” interrupt. If this interrupt is enabled, then the Receive SONET POH Processor 390 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S block will generate this interrupt anytime it receives and “validates” a new RDI-P value. 0 – Disables the “New RDI-P Value” Interrupt. 1 – Enable the “New RDI-P Value” Interrupt. 391 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 264: Receive SONET Path – SONET Receive Path Interrupt Enable – Byte 0 (Address Location= 0xN18F, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Detection of B3 Byte Error Interrupt Enable Detection of New Pointer Interrupt Enable Detection of Unknown Pointer Interrupt Enable Detection of Pointer Decrement Interrupt Enable Detection of Pointer Increment Interrupt Enable Detection of NDF Pointer Interrupt Enable Change of LOP-P Defect Condition Interrupt Enable Change of AIS-P Defect Condition Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Detection of B3 Byte Error Interrupt Enable R/W DESCRIPTION Detection of B3 Byte Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of B3 Byte Error” Interrupt. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime it detects a B3-byte error in the incoming STS-1 data-stream. 0 – Disables the “Detection of B3 Byte Error” interrupt. 1 – Enables the “Detection of B3 Byte Error” interrupt. 6 Detection of New Pointer Interrupt Enable R/W Detection of New Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of New Pointer” interrupt. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime it detects a new pointer value in the incoming STS-1 frame. Note: Pointer Adjustments with NDF will not generate this interrupt. 0 – Disables the “Detection of New Pointer” Interrupt. 1 – Enables the “Detection of New Pointer” Interrupt. 5 Detection of Unknown Pointer Interrupt Enable R/W Detection of Unknown Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of Unknown Pointer” interrupt. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime it detects a “Pointer Adjustment” that does not fit into any of the following categories. • An Increment Pointer. • A Decrement Pointer • An NDF Pointer • AIS Pointer • New Pointer. 0 – Disables the “Detection of Unknown Pointer” Interrupt. 1 – Enables the “Detection of Unknown Pointer” Interrupt. 4 Detection of Pointer Decrement Interrupt Enable R/W Detection of Pointer Decrement Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the “Detection of Pointer Decrement” Interrupt. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime it detects a “Pointer-Decrement” event. 0 – Disables the “Detection of Pointer Decrement” Interrupt. 392 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1 – Enables the “Detection of Pointer Decrement” Interrupt. 3 Detection of Pointer Increment Interrupt Enable R/W Detection of Pointer Increment Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of Pointer Increment” Interrupt. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime it detects a “Pointer Increment” event. 0 – Disables the “Detection of Pointer Increment” Interrupt. 1 – Enables the “Detection of Pointer Increment” Interrupt. 2 Detection of NDF Pointer Interrupt Enable R/W Detection of NDF Pointer Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of NDF Pointer” Interrupt. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt anytime it detects an NDF Pointer event. 0 – Disables the “Detection of NDF Pointer” interrupt. 1 – Enables the “Detection of NDF Pointer” interrupt. 1 Change of LOP-P Defect Condition Interrupt Enable R/W Change of LOP-P Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in LOP (Loss of Pointer)” Defect Condition interrupt. If the user enables this interrupt, then the Receive SONET POH Processor will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declares the LOP-P defect condition. • Whenever the Receive SONET POH Processor block clears the LOP-P defect condition. 0 – Disable the “Change of LOP-P Defect Condition” Interrupt. 1 – Enables the “Change of LOP-P Defect Condition” Interrupt. Note: 0 Change of AIS-P Defect Condition Interrupt Enable R/W The user can determine if the Receive SONET POH Processor block is currently declaring the LOP-P defect condition by reading out the contents of Bit 1 (LOP-P Defect Declared) within the “Receive STS-1 Path – SONET Receive POH Status – Byte 0” (Address Location= 0xN187). Change of AIS-P Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of AIS-P (Path AIS)” Defect Condition interrupt. If the user enables this interrupt, then the Receive SONET POH Processor block will generate an interrupt in response to either of the following events. • Whenever the Receive SONET POH Processor block declares the “AIS-P” defect condition. • Whenever the Receive SONET POH Processor block clears the “AIS-P” defect condition. 0 – Disables the “Change of AIS-P Defect Condition” Interrupt. 1 – Enables the “Change of AIS-P Defect Condition” Interrupt. Note: The user can determine if the Receive SONET POH Processor block is currently declaring the AIS-P defect condition by reading out the contents of Bit 0 (AIS-P Defect Declared) within the “Receive SONET Path – SONET Receive POH Status – Byte 0” (Address Location= 0xN187). 393 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 265: Receive SONET Path – SONET Receive RDI-P Register (Address Location= 0xN193, where N ranges in value from 0x05 to 0x07) BIT 7 BIT 6 Unused BIT 5 BIT 4 BIT 3 RDI-P_ACCEPT[2:0] BIT 2 BIT 1 BIT 0 RDI-P THRESHOLD[3:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6–4 RDI-P_ACCEPT[2:0] R/O DESCRIPTION Accepted RDI-P Value: These READ-ONLY bit-fields contain the RDI-P (e.g., bits 5, 6 and 7 within the G1 byte) value that has been most recently accepted by the Receive SONET POH Processor block. Note: 3–0 RDI-P THRESHOLD[3:0] R/W A given RDI-P value will be “accepted” by the Receive SONET POH Processor block, if this RDI-P value has been consistently received in “RDI-P THRESHOLD[3:0]” number of SONET frames. RDI-P Threshold[3:0]: These READ/WRITE bit-fields permit the user to defined the “RDI-P Acceptance Threshold” for the Receive SONET POH Processor Block. The “RDI-P Acceptance Threshold” is the number of consecutive SONET frames, in which the Receive SONET POH Processor block must receive a given RDI-P value, before it “accepts” or “validates” it. The most recently “accepted” RDI-P value is written into the “RDI-P ACCEPT[2:0]” bit-fields, within this register. 394 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 266: Receive SONET Path – Received Path Label Value (Address Location= = 0xN196, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 1 1 1 1 Received_C2_Byte_Value[7:0] BIT NUMBER NAME TYPE 7–0 Received C2 Byte Value[7:0] R/O DESCRIPTION Received “Filtered” C2 Byte Value: These READ-ONLY bit-fields contain the value of the most recently “accepted” C2 byte, via the Receive SONET POH Processor block. The Receive SONET POH Processor block will “accept” a C2 byte value (and load it into these bit-fields) if it has received a consistent C2 byte, in five (5) consecutive SONET frames. Note: The Receive SONET POH Processor block uses this register, along the “Receive SONET Path – Expected Path Label Value” Register (Address Location= 0xN197), when declaring or clearing the UNEQ-P and PLM-P defect conditions. 395 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 267: Receive SONET Path – Expected Path Label Value (Address Location= 0xN197, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/W R/W R/W R/W 1 1 1 1 BIT 3 BIT 2 BIT 1 BIT 0 R/W R/W R/W R/W 1 1 1 1 Expected_C2_Byte_Value[7:0] BIT NUMBER NAME TYPE 7–0 Expected C2 Byte Value[7:0] R/W DESCRIPTION Expected C2 Byte Value: These READ/WRITE bit-fields permits the user to specify the C2 (Path Label Byte) value, that the Receive SONET POH Processor block should expect when declaring or clearing the UNEQ-P and PLM-P defect conditions. If the contents of the “Received C2 Byte Value[7:0]” (see “Receive SONET Path – Received Path Label Value” register) matches the contents in these register, then the Receive SONET POH will not declare the PLM-P nor the UNEQ-P defect conditions. Table 268: Receive SONET Path – B3 Byte Error Count Register – Byte 3 (Address Location= 0xN198, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B3_Byte_Error_Count[31:24] RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 B3_Byte_Error_Count[31:24] RUR DESCRIPTION B3 Byte Error Count – MSB: This RESET-upon-READ register, along with “Receive SONET Path – B3 Byte Error Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive SONET POH Processor block detects a B3 byte error. Note: 1. If the Receive SONET POH Processor block is configured to count B3 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B3 byte (of each incoming STS-1 SPE) that are in error. 2. If the Receive SONET POH Processor block is configured to count B3 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-1 SPE that contains an erred B3 byte. 396 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 269: Receive SONET Path – B3 Byte Error Count Register – Byte 2 (Address Location= 0xN199, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B3_Byte_Error_Count[23:16] BIT NUMBER NAME TYPE 7–0 B3_Byte_Error_Count[23:16] RUR DESCRIPTION B3 Byte Error Count (Bits 23 through 16): This RESET-upon-READ register, along with “Receive SONET Path – B3 Byte Error Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive SONET POH Processor block detects a B3 byte error. Note: 1. If the Receive SONET POH Processor block is configured to count B3 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B3 byte (of each incoming STS-1 SPE) that are in error. 2. If the Receive SONET POH Processor block is configured to count B3 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-1 SPE that contains an erred B3 byte. 397 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 270: Receive SONET Path – B3 Byte Error Count Register – Byte 1 (Address Location= 0xN19A, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B3_Byte_Error_Count[15:8] BIT NUMBER NAME TYPE 7–0 B3_Byte_Error_Count[15:8] RUR DESCRIPTION B3 Byte Error Count – (Bits 15 through 8): This RESET-upon-READ register, along with “Receive SONET Path – B3 Byte Error Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive SONET POH Processor block detects a B3 byte error. Note: 1. If the Receive SONET POH Processor block is configured to count B3 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B3 byte (of each incoming STS-1 SPE) that are in error. 2. If the Receive SONET POH Processor block is configured to count B3 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-1 SPE that contains an erred B3 byte. 398 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 271: Receive SONET Path – B3 Byte Error Count Register – Byte 0 (Address Location= 0xN19B, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 B3_Byte_Error_Count[7:0] BIT NUMBER NAME TYPE 7–0 B3_Byte_Error_Count[7:0] RUR DESCRIPTION B3 Byte Error Count – LSB: This RESET-upon-READ register, along with “Receive SONET Path – B3 Byte Error Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive SONET POH Processor block detects a B3 byte error. Note: 1. If the Receive SONET POH Processor block is configured to count B3 byte errors on a “per-bit” basis, then it will increment this 32 bit counter by the number of bits, within the B3 byte (of each incoming STS-1 SPE) that are in error. 2. If the Receive SONET POH Processor block is configured to count B3 byte errors on a “per-frame” basis, then it will increment this 32 bit counter each time that it receives an STS-1 SPE that contains an erred B3 byte. 399 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 272: Receive SONET Path – REI-P Event Count Register – Byte 3 (Address Location= 0xN19C, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-P_Event_Count[31:24] BIT NUMBER NAME TYPE 7–0 REI-P Event_Count[31:24] RUR DESCRIPTION REI-P Event Count – MSB: This RESET-upon-READ register, along with “Receive SONET Path – REI-P Event Count Register – Bytes 2 through 0; function as a 32 bit counter, which is incremented anytime the Receive SONET POH Processor block detects a Path – Remote Error Indicator event within the incoming STS-1 SPE data-stream. Note: 1. If the Receive SONET POH Processor block is configured to count REI-P events on a “per-bit” basis, then it will increment this 32-bit counter by the nibble-value within the REI-P field of the incoming G1 byte within each incoming STS-1 SPE. 2. If the Receive SONET POH Processor block is configured to count REI-P events on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-1 SPE that contains a “non-zero” REI-P value. 400 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 273: Receive SONET Path – REI-P Event Count Register – Byte 2 (Address Location= 0xN19D, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-P_Event_Count[23:16] BIT NUMBER NAME TYPE 7–0 REI-P Event_Count[23:16] RUR DESCRIPTION REI-P Event Count (Bits 23 through 16): This RESET-upon-READ register, along with “Receive SONET Path – REI-P Event Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is incremented anytime the Receive SONET POH Processor block detects a Path – Remote Error Indicator event within the incoming STS-1 SPE data-stream. Note: NOTES: 1. If the Receive SONET POH Processor block is configured to count REI-P events on a “per-bit” basis, then it will increment this 32-bit counter by the nibble-value within the REI-P field of the incoming G1 byte within each incoming STS-1 frame. 2. If the Receive SONET POH Processor block is configured to count REI-P events on a “per-frame” basis, then it will increment this 32-bit counter each tiem that it receives an STS-1 SPE that contains a “non-zero” REI-P value. 401 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 274: Receive SONET Path – REI-P Event Count Register – Byte 1 (Address Location=0xN19E, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-P_Event_Count[15:8] BIT NUMBER NAME TYPE 7–0 REI-P Event_Count[15:8] RUR DESCRIPTION REI-P Event Count – (Bits 15 through 8) This RESET-upon-READ register, along with “Receive SONET Path – REI-P Event Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is incremented anytime the Receive SONET POH Processor block detects a Path –Remote Error Indicator event within the incoming STS-1 SPE data-stream. Note: 1. If the Receive SONET POH Processor block is configured to count REI-P events on a “per-bit” basis, then it will increment this 32-bit counter by the nibble-value within the REI-P field of the incoming G1 byte within each incoming STS-1 SPE. 2. If the Receive SONET POH Processor block is configured to count REI-P events on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-1 SPE that contains a non-zero REI-P value. 402 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 275: Receive SONET Path – REI-P Event Count Register – Byte 0 (Address Location= 0xN19F, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 RUR RUR RUR RUR 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 RUR RUR RUR RUR 0 0 0 0 REI-P_Event_Count[7:0] BIT NUMBER NAME TYPE 7–0 REI-P Event_Count[7:0] RUR DESCRIPTION REI-P Event Count – LSB: This RESET-upon-READ register, along with “Receive SONET Path – REI-P Event Count Register – Bytes 3 through 1; function as a 32 bit counter, which is incremented anytime the Receive SONET POH Processor block detects a Path – Remote Error Indicator event within the incoming STS-1 SPE data-stream. Note: 1. If the Receive SONET POH Processor block is configured to count REI-P events on a “per-bit” basis, then it will increment this 32-bit counter by the nibble-value within the REI-P field of the incoming G1 byte within each incoming STS-1 frame. 2. If the Receive SONET POH Processor block is configured to count REI-P events on a “per-frame” basis, then it will increment this 32-bit counter each time that it receives an STS-1 SPE that contains a “nonzero” REI-P value. 403 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 276: Receive SONET Path – Receive Path Trace Message Buffer Control Register (Address Location=0xN1A3, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 Receive Path Trace Message Buffer Read Select Receive Path Trace Message Accept Threshold Path Trace Message Alignment Message Type BIT 1 BIT 0 Receive Path Trace Message Length[1:0] R/O R/O R/O R/W R/W R/W R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–5 Unused R/O 4 Received Path Trace Message Buffer Read Select R/W DESCRIPTION Receive Path Trace Message Buffer Read Selection: This READ/WRITE bit-field permits a user to specify which of the following Receive Path Trace Message buffer segments that the Microprocessor will read out, whenever it reads out the contents of the Receive Path Trace Message Buffer. m. The “Actual” Receive Path Trace Message Buffer. The “Actual” Receive Path Trace Message Buffer contains the contents of the most recently received (and accepted) Path Trace Message via the incoming STS-1 data-stream. n. The “Expected” Receive Path Trace Message Buffer. The “Expected” Receive Path Trace Message Buffer contains the contents of the Path Trace Message that the user “expects” to receive from the remote PTE. The contents of particular buffer are usually specified by the user. 0 – Executing a READ to the Receive Path Trace Message Buffer, will return the contents within the “Actual” Receive Path Trace Message” buffer. 1 – Executing a READ to the Receive Path Trace Message Buffer will return the contents within the “Expected Receive Path Trace Message Buffer”. Note: 3 Path Trace Message Accept Threshold R/W In the case of the Receive SONET POH Processor block, the “Receive Path Trace Message Buffer” is located at Address Location 0xN500 through 0xN53F, where N ranges in value from 0x02 to 0x04. Path Trace Message Accept Threshold: This READ/WRITE bit-field permits a user to select the number of consecutive times that the Receive SONET POH Processor block must receive a given Receive Path Trace Message, before it is accepted and loaded into the “Actual” Receive Path Trace Message buffer, as described below. 0 – Configures the Receive SONET POH Processor block to accept the incoming Path Trace Message after it has received it the third time in succession. 1 – Configures the Receive SONET POH Processor block to accept the Incoming Path Trace Message after it has received in 404 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S the fifth time in succession. 2 Path Trace Message Alignment Type R/O Path Trace Message Alignment Type: This READ/WRITE bit-field permits a user to specify how the Receive SONET POH Processor block will locate the boundary of the incoming Path Trace Message (within the incoming STS-1 data-stream), as indicated below. 0 – Configures the Receive SONET POH Processor block to expect the Path Trace Message boundary to be denoted by a “Line Feed” character. 1 – Configures the Receive SONET POH Processor block to expect the Path Trace Message boundary to be denoted by the presence of a “1” in the MSB (most significant byte) of the very first byte (within the incoming Path Trace Message). In this caes, all of the remaining bytes (within the incoming Path Trace Message) will each have a “0” within their MSBs. 1–0 Receive Path Trace Message Length[1:0] R/W Receive Path Trace Message Length[1:0]: These READ/WRITE bit-fields permit the user to specify the length of the Receive Path Trace Message that the Receive SONET POH Processor block will accept and load into the “Actual” Receive Path Trace Message Buffer. The relationship between the content of these bit-fields and the corresponding Receive Path Trace Message Length is presented below. Receive Path Trace Message Length[1:0] Resulting Path Trace Message Length (in terms of bytes) 00 1 Byte 01 16 Bytes 10/11 64 Bytes 405 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 277: Receive SONET Path – Pointer Value – Byte 1 (Address Location= 0xN1A6, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 R/O R/O 0 0 BIT 1 R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 Unused BIT 0 Current_Pointer Value MSB[9:8] BIT NUMBER NAME TYPE 7-2 Unused R/O 1–0 Current_Pointer_Value_MSB[1:0] R/O DESCRIPTION Current Pointer Value – MSB: These READ-ONLY bit-fields, along with that from the “Receive SONET Path – Pointer Value – Byte 0” Register combine to reflect the current value of the pointer that the “Receive SONET POH Processor” block is using to locate the SPE within the incoming SONET data stream. Note: These register bits comprise the two-most significant bits of the Pointer Value. Table 278: Receive SONET Path – Pointer Value – Byte 0 (Address Location=0xN1A7, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Current_Pointer_Value_LSB[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Current_Pointer_Value_LSB[7:0] R/O DESCRIPTION Current Pointer Value – LSB: These READ-ONLY bit-fields, along with that from the “Receive SONET Path – Pointer Value – Byte 1” Register combine to reflect the current value of the pointer that the “Receive SONET POH Processor” block is using to locate the SPE within the incoming SONET data stream. Note: 406 These register bits comprise the Lower Byte value of the Pointer Value. XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 279: Receive SONET Path – AUTO AIS Control Register (Address Location= 0xN1BB, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Transmit AIS-P (Downstream) Upon C2 Byte Unstable Transmit AIS-P (Downstream) Upon UNEQ-P Transmit AIS-P (Downstream) Upon PLMP Transmit AIS-P (Downstream) Upon Path Trace Message Unstable Transmit AIS-P (Downstream) Upon TIM-P Transmit AIS-P (Downstream) upon LOP-P Transmit AIS-P (Downstream) Enable R/O R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Transmit AIS-P (Downstream) upon C2 Byte Unstable R/W DESCRIPTION Transmit Path AIS (Downstream, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) upon Declaration of the Unstable C2 Byte Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive SONET POH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper blocks), anytime (and for the duration that) it declares the Unstable C2 Byte defect condition within the “incoming” STS-1 data-stream. 0 – Does not configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever it declares the “Unstable C2 Byte” defect condition. 1 – Configures the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever (and for the duration that) it declares the “Unstable C2 Byte” defect condition. Note: 5 Transmit AIS-P (Downstream) upon UNEQ-P R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (Downstream, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper blocks) upon Declaration of the UNEQ-P (Path – Unequipped) Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive SONET POH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block), anytime (and for the duration that) it declares the UNEQ-P defect condition. 0 – Does not configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper Block) whenever it declares the UNEQ-P defect condition. 1 – Configures the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the 407 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever (and for the duration that) it declares the UNEQ-P defect condition. Note: 4 Transmit AIS-P (Downstream) upon PLM-P R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (Downstream, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) upon Declaration of PLM-P (Path – Payload Label Mismatch) Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive SONET POH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block), anytime (and for the duration that) it declares the PLM-P defect condition. 0 – Does not configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever it declares the PLM-P defect condition. 1 – Configures the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever (and for the duration that) it declares the PLM-P defect condition. Note: 3 Transmit AIS-P (Downstream) upon Path Trace Message Unstable R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (Downstream, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) upon declaration of the Path Trace Message Unstable Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive SONET POH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block), anytime (and for the duration that) it declares the Path Trace Message Unstable defect condition within the “incoming” STS-1 data-stream. 0 – Does not configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever (and for the duration that) it declares the Path Trace Message Unstable defect condition within the “incoming” STS-1 data-stream. 1 – Configures the Receive SONET POH Processor block to automatically automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever (and for the duration that) it declares the Path Trace Message Unstable defect condition. Note: 2 Transmit AIS-P (Downstream) upon TIM-P R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (Downstream towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) upon declaration o the TIM-P (Path Trace Identification Message Mismatch) defect condition: 408 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S This READ/WRITE bit-field permits the user to configure the Receive SONET POH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block), anytime (and for the duration that) it declares the TIM-P defect condition within the incoming STS-1 data-stream. 0 – Does not configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever it declares the TIM-P defect condition. 1 – Configures the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever (and for the duration that) it declares the TIM-P defect condition. Note: 1 Transmit AIS-P (Downstream) upon LOP-P R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Transmit Path AIS (Downstream, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) upon Declaration of the Loss of Pointer (LOP-P) Defect Condition: This READ/WRITE bit-field permits the user to configure the Receive SONET POH Processor block to automatically transmit the Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block), anytime (and for the duration that) it declares the LOP-P defect condition within the incoming STS-1 data-stream. 0 – Does not configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) whenever it declares the LOP-P defect condition. 1 – Configures the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block)) whenever (and for the duration that) it declares the LOP-P defect condition. Note: 0 Transmit AIS-P (Downstream) Enable R/W The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator, in response to this defect condition. Automatic Transmission of AIS-P Enable: This READ/WRITE bit-field serves two purposes. It permits the user to configure the Receive SONET POH Processor block to automatically transmit the Path AIS (AIS-P) indicator, via the downstream traffic (e.g., towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block), upon declaration of either the UNEQP, PLM-P, TIM-P, LOP-P or the Path Trace Message Unstable defect conditions. It also permits the user to configure the Receive SONET POH Processor block to automatically transmit a Path (AIS-P) Indicator via the “downstream” traffic (e.g., towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapper block) anytime (and for the duration that) it declares the AIS-P defect condition within the “incoming “ STS-1 datastream. 0 – Configures the Receive SONET POH Processor block to NOT automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 409 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Mapper block) whenever it declares any of the “above-mentioned” defect conditions. 1 – Configures the Receive SONET POH Processor block to automatically transmit the AIS-P indicator (via the “downstream” traffic, towards the corresponding Transmit STS-1 POH Processor or DS3/E3 Mapp;er block) whenver (and for the duration that) it declares any of the “abovementioned” condition. Note: The user must also set the corresponding bit-fields (within this register) to “1” in order to configure the Receive SONET POH Processor block to automatically transmit the AIS-P indicator upon detection of a given alarm/defect condition. 410 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 280: Receive SONET Path – Serial Port Control Register (Address Location= 0xN1BF) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 RxPOH_CLOCK_SPEED[7:0] R/O R/O R/O R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Unused R/O 3-0 RxPOH_CLOCK_SPEED[7:0] R/W DESCRIPTION RxPOHClk Output Clock Signal Speed: These READ/WRITE bit-fields permit the user to specify the frequency of the “RxPOHClk output clock signal. The formula that relates the contents of these register bits to the “RxPOHClk” frequency is presented below. FREQ = 19.44 /[2 * (RxPOH_CLOCK_SPEED + 1) Notes: 411 For STS-3/STM-1 applications, the frequency of the RxPOHClk output signal must be in the range of 0.304MHz to 9.72MHz XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 281: Receive SONET Path – SONET Receive Auto Alarm Register – Byte 0 (Address Location= 0xN1C3, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3s) upon LOP-P Unused Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3s) upon PLM-P Unused Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3s) upon UNEQ-P Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3s) upon TIM-P Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3s) upon AIS-P Transmit DS3 AIS (via Downstream DS3/E3) upon PDI-P R/W R/O R/W R/O R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7 Transmit AIS-P or DS3/E3 AIS (via Downstream STS1s or DS3/E3s) upon LOPP R/W Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3 signals) upon declaration of the LOP-P defect condition: The exact function of this register bit-field depends upon whether the channel has been configured to operate in the STS-1 or DS3/E3 Mode, as described below. If the Channel has been configured to operate in the STS-1 Mode: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the LOP-P defect condition. If the Channel has been configured to operate in the DS3/E3 Mode: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block (within the corresponding channel) to automatically transmit the DS3/E3 AIS indicator via the “downstream” DS3/E3 signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the LOP-P defect condition. 0 – Does not configure the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signal, anytime the Receive SONET POH Processor block declares the LOP-P defect condition. 1 – Configures the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the LOP-P defect condition. 6 Unused R/O 5 Transmit AIS-P or DS3/E3 AIS (via Downstream STS1s or DS3/E3s) upon PLMP R/W Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3 signals) upon declaration of the PLM-P defect condition: The exact function of this register bit-field depends upon whether the 412 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S channel has been configured to operate in the STS-1 or DS3/E3 Mode, as described below. If the Channel has been configured to operate in the STS-1 Mode: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the PLM-P defect condition. If the Channel has been configured to operate in the DS3/E3 Mode: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block (within the corresponding channel) to automatically transmit the DS3/E3 AIS indicator via the “downstream” DS3/E3 signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the PLM-P defect condition. 0 – Does not configure the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signals, anytime the Receive SONET POH Processor block declares the PLM-P defect condition. 1 – Configures the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the PLM-P defect condition. 4 Unused R/O 3 Transmit AIS-P or DS3/E3 AIS (via Downstream STS1s or DS3/E3s) upon UNEQ-P R/W Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3 signals) upon declaration of the UNEQ-P defect condition: The exact function of this register bit-field depends upon whether the channel has been configured to operate in the STS-1 or DS3/E3 Mode, as described below. If the Channel has been configured to operate in the STS-1 Mode: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the UNEQ-P defect condition. If the Channel has been configured to operate in the DS3/E3 Mode: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block (within the corresponding channel) to automatically transmit the DS3/E3 AIS indicator via the “downstream” DS3/E3 signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the UNEQ-P defect condition. 0 – Does not configure the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signal, anytime the Receive SONET POH Processor block declares the UNEQ-P defect condition. 413 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 1 – Configures the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the UNEQ-P defect condition. 2 Transmit AIS-P or DS3/E3 (via Downstream STS-1s) upon TIM-P R/W Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3 signals) upon declaration of the TIM-P defect condition: The exact function of this register bit-field depends upon whether the channel has been configured to operate in the STS-1 or DS3/E3 Mode, as described below. If the Channel has been configured to operate in the STS-1 Mode: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the TIM-P defect condition. If the Channel has been configured to operate in the DS3/E3 Mode: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block (within the corresponding channel) to automatically transmit the DS3/E3 AIS indicator via the “downstream” DS3/E3 signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the TIM-P defect condition. 0 – Does not configure the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signals, anytime the Receive SONET POH Processor block declares the TIM-P defect condition. 1 – Configures the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the TIM-P defect condition. 1 Transmit AIS-P or DS3/E3 AIS (via Downstream STS1s or DS3/E3s) upon AISP R/W Transmit AIS-P or DS3/E3 AIS (via Downstream STS-1s or DS3/E3 signals) upon declaration of the AIS-P defect condition: The exact function of this register bit-field depends upon whether the channel has been configured to operate in the STS-1 or DS3/E3 Mode, as described below. If the Channel has been configured to operate in the STS-1 Mode: This READ/WRITE bit-field permits the user to configure the Transmit STS-1 POH Processor block (within the corresponding channel) to automatically transmit the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the AIS-P defect condition. If the Channel has been configured to operate in the DS3/E3 Mode: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer block (within the corresponding channel) to automatically transmit the DS3/E3 AIS indicator via the “downstream” DS3/E3 signal, anytime (and for the duration that) the Receive SONET POH 414 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Processor block declares the AIS-P defect condition. 0 – Does not configure the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signals, anytime the Receive SONET POH Processor block declares the AIS-P defect condition. 1 – Configures the corresponding Transmit STS-1 POH Processor (or DS3/E3 Framer) block to automatically transmit the AIS-P (or DS3/E3 AIS) Indicator via the “downstream” STS-1 (or DS3/E3) signal, anytime (and for the duration that) the Receive SONET POH Processor block declares the AIS-P defect condition. 0 Transmit DS3 AIS (via Downstream DS3s) upon PDI-P R/W Transmit DS3 AIS upon PDI-P or AIS-P: This READ/WRITE bit-field permits the user to configure the Receive SONET POH Processor block to automatically command the DS3/E3 Framer block to transmit an AIS signal (to downstream circuitry) whenever it (the Receive SONET POH Processor block) detects an Async PDI-P or an AIS-P condition, in the incoming STS1 SPE data-stream. 0 – Configures the Receive SONET POH Processor block to NOT command the DS3/E3 Framer block to automatically transmit an AIS signal upon detection of an AIS-P or a PDI-P condition. 1 – Configures the Receive SONET POH Processor block to command the DS3/E3 Framer block to automatically transmit an AIS signal upon detection of an AIS-P or PDI-P. Note: Note: This register bit is only valid if the incoming STS-1 signal is transporting an asynchronous DS3 signal; and if the corresponding channel is configured to operate in the DS3 Mode. When an asynchronous DS3 signal is being transported by a SONET signal, the PDI-P condition is indicated by setting the C2 byte to the value “0xFC”. 415 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 282: Receive SONET Path – Receive J1 Byte Capture Register (Address Location= 0xN1D3, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 J1_Byte_Captured_Value[7:0] BIT NUMBER NAME TYPE 7–0 J1_Byte_Captured_Value[7:0] R/O DESCRIPTION J1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the J1 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new J1 byte value. Table 283: Receive SONET Path – Receive B3 Byte Capture Register (Address Location= 0xN1D7, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 B3_Byte_Captured_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 B3_Byte_Captured_Value[7:0] R/O DESCRIPTION B3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the B3 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new B3 byte value. 416 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 284: Receive SONET Path – Receive C2 Byte Capture Register (Address Location= 0xN1DB, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 C2_Byte_Captured_Value[7:0] BIT NUMBER NAME TYPE 7–0 C2_Byte_Captured_Value[7:0] R/O DESCRIPTION C2 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the C2 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new C2 byte value. Table 285: Receive SONET Path – Receive G1 Byte Capture Register (Address Location= 0xN1DF, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 G1_Byte_Captured_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 G1_Byte_Captured_Value[7:0] R/O DESCRIPTION G1 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the G1 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new G1 byte value. 417 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 286: Receive SONET Path – Receive F2 Byte Capture Register (Address Location=0xN1E3, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 F2_Byte_Captured_Value[7:0] BIT NUMBER NAME TYPE 7–0 F2_Byte_Captured_Value[7:0] R/O DESCRIPTION F2 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the F2 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new F2 byte value. Table 287: Receive SONET Path – Receive H4 Byte Capture Register (Address Location= 0xN1E7, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 H4_Byte_Captured_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 H4_Byte_Captured_Value[7:0] R/O DESCRIPTION H4 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the H4 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new H4 byte value. 418 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 288: Receive SONET Path – Receive Z3 Byte Capture Register (Address Location= 0xN1EB, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 Z3_Byte_Captured_Value[7:0] BIT NUMBER NAME TYPE 7–0 Z3_Byte_Captured_Value[7:0] R/O DESCRIPTION Z3 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z3 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new Z3 byte value. Table 289: Receive SONET Path – Receive Z4 (K3) Byte Capture Register (Address Location= 0xN1EF, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Z4(K3)_Byte_Captured_Value[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–0 Z4(K3)_Byte_Captured_Value [7:0] R/O DESCRIPTION Z4 (K3) Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z4 (K3) byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new Z4 (K3) byte value. 419 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 290: Receive SONET Path – Receive Z5 Capture Register (Address Location= 0xN1F3, where N ranges in value from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 Z5_Byte_Captured_Value[7:0] BIT NUMBER NAME TYPE 7–0 Z5_Byte_Captured_Value[7:0] R/O DESCRIPTION Z5 Byte Captured Value[7:0] These READ-ONLY bit-fields contain the value of the Z5 byte, within the most recently received SONET frame. This particular value is stored in this register for one SONET frame period. During the next SONET frame period, this value will be overridden with a new Z5 byte value. 420 XRT94L33 Rev222...000...000 1.10 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S DS3/E3 FRAMER BLOCK The register map for the DS3/E3 Framer Block is presented in the Table below. Additionally, a detailed description of each of the “DS3/E3 Framer” block registers is presented below. In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the XRT94L33, with the “DS3/E3 Framer Block “highlighted” is presented below in Figure 7. Figure 7: Illustration of the Functional Block Diagram of the XRT94L33 (whenever it has been configured to operate in the 3-Channel DS3/STS-1 to STS-3 Mode), with the DS3/E3 Framer Block “Highlighted Tx TxSTS-3 STS-3 TOH TOHProcessor Processor Block Block Rx RxSTS-3 STS-3TOH TOH Processor Rx STS-3 Processor Rx STS-3TOH TOH Block Processor Block Block Processor Block (Primary) (Primary) STS-3 STS-3 Telecom TelecomBus Bus Block Block Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (Primary) (Primary) Tx/Rx Tx/Rx Line LineI/F I/FBlock Block (APS) (APS) Tx TxSONET SONET POH POH Processor Processor Block Block Rx RxSONET SONET POH POH Processor Processor Block Block Rx RxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block Tx TxSTS-1 STS-1 Pointer Pointer Justification Justification Block Block DS3/E3 DS3/E3 Mapper Mapper Block Block Rx RxSTS-1 STS-1 POH POH Block Block Rx RxSTS-1 STS-1 TOH TOH Block Block Tx TxSTS-1 STS-1 POH POH Block Block Tx TxSTS-1 STS-1 TOH TOH Block Block DS3/E3 DS3/E3 Jitter Jitter Attenuator Attenuator Block Block DS3/E3 DS3/E3 Framer Framer Block Block Channel 1 To Channels 2 – 3 From Channels 2 – 3 Clock ClockSynthesizer SynthesizerBlock Block Microprocessor MicroprocessorInterface Interface 421 JTAG JTAGTest TestPort Port XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 DS3/E3 FRAMER BLOCK REGISTER Table 291: DS3/E3 Framer Block Control Register Map ADDRESS LOCATION REGISTER NAME DEFAULT VALUES 0xN300 Operating Mode Register 0x23 0xN301 I/O Control Register 0xA0 Reserved 0x00 0xN304 Block Interrupt Enable Register 0x00 0xN305 Block Interrupt Status Register 0x00 Reserved 0x00 Test Register 0x00 0xN30D – 0xN30F Payload HDLC Control Register 0x00 0xN30E – 0xN30F Reserved 0x00 RxDS3 Configuration and Status Register 0x02 0xN302, 0xN303 0xN306 – 0xN30B 0xN30C 0xN310 RxE3 Configuration and Status Register # 1 – G.832 RxE3 Configuration and Status Register # 1 – G.751 0xN311 0x67 RxDS3 Status Register RxE3 Configuration and Status Register # 2 – G.832 RxE3 Configuration and Status Register # 2 – G.751 0xN312 RxDS3 Interrupt Enable Register 0x00 RxE3 Interrupt Enable Register # 1 – G.832 RxE3 Interrupt Enable Register # 1 – G.751 0xN313 0x00 RxDS3 Interrupt Status Register RxE3 Interrupt Enable Register # 2 – G.832 RxE3 Interrupt Enable Register # 2 – G.751 0xN314 RxDS3 Sync Detect Enable Register 0x00 RxE3 Interrupt Status Register # 1 – G.832 RxE3 Interrupt Status Register # 1 – G.751 0xN315 RxE3 Interrupt Status Register # 2 – G.832 0x00 RxE3 Interrupt Status Register # 2 – G.751 0xN316 RxDS3 FEAC Register 0x7E 0xN317 RxDS3 FEAC Interrupt Enable/Status Register 0x00 0xN318 RxDS3 LAPD Control Register 0x00 RxE3 LAPD Control Register 0xN319 0x00 RxDS3 LAPD Status Register RxE3 LAPD Status Register 422 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S ADDRESS LOCATION 0xN31A REGISTER NAME DEFAULT VALUES 0x00 RxE3 NR Byte Register – G.832 RxE3 Service Bit Register – G.751 0xN31B RxE3 GC Byte Register – G.832 0x00 0xN31C RxE3 TTB-0 Register – G.832 0x00 0xN31D RxE3 TTB-1 Register – G.832 0x00 0xN31E RxE3 TTB-2 Register – G.832 0x00 0xN31F RxE3 TTB-3 Register – G.832 0x00 0xN320 RxE3 TTB-4 Register – G.832 0x00 0xN321 RxE3 TTB-5 Register – G.832 0x00 0xN322 RxE3 TTB-6 Register – G.832 0x00 0xN323 RxE3 TTB-7 Register – G.832 0x00 0xN324 RxE3 TTB-8 Register – G.832 0x00 0xN325 RxE3 TTB-9 Register – G.832 0x00 0xN326 RxE3 TTB-10 Register – G.832 0x00 0xN327 RxE3 TTB-11 Register – G.832 0x00 0xN328 RxE3 TTB-12 Register – G.832 0x00 0xN329 RxE3 TTB-13 Register – G.832 0x00 0xN32A RxE3 TTB-14 Register – G.832 0x00 0xN32B RxE3 TTB-15 Register – G.832 0x00 0xN32C RxE3 SSM Register – G.832 0x00 Reserved 0x00 0xN32F RxDS3 Pattern Register 0x0C 0xN330 TxDS3 Configuration Register 0x00 0xN32D – 0xN32E TxE3 Configuration Register – G.832 TxE3 Configuration Register – G.751 0xN331 TxDS3 FEAC Configuration and Status Register 0x00 0xN332 TxDS3 FEAC Register 0x7E 0xN333 TxDS3 LAPD Configuration Register 0x08 TxE3 LAPD Configuration Register 0xN334 TxDS3 LAPD Status/Interrupt Register 0x00 TxE3 LAPD Status/Interrupt Register 0xN335 0x00 TxDS3 M-Bit Mask Register TxE3 GC Byte Register – G.832 TxE3 Service Bits Register – G.751 423 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM ADDRESS LOCATION 0xN336 REGISTER NAME Rev222...000...000 DEFAULT VALUES 0x00 TxDS3 F-Bit Mask # 1 Register TxE3 MA Byte Register – G.832 0xN337 0x00 TxDS3 F-Bit Mask # 2 Register TxE3 NR Byte Register – G.832 0xN338 0x00 TxDS3 F-Bit Mask # 3 Register TxE3 TTB-0 Register – G.832 0xN339 0x00 TxDS3 F-Bit Mask # 4 Register TxE3 TTB-1 Register – G.832 0xN33A TxE3 TTB-2 Register – G.832 0x00 0xN33B TxE3 TTB-3 Register – G.832 0x00 0xN33C TxE3 TTB-4 Register – G.832 0x00 0xN33D TxE3 TTB-5 Register – G.832 0x00 0xN33E TxE3 TTB-6 Register – G.832 0x00 0xN33F TxE3 TTB-7 Register – G.832 0x00 0xN340 TxE3 TTB-8 Register – G.832 0x00 0xN341 TxE3 TTB-9 Register – G.832 0x00 0xN342 TxE3 TTB-10 Register – G.832 0x00 0xN343 TxE3 TTB-11 Register – G.832 0x00 0xN344 TxE3 TTB-12 Register – G.832 0x00 0xN345 TxE3 TTB-13 Register – G.832 0x00 0xN346 TxE3 TTB-14 Register – G.832 0x00 0xN347 TxE3 TTB-15 Register – G.832 0x00 0xN348 TxE3 FA1 Error Mask Register – G.832 0x00 TxE3 FAS Error Mask Upper Register – G.751 0xN349 TxE3 FA2 Error Mask Register – G.832 0x00 TxE3 FAS Error Mask Lower Register – G.751 0xN34A TxE3 BIP-8 Mask Register – G.832 0x00 TxE3 BIP-4 Mask Register – G.751 0xN34B Tx SSM Register – G.832 0x00 0xN34C TxDS3 Pattern Register 0x0C 0xN34D Receive DS3/E3 AIS/PDI-P Alarm Enable Register 0x00 0xN34E PMON Excessive Zero Count Register - MSB 0x00 0xN34F PMON Excessive Zero Count Register - LSB 0x00 0xN350 PMON LCV Event Count Register - MSB 0x00 424 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S ADDRESS LOCATION REGISTER NAME DEFAULT VALUES 0xN351 PMON LCV Event Count Register - LSB 0x00 0xN352 PMON Framing Bit/Byte Error Count Register - MSB 0x00 0xN353 PMON Framing Bit/Byte Error Count Register - LSB 0x00 0xN354 PMON Parity Error Event Count Register - MSB 0x00 0xN355 PMON Parity Error Event Count Register - LSB 0x00 0xN356 PMON FEBE Event Count Register - MSB 0x00 0xN357 PMON FEBE Event Count Register - LSB 0x00 0xN358 PMON CP-Bit Error Count Register - MSB 0x00 0xN359 PMON CP-Bit Error Count Register - LSB 0x00 Reserved 0x00 0xN368 PMON PRBS Bit Error Count Register - MSB 0x00 0xN369 PMON PRBS Bit Error Count Register - LSB 0x00 Reserved 0x00 0xN36C PMON Holding Register 0x00 0xN36D One Second Error Status Register 0x00 0xN36E One Second – LCV Count Accumulator Register - MSB 0x00 0xN36F One Second – LCV Count Accumulator Register - LSB 0x00 0xN370 One Second – Parity Error Accumulator Register - MSB 0x00 0xN371 One Second – Parity Error Accumulator Register - LSB 0x00 0xN372 One Second – CP Bit Error Accumulator Register - MSB 0x00 0xN373 One Second – CP Bit Error Accumulator Register – LSB 0x00 Reserved 0x00 Line Interface Drive Register 0x00 Reserved 0x00 0xN383 TxLAPD Byte Count Register 0x00 0xN384 RxLAPD Byte Count Register 0x00 Reserved 0x00 0xN3B0 Transmit LAPD Memory Indirect Address Register 0x00 0xN3B1 Transmit LAPD Memory Indirect Data Register 0x00 0xN3B2 Receive LAPD Memory Indirect Address Register 0x00 0xN3B3 Receive LAPD Memory Indirect Data Register 0x00 Reserved 0x00 0xN35A – 0xN367 0xN36A – 0xN36B 0xN374 – 0xN37F 0xN380 0xN381 – 0xN382 0xN385 – 0xN3AF 0xN3B4 – 0xN3EF 425 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM ADDRESS LOCATION Rev222...000...000 REGISTER NAME DEFAULT VALUES 0xN3F0 Receive DS3/E3 Configuration Synchronizer Block – Byte 1 Register – Secondary Frame 0x10 0xN3F1 Receive DS3/E3 Configuration Synchronizer Block – Byte 0 Register – Secondary Frame 0x10 0xN3F2 Receive DS3/E3 AIS/PDI-P Alarm Enable Register – Secondary Frame Synchronizer Block 0x00 Reserved 0x00 0xN3F8 Receive DS3/E3 Interrupt Enable Register – Secondary Frame Synchronizer Block 0x00 0xN3F9 Receive DS3/E3 Interrupt Status Register – Secondary Frame Synchronizer Block 0x00 Reserved 0x00 0xN3F3 – 0xN3F7 0xN3FA – 0xN3FF 426 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.10.1 DS3/E3 FRAMER BLOCK REGISTER DESCRIPTION Table 292: Operating Mode Register (Address Location= 0xN300, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Framer Local Loop Back IsDS3 Internal LOS Enable Software RESET Unused Frame Format R/W R/W R/W R/W R/O R/W R/W R/W 0 0 1 0 0 0 1 1 BIT NUMBER NAME TYPE DESCRIPTION 7 Framer Local Loop Back R/W Framer Block Local Loop-back Mode: BIT 1 BIT 0 TimRefSel[1:0] This READ/WRITE bit field configures the corresponding DS3/E3 Framer block to operate in the Framer Local Loop-back Mode. If the DS3/E3 Framer block has been configured to operate in the Framer Local Loop-back Mode, then the output of the Frame Generator block will be internally looped back into the input of the Primary Frame Synchronizer block. 0 – Configures the DS3/E3 Framer block to to operate in the Normal Operating (e.g., Non-Framer Local Loop-back) Mode 1 – Configures the DS3/E3 Framer block to operate in the Framer Local Loopback Mode 6 IsDS3 R/W Is DS3 Mode: This READ/WRITE bit-field, along with Bit 2 (Frame Format), permits the user to configure the Frame Generator, the Primary Frame Synchronizer and the Secondary Frame Synchronizer blocks to operate in the appropriate framing format. The relationship between the state of this bit-field, Bit 2 and the resulting framing format is presented below. Bit 6 (IsDS3) Bit 2 (Frame Format) Framing Format 0 0 E3, ITU-T G.751 0 1 E3, ITU-T G.832 1 0 DS3, C-bit Parity 1 1 DS3, M13 NOTE: These bit settings apply to all three (3) sub-blocks within the DS3/E3 Framer block (e.g., the Primary Frame Synchronizer block, the Secondary Frame Synchronizer block and the Frame Generator block). 5 Internal LOS Enable R/W Internal LOS Enable: This READ/WRITE bit-field permits the user to enable or disable the “Internal LOS Detector”, within both the Primary and Secondary Frame Synchronizer blocks. If the user enables the “Internal LOS Detector”, then the Primary and/or Secondary Frame Synchronizer block will be configured to check the incoming DS3/E3 signal for a sufficient number of “consecutive” all-zeros bits and it will declare and clear the LOS defect condition based upon the “1s” density and the number of consecutive “0” bits within the incoming DS3/E3 data-stream. If the user disables the “Internal LOS Detector” then the Primary and/or Secondary Frame Synchronizer block will NOT be configured to check the incoming DS3/E3 signal for a sufficient number of “consecutive” 0 bits, and it 427 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 will NOT declare nor clear the LOS defect condition based upon the “1s” density and the number of consecutive “0” bits within the incoming DS3/E3 data-stream. 0 – Internal LOS Detector is disabled. 1 – Internal LOS Detector is enabled. Note: 4 RESET R/W 1. The Internal LOS Detector can only be enabled if the Channel is configured to operate in the Dual-Rail Mode. If the Channel is configured to operate in the Single-Rail Mode, then the Internal LOS Detector will be disabled. 2. The Primary Frame Synchronizer block or the Secondary Frame Synchronizer block (depending upon which block is configured to operate in the Ingress Path) will automatically declare the LOS defect condition anytime an off-chip LIU device asserts the corresponding “EXT_LOS_n” input pin, independent of the setting of this register bit. Software RESET Input: A “0” to “1” transition in this bit-field commands a Software RESET to each of the following blocks within the Channel. • The Primary Frame Synchronizer Block • The Secondary Frame Synchronizer Block • The Ingress Direction Mapper Block • The Egress Direction Mapper Block Once the user executes a Software reset to the Channel, all of the internal state machines (within each of these blocks) will be reset; and the Primary and Secondary Frame Synchronizer blocks will execute a “Reframe” operation. Note: 3 Unused R/O 2 Frame Format R/W For a Software Reset, the contents of the Command Registers within the corresponding DS3/E3 Framer block will not be reset to their default values. Frame Format: This READ/WRITE bit-field, along with Bit 6 (IsDS3), permits the user to configure the Frame Generator, the Primary Frame Synchronizer and the Secondary Frame Synchronizer blocks to operate in the appropriate framing format. The relationship between the state of this bit-field, Bit 2 and the resulting framing format is presented below. 1-0 TimRefSel[1:0] R/W Bit 6 (IsDS3) Bit 2 (Frame Format) Framing Format 0 0 E3, ITU-T G.751 0 1 E3, ITU-T G.832 1 0 DS3, C-bit Parity 1 1 DS3, M13 Time Reference Select: These two READ/WRITE bit-fields permit the user to define both the timing source and the framing-alignment source for the Frame Generator block, as 428 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S presented below. TimRefSel[1:0] Note: Timing Reference Framing Reference 00 Loop-Timing (Timing is taken from the Primary Frame Synchronizer block) Asynchronous (The Frame Generator block will initiate the generation of a new DS3 or E3 frame, asynchronous to any signals within the Viper Device). 01 The clock source originating from traffic that is “up-stream” from the Frame Generator block. Framing Alignment Information from either the Primary or Secondary Frame Synchronizer block (The Frame Generator block will initialte the generation of a new DS3 or E3 Frame based upon Framing Alignment information originating from either the Primary Frame Synchronizer block or the Secondary Frame Synchronizer block, depending upon which block is upstream from the Frame Generator block). 10 The clock source originating from traffic that is “up-stream” from the Frame Generator block. Asynchronous (The Frame Generator block will initiate the generation of a new DS3 or E3 frame, asynchronous to any signals within the Viper Device). 11 The clock source originating from traffic that is “up-stream” from the Frame Generator block. Asynchronous (The Frame Generator block will initiate the generation of a new DS3 or E3 frame, asynchronous to any signals within the Viper Device). If the user has selected a Frame Generator/Frame Synchronizer configuration, in which the Frame Generator block is down-stream from either the Primary Frame Synchronizer block or the Secondary Frame Synchronizer block, then the user is strongly advised to set these bit-fields to “[0, 1]”. 429 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 293: I/O Control Register (Address Location= 0xN301, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Disable TxLOC LOC Disable RxLOC AMI/ZeroSuppression Primary Frame Single Rail/Dual Rail* Select Frame Generator Block DS3/E3 Clock Output Invert: DS3/E3 CLK_IN Invert: Reframe R/W R/O R/W R/W R/O R/O R/O R/W 1 0 1 0 1 0 0 0 BIT NUMBER NAME TYPE 7 Disable TxLOC R/W DESCRIPTION Disable Transmit Loss of Clock Feature: This READ/WRITE bit-field permits the user to either enable or disable the “Transmit Loss of Clock” feature. If this feature is enabled, then the DS3/E3 Framer block will enable some circuitry that will terminate the current READ or WRITE access (to the Microprocessor Interface), if a “Loss of Transmit (or Frame Generator) Clock Event were to occur. The intent behind this feature is to prevent any READ/WRITE accesses (to the DS3/E3 Framer block) from “hanging” in the event of a “Loss of Clock” event. 0 – Enables the “Transmit Loss of Clock” feature. 1 - Disables the “Transmit Loss of Clock” feature. 6 LOC R/O Loss of Clock Indicator: This READ-ONLY bit-field indicates that the Channel has experiences a Loss of Clock event. 5 Disable RxLOC R/W Disable Receive Loss of Clock Feature This READ/WRITE bit-field permits the user to either enable or disable the “Receive Loss of Clock” feature. If this feature is enabled, then the DS3/E3 Framer block will enable some circuitry that will terminate the current READ or WRITE access (to the Microprocessor Interface), if a “Loss of Receiver (or Frame Synchronizer) Clock Event were to occur. The intent behind this feature is to prevent any READ/WRITE accesses (to the DS3/E3 Framer block) from “hanging” in the event of a “Loss of Clock” event. 0 – Enables the “Receive Loss of Clock” feature. 1 – Disables the “Receive Loss of Clock” feature. 4 AMI/ZeroSuppressi on R/W AMI/Zero-Suppression Line Code Select - Primary Frame Synchronizer Block Input/ Frame Generator Block Output: This READ/WRITE bit-field permits the user to configure the DS3/E3 Framer Block (associated with channel N) to operate in either the AMI or B3ZS/HDB3 Line Code; as described below. 0 – Configures the DS3/E3 Framer Channel to operate in the B3ZS/HDB3 Line Code. 1- Configures the DS3/E3 Framer Channel to operate in the AMI Line Code. 3 Primary Frame Single R/W Primary Frame Synchronizer Block Input/Frame Generator Block Output Single-Rail/Dual-Rail Select: 430 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Rail/Dual Rail Select This READ/WRITE bit-field permits the user to implement either of the following options. 1. To configure the Primary Frame Synchonizer block to accept the Ingress DS3/E3 data (from the DS3/E3 LIU IC) in either the Single-Rail or DualRail Manner. 2. To configure the DS3/E3 Frame Generator block to output the Egress DS3/E3 data (to the DS3/E3 LIU IC) in either rthe Single-Rail or Dual-Rail Manner. More specifically, if the user configures the Primary Frame Synchronizer and the Frame Generator blocks to operate in the Single-Rail Mode, then the following will happen. • The Primary Frame Synchronizer block will accept data (from the LIU IC) in a Single-Rail Manner. • The Frame Generator block will output data (to the LIU IC) in a Single-Rail Manner. If the user configures the Primary Frame Synchronizer and Frame Generator blocks to operate in the Dual-Rail mode, then the following will happen. • The Primary Frame Synchronizer block will accept data (from the LIU IC) in a Dual-Rail Manner. • The Frame Generator block will output data (to the LIU IC) in a Dual-Rail Manner. 0 – Configures the Primary Frame Synchronizer/Frame Generator blocks to operate in the Dual-Rail Mode. 1 – Configures the Primary Frame Synchronizer/Frame Generator blocks to operate in the Single-Rail Mode. Note: 2 Frame Generator Block DS3/E3_ CLK_OUT Invert: This bit-field is only valid if the Primary Frame Synchronizer block has been configured to operate in the Ingress Direction, and if the Frame Generator block has been configured to operate in the Egress Direction. Frame Generator Block - DS3/E3_CLK_OUT Invert: This READ/WRITE bit-field permits the user to configure the DS3/E3 Frame Generator block (of Channel n), within the XRT94L33, to update the “TxDS3POS_n” and “TxDS3NEG_n” output pins (pin B18, G24, AG9) upon either the rising or falling edge of “TxDS3LineClk_n” (pin C17, E25, AF10) 0 – “TxDS3POS_n/TxDS3NEG_n” is updated upon the rising edge of “TxDS3LineClk_n”. The user should insure that the LIU IC will sample “TxDS3POS_n” upon the falling edge of “TxDS3LineClk_n”. 1 – “TxDS3POS_n/TxDS3NEG_n” is updated upon the falling edge of “TxDS3LineClk_n”. The user should insure that the LIU IC will sample “TxDS3POS_n/TxDS3NEG_n” pins upon the rising edge of “TxDS3LineClk_n”. Note: 1 DS3/E3_ Clock Input Invert R/O This bit-field is only active if the Frame Generator block has been configured to operate in the Egress Path. DS3/E3_Clock Input - Invert: This READ/WRITE bit-field permits the user to configure either the Primary or Secondary Frame Synchronizer block (depending upon which Synchronizer block is operating in the Ingress Path), within the XRT94L33; to sample and latch the “RxDS3POS_n” input pins (pin B14. C21. AG15)” upon either the rising or falling edge of “RxDS3LineClk_n” (pin D14, A24, AF14).. 0 – Configures the DS3/E3 Framer “RxDS3POS_n/RxDS3NEG_n” input pins “RxDS3LineClk_n” input signal. block circuitry to sample upon the falling edge of the the 1 block the – Configures the 431 DS3/E3 Framer circuitry to sample XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM “RxDS3POS_n/RxDS3NEG_n” “RxDS3LineClk_n”. input pins upon Rev222...000...000 the rising edge of NOTE: This register bit-field applies to either the Primary or Secondary Frame Synchronizer block (depending upon which block is operating in the Ingress Path). 0 Reframe R/W Primary DS3/E3 Frame Synchronizer Block – Reframe Command: A “0” to “1” transition, within this bit-field commands the Primary DS3/E3 Frame Synchronizer block (within Channel n) to exit the Frame Maintenance Mode, and go back and enter the Frame Acquisition Mode. Note: The user should go back and set this bit-field to “0” following execution of the “Reframe” Command. 432 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 294: Block Interrupt Enable Register (Address Location= 0xN304, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 Primary and/or Secondary DS3/E3 Frame Synchronizer Block Interrupt Enable BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 DS3/E3 Frame Generator Block Interrupt Enable One Second Interrupt R/W R/O R/O R/O R/O R/O R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7 Primary and/or Secondary DS3/E3 Frame Synch Block Interrupt Enable R/W Primary and/or Secondary DS3/E3 Frame Synchronizer Block Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable both the Primary and Secondary Frame Synchronizer blocks for Interrupt Generation. If the user enables the Primary and Secondary Frame Synchronizer blocks (for Interrupt Generation) at the block level, the user still needs to enable the interrupts at the “Source” level, as well; in order for these interrupts to be enabled. However, if the user disables the Primary and Secondary Frame Synchronizer block (for Interrupt Generation) at the Block Level, then ALL Frame Synchronizer-related blocks are disabled. 0 – Both the Primary and Secondary Frame Synchronizer blocks are Disabled for Interrupt Generation. 1 – Both the Primary and Secondary Frame Synchronizer blocks are enabled (at the Block level) for Interrupt Generation. 6–2 Unused R/O 1 DS3/E3 Frame Generator Block Interrupt Enable R/W DS3/E3 Frame Generator Block Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the Frame Generator block for Interrupt Generation. If the user enables the Frame Generator block (for Interrupt Generation) at the block level, the user still needs to enable the interrupts at the “Source” level, as well; in order for these interrupts to be enabled. However, if the user disables the Frame Generator block (for Interrupt Generation) at the Block Level, then ALL Frame Generator-related blocks are disabled. 0 – Frame Generator block is Disabled for Interrupt Generation. 1 – Frame Generator block is Enabled (at the Block Level) for Interrupt Generation. 0 One Second Interrupt R/W One Second Interrupt Enable: This READ/WRITE bit-field permits the user to enable or disable the OneSecond Interrupt, within Channel n. If the user enables this interrupt, then Channel n will generate an interrupt at one second intervals. 0 – One Second Interrupt is disabled. 1 – One Second Interrupt is enabled. 433 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 295: Block Interrupt Status Register (Address Location= 0xN305, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 Primary and/or Secondary DS3/E3 Frame Sync Block Interrupt Status BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 DS3/E3 Frame Generator Block Interrupt Status One Second Interrupt R/O R/O R/O R/O R/O R/O R/O RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7 Primary and/or Secondary DS3/E3 Frame Synch Block Interrupt Status R/O Primary and/or Secondary DS3/E3 Frame Synchronizer Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a “Primary or Secondary DS3/E3 Frame Synchronizer Block”-related interrupt (within Channel n) is requesting interrupt service. 0 – Indicates that neither the Primary nor the Secondary DS3/E3 Frame Synchronizer block (within Channel n) is NOT requesting any interrupt service. 1 – Indicates that either the Primary or the Secondary DS3/E3 Frame Synchronizer block (within Channel n) is requesting interrupt service. 6-2 Unused R/O 1 DS3/E3 Frame Generator Block Interrupt Status R/O DS3/E3 Frame Generator Block Interrupt Status: This READ-ONLY bit-field indicates whether or not a “DS3/E3 Frame Generator” –related interrupt (within Channel n) is requesting interrupt service. 0 – The DS3/E3 Frame Generator block (within Channel n) is NOT requesting any interrupt service. 1 – The DS3/E3 Frame Synchronizer block (within Channel n) is requesting interrupt service. 0 One Second Interrupt Status RUR One Second Interrupt Status This RESET-upon-READ bit-field indicates whether or not a “One Second” Interrupt (from Channel n) has occurred since the last read of this register. 0 – The One Second Interrupt has NOT occurred since the last read of this register. 1 – The One Second Interrupt has occurred since the last read of this register. 434 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 296: Test Register (Address Location= 0xN30C, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 TxOHSrc BIT 5 Unused BIT 4 BIT 3 BIT 2 RxPRBS Lock RxPRBS Enable TxPRBS Enable BIT 1 BIT 0 Unused R/W R/O R/O R/O R/W R/W R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 TxOHSrc R/W DESCRIPTION Transmit Overhead Bit Source: This READ/WRITE bit-field permits the user to configure the DS3/E3 Frame Generator block to accept and insert overhead bits/bytes which are input via the “Transmit Payload Data Input Interface” block, as indicated below. 0 – No overhbead bit insertion will occur. Overhead bits/bytes are internally generated by the DS3/E3 Frame Generator block. 1 – Overhead bit insertion will occur. In this case, the Overhead bits/byte data is accepted from the Transmit Payload Data Input Interface block. Note: 6-5 Unused R/O 4 RxPRBS Lock R/O This register bit applies to all framing formats that are supported by the Frame Generator block. PRBS Lock Indicator: This READ-ONLY bit-field indicates whether or not the PRBS Receiver (within the Primary Frame Synchronizer block) has acquired “PRBS Lock” with the payload data of the incoming DS3 or E3 data stream, as described below. 0 – Indicates that the PRBS Receiver does not have PRBS Lock with the incoming data stream. 1 – Indicates that the PRBS Receiver does have PRBS Lock with the incoming data stream. Note: 3 RxPRBS Enable R/W This bit-field is not valid if the PRBS Receiver is disabled, or if the Primary Frame Synchronizer block is bypassed. Receive PRBS Enable: This READ/WRITE bit-field permits the user to either enable or disable the PRBS Receiver within the Primary Frame Synchronizer block. Once the user enables the PRBS Receiver, then it will proceed to attempt to acquire and maintain pattern (or PRBS Lock) within the payload bits, within the incoming DS3 or E3 data stream. 0 – Disables the PRBS Receiver. 1 – Enables the PRBS Receiver. Note: 2 TxPRBS Enable R/W This bit-field is ignored if the Frame Synchronizer block is by-passed. Transmit PRBS Enable: This READ/WRITE bit-field permits the user to either enable or disable the PRBS Generator within the DS3/E3 Frame Generator block. Once the user enables the PRBS Generator block, then it will proceed to insert a PRBS pattern into the payload bits, within the outbound DS3 or E3 data stream. 0 – Disables the PRBS Generator. 1 – Enables the PRBS Generator. Note: This bit-field is ignored if the Frame Generator block is by-passed. 435 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1-0 Unused R/O 436 Rev222...000...000 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.10.2 RECEIVE DS3 RELATED REGISTERS Table 297: RxDS3 Configuration and Status Register (Address Location= 0xN310, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DS3 AIS Defect Declared DS3 LOS Defect Declared DS3 Idle Condition Declared OOF Defect Declared Unused Framing with Valid PBits F-Sync Algo M-Sync Algo R/O R/O R/O R/O R/O R/W R/W R/W 0 0 0 1 0 0 1 0 BIT NUMBER NAME TYPE DESCRIPTION 7 DS3 AIS Defect Declared R/O DS3 AIS Defect Declared Indicator – Primary Frame Synchronizer Block: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the AIS defect condition in its incoming path, as described below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the DS3 AIS Defect condition. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the DS3 AIS Defect condition. 6 LOS Defect Declared R/O LOS Defect Condition Declared Indicator – Primary Frame Synchronizer Block: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the LOS defect condition, in its incoming path, as described below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the LOS defect condition in its incoming path. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the LOS defect condition in its incoming path. 5 DS3 Idle Condition Declared R/O DS3 Idle Signal Pattern Detected – Primary Frame Synchronizer Block: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently detecting the DS3 Idle pattern, in its incoming path. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently detecting the DS3 Idle Pattern, in its incoming path. 1 – Indicates that the Primary Frame Synchronizer block is currently detecting the DS3 Idle Pattern in its incoming path. NOTE: This bit-field is only valid of the DS3/E3 Framer block has been configured to operate in the DS3 Mode. 4 OOF Defect Condition Declared R/O OOF (Out of Frame) Defect Condition Declared Indicator – Primary Frame Synchronizer Block: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the OOF (Out of Frame) defect condition, as described below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the OOF defect condition. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the OOF defect condition. 437 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 3 Unused R/O 2 Framing with Valid P Bits R/W Rev222...000...000 Framing with Valid P-Bit Select: This READ/WRITE bit-field permits the user to choose between two different sets of DS3 Frame Acquisition/Maintenance criteria that the Primary Frame Synchronizer block will use to (1) acquire and declare Frame Synchronization, and (2) to declare the OOF defect condition. 0 – Normal Framing Acquisition/Maintenance Criteria (without P-bit Checking) In this mode, the Primary Frame Synchronizer block will declare the “In-frame” state, one it has successfully completed both the “F-Bit Search” and the “M-Bit Search” states. 1 – Framing Acquisition/Maintenance with P-bit Checking In this mode, the Primary Frame Synchronizer block will (in addition to passing through the “F-Bit Search” and “M-Bit Search” states) also verify valid P-bits, prior to declaring the “In-Frame” state. Note: 1 F-Sync Algo R/W This bit-field is ignored if the DS3/E3 Framer block is configured to operate in the E3 Mode, or if the Primary Frame Synchronizer block is by-passed. F-Bit Search State Criteria Select: This READ/WRITE bit-field permits the user to choose between two different sets of DS3 Out of Frame (OOF) Declaration criteria. 0 – Configures the Primary Frame Synchronizer block to declare the OOF defect condition anytime it determines that 6 out of the last 15 F-bits are erred. 1 – Configures the Primary Frame Synchronizer block to declare the OOF is defect condition anytime it determines that 3 out of the last 15 F-bits are erred. Note: 0 M-Sync Algo R/W This bit-field is ignored if the DS3/E3 Framer block has been configured to operate in the E3 Mode, or if the Primary Frame Synchronizer block is by-passed. M-Bit Search State Criteria Select: This READ/WRITE bit-field permits the user to choose between two different sets of DS3 Out of Frame (OOF) Declaration criteria. 0 – Configures the Primary Frame Synchronizer block to NOT declare the OOF defect condition, due to M-bit Errors. 1 – Configures the Primary Frame Synchronizer block to declare the OOF defect condition anytime it determines that the M-bits within 3 out of 4 consecutive DS3 frames are in error. NOTE: This bit-field is ignored if the DS3/E3 Framer block has been configured to operate in the E3 Mode. 438 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 298: RxDS3 Status Register (Address Location= 0xN311, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 FERF/RDI Defect Declared RxAIC BIT 2 BIT 1 BIT 0 RxFEBE[2:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-5 Unused R/O 4 FERF/RDI Defect Declared R/O DESCRIPTION FERF/RDI (Far-End Receive Failure/Remote Defect Indicator) Defect Declared Indicator: This READ-ONLY bit-field indicates whether or not the PrimaryFrame Synchronizer block is currently declaring the FERF/RDI defect condition as described below. 0 – The Primary Frame Synchronizer block is NOT currently declaring the FERF/RDI defect condition. 1 – The Primary Frame Synchronizer block is currently declaring the FERF/RDI defect condition. Note: 3 RxAIC R/O This bit-field is not valid if the Primary Frame Synchronizer block has been by-passed. Receive AIC State: This READ-ONLY bit-field indicates the current state of the AIC bit-field within the incoming DS3 data-stream. 0 – Indicates that the Frame Synchronizer block has received at least 2 consecutive M-frames that have the AIC bit-field set to “0”. 1 – Indicates that the Frame Synchronizer block has received at least 63 consecutive M-frames that have the AIC bit-field set to “1”. NOTE: This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3 Mode. 2–0 RxFEBE[2:0] R/O Receive FEBE (Far-End Block Error) Value: These READ-ONLY bit-fields reflect the FEBE value within the most recently received DS3 frame. RxFEBE[2:0] = [1, 1, 1] indicates a normal condition. All other values for RxFEBE[2:0] indicates an erred condition at the remote terminal equipment. Note: 1. This bit-field is not valid if the Primary Frame Synchronizer block has been by-passed. 2. This bit-field is only valid if the Primary Frame Synchronizer block has been configured to operate in the DS3, C-bit Parity Framing format. 439 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 299: RxDS3 Interrupt Enable Register (Address Location= 0xN312, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Detection of CP Bit Error Interrupt Enable Change of LOS Defect Condition Interrupt Enable Change of AIS Defect Condition Interrupt Enable Change of Idle Condition Interrupt Enable Change of FERF/RDI Defect Condition Interrupt Enable Change of AIC State Interrupt Enable Change of OOF Defect Condition Interrupt Enable Detection of P-Bit Error Interrupt Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7 Detection of CP Bit Error Interrupt Enable R/W Detection of CP-Bit Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of CP-Bit Error” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt anytime it detects CP bit errors. 0 – Disables the “Detection of CP Bit Error” Interrupt. 1 – Enables the “Detection of CP-Bit Error” Interrupt. Note: 6 Change of LOS Defect Condition Interrupt Enable R/W This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. Change in LOS Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in LOS (Loss of Signal) Defect Condition” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. • The instant that the Primary Frame Synchronizer block declares an LOS defect condition. • The instant that the Primary Frame Synchronizer block clears the LOS defect condition. 0 – Disables the “Change in LOS Defect Condition” Interrupt. 1 – Enables the “Change in LOS Defect Condition” Interrupt. NOTE: This configuration setting only applies to the Primary Frame Synchronizer block. This configuration setting does not apply to the Secondary Frame Synchronizer block. 5 Change of AIS Defect Condition Interrupt Enable R/W Change in AIS Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in AIS (Alarm Indication Signal) Defect Condition” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. • The instant that the Primary Frame Synchronizer block declares an AIS defect condition. • The instant that the Primary Frame Synchronizer block clears the AIS defect condition. 0 – Disables the “Change in AIS Defect Condition” Interrupt. 440 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1 – Enables the “Change in AIS Defect Condition” Interrupt. Note: 4 Change of DS3 Idle Condition Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Change in DS3 Idle Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in DS3 Idle Condition” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. • The instant that the Primary Frame Synchronizer block declares the DS3 Idle condition. • The instant that the Primary Frame Synchronizer block clears the DS3 Idle condition. 0 – Disables the “Change in DS3 Idle Condition” Interrupt. 1 – Enables the “Change in DS3 Idle Condition” Interrupt. Note: 3 Change of FERF/RDI Defect Condition Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Change in FERF/RDI Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in FERF/RDI (Far-End Receive Failure/Remote Defect Indicator) Condition” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. • The instant that the Primary Frame Synchronizer block declares the FERF/RDI defect condition. • The instant that the Primary Frame Synchronizer block clears the FERF/RDI defect condition. 0 – Disables the “Change in FERF/RDI Defect Condition” Interrupt. 1 – Enables the “Change in FERF/RDI Defect Condition” Interrupt. Note: 2 Change of AIC State Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Change in AIC State Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in AIC State” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to it detecting a change in the AIC bit-field, within the incoming DS3 data stream. 0 – Disables the “Change in AIC State” Interrupt. 1 – Enables the “Change in AIC State” Interrupt. Note: 1 Change of OOF Defect Condition Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Change in OOF Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in OOF (Out of Frame) Defect Condition” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. • The instant that the Primary Frame Synchronizer block declares the OOF defect condition. 441 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 • The instant that the Primary Frame Synchronizer block clears the OOF defect condition. 0 – Disables the “Change in OOF Defect Condition” Interrupt. 1 – Enables the “Change in OOF Defect Condition” Interrupt. Note: 0 Detection of PBit Error Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Detection of P-Bit Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of P-Bit Error” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt anytime it detects P bit errors. 0 – Disables the “Detection of P Bit Error” Interrupt. 1 – Enables the “Detection of P-Bit Error” Interrupt. Note: This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. 442 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 300: RxDS3 Interrupt Status Register (Address Location= 0xN313, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Detection of CP Bit Error Interrupt Status Change of LOS Defect Condition Interrupt Status Change of AIS Defect Condition Interrupt Status Change of DS3 Idle Condition Interrupt Status Change of FERF/RDI Condition Interrupt Status Change of AIC State Interrupt Status Change of OOF Defect Condition Interrupt Status Detection of P-Bit Error Interrupt Status RUR RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7 Detection of CP Bit Error Interrupt Status RUR Detection of CP-Bit Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of CP-Bit Error” Interrupt has occurred since the last read of this register. 0 – The “Detection of CP-Bit Error” Interrupt has not occurred since the last read of this register. 1 – The “Detection of CP-Bit Error” Interrupt has occurred since the last read of this register. Note: 6 Change of LOS Defect Condition Interrupt Status RUR This bit-field is only active if the DS3/E3 Framer block has been configured to operae in the DS3, C-bit Parity Framing Format. This bit field is also ignored if the Primary Frame Synchronizer block is by-passed. Change in LOS Defect Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the “Change in LOS Defect Condition” Interrupt has occurred since the last read of this register. 0 – The “Change in LOS Defect Condition” Interrupt has not occurred since the last read of this register. 1 – The “Change in LOS Defect Condition” Interrupt has occurred since the last read of this register. Note: 5 Change of AIS Defect Condition Interrupt Status RUR This bit-field is ignored if the Primary Frame Synchronizer block is by-passed. Change in AIS Defect Condition Interrupt Status This RESET-upon-READ register indicates whether or not the “Change in AIS Defect Condition” Interrupt has occurred since the last read of this register. 0 – The “Change in AIS Defect Condition” Interrupt has not occurred since the last read of this register. 1 – The “Change in AIS Defect Condition” Interrupt has occurred since the last read of this register. Note: 4 Change of DS3 Idle Condition Interrupt Status RUR This bit-field is ignored if the Primary Frame Synchronizer block is by-passed. Change in DS3 Idle Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the “Change in DS3 Idle Condition” interrupt has occurred since the last read of this register. 0 – The “Change in DS3 Idle Condition” Interrupt has not occurred since the 443 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 last read of this register. 1 – The “Change in DS3 Idle Condition” Interrupt has occurred since the last read of this register. Note: 3 Change of FERF/RDI Defect Condition Interrupt Status RUR This bit-field is ignored if the Primary Frame Synchronizer block is by-passed. Change in FERF/RDI Defect Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the “Change in FERF/RDI Defect Condition” Interrupt has occurred since the last read of this register. 0 – The “Change in FERF/RDI Defect Condition” Interrupt has not occurred since the last read of this register. 1 – The “Change in FERF/RDI Defect Condition” Interrupt has occurred since the last read of this register. Note: 2 Change of AIC State Interrupt Status RUR This bit-field is ignored if the Primary Frame Synchronizer block is by-passed. Change in AIC State Interrupt Status: This RESET-upon-READ register bit indicates whether or not the “Change in AIC State” interrupt has occurred since the last read of this register. 0 – The “Change in AIC State” Interrupt has not occurred since the last read of this register. 1 – The “Change in AIC State” Interrupt has occurred since the last read of this register. Note: 1 Change of OOF Defect Condition Interrupt Status RUR This bit-field is ignored if the Primary Frame Synchronizer block is by-passed. Change in OOF Defect Condition Interrupt Status: This RESET-upon-READ register indicates whether or not the “Change in OOF Defect Condition” Interrupt has occurred since the last read of this register. 0 – The “Change in OOF Defect Condition” Interrupt has not occurred since the last read of this register. 1 – The “Change in OOF Defect Condition” Interrupt has occurred since the last read of this register. Note: 0 Detection of P-Bit Error Interrupt Status RUR This bit-field is ignored if the Primary Frame Synchronizer block is by-passed. Detection of P-Bit Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of P-Bit Error” Interrupt has occurred since the last read of this register. 0 – The “Detection of P-Bit Error” Interrupt has not occurred since the last read of this register. 1 – The “Detection of P-Bit Error” Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Primary Frame Synchronizer block is by-passed. 444 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 301: RxDS3 Sync Detect Register (Address Location= 0xN314, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 R/O R/O 0 0 BIT 5 BIT 4 BIT 3 R/O R/O R/O 0 0 0 Unused BIT NUMBER NAME TYPE 2 P-Bit Correct R/W BIT 2 BIT 1 BIT 0 P-Bit Correct F Algorithm One and Only R/W R/W R/W 0 0 0 DESCRIPTION P-Bit Correct: This READ/WRITE bit-field permits the user to enable or disable the “P-Bit Correct” feature within the Primary Frame Synchronizer block. If the user enables this feature, then the Primary Frame Synchronizer block will automatically invert the state of any P-bits, whenever it detects “P-bit errors” within the incoming DS3 data-stream. 0 – Disables the “P-Bit Correct” feature. 1 – Enables the “P-Bit Correct” feature 1 F Algorithm R/W F-Bit Search Algorithm Select: This READ/WRITE bit-field permits the user to select the “F-bit acquisition” criteria that the Primary Frame Synchronizer block will use whenever it is operating in the “F-Bit Search” state, as depicted below. 0 – Configures the Primary Frame Synchronizer block will move on to the “M-Bit Search” state, whenever it has properly located 10 consecutive Fbits within the incoming DS3 data-stream. 1 – Primary Frame Synchronizer block will move on to the “M-Bit Search” state, when it has properly located 16 consecutive F-bits within the incoming DS3 data-stream. NOTE: This bit-field is only active if the user has configured the DS3/E3 Framer block to operate in the DS3 Mode. 0 One and Only R/W F-Bit Search/Mimic-Handling Algorithm Select: This READ/WRITE bit-field permits the user to select the “F-bit acquisition” criteria that the Primary Frame Synchronizer block will use whenever it is operating in the “F-Bit Search” state. 0 – Configures the Primary Frame Synchronizer block to move on to the “M-Bit Search” state, when it has properly located 10 (or 16) consecutive Fbits (as configured in Bit 1 of this register). 1 – Configures the Primary Frame Synchronizer block to move on to the “M-Bit Search” state, when (1) it has properly located 10 (or 16) consecutive F-bits; and (2) when it has located and identified only one viable “F-Bit Alignment” candidate. Note: If this bit is set to “1”, then the Primary Frame Synchronizer block will NOT transition into the “M-Bit Search” state, as long as at least two viable candidate set of bits appear to function as the Fbits. 445 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 302: RxDS3 FEAC Register (Address Location= 0xN316, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 RxFEACCode[5:0] BIT 0 Unused R/O R/O R/O R/O R/O R/O R/O R/O 0 1 1 1 1 1 1 0 BIT NUMBER NAME TYPE 7 Unused R/O 6-1 RxFEAC_Code[5:0] R/O DESCRIPTION Receive FEAC Code Word: These READ-ONLY bit-fields contain the value of the most recently “validated” FEAC Code word. NOTE: These bit-fields are only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. 0 Unused R/O 446 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 303: RxDS3 FEAC Interrupt Enable/Status Register (Address Location= 0xN317, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FEAC Valid RxFEAC Remove Interrupt Enable RxFEAC Remove Interrupt Status RxFEAC Valid Interrupt Enable RxFEAC Valid Interrupt Status R/O R/O R/O R/O R/W RUR R/W RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE DESCRIPTION 7-5 Unused R/O Please set to “0” (the default value) for normal operation. 4 FEAC Valid R/O FEAC Message Validation Indicator: This READ-ONLY bit-field indicates that the FEAC Code (which resides within the “RxDS3 FEAC” Register) has been validated by the Receive FEAC Controller block. The Receive FEAC Controller block will validate a FEAC codeword if it has received this codeword in 8 out of the last 10 FEAC Messages. Polled systems can monitor this bit-field, when checking for a newly validated FEAC codeword. 0 – FEAC Message is not (or no longer) validated. 1 – FEAC Message has been validated. NOTE: This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. 3 RxFEAC Remove Interrupt Enable R/W FEAC Message Remove Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Receive FEAC Remove Interrupt”. If the user enables this interrupt, then the Primary Framer Synchronizer block will generate an interrupt anytime the most recently validated FEAC Message has been removed. The Receive FEAC Controller sub-block will remove a validated FEAC codeword, if it has received a different codeword in 3 out of the last 10 FEAC Messages. 0 – Receive FEAC Remove Interrupt is disabled. 1 – Receive FEAC Remove Interrupt is enabled. Note: 2 RxFEAC Remove Interrupt Status RUR This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. Further, this bit-field is ignored if the Primary Frame Synchronizer block is by-passed. FEAC Message Remove Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “FEAC Message Remove Interrupt” has occurred since the last read of this register. 0 – FEAC Message Remove Interrupt has NOT occurred since the last read of this register. 1 – FEAC Message Remove Interrupt has occurred since the last read of this register. NOTE: This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. 1 RxFEAC Valid Interrupt R/W FEAC Message Validation Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the 447 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Interrupt Enable Rev222...000...000 FEAC Message Validation Interrupt. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt anytime a new FEAC Codeword has been validated by the Receive FEAC Controller sub-block. 0 – FEAC Message Validation Interrupt is NOT enabled. 1 – FEAC Message Validation Interrupt is enabled. NOTE: This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. 0 RxFEAC Valid Interrupt Status RUR FEAC Message Validation Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “FEAC Message Validation” Interrupt has occurred since the last read of this register. 0 – FEAC Message Validation Interrupt has not occurred since the last read of this register. 1 – FEAC Message Validation Interrupt has occurred since the last read of this register. NOTE: This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. 448 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 304: RxDS3 LAPD Control Register (Address Location= 0xN318, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 RxLAPD Any BIT 4 BIT 3 Unused BIT 2 BIT 1 BIT 0 Receive LAPD Enable Receive LAPD Interrupt Enable Receive LAPD Interrupt Status R/W R/O R/O R/O R/O R/W R/W RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 RxLAPD Any R/W DESCRIPTION Receive LAPD – Any kind: This READ/WRITE bit-field permits the user to configure the Receive LAPD Controller sub-block (within the Primary Frame Synchronizer block) to receive any kind of LAPD Message (or HDLC Message) with a size of 82 bytes or less. If the user implements this option, then the Receive LAPD Controller sub-block will be capable of receiving any kind of HDLC Message (with any value of header bytes). The only restriction is that the size of the HDLC Message must not exceed 82 bytes. 0 – Does not invoke this “Any Kind of HDLC Message” feature. In this case, the Receive LAPD Controller sub-block will only receive HDLC Messages that contains the Bellcore GR-499-CORE values for SAPI and TEI. Invokes this “Any Kind of HDLC Message” feature. In this case, the Receive LAPD Controller sub-block will be able to receive HDLC Messages that contain any header byte values. Note: This bit-field is ignored if the Primary Frame Synchronizer block is by-passed. The user can determine the size (or byte-count) of the most recently received LAPD/PMDL Message, by reading the contents of the “RxLAPD Byte Count” Register (Address Location= 0xN384) 6–3 Unused R/O 2 Receive LAPD Enable R/W Receive LAPD Controller sub-block Enable: This READ/WRITE bit-field permits the user to either enable or disable the Receive LAPD Controller sub-block within the Primary Frame Synchronizer block. If the user enables the Receive LAPD Controller sub-block, then it will immediately begin extracting out and monitoring the data (being carried via the “DL” bits) within the incoming DS3 data stream. 0 – Enables the Receive LAPD Controller sub-block. 1 – Disables the Receive LAPD Controller sub-block. Note: 1 Receive LAPD Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Receive LAPD Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Receive LAPD Message” Interrupt. If the user enables this interrupt, then the channel will generate an interrupt, anytime the Receive LAPD Controller subblock receives a new PMDL Message. 0 – Disables the “Receive LAPD Message” Interrupt. 1 – Enables the “Receive LAPD Message” Interrupt. 449 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Note: 0 Receive LAPD Interrupt Status RUR Rev222...000...000 This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Receive LAPD Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Receive LAPD Message” Interrupt has occurred since the last read of this register. 0 – “Receive LAPD Message” Interrupt has NOT occurred since the last read of this register. 1 – “Receive LAPD Message” Interrupt has occurred since the last read of this register. Note: This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. 450 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 305: RxDS3 LAPD Status Register (Address Location= 0xN319, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused RxABORT RxLAPDType[1:0] RxCR Type RxFCS Error End of Message Flag Present R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 RxABORT R/O DESCRIPTION Receive ABORT Sequence Indicator: This READ-ONLY bit-field indicates that the Receive LAPD Controller sub-block has received an ABORT sequence (e.g., a string of seven consecutive “0s”). 0 – Indicates that the Receive LAPD Controller sub-block has NOT received an ABORT sequence. 1 - Indicates that the Receive LAPD Controller sub-block has received an ABORT sequence. Note: 5–4 RxLAPDType[1:0] R/O Once the Receive LAPD Controller sub-block receives an ABORT sequence, it will set this bit-field “high”, until it receives another LAPD Messages. Receive LAPD Message Type Indicator: These two READ-ONLY bits indicate the type of LAPD Message that is residing within the Receive LAPD Message buffer. The relationship between the content of these two bit-fields and the corresponding message type is presented below. 3 RxCR Type R/O RxLAPDType[1:0] Message Type 0 0 CL Path Identification 0 1 Idle Signal Identification 1 0 Test Signal Identification 1 1 ITU-T Path Identification Received C/R Value: This READ-ONLY bit-field indicates the value of the C/R bit (within one of the header bytes) of the most recently received LAPD Message. NOTE: This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. 2 RxFCS Error R/O Receive Frame Check Sequence (FCS) Error Indicator: This READ-ONLY bit-field indicates whether or not the most recently received LAPD Message frame contained an FCS error. 0 – The most recently received LAPD Message frame does not contain an FCS error. 1 – The most recently received LAPD Message frame does contain an 451 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 FCS error. NOTE: This bit-field is only active if the DS3/E3 Framer block has been configured to operate in the DS3, C-bit Parity Framing format. 1 End of Message R/O End of Message Indicator This READ-ONLY bit-field indicates whether or not the Receive LAPD Controller sub-block has received a complete LAPD Message, as described below. 0 – The Receive LAPD Controller sub-block is currently receiving a LAPD Message, but has not received the complete message. 1 – The Receive LAPD Controller sub-block has received a completed LAPD Message. Note: 0 Flag Present R/O Once the Receive LAPD Controller sub-block sets this bit-field “high”, this bit-field will remain high, until the Receive LAPD Controller sub-block begins to receive a new LAPD Message. Receive Flag Sequence Indicator: This READ-ONLY bit-field indicates whether or not the Receive LAPD Controller sub-block is currently receiving the Flag Sequence (e.g., a continuous stream of 0x7E octets within the Data Link channel), as described below. 0 – Indicates that the Receive LAPD Controller sub-block is NOT currently receiving the Flag Sequence octet. 1 – Indicates that the Receive LAPD Controller sub-block is currently receiving the Flag Sequence octet. 452 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 306: RxDS3 Pattern Register (Address Location= 0xN32F, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 DS3 AIS Unframed All Ones DS3 AIS Non Stuck Stuff Unused Receive LOS Pattern R/W R/W R/O R/W R/W R/W R/W R/W 0 0 0 0 1 1 0 0 BIT NUMBER NAME TYPE 7 DS3 AIS Unframed All Ones R/W BIT 3 BIT 2 BIT 1 BIT 0 Receive DS3 Idle Pattern[3:0] DESCRIPTION DS3 AIS - Unframed All Ones – AIS Pattern This READ/WRITE bit-field, (along with the “Non-Stuck-Stuff” bit) permits the user specify the “AIS Declaration” criteria for the Primary Frame Synchronizer block, as described below. 0 – Configures the Primary Frame Synchronizer block to declare the AIS defect condition, when receiving a DS3 signal carrying a “framed 1010..” pattern. 1 – Configures the Primary Frame Synchronizer block to declare the AIS defect condition, when receiving either an unframed, All Ones pattern or a “framed 1010..” pattern. 6 DS3 AIS Non-Stuck Stuff R/W DS3 AIS - Non-Stuck-Stuff Option – AIS Pattern This READ/WRITE bit-field (along with the “Unframed All Ones – AIS Pattern bit-field) permits the user to define the “AIS Defect Declaration” criteria for the Primary Frame Synchronizer block, as described below. 0 – Configures the Primary Frame Synchronizer block to require that all “C” bits are set to “0” before it will declare the AIS defect condition. 1 – Configures the Primary Frame Synchronizer block to NOT require that all “C” bits are set to “0” before it will declare the AIS defect condition. In this mode, no attention will be paid to the state of the “C” bits within the incoming DS3 data-stream. 5 Unused R/O 4 Receive LOS Pattern R/W Receive LOS Pattern: This READ/WRITE bit-field permits the user to define the “LOS Defect Declaration” criteria for the Primary Frame Synchronizer block, as described below. 0 – Configures the Primary Frame Synchronizer block to declare the LOS defect condition if it receives a string of a specific length of consecutive zeros. 1 – Configures the Primary Frame Synchronizer block to declare the LOS defect condition if it receives a string (of a specific length) of consecutive ones. NOTE: This bit-field is only enabled if the “Internal LOS Enable” feature has been enabled within the Primary Frame Synchronizer block. 3–0 Receive DS3 Idle Pattern[3:0] R/W Receive DS3 Idle Pattern: These READ/WRITE bit-fields permit the user to specify the pattern in which the Primary Frame Synchronizer will recognize as the “DS3 Idle Pattern”. Note: The Bellcore GR-499-CORE specified value for the Idle Pattern is a framed repeating “1, 1, 0, 0…” pattern. Therefore, if the user wishes to configure the “Primary Frame Synchronizer” to declare 453 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 an “Idle Pattern” when it receives this pattern, then he/she write the value [1100] into these bit-fields. 454 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 1.10.3 RECEIVE E3, ITU-T G.751 RELATED REGISTERS Table 307: RxE3 Configuration and Status Register # 1 - G.751 (Address Location= 0xN310, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 RxFERF Algo BIT 2 BIT 1 Unused BIT 0 RxBIP-4 Enable R/O R/O R/O R/W R/O R/O R/O R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–5 Unused R/O 4 RxFERF Algo R/W DESCRIPTION Receive FERF Algorithm Select: This READ/WRITE bit-field permits the user to select the “FERF Declaration” and “Clearance” criteria that will be used by the Primary Frame Synchronizer block. 0 – The Primary Frame Synchronizer block declares the FERF/RDI defect condition if the “A” bit-field (within the incoming E3 data-stream) is set to “1” for 3 consecutive frames. The Primary Frame Synchronizer block will clear the FERF/RDI defect condition if the “A” bit-field is set to “0” for 3 consecutive frames. 1 – The Primary Frame Synchronizer block declares the FERF/RDI defect condition if the “A” bit-field (within the incoming E3 data-stream) is set to “1” for 5 consecutive frames. The Primary Frame Synchonizer block will clear the FERF/RDI defect condition if the “A” bit-field is set to “0” for 5 consecutive frames. NOTE: This bit-field is only valid if the DS3/E3 Framer block has been configured to operate in the E3, ITU-T G.751 Framing format. 3–1 Unused R/O 0 RxBIP4 Enable R/W Enable BIP-4 Verification: This READ/WRITE bit-field permits the user to configure the Primary Frame Synchronizer block to compute and verify the BIP-4 value, within the incoming E3 data-stream. 0 – BIP-4 Verification is NOT performed. 1 – BIP-4 Verification is performed. 455 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 308: RxE3 Configuration and Status Register # 2 - G.751 (Address Location= 0xN311, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RxLOF Algo LOF Defect Condition Declared OOF Defect Condition Declared LOS Defect Condition Declared AIS Defect Condition Declared R/W R/O R/O R/O R/O R/O R/O R/O 0 1 1 0 0 0 0 1 FERF/RDI Defect Condition Declared Unused BIT NUMBER NAME TYPE DESCRIPTION 7 RxLOF Algo R/W Receive LOF (Loss of Frame) Defect Declaration/Clearance Criteria Select: This READ/WRITE bit-field permits the user to select the Loss of Frame (LOF) Declaration and Clearance Criteria that the Primary Frame Synchronizer block will use. 0 – The Primary Frame Synchronizer block will declare the LOF defect condition if the Primary Frame Synchronizer block resides within the OOF (Out-of-Frame) state for 24 E3 frame periods. The Primary Frame Synchronizer block will clear the LOF defect condition once it (the Primary Frame Synchronizer block) resides within the “In-Frame” state for 24 E3 frame period. 1 – The Primary Frame Synchronizer block will declare the LOF defect condition if the Primary Frame Synchronizer block resides within the OOF state for 8 E3 frame periods. The Primary Frame Synchronizer block will clear the LOF defect condition once it (the Primary Frame Synchronizer block) resides within the “In-Frame” state for 8 E3 frame periods. 6 LOF Defect Condition Declared R/O LOF (Loss of Frame) Defect Declared Indicator This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the LOF defect condition, as described below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the LOF defect condition within the incoming data stream. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the LOF defect condition within the incoming data stream. Note: 5 OOF Defect Condition Declared R/O This bit-field is not valid if the Primary Frame Synchronizer block is by-passed. OOF (Out of Frame) Defect Condition Indicator This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the OOF defect condition, as depicted below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the OOF defect condition with the incoming data stream. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the OOF defect condition with the incoming data stream. Note: 4 LOS Defect Condition Declared R/O This bit-field is not valid if the Primary Frame Synchronizer block is by-passed. LOS (Loss of Signal) Defect Condition Indicator This READ-ONLY bit-field indicates whether or not the Primary Frame 456 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Declared Synchronizer block is currently declaring the LOS defect condition, as described below. 0 – Indicates that the Primary Frame Synchronizer/Channel is NOT currently declaring the LOS defect condition in the incoming data stream. 1 – Indicates that the Primary Frame Synchronizer/Channel is currently declaring the LOS defect condition in the incoming data stream. 3 AIS Defect Condition Declared R/O AIS Defect Condition Indicator: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the AIS defect condition within the incoming E3 data-stream, as described below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the AIS defect condition with the incoming data stream. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the AIS defect condition with the incoming data stream. Note: 2–1 Unused R/O 0 FERF/RDI Defect Condition Declared R/O This bit-field is not valid if the Primary Frame Synchronizer block is by-passed. FERF/RDI (Far-End-Receive Failure/Remote Defect Indicator) Defect Condition Indicator: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the FERF/RDI defect condition as described below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the FERF/RDI defect condition. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the FERF/RDI defect condition. Note: This bit-field is ignored if the Primary Frame Synchronizer block is bypassed or if the user has configured the Primary Frame Synchronizer block to compute and verify the BIP-4 within the incoming E3 data-stream. 457 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 309: RxE3 Interrupt Enable Register # 1 – G.751 (Address Location= 0xN312, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COFA Interrupt Enable Change in OOF Defect Condition Interrupt Enable Change in LOF Defect Condition Interrupt Enable Change in LOS Defect Condition Interrupt Enable Change in AIS Defect Condition Interrupt Enable R/O R/O R/O R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-5 Unused R/O 4 COFA Interrupt Enable R/W DESCRIPTION Change of Framing Alignment Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of Framing Alignment” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt anytime it detects a Change in Frame Alignment (e.g., the FAS bits have appeared to move to a different location in the E3 data stream). 0 – Disables the “Change of Framing Alignment” Interrupt 1 – Enables the “Change of Framing Alignment” Interrupt 3 Change in OOF Defect Condition Interrupt Enable R/W Change in OOF Defect Condition Interrupt Enable This READ/WRITE bit-field permits the user to either enable or disable the “Change in OOF (Out of Frame) Defect Condition” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. • The instant that the Primary Frame Synchronizer block declares the OOF defect condition. • The instant that the Primary Frame Synchronizer block clears the OOF defect condition. 0 – Disables the “Change in OOF Defect Condition” Interrupt. 1 – Enables the “Change in OOF Defect Condition” Interrupt. Note: 2 Change in LOF Defect Condition Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Change in LOF Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in LOF (Loss of Frame) Defect Condition” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. • The instant that the Primary Frame Synchronizer block declares the LOF defect condition. • The instant that the Primary Frame Synchronizer block clears the LOF defect condition. 0 – Disables the “Change in LOF Defect Condition” Interrupt. 1 – Enables the “Change in LOF Defect Condition” Interrupt. 458 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Note: 1 Change in LOS Defect Condition Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Change in LOS Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in LOS (Loss of Signal) Defect Condition” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. • The instant that the Primary Frame Synchronizer block declares an LOS defect condition. • The instant that the Primary Frame Synchronizer block clears the LOS defect condition. 0 – Disables the “Change in LOS Defect Condition” Interrupt. 1 – Enables the “Change in LOS Defect Condition” Interrupt. 0 Change in AIS Defect Condition Interrupt Enable R/W Change in AIS Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in AIS (Alarm Indication Signal) Defect Condition” Interrupt, within the Channel. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following conditions. • The instant that the Primary Frame Synchronizer block declares the AIS defect condition. • The instant that the Primary Frame Synchronizer block clears the AIS defect condition. The “Change in AIS Defect Condition” Interrupt can be enabled or disabled, as described below. 0 – Disables the “Change in AIS Defect Condition” Interrupt. 1 – Enables the “Change in AIS Defect Condition” Interrupt. Note: This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. 459 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 310: RxE3 Interrupt Enable Register # 2 – G.751 (Address Location= 0xN313, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 Change in FERF/RDI Defect Condition Interrupt Enable Detection of BIP-4 Error Interrupt Enable Detection of FAS Bit Error Interrupt Enable Reserved R/O R/O R/O R/O R/W R/W R/W R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-4 Unused R/O Please set to “0” (the default value) for normal operation 3 Change in FERF/RDI Defect Condition Interrupt Enable R/W Change in FERF/RDI Defect Condition Interrupt Enable: DESCRIPTION This READ/WRITE bit-field permits the user to either enable or disable the “Change in FERF/RDI Defect Condition” Interrupt. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt in response to either of the following events. • Whenever the Primary Frame Synchronizer block declares the FERF/RDI Defect condition. • Whenever the Primary Frame Synchronizer block clears the FERF/RDI Defect condition. The user can enable or disable this particular interrupt as described below. 0 – Disables the “Change in FERF/RDI Defect Condition” Interrupt. 1 – Enables the “Change in FERF/RDI Defect Condition” Interrupt. Note: 2 Detection of BIP-4 Error Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is configured to verify BIP-4 values within each incoming E3 frame. Further, this bit-field is ignored anytime the Primary Frame Synchronizer block is by-passed. Detection of BIP-4 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of BIP-4 Error” Interrupt. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt anytime it detects a BIP-4 error, within the incoming E3 data stream. The user can enable or disable this interrupt as described below. 0 – Disables the “Detection of BIP-4 Error” Interrupt. 1 – Enables the “Detection of BIP-4 Error” Interrupt. Note: 1 Detection of FAS Bit Error Interrupt Enable R/W This bit-field is only active if the Receive E3 Framer block has been configured to compute and verify the BIP-4 values within each incoming E3 frame. This bit-field is ignored anytime the Primary Frame Synchronizer block is by-passed. Detection of FAS (Framing Alignment Signal) Bit Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “FAS Bit Error” Interrupt. If the user enables this interrupt, then the Primary Frame Synchronizer block will generate an interrupt anytime it detects an FAS error within the incoming E3 data stream. 460 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 0 – Disables the “Detection of FAS Bit Error” Interrupt. 1 – Enables the “Detection of FAS Bit Error” Interrrupt. Note: 0 Unused R/O This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Please set to “0” (the default value) for normal operation. 461 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 311: RxE3 Interrupt Status Register # 1 – G.751 (Address Location= 0xN314, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 Unused BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COFA Interrupt Status Change in OOF Defect Condition Interrupt Status Change in LOF Defect Condition Interrupt Status Change in LOS Defect Condition Interrupt Status Change in AIS Defect Condition Interrupt Status R/O R/O R/O RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-5 Unused R/O 4 COFA Interrupt Status RUR DESCRIPTION Change of Framing Alignment (COFA) Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of Framing Alignment (COFA) interrupt has occurred since the last read of this register. 0 – The “COFA” Interrupt has NOT occurred since the last read of this register. 1 – The “COFA” Interrupt has occurred since the last read of this register. 3 Change in OOF Defect Condition Interrupt Status RUR Change of OOF (Out of Frame) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of OOF Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt in response to either of the following condition. • Whenever the Primary Frame Synchronizer block declares the OOF Defect Condition. • Whenever the Primary Frame Synchronizer block clears the OOF Defect Condition. 0 – Indicates that the “Change in OOF Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in OOF Defect Condition” Interrupt has occurred since the last read of this register. Note: 2 Change in LOF Defect Condition Interrupt Status RUR The user can obtain the current state of the OOF Defect condition within the DS3/E3 Framer block by reading out the state of Bit 5 (OOF Defect Declared) within the “RxE3 Configuration and Status # 2 – G.751” (Address Location= 0xN311). Change of LOF (Loss of Frame) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of LOF Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt in response to either of the following condition. • Whenever the Primary Frame Synchronizer block declares the LOF Defect Condition. • Whenever the Primary Frame Synchronizer block clears the LOF Defect Condition. 0 – Indicates that the “Change in LOF Defect Condition” Interrupt has NOT 462 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 occurred since the last read of this register. 1 – Indicates that the “Change in LOF Defect Condition” Interrupt has occurred since the last read of this register. Note: 1 Change in LOS Defect Condition Interrupt Status RUR The user can obtain the current state of the LOF defect condition within the DS3/E3 Framer block by reading out the state of Bit 6 (LOF Defect Declared) within the “RxE3 Configuration and Status # 2 – G.751” (Address Location= 0xN311). Change of LOS (Loss of Signal) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of LOS Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt in response to either of the following condition. • Whenever the Primary Frame Synchronizer block declares the LOS Defect Condition. • Whenever the Primary Frame Synchronizer block clears the LOS Condition. 0 – Indicates that the “Change of LOS Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of LOS Defect Condition” Interrupt has occurred since the last read of this register. Note: 0 Change in AIS Defect Condition Interrupt Status RUR The user can obtain the current state of the LOS Defect Condition within the DS3/E3 Framer block by reading out the state of Bit 4 (LOS Defect Declared) within the “RxE3 Configuration and Status # 2 – G.751” (Address Location= 0xN311). Change of AIS Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of AIS Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the DS3/E3 Framer block will generate an interrupt in response to either of the following condition. • Whenever the Primary Frame Synchronizer block declares the AIS Defect Condition. • Whenever the Primary Frame Synchronizer block clears the AIS Defect Condition. 0 – Indicates that the “Change of AIS Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change of AIS Defect Condition” Interrupt has occurred since the last read of this register. Note: The user can obtain the current state of the AIS defect condition within the DS3/E3 Framer block by reading out the state of Bit 3 (AIS Defect Declared) within the “RxE3 Configuration and Status # 2 – G.751” (Address Location= 0xN311). 463 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 312: RxE3 Interrupt Status Register # 2 – G.751 (Address Location= 0xN315, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 Unused BIT 3 BIT 2 BIT 1 BIT 0 Change of FERF/RDI Defect Condition Interrupt Status Detection of BIP-4 Error Interrupt Status Detection of FAS Bit Error Interrupt Status Reserved R/O R/O R/O R/O RUR RUR RUR R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7–4 Unused R/O 3 Change of FERF/RDI Defect Condition Interrupt Status RUR DESCRIPTION Change of FERF/RDI Defect Condition Interrupt – Primary Frame Synchronizer block: This RESET-upon-READ bit-field indicates whether or not the “Change in FERF/RDI Condition” interrupt has occurred since the last read of this register. The Primary Frame Synchronizer block will generate this interrupt in response to either of the following events. • Whenever the Primary Frame Synchronizer block declares the FERF/RDI Defect condition. • Whenever the Primary Frame Synchronizer block clears the FERF/RDI Defect condition. 0 – Indicates that the “Change in FERF/RDI Defect Condition” interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in FERF/RDI Defect Condition” interrupt has occurred since the last read of this register. 2 Detection of BIP-4 Error Interrupt Status RUR Detection of BIP-4 Error Interrupt – Primary Frame Synchronizer block: This “RESET-upon-READ” bit-field indicates whether or not the “Detection of BIP-4 Error” interrupt has occurred since the last read of this register. The Primary Frame Synchronizer block will generate this interrupt anytime it detects BIP-4 errors within the incoming E3 data-stream. 0 – Indicates that the “Detection of BIP-4 Error” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of BIP-4 Error” Interrupt has occurred since the last read of this register. 1 Detection of FAS Bit Error Interrupt Status RUR Detection of FAS Bit Error Interrupt – Primary Frame Synchronizer block: This “RESET-upon-READ” bit-field indicates whether or not the “Detection of FAS Bit Error” interrupt has occurred since the last read of this register. The Primary Frame Synchronizer block will generate this interrupt anytime it detects FAS bit errors within the incoming E3 data-stream. 0 – Indicates that the “Detection of FAS Bit Error” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of FAS Bit Error” Interrupt has occurred 464 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 since the last read of this register. 0 Unused R/O 465 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 313: RxE3 LAPD Control Register – G.751 (Address Location= 0xN318, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 RxLAPD Any Message Check Disable R/W R/W R/O R/O 0 0 0 0 BIT NUMBER NAME TYPE 7 RxLAPD Any R/W BIT 3 BIT 2 BIT 1 BIT 0 Receive LAPD Enable Receive LAPD Interrupt Enable Receive LAPD Interrupt Status R/O R/W R/W RUR 0 0 0 0 Unused DESCRIPTION Receive LAPD – Any kind: This READ/WRITE bit-field permits the user to configure the Receive LAPD Controller sub-block to receive any kind of LAPD Message (or HDLC Message) with a size of 82 bytes or less. If the user implements this option, then the Receive LAPD Controller sub-block will be capable of receiving any kind of HDLC Message (with any value of header bytes). The only restriction is that the size of the HDLC Message must not exceed 82 bytes. 0 – Does not invoke this “Any Kind of HDLC Message” feature. In this case, the Receive LAPD Controller sub-block will only receive HDLC Messages that contains the Bellcore GR-499-CORE values for SAPI and TEI. 1 - Invokes this “Any Kind of HDLC Message” feature. In this case, the Receive LAPD Controller sub-block will be able to receive HDLC Messages that contain any header byte values. Note: This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. The user can determine the size (or byte count) of the most recently received LAPD/PMDL Message, by reading the contents of the “Receive LAPD Byte Count” Register (Address Location= 0xN384). 6 Message Check Disable R/W Message Check Disable: This READ/WRITE bit-field permits the user to either enable or disable the new message comparison logic. If the user disables the new message comparison logic, then every message received would generate an interrupt. 0 – Enables the new message comparison logic 1 – Disables the new message comparison logic 5–3 Unused R/O 2 Receive LAPD Enable R/W Receive LAPD Controller Sub-Block Enable: This READ/WRITE bit-field permits the user to either enable or disable the Receive LAPD Controller sub-block within the channel. If the user enables the Receive LAPD Controller sub-block, then it will immediately begin extracting out and monitoring the data (being carried via the “N” bits) within the incoming E3 data stream. 0 – Enables the Receive LAPD Controller sub-block. 1 – Disables the Receive LAPD Controller sub-block. Note: 1 Receive LAPD Interrupt R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Receive LAPD Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “R i LAPD M ”I t t If th bl thi i t t th th 466 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Enable “Receive LAPD Message” Interrupt. If the user enables this interrupt, then the channel will generate an interrupt, anytime the Receive LAPD Controller subblock receives a new PMDL Message. 0 – Disables the “Receive LAPD Message” Interrupt. 1 – Enables the “Receive LAPD Message” Interrupt. Note: 0 Receive LAPD Interrupt Status RUR This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Receive LAPD Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Receive LAPD Message” Interrupt has occurred since the last read of this register. 0 – “Receive LAPD Message” Interrupt has NOT occurred since the last read of this register. 1 – “Receive LAPD Message” Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. 467 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 314: RxE3 LAPD Status Register – G.751 (Address Location= 0xN319, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused RxABORT RxLAPDType[1:0] RxCR Type RxFCS Error End of Message Flag Present R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 RxABORT R/O DESCRIPTION Receive ABORT Sequence Indicator: This READ-ONLY bit-field indicates whether or not the Receive LAPD Controller sub-block has received an ABORT sequence (e.g., a string of seven consecutive “0s”), as described below. 0 – Indicates that the Receive LAPD Controller sub-block has NOT received an ABORT sequence. 1 – Indicates that the Receive LAPD Controller sub-block has received an ABORT sequence. Note: 5–4 RxLAPDType[1:0] R/O Once the Receive LAPD Controlller sub-block receives an ABORT sequence, it will set this bit-field “high”, until it receives another LAPD Messages. Receive LAPD Message Type Indicator: These two READ-ONLY bits indicate the type of LAPD Message that is residing within the Receive LAPD Message buffer. The relationship between the content of these two bit-fields and the corresponding message type is presented below. RxLAPDType[1:0] 3 RxCR Type R/O Message Type 0 0 CL Path Identification 0 1 Idle Signal Identification 1 0 Test Signal Identification 1 1 ITU-T Path Identification Received C/R Value: This READ-ONLY bit-field indicates the value of the C/R bit (within one of the header bytes) of the most recently received LAPD Message. 2 RxFCS Error R/O Receive Frame Check Sequence (FCS) Error Indicator: This READ-ONLY bit-field indicates whether or not the most recently received LAPD Message frame contained an FCS error. 0 – Indicates that the most recently received LAPD Message frame does not contain an FCS error. 1 – Indicates that the most recently received LAPD Message frame does contain an FCS error. 1 End of Message R/O End of Message Indicator 468 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 This READ-ONLY bit-field indicates whether or not the Receive LAPD Controller sub-block has received a complete LAPD Message, as described below. 0 – Indicates that the Receive LAPD Controller sub-block is currently receiving a LAPD Message, but has not received the complete message. 1 – Indicates that the Receive LAPD Controller sub-block has received a completed LAPD Message. Note: 0 Flag Present R/O Once the Receive LAPD Controller sub-block sets this bit-field “high”, this bit-field will remain high, until the Receive LAPD Controller sub-block begins to receive a new LAPD Message. Receive Flag Sequence Indicator: This READ-ONLY bit-field indicates whether or not the Receive LAPD Controller sub-block is currently receiving the Flag Sequence (e.g., a continuous stream of 0x7E octets within the Data Link channel) as described below. 0 – Indicates that the Receive LAPD Controller sub-block is NOT currently receiving the Flag Sequence octet. 1 – Indicates that the Receive LAPD Controller sub-block is currently receiving the Flag Sequence octet. Table 315: RxE3 Service Bits Register – G.751 (Address Location= 0xN31A, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Unused BIT 1 BIT 0 RxA RxN R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-2 Unused R/O 1 RxA R/O DESCRIPTION Received A Bit Value: This READ-ONLY bit-field reflects the value of the “A” bit, within the most recently received E3 frame. NOTE: This register bit pertains to the “A” bit that has been received by the Primary Frame Synchronizer block. 0 RxN R/O Received N Bit Value: This READ-ONLY bit-field reflects the value of the “N” bit, within the most recently received E3 frames. NOTE: This register bit pertains to the “N” bit that has been received by the Primary Frame Synchronizer block. 469 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 1.10.4 Rev222...000...000 RECEIVE E3, ITU-T G.832 RELATED REGISTERS Table 316: RxE3 Configuration and Status Register # 1 – G.832 (Address Location= 0xN310, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 RxPLDType[2:0] BIT 4 BIT 3 RxFERF Algo. RxTMark Algo BIT 2 BIT 1 BIT 0 RxPLDTypeExp[2:0] R/O R/O R/O R/W R/W R/W R/W R/W 0 1 0 0 0 0 1 0 BIT NUMBER NAME TYPE 7-5 RxPLDType[2:0] R/O DESCRIPTION Received PLD (Payload) Type[2:0]: These three READ-ONLY bit-fields reflect the value of the Payload Type bits, within the MA byte of the most recently received E3 frame. 4 RxFERF Algo R/W Receive FERF/RDI Defect Declaration/Clearance Algorithm: This READ/WRITE bit-field permits the user to select a “FERF/RDI Defect Declaration and Clearance” Algorithm, as indicated below. 0 – Configures the Primary Frame Synchronizer block to declare the FERF/RDI defect condition anytime that it receives the FERF/RDI indicator in 3 consecutive E3 frames. Additionally, this same setting will also configure the Primary Frame Synchronizer block to clear the FERF/RDI defect condition if it no longer receives the FERF/RDI indicator (within the E3 data-stream) for 3 consecutive E3 frames. 1 – Configures the Primary Frame Synchronizer block to declare the FERF/RDI defect condition anytime it receives the FERF/RDI indicator (within the incoming E3 data-stream) in 5 consecutive E3 frames. Additionally, this same seting will also configure the Primary Frame Synchronizer block to clear the FERF/RDI defect condition anytime it ceases to receive the FERF/RDI indicator for 5 consecutive E3 frames. 3 RxTMark Algo R/W Receive Timing Marker Validation Algorithm: This READ/WRITE bit-field permits the user to select the “Receive Timing Marker Validation” algorithm, as indicated below. 0 – The Timing Marker will be validated if it is of the same state for three (3) consecutive E3 frames. 1 – The Timing Marker will be validated if it is of the same state for five (5) consecutive E3 frames. 2-0 RxPLDTypExp[2:0] R/W Receive PLD (Payload) Type – Expected: This READ/WRITE bit-field permits the user to specify the “expected value” for the Payload Type, within the MA bytes of each incoming E3 frame. If the Primary Frame Synchronizer block receives a Payload Type that differs then what has been written into these register bits, then it will generate the “Payload Type Mismatch” Interrupt. 470 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 317: RxE3 Configuration and Status Register # 2 – G.832 (Address Location= 0xN311, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RxLOF Algo LOF Defect Condition Declared - Primary Frame Synchronizer Block OOF Defect Condition Declared – Primary Frame Synchronizer Block LOS Defect Condition Declared – Primary Frame Synchronizer Block AIS Defect Condition Declared – Primary Frame Synchronizer Block RxPLD Unstab RxTMark FERF/RDI Defect Condition Declared – Primary Frame Synchronizer Block R/W R/O R/O R/O R/O R/O R/O R/O 0 1 1 0 0 1 1 1 BIT NUMBER NAME TYPE 7 RxLOF Algo R/W DESCRIPTION Receive LOF (Loss of Frame) Defect Declaration Algorithm: This READ/WRITE bit-field permits the user to select a “Receive LOF Defect Declaration” Algorithm, as indicated below. 0 – Configures the Primary Frame Synchronizer block to declare the LOF defect condition after it has resided within the “OOF” (Out of Frame) condition for 24 E3 frame periods. 1 – Configures the Primary Frame Synchronizer block to declare the LOF defect condition after it has resided within the “OOF” condition for 8 E3 frame periods. 6 LOF Defect Condition Declared R/O LOF (Loss of Frame) Defect Condition Indicator – Primary Frame Synchronizer Block: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the LOF defect condition, as indicated below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the LOF defect condition. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the LOF defect condition. 5 OOF Defect Condition Declared R/O OOF (Out of Frame) Defect Condition Indicator – Primary Frame Synchronizer Block: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer is currently declaring an Out of Frame (OOF) defect condition, as indicated below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the OOF defect condition. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the OOF defect condition. Note: 4 LOS Detect Condition Declared R/O The Primary Frame Synchronizer block will declare the “OOF” defect condition anytime it detects FA1 or FA2 byte errors within four (4) consecutive “incoming” E3 frames. LOS (Loss of Signal) Defect Condition Indicator – Primary Frame Synchronizer Block: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the LOS (Loss of Signal) defect 471 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 condition, as indicated below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the LOS defect condition. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the LOS defect condition. 3 AIS Defect Condition Declared R/O AIS Defect Condition Indicator – Primary Frame Synchronizer Block: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the AIS defect condition within the incoming E3 data stream; as indicated below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the AIS defect condition within the incoming E3 data stream. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the AIS defect condition within the incoming E3 data stream. Note: 2 RxPLD Unstab R/O The Primary Frame Synchronizer block will declare an “AIS” condition if it detects 7 or less “0s” within two consecutive “incoming” E3 frames. Receive Payload-Type Unstable Indicator: This READ-ONLY bit-field indicates whether or not the Payload Type (within the MA bytes of each incoming E3 frame) has been consistent in the last 5 frames, as indicated below. 0 – The Payload Type value has been consistent for at least 5 consecutive E3 frames. 1 – The Payload Type value has NOT been consistence for the last 5 E3 frames. 1 RxTMark R/O Received (Validated) Timing Marker: This READ-ONLY bit-field indicates the value of the most recently validated “Timing Marker”. 0 FERF/RDI Defect Condition Declared R/O FERF/RDI (Far-End-Receive Failure) Defect Condition Indicator – Primary Frame Synchronizer block: This READ-ONLY bit-field indicates whether or not the Primary Frame Synchronizer block is currently declaring the FERF/RDI defect condition, as indicated below. 0 – Indicates that the Primary Frame Synchronizer block is NOT currently declaring the FERF/RDI defect condition. 1 – Indicates that the Primary Frame Synchronizer block is currently declaring the FERF/RDI condition. 472 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 318: RxE3 Interrupt Enable Register # 1 – G.832 (Address Location= 0xN312, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Change in SSM MSG Interrupt Enable Change in SSM OOS Interrupt Enable COFA Interrupt Enable Change in OOF Defect Condition Interrupt Enable Change in LOF Defect Condition Interrupt Enable Change in LOS Defect Condition Interrupt Enable Change in AIS Defect Condition Interrupt Enable R/O R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Change in SSM MSG Interrupt Enable R/W DESCRIPTION Change of Synchronization Status Message (SSM) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in SSM Message” Interrupt, as indicated below. 0 – Disables the “Change in SSM Message” Interrupt. 1 – Enables the “Change of SSM Message” Interrupt. In this configuration, the Primary Frame Synchronizer block will generate an interrupt anytime it receives a new (or different) SSM Message in the incoming E3 data-stream. 5 Change in SSM OOS State Interrupt Enable R/W Change of SSM OOS (Out of Sequence) Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of SSM OOS Condition” Interrupt, as indicated below. 0 – Disables the “Change of SSM OOS Condition” Interrupt. 1 – Enables the “Change of SSM OOS Condition” Interrupt. In this configuration, the Primary Frame Synchronizer block will generate an interrupt under the following conditions. 4 COFA Interrupt Enable R/W • Whenever the Primary Frame Synchronizer block declares the SSM OOS condition. • When the Primary Frame Synchronizer block clears the SSM OOS condition. Change of Framing Alignment Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of Framing Alignment” condition interrupt, as indicated below. 0 – Disables the “Change of Framing Alignment” Interrupt. 1 – Enables the “Change of Framing Alignment” Interrupt. 3 Change in OOF Defect Condition Interrupt Enable R/W Change of OOF (Out of Frame) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of OOF Defect Condition” Interrupt, as indicated below. 473 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 0 – Disables the “Change of OOF Defect Condition” Interrupt. 1 – Enables the “Change of OOF Defect Condition” Interrupt. In this configuration setting, the Primary Frame Synchronizer block will generate an interrupt under the following conditions. 2 Change in LOF Defect Condition Interrupt Enable R/W • Whenever the Primary Frame Synchronizer block declares the OOF defect condition. • Whenever the Primary Frame Synchronizer block clears the OOF defect condition. Change of LOF (Loss of Frame) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of LOF Defect Condition” Interrupt, as indicated below. 0 – Disables the “Change of LOF Defect Condition” Interrupt. 1 – Enables the “Change of LOF Defect Condition” Interrupt. In this configuration, the Primary Frame Synchronizer block will generate an interrupt under the following conditions. 1 Change in LOS Defect Condition Interrupt Enable R/W • Whenever the Primary Frame Synchronizer block declares the LOF defect condition. • Whenever the Primary Frame Synchronizer block clears the LOF defect condition. Change of LOS (Loss of Signal) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of LOS Defect Condition” Interrupt, as indicated below. 0 – Disables the “Change of LOS Defect Condition” Interrupt. 1 – Enables the “Change of LOS Defect Condition” Interrupt. In this configuration, the Primary Frame Synchronizer block will generate an interrupt under the following conditions. 0 Change of AIS Defect Condition Interrupt Enable R/W • Whenever the Primary Frame Synchronizer block declares the LOS defect condition. • Whenever the Primary Frame Synchronizer block clears the LOS defect condition. Change of AIS (Alarm Indication Signal) Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change of AIS Defect Condition” Interrupt, as indicated below. 0 – Disables the “Change of AIS Defect Condition” Interrupt. 1 – Enables the “Change of AIS Defect Condition” Interrupt. In this configuration, the Primary Frame Synchronizer block will generate an interrupt under the following conditions. • Whenever the Primary Frame Synchronizer block declares the AIS defect condition. • Whenever the Primary Frame Synchronizer block clears the AIS defect condition. 474 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 319: RxE3 Interrupt Enable Register # 2 – G.832 (Address Location= 0xN313, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Change in Receive TrailTrace Message Interrupt Enable Reserved Detection of FEBE Event Interrupt Enable Change in FERF/RDI Defect Condition Interrupt Enable Detection of BIP-8 Error Interrupt Enable Detection of Framing Byte Error Interrupt Enable RxPLD Mismatch Interrupt Enable R/O R/W R/O R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Change in Receive Trail-Trace Message Interrupt Enable R/W DESCRIPTION Change in Receive Trail-Trace Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Change in Receive Trail-Trace Message” Interrupt, as indicated below. 0 – Disables the “Change in Receive Trail-Trace Message” Interrupt. 1 – Enables the “Change in Receive Trail-Trace Message” Interrupt. In this mode, the Primary Frame Synchronizer block will generate an interrupt anytime it receives a different Trail-Trace message, then what it had been receiving. 5 Unused R/W 4 Detection of FEBE Event Interrupt Enable R/W Detection of FEBE Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of FEBE” Interrupt, as indicated below. 0 – Disables the “Detection of FEBE” Interrupt. 1 – Enables the “Detection of FEBE” Interrupt. In this mode, the Primary Frame Synchronizer block will generate an interrupt anytime it detects a FEBE (Far-End Block Error) indicator in the incoming E3 data-stream. 3 Change in FERF/RDI Defect Condition Interrupt Enable R/W Change in FERF Defect Condition Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the Change in FERF/RDI Defect Condition Interrupt, as indicated below. 0 – Disables the “Change in FERF/RDI Defect Condition” Interrupt. 1 – Enables the “Change in FERF/RDI Defect Condition” Interrupt. In this mode, the Primary Frame Synchronizer block will generate an interrupt, in response to either of the following conditions. 2 Detection of BIP-8 Error Interrupt Enable R/W • Whenever the Primary Frame Synchronizer block declares the FERF/RDI Defect condition. • Whenever the Primary Frame Synchronizer block clears the FERF/RDI defect condition. Detection of BIP-8 Error Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of BIP-8 Error” Interrupt, as indicated below. 475 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 0 – Disables the “Detection of BIP-8 Error” Interrupt. 1 – Enables the “Detection of BIP-8 Error” Interrupt. In this mode, the Primary Frame Synchronizer block will generate an interrupt anytime it detects a BIP-8 error in the incoming E3 data-stream. 1 Detection of Framing Byte Error Interrupt Enable R/W Detection of Framing Byte Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Detection of Framing Byte Error” Interrupt, as indicated below. 0 – Disables the “Detection of Framing Byte Error” Interrupt. 1 – Enables the “Detection of Framing Byte Error” Interrupt. In this mode, the Primary Frame Synchronizer block will generate an interrupt anytime it detects a FA1 or FA2 byte error in the incoming E3 data stream. 0 RxPLD Mis Interrupt Enable Received Payload Type Mismatch Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Receive Payload Type Mismatch” interrupt, as indicated below. 0 – Disables the “Received Payload Type Mismatch” Interrupt. 1 – Enables the “Received Payload Type Mismatch” Interrupt. In this mode, the Primary Frame Synchronizer block will generate an interrupt anytime it receives a “Payload Type” value (within the MA byte) that differs from that written into the “RxPLDExp[2:0]” bit-fields. 476 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 320: RxE3 Interrupt Status Register # 1 – G.832 (Address Location= 0xN314, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Change in SSM MSG Interrupt Status Change in SSM OOS Interrupt Status COFA Interrupt Status Change in OOF Defect Condition Interrupt Status Change in LOF Defect Condition Interrupt Status Change in LOS Defect Condition Interrupt Status Change in AIS Defect Condition Interrupt Status R/O RUR RUR RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Change in SSM MSG Interrupt Status RUR DESCRIPTION Change in SSM (Synchronization Status Message) Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in SSM Message” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate an interrupt, anytime it detects a change in the “SSM[3:0]” value that it has received via the incoming E3 data-stream. 0 – Indicates that the “Change in SSM Message” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in SSM Message” Interrupt has occurred since the last read of this register. Note: 5 Change in SSM OOS State Interrupt Status RUR The user can obtain the newly received value for “SSM” by reading out the contents of Bits 3 through 1 (RxSSM[3:0]) within the “RxE3 SSM Register – G.832” (Address Location= 0xN32C). Change in SSM OOS (Out of Sequence) State Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in SSM OOS State” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate the “Change in SSM OOS State” Interrupt will response to the following events. • Whenever the Primary Frame Synchronizer block declares the SSM OOS Condition. • Whenever the Primary Frame Synchronizer block clears the SSM OOS condition. 0 – Indicates that the “Change in SSM OOS Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in SSM OOS Condition” Interrupt has occurred since the last read of this register. 4 COFA Interrupt Status RUR COFA Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “COFA” (Change of Framing Alignment) Interrupt has occurred 477 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate an interrupt anytime it detects a new “Framing Alignment” with the incoming E3 data-stream. 0 – Indicates that the “COFA Interrupt” has not occurred since the last of this register. 1 – Indicates that the “COFA Interrupt” has occurred since the last read of this register. 3 Change in OOF Defect Condition Interrupt Status RUR Change in OOF (Out of Frame) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in OOF Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate the “Change in OOF Defect Condition” Interrupt in response to the following events. • Whenever the Primary Frame Synchronizer block declares the “OOF Condition”. • Whenever the Primary Frame Synchronizer block clears the “OOF Condition”. 0 – Indicates that the “Change in OOF Defect Condition Interrupt” has not occurred since the last of this register. 1 – Indicates that the “Change in OOF Defect Condition Interrupt” has occurred since the last read of this register. Note: 2 Change in LOF Defect Condition Interrupt Status RUR The user can determine the current state of the “AIS Condition” by reading out the contents of Bit 5 (OOF Defect Declared) within the “RxE3 Configuration and Status Register # 2 – G.832” (Address Location= 0xN311). Change in LOF (Loss of Frame) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in LOF Defect Condition Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate the “Change in LOF Defect Condition” Interrupt will occur in response to the following events. • Whenever the Primary Frame Synchronizer block declares the “LOF Defect Condition”. • When the Primary Frame Synchronizer block clears the “LOF Defect Condition”. 0 – Indicates that the “Change in LOF Defect Condition Interrupt” has not occurred since the last of this register. 1 – Indicates that the “Change in LOF Defect Condition Interrupt” has occurred since the last read of this register. Note: 1 Change in LOS Defect RUR The user can determine the current state of the “LOF Condition” by reading out the contents of Bit 6 (LOF Defect Declared) within the “RxE3 Configuration and Status Register # 2 – G.832” (Address Location= 0xN311). Change in LOS (Loss of Signal) Defect Condition Interrupt 478 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Status: Condition Interrupt Status This RESET-upon-READ bit-field indicates whether or not the “Change in LOS Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate the “Change in LOS Defect Condition” Interrupt will occur in response to the following events. • Whenever the Primary Frame Synchronizer block declares the “LOS Defect Condition”. • When the Primary Frame Synchronizer block clears the “LOS Defect Condition”. 0 – Indicates that the “Change in LOS Defect Condition Interrupt” has not occurred since the last of this register. 1 – Indicates that the “Change in LOS Defect Condition Interrupt” has occurred since the last read of this register. Note: 0 Change in AIS Defect Condiiton Interrupt Status RUR The user can determine the current state of the “LOS Condition” by reading out the contents of Bit 4 (LOS Defect Declared) within the “RxE3 Configuration and Status Register # 2 – G.832” (Address Location= 0xN311). Change in AIS Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in AIS Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate the “Change in AIS Defect Condition” Interrupt will occur in response to the following events. • Whenever the Primary Frame Synchronizer block declares the “AIS Condition”. • Whenever the Primary Frame Synchronizer block clears the “AIS Condition”. 0 – Indicates that the “Change in AIS Defect Condition Interrupt” has not occurred since the last of this register. 1 – Indicates that the “Change in AIS Defect Condition Interrupt” has occurred since the last read of this register. Note: 479 The user can determine the current state of the “AIS Condition” by reading out the contents of Bit 3 (AIS Defect Declared) within the “RxE3 Configuration and Status Register # 2 – G.832” (Address Location= 0xN311). XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 321: RxE3 Interrupt Status Register # 2 – G.832 (Address Location= 0xN315, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused Change in Receive Trail-Trace Message Interrupt Status Reserved Detection of FEBE/REI Event Interrupt Status Change in FERF/RDI Defect Condition Interrupt Status Detection of BIP-8 Error Interrupt Status Detection of Framing Byte Error Interrupt Status RxPLD Mismatch Interrupt Status R/O RUR R/O RUR RUR RUR RUR RUR 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 Change in Receive Trail-Trace Message Interrupt Status RUR DESCRIPTION Change in Receive Trail-Trace Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in Receive Trail-Trace Message” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate an interrupt anytime it receives a Trail-Trace Message, that is different from that of the previously received message. 0 – Indicates that the “Change in Receive Trail-Trace Message” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in Receive Trail-Trace Message” Interrupt has occurred since the last read of this register. Note: 5 Unused R/O 4 Detection of FEBE/REI Event Interrupt Status RUR The user can obtain the value of the most recently received Trail-Trace Message by reading out the contents of the “RxE3 Trail-Trace Message Byte-0” through “RxE3 Trail-Trace Message Byte-15” registers (Address Location= 0xN31C through 0xN32B). Detection of FEBE/REI Event Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of FEBE/REI Event” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate an interrupt anytime is detects a FEBE/REI event in the incoming E3 data-stream. 0 – Indicates that the “Detection of FEBE/REI Event” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of FEBE/REI Event” Interrupt has occurred since the last read of this register. 3 Change in FERF/RDI Defect Condition Interrupt Status RUR Change in FERF/RDI (Far-End Receive Failure) Defect Condition Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change in FERF/RDI Defect Condition” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block 480 XRT94L33 Rev222...000...000 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S will generate an interrupt in response to the following events. • Whenever the Primary Frame Synchronizer block declares the FERF/RDI defect condition. • Whenever the Primary Frame Synchronizer block clears the FERF/RDI condition. 0 – Indicates that the “Change in FERF/RDI Defect Condition” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Change in FERF/RDI Defect Condition” Interrupt has occurred since the last read of the register. Note: 2 Detection of BIP-8 Error Interrupt Status RUR The user can obtain the state of the FERF/RDI defect condition, by reading out the contents of Bit 0 (FERF/RDI Defect Declared) within the “RxE3 Configuration and Status Register # 2 – G.832” (Address Location= 0xN311). Detection of BIP-8 Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of BIP-8 Error” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate an interrupt anytime is detects a BIP-8 Error in the incoming E3 data-stream. 0 – Indicates that the “Detection of BIP-8 Error” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of BIP-8 Error” Interrupt has occurred since the last read of this register. 1 Detection of Framing Byte Error Interrupt Status RUR Detection of Framing Byte Error Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Framing Byte Error” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate an interrupt anytime is detects an error in either the FA1 or FA2 byte, within the incoming E3 data-stream. 0 – Indicates that the “Detection of Framing Byte Error” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of Framing Byte Error” Interrupt has occurred since the last read of this register. 0 Detection of PLD Type Mismatch Interrupt Status RUR Detection of Payload Type Mismatch Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Detection of Payload Type Mismatch” Interrupt has occurred since the last read of this register. If this interrupt is enabled, then the Primary Frame Synchronizer block will generate an interrupt anytime it receives an E3 data-stream that contains a “RxPLDType[2:0]” that is different from the “RxPLDTypeExp[2:0]” value. 0 – Indicates that the “Detection of Payload Type Mismatch” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Detection of Payload Type Mismatch” Interrupt has occurred since the last read of this register. Note: The user can obtain the contents of the most recently received Payload Type by reading out the contents of Bits 7 through 5 (RxPLDType[2:0]) within the “RxE3 Configuration and Status 481 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Register # 1 – G.832” (Address Location= 0xN310). 482 Rev222...000...000 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 322: RxE3 LAPD Control Register – G.832 (Address Location= 0xN318, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 RxLAPD Any Message Check Disable R/W R/W R/O 0 0 0 BIT NUMBER NAME TYPE 7 RxLAPD Any R/W BIT 3 BIT 2 BIT 1 BIT 0 Receive LAPD from NR Byte Receive LAPD Enable Receive LAPD Interrupt Enable Receive LAPD Interrupt Status R/O R/W R/W R/W RUR 0 0 0 0 0 Unused DESCRIPTION Receive LAPD – Any kind: This READ/WRITE bit-field permits the user to configure the Receive LAPD Controller sub-block (within the Primary Frame Synchronizer block) to receive any kind of LAPD Message (or HDLC Message) with a size of 82 bytes or less. If the user implements this option, then the Receive LAPD Controller sub-block will be capable of receiving any kind of HDLC Message (with any value of header bytes). The only restriction is that the size of the HDLC Message must not exceed 82 bytes. 0 – Does not invoke this “Any Kind of HDLC Message” feature. In this case, the Receive LAPD Controller sub-block will only receive HDLC Messages that contains the Bellcore GR-499-CORE values for SAPI and TEI. 1-Invokes this “Any Kind of HDLC Message” feature. In this case, the Receive LAPD Controller sub-block will be able to receive HDLC Messages that contain any header byte values. Note: This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. The user can determine the size (or byte count) fo the most recently received LAPD/PMDL Message, by reading the contents of the “RxLAPD Byte Count” Register (Address Location= 0xN384). 6 Message Check Disable R/W Message Check Disable: This READ/WRITE bit-field permits the user to either enable or disable the new message comparison logic. If the user disables the new message comparison logic, then every message received would generate an interrupt. 0 – Enables the new message comparison logic 1 – Disables the new message comparison logic 6–4 Unused R/O 3 Receive LAPD from NR Byte R/W Receive LAPD Message from NR Byte Select: This READ/WRITE bit-field permits the user to configure the Receive LAPD Controller sub-block to extract out the PMDL data from the NR or GC byte, within the incoming E3 data stream. 0 – Configures the Receive LAPD Controlller sub-block to extract PMDL information from the GC byte, within the incoming E3 data stream. 1 – Configures the Receive LAPD Controller sub-block to extract PMDL information from the NR byte, within the incoming E3 data stream. Note: This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. 483 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM 2 Receive LAPD Enable R/W Rev222...000...000 Receive LAPD Controller Block Enable: This READ/WRITE bit-field permits the user to either enable or disable the Receive LAPD Controller sub-block (within the Primary Frame Synchronizer block). If the user enables the Receive LAPD Controller sub-block, then it will immediately begin extracting out and monitoring the data that is being carried by either the NR or GC bytes (depending upon user configuration) within the incoming E3 data stream. 0 – Disables the Receive LAPD Controller sub-block. 1 – Enables the Receive LAPD Controller sub-block. Note: 1 Receive LAPD Interrupt Enable R/W This bit-field is ignored if the Primary Frame Synchronizer block is bypassed. Receive LAPD Message Interrupt Enable: This READ/WRITE bit-field permits the user to either enable or disable the “Receive LAPD Message” Interrupt. If the user enables this interrupt, then the Receive LAPD Controller sub-block (within the Primary Frame Synchronizer block) will generate an interrupt, anytime the Receive LAPD Controller subblock receives a new LAPD/PMDL Message. 0 – Disables the “Receive LAPD Message” Interrupt. 1 – Enables the “Receive LAPD Message” Interrupt. Note: 0 Receive LAPD Interrupt Status RUR This bit-field is ignored if the Receive LAPD Controller sub-block is disabled. Receive LAPD Message Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Receive LAPD Message” Interrupt has occurred since the last read of this register. 0 – Indicates that the “Receive LAPD Message” Interrupt has NOT occurred since the last read of this register. 1 – Indicates that the “Receive LAPD Message” Interrupt has occurred since the last read of this register. Note: This bit-field is ignored if the Receive LAPD Controller sub-block is disabled. 484 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 323: RxE3 LAPD Status Register – G.832 (Address Location= 0xN319, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Unused RxABORT RxLAPDType[1:0] RxCR Type RxFCS Error End of Message Flag Present R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7 Unused R/O 6 RxABORT R/O DESCRIPTION Receive ABORT Sequence Indicator: This READ-ONLY bit-field indicates whether or not the most recently received LAPD/PMDL Message was interrupted by an ABORT sequence (e.g., a string of seven consecutive “1s”) as described below. 0 – Indicates that the Receive LAPD Controller sub-block has NOT received an ABORT sequence within the most recently LAPD/PMDL Message. 1 - Indicates that the Receive LAPD Controller sub-block has received an ABORT sequence within the most recently received LAPD/PMDL Message. Note: 5–4 RxLAPDType[1:0] R/O Once the Receive LAPD Controller sub-block receives an ABORT sequence, it will set this bit-field “high”, until it receives another LAPD Message. Receive LAPD Message Type Indicator[1:0]: These two READ-ONLY bits indicate the type of LAPD Message that is residing within the Receive LAPD Message buffer. The relationship between the content of these two bit-fields and the corresponding message type is presented below. 3 RxCR Type R/O RxLAPDType[1:0] Message Type 0 0 CL Path Identification 0 1 Idle Signal Identification 1 0 Test Signal Identification 1 1 ITU-T Path Identification Received C/R Value: This READ-ONLY bit-field indicates the value of the C/R bit (within one of the header bytes) of the most recently received LAPD Message. 2 RxFCS Error R/O Receive Frame Check Sequence (FCS) Error Indicator: This READ-ONLY bit-field indicates whether or not the most recently received LAPD Message frame contained an FCS error as described below. 0 – Indicates that the most recently received LAPD Message frame does not contain an FCS error. 1 – Indicates that the most recently received LAPD Message frame 485 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 does contain an FCS error. 1 End of Message R/O End of Message Indicator This READ-ONLY bit-field indicates whether or not the Receive LAPD Controller sub-block has received a complete LAPD Message as described below. 0 – Indicates that the Receive LAPD Controller sub-block is currently receiving a LAPD Message, but has not received the complete message. 1 – Indicates that the Receive LAPD Controller sub-block has received a completed LAPD Message. Note: 0 Flag Present R/O Once the Receive LAPD Controller sub-block sets this bit-field “high”, this bit-field will remain high, until the Receive LAPD Controller sub-block begins to receive a new LAPD Message. Receive Flag Sequence Indicator: This READ-ONLY bit-field indicates whether or not the Receive LAPD Controller sub-block is currently receiving the Flag Sequence (e.g., a continuous stream of 0x7E octets within the Data Link channel). 0 – Indicates that the Receive LAPD Controller sub-block is NOT currently receiving the Flag Sequence octet. 1 – Indicates that the Receive LAPD Controller sub-block is currently receiving the Flag Sequence octet. 486 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 324: RxE3 NR Byte Register – G.832 (Address Location= 0xN31A, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 RxNR_Byte[7:0] BIT NUMBER NAME TYPE 7-0 RxNR_Byte[7:0] R/O DESCRIPTION Receive NR Byte Value: These READ-ONLY bit-fields contain the value of the NR byte, within the most recently received E3 frame. Table 325: RxE3 GC Byte Register – G.832 (Address Location= 0xN31B, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RxGC_Byte[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 RxGC_Byte[7:0] R/O DESCRIPTION Receive GC Byte Value: These READ-ONLY bit-fields contain the value of the GC byte, within the most recently received E3 frame. Table 326: RxE3 Trail-Trace-0 Register – G.832 (Address Location= 0xN31C, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RxTTB_0[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 RxTTB_0[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 0: These READ-ONLY bit-fields contain the contents of Byte 0 (e.g., the “Marker” Byte), within the most recently received Trail-Trace Buffer” Message. 487 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 327: RxE3 Trail-Trace-1 Register – G.832 (Address Location= 0xN31D, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 RxTTB_1[7:0] BIT NUMBER NAME TYPE 7-0 RxTTB_1[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 1: These READ-ONLY bit-fields contain the contents of Byte 1, within the most recently received Trail-Trace Buffer” Message. Table 328: RxE3 Trail-Trace-2 Register – G.832 (Address Location= 0xN31E, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 RxTTB_2[7:0] BIT NUMBER NAME TYPE 7-0 RxTTB_2[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 2: These READ-ONLY bit-fields contain the contents of Byte 2, within the most recently received Trail-Trace Buffer” Message. Table 329: RxE3 Trail-Trace-3 Register – G.832 (Address Location= 0xN31F, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RxTTB_3[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 RxTTB_3[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 3: These READ-ONLY bit-fields contain the contents of Byte 3, within the most recently received Trail-Trace Buffer” Message. 488 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 330: RxE3 Trail-Trace-4 Register – G.832 (Address Location= 0xN320, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 RxTTB_4[7:0] BIT NUMBER NAME TYPE 7-0 RxTTB_4[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 4: These READ-ONLY bit-fields contain the contents of Byte 4, within the most recently received Trail-Trace Buffer” Message. Table 331: RxE3 Trail-Trace-5 Register – G.832 (Address Location= 0xN321, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 RxTTB_5[7:0] BIT NUMBER NAME TYPE 7-0 RxTTB_5[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 5: These READ-ONLY bit-fields contain the contents of Byte 5, within the most recently received Trail-Trace Buffer” Message. Table 332: RxE3 Trail-Trace-6 Register – G.832 (Address Location= 0xN322, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RxTTB_6[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 RxTTB_6[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 6: These READ-ONLY bit-fields contain the contents of Byte 6, within the most recently received Trail-Trace Buffer” Message. 489 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM Rev222...000...000 Table 333: RxE3 Trail-Trace-7 Register – G.832 (Address Location= 0xN323, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 RxTTB_7[7:0] BIT NUMBER NAME TYPE 7-0 RxTTB_7[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 7: These READ-ONLY bit-fields contain the contents of Byte 7, within the most recently received Trail-Trace Buffer” Message. Table 334: RxE3 Trail-Trace-8 Register – G.832 (Address Location= 0xN324, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 RxTTB_8[7:0] BIT NUMBER NAME TYPE 7-0 RxTTB_8[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 8: These READ-ONLY bit-fields contain the contents of Byte 8, within the most recently received Trail-Trace Buffer” Message. Table 335: RxE3 Trail-Trace-9 Register – G.832 (Address Location= 0xN325, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RxTTB_9[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 RxTTB_9[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 9: These READ-ONLY bit-fields contain the contents of Byte 9, within the most recently received Trail-Trace Buffer” Message. 490 XRT94L33 333---C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S---111 T TO OS ST TS S---333///S ST TM M---111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE ER RS S Rev222...000...000 Table 336: RxE3 Trail-Trace-10 Register – G.832 (Address Location= 0xN326, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 RxTTB_10[7:0] BIT NUMBER NAME TYPE 7-0 RxTTB_10[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 10: These READ-ONLY bit-fields contain the contents of Byte 10, within the most recently received Trail-Trace Buffer” Message. Table 337: RxE3 Trail-Trace-11 Register – G.832 (Address Location= 0xN327, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 R/O R/O R/O R/O 0 0 0 0 BIT 3 BIT 2 BIT 1 BIT 0 R/O R/O R/O R/O 0 0 0 0 RxTTB_11[7:0] BIT NUMBER NAME TYPE 7-0 RxTTB_11[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 11: These READ-ONLY bit-fields contain the contents of Byte 11, within the most recently received Trail-Trace Buffer” Message. Table 338: RxE3 Trail-Trace-12 Register – G.832 (Address Location= 0xN328, where N ranges from 0x02 to 0x04) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RxTTB_12[7:0] R/O R/O R/O R/O R/O R/O R/O R/O 0 0 0 0 0 0 0 0 BIT NUMBER NAME TYPE 7-0 RxTTB_12[7:0] R/O DESCRIPTION Receive Trail-Trace Buffer Message – Byte 12: These READ-ONLY bit-fields contain the contents of Byte 12, within the most recently received Trail-Trace Buffer” Message. 491 XRT94L33 333---C T M M A P P E R S O N E T R E G S T E R S C H A N N E L D S E S T S T O S T S S M---111 M MA AP PP PE ER R –