EXAR XRT94L33_07

XRT94L33
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ST
TS
S---333///S
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M---111 M
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AP
PP
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R ––– A
AT
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EG
GIIIS
ST
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S
March 2007
Rev 2.0.0
GENERAL DESCRIPTION
FEATURES
The XRT94L33 is a highly integrated SONET/SDH
terminator
designed
for
E3/DS3/STS-1
mapping/de-mapping functions from either the
STS-3 or STM-1 data stream. The XRT94L33
interfaces directly to the optical transceiver
•
Provides DS3/ E3 mapping/de-mapping for up to
3 tributaries through SONET STS-1 or SDH AU3 and/or TUG-3/AU-4 containers
•
Generates and terminates SONET/SDH section,
line and path layers
•
Integrated SERDES with Clock Recovery Circuit
•
Provides SONET
descrambling
•
Integrated Clock Synthesizer that generates 155
MHz and 77.76 MHz clock from an external
12.96/19.44/77.76 MHz reference clock
The XRT94L33 uses the internal E3/DS3 DeSynchronizer circuit with an internal pointer leak
algorithm for clock smoothing as well as to remove
the jitter due to mapping and pointer movements.
These De-Synchronizer circuits do not need any
external clock reference for its operation.
•
Integrated 3 E3/DS3/STS-1 De-Synchronizer
circuit that de-jitter gapped clock to meet
0.05UIpp jitter requirements
•
Access to Line or Section DCC
•
Level 2 Performance Monitoring for E3 and DS3
The SONET/SDH transmit blocks allow flexible
insertion of TOH and POH bytes through both
Hardware and Software. Individual POH bytes for
the transmitted SONET/SDH signal are mapped
either from the XRT94L33 memory map or from
external interface. A1, A2 framing pattern, C1 byte
and H1, H2 pointer byte are generated.
•
Supports mixing of STS-1E and DS3 or E3 and
DS3 tributaries
•
UTOPIA Level 2 interface for ATM or level 2P for
Packets
•
E3 and DS3 framers for both Transmit and
Receive directions
The SONET/SDH receive blocks receive SONET
STS-3 signal or SDH STM-1 signal and perform the
necessary transport and path overhead processing.
•
Complete
Transport/Section
Overhead
Processing and generation per Telcordia and
ITU standards
The XRT94L33 provides a line side APS
(Automatic Protection Switching) interface by
offering redundant receive serial interface to be
switched at the frame boundary.
•
Single PHY and Multi-PHY operations supported
•
Full line APS
applications
The XRT94L33 provides 3 Mappers for performing
STS-1/VC-3 to STS-1/DS3/E3 mapping function,
one for each STS-1/DS3/E3 framers.
•
Loopback support for both SONET/SDH as well
as E3/DS3/STS-1
•
Boundary scan capability with JTAG IEEE 1149
•
8-bit microprocessor interface
•
3.3 V ± 5% Power Supply; 5 V input signal
tolerance
APPLICATIONS
•
-40°C to +85°C Operating Temperature Range
•
Network switches
Available in a 504 Ball TBGA package
•
Add/Drop Multiplexer
•
W-DCS Digital Cross Connect Systems
The XRT94L33 processes the section, line and
path overhead in the SONET/SDH data stream and
also performs ATM and PPP PHY-layer
processing. The processing of path overhead bytes
within the STS-1s or TUG-3s includes 64 bytes for
storing the J1 bytes. Path overhead bytes can be
accessed through the microprocessor interface or
via serial interface.
A PRBS test pattern generation and detection is
implemented to measure the bit-error performance.
A general-purpose microprocessor interface is
included for control, configuration and monitoring.
frame
support
scrambling
for
and
redundancy
E Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * Fax (510) 668-7017 * www.exar.com
XRT94L33
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M---111 M
MA
AP
PP
PE
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Block Diagram of the XRT94L33
To OC3
Telecom
Bus
Interface
To F.O.
OC3
TxRx
SONET/SDH
TOH
SONET/SDH
POH
Telecom
Bus
Interface
To DS3/E3
STS-1
Telecom
Bus/
T3/E3/HDLC
Intf
SONET/SDH
POH
Boundry
Scan
SDH MUX
Microprocessor
Interface
DS3/E3
Mapper
Jitter Attenuator
&
Clock Sm oothing
DS3/E3
Fram er
ATM
Processor
PLCP
PPP
Processor
Pointer
Justify
HDLC
Controller
STS-1 Tx/Rx
TO H & POH
SO NET/SDH
PO H
Telecom
Bus
Interface
To DS3/E3
STS-1
Telecom
Bus/
T3/E3/HDLC
Intf
DS3/E3
Mapper
STS-1 Channel 0
Jitter Attenuator
&
Clock Sm oothing
DS3/E3
Fram er
ATM
Processor
PLCP
PPP
Processor
Pointer
Justify
UTOPIA
II/IIp
Interface
HDLC
Controller
STS-1 Tx/Rx
TOH & POH
SO NET/SDH
PO H
Telecom
Bus
Interface
To DS3/E3
STS-1
Telecom
Bus/
T3/E3/HDLC
Intf
DS3/E3
Mapper
STS-1 Channel 1
Jitter Attenuator
&
Clock Sm oothing
DS3/E3
Fram er
ATM
Processor
PLCP
PPP
Processor
Pointer
Justify
HDLC
Controller
STS-1 Tx/Rx
TOH & POH
STS-1 Channel 2
ORDERING INFORMATION
PART NUMBER
PACKAGE TYPE
OPERATING TEMPERATURE RANGE
XRT94L33IB
27 x 27 504 Lead TBGA
-40°C to +85°C
1.0 XRT94L33 REGISTERS FOR SONET ATM/PPP APPLICATIONS
1.1
THE OVERALL REGISTER MAP WITHIN THE XRT94L33
The XRT94L33 employs a direct Addressing Scheme. The Address Locations for each of the “Register
Groups” (or Register pages) is presented in the Table below.
Table 1: The Address Register Map for the XRT94L33
ADDRESS LOCATION
REGISTER NAME
DEFAULT VALUE
OPERATION CONTROL BLOCK REGISTERS
0x0000 – 0x00FF
Reserved
0x0100
Operation Control Register – Byte 3
0x00
0x0101
Operation Control Register – Byte 2
0x00
2
XRT94L33
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S333///E
E333///S
ST
TS
S---111 T
TO
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ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
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R ––– A
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MR
RE
EG
GIIIS
ST
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Rev222...000...000
0x0102
Reserved
0x00
0x0103
Operation Control Register – Byte 0
0x00
0x0104
Operation Status Register – Byte 3 (Device ID)
0xE3
0x0105
Operation Status Register – Byte 2 (Revision ID)
0x01
Reserved
0x00
Operation Interrupt Status Register – Byte 0
0x00
Reserved
0x00
Operation Interrupt Enable Register – Byte 0
0x00
Reserved
0x00
0x0112
Operation Block Interrupt Status Register – Byte 1
0x00
0x0113
Operation Block Interrupt Status Register – Byte 0
0x00
Reserved
0x00
0x0116
Operation Block Interrupt Enable Register – Byte 1
0x00
0x0117
Operation Block Interrupt Enable Register – Byte 0
0x00
0x0118 – 0x0119
Reserved
0x00
0x011A
Reserved
0x00
0x011B
Mode Control Register – Byte 0
0x00
Reserved
0x00
0x011F
Loop-back Control Register – Byte 0
0x00
0x0120
Channel Interrupt Indicator – Receive SONET POH Processor Block
0x00
0x0121
Reserved
0x00
0x0122
Channel Interrupt Indicator – DS3/E3 framer Block
0x00
0x0123
Channel Interrupt Indicator – Receive STS-1 POH Processor Block
0x00
0x0124
Channel Interrupt Indicator – Receive STS-1 TOH Processor Block
0x00
0x0125
Reserved
0x00
0x0126
Channel Interrupt Indicator – STS-1/DS3/E3 Mapper Block
0x00
0x0127
Reserved
0x00
0x0128
Reserved
0x00
0x0129
Reserved
0x00
0x012A – 0x012F
Reserved
0x00
0x0130
Reserved
0x11
0x0131
Reserved
0x00
0x0132
Interface Control Register – Byte 1
0x00
0x0106 – 0x010A
0x010B
0x010C – 0x010E
0x010F
0x0110 – 0x0111
0x0114 – 0x0115
0x011C – 0x011E
3
XRT94L33
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M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
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ST
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S---333///S
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Rev222...000...000
0x0133
Interface Control Register – Byte 0
0x00
0x0134
STS-3/STM-1 Telecom Bus Control Register – Byte 3
0x00
0x0135
STS-3/STM-1 Telecom Bus Control Register – Byte 2
0x00
0x0136
Reserved
0x00
0x0137
STS-3/STM-1 Telecom Bus Control Register – Byte 0
0x00
0x0138
Reserved
0x00
0x0139
Interface Control Register – Byte 2 – STS-3 Telecom Bus 2
0x00
0x013A
Interface Control Register – Byte 1 – STS-3 Telecom Bus 1
0x00
0x013B
Interface Control Register – Byte 0 – STS-3 Telecom Bus 0
0x00
0x013C
Interface Control Register – STS-1 Telecom Bus Interrupt Register
0x00
0x013D
Interface Control Register – STS-1 Telecom Bus Interrupt Status Register
0x00
0x013E
Interface Control Register – STS-1 Telecom Bus Interrupt Register # 2
0x00
0x013F
Interface Control Register – STS-1 Telecom Bus Interrupt Enable Register
0x00
Reserved
0x00
Operation General Purpose Input/Output Register
0x00
0x0148 – 0x0149
Reserved
0x00
0x014A
Reserved
0x00
0x014B
Operation General Purpose Input/Output Direction Register – Byte 0
0x00
0x014C –0x014E
Reserved
0x00
0x014F
Reserved
0x00
0x0150
Operation Output Control Register – Byte 1
0x00
Reserved
0x00
0x0153
Operation Output Control Register – Byte 0
0x00
0x0154
Operation Slow Speed Port Control Register – Byte 1
0x00
Reserved
0x00
0x0157
Operation Slow Speed Port Control Register –Byte 0
0x00
0x0158
Operation – DS3/E3/STS-1 Clock Frequency Out of Range Detection –
Direction Register
0x00
0x0159
Reserved
0x00
0x015A
Operation – DS3/E3/STS-1 Clock Frequency – DS3 Out of Range Detection
Threshold Register
0x00
0x015B
Operation – DS3/E3/STS-1 Clock Frequency – STS-1/E3 Out of Range
Detection Threshold Register
0x00
0x015C
Reserved
0x00
0x015D
Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Enable Register
0x00
0x0140 – 0x0146
0x0147
0x0151 –0x0152
0x0155 – 0x0156
4
XRT94L33
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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S
Rev222...000...000
– Byte 0
0x015E
Reserved
0x00
0x015F
Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Status Register –
Byte 0
0x00
Reserved
0x00
0x0180
APS Mapping Register
0x00
0x0181
APS Control Register
0x00
Reserved
0x00
0x0194
APS Status Register
0x00
0x0195
Reserved
0x00
0x0196
APS Status Register
0x00
0x0197
APS Status Register
0x00
0x0198
APS Interrupt Register
0x00
0x0199
Reserved
0x00
0x019A
APS Interrupt Register
0x00
0x019B
APS Interrupt Register
0x00
0x019C
APS Interrupt Register
0x00
0x019D
Reserved
0x00
0x019E
APS Interrupt Enable Register
0x00
0x019F
APS Interrupt Enable Register
0x00
Reserved
0x00
0x0160 – 0x017F
0x0182 – 0x0193
0x01A0 – 0x01FF
LINE INTERFACE CONTROL REGISTERS
0x0302
Receive Line Interface Control Register – Byte 1
0x00
0x0303
Receive Line Interface Control Register – Byte 0
0x00
Reserved
0x00
Receive Line Status Register
0x00
Reserved
0x00
Receive Line Interrupt Register
0x00
Reserved
0x00
Receive Line Interrupt Enable Register
0x00
Reserved
0x00
Transmit Line Interface Control Register
0x00
0x0304 – 0x0306
0x0307
0x0308 -0x030A
0x030B
0x030C – 0x030E
0x030F
0x0310 – 0x0382
0x0383
RECEIVE/TRANSMIT UTOPIA INTERFACE REGISTERS
0x0384 – 0x0502
0x00
Reserved
5
XRT94L33
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L
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S
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S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
0x0503
0x0504 – 0x0512
0x0513
0x0514 – 0x0516
0x0517
0x0518 – 0x0582
0x0583
0x0584 – 0x0592
0x0593
0x0594 – 0x0596
0x0597
0x0598 – 0x1102
Rev222...000...000
Receive UTOPIA Control Register – Byte 0
0x8F
Reserved
0x00
Receive UTOPIA Port Address
0x00
Reserved
0x00
Receive UTOPIA Port Number
0x00
Reserved
0x00
Transmit UTOPIA Control Register – Byte 0
0x8F
Reserved
0x00
Transmit UTOPIA Port Address
0x00
Reserved
0x00
Transmit UTOPIA Port Number
0x00
Reserved
0x00
RECEIVE STS-3 TOH PROCESSOR BLOCK CONTROL REGISTERS
0x1103
Receive STS-3 Transport Control Register – Byte 0
0x00
Reserved
0x00
0x1106
Receive STS-3 Transport Status Register – Byte 1
0x00
0x1107
Receive STS-3 Transport Status Register – Byte 0
0x02
0x1108
Reserved
0x00
0x1109
Receive STS-3 Transport Interrupt Status Register – Byte 2
0x00
0x110A
Receive STS-3 Transport Interrupt Status Register – Byte 1
0x00
0x110B
Receive STS-3 Transport Interrupt Status Register – Byte 0
0x00
0x110C
Reserved
0x00
0x110D
Receive STS-3 Transport Interrupt Enable Register – Byte 2
0x00
0x110E
Receive STS-3 Transport Interrupt Enable Register – Byte 1
0x00
0x110F
Receive STS-3 Transport Interrupt Enable Register – Byte 0
0x00
0x1110
Receive STS-3 Transport B1 Error Count – Byte 3
0x00
0x1111
Receive STS-3 Transport B1 Error Count – Byte 2
0x00
0x1112
Receive STS-3 Transport B1 Error Count – Byte 1
0x00
0x1113
Receive STS-3 Transport B1 Error Count – Byte 0
0x00
0x1114
Receive STS-3 Transport B2 Error Count – Byte 3
0x00
0x1115
Receive STS-3 Transport B2 Error Count – Byte 2
0x00
0x1116
Receive STS-3 Transport B2 Error Count – Byte 1
0x00
0x1117
Receive STS-3 Transport B2 Error Count – Byte 0
0x00
0x1104 – 0x1105
6
XRT94L33
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CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0x1118
Receive STS-3 Transport REI-L Error Count – Byte 3
0x00
0x1119
Receive STS-3 Transport REI-L Error Count – Byte 2
0x00
0x111A
Receive STS-3 Transport REI-L Error Count – Byte 1
0x00
0x111B
Receive STS-3 Transport REI-L Error Count – Byte 0
0x00
0x111C
Reserved
0x00
0x111D - 0 x111E
Reserved
0x00
Receive STS-3 Transport K1 Byte Value
0x00
Reserved
0x00
Receive STS-3 Transport K2 Byte Value
0x00
Reserved
0x00
Receive STS-3 Transport S1 Byte Value
0x00
Reserved
0x00
Receive STS-3 Transport – In-Sync Threshold Value
0x00
Reserved
0x00
0x112E
Receive STS-3 Transport – LOS Threshold Value – MSB
0xFF
0x112F
Receive STS-3 Transport – LOS Threshold Value – LSB
0xFF
0x1130
Reserved
0x00
0x1131
Receive STS-3 Transport – SF Set Monitor Interval – Byte 2
0x00
0x1132
Receive STS-3 Transport – SF Set Monitor Interval – Byte 1
0x00
0x1133
Receive STS-3 Transport – SF Set Monitor Interval – Byte 0
0x00
Reserved
0x00
0x1136
Receive STS-3 Transport – SF Set Threshold – Byte 1
0x00
0x1137
Receive STS-3 Transport – SF Set Threshold – Byte 0
0x00
Reserved
0x00
0x113A
Receive STS-3 Transport – SF Clear Threshold – Byte 1
0x00
0x113B
Receive STS-3 Transport – SF Clear Threshold – Byte 0
0x00
0x113C
Reserved
0x00
0x113D
Receive STS-3 Transport – SD Set Monitor Interval – Byte 2
0x00
0x113E
Receive STS-3 Transport – SD Set Monitor Interval – Byte 1
0x00
0x113F
Receive STS-3 Transport – SD Set Monitor Interval – Byte 0
0x00
Reserved
0x00
0x1142
Receive STS-3 Transport – SD Set Threshold – Byte 1
0x00
0x1143
Receive STS-3 Transport – SD Set Threshold – Byte 0
0x00
0x111F
0x1120 – 0x1122
0x1123
0x1124 – 0x1126
0x1127
0x1128 – 0x112A
0x112B
0x112C, 0x112D
0x1134 – 0x1135
0x1138, 0x1139
0x1140, 0x1141
7
XRT94L33
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
0x1144, 0x1145
Rev222...000...000
Reserved
0x00
0x1146
Receive STS-3 Transport – SD Clear Threshold – Byte 1
0x00
0x1147
Receive STS-3 Transport – SD Clear Threshold – Byte 0
0x00
Reserved
0x00
Receive STS-3 Transport – Force SEF Condition
0x00
Reserved
0x00
Receive STS-3 Transport – Receive J0 Trace Buffer Control
0x00
Reserved
0x00
0x1152
Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 1
0x00
0x1153
Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte 0
0x00
Reserved
0x00
0x1156
Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 1
0x00
0x1157
Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte 0
0x00
0x1158
Reserved
0x00
0x1159
Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 2
0xFF
0x115A
Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1
0xFF
0x115B
Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0
0xFF
0x115C
Reserved
0x00
0x115D
Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2
0xFF
0x115E
Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1
0xFF
0x115F
Receive STS-3 Transport – Receive SF Clear Monitor – Byte 0
0xFF
Reserved
0x00
Receive STS-3 Transport – Auto AIS Control Register
0x00
Reserved
0x00
Receive STS-3 Transport – Serial Port Control Register
0x00
Reserved
0x00
Receive STS-3 Transport – Auto AIS (in Downstream STS-1s) Control Register
0x000
Reserved
0x00
0x117A
Receive STS-3 Transport – TOH Capture Indirect Address
0x00
0x117B
Receive STS-3 Transport – TOH Capture Indirect Address
0x00
0x117C
Receive STS-3 Transport – TOH Capture Indirect Data
0x00
0x117D
Receive STS-3 Transport – TOH Capture Indirect Data
0x00
0x117E
Receive STS-3 Transport – TOH Capture Indirect Data
0x00
0x1148 – 0x114A
0x114B
0x114C, 0x114E
0x114F
0x1150, 0x1151
0x1154, 0x1155
0x1160 – 0x1162
0x1163
0x1164 – 0x1166
0x1167
0x1168 – 0x116A
0x116B
0x116C – 0x1179
8
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0x117F
0x1180 – 0x11FF
Receive STS-3 Transport – TOH Capture Indirect Data
0x00
Reserved
0x00
RECEIVE STS-3/STM-1 TOH PROCESSOR BLOCK – RECEIVE J0 (SECTION) TRACE MESSAGE BUFFER
0x1300 – 0x133F
Receive STS-3/STM-1 TOH Processor Block – Receive J0 (Section) Trace
Message Buffer – Expected and Received
0x00
0x1340 – 0x13FF
Reserved
0x00
TRANSMIT STS-3 TOH PROCESSOR BLOCK CONTROL REGISTERS
0x1800 – 0x1901
Reserved
0x00
0x1902
Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1
0x00
0x1903
Transmit STS-1 Transport – SONET Transmit Control Register – Byte 0
0x00
0x1904 – 0x1915
Reserved
0x00
0x1916
Reserved
0x00
0x1917
Transmit STS-3 Transport – Transmit A1 Error Mask – Low Register – Byte 0
0x00
0x1918 – 0x191D
Reserved
0x00
0x191E
Reserved
0x00
0x191F
Transmit STS-3 Transport – Transmit A2 Error Mask – Low Register – Byte 0
0x00
Reserved
0x00
Transmit STS-3 Transport – B1 Byte Error Mask Register
0x00
0x1924 – 0x1925
Reserved
0x00
0x1926
Reserved
0x00
0x1927
Transmit STS-3 Transport – Transmit B2 Byte Error Mask Register – Byte 0
0x00
Reserved
0x00
Transmit STS-3 Transport – Transmit B2 Bit Error Mask Register – Byte 0
0x00
Reserved
0x00
0x192E
Transmit STS-3 Transport – K1K2 (APS) Value Register – Byte 1
0x00
0x192F
Transmit STS-3 Transport – K1K2 (APS) Value Register – Byte 0
0x00
Reserved
0x00
Transmit STS-3 Transport – RDI-L Control Register
0x00
Reserved
0x00
Transmit STS-3 Transport – M0M1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3 Transport – S1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3 Transport – F1 Byte Value Register
0x00
0x1920 – 0x1921
0x1923
0x1928 – 0x192A
0x192B
0x192C – 0x192D
0x1930 – 0x1931
0x1933
0x1934 – 0x1936
0x1937
0x1938 –
0x193A
0x193B
0x193C – 0x193E
0x193F
9
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
0x1940 – 0x1942
Rev222...000...000
Reserved
0x00
0x1943
Transmit STS-3 Transport – E1 Byte Value Register
0x00
0x1944
Reserved
0x00
0x1945
Reserved
0x00
0x1946
Reserved
0x00
0x1947
Transmit STS-3 Transport – E2 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3 Transport – J0 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3 Transport – J0 Byte Control Register
0x00
Reserved
0x00
Transmit STS-3 Transport – Serial Port Control Register
0x00
Reserved
0x00
0x1948 – 0x194A
0x194B
0x194C – 0x194E
0x194F
0x1950 – 0x1952
0x1953
0x1954 –0x19FF
TRANSMIT STS-3 TOH PROCESSOR BLOCK – TRANSMIT J0 (SECTION) TRACE MESSAGE BUFFER
0x1B00 – 0x1B3F
Transmit STS-3 TOH Processor Block – Transmit J0 (Section) Trace Message
Buffer
0x00
0x1B40 – 0x1BFF
Reserved
0x00
REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK CONTROL REGISTERS
0x1600 – 0x1702
0x1703
Reserved
Redundant Receive STS-3 Transport Control Register – Byte 0
0x00
Reserved
0x00
0x1706
Redundant Receive STS-3 Transport Status Register – Byte 1
0x00
0x1707
Redundant Receive STS-3 Transport Status Register – Byte 0
0x02
0x1708
Reserved
0x00
0x1709
Redundant Receive STS-3 Transport Interrupt Status Register – Byte 2
0x00
0x170A
Redundant Receive STS-3 Transport Interrupt Status Register – Byte 1
0x00
0x170B
Redundant Receive STS-3 Transport Interrupt Status Register – Byte 0
0x00
0x170C
Reserved
0x00
0x170D
Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 2
0x00
0x170E
Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 1
0x00
0x170F
Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 0
0x00
0x1710
Redundant Receive STS-3 Transport B1 Error Count – Byte 3
0x00
0x1711
Redundant Receive STS-3 Transport B1 Error Count – Byte 2
0x00
0x1712
Redundant Receive STS-3 Transport B1 Error Count – Byte 1
0x00
0x1704 – 0x1705
10
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0x1713
Redundant Receive STS-3 Transport B1 Error Count – Byte 0
0x00
0x1714
Redundant Receive STS-3 Transport B2 Error Count – Byte 3
0x00
0x1715
Redundant Receive STS-3 Transport B2 Error Count – Byte 2
0x00
0x1716
Redundant Receive STS-3 Transport B2 Error Count – Byte 1
0x00
0x1717
Redundant Receive STS-3 Transport B2 Error Count – Byte 0
0x00
0x1718
Redundant Receive STS-3 Transport REI-L Error Count – Byte 3
0x00
0x1719
Redundant Receive STS-3 Transport REI-L Error Count – Byte 2
0x00
0x171A
Redundant Receive STS-3 Transport REI-L Error Count – Byte 1
0x00
0x171B
Redundant Receive STS-3 Transport REI-L Error Count – Byte 0
0x00
0x171C
Reserved
0x00
0x171D - 0 x171E
Reserved
0x00
Redundant Receive STS-3 Transport K1 Value
0x00
Reserved
0x00
Redundant Receive STS-3 Transport K2 Value
0x00
Reserved
0x00
Redundant Receive STS-3 Transport S1 Value
0x00
Reserved
0x00
Redundant Receive STS-3 Transport – In-Sync Threshold Value
0x00
Reserved
0x00
0x172E
Redundant Receive STS-3 Transport – LOS Threshold Value – MSB
0xFF
0x172F
Redundant Receive STS-3 Transport – LOS Threshold Value – LSB
0xFF
0x1730
Reserved
0x00
0x1731
Redundant Receive STS-3 Transport – SF Set Monitor Interval – Byte 2
0x00
0x1732
Redundant Receive STS-3 Transport – SF Set Monitor Interval – Byte 1
0x00
0x1733
Redundant Receive STS-3 Transport – SF Set Monitor Interval – Byte 0
0x00
Reserved
0x00
0x1736
Redundant Receive STS-3 Transport – SF Set Threshold – Byte 1
0x00
0x1737
Redundant Receive STS-3 Transport – SF Set Threshold – Byte 0
0x00
Reserved
0x00
0x173A
Redundant Receive STS-3 Transport – SF Clear Threshold – Byte 1
0x00
0x173B
Redundant Receive STS-3 Transport – SF Clear Threshold – Byte 0
0x00
0x173C
Reserved
0x00
0x173D
Redundant Receive STS-3 Transport – SD Set Monitor Interval – Byte 2
0x00
0x171F
0x1720 – 0x1722
0x1723
0x1724 – 0x1726
0x1727
0x1728 – 0x172A
0x172B
0x172C, 0x172D
0x1734 – 0x1735
0x1738, 0x1739
11
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0x173E
Redundant Receive STS-3 Transport – SD Set Monitor Interval – Byte 1
0x00
0x173F
Redundant Receive STS-3 Transport – SD Set Monitor Interval – Byte 0
0x00
Reserved
0x00
0x1742
Redundant Receive STS-3 Transport – SD Set Threshold – Byte 1
0x00
0x1743
Redundant Receive STS-3 Transport – SD Set Threshold – Byte 0
0x00
Reserved
0x00
0x1746
Redundant Receive STS-3 Transport – SD Clear Threshold – Byte 1
0x00
0x1747
Redundant Receive STS-3 Transport – SD Clear Threshold – Byte 0
0x00
Reserved
0x00
Redundant Receive STS-3 Transport – Force SEF Condition
0x00
Reserved
0x00
Redundant Receive STS-3 Transport – Receive J0 Trace Buffer Control
0x00
Reserved
0x00
0x1752
Redundant Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte
1
0x00
0x1753
Redundant Receive STS-3 Transport – SD Burst Error Count Tolerance – Byte
0
0x00
Reserved
0x00
0x1756
Redundant Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte
1
0x00
0x1757
Redundant Receive STS-3 Transport – SF Burst Error Count Tolerance – Byte
0
0x00
0x1758
Reserved
0x00
0x1759
Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval –
Byte 2
0xFF
0x175A
Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval –
Byte 1
0xFF
0x175B
Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval –
Byte 0
0xFF
0x175C
Reserved
0x00
0x175D
Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval –
Byte 2
0xFF
0x175E
Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval –
Byte 1
0xFF
0x175F
Redundant Receive STS-3 Transport – Receive SF Clear Monitor – Byte 0
0xFF
Reserved
0x00
Redundant Receive STS-3 Transport – Auto AIS Control Register
0x00
0x1740, 0x1741
0x1744, 0x1745
0x1748 – 0x174A
0x174B
0x174C, 0x174E
0x174F
0x1750, 0x1751
0x1754, 0x1755
0x1760 – 0x1762
0x1763
12
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0x1764 – 0x1766
Reserved
0x00
Redundant Receive STS-3 Transport – Serial Port Control Register
0x00
Reserved
0x00
Redundant Receive STS-3 Transport – Auto AIS (in Downstream STS-1s)
Control Register
0x000
Reserved
0x00
0x177A
Redundant Receive STS-3 Transport – TOH Capture Indirect Address
0x00
0x177B
Redundant Receive STS-3 Transport – TOH Capture Indirect Address
0x00
0x177C
Redundant Receive STS-3 Transport – TOH Capture Indirect Data
0x00
0x177D
Redundant Receive STS-3 Transport – TOH Capture Indirect Data
0x00
0x177E
Redundant Receive STS-3 Transport – TOH Capture Indirect Data
0x00
0x177F
Redundant Receive STS-3 Transport – TOH Capture Indirect Data
0x00
Reserved
0x00
0x1767
0x1768 – 0x176A
0x176B
0x176C – 0x1779
0x1780 – 0x17FF
RECEIVE SONET POH PROCESSOR BLOCK CONTROL REGISTERS
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04
0xN000 – 0xN181
Reserved
0x00
0xN182
Receive SONET Path – Control Register – Byte 1
0x00
0xN183
Receive SONET Path – Control Register – Byte 0
0x00
Reserved
0x00
0xN186
Receive SONET Path – Status Register – Byte 1
0x00
0xN187
Receive SONET Path – Status Register – Byte 0
0x00
0xN188
Reserved
0x00
0xN189
Receive SONET Path – Interrupt Status Register – Byte 2
0x00
0xN18A
Receive SONET Path – Interrupt Status Register – Byte 1
0x00
0xN18B
Receive SONET Path – Interrupt Status Register – Byte 0
0x00
0xN18C
Reserved
0x00
0xN18D
Receive SONET Path – Interrupt Enable Register – Byte 2
0x00
0xN18E
Receive SONET Path – Interrupt Enable Register – Byte 1
0x00
0xN18F
Receive SONET Path – Interrupt Enable Register – Byte 0
0x00
Reserved
0x00
Receive SONET Path – SONET Receive RDI-P Register
0x00
Reserved
0x00
0xN196
Receive SONET Path – Received Path Label Register
0x00
0xN197
Receive SONET Path – Expected Path Label Register
0x00
0xN184, 0xN185
0xN190 – 0xN192
0xN193
0xN194, 0xN195
13
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0xN198
Receive SONET Path – B3 Error Count Register – Byte 3
0x00
0xN199
Receive SONET Path – B3 Error Count Register – Byte 2
0x00
0xN19A
Receive SONET Path – B3 Error Count Register – Byte 1
0x00
0xN19B
Receive SONET Path – B3 Error Count Register – Byte 0
0x00
0xN19C
Receive SONET Path – REI-P Error Count Register – Byte 3
0x00
0xN19D
Receive SONET Path – REI-P Error Count Register – Byte 2
0x00
0xN19E
Receive SONET Path – REI-P Error Count Register – Byte 1
0x00
0xN19F
Receive SONET Path – REI-P Error Count Register – Byte 0
0x00
Reserved
0x00
0xN1A3
Receive SONET Path – Receiver J1 Control Register
0x00
0xN1A4,
0xN1A5
Reserved
0xN1A6
Receive SONET Path – Pointer Value – Byte 1
0x00
0xN1A7
Receive SONET Path – Pointer Value – Byte 0
0x00
Reserved
0x00
Receive SONET Path – Loss of Pointer – Concatenation Status Register
0x00
Reserved
0x00
Receive SONET Path – AIS - Concatenation Status Register
0x00
Reserved
0x00
Receive SONET Path – AUTO AIS Control Register
0x00
Reserved
0x00
Receive SONET Path – Serial Port Control Register
0x00
Reserved
0x00
Receive SONET Path – SONET Receive Auto Alarm Register – Byte 0
0x00
Reserved
0x00
Receive SONET Path – Receive J1 Capture Register
0x00
Reserved
0x00
Receive SONET Path – Receive B3 Capture Register
0x00
Reserved
0x00
Receive SONET Path – Receive C2 Capture Register
0x00
Reserved
0x00
Receive SONET Path – Receive G1 Byte Capture Register
0x00
Reserved
0x00
0xN1A0 – 0xN1A2
0xN1A8 – 0xN1AA
0xN1AB
0xN1AC – 0xN1B2
0xN1B3
0xN1B4 – 0xN1BA
0xN1BB
0xN1BC –
0xN1BE
0xN1BF
0xN1C0 – 0xN1C2
0xN1C3
0xN1C4 – 0xN1D2
0xN1D3
0xN1D4 – 0xN1D6
0xN1D7
0xN1D8 –
0xN1DA
0xN1DB
0xN1DC –
0xN1DE
0xN1DF
0xN1E0 – 0xN1E2
14
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xN1E3
0xN1E4 – 0xN1E6
0xN1E7
0xN1E8 – 0xN1EA
0xN1EB
0xN1EC –
0xN1EE
0xN1EF
0xN1F0 – 0xN1F2
0xN1F3
0xN1F4 – 0xN1FF
Receive SONET Path – Receive F2 Byte Capture Register
0x00
Reserved
0x00
Receive SONET Path – Receive H4 Byte Capture Register
0x00
Reserved
0x00
Receive SONET Path – Receive Z3 Byte Capture Register
0x00
Reserved
0x00
Receive SONET Path – Receive Z4 (K3) Byte Capture Register
0x00
Reserved
0x00
Receive SONET Path – Receive Z5 Byte Capture Register
0x00
Reserved
RECEIVE SONET POH PROCESSOR BLOCK – RECEIVE J1 (PATH) TRACE MESSAGE BUFFER
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04
0xN500 – 0xN53F
Receive SONET POH Processor Block – Receive J1 (Path) Trace Message
Buffer – Expected and Received
0x00
0xN540 – 0xN5FF
Reserved
0x00
RECEIVE ATM CELL PROCESSOR/ PPP CELL PROCESSOR BLOCK CONTROL REGISTERS
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04
0xN700
Receive ATM Control – Receive ATM Control Register - Byte 3
0x00
0xN701
Receive ATM Control – Receive ATM Control Register – Byte 2
0x00
0xN702
Receive ATM Control – Receive ATM Control Register – Byte 1
0x00
0xN703
Receive ATM Cell/PPP Control – Receive ATM Control Register – Byte 0
0x00
Reserved
0x00
Receive ATM Status Register- Channel 0
0x00
Reserved
0x00
0xN70A
Receive ATM Interrupt Status Register – Byte 1
0x00
0xN70B
Receive ATM Cell/PPP Processor Interrupt Status Register – Byte 0
0x00
Reserved
0x00
0xN70E
Receive ATM Cell Processor Block Interrupt Enable Register – Byte 1
0x00
0xN70F
Receive ATM Cell/PPP Processor Block Interrupt Enable Register – Byte 0
0x00
0xN710
Receive PPP Processor – Receive Good PPP Packet Count Register – Byte 3
0x00
0xN711
Receive PPP Processor – Receive Good PPP Packet Count Register – Byte 2
0x00
0xN712
Receive PPP Processor – Receive Good PPP Packet Count Register – Byte 1
0x00
0xN713
Receive ATM Cell Insertion/Extraction Memory Control Register
0x00
0xN704 –
0xN706
0xN707
0xN708 –
0xN709
0xN70C –
0xN70D
15
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Receive PPP Processor – Receive Good PPP Packet Count Register – Byte 0
0xN714
Receive ATM Cell Insertion/Extraction Memory Data Register – Byte 3
0x00
Receive PPP Processor – Receive FCS Error Count Register – Byte 3
0xN715
Receive ATM Cell Insertion/Extraction Memory Data Register – Byte 2
0x00
Receive PPP Processor – Receive FCS Error Count Register – Byte 2
0xN716
Receive ATM Cell Insertion/Extraction Memory Data Register – Byte 1
0x00
Receive PPP Processor – Receive FCS Error Count Register – Byte 1
0xN717
Receive ATM Cell Insertion/Extraction Memory Data Register – Byte 0
0x00
Receive PPP Processor – Receive FCS Error Count Register – Byte 0
0xN718
Receive ATM Programmable User Defined Field Register – Byte 3
0x00
Receive PPP Processor – Receive ABORT Count Register – Byte 3
0xN719
Receive ATM Programmable User Defined Field Register – Byte 2
0x00
Receive PPP Processor – Receive ABORT Count Register – Byte 2
0xN71A
Receive ATM Programmable User Defined Field Register – Byte 1
0x00
Receive PPP Processor – Receive ABORT Count Register – Byte 1
0xN71B
Receive ATM Programmable User Defined Field Register – Byte 0
0x00
Receive PPP Processor – Receive ABORT Count Register – Byte 0
0xN71C
Receive PPP Processor – Receive RUNT PPP Count Register – Byte 3
0x00
0xN71D
Receive PPP Processor – Receive RUNT PPP Count Register – Byte 2
0x00
0xN71E
Receive PPP Processor – Receive RUNT PPP Count Register – Byte 1
0x00
0xN71F
Receive PPP Processor – Receive RUNT PPP Count Register – Byte 0
0x00
0xN720
Receive ATM Controller - Test Cell Header – Byte 1
0x00
0xN721
Receive ATM Controller – Test Cell Header – Byte 2
0x00
0xN722
Receive ATM Controller – Test Cell Header – Byte 3
0x00
0xN723
Receive ATM Controller – Test Cell Header – Byte 4
0x00
0xN724
Receive ATM Controller – Test Cell Error Counter – Byte 3
0x00
0xN725
Receive ATM Controller – Test Cell Error Counter – Byte 2
0x00
0xN726
Receive ATM Controller – Test Cell Error Counter – Byte 1
0x00
0xN727
Receive ATM Controller – Test Cell Error Counter – Byte 0
0x00
0xN728
Receive ATM Controller – Receive ATM Cell Count – Byte 3
0x00
0xN729
Receive ATM Controller – Receive ATM Cell Count – Byte 2
0x00
0xN72A
Receive ATM Controller – Receive ATM Cell Count – Byte 1
0x00
0xN72B
Receive ATM Controller – Receive ATM Cell Count – Byte 0
0x00
0xN72C
Receive ATM Controller – Receive ATM Discard Cell Count – Byte 3
0x00
0xN72D
Receive ATM Controller – Receive ATM Discard Cell Count – Byte 2
0x00
16
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xN72E
Receive ATM Controller – Receive ATM Discard Cell Count – Byte 1
0x00
0xN72F
Receive ATM Controller – Receive ATM Discard Cell Count – Byte 0
0x00
0xN730
Receive ATM Controller – Receive ATM Correctable HEC Cell Counter – Byte
3
0x00
0xN731
Receive ATM Controller – Receive ATM Correctable HEC Cell Counter – Byte
2
0x00
0xN732
Receive ATM Controller – Receive ATM Correctable HEC Cell Counter – Byte
1
0x00
0xN733
Receive ATM Controller – Receive ATM Correctable HEC Cell Counter – Byte
0
0x00
0xN734
Receive ATM Controller – Receive ATM Uncorrectable HEC Cell Counter –
Byte 3
0x00
0xN735
Receive ATM Controller – Receive ATM Uncorrectable HEC Cell Counter –
Byte 2
0x00
0xN736
Receive ATM Controller – Receive ATM Uncorrectable HEC Cell Counter –
Byte 1
0x00
0xN737
Receive ATM Controller – Receive ATM Uncorrectable HEC Cell Counter –
Byte 0 –Channel 0
0x00
Reserved
0x00
0xN743
Receive ATM Controller – Receive ATM Filter # 0 Control Register
0x00
0xN744
Receive ATM Controller – Receive ATM Filter # 0 Pattern – Header Byte 1
0x00
0xN745
Receive ATM Controller – Receive ATM Filter # 0 Pattern – Header Byte 2
0x00
0xN746
Receive ATM Controller – Receive ATM Filter # 0 Pattern – Header Byte 3
0x00
0xN747
Receive ATM Controller – Receive ATM Filter # 0 Pattern – Header Byte 4
0x00
0xN748
Receive ATM Controller – Receive ATM Filter # 0 Check – Header Byte 1
0x00
0xN749
Receive ATM Controller – Receive ATM Filter # 0 Check – Header Byte 2
0x00
0xN74A
Receive ATM Controller – Receive ATM Filter # 0 Check – Header Byte 3
0x00
0xN74B
Receive ATM Controller – Receive ATM Filter # 0 Check – Header Byte 4
0x00
0xN74C
Receive ATM Controller – Filter # 0 - Filtered Cell Count Register – Byte 3
0x00
0xN74D
Receive ATM Controller – Filter # 0 - Filtered Cell Count Register – Byte 2
0x00
0xN74E
Receive ATM Controller – Filter # 0 - Filtered Cell Count Register – Byte 1
0x00
0xN74F
Receive ATM Controller – Filter # 0 - Filtered Cell Count Register – Byte 0
0x00
Reserved
0x00
0xN753
Receive ATM Controller – Receive ATM Filter # 1 Control Register
0x00
0xN754
Receive ATM Controller – Receive ATM Filter # 1 Pattern – Header Byte 1
0x00
0xN755
Receive ATM Controller – Receive ATM Filter # 1 Pattern – Header Byte 2
0x00
0xN738 –
0xN742
0xN750 –
0xN752
17
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0xN756
Receive ATM Controller – Receive ATM Filter # 1 Pattern – Header Byte 3
0x00
0xN757
Receive ATM Controller – Receive ATM Filter # 1 Pattern – Header Byte 4
0x00
0xN758
Receive ATM Controller – Receive ATM Filter # 1 Check – Header Byte 1
0x00
0xN759
Receive ATM Controller – Receive ATM Filter # 1 Check – Header Byte 2
0x00
0xN75A
Receive ATM Controller – Receive ATM Filter # 1 Check – Header Byte 3
0x00
0xN75B
Receive ATM Controller – Receive ATM Filter # 1 Check – Header Byte 4
0x00
0xN75C
Receive ATM Controller – Filter # 1 – Filtered Cell Count Register – Byte 3
0x00
0xN75D
Receive ATM Controller – Filter # 1 - Filtered Cell Count Register – Byte 2
0x00
0xN75E
Receive ATM Controller – Filter # 1 - Filtered Cell Count Register – Byte 1
0x00
0xN75F
Receive ATM Controller – Filter # 1 - Filtered Cell Count Register – Byte 0
0x00
Reserved
0x00
0xN763
Receive ATM Controller – Receive ATM Filter # 2 Control Register
0x00
0xN764
Receive ATM Controller – Receive ATM Filter # 2 Pattern – Header Byte 1
0x00
0xN765
Receive ATM Controller – Receive ATM Filter # 2 Pattern – Header Byte 2
0x00
0xN766
Receive ATM Controller – Receive ATM Filter # 2 Pattern – Header Byte 3
0x00
0xN767
Receive ATM Controller – Receive ATM Filter # 2 Pattern – Header Byte 4
0x00
0xN768
Receive ATM Controller – Receive ATM Filter # 2 Check – Header Byte 1
0x00
0xN769
Receive ATM Controller – Receive ATM Filter # 2 Check – Header Byte 2
0x00
0xN76A
Receive ATM Controller – Receive ATM Filter # 2 Check – Header Byte 3
0x00
0xN76B
Receive ATM Controller – Receive ATM Filter # 2 Check – Header Byte 4
0x00
0xN76C
Receive ATM Controller – Filter # 2 - Filtered Cell Count Register – Byte 3
0x00
0xN76D
Receive ATM Controller – Filter # 2 - Filtered Cell Count Register – Byte 2
0x00
0xN76E
Receive ATM Controller – Filter # 2 - Filtered Cell Count Register – Byte 1
0x00
0xN76F
Receive ATM Controller – Filter # 2 - Filtered Cell Count Register – Byte 0
0x00
Reserved
0x00
0xN773
Receive ATM Controller – Receive ATM Filter # 3 Control Register
0x00
0xN774
Receive ATM Controller – Receive ATM Filter # 3 Pattern – Header Byte 1
0x00
0xN775
Receive ATM Controller – Receive ATM Filter # 3 Pattern – Header Byte 2
0x00
0xN776
Receive ATM Controller – Receive ATM Filter # 3 Pattern – Header Byte 3
0x00
0xN777
Receive ATM Controller – Receive ATM Filter # 3 Pattern – Header Byte 4
0x00
0xN778
Receive ATM Controller – Receive ATM Filter # 3 Check – Header Byte 1
0x00
0xN779
Receive ATM Controller – Receive ATM Filter # 3 Check – Header Byte 2
0x00
0xN760 –
0xN762
0xN770 –
0xN772
18
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xN77A
Receive ATM Controller – Receive ATM Filter # 3 Check – Header Byte 3
0x00
0xN77B
Receive ATM Controller – Receive ATM Filter # 3 Check – Header Byte 4
0x00
0xN77C
Receive ATM Controller – Filter # 3 - Filtered Cell Count Register – Byte 3
0x00
0xN77D
Receive ATM Controller – Filter # 3 - Filtered Cell Count Register – Byte 2
0x00
0xN77E
Receive ATM Controller – Filter # 3 - Filtered Cell Count Register – Byte 1
0x00
0xN77F
Receive ATM Controller – Filter # 3 - Filtered Cell Count Register – Byte 0
0x00
Reserved
0x00
0xN780 –
0xN901
TRANSMIT ATM CELL PROCESSOR/ PPP PROCESSOR BLOCK REGISTERS
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04
0xNF00
Transmit ATM Cell Processor Control Register – Byte 3
0x00
0xNF01
Transmit ATM Cell Processor Control Register – Byte 2
0x00
0xNF02
Transmit ATM Cell Processor Control Register – Byte 1
0x00
0xNF03
Transmit ATM Cell/PPP Processor Control Register – Byte 0
0x00
0xNF04
Transmit ATM Status Register
0x00
Reserved
0x00
Transmit ATM Cell/PPP Processor Interrupt Status Register
0x00
Reserved
0x00
Transmit ATM Cell/PPP Processor Interrupt Enable Register
0x00
Reserved
0x00
0xNF13
Transmit ATM Cell Insertion/Extraction Memory Control Register
0x00
0xNF14
Transmit ATM Cell Insertion/Extraction Memory – Byte 3
0x00
0xNF15
Transmit ATM Cell Insertion/Extraction Memory – Byte 2
0x00
0xNF16
Transmit ATM Cell Insertion/Extraction Memory – Byte 1
0x00
0xNF17
Transmit ATM Cell Insertion/Extraction Memory – Byte 0
0x00
0xNF18
Transmit ATM Cell – Idle Cell Header Byte # 1 Register
0x00
0xNF19
Transmit ATM Cell – Idle Cell Header Byte # 2 Register
0x00
0xNF1A
Transmit ATM Cell – Idle Cell Header Byte # 3 Register
0x00
0xNF1B
Transmit ATM Cell – Idle Cell Header Byte # 4 Register
0x00
Reserved
0x00
0xNF1F
Transmit ATM Cell – Idle Cell Payload Byte Register
0x00
0xNF20
Transmit ATM Cell – Test Cell Header Byte # 1 Register
0x00
0xNF21
Transmit ATM Cell – Test Cell Header Byte # 2 Register
0x00
0xNF05 –
0xNF0A
0xNF0B
0xNF0C –
0xNF0E
0xNF0F
0xNF10 –
0xNF12
0xNF1C –
0xNF1E
19
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0xNF22
Transmit ATM Cell – Test Cell Header Byte # 3 Register
0x00
0xNF23
Transmit ATM Cell – Test Cell Header Byte # 4 Register
0x00
Reserved
0x00
0xNF28
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF29
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF2A
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF2B
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
0xNF2C
Transmit ATM Cell – Discard Cell Count Register – Byte 3
0x00
0xNF2D
Transmit ATM Cell – Discard Cell Count Register – Byte 2
0x00
0xNF2E
Transmit ATM Cell – Discard Cell Count Register – Byte 1
0x00
0xNF2F
Transmit ATM Cell – Discard Cell Count Register – Byte 0
0x00
0xNF30
Transmit ATM Cell – HEC Byte Error Count Register – Byte 3
0x00
0xNF31
Transmit ATM Cell – HEC Byte Error Count Register – Byte 2
0x00
0xNF32
Transmit ATM Cell – HEC Byte Error Count Register – Byte 1
0x00
0xNF33
Transmit ATM Cell – HEC Byte Error Count Register – Byte 0
0x00
0xNF34
Transmit ATM Cell – Parity Error Count Register – Byte 3
0x00
0xNF35
Transmit ATM Cell – Parity Error Count Register – Byte 2
0x00
0xNF36
Transmit ATM Cell – Parity Error Count Register – Byte 1
0x00
0xNF37
Transmit ATM Cell – Parity Error Count Register – Byte 0
0x00
Reserved
0x00
0xNF43
Transmit ATM Controller – Transmit ATM Filter # 0 Control Register
0x00
0xNF44
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 1
0x00
0xNF45
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 2
0x00
0xNF46
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 3
0x00
0xNF47
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 4
0x00
0xNF48
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 1
0x00
0xNF49
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 2
0x00
0xNF4A
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 3
0x00
0xNF4B
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 4
0x00
0xNF4C
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF4D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF4E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF24 –
0xNF27
0xNF38 –
0xNF42
20
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xNF4F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF53
Transmit ATM Controller – Transmit ATM Filter # 1 Control Register
0x00
0xNF54
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 1
0x00
0xNF55
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 2
0x00
0xNF56
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 3
0x00
0xNF57
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 4
0x00
0xNF58
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 1
0x00
0xNF59
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 2
0x00
0xNF5A
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 3
0x00
0xNF5B
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 4
0x00
0xNF5C
Transmit ATM Cell – Cell Count Register - Byte 3
0x00
0xNF5D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF5E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF5F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF63
Transmit ATM Controller – Transmit ATM Filter # 2 Control Register
0x00
0xNF64
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 1
0x00
0xNF65
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 2
0x00
0xNF66
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 3
0x00
0xNF67
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 4
0x00
0xNF68
Transmit ATM Controller – Transmit ATM Filter # 2 Check – Header Byte 1
0x00
0xNF69
Transmit ATM Controller – Transmit ATM Filter # 2 Check – Header Byte 2
0x00
0xNF6A
Transmit ATM Controller – Transmit ATM Filter # 2 Check – Header Byte 3
0x00
0xNF6B
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 4
0x00
0xNF6C
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF6D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF6E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF6F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF73
Transmit ATM Controller – Transmit ATM Filter # 3 Control Register
0x00
0xNF74
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 1
0x00
0xNF50 –
0xNF52
0xNF60 –
0xNF62
0xNF70 –
0xNF72
21
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0xNF75
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 2
0x00
0xNF76
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 3
0x00
0xNF77
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 4
0x00
0xNF78
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 1
0x00
0xNF79
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 2
0x00
0xNF7A
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 3
0x00
0xNF7B
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 4
0x00
0xNF7C
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF7D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF7E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF7F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF80 –
0xN102
RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK REGISTERS
Note:
N represents the “Channel Number” and ranges in value from 0x05 to 0x07
0xN103
Receive STS-1 Transport Control Register – Byte 0
0x00
Reserved
0x00
0xN106
Receive STS-1 Transport Status Register – Byte 1
0x00
0xN107
Receive STS-1 Transport Status Register – Byte 0
0x02
0xN108
Reserved
0x00
0xN109
Receive STS-1 Transport Interrupt Status Register – Byte 2
0x00
0xN10A
Receive STS-1 Transport Interrupt Status Register – Byte 1
0x00
0xN10B
Receive STS-1 Transport Interrupt Status Register – Byte 0
0x00
0xN10C
Reserved
0x00
0xN10D
Receive STS-1 Transport Interrupt Enable Register – Byte 2
0x00
0xN10E
Receive STS-1 Transport Interrupt Enable Register – Byte 1
0x00
0xN10F
Receive STS-1 Transport Interrupt Enable Register – Byte 0
0x00
0xN110
Receive STS-1 Transport B1 Error Count – Byte 3
0x00
0xN111
Receive STS-1 Transport B1 Error Count – Byte 2
0x00
0xN112
Receive STS-1 Transport B1 Error Count – Byte 1
0x00
0xN113
Receive STS-1 Transport B1 Error Count – Byte 0
0x00
0xN114
Receive STS-1 Transport B2 Error Count – Byte 3
0x00
0xN115
Receive STS-1 Transport B2 Error Count – Byte 2
0x00
0xN116
Receive STS-1 Transport B2 Error Count – Byte 1
0x00
0xN104 – 0xN105
22
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xN117
Receive STS-1 Transport B2 Error Count – Byte 0
0x00
0xN118
Reserved
0x00
0xN119
Receive STS-1 Transport REI-L Error Count – Byte 3
0x00
0xN11A
Receive STS-1 Transport REI-L Error Count – Byte 2
0x00
0xN11B
Receive STS-1 Transport REI-L Error Count – Byte 1
0x00
0xN11C
Receive STS-1 Transport REI-L Error Count – Byte 0
0x00
Reserved
0x00
Receive STS-1 Transport – Received K1 Byte Value
0x00
Reserved
0x00
Receive STS-1 Transport – Received K2 Byte Value
0x00
Reserved
0x00
Receive STS-1 Transport – Received S1 Byte Value
0x00
Reserved
0x00
0xN12E
Receive STS-1 Transport – LOS Threshold Value – MSB
0xFF
0xN12F
Receive STS-1 Transport – LOS Threshold Value – LSB
0xFF
0xN130
Reserved
0x00
0xN131
Receive STS-1 Transport – Receive SF Set Monitor Interval – Byte 2
0x00
0xN132
Receive STS-1 Transport – Receive SF Set Monitor Interval – Byte 1
0x00
0xN133
Receive STS-1 Transport – Receive SF Set Monitor Interval – Byte 0
0x00
Reserved
0x00
0xN136
Receive STS-1 Transport – Receive SF Set Threshold – Byte 1
0x00
0xN137
Receive STS-1 Transport – Receive SF Set Threshold – Byte 0
0x00
Reserved
0x00
0xN13A
Receive STS-1 Transport – Receive SF Clear Threshold – Byte 1
0x00
0xN13B
Receive STS-1 Transport – Receive SF Clear Threshold – Byte 0
0x00
0xN13C
Reserved
0x00
0xN13D
Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte 2
0x00
0xN13E
Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte 1
0x00
0xN13F
Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte 0
0x00
Reserved
0x00
0xN142
Receive STS-1 Transport – Receive SD Set Threshold – Byte 1
0x00
0xN143
Receive STS-1 Transport – Receive SD Set Threshold – Byte 0
0x00
Reserved
0x00
0xN11D – 0xN11E
0xN11F
0xN120 – 0xN122
0xN123
0xN124 – 0xN126
0xN127
0xN128 – 0xN12D
0xN134, 0xN135
0xN138 – 0xN139
0xN140 – 0xN141
0xN144, 0xN145
23
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0xN146
Receive STS-1 Transport – Receive SD Clear Threshold – Byte 1
0x00
0xN147
Receive STS-1 Transport – SD Clear Threshold – Byte 0
0x00
Reserved
0x00
Receive STS-1 Transport – Force SEF Condition
0x00
Reserved
0x00
Receive STS-1 Transport – Receive J0 Trace Buffer Control Register
0x00
0xN14B – 0xN14A
0xN14B
0xN14C – 0xN14E
0xN14F
0xN150 – 0xN151
Reserved
0xN152
Receive STS-1 Transport – Receive SD Burst Error Count Tolerance – Byte 1
0x00
0xN153
Receive STS-1 Transport – Receive SD Burst Error Count Tolerance – Byte 0
0x00
Reserved
0x00
0xN156
Receive STS-1 Transport – Receive SF Burst Error Count Tolerance – Byte 1
0x00
0xN157
Receive STS-1 Transport – Receive SF Burst Error Count Tolerance – Byte 0
0x00
0xN158
Reserved
0x00
0xN159
Receive STS-1 Transport – Receive SD Clear Monitor Interval – Byte 2
0x00
0xN15A
Receive STS-1 Transport – Receive SD Clear Monitor Interval – Byte 1
0x00
0xN15B
Receive STS-1 Transport – Receive SD Clear Monitor Interval – Byte 0
0x00
0xN15C
Reserved
0x00
0xN15D
Receive STS-1 Transport – Receive SF Clear Monitor Interval – Byte 2
0x00
0xN15E
Receive STS-1 Transport – Receive SF Clear Monitor Interval – Byte 1
0x00
0xN15F
Receive STS-1 Transport – Receive SF Clear Monitor Interval – Byte 0
0x00
Reserved
0x00
Receive STS-1 Transport – Auto AIS Control Register
0x00
Reserved
0x00
Receive STS-1 Transport – Auto AIS (in Downstream STS-1s) Control
Register
0x00
Reserved
0x00
Receive STS-1 Path – Control Register – Byte 2
0x00
Reserved
0x00
0xN154, 0xN155
0xN160 – 0xN162
0xN163
0xN164 – 0xN16A
0xN16B
0xN16C – 0xN182
0xN183
0xN184 - 0xN185
0xN186
Receive STS-1 Path – Control Register – Byte 1
0xN187
Receive STS-1 Path – Status Register – Byte 0
0x00
0xN188
Reserved
0x00
0xN189
Receive STS-1 Path – Interrupt Status Register – Byte 2
0x00
0xN18A
Receive STS-1 Path – Interrupt Status Register – Byte 1
0x00
0xN18B
Receive STS-1 Path – Interrupt Status Register – Byte 0
0x00
24
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xN18C
Reserved
0x00
0xN18D
Receive STS-1 Path – Interrupt Enable Register – Byte 2
0x00
0xN18E
Receive STS-1 Path – Interrupt Enable Register – Byte 1
0x00
0xN18F
Receive STS-1 Path – Interrupt Enable Register – Byte 0
0x00
Reserved
0x00
Receive STS-1 Path – SONET Receive RDI-P Register
0x00
Reserved
0x00
0xN196
Receive STS-1 Path – Received Path Label Value (C2 Byte) Register
0x00
0xN197
Receive STS-1 Path – Expected Path Label Value (C2 Byte) Register
0x00
0xN198
Receive STS-1 Path – B3 Error Count Register – Byte 3
0x00
0xN199
Receive STS-1 Path – B3 Error Count Register – Byte 2
0x00
0xN19A
Receive STS-1 Path – B3 Error Count Register – Byte 1
0x00
0xN19B
Receive STS-1 Path – B3 Error Count Register – Byte 0
0x00
0xN19C
Receive STS-1 Path – REI-P Error Count Register – Byte 3
0x00
0xN19D
Receive STS-1 Path – REI-P Error Count Register – Byte 2
0x00
0xN19E
Receive STS-1 Path – REI-P Error Count Register – Byte 1
0x00
0xN19F
Receive STS-1 Path – REI-P Error Count Register – Byte 0
0x00
Reserved
0x00
0xN1A6
Receive STS-1 Path – Pointer Value – Byte 1
0x00
0xN1A7
Receive STS-1 Path – Pointer Value – Byte 0
0x00
Reserved
0x00
Receive STS-1 Path – AUTO AIS Control Register
0x00
Reserved
0x00
Receive STS-1 Path – Serial Port Control Register
0x00
Reserved
0x00
Receive STS-1 Path – SONET Receive Auto Alarm Register – Byte 0
0x00
Reserved
0x00
Receive STS-1 Path – Receive J1 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive B3 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive C2 Byte Capture Register
0x00
0xN190 – 0xN192
0xN193
0xN194, 0xN195
0xN1A0 – 0xN1A5
0xN1A8 – 0xN1BA
0xN1BB
0xN1BC –
0xN1BE
0xN1BF
0xN1C0 – 0xN1C2
0xN1C3
0xN1C4 –0xN1D2
0xN1D3
0xN1D4 – 0xN1D6
0xN1D7
0xN1D8 –
0xN1DA
0xN1DB
25
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
0xN1DC –
0xN1DE
0xN1DF
0xN1E0 – 0xN1E2
0xN1E3
0xN1E4 – 0xN1E6
0xN1E7
0xN1E8 – 0xN1EA
0xN1EB
0xN1EC –
0xN1EE
0xN1EF
0xN1F0 – 0xN1F2
0xN1F3
0xN1F4 – 0xN1FF
Rev222...000...000
Reserved
0x00
Receive STS-1 Path – Receive G1 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive F2 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive H4 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive Z3 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive Z4 (K3) Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive Z5 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 TOH Processor Block – Receive J0 (Path) Trace Message Buffer
Note:
N represents the “Channel Number” and ranges in value from 0x05 to 0x07
0xN300 – 0xN33F
Receive STS-1 POH Processor Block – Receive J0 (Path) Trace Message
Buffer – Expected and Received
0x00
0xN340 – 0xN3FF
Reserved
0x00
RECEIVE STS-1 POH PROCESSOR BLOCK – RECEIVE J1 (PATH) TRACE MESSAGE BUFFER
Note:
N represents the “Channel Number” and ranges in value from 0x05 to 0x07
0xN500 – 0xN53F
Receive STS-1 POH Processor Block – Receive J1 (Path) Trace Message
Buffer – Expected and Received
0x00
0xN540 – 0xN5FF
Reserved
0x00
DS3/E3 MAPPER BLOCK REGISTER
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04
0xNA00 – 0xNB00
Unused
0x00
0xNB01
Mapper Control Register – Byte 2
0x00
0xNB02
Mapper Control Register – Byte 1
0x03
0xNB03
Mapper Control Register – Byte 0
0x80
Unused
0x00
0xNB06
Receive Mapper Status Register – Byte 1
0x03
0xNB07
Receive Mapper Status Register – Byte 0
0x00
Unused
0x00
Receive Mapper Interrupt Status Register – Byte 0
0x00
0xNB04, 0xNB05
0xNB08 – 0xNB0A
0xNB0B
26
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xNB0C –
0xNB0E
0xNB0F
0xNB10 – 0xNB12
0xNB13
0xNB14 – 0xNBFF
Unused
0x00
Receive Mapper Interrupt Enable Register – Byte 0
0x00
Unused
0x00
T3/E3 Routing Register Byte
0x00
Reserved
0x00
TRANSMIT SONET POH PROCESSOR BLOCK REGISTERS
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04)
0xN800 – 0xN981
Reserved
0x00
0xN982
Transmit SONET Path – SONET Control Register – Byte 1
0x00
0xN983
Transmit SONET Path – SONET Control Register – Byte 0
0x00
Reserved
0x00
Transmit SONET Path – Transmitter J1 Byte Value Register
0x00
Reserved
0x00
0xN996
Transmit SONET Path – B3 Byte Control Register
0x00
0xN997
Transmit SONET Path – B3 Byte Mask Register
0x00
Reserved
0x00
Transmit SONET Path – Transmit C2 Byte Value Register
0x00
Reserved
0x00
Transmit SONET Path – Transmit G1 Byte Value Register
0x00
Reserved
0x00
Transmit SONET Path – Transmit F2 Byte Value Register
0x00
Reserved
0x00
Transmit SONET Path – Transmit H4 Byte Value Register
0x00
Reserved
0x00
Transmit SONET Path – Transmit Z3 Byte Value Register
0x00
Reserved
0x00
Transmit SONET Path – Transmit Z4 Byte Value Register
0x00
Reserved
0x00
Transmit SONET Path – Transmit Z5 Byte Value Register
0x00
Reserved
0x00
Transmit SONET Path – Transmit Path Control Register – Byte 0
0x00
Reserved
0x00
0xN984 –
0xN8992
0xN993
0xN994 – 0xN995
0xN998 – 0xN99A
0xN99B
0xN99C – 0xN99E
0xN99F
0xN9A0 – 0xN9A2
0xN9A3
0xN9A4 – 0xN9A6
0xN9A7
0xN9A8 – 0xN9AA
0xN9AB
0xN9AC –
0xN9AE
0xN9AF
0xN9B0 – 0xN9B2
0xN9B3
0xN9B4 – 0xN9B6
0xN9B7
0xN9B8 – 0xN9BA
27
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
0xN9BB
Rev222...000...000
Transmit SONET Path – Transmit J1 Control Register
0x00
Reserved
0x00
Transmit SONET Path – Transmit Arbitrary H1 Pointer Register
0x94
Reserved
0x00
Transmit SONET Path – Transmit Arbitrary H2 Pointer Register
0x00
Reserved
0x00
0xN9C6
Transmit SONET Path – Transmit Pointer Byte Register – Byte 1
0x02
0xN9C7
Transmit SONET Path – Transmit Pointer Byte Register – Byte 0
0x0A
0xN9C8
Reserved
0x00
0xN9C9
Transmit SONET Path – RDI-P Control Register – Byte 2
0x40
0xN9CA
Transmit SONET Path – RDI-P Control Register – Byte 1
0xC0
0xN9CB
Transmit SONET Path – RDI-P Control Register – Byte 0
0xA0
Reserved
0x00
Transmit SONET Path – Transmit Path Serial Port Control Register
0x00
Reserved
0x00
0xN9BC –
0xN9BE
0xN9BF
0xN9C0 – 0xN9C2
0xN9C3
0xN9C4 – 0xN9C5
0xN9CC –
0xN9CE
0xN9CF
0xN9D0 – 0xN9FF
TRANSMIT SONET POH PROCESSOR BLOCK – TRANSMIT J1 (PATH) TRACE MESSAGE BUFFER
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04
0xND00 – 0xND3F
Transmit SONET POH Processor Block – Transmit J1 (Path) Trace Message
Buffer
0x00
0xND40 – 0xNEFF
Reserved
0x00
TRANSMIT STS-1 TOH AND POH PROCESSOR BLOCK REGISTERS
Note:
N represents the “Channel Numbers” and ranges in value from 0x05 to 0x07)
0xN800 – 0xN901
Reserved
0x00
0xN902
Transmit STS-1 Transport – SONET Transmit Control Register – Byte 1
0x00
0xN903
Transmit STS-1 Transport – SONET Transmit Control Register – Byte 0
0x00
Reserved
0x00
Transmit STS-1 Transport – B1 Byte Error Mask Register
0x00
Reserved
0x00
Transmit STS-1 Transport – Transmit B2 Bit Error Mask Register – Byte 0
0x00
Reserved
0x00
0xN92E
Transmit STS-1 Transport – K1K2 (APS) Value Register – Byte 1
0x00
0xN92F
Transmit STS-1 Transport – K1K2 (APS) Value Register – Byte 0
0x00
Reserved
0x00
0xN904 – 0xN922
0xN923
0xN924 – 0xN92A
0xN92B
0xN92C – 0xN92D
0xN930 – 0xN932
28
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xN933
Transmit STS-1 Transport – RDI-L Control Register
0x00
Reserved
0x00
Transmit STS-1 Transport – M0M1 Value Register
0x00
Reserved
0x00
Transmit STS-1 Transport – S1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-1 Transport – F1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-1 Transport – E1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-1 Transport – E2 Byte Value Register
0x00
Reserved
0x00
Transmit STS-1 Transport – J0 Byte Value Register
0x00
Reserved
0x00
Transmit STS-1 Transport – J0 Byte Control Register
0x00
Reserved
0x00
0xN982
Transmit STS-1 Path – SONET Control Register – Byte 1
0x00
0xN983
Transmit STS-1 Path – SONET Control Register – Byte 0
0x00
Reserved
0x00
Transmit STS-1 Path – Transmitter J1 Byte Value Register
0x00
Reserved
0x00
0xN996
Transmit STS-1 Path – B3 Byte Control Register
0x00
0xN997
Transmit STS-1 Path – B3 Byte Mask Register
0x00
Reserved
0x00
Transmit STS-1 Path – Transmit C2 Byte Value Register
0x00
Reserved
0x00
Transmit STS-1 Path – Transmit G1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-1 Path – Transmit F2 Byte Value Register
0x00
Reserved
0x00
Transmit STS-1 Path – Transmit H4 Value Register
0x00
Reserved
0x00
Transmit STS-1 Path – Transmit Z3 Value Register
0x00
0xN934 – 0xN936
0xN937
0xN938 - 0xN93A
0xN93B
0xN93C – 0xN93E
0xN93F
0xN940 – 0xN942
0xN943
0xN944 – 0xN946
0xN947
0xN948 – 0xN94A
0xN94B
0xN94C – 0xN94E
0xN94F
0xN950 – 0xN981
0xN984 – 0xN992
0xN993
0xN994 – 0xN995
0xN998 – 0xN99A
0xN99B
0xN99C – 0xN99E
0xN99F
0xN9A0 – 0xN9A2
0xN9A3
0xN9A4 – 0xN9A6
0xN9A7
0xN9A8 – 0xN9AA
0xN9AB
29
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
0xN9AC –
0xN9AE
Rev222...000...000
Reserved
0x00
Transmit STS-1 Path – Transmit Z4 Value Register
0x00
Reserved
0x00
Transmit STS-1 Path – Transmit Z5 Value Register
0x00
Reserved
0x00
Transmit STS-1 Path – Transmit Path Control Register – Byte 0
0x00
Reserved
0x00
Transmit STS-1 Path – Transmit J1 Control Register
0x00
Reserved
0x00
Transmit STS-1 Path – Transmit Arbitrary H1 Pointer Register
0x94
Reserved
0x00
Transmit STS-1 Path – Transmit Arbitrary H2 Pointer Register
0x00
Reserved
0x00
0xN9C6
Transmit STS-1 Path – Transmit Pointer Byte Register – Byte 1
0x02
0xN9C7
Transmit STS-1 Path – Transmit Pointer Byte Register – Byte 0
0x0A
0xN9C8
Reserved
0x00
0xN9C9
Transmit STS-1 Path – RDI-P Control Register – Byte 2
0x40
0xN9C2
Transmit STS-1 Path – RDI-P Control Register – Byte 1
0xC0
0xN9CB
Transmit STS-1 Path – RDI-P Control Register – Byte 0
0xA0
Reserved
0x00
Transmit STS-1 Path – Transmit Path Serial Port Control Register
0x00
Reserved
0x00
0xN9AF
0xN9B0 – 0xN9B2
0xN9B3
0xN9B4 – 0xN9B6
0xN9B7
0xN9B8 – 0xN9BA
0xN9BB
0xN9BC –
0xN9BE
0xN9BF
0xN9C0 – 0xN9C2
0xN9C3
0xN9C4 – 0xN9C5
0xN9CC –
0xN9CE
0xN9CF
0xN9D0 –0xN9FF
TRANSMIT STS-1 TOH PROCESSOR BLOCK – TRANSMIT J0 (PATH) TRACE MESSAGE BUFFER
Note:
N represents the “Channel Number” and ranges in value from 0x05 to 0x07
0xNB00 – 0xNB3F
Transmit STS-1 POH Processor Block – Transmit J0 (Path) Trace Message
Buffer
0x00
0xNB40 – 0xNBFF
Reserved
0x00
TRANSMIT STS-1 POH PROCESSOR BLOCK – TRANSMIT J1 (PATH) TRACE MESSAGE BUFFER
Note:
N represents the “Channel Number” and ranges in value from 0x05 to 0x07
0xND00 – 0xND3F
0xND40 –
0xNDFF
Transmit STS-1 POH Processor Block – Transmit J1 (Path) Trace Message
Buffer
0x00
Reserved
0x00
DS3/E3 FRAMER BLOCK REGISTERS
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04
30
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xN300
Operating Mode Register
0x23
0xN301
I/O Control Register
0xA0
Reserved
0x00
0xN304
Block Interrupt Enable Register
0x00
0xN305
Block Interrupt Status Register
0x00
Reserved
0x00
Test Register
0x00
Reserved
0x00
RxDS3 Configuration and Status Register
0x02
0xN302 – 0xN303
0xN306 – 0xN30B
0xN30C
0xN30D – 0xN30F
0xN310
RxE3 Configuration and Status Register # 1 – G.832
RxE3 Configuration and Status Register # 2 – G.751
0xN311
0x67
RxDS3 Status Register
RxE3 Configuration and Status Register # 2 – G.832
RxE3 Configuration and Status Register # 2 – G.751
0xN312
0x00
RxDS3 Interrupt Enable Register
RxE3 Interrupt Enable Register # 1 – G.832
RxE3 Interrupt Enable Register # 1 – G.751
0xN313
0x00
RxDS3 Interrupt Status Register
RxE3 Interrupt Enable Register # 2 – G.832
RxE3 Interrupt Enable Register # 2 – G.751
0xN314
0x00
RxDS3 Sync Detect Enable Register
RxE3 Interrupt Status Register # 1 – G.832
RxE3 Interrupt Status Register # 1 – G.751
0xN315
RxE3 Interrupt Status Register # 2 – G.832
0x00
RxE3 Interrupt Status Register # 2 – G.751
0xN316
RxDS3 FEAC Register
0x7E
0xN317
RxDS3 FEAC Interrupt Enable/Status Register
0x00
0xN318
RxDS3 LAPD Control Register
0x00
RxE3 LAPD Control Register
0xN319
0x00
RxDS3 LAPD Status Register
RxE3 LAPD Status Register
0xN31A
0x00
RxE3 NR Byte Register – G.832
RxE3 Service Bit Register –G.751
0xN31B
RxE3 GC Byte Register – G.832
0x00
0xN31C
RxE3 TTB-0 Register – G.832
0x00
31
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0xN31D
RxE3 TTB-1 Register – G.832
0x00
0xN31E
RxE3 TTB-2 Register – G.832
0x00
0xN31F
RxE3 TTB-3 Register –G.832
0x00
0xN320
RxE3 TTB-4 Register –G.832
0x00
0xN321
RxE3 TTB-5 Register –G.832
0x00
0xN322
RxE3 TTB-6 Register – G.832
0x00
0xN323
RxE3 TTB-7 Register – G.832
0x00
0xN324
RxE3 TTB-8 Register – G.832
0x00
0xN325
RxE3 TTB-9 Register – G.832
0x00
0xN326
RxE3 TTB-10 Register – G.832
0x00
0xN327
RxE3 TTB-11 Register –G.832
0x00
0xN328
RxE3 TTB-12 Register – G.832
0x00
0xN329
RxE3 TTB-13 Register – G.832
0x00
0xN32A
RxE3 TTB-14 Register – G.832
0x00
0xN32B
RxE3 TTB-15 Register –G.832
0x00
0xN32C
RxE3 SSM Register –G.832
0x00
Reserved
0x00
0xN32F
RxDS3 Pattern Register
0x00
0xN330
TxDS3 Configuration Register
0x00
0xN32D – 0xN32E
TxE3 Configuration Register – G.832
TxE3 Configuration Register – G.751
0xN331
TxDS3 FEAC Configuration and Status Register
0x00
0xN332
TxDS3 FEAC Register
0x7E
0xN333
TxDS3 LAPD Configuration Register
0x08
TxE3 LAPD Configuration Register
0xN334
TxDS3 LAPD Status/Interrupt Register
0x00
TxE3 LAPD Status/Interrupt Register
0xN335
0x00
TxDS3 M-Bit Mask Register
TxE3 GC Byte Register – G.832
TxE3 Service Bits Register – G.751
0xN336
0x00
TxDS3 F-Bit Mask # 1 Register
TxE3 MA Byte Register – G.832
0xN337
0x00
TxDS3 F-Bit Mask # 2 Register
TxE3 NR Byte Register – G.832
32
XRT94L33
Rev222...000...000
0xN338
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
0x00
TxDS3 F-Bit Mask # 3 Register
TxE3 TTB-0 Register – G.832
0xN339
0x00
TxDS3 F-Bit Mask # 4 Register
TxE3 TTB-1 Register – G.832
0xN33A
TxE3 TTB-2 Register – G.832
0x00
0xN33B
TxE3 TTB-3 Register – G.832
0x00
0xN33C
TxE3 TTB-4 Register – G.832
0x00
0xN33D
TxE3 TTB-5 Register – G.832
0x00
0xN33E
TxE3 TTB-6 Register – G.832
0x00
0xN33F
TxE3 TTB-7 Register – G.832
0x00
0xN340
TxE3 TTB-8 Register –G.832
0x00
0xN341
TxE3 TTB-9 Register – G.832
0x00
0xN342
TxE3 TTB-10 Register – G.832
0x00
0xN343
TxE3 TTB-11 Register – G.832
0x00
0xN344
TxE3 TTB-12 Register – G.832
0x00
0xN345
TxE3 TTB-13 Register – G.832
0x00
0xN346
TxE3 TTB-14 Register – G.832
0x00
0xN347
TxE3 TTB-15 Register –G.832
0x00
0xN348
TxE3 FA1 Error Mask Register – G.832
0x00
TxE3 FAS Error Mask Upper Register – G.751
0xN349
TxE3 FA2 Error Mask Register – G.832
0x00
TxE3 FAS Error Mask Lower Register – G.751
0xN34A
0x00
TxE3 BIP-8 Mask Register – G.832
TxE3 BIP-4 Mask Register – G.751
0xN34B
Tx SSB Register – G.832
0x00
0xN34C
TxDS3 Pattern Register
0x0C
0xN34D
Receive DS3/E3 AIS/PDI-P Alarm Enable Register
0x00
0xN34E
PMON Excessive Zero Count Register - MSB
0x00
0xN34F
PMON Excessive Zero Count Register- LSB
0x00
0xN350
PMON LCV Event Count Register - MSB
0x00
0xN351
PMON LCV Event Count Register - LSB
0x00
0xN352
PMON Framing Bit/Byte Error Count Register - MSB
0x00
0xN353
PMON Framing Bit/Byte Error Count Register - LSB
0x00
0xN354
PMON Parity Error Event Count Register - MSB
0x00
33
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0xN355
PMON Parity Error Event Count Register - LSB
0x00
0xN356
PMON FEBE Event Count Register- MSB
0x00
0xN357
PMON FEBE Event Count Register – LSB
0x00
0xN358
PMON CP-Bit Error Count Register - MSB
0x00
0xN359
PMON CP-Bit Error Count Register - LSB
0x00
0xN35A
PMON PLCP BIP-8 Error Count Register – MSB
0x00
0xN35B
PMON PLCP BIP-8 Error Count Register – LSB
0x00
0xN35C
PMON PLCP Framing Byte Error Count Register – MSB
0x00
0xN35D
PMON PLCP Framing Byte Error Count Register – LSB
0x00
0xN35E
PMON PLCP FEBE Error Count Register – MSB
0x00
0xN35F
PMON PLCP FEBE Error Count Register – LSB
0x00
Reserved
0x00
0xN368
PMON PRBS Bit Error Count Register - MSB
0x00
0xN369
PMON PRBS Bit Error Count Register - LSB
0x00
Reserved
0x00
0xN36C
PMON Holding Register
0x00
0xN36D
One Second Error Status Register
0x00
0xN36E
One Second – LCV Count Accumulator Register - MSB
0x00
0xN36F
One Second – LCV Count Accumulator Register - LSB
0x00
0xN370
One Second – Parity Error Accumulator Register - MSB
0x00
0xN371
One Second – Parity Error Accumulator Register - LSB
0x00
0xN372
One Second – CP Bit Error Accumulator Register - MSB
0x00
0xN373
One Second – CP Bit Error Accumulator Register - LSB
0x00
0xN374 – 0xN37F
Reserved
0x00
0xN380
Reserved
0x00
0xN381
Line Interface Scan Register
0x00
0xN382
Reserved
0x00
0xN383
Transmit LAPD Byte Count Register
0x00
0xN384
Receive LAPD Byte Count Register
0x00
Reserved
0x00
0xN390
Receive PLCP Configuration and Status Register
0x06
0xN391
Receive PLCP Interrupt Enable Register
0x00
0xN392
Receive PLCP Interrupt Status Register
0x00
0xN360 – 0xN367
0xN36A – 0xN36B
0xN385 – 0xN389
34
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xN393 – 0xN397
Reserved
0x00
0xN398
Transmit PLCP A1 Byte Error Mask Register
0x00
0xN399
Transmit PLCP A2 Byte Error Mask Register
0x00
0xN39A
Transmit PLCP BIP-8 Error Mask Register
0x00
0xN39B
Transmit PLCP G1 Byte Register
0x00
Reserved
0x00
0xN3B0
Transmit LAPD Memory Indirect Address Register
0x00
0xN3B1
Transmit LAPD Memory Indirect Data Register
0x00
0xN3B2
Receive LAPD Memory Indirect Address Register
0x00
0xN3B3
Receive LAPD Memory Indirect Data Register
0x00
Reserved
0x00
0xN3F0
Receive DS3/E3 Configuration Register – Secondary Frame Synchronizer
Block – Byte 1
0x10
0xN3F1
Receive DS3/E3 Configuration Register – Secondary Frame Synchronizer
Block – Byte 0
0x10
0xN3F2
Receive DS3/E3 AIS/PDI-P Alarm Enable Register – Secondary Frame
Synchronizer Block
0x00
Reserved
0x00
0xN3F8
Receive DS3/E3 Interrupt Enable Register – Secondary Frame Synchronizer
Block
0x00
0xN3F9
Receive DS3/E3 Interrupt Status Register – Secondary Frame Synchronizer
Block
0x00
0xN39C –
0xN3AF
0xN3B4 – 0xN3EF
0xN3F3 – 0xN3F7
RECEIVE STS-3C POH PROCESSOR BLOCK
0x1000 – 0x1181
Reserved
0x00
0x1182
Receive STS-3c Path – Control Register – Byte 1
0x00
0x1183
Receive STS-3c Path – Control Register – Byte 0
0x00
Reserved
0x00
0x1186
Receive STS-3c Path – Status Register – Byte 1
0x00
0x1187
Receive STS-3c Path – Status Register – Byte 0
0x00
0x1188
Reserved
0x00
0x1189
Receive STS-3c Path – Interrupt Status Register – Byte 2
0x00
0x118A
Receive STS-3c Path – Interrupt Status Register – Byte 1
0x00
0x118B
Receive STS-3c Path – Interrupt Status Register – Byte 0
0x00
0x118C
Reserved
0x00
0x118D
Receive STS-3c Path – Interrupt Enable Register – Byte 2
0x00
0x1184 – 0x1185
35
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0x118E
Receive STS-3c Path – Interrupt Enable Register – Byte 1
0x00
0x118F
Receive STS-3c Path – Interrupt Enable Register – Byte 0
0x00
Reserved
0x00
Receive STS-3c Path – SONET Receive RDI-P Register
0x00
Reserved
0x00
0x1196
Receive STS-3c Path – Receive Path Label Byte (C2) Register
0x00
0x1197
Receive STS-3c Path – Expected Path Label Byte (C2) Register
0x00
0x1198
Receive STS-3c Path – B3 Error Count Register – Byte 3
0x00
0x1199
Receive STS-3c Path – B3 Error Count Register – Byte 2
0x00
0x119A
Receive STS-3c Path – B3 Error Count Register – Byte 1
0x00
0x119B
Receive STS-3c Path – B3 Error Count Register – Byte 0
0x00
0x119C
Receive STS-3c Path – REI-P Error Count Register – Byte 3
0x00
0x119D
Receive STS-3c Path – REI-P Error Count Register – Byte 2
0x00
0x119E
Receive STS-3c Path – REI-P Error Count Register – Byte 1
0x00
0x119F
Receive STS-3c Path – REI-P Error Count Register – Byte 0
0x00
Reserved
0x00
Receive STS-3c Path – Receive J1 Byte Control Register
0x00
Reserved
0x00
0x11A6
Receive STS-3c Path – Pointer Value Register – Byte 1
0x00
0x11A7
Receive STS-3c Path – Pointer Value Register – Byte 0
0x00
Reserved
0x00
Receive STS-3c Path – Loss of Pointer – Concatenation Status Register
0x00
Reserved
0x00
Receive STS-3c Path – AIS – Concatenation Status Register
0x00
Reserved
0x00
Receive STS-3c Path – Auto AIS Control Register
0x00
Reserved
0x00
Receive STS-3c Path – Serial Port Control Register
0x00
Reserved
0x00
Receive STS-3c Path - SONET Receive Auto Alarm Register – Byte 0
0x00
Reserved
0x00
Receive STS-3c Path – Receive J1 Byte Capture Register
0x00
Reserved
0x00
0x1190 – 0x1192
0x1193
0x1194 – 0x1195
0x11A0 – 0x11A2
0x11A3
0x11A4 – 0x11A5
0x11A8 – 0x11AA
0x11AB
0x11AC – 0x11B2
0x11B3
0x11B4 – 0x11BA
0x11BB
0x11BC – 0x11BE
0x11BF
0x11C0 – 0x11C2
0x11C3
0x11C4 –0x11D2
0x11D3
0x11D4 – 0x11D6
36
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0x11D7
0x11D8 – 0x11DA
0x11DB
0x11DC – 0x11DE
0x11DF
0x11E0 – 0x11E2
0x11E3
0x11E4 – 0x11E6
0x11E7
0x11E8 – 0x11EA
0x11EB
0x11EC – 0x11EE
0x11EF
0x11F0 – 0x11F2
0x11F3
0x11F4 – 0x11FF
Receive STS-3c Path – Receive B3 Byte Capture Register
0x00
Reserved
0x00
Receive STS-3c Path – Receive C2 Byte Capture Register
0x00
Reserved
0x00
Receive STS-3c Path – Receive G1 Byte Capture Register
0x00
Reserved
0x00
Receive STS-3c Path – Receive F2 Byte Capture Register
0x00
Reserved
0x00
Receive STS-3c Path – Receive H4 Byte Capture Register
0x00
Reserved
0x00
Receive STS-3c Path – Receive Z3 Byte Capture Register
0x00
Reserved
0x00
Receive STS-3c Path – Receive Z4 (K3) Byte Capture Register
0x00
Reserved
0x00
Receive STS-3c Path – Receive Z5 Byte Capture Register
0x00
Reserved
0x00
RECEIVE STS-3C POH PROCESSOR BLOCK – RECEIVE J1 (PATH) TRACE MESSAGE BUFFER – STS-3C
0x1500 – 0x153F
Receive STS-3c POH Processor Block – Receive J1 (Path) Trace Message
Buffer
0x00
0x1540 – 0x15FF
Reserved
0x00
TRANSMIT STS-3C POH PROCESSOR BLOCK
0x1900 – 0x1981
Reserved
0x00
0x1982
Transmit STS-3c Path – SONET Control Register – Byte 1
0x00
0x1983
Transmit STS-3c Path – SONET Control Register- Byte 0
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit J1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3c Path – B3 Byte Mask Register
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit C2 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit G1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit F2 Byte Value Register
0x00
0x1984 – 0x1992
0x1993
0x1994 – 0x1996
0x1997
0x1998 – 0x199A
0x199B
0x199C – 0x199E
0x199F
0x19A0 – 0x19A2
0x19A3
37
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
0x19A4 –0x19A6
Rev222...000...000
Reserved
0x00
Transmit STS-3c Path – Transmit H4 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit Z3 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit Z4 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit Z5 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit Path Control Register – Byte 0
0x00
Reserved
0x00
Transmit STS-3c Path- Transmit J1 Byte Control Register
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit Arbitrary H1 Byte Pointer Register
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit Arbitrary H2 Byte Pointer Register
0x00
Reserved
0x00
0x19C6
Transmit STS-3c Path – Transmit Pointer Byte Register –Byte 1
0x00
0x19C7
Transmit STS-3c Path – Transmit Pointer Byte Register – Byte 0
0x00
0x19C8
Reserved
0x00
0x19C9
Transmit STS-3c Path – RDI-P Control Register – Byte 2
0x00
0x19CA
Transmit STS-3c Path –RDI-P Control Register – Byte 1
0x00
0x19CB
Transmit STS-3c Path – RDI-P Control Register – Byte 0
0x00
Reserved
0x00
Transmit STS-3c Path – Transmit Path Serial Port Control Register
0x00
Reserved
0x00
0x19A7
0x19A8 – 0x19AA
0x19AB
0x19AC – 0x19AE
0x19AF
0x19B0 – 0x19B2
0x19B3
0x19B4 – 0x19B6
0x19B7
0x19B8 – 0x19BA
0x19BB
0x19BC –0x19BE
0x19BF
0x19C0 – 0x19C2
0x19C3
0x19C4 – 0x19C5
0x19CC –0x19CE
0x19CF
0x19D0 – 0x1AFF
TRANSMIT STS-3C POH PROCESSOR BLOCK – TRANSMIT J1 (PATH) TRACE MESSAGE BUFFER
0x1D00 – 0x1D3F
Transmit STS-3c POH Processor Block –Transmit J1 (Path) Trace Message
Buffer
0x00
0x1D40 – 0x1DFF
Reserved
0x00
38
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1.2
THE OPERATION CONTROL BLOCK
The Operation Control Block is responsible for the following functions.
• Control of the Interrupt Structure (at the Highest Level within the XRT94L33)
• Control of the Clock Synthesizer block
• Control of the STS-3/STM-1 Telecom Bus Interface
• Control of the STS-1 Telecom Bus Interfaces
The register map for the Operation Control block is presented in the Table below. Additionally, a detailed
description of each of the “Operation Control” Block registers is presented below.
1.2.1
OPERATION CONTROL BLOCK REGISTER
Table 2: Operation Control Register Address Map
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x00
0x0100
Operation Control Register – Byte 3
0x00
0x01
0x0101
Operation Control Register – Byte 2
0x00
0x02
0x0102
Reserved
0x00
0x03
0x0103
Operation Control Register – Byte 0
0x00
0x04
0x0104
Operation Status Register – Byte 3 (Device ID)
0xE3
0x05
0x0105
Operation Status Register – Byte 2 (Revision ID)
0x01
0x06 – 0x0A
0x0106 – 0x010A
Reserved
0x00
0x0B
0x010B
Operation Interrupt Status Register – Byte 0
0x00
0x0C – 0x0E
0x010C –
0x010E
Reserved
0x00
0x0F
0x010F
Operation Interrupt Enable Register – Byte 0
0x00
0x10 – 0x11
0x0110 – 0x0111
Reserved
0x00
0x12
0x0112
Operation Block Interrupt Status Register – Byte 1
0x00
0x13
0x0113
Operation Block Interrupt Status Register – Byte 0
0x00
0x14 – 0x15
0x0114 – 0x0115
Reserved
0x00
0x16
0x0116
Operation Block Interrupt Enable Register – Byte 1
0x00
0x17
0x0117
Operation Block Interrupt Enable Register – Byte 0
0x00
0x18 – 0x19
0x0118 – 0x0119
Reserved
0x00
0x1A
0x0111A
Reserved
0x00
0x1B
0x011B
Mode Control Register – Byte 0
0x00
0x1C – 0x1E
0x011C –
0x011E
Reserved
0x00
0x1F
0x011F
Loop-back Control Register – Byte 0
0x00
REGISTER NAME
39
DEFAULT VALUE
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
REGISTER NAME
DEFAULT VALUE
0x20
0x0120
Channel Interrupt Indicator – Receive SONET POH Processor
Block
0x00
0x21
0x0121
Reserved
0x00
0x22
0x0122
Channel Interrupt Indicator – DS3/E3 framer Block
0x00
0x23
0x0123
Channel Interrupt Indicator – Receive STS-1 POH Processor
Block
0x00
0x24
0x0124
Channel Interrupt Indicator – Receive STS-1 TOH Processor
Block
0x00
0x25
0x0125
Reserved
0x00
0x26
0x0126
Channel Interrupt Indicator – STS-1/DS3/E3 Mapper Block
0x00
0x27
0x0127
Reserved
0x00
0x28
0x0128
Reserved
0x00
0x29
0x0129
Reserved
0x00
0x2A
0x012A
Reserved
0x00
0x2B – 0x2F
0x012B –
0x012F
Unused
0x00
0x2E
0x012E
Reserved
0x00
0x2F
0x012F
Reserved
0x00
0x30
0x0130
Reserved
0x00
0x31
0x0131
Reserved
0x00
0x32
0x0132
Interface Control Register – Byte 1
0x00
0x33
0x0133
Interface Control Register – Byte 0
0x00
0x34
0x0134
STS-3/STM-1 Telecom Bus Control Register – Byte 3
0x00
0x35
0x0135
STS-3/STM-1 Telecom Bus Control Register – Byte 2
0x00
0x36
0x0136
Reserved
0x00
0x37
0x0137
STS-3/STM-1 Telecom Bus Control Register – Byte 0
0x00
0x38
0x0138
Reserved
0x00
0x39
0x0139
Interface Control Register – Byte 2 – STS-1 Telecom Bus 2
0x00
0x3A
0x013A
Interface Control Register – Byte 1 – STS-1 Telecom Bus 1
0x00
0x3B
0x013B
Interface Control Register – Byte 0 – STS-1 Telecom Bus 0
0x00
0x3C
0x013C
Interface Control Register – STS-1 Telecom Bus Interrupt
Register
0x00
0x3D
0x013D
Interface Control Register – STS-1 Telecom Bus Interrupt
Status Register
0x00
0x3E
0x013E
Interface Control Register – STS-1 Telecom Bus Interrupt
0x00
40
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
REGISTER NAME
DEFAULT VALUE
Interface Control Register – STS-1 Telecom Bus Interrupt
Enable Register
0x00
Register # 2
0x3F
0x013F
0x40 – 0x45
0x0140 – 0x0145
Reserved
0x00
0x46
0x0146
Reserved
0x00
0x47
0x0147
Operation General Purpose Input/Output Register
0x00
0x48 – 0x49
0x0148 – 0x0149
Reserved
0x00
0x4A
0x014A
Reserved
0x00
0x4B
0x014B
Operation General Purpose Input/Output Direction Register
0x00
0x4C – 0x4F
0x014C –
0x014F
Reserved
0x00
0x50
0x0150
Operation Output Control Register – Byte 1
0x00
0x51 – 0x52
0x0151 –0x0152
Reserved
0x00
0x53
0x0153
Operation Output Control Register – Byte 0
0x00
0x54
0x0154
Operation Slow Speed Port Control Register – Byte 1
0x00
0x55 – 0x56
0x0155 – 0x0156
Reserved
0x00
0x57
0x0157
Operation Slow Speed Port Control Register –Byte 0
0x00
0x58
0x0158
Operation – DS3/E3/STS-1 Clock Frequency Out of Range
Detection – Direction Register
0x00
0x59
0x0159
Reserved
0x00
0x5A
0x015A
Operation – DS3/E3/STS-1 Clock Frequency – DS3 Out of
Range Detection Threshold Register
0x00
0x5B
0x015B
Operation – DS3/E3/STS-1 Clock Frequency – STS-1/E3 Out
of Range Detection Threshold Register
0x00
0x5C
0x015C
Reserved
0x00
0x5D
0x015D
Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt
Enable Register – Byte 0
0x00
0x5E
0x015E
Reserved
0x00
0x5F
0x015F
Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt
Status Register – Byte 0
0x00
0x60 – 0x7F
0x0160 – 0x017F
Reserved
0x00
0x80
0x0180
APS Mapping Register
0x00
0x81
0x0181
APS Control Register
0x00
0x82 – 0x93
0x0182 – 0x0193
Reserved
0x00
0x94
0x0194
APS Status Register
0x00
41
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x95
0x0195
Reserved
0x00
0x96
0x0196
APS Status Register
0x00
0x97
0x0197
APS Status Register
0x00
0x98
0x0198
APS Interrupt Register
0x00
0x99
0x0199
Reserved
0x00
0x9A
0x019A
APS Interrupt Register
0x00
0x9B
0x019B
APS Interrupt Register
0x00
0x9C
0x019C
APS Interrupt Register
0x00
0x9D
0x019D
Reserved
0x00
0x9E
0x019E
APS Interrupt Enable Register
0x00
0x9F
0x019F
APS Interrupt Enable Register
0x00
0xA0 – 0xFF
0x01A0 –
0x01FF
Reserved
0x00
REGISTER NAME
42
DEFAULT VALUE
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1.2.2
OPERATION CONTROL REGISTER DESCRIPTIONS
Table 3: Operation Control Register – Byte 3 (Address Location= 0x0100)
BIT 7
BIT 6
BIT 5
R/O
R/O
R/O
0
0
0
BIT 4
BIT 3
BIT 2
BIT 1
R/O
R/O
R/W
R/W
R/W
0
0
0
0
0
Unused
BIT 0
Configuration Control [1:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
Bit 7 – Bit 2
Unused
R/O
Please set to “0” for normal operation.
Bit 1 – Bit 0
Configuration
Control [1:0]
R/W
Configuration Control [1:0]:
This READ/WRITE bit-field permits the user to determine the configuration
of the XRT94L33.
The XRT94L33 can be configured for both Mapper applications and
ATM/PPP applications. For Mapper applications, please refer to our “3channel DS3/E3/STS-1 To STS-3/STM-1 Mapper IC Datasheet”.
For ATM/PPP applications, the XRT94L33 can have the following
configurations:
Configuration
Control [1:0]
Operation Modes
00
If the user set these bits to “00”, the user is allowing
the XRT94L33 to be configured as the following:
01
a.
A single STS-3c ATM UNI and two-channel
DS3/E3 ATM/PPP/HDLC/Clear Channel
device
b.
A single STS3-c ATM UNI and two-channel
STS-1 ATM UNI device.
c.
A single STS-3c PPP and two-channel
DS3/E3 ATM/PPP/HDLC/Clear Channel
device
d.
A single STS3-c PPP and two-channel STS1 PPP device.
If the user set these bits to “01”, the user is allowing
the XRT94L33 to be configured as a 3 channel
DS3/E3 ATM UNI/PPP/HDLC/Clear Channel to STS3 device (See
Figure 1)
10
If the user set these bits to “10”, the user is allowing
the XRT94L33 to be configured as either a 3-channel
STS-1/DS3/E3 to ATM/PPP device (See
Figure 2) or as a 3 channel DS3/E3 to HDLC/CC
device (See Figure 3).
11
If the user set these bits to “11”, the user is allowing
the XRT94L33 to be configured as a 3 channel
ATM/PPP to STS-3 device (See Figure 4).
43
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Figure 1: Functional Block Diagram for 3-channel DS3/E3 ATM UNI/PPP to STS-3 Applications
From Channels 1 & 2
Tx
Tx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Rx
Rx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Clock
Clock
Synthesizer
Synthesizer
Block
Block
Tx
TxCell
Cell
Processor
Processor
Block
Block
Tx
TxPLCP
PLCP
Processor
Processor
Block
Block
Tx
TxPPP
PPP
Processor
Processor
Block
Block
Tx
TxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Tx
TxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Tx
TxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxPPP
PPP
Processor
Processor
Block
Block
Rx
RxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
RxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Rx
RxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxCell
Cell
Processor
Processor
Block
Block
Rx
RxPLCP
PLCP
Processor
Processor
Block
Block
Channel 0
To Channel 1 & 2
44
Tx
TxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
Tx
TxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Tx
TxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Rx
RxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Clock
Clock&&
Data
Data
Recovery
Recovery
Block
Block
Rx
RxSTS-3
STS-3
Telecom
Telecom
Bus
Block
Bus Block
Rx
RxSTS-3
STS-3
PECL
PECL
I/F
Block
I/F Block
Rev222...000...000
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Figure 2: Functional Block Diagram for 3-channel DS3/E3/STS-1 ATM UNI/PPP Applications
Tx
TxPPP
PPP
Processor
Processor
Block
Block
Tx
Tx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Rx
Rx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Tx
TxCell
Cell
Processor
Processor
Block
Block
Tx
TxPLCP
PLCP
Processor
Processor
Block
Block
Rx
RxCell
Cell
Processor
Processor
Block
Block
Rx
RxPLCP
PLCP
Processor
Processor
Block
Block
Rx
RxPPP
PPP
Processor
Processor
Block
Block
Tx
TxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
RxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Channel 0
Figure 3: Functional Block Diagram for 3-channel DS3/E3 HDLC/Clear Channel Applications
Tx
Tx
Overhead
Overhead
Data
DataInput
Input
Interface
Interface
Block
Block
Tx
TxPayload
Payload
Data
DataInput
Input
Interface
Interface
Block
Block
Rx
RxPayload
Payload
Data
DataOutput
Output
Interface
Interface
Block
Block
Tx
TxPMDL/
PMDL/
FEAC
FEAC
Controller
Controller
Block
Block
Tx
TxHDLC
HDLC
Controller
Controller
Block
Block
Tx
TxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
RxHDLC
HDLC
Controller
Controller
Block
Block
Rx
RxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
Rx
Overhead
Overhead
Data
DataOutput
Output
Interface
Interface
Block
Block
Rx
RxPMDL/
PMDL/
FEAC
FEAC
Controller
Controller
Block
Block
Channel 0
Figure 4: Functional Block Diagram for STS-3 ATM UNI/PPP Applications
45
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
From Channel 1 & 2
Clock
Clock
Synthesizer
Synthesizer
Block
Block
Tx
TxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
Tx
TxPPP
PPP
Processor
Processor
Block
Block
Tx
Tx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Rx
Rx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Tx
TxCell
Cell
Processor
Processor
Block
Block
Tx
TxATM/
ATM/
PPP
PPP
Mapper
Mapper
Block
Block
Tx
TxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxCell
Cell
Processor
Processor
Block
Block
Rx
RxATM/
ATM/
PPP
PPP
Mapper
Mapper
Block
Block
Rx
RxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxPPP
PPP
Processor
Processor
Block
Block
Channel 0
To Channel 1 & 2
Rev222...000...000
Tx
TxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Tx
TxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Rx
RxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Clock
Clock&&
Data
Data
Recovery
Recovery
Block
Block
Rx
RxSTS-3
STS-3
Telecom
Telecom
Bus
Block
Bus Block
Rx
RxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
Table 4: Operation Control Register – Byte 2 (Address Location= 0x0101)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Interrupt
Write
Clear/RUR
Enable
Interrupt
Clear
Interrupt
Enable
R/O
R/O
R/O
R/O
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
Bit 7 – Bit 3
Unused
R/O
Please set to “0” for normal operation.
Bit 2
Interrupt Write
to Clear/RUR
R/W
Interrupt – Write to Clear/RUR Select:
This READ/WRITE bit-field permits the user to configure all of the “SourceLevel” Interrupt Status bits (within the XRT94L33) to either be “Write to
Clear” (WTC) or “Reset-upon-Read” (RUR) bits.
0 – Configures all “Source-Level” Interrupt Status register bits to function as
“Reset-upon-Read” (RUR).
1 – Configures all “Source-Level” Interrupt Status register bits to function as
“Write-to-Clear” (WTC).
Bit 1
Enable Interrupt
Clear
R/W
Enable Auto-Clear of Interrupts Select:
This READ/WRITE bit-field permits the user to configure the XRT94L33 to
automatically disable all interrupts that are activated.
0 – Configures the chip to NOT automatically disable any Interrupts
following their activation.
1 – Configures the chip to automatically disable all Interrupts following their
46
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
activation.
Bit 0
Interrupt Enable
R/W
Interrupt Enable:
This READ/WRITE bit-field permits the user to configure the XRT94L33 to
generate interrupt requests to the Microprocessor.
0 – Configures the chip to NOT generate interrupt to the Microprocessor. All
interrupts are disabled and the Microprocessor must poll the register bits.
1 – Configures the chip to generate interrupts the Microprocessor.
47
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 5: Operation Control Register – Byte 0 (Address Location= 0x0103)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Transmit
UTOPIA
PLL OFF
Receive
UTOPIA
PLL OFF
R/W
R/W
R/O
R/O
R/O
R/W
R/O
R/W
1
1
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Transmit
UTOPIA PLL
OFF
R/W
6
Receive
UTOPIA PLL
OFF
R/W
5-3
Unused
R/O
2
PPP/ATM
R/W
PPP/ATM
BIT 0
SW
RESET
DESCRIPTION
PPP/ATM UNI Mode Select:
This READ-WRITE bit-field permits the user to configure the XRT94L33 to
operate in either the ATM UNI or PPP Mode.
0 – Configures the UTOPIA/POS-PHY bus to operate in the UTOPIA (ATM)
Mode.
1 – Configures the UTOPIA/POS-PHY Bus to operate in the POS-PHY
Mode.
1
Unused
R/O
Please set to “0” for normal operation
Bit 0
SW
Reset
R/W
Software Reset – SONET Block:
This READ/WRITE bit-field permits the user to command a software reset to
the SONET/SDH block. If the user invokes a software reset to the
SONET/SDH blocks then all of the internal state machines will be reset to
their default conditions; and each of the Receive STS-1/STS-3 TOH
Processor blocks will undergo a re-frame operation.
A “0” to “1” transition, within this bit-field commands this Software Reset.
Note:
This Software Reset does not reset the command registers to their default
state. This can only be achieved by executing a “Hardware RESET” (e.g.,
by pulling the RESET_L* input pin “LOW”). This Software Reset does not
affect the DS3/E3 Framer blocks. The Software Reset bit-field, for the
DS3/E3 Framer block can be found in each of the 3 “DS3/E3 Operating
Mode” registers (Address Location= 0xNF00).
48
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 6: Operation Status Register – Byte 3 (Address Location= 0x0104)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Device ID Value
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
1
1
1
0
0
0
1
1
BIT NUMBER
NAME
TYPE
7–0
Device ID Value
R/O
DESCRIPTION
Device ID Value:
This READ-ONLY bit-field is set to the value “0xE3” and permits the
user’s software code to uniquely identify this device as being the
XRT94L33.
Table 7: Operation Status Register – Byte 2 (Address Location= 0x0105)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Revision Number Value
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
1
BIT NUMBER
NAME
TYPE
7–0
Revision Number
Value
R/O
DESCRIPTION
Revision NumberValue:
This READ-ONLY bit-field is set to the value that corresponds to its
revision number. Revision A silicon will be set to the value “0x01”. This
register permits the user’s software code to uniquely identify the
revision number of this device.
49
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 8: Operation Interrupt Status Register – Byte 0 (Address Location= 0x010B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
BIT 0
TB Parity Error Interrupt Status
R/O
R/O
R/O
R/O
R/O
R/O
R/O
RUR/WTC
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
Bit 7 – Bit 1
Unused
R/O
Bit 0
TB Parity Error
Interrupt Status
RUR/
WTC
DESCRIPTION
Please set to “0” for normal operation
Telecom Bus Parity Error Interrupt Status:
This “RESET-upon-READ” bit-field indicates whether or not the
“Detection of 155.52Mbps Telecom Bus – Parity Error” interrupt has
occurred since the last read of this register bit.
0 – Indicates that the “Detection of 155.52Mbps Telecom Bus – Parity
Error” interrupt has NOT occurred since the last read of this register bit.
1 – Indicates that the “Detection of 155.52Mbps Telecom Bus – Parity
Error” interrupt has occurred since the last of this register bit.
Note:
This register bit is only active if the 155.52Mbps port is
configured to operate via the Telecom Bus.
Table 9: Operation Interrupt Enable Register – Byte 0 (Address Location= 0x010F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
BIT 0
Telecom Bus Parity Error
Interrupt Enable
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
Bit 7 – Bit 1
Unused
R/O
Please set to “0” for normal operation
Bit 0
TB Parity Error
Interrupt Enable
R/W
Telecom Bus Parity Error Interrupt Enable:
This “READ/WRITE” bit-field permits the user to either enable or
disable the “Detection of 155.52Mbps Telecom Bus – Parity Error”
interrupt.
0 – Disables the “Detection of 155.52Mbps Telecom Bus – Parity Error”
interrupt.
1 – Enables the “Detection of 155.52Mbps Telecom Bus – Parity Error”
interrupt.
Note:
This register bit is only active if the 155.52Mbps port is
configured to operate via the Telecom Bus.
50
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 10: Operation Block Interrupt Status Register – Byte 1 (Address Location= 0x0112)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Op Control
Block
Interrupt
Status
DS3/E3
Mapper
Block
Interrupt
Status
Unused
Rx STS-1
TOH
Block
Interrupt
Status
Rx STS-1
POH Block
Interrupt
Status
DS3/E3
Framer
Block
Interrupt
Status
Rx Line
Interface
Block
Interrupt
Status
Unused
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7
Op Control Block
Interrupt Status
R/O
DESCRIPTION
Operation Control Block Interrupt Status:
This READ-ONLY bit-field indicates whether or not an Operation Control
Block-related Interrupt is awaiting service.
0 – No Operation Control Block Interrupts are awaiting service.
1 – At least one “Operation Control Block” Interrupt is awaiting service.
6
DS3/E3 Mapper Block
Interrupt Status
R/O
DS3/E3 Mapper Block Interrupt Status:
This READ-ONLY bit-field indicates whether or not a Mapper Blockrelated Interrupt is awaiting service.
0 – No Mapper Block interrupt is awaiting service.
1 – At least one “Mapper Block” Interrupt is awaiting service.
5
Unused
R/O
4
Rx STS-1 TOH Block
Interrupt Status
R/O
STS-1 Receive Transport Overhead (TOH) Processor Block Interrupt
Status:
This READ-ONLY bit-field indicates whether or not an “Receive STS-1
TOH Processor” Block Interrupt is awaiting service.
0 – No “Receive STS-1 TOH Processor” block interrupt is awaiting
service.
1 – At least one “Receive STS-1 TOH Processor” block interrupt is
awaiting service.
Note:
3
Rx STS-1 POH Block
Interrupt Status
R/O
This bit-field is in-active if the XRT94L33 has been configured to
operate in the SDH Mode.
Receive STS-1 Path Overhead (POH) Processor Block Interrupt
Status:
This READ-ONLY bit-field indicates whether or not an “Receive STS-1
POH Processor” Block Interrupt is awaiting service.
0 – No “Receive STS-1 POH Processor” block interrupt is awaiting
service.
1 – At least one “Receive STS-1 POH Processor” block interrupt is
awaiting service.
Note:
2
DS3/E3 Framer Block
Interrupt Status
R/O
This bit-field is in-active if the XRT94L33 has been configured to
operate in the SDH Mode.
DS3/E3 Framer Block Interrupt Status
This READ-ONLY bit-field indicates whether or not a “DS3/E3 Framer
51
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Block” interrupt is awaiting service.
0 – No “DS3/E3 Framer” block interrupt is awaiting service.
1 – At least one “DS3/E3 Framer” block interrupt is awaiting service.
1
Rx Line Interface
Block Interrupt Status
R/O
Receive Line Interface Block Interrupt Status
This READ-ONLY bit-field indicates whether or not a “Receive Line
Interface Block” interrupt is awaiting service.
0 – No “Receive Line Interface” block interrupt is awaiting service.
1 – At least one “Receive Line Interface” block interrupt is awaiting
service.
0
Unused
R/O
52
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 11: Operation Block Interrupt Status Register – Byte 0 (Address Location= 0x0113)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Receive
ATM Cell
Processor
Block
Interrupt
Status
Receive
STS-3/
STM-1
TOH Block
Interrupt
Status
Receive
SONET/
VC-3
POH Block
Interrupt
Status
Receive
PPP
Processor
Block
Interrupt
Status
Transmit
ATM Cell
Processor
Block
Interrupt
Status
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Receive ATM Cell
Processor Block
Interrupt Status
R/O
BIT 2
BIT 1
BIT 0
Transmit
PPP
Processor
Block
Interrupt
Status
Unused
DESCRIPTION
Receive ATM Cell Processor Block Interrupt Status:
This READ-ONLY bit-field indicates whether or not a “Receive ATM Cell
Processor Block” interrupt is awaiting service.
0 – No “Receive ATM Cell Processor Block” Interrupt is awaiting service.
1 – At least one “Receive ATM Cell Processor Block” interrupt is awaiting
service.
6
Receive
STS-3/
STM-1
TOH Block
Interrupt Status
R/O
Receive STS-3/STM-1 TOH Processor Block Interrupt Status:
This READ-ONLY bit-field indicates whether or not a “Receive STS3/STM-1 TOH Processor Block” interrupt is awaiting service.
0 – No “Receive STS-3/STM-1 TOH Processor Block” Interrupt is awaiting
service.
1 – At least one “Receive STS-3/STM-1 TOH Processor Block” interrupt is
awaiting service.
5
Receive
SONET/
VC-3
POH Block
Interrupt Status
R/O
Receive SONET/VC-3 POH Processor Block Interrupt Status:
This READ-ONLY bit-field indicates whether or not a “Receive
SONET/VC-3 POH Processor Block” interrupt is awaiting service.
0 – No “Receive SONET/VC-3 POH Processor Block” Interrupt is awaiting
service.
1 – At least one “Receive SONET/VC-3 POH Processor Block” Interrupt is
awaiting service.
4
Receive PPP
Processor Block
Interrupt Status
R/O
Receive PPP Processor Block Interrupt Status:
This READ-ONLY bit-field indicates whether or not a “Receive PPP
Processor Block” interrupt is awaiting service.
0 – No “Receive PPP Processor Block” Interrupt is awaiting service.
1 – At least one “Receive PPP Processor Block” interrupt is awaiting
service.
3
Transmit ATM Cell
Processor Block
Interrupt Status
R/O
Transmit ATM Cell Processor Block Interrupt Status:
This READ-ONLY bit-field indicates whether or not a “Transmit ATM Cell
Processor Block” interrupt is awaiting service.
0 – No “Transmit ATM Cell Processor Block” Interrupt is awaiting service.
1 – At least one “Transmit ATM Cell Processor Block” interrupt is awaiting
service.
53
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
2-1
Unused
R/O
0
Transmit PPP
Processor Block
Interrupt Status
R/O
Rev222...000...000
Transmit PPP Processor Block Interrupt Status:
This READ-ONLY bit-field indicates whether or not a “Transmit PPP
Processor Block” interrupt is awaiting service.
0 – No “Transmit PPP Processor Block” Interrupt is awaiting service.
1 – At least one “Transmit PPP Processor Block” Interrupt is awaiting
service.
54
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 12: Operation Block Interrupt Enable Register – Byte 1 (Address Location= 0x0116)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Op Control
Block
Interrupt
Enable
DS3/E3
Mapper
Block
Interrupt
Enable
Unused
Rx STS-1
TOH
Block
Interrupt
Enable
Rx STS-1
POH Block
Interrupt
Enable
DS3/E3
Framer
Block
Interrupt
Enable
Rx Line
Interface
Block
Interrupt
Enable
Unused
R/W
R/W
R/O
R/W
R/W
R/W
R/W
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Op Control
Block Interrupt
Enable
R/W
DESCRIPTION
Operation Control Block Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
Operation Control Block for interrupt generation. If the user writes a “0” to this
register bit and disables the “Operation Control Block” (for interrupt
generation), then all “Operation Control Block” interrupts will be disabled for
interrupt generation. If the user writes a “1” to this register bit, he/she will still
need to enable the individual “Operation Control Block” interrupt(s) at the
“Source Level” in order to enable that particular interrupt.
0 – Disable all “Operation Control Block” interrupts within the device.
1 – Enables the “Operation Control Block” at the “Block-Level” for interrupt
generation
6
DS3/E3
Mapper Block
Interrupt
Enable
R/W
DS3/E3 Mapper Block Interrupt Enable:
This READ/WRITE bit permits the user to either enable or disable the Mapper
Block for interrupt generation. If the user writes a “0” to this register bit and
disables the “Mapper Block” (for interrupt generation), then all “Mapper Block”
interrupts will be disabled for interrupt generation. If the user writes a “1” to
this register bit, he/she will still need to enable the individual “Mapper Block”
interrupt(s) at the “Source Level” in order to enable that particular interrupt.
0 – Disable all “Mapper Block” interrupts within the device.
1 – Enables the “Mapper Block” at the “Block-Level”
5
Unused
R/O
4
Rx STS-1 TOH
Block Interrupt
Enable
R/W
Receive STS-1 TOH (Transport Overhead) Processor Block Interrupt
Enable:
This READ/WRITE bit permits the user to either enable or disable the Receive
STS-1 TOH Processor Block for interrupt generation. If the user writes a “0” to
this register bit and disables the “Receive STS-1 TOH Processor Block” (for
interrupt generation), then all “Receive STS-1 TOH Processor Block” interrupts
will be disabled for interrupt generation. If the user writes a “1” to this register
bit, he/she will still need to enable the individual “Receive STS-1 TOH
Processor Block” interrupt(s) at the “Source Level” in order to enable that
particular interrupt.
0 – Disable all “Receive STS-1 TOH Processor Block” interrupts within the
device.
1 – Enables the “Receive STS-1 TOH Processor Block” at the “Block-Level”.
Note:
3
Rx STS-1 POH
Block Interrupt
Enable
R/W
This bit-field is inactive if the XRT94L33 has been configured to
operate in the SDH Mode.
Receive STS-1 POH (Path Overhead) Processor Block Interrupt Enable:
This READ/WRITE bit permits the user to either enable or disable the Receive
55
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Enable
Rev222...000...000
STS-1 POH Processor Block for interrupt generation. If the user writes a “0” to
this register bit and disables the “Receive STS-1 POH Processor Block” (for
interrupt generation), then all “Receive STS-1 POH Processor Block”
interrupts will be disabled for interrupt generation. If the user writes a “1” to
this register bit, he/she will still need to enable the individual “Receive STS-1
POH Processor Block” interrupt(s) at the “Source Level” in order to enable that
particular interrupt.
0 – Disable all “Receive STS-1 POH Processor Block” interrupts within the
device.
1 – Enables the “Receive STS-1 POH Processor Block” at the “Block-Level”.
Note:
2
DS3/E3
Framer Block
Interrupt
Enable
R/W
This bit-field is inactive if the XRT94L33 has been configured to
operate in the SDH Mode.
DS3/E3 Framer Block Interrupt Enable:
This READ/WRITE bit permits the user to either enable or disable the DS3/E3
Framer Block for interrupt generation. If the user writes a “0” to this register bit
and disables the “DS3/E3 Framer Block” (for interrupt generation), then all
“DS3/E3 Framer Block” interrupts will be disabled for interrupt generation. If
the user writes a “1” to this register bit, he/she will still need to enable the
individual “DS3/E3 Framer Block” interrupt(s) at the “Source Level” in order to
enable that particular interrupt.
0 – Disable all “DS3/E3 Framer Block” interrupts within the device.
1 – Enables the “DS3/E3 Framer Block” at the “Block-Level”.
1
Rx Line
Interface Block
Interrupt
Enable
R/W
Receive Line Interface Block Interrupt Enable:
This READ/WRITE bit permits the user to either enable or disable the Receive
Line Interface Block for interrupt generation. If the user writes a “0” to this
register bit and disables the “Receive Line Interface Block” (for interrupt
generation), then all “Receive Line Interface Block” interrupts will be disabled
for interrupt generation. If the user writes a “1” to this register bit, he/she will
still need to enable the individual “Receive Line Interface Block” interrupt(s) at
the “Source Level” in order to enable that particular interrupt.
0 – Disable all “Receive Line Interface Block” interrupts within the device.
1 – Enables the “Receive Line Interface Block” at the “Block-Level”.
0
Unused
R/O
56
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 13: Operation Block Interrupt Enable Register – Byte 0 (Address Location= 0x0117)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Receive
ATM Cell
Processor
Block
Interrupt
Enable
Receive
STS-3/
STM-1
TOH Block
Interrupt
Enable
Receive
SONET/
VC-3
POH Block
Interrupt
Enable
Receive
PPP
Processor
Block
Interrupt
Enable
Transmit
ATM Cell
Processor
Block
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Receive ATM Cell
Processor Block
Interrupt Enable
R/W
BIT 2
BIT 1
BIT 0
Transmit
PPP
Processor
Block
Interrupt
Enable
Unused
DESCRIPTION
Receive ATM Cell Processor Block Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Receive ATM Cell Processor Block” for interrupt generation. If the
user writes a “0” to this register bit and disables the “Receive ATM Cell
Processor Block” (for interrupt generation), then all “Receive ATM Cell
Processor Block” interrupts will be disabled for interrupt generation. If the
user writes a “1” to this register bit, he/she will still need to enable the
individual “Receive ATM Cell Processor Block” interrupt(s) at the “Source
Level” in order to enable that particular interrupt.
0 – Disables all “Receive ATM Cell Processor Block” interrupts within the
device.
1 – Enables the “Receive ATM Cell Processor Block at the “Block Level”
for interrupt generation.
6
Receive
STS-3/STM-1
TOH Block
Interrupt Enable
R/W
Receive STS-3/STM-1 TOH Processor Block Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Receive STS-3/STM-1 TOH Processor Block” for interrupt
generation. If the user writes a “0” to this register bit and disables the
“Receive STS-3/STM-1 TOH Processor Block” (for interrupt generation),
then all “Receive STS-3/STM-1 TOH Processor Block” interrupts will be
disabled for interrupt generation. If the user writes a “1” to this register bit,
he/she will still need to enable the individual “Receive STS-3/STM-1 TOH
Processor Block” interrupt(s) at the “Source Level” in order to enable that
particular interrupt.
0 – Disables all “Receive STS-3/STM-1 TOH Processor Block” interrupts
within the device.
1 – Enables the “Receive STS-3/STM-1 TOH Processor Block” at the
“Block Level” for interrupt generation.
5
Receive SONET/
VC-3
POH Block
Interrupt Enable
R/W
Receive SONET/VC-3 POH Processor Block Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Receive SONET/VC-3 POH Processor Block” for interrupt
generation. If the user writes a “0” into this register bit and disables the
“Receive SONET/VC-3 POH Processor Block” (for interrupt generation),
then all “Receive SONET/VC-3 Processor Block” interrupts will be
disabled for interrupt generation. If the user writes a “1” to this register bit,
then he/she will still need to enable the individual “Receive SONET/VC-3
POH Processor Block” Interrupt(s) at the “Source Level” in order to enable
that particular interrupt.
0 – Disables all “Receive SONET/VC-3 POH Processor Block” Interrupts
57
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
within the device.
1 – Enables the “Receive SONET/VC-3 POH Processor Block” at the
“Block Level” for interrupt generation.
4
Receive PPP
Processor Block
Interrupt Enable
R/W
Receive PPP Processor Block Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Receive PPP Processor Block” for interrupt generation. If the user
writes a “0” to this register bit and disables the “Receive PPP Processor
Block” (for interrupt generation), then all “Receive PPP Processor Block”
interrupts will be disabled for interrupt generation. If the user writes a “1”
to this register bit, he/she will still need to enable the individual “Receive
PPP Processor Block” interrupt(s) at the “Source Level” in order to enable
that particular interrupt.
0 – Disables all “Receive PPP Processor Block” interrupts within the
device.
1 – Enables the “Receive PPP Processor Block” at the “Block Level” for
interrupt generation.
3
Transmit ATM Cell
Processor Block
Interrupt Enable
R/W
Transmit ATM Cell Processor Block Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Transmit ATM Cell Processor Block” for interrupt generation. If the
user writes a “0” to this register bit and disables the “Transmit ATM Cell
Processor Block” (for interrupt generation), then all “Transmit ATM Cell
Processor Block” interrupts will be disabled for interrupt generation. If the
user writes a “1” to this register bit, he/she will still need to enable the
individual “Transmit ATM Cell Processor Block” interrupt(s) at the “Source
Level” in order to enable that particular interrupt.
0 – Disables all “Transmit ATM Cell Processor Block” interrupts within the
device.
1 – Enables the “Transmit ATM Cell Processor Block” at the “Block Level”
for interrupt generation.
2 –1
Unused
R/O
0
Transmit PPP
Processor Block
Interrupt Enable
R/W
Transmit PPP Processor Block Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Transmit PPP Processor Block” for interrupt generation. If the user
writes a “0” to this register bit and disables the “Transmit PPP Processor
Block” (for interrupt generation), then all “Transmit PPP Processor Block”
interrupts will be disabled for interrupt generation. If the user writes a “1”
to this register bit, he/she will still need to enable the individual “Transmit
PPP Processor Block” interrupt(s) at the “Source Level” in order to enable
that particular interrupt.
0 – Disables all “Transmit PPP Processor Block” interrupts within the
device.
1 – Enables the “Transmit PPP Processor Block” at the “Block Level” for
interrupt generation.
58
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 14: Mode Control Register – Byte 0 (Address Location= 0x011B)
BIT 7
BIT 6
BIT 5
BIT 4
Disable Jitter
Attenuator Fast
Lock
TBUS0_IS
_SDH
V1_PULS
E_EN
TBUS0_
MASTER
R/W
R/W
R/W
R/W
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
DISFASTLOCK
R/W
BIT 3
BIT 2
BIT 1
BIT 0
AU-3/TUG-3*
Mapping Select
Reserved
DESCRIPTION
Disable Jitter Attenuator Fast lock:
This READ/WRITE bit field is used to disable the fast lock feature for the
Jitter Attenuator block
0 – Fast Lock feature is enabled
1 – Fast Lock feature is disabled
Note:
6
TBUS0_IS_SDH
R/W
To configure the XRT94L33 such that it will comply with the
Telcordia GR-253-CORE APS Recovery time requirements of
50ms, then the “Fast Lock” feaure MUST be enabled within the
Jitter Attenuator block, by setting this bit-field to “0”
Telecom Bus 0 operating in SDH Mode
This bit is used to qualify and process a Highrate SDH signal for Subrate
Telecom Bus 0 operation.
0- Clearing this bit will disable SDH format signal validation on Telecom Bus
0. Subrate Telecom Bus 0 RxD[7:0] data bus ouput will be disabled.
1 - Setting this bit will enable SDH format signal validation on Telecom Bus
0. It enables RxD[7:0] data bus output upon reception of a valid SDH signal
format structure.
Note:
5
V1_PULSE_EN
R/W
This bit must be enabled in SDH mode for Subrate Telecom Bus 0
operation. This bit is ignored and does not apply in SONET mode
of operation.
V1 Pulse Enable
This bit provides the option of using an additional pulse on the Telecom
Drop Bus RxD_C1J1 output pin and Telecom Add Bus TxA_C1J1 pin to
denote the location or onset of V1 Byte within the Synchronous Payload
Envelope/Virtual Container of the SONET/SDH frame whenever the
Telecom Bus is processing the Virtual Tributary Group/Virtual Container
multi-frame boundary
0 - Telecom Bus 0 in STS-3/STM-1 mode will not indicate a V1 pulse on
RxD_CIJ1V1 output pin and TxA_C1J1V1 pin to indicate VT/VC multi-frame
boundary.
1 - Telecom Bus 0 in STS-3/STM-1 mode has V1 pulse added on
RxD_CIJ1V1 output pin and TxA_C1J1V1 pin to indicate VT/VC multi-frame
boundary
4
TBUS0_MASTER
R/W
Select Phase Timing Reference
This bit selects TxA_C1J1V1 and TxA_PL phase timing reference when
operating the Subrate Add Telecom Bus 0 in Rephase OFF mode.
0 - Add Telecom Bus 0 timing in Slave Mode. TxA_C1J1V1 and TxA_PL
pins are inputs.
59
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
1 - Add Telecom Bus 0 timing in Master Mode. TxA_C1J1V1 and TxA_PL
pins are outputs.
3-1
Unused
R/O
Reserved
0
AU-3/TUG-3*
R/W
AU-3/TUG-3 Mapping Select:
This READ/WRITE bit-field is used to to specify how the DS3/E3 data,
associated with Channels 0, 1 and 2 are mapped into an SDH signal, as
indicated below.
0 – DS3/E3 Channels are mapped into a VC-3, a TU-3, and then finally a
TUG-3 structure, when being mapped into an STM-1 signal.
1 – DS3/E3 Channels are mapped into a VC-3 and then an AU-3 when
being mapped into an STM-1 signal.
Note:
This register bit is only active if the XRT94L33 has been configured
to operate in the SDH Mode.
60
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 15: Loop-back Control Register – Byte 0 (Address Location= 0x011F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
Loop-back[3:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-4
Unused
R/O
3-0
Loop-back[3:0]
R/W
DESCRIPTION
Loop-back Mode[3:0]
These four READ/WRITE bits-fields permit the user to configure the
XRT94L33 to operate in a variety of loop-back modes, as is tabulated
below.
Loop-back[3:0]
Resulting Loop-back Mode
0000
Normal Mode (e.g., No Loop-back Mode)
0001
Remote Line Loop-back:
In this mode, all data that is received by the
“Receive STS-3/STM-1 PECL Interface” block
will be routed to the “Transmit STS-3/STM-1
PECL Interface” block.
Note:
If the user invokes this loop-back, then
he/she must configure the Transmit
STS-3/STM-1 PECL Interface to
operate in the Loop-timing mode by
setting Bit 6 within the Receive Line
Interface Control Register – Byte 1, to
“1” (Address Location: 0x0302).
Local Transport Loop-back:
0010
In this mode, all data that is being output via the
“Transmit STS-3 TOH Processor” block will also
be routed to the “Receive STS-3 TOH
Processor” block.
Local Path Loop-back:
0011
In this mode, all data that is output by the
Transmit SONET POH Processor block (e.g.,
towards the “Transmit STS-3 TOH Processor”
block) will be routed to the “Receive SONET
POH Processor” block.
Note:
0100 - 1111
61
This mode effect all 3 Transmit SONET
POH Processor and Receive SONET
POH Processor blocks.
Reserved – Do Not Use
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 16: Channel Interrupt Indicator – Receive SONET POH Processor Block (Address Location=
0x0120)
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Rx STS-3c
POH
Processor
Block
Interrupt
Rx SDH
POH Block
Interrupt
Rx SONET
POH Block
Interrupt Ch
2
Rx SONET
POH Block
Interrupt Ch
1
Rx SONET
POH Block
Interrupt Ch
0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-5
Unused
4
Rx STS-3c POH
Block Interrupt
R/O
DESCRIPTION
Receive STS-3c POH Processor Block Interrupt:
This READ/ONLY bit-field indicates whether or not the “Receive STS-3c
POH Processor” block, associated with Channel 0 is declaring an Interrupt,
as described below.
0 – The Receive STS-3c POH Processor block, associated with Channel 0
is NOT declaring an Interrupt.
1 – The Receive STS-3c POH Processor block, associated with Channel 0
is currently declaring an Interrupt.
Note:
3
Rx SDH POH
Block Interrupt
R/O
This register bit is only active if the XRT94L33 has been configured
to support an STS-3c signal via Channel 0.
Receive SDH POH Processor Block Interrupt:
This READ/ONLY bit-field indicates whether or not the “Receive SDH POH
Processor” block, associated with Channel 3 is declaring an Interrupt, as
described below.
0 – The Receive SDH POH Processor block, associated with Channel 3 is
NOT declaring an Interrupt.
1 – The Receive SDH POH Processor block, associated with Channel 3 is
currently declaring an interrupt.
2
Rx SONET POH
Block Interrupt
Channel 2
R/O
Receive SONET POH Processor Block Interrupt – Channel 2:
This READ/ONLY bit-field indicates whether or not the “Receive SONET
POH Processor” block, associated with Channel 2 is declaring an Interrupt,
as described below.
0 – The Receive SONET POH Processor block, associated with Channel 2
is NOT declaring an Interrupt.
1 – The Receive SONET POH Processor block, associated with Channel 2
is currently declaring an interrupt.
1
Rx SONET POH
Block Interrupt
Channel 1
R/O
Receive SONET POH Processor Block Interrupt – Channel 1:
This READ/ONLY bit-field indicates whether or not the “Receive SONET
POH Processor” block, associated with Channel 1 is declaring an Interrupt,
as described below.
0 – The Receive SONET POH Processor block, associated with Channel 9
is NOT declaring an Interrupt.
1 – The Receive SONET POH Processor block, associated with Channel 9
is currently declaring an interrupt.
62
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0
Rx SONET POH
Block Interrupt
Channel 0
R/O
Receive SONET POH Processor Block Interrupt :
This READ/ONLY bit-field indicates whether or not the “Receive SONET
POH Processor” block, associated with Channel 0 is declaring an Interrupt,
as described below.
0 – The Receive SONET POH Processor block, associated with Channel 0
is NOT declaring an Interrupt.
1 – The Receive SONET POH Processor block, associated with Channel 0
is currently declaring an interrupt.
63
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 17: Channel Interrupt Indicator – DS3/E3 Framer Block (Address Location= 0x0122)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
DS3/E3
Framer Block
Interrupt Ch 2
DS3/E3
Framer Block
Interrupt Ch 1
DS3/E3
Framer Block
Interrupt Ch 0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7 –3
Unused
R/O
2
DS3/E3 Framer
Block Interrupt
Ch 2
R/O
DESCRIPTION
DS3/E3 Framer Block Interrupt – Channel 2:
This READ/ONLY bit-field indicates whether or not the “DS3/E3 Framer”
block, associated with Channel 2 is declaring an Interrupt, as described
below.
0 – The DS3/E3 Framer block, associated with Channel 2 is NOT declaring
an Interrupt.
1 – The DS3/E3 Framer block, associated with Channel 2 is currently
declaring an interrupt.
1
DS3/E3 Framer
Block Interrupt
Ch 1
R/O
DS3/E3 Framer Block Interrupt – Channel 1:
This READ/ONLY bit-field indicates whether or not the “DS3/E3 Framer”
block, associated with Channel 1 is declaring an Interrupt, as described
below.
0 – The DS3/E3 Framer block, associated with Channel 1 is NOT declaring
an Interrupt.
1 – The DS3/E3 Framer block, associated with Channel 1 is currently
declaring an interrupt.
0
DS3/E3 Framer
Block Interrupt
Ch 0
R/O
DS3/E3 Framer Block Interrupt – Channel 0:
This READ/ONLY bit-field indicates whether or not the “DS3/E3 Framer”
block, associated with Channel 0 is declaring an Interrupt, as described
below.
0 – The DS3/E3 Framer block, associated with Channel 0 is NOT declaring
an Interrupt.
1 – The DS3/E3 Framer block, associated with Channel 0 is currently
declaring an interrupt.
64
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 18: Channel Interrupt Indicator – Receive STS-1 POH Processor Block (Address Location=
0x0123)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Rx STS-1 POH
Block Interrupt
Ch 2
Rx STS-1
POH Block
Interrupt Ch 1
Rx STS-1 POH
Block Interrupt
Ch 0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
Rx STS-1 POH
Block Interrupt
Channel 2
R/O
DESCRIPTION
Receive STS-1 POH Processor Block Interrupt – Channel 2:
This READ/ONLY bit-field indicates whether or not the “Receive STS-1 POH
Processor” block, associated with Channel 2 is declaring an Interrupt, as
described below.
0 – The Receive STS-1 POH Processor block, associated with Channel 2 is
NOT declaring an Interrupt.
1 – The Receive STS-1 POH Processor block, associated with Channel 2 is
currently declaring an interrupt.
1
Rx STS-1 POH
Block Interrupt
Channel 1
R/O
Receive STS-1 POH Processor Block Interrupt – Channel 1:
This READ/ONLY bit-field indicates whether or not the “Receive STS-1 POH
Processor” block, associated with Channel 1 is declaring an Interrupt, as
described below.
0 – The Receive STS-1 POH Processor block, associated with Channel 1 is
NOT declaring an Interrupt.
1 – The Receive STS-1 POH Processor block, associated with Channel 1 is
currently declaring an interrupt.
0
Rx STS-1 POH
Block Interrupt
Channel 0
R/O
Receive STS-1 POH Processor Block Interrupt – Channel 0:
This READ/ONLY bit-field indicates whether or not the “Receive STS-1 POH
Processor” block, associated with Channel 0 is declaring an Interrupt, as
described below.
0 – The Receive STS-1 POH Processor block, associated with Channel 0 is
NOT declaring an Interrupt.
1 – The Receive STS-1 POH Processor block, associated with Channel 0 is
currently declaring an interrupt.
65
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 19: Channel Interrupt Indicator – Receive STS-1 TOH Processor Block (Address Location=
0x0124)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Rx STS-1 TOH
Block
Interrupt Ch 2
Rx STS-1 TOH
Block
Interrupt Ch 1
Rx STS-1 TOH
Block
Interrupt Ch 0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
Rx STS-1 TOH
Block Interrupt
Channel 2
R/O
DESCRIPTION
Receive STS-1 TOH Processor Block Interrupt – Channel 2:
This READ/ONLY bit-field indicates whether or not the “Receive STS-1 TOH
Processor” block, associated with Channel 2 is declaring an Interrupt, as
described below.
0 – The Receive STS-1 TOH Processor block, associated with Channel 2 is
NOT declaring an Interrupt.
1 – The Receive STS-1 TOH Processor block, associated with Channel 2 is
currently declaring an interrupt.
1
Rx STS-1 TOH
Block Interrupt
Channel 1
R/O
Receive STS-1 TOH Processor Block Interrupt – Channel 1:
This READ/ONLY bit-field indicates whether or not the “Receive STS-1 TOH
Processor” block, associated with Channel 1 is declaring an Interrupt, as
described below.
0 – The Receive STS-1 TOH Processor block, associated with Channel 1 is
NOT declaring an Interrupt.
1 – The Receive STS-1 TOH Processor block, associated with Channel 1 is
currently declaring an interrupt.
0
Rx STS-1 TOH
Block Interrupt
Channel 0
R/O
Receive STS-1 TOH Processor Block Interrupt – Channel 0:
This READ/ONLY bit-field indicates whether or not the “Receive STS-1 TOH
Processor” block, associated with Channel 0 is declaring an Interrupt, as
described below.
0 – The Receive STS-1 TOH Processor block, associated with Channel 0 is
NOT declaring an Interrupt.
1 – The Receive STS-1 TOH Processor block, associated with Channel 0 is
currently declaring an interrupt.
66
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 20: Channel Interrupt Indicator –DS3/E3 Mapper Block (Address Location= 0x0126)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
DS3/E3
Mapper Block
Interrupt Ch 2
DS3/E3
Mapper Block
Interrupt Ch 1
DS3/E3
Mapper Block
Interrupt Ch 0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
DS3/E3 Mapper
Block Interrupt
Channel 2
R/O
DESCRIPTION
DS3/E3 Mapper Block Interrupt – Channel 2:
This READ/ONLY bit-field indicates whether or not the “DS3/E3 Mapper”
block, associated with Channel 2 is declaring an Interrupt, as described
below.
0 – The DS3/E3 Mapper block, associated with Channel 2 is NOT declaring
an Interrupt.
1 – The DS3/E3 Mapper block, associated with Channel 2 is currently
declaring an interrupt.
1
DS3/E3 Mapper
Block Interrupt
Channel 1
R/O
DS3/E3 Mapper Block Interrupt – Channel 1:
This READ/ONLY bit-field indicates whether or not the “DS3/E3 Mapper”
block, associated with Channel 1 is declaring an Interrupt, as described
below.
0 – The DS3/E3 Mapper block, associated with Channel 1 is NOT declaring
an Interrupt.
1 – The DS3/E3 Mapper block, associated with Channel 1 is currently
declaring an interrupt.
0
DS3/E3 Mapper
Block Interrupt
Channel 0
R/O
DS3/E3 Mapper Block Interrupt – Channel 0:
This READ/ONLY bit-field indicates whether or not the “DS3/E3 Mapper”
block, associated with Channel 0 is declaring an Interrupt, as described
below.
0 – The DS3/E3 Mapper block, associated with Channel 0 is NOT declaring
an Interrupt.
1 – The DS3/E3 Mapper block, associated with Channel 0 is currently
declaring an interrupt.
67
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 21: Channel Interrupt Indicator –Transmit ATM Cell Processor Block (Address Location=
0x0127)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Transmit ATM
Cell Processor
Block Interrupt
Ch 2
Transmit ATM
Cell Processor
Block Interrupt
Ch 1
Transmit ATM
Cell Processor
Block Interrupt
Ch 0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
Transmit ATM
Cell Processor
Block Interrupt
Channel 2
R/O
DESCRIPTION
Transmit ATM Cell Processor Block Interrupt – Channel 2:
This READ/ONLY bit-field indicates whether or not the “Transmit ATM Cell
Processor Block”, associated with Channel 2 is declaring an Interrupt, as
described below.
0 – The transmit ATM Cell Processor Block, associated with Channel 2 is
NOT declaring an Interrupt.
1 – The transmit ATM Cell Processor Block, associated with Channel 2 is
currently declaring an interrupt.
1
Transmit ATM
Cell Processor
Block Interrupt
Channel 1
R/O
Transmit ATM Cell Processor Block Interrupt – Channel 1:
This READ/ONLY bit-field indicates whether or not the “Transmit ATM Cell
Processor Block”, associated with Channel 1 is declaring an Interrupt, as
described below.
0 – The transmit ATM Cell Processor Block, associated with Channel 1 is
NOT declaring an Interrupt.
1 – The transmit ATM Cell Processor Block, associated with Channel 1 is
currently declaring an interrupt.
0
Transmit ATM
Cell Processor
Block Interrupt
Channel 0
R/O
Transmit ATM Cell Processor Block Interrupt – Channel 0:
This READ/ONLY bit-field indicates whether or not the “Transmit ATM Cell
Processor Block” associated with Channel 0 is declaring an Interrupt, as
described below.
0 – The transmit ATM Cell Processor Block, associated with Channel 0 is
NOT declaring an Interrupt.
1 – The transmit ATM Cell Processor Block, associated with Channel 0 is
currently declaring an interrupt.
68
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 22: Channel Interrupt Indicator –Receive ATM Cell Processor Block (Address Location= 0x0128)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Receive ATM
Cell Processor
Block Interrupt
Ch 2
Receive ATM
Cell Processor
Block Interrupt
Ch 1
Receive ATM
Cell Processor
Block Interrupt
Ch 0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
Receive ATM
Cell Processor
Block Interrupt
Channel 2
R/O
DESCRIPTION
Receive ATM Cell Processor Block Interrupt – Channel 2:
This READ/ONLY bit-field indicates whether or not the “Receive ATM Cell
Processor Block”, associated with Channel 2 is declaring an Interrupt, as
described below.
0 – The Receive ATM Cell Processor Block, associated with Channel 2 is
NOT declaring an Interrupt.
1 – The Receive ATM Cell Processor Block, associated with Channel 2 is
currently declaring an interrupt.
1
Receive ATM
Cell Processor
Block Interrupt
Channel 1
R/O
Receive ATM Cell Processor Block Interrupt – Channel 1:
This READ/ONLY bit-field indicates whether or not the “Receive ATM Cell
Processor Block”, associated with Channel 1 is declaring an Interrupt, as
described below.
0 – The Receive ATM Cell Processor Block, associated with Channel 1 is
NOT declaring an Interrupt.
1 – The Receive ATM Cell Processor Block, associated with Channel 1 is
currently declaring an interrupt.
0
Receive ATM
Cell Processor
Block Interrupt
Channel 0
R/O
Receive ATM Cell Processor Block Interrupt – Channel 0:
This READ/ONLY bit-field indicates whether or not the “Receive ATM Cell
Processor Block” associated with Channel 0 is declaring an Interrupt, as
described below.
0 – The Receive ATM Cell Processor Block, associated with Channel 0 is
NOT declaring an Interrupt.
1 – The Receive ATM Cell Processor Block, associated with Channel 0 is
currently declaring an interrupt.
69
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 23: Channel Interrupt Indicator –Transmit PPP Processor Block (Address Location= 0x0129)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Transmit PPP
Processor
Block Interrupt
Ch 2
Transmit PPP
Processor
Block Interrupt
Ch 1
Transmit PPP
Processor
Block Interrupt
Ch 0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
Transmit PPP
Processor Block
Interrupt Channel
2
R/O
DESCRIPTION
Transmit PPP Processor Block Interrupt – Channel 2:
This READ/ONLY bit-field indicates whether or not the “Transmit PPP
Processor Block”, associated with Channel 2 is declaring an Interrupt, as
described below.
0 – The Transmit PPP Processor Block, associated with Channel 2 is NOT
declaring an Interrupt.
1 – The Transmit PPP Processor Block, associated with Channel 2 is
currently declaring an interrupt.
1
Transmit PPP
Processor Block
Interrupt Channel
1
R/O
Transmit PPP Processor Block Interrupt – Channel 1:
This READ/ONLY bit-field indicates whether or not the “Transmit PPP
Processor Block”, associated with Channel 1 is declaring an Interrupt, as
described below.
0 – The Transmit PPP Processor Block, associated with Channel 1 is NOT
declaring an Interrupt.
1 – The Transmit PPP Processor Block, associated with Channel 1 is
currently declaring an interrupt.
0
Transmit PPP
Processor Block
Interrupt Channel
0
R/O
Transmit PPP Processor Block Interrupt – Channel 0:
This READ/ONLY bit-field indicates whether or not the “Transmit PPP
Processor Block” associated with Channel 0 is declaring an Interrupt, as
described below.
0 – The Transmit PPP Processor Block, associated with Channel 0 is NOT
declaring an Interrupt.
1 – The Transmit PPP Processor Block, associated with Channel 0 is
currently declaring an interrupt.
70
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 24: Channel Interrupt Indicator –Receive PPP Processor Block (Address Location= 0x012A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Receive PPP
Processor
Block Interrupt
Ch 2
Receive PPP
Processor
Block Interrupt
Ch 1
Receive PPP
Processor
Block Interrupt
Ch 0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
Receive PPP
Processor Block
Interrupt Channel
2
R/O
DESCRIPTION
Receive PPP Processor Block Interrupt – Channel 2:
This READ/ONLY bit-field indicates whether or not the “Receive PPP
Processor Block”, associated with Channel 2 is declaring an Interrupt, as
described below.
0 – The Receive PPP Processor Block, associated with Channel 2 is NOT
declaring an Interrupt.
1 – The Receive PPP Processor Block, associated with Channel 2 is
currently declaring an interrupt.
1
Receive PPP
Processor Block
Interrupt Channel
1
R/O
Receive PPP Processor Block Interrupt – Channel 1:
This READ/ONLY bit-field indicates whether or not the “Receive PPP
Processor Block”, associated with Channel 1 is declaring an Interrupt, as
described below.
0 – The Receive PPP Processor Block, associated with Channel 1 is NOT
declaring an Interrupt.
1 – The Receive PPP Processor Block, associated with Channel 1 is
currently declaring an interrupt.
0
Receive PPP
Processor Block
Interrupt Channel
0
R/O
Receive PPP Processor Block Interrupt – Channel 0:
This READ/ONLY bit-field indicates whether or not the “Receive PPP
Processor Block” associated with Channel 0 is declaring an Interrupt, as
described below.
0 – The Receive PPP Processor Block, associated with Channel 0 is NOT
declaring an Interrupt.
1 – The Receive PPP Processor Block, associated with Channel 0 is
currently declaring an interrupt.
71
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 25: Interface Control Register – Byte 1 (Address Location= 0x0132)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Receive STS-3/STM-1 Line
Select[1:0]
Unused
BIT 2
BIT 1
BIT 0
Transmit STS-3/STM-1 Line
Select[1:0]
Unused
R/O
R/O
R/W
R/W
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–6
Unused
R/O
5–4
Receive STS3/STM-1 Line
Select[1:0]
R/W
DESCRIPTION
Receive STS-3/STM-1 Line Select[1:0]:
These two READ/WRITE bit-fields permit the user to configure the
Receive STS-3 TOH Processor block to either accept its STS-3/STM-1
data from the Receive STS-3/STM-1 Telecom Bus Interface, or from the
Receive STS-3/STM-1 PECL Interface.
0, 0 – Configures the Receive STS-3 TOH Processor block to accept the
incoming STS-3/STM-1 data via the Receive STS-3/STM-1 PECL
Interface block
0, 1 – Configures the Receive STS-3 TOH Processor block to accept the
incoming STS-3/STM-1 data via the Receive STS-3/STM-1 Telecom Bus
Interface block
1, 0 and 1, 1 – Do not use.
3–2
Unused
R/O
1–0
Transmit STS3/STM-1 Line
Select[1:0]
R/W
Transmit STS-3/STM-1 Line Select[1:0]:
These two READ/WRITE bit-fields permit the user to configure the
Transmit STS-3 TOH Processor block to output its outbound STS-3/STM1 data to either the Transmit STS-3/STM-1 Telecom Bus Interface, or to
the Transmit STS-3/STM-1 PECL Interface.
0, 0 – Configures the Transmit STS-3 TOH Processor block to output the
outbound STS-3/STM-1 data via the Transmit STS-3/STM-1 PECL
Interface block
0, 1 – Configures the Transmit STS-3 TOH Processor block to output the
outbound STS-3/STM-1 data via the Transmit STS-3/STM-1 Telecom Bus
Interface block
1, 0 and 1, 1 – Do not use.
72
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 26: Interface Control Register – Byte 0 (Address Location= 0x0133)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SBSYNC_Delay[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
SBSYNC_Delay[7:0]
R/W
DESCRIPTION
STS-1 Telecom Bus – Sync Delay:
The Transmit STS-1 Telecom Bus is aligned to the “TxSBFP_in” input pin.
The user is expected to apply a pulse (with the period of a 6.48MHz clock
signal) at a rate of 8kHz to the “TxSBFP_in input (pin number G4). Each
Transmit STS-1 Telecom Bus will align its transmission of the very first
byte of a new STS-1 frame, with a pulse at this input pin.
These READ/WRITE bit-fields permit the user to specify the amount of
delay (in terms of 6.48MHz clock periods) that will exist between the rising
edge of “TxSBFP_in” and the transmission of the very first byte, within a
given STS-1 via the Transmit STS-1 Telecom Bus.
Setting this register to “0x00” configures each of the Transmit STS-1
Telecom Bus Interfaces to transmit the very first byte of a new STS-1
frame, upon detection of the rising edge of the “TxSBFP_in”.
Setting this register to “0x01” configures each of the Transmit STS-1
Telecom Bus Interfaces to delay its transmission of the very first byte of a
new STS-1 frame, by one 6.48MHz clock period, and so on.
Note:
This register is only active if at least one of the three STS-1
Telecom Bus Interfaces are enabled.
73
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 27: STS-3/STM-1 Telecom Bus Control Register – Byte 3 (Address Location= 0x0134)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HRSYNC_Delay[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
HRSYNC_Delay[15:8]
R/W
DESCRIPTION
STS-3 Telecom Bus – Sync Delay – Upper Byte:
The Transmit STS-3 Telecom Bus is aligned to the “TxSBFP_in” input
pin.
The user is expected to apply a pulse (with the period of a 6.48MHz
clock signal) at a rate of 8kHz to the “TxSBFP_in input (pin number
G4).
The Transmit STS-3/STM-1 Telecom Bus will align its
transmission of the very first byte of a new STS-3/STM-1 frame, with a
pulse at this input pin.
These READ/WRITE bit-fields permit the user to specify the amount of
delay (in terms of 19.44MHz clock periods) that will exist between the
rising edge of “TxSBFP_in” and the transmission of the very first byte,
within a given STS-3 via the Transmit STS-3/STM-1 Telecom Bus.
Setting these two registers to “0x0000” configures each of the Transmit
STS-3/STM-1 Telecom Bus Interfaces to transmit the very first byte of a
new STS-3 frame, upon detection of the rising edge of the
“TxSBFP_in”.
Setting these register to “0x0001” configures each of the Transmit STS3 Telecom Bus Interfaces to delay its transmission of the very first byte
of a new STS-3 frame, by one 19.44MHz clock period, and so on.
Note:
This register is only active if the STS-3/STM-1 Telecom Bus
Interfaces is enabled.
74
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
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Table 28: STS-3/STM-1 Telecom Bus Control Register – Byte 2 (Address Location= 0x0135)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HRSYNC_Delay[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
HRSYNC_Delay[7:0]
R/W
DESCRIPTION
STS-3 Telecom Bus – Sync Delay – Lower Byte:
The Transmit STS-3 Telecom Bus is aligned to the “TxSBFP_in” input
pin.
The user is expected to apply a pulse (with the period of a 6.48MHz
clock signal) at a rate of 8kHz to the “TxSBFP_in input (pin number
G4).
The Transmit STS-3/STM-1 Telecom Bus will align its
transmission of the very first byte of a new STS-3/STM-1 frame, with a
pulse at this input pin.
These READ/WRITE bit-fields (along with that within the “Interface
Control Register – Byte 3) permit the user to specify the amount of
delay (in terms of 19.44MHz clock periods) that will exist between the
rising edge of “TxSBFP_in” and the transmission of the very first byte,
within a given STS-3 via the Transmit STS-3/STM-1 Telecom Bus.
Setting this register to “0x0000” configures each of the Transmit STS3/STM-1 Telecom Bus Interfaces to transmit the very first byte of a new
STS-3 frame, upon detection of the rising edge of the “TxSBFP_in”.
Setting this register to “0x0001” configures each of the Transmit STS-3
Telecom Bus Interfaces to delay its transmission of the very first byte of
a new STS-3 frame, by one 19.44MHz clock period, and so on.
Note:
This register is only active if the STS-3/STM-1 Telecom Bus
Interfaces is enabled.
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Table 29: STS-3/STM-1 Telecom Bus Control Register – Byte 0 (Address Location= 0x0137)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Telecom
Bus ON
Telecom
Bus Disable
Is STS-3
Payload
Telecom
Bus Parity
Type
Telecom
Bus J1 Only
Telecom
Bus Parity
Odd
Telecom
Bus Parity
Disable
STS-3
Rephase
OFF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
Bit 7
Telecom Bus ON
R/W
DESCRIPTION
Telecom Bus Enable:
This READ/WRITE permits the user to either enable or disable the
155.52Mbps Telecom Bus Interface.
0 – Telecom Bus Interface is Disabled:
STS-3/STM-1 data will
“Clock/Data” Interface.
output
via
“Interleave/De-Interleave”
or
1 – Telecom Bus Interface is Enabled:
In this selection, the STS-3/STM-1 Transmit and Receive Telecom Bus
Interface will be enabled.
Bit 6
Telecom Bus TriState
R/W
Telecom Bus Tri-state:
This READ/WRITE bit-field permits the user to “tri-state” the Telecom Bus
Interface.
0 – Telecom Bus Interface is NOT tri-stated.
1 – Telecom Bus Interface is tri-stated.
Note:
Bit 5
Is STS-3 Payload
R/W
This READ/WRITE bit-field is ignored if the STS-3/STM-1
Transmit and Receive Telecom Bus Interface is disabled.
Is STS-3 Payload:
This READ/WRITE bit-field permits the user to enable Telecom bus 0 to
handle complete STS-3 payload
0 – All three buses are enabled
1 – Telecom Bus 0 is enabled to handle complete STS-3 payload, the
other two buses are not used.
Bit 4
Telecom Bus
Parity Type
R/W
Telecom Bus Parity Type:
This READ/WRITE bit-field permits the user to define the parameters,
over which “Telecom Bus” parity will be computed.
0 – Parity is computed/verified over the STS-3/STM-1 Transmit and
Receive Telecom Bus – data bus pins (e.g., TXA_D[7:0] and
RXD_D[7:0]).
If the user implements this selection, then the following will happen.
a.
The STS-3/STM-1 Transmit Telecom Bus Interface will compute
and output parity (via the “TXA_DP” output pin) based upon and
coincident with the data being output via the “TXA_D[7:0]” output
pins.
b.
The STS-3/STM-1 Receive Telecom Bus Interface will compute
and verify the parity data (which is input via the “RXD_DP” input
pin) based upon the data which is being input (and latched) via
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the “RXD_D[7:0]” input pins.
1 – Parity is computed/verified over the STS-3/STM-1 Transmit and
Receive Telecom Bus – data bus pins (e.g., TXA_D[7:0] and
RXD_D[7:0]); the C1J1 and PL input/output pins.
If the user implements this selection, then the following will happen.
a.
The STS-3/STM-1 Transmit Telecom Bus Interface will compute
and output parity (via the “TXA_DP” output) based upon and
coincident with (1) the data being output via the “TXA_D[7:0]”
output pins, (2) the state of the “TXA_PL” output pin, and (3) the
state of the “TXA_C1J1” output pin.
b.
The STS-3/STM-1 Transmit Telecom Bus Interface will compute
and verify the parity data (which is input via the “RXD_DP” input
pin) based upon (1) the data which is being input (and latched)
via the “RXD_D[7:0]” input pins, (2) the state of the “RXD_PL”
input pin, and (3) the state of the “RXD_C1J1” input pin.
Note:
Bit 3
Telecom Bus J1
Only
R/W
This bit-field is disabled if the STS-3/STM-1 Telecom Bus is
disabled. The user can configure the STS-3/STM-1 Telecom
Bus to compute with either even or odd parity, by writing the
appropriate data into Bit 2 (Telecom Bus Parity – Odd), within
this register.
Telecom Bus – J1 Indicator Only:
This READ/WRITE bit-field permits the user to configure how the STS3/STM-1 Transmit and Receive Telecom Bus interface handles the
“TXA_C1J1” and RXD_C1J1” signals, as described below.
0 – C1 and J1 Bytes
This selection configures the following.
c.
The STS-3/STM-1 Transmit Telecom Bus to pulse the
“TXA_C1J1” output coincident to whenever the C1 and J1 bytes
are being output via the “TXA_D[7:0]” output pins.
d.
The STS-3/STM-1 Receive Telecom Bus will expect the
“RXD_C1J1” input to pulse “high” coincident to whenever the C1
and J1 bytes are being sampled via the “RXD_D[7:0]” input pins.
1 – J1 Bytes Only
This selection configures the following.
Bit 2
Telecom Bus
Parity Odd
R/W
e.
The STS-3/STM-1 Transmit Telecom Bus Interface to only pulse
the “TXA_C1J1” output pin coincident to whenever the J1 byte is
being output via the “TXA_D[7:0]” output pins.
Note:
The “TXA_C1J1” output pin will NOT be pulsed “high” whenever
the C1 byte is being output via the “TXA_D[7:0]” output pins
f.
The STS-3/STM-1 Receive Telecom Bus Interface will expect
the “RXD_C1J1” input to only pulse “high” coincident to
whenever the J1 byte is being sampled via the “RXD_D[7:0]”
input pins.
Note:
The “RXD_C1J1” input pin will NOT be pulsed “high” whenever
the C1 byte is being input via the “RXD_D[7:0]” input pins
Telecom Bus Parity – ODD Parity Select:
This READ/WRITE bit-field permits the user to configure the STS-3/STM1 Telecom Bus Interface to do the following.
In the Transmit (Drop) Direction
The STS-3/STM-1 Telecom Bus to compute either the EVEN or ODD
parity over the contents of the (1) TxD_D[7:0] output pins, or (2)
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TxD_D[7:0] output pins, the states of the TxD_PL and TxD_C1J1 output
pins (depending upon user setting for Bit 3).
In the Receive (Add) Direction
Receive STS-3/STM-1 Telecom Bus to compute and verify the EVEN or
ODD parity over the contents of the (1) RxA_D[7:0] input pins, or (2)
RxA_D[7:0] input pins, the states of the RxA_PL and RxA_C1J1 input
pins (depending upon user setting for Bit 3).
0 – Configures Transmit (Drop) Telecom Bus to compute EVEN parity and
configures the Receive (Add) Telecom Bus to verify EVEN parity.
1 – Configures Transmit (Drop) Telecom Bus to compute ODD parity and
configures the Receive (Add) Telecom Bus to verify ODD parity.
Bit 1
Telecom Bus
Parity Disable
R/W
Telecom Bus Parity Disable:
This READ/WRITE bit-field permits the user to either enable or disable
parity calculation and placement via the “TxA_DP” output pin. This bit
field also permits the user to enable or disable parity verification by the
Receive Telecom Bus.
0 – Enables Parity Calculation (on the Transmit Telecom Bus) and
Disables Parity Verification (on the Receive Telecom Bus.
1 – Disables Parity Calculation and Verification
Bit 0
Rephase OFF
Only
R/W
Telecom Bus – Rephase Disable:
This READ/WRITE bit-field permits the user to configure the Receive
STS-3/STM-1 Telecom Bus to internally compute the Pointer Bytes,
based upon the data that it receives via the “RxD_D[7:0] input pins.
Note:
If the Receive STS-3/STM-1 Telecom Bus is being provided with
pulses denoting the C1 and J1 bytes (via the “RxD_C1J1” input
pin), then this feature is unnecessary.
1 – Disables Rephase
0 – Enables Rephase
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Table 30: Interface Control Register – Byte 2 – STS-1/STM-0 Telecom Bus 2 (Address Location=
0x0139)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
STS-1
Telecom
Bus ON # 2
STS-1
Telecom
Bus TriState # 2
Unused
STS-1
Telecom
Bus Parity
Type # 2
STS-1
Telecom
Bus J1
ONLY
STS-1
Telecom
Bus Parity
Odd
STS-1
Telecom
Bus Parity
Disable
STS-1
REPHASE
OFF
R/W
R/W
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
Bit 7
STS-1
Telecom Bus
ON # 2
R/W
DESCRIPTION
STS-1 Telecom Bus ON – Channel 2:
This READ/WRITE bit-field permits the user to either enable or disable the
Telecom Bus associated with STS-1 Telecom Bus # 2. If the STS-1 Telecom
Bus is enabled, then an STS-1 signal will be mapped into (demapped) from
the STS-3 signal. If STS-1 Telecom Bus Interface – Channel 2 is disabled,
then Channel 2 will support the mapping of DS3, E3 or STS-1 into the STS-3
signal.
0 – STS-1 Telecom Bus # 2 is disabled.
In this mode, DS3/E3/STS-1 Channel 2 will now be enabled. Depending
upon user’s selection, the following functional blocks (within Channel 2) will
now be enabled.
If DS3/E3 Framing is support
• DS3/E3 Framer Block
• DS3/E3 Mapper Block
• DS3/E3 Jitter Attenuator/De-Sync Block
If STS-1 Framing is supported
• Receive STS-1 TOH Processor Block
• Receive STS-1 POH Processor Block
• Transmit STS-1 POH Processor Block
• Transmit STS-1 TOH Processor Block
1 – STS-1 Telecom Bus # 2 is enabled.
In this mode, all DS3/E3 Framer block and STS-1 circuitry associated with
Channel 2 will be disabled.
Bit 6
STS-1
Telecom Bus
Tri-State # 2
R/W
STS-1 Telecom Bus Tri-state – Channel 2:
This READ/WRITE bit-field permits the user to “tri-state” the Telecom Bus
Interface.
0 – Telecom Bus Interface is NOT tri-stated.
1 – Telecom Bus Interface is tri-stated.
Note:
Bit 5
Unused
R/W
Bit 4
STS-1
Telecom Bus
Parity Type #
R/W
This READ/WRITE bit-field is ignored if the STS-1 Transmit and
Receive Telecom Bus Interface is disabled.
STS-1 Telecom Bus Parity Type – Channel 2:
This READ/WRITE bit-field permits the user to define the parameters, over
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which “Telecom Bus” parity will be computed.
0 – Parity is computed/verified over the STS-1 Transmit and Receive Telecom
Bus – data bus pins (e.g., STS1TXA_D_2[7:0] and STS1RXD_D_2[7:0]).
If the user implements this selection, then the following will happen.
g.
The STS-1 Receive Telecom Bus Interface will compute and output
parity (via the “STS1RXD_DP_2” output pin) based upon and
coincident with the data being output via the “STS1RXD_D_2[7:0]”
output pins.
h.
The STS-1 Transmit Telecom Bus Interface will compute and verify
the parity data (which is input via the “STS1TXA_DP_2” input pin)
based upon the data which is being input (and latched) via the
“STS1TXA_D_2[7:0]” input pins.
1 – Parity is computed/verified over the STS-1 Transmit and Receive Telecom
Bus – data bus pins (e.g., STS1TXA_D_2[7:0] and STS1RXD_D_3[7:0]); the
STS1TXA_C1J1_2,
STS1RXD_C1J1_2,
STS1TXA_PL_2
and
STS1RXD_PL_2 input/output pins.
If the user implements this selection, then the following will happen.
The STS-1 Receive Telecom Bus Interface will compute and output
parity (via the “RXD_DP_2” output) based upon and coincident with (1)
the data being output via the “STS1RXD_D_2[7:0]” output pins, (2)
the state of the “STS1RXD_PL_2” output pin, and (3) the state of the
“STS1RXD_C1J1_2” output pin.
The STS-1 Transmit Telecom Bus Interface will compute and verify
the parity data (which is input via the “STS1TXA_DP_2” input pin)
based upon (1) the data which is being input (and latched) via the
“STS1TXA_D_2[7:0]” input pins, (2) the state of the “STS1TXA_PL_2”
input pin, and (3) the state of the “STS1TXA_C1J1_2” input pin.
Note:
Bit 3
STS-1
Telecom Bus
J1
ONLY
R/W
This bit-field is disabled if the STS-1 Telecom Bus is disabled. The
user can configure the STS-1 Telecom Bus to compute with either
even or odd parity, by writing the appropriate data into Bit 2
(Telecom Bus Parity – Odd), within this register.
Telecom Bus – J1 Indicator Only – Channel 2:
This READ/WRITE bit-field permits the user to configure how the STS-1
Transmit and Receive Telecom Bus interface handles the “STS1TXA_C1J1_2”
and STS1RXD_C1J1_2” signals, as described below.
0 – C1 and J1 Bytes
This selection configures the following.
a.
The STS-1 Receive Telecom Bus to pulse the “STS1RXD_C1J1_2”
output coincident to whenever the C1 and J1 bytes are being output
via the “STS1RXD_D_2[7:0]” output pins.
b.
The
STS-1
Transmit
Telecom
Bus
will
expect
the
“STS1TXA_C1J1_2” input to pulse “high” coincident to whenever the
C1 and J1 bytes are being sampled via the “STS1TXA_D_2[7:0]”
input pins.
1 – J1 Bytes Only
This selection configures the following.
a.
The STS-1 Receive Telecom Bus Interface to only pulse the
“STS1RXD_C1J1_2” output pin coincident to whenever the J1 byte is
being output via the “STSRXD_D_2[7:0]” output pins.
Note:
The “STS1RXD_C1J1_2” output pin will NOT be pulsed “high”
whenever the C1 byte is being output via the “STS1RXD_D_2[7:0]”
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output pins
Bit 2
STS-1
Telecom Bus
Parity Odd
R/W
b.
The STS-1 Transmit Telecom Bus Interface will expect the
“STS1TXA_C1J1_2” input to only pulse “high” coincident to whenever
the J1 byte is being sampled via the “STS1TXA_D_2[7:0]” input pins.
Note:
The “STS1TXA_C1J1_2” input pin will NOT be pulsed “high”
whenever the C1 byte is being input via the “STS1TXA_D_2[7:0]”
input pins
Telecom Bus Parity – ODD Parity Select – Channel 2:
This READ/WRITE bit-field permits the user to configure the STS-1 Telecom
Bus Interface, associated with Channel 2 to do the following.
In the Receive (Drop) Direction
Receive STS-1 Telecom Bus to compute either the EVEN or ODD parity over
the contents of the (1) STS1RxD_D_2[7:0] output pins, or (2)
STS1RxD_D_2[7:0] output pins, the states of the STS1RxD_PL_2 and
STS1RxD_C1J1_2 output pins (depending upon user setting for Bit 3).
In the Transmit (Add) Direction
Transmit STS-1 Telecom Bus to compute and verify the EVEN or ODD parity
over the contents of the (1) STS1TxA_D_2[7:0] input pins, or (2)
STS1TxA_D_2[7:0] input pins, the states of the STS1TxA_PL_2 and
STS1TxA_C1J1_2 input pins (depending upon user setting for Bit 3).
0 – Configures Receive (Drop) Telecom Bus to compute EVEN parity and
configures the Transmit (Add) Telecom Bus to verify EVEN parity.
1 – Configures Receive (Drop) Telecom Bus to compute ODD parity and
configures the Transmit (Add) Telecom Bus to verify ODD parity.
Bit 1
STS-1
Telecom Bus
Parity Disable
R/W
STS-1 Telecom Bus Parity Disable – Channel 2:
This READ/WRITE bit-field permits the user to either enable or disable parity
calculation and placement via the “STSRxD_DP_2” output pin. Further, this
bit-field also permits the user to enable or disable parity verification via the
“STS1TxA_DP_2” input pin by the Transmit Telecom Bus.
1 – Disables Parity Calculation (on the Receive Telecom Bus) and Disables
Parity Verification (on the Transmit Telecom Bus.
0 – Enables Parity Calculation and Verification
Bit 0
STS-1
REPHASE
OFF
R/W
STS-1 Telecom Bus – Rephase Disable – Channel 2:
This READ/WRITE bit-field permits the user to configure the Receive STS-1
Telecom Bus to internally compute the Pointer Bytes, based upon the data
that it receives via the “RxD_D[7:0] input pins.
Note:
If the Receive STS-1 Telecom Bus is being provided with pulses
denoting the C1 and J1 bytes (via the “RxD_C1J1” input pin), then
this feature is unnecessary.
1 – Disable Rephase
0 – Enable Rephase
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Table 31: Interface Control Register – Byte 1 – STS-1/STM-0 Telecom Bus 1 (Address Location=
0x013A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
STS-1
Telecom
Bus ON
#1
STS-1
Telecom
Bus TriState # 1
Unused
STS-1
Telecom
Bus Parity
Type # 1
STS-1
Telecom
Bus J1
ONLY
STS-1
Telecom
Bus Parity
ODD
STS-1
Telecom
Bus Parity
Disable
STS-1
REPHASE
OFF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
Bit 7
STS-1
Telecom
Bus ON # 1
R/W
DESCRIPTION
STS-1 Telecom Bus ON – Channel 1:
This READ/WRITE bit-field permits the user to either enable or disable the
Telecom Bus associated with STS-1 Telecom Bus # 1. If the STS-1 Telecom
Bus is enabled, then an STS-1 signal will be mapped into (demapped from)
the STS-3 signal. If STS-1 Telecom Bus Interface – Channel 1 is disabled,
then Channel 1 will support the mapping of DS3, E3 or STS-1 into the STS-3
signal.
0 – STS-1 Telecom Bus # 1 is disabled.
In this mode, DS3/E3/STS-1 Channel 1 will now be enabled. Depending upon
user’s selection, the following functional blocks (within Channel 1) will now be
enabled.
If DS3/E3 Framing is supported
• DS3/E3 Framer Block
• DS3/E3 Mapper Block
• DS3/E3 Jitter Attenuator/De-Sync Block
If STS-1 Framing is supported
• Receive STS-1 TOH Processor Block
• Receive STS-1 POH Processor Block
• Transmit STS-1 POH Processor Block
• Transmit STS-1 TOH Processor Block
1 – STS-1 Telecom Bus # 1 is enabled.
In this mode, all DS3/E3 Framer block and STS-1 circuitry associated with
Channel 1 will be disabled.
Bit 6
STS-1
Telecom
Bus TriState # 1
R/W
STS-1 Telecom Bus Tri-state – Channel 1:
This READ/WRITE bit-field permits the user to “tri-state” the Telecom Bus
Interface.
0 – Telecom Bus Interface is NOT tri-stated.
1 – Telecom Bus Interface is tri-stated.
Note:
Bit 5
Unused
R/O
Bit 4
STS-1
Telecom
Bus Parity
R/W
This READ/WRITE bit-field is ignored if the STS-1 Transmit and
Receive Telecom Bus Interface is disabled.
STS-1 Telecom Bus Parity Type – Channel 1:
This READ/WRITE bit-field permits the user to define the parameters, over
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Type # 1
which “Telecom Bus” parity will be computed.
0 – Parity is computed/verified over the STS-1 Transmit and Receive Telecom
Bus – data bus pins (e.g., STS1TXA_D_1[7:0] and STS1RXD_D_1[7:0]).
If the user implements this selection, then the following will happen.
a.
The STS-1 Receive Telecom Bus Interface will compute and output
parity (via the “STS1RXD_DP_1” output pin) based upon and
coincident with the data being output via the “STS1RXD_D_1[7:0]”
output pins.
b.
The STS-1 Transmit Telecom Bus Interface will compute and verify
the parity data (which is input via the “STS1TXA_DP_1” input pin)
based upon the data which is being input (and latched) via the
“STS1TXA_D_1[7:0]” input pins.
1 – Parity is computed/verified over the STS-1 Transmit and Receive Telecom
Bus – data bus pins (e.g., STS1TXA_D_1[7:0] and STS1RXD_D_1[7:0]); the
STS1TXA_C1J1_1,
STS1RXD_C1J1_1,
STS1TXA_PL_1
and
STS1RXD_PL_1 input/output pins.
If the user implements this selection, then the following will happen.
Bit 3
STS-1
Telecom
Bus J1
ONLY
R/W
a.
The STS-1 Receive Telecom Bus Interface will compute and output
parity (via the “STS1RXD_DP_1” output) based upon and coincident
with (1) the data being output via the “STS1RXD_D_1[7:0]” output
pins, (2) the state of the “STS1RXD_PL_1” output pin, and (3) the
state of the “STS1RXD_C1J1_1” output pin.
b.
The STS-1 Transmit Telecom Bus Interface will compute and verify
the parity data (which is input via the “STS1TXA_DP_1” input pin)
based upon (1) the data which is being input (and latched) via the
“STS1TXA_D_1[7:0]” input pins, (2) the state of the
“STS1TXA_PL_1” input pin, and (3) the state of the
“STS1TXA_C1J1_1” input pin.
Note:
This bit-field is disabled if the STS-1 Telecom Bus is disabled. The
user can configure the STS-1 Telecom Bus to compute/verify with
either even or odd parity, by writing the appropriate data into Bit 2
(Telecom Bus Parity – Odd), within this register.
Telecom Bus – J1 Indicator Only – Channel 1:
This READ/WRITE bit-field permits the user to configure how the STS-1
Transmit and Receive Telecom Bus interface handles the “STS1TXA_C1J1_1”
and STS1RXD_C1J1_1” signals, as described below.
0 – C1 and J1 Bytes
This selection configures the following.
a.
The STS-1 Receive Telecom Bus to pulse the “STS1RXD_C1J1_1”
output coincident to whenever the C1 and J1 bytes are being output
via the “STS1RXD_D_1[7:0]” output pins.
b.
The
STS-1
Transmit
Telecom
Bus
will
expect
the
“STS1TXA_C1J1_1” input to pulse “high” coincident to whenever the
C1 and J1 bytes are being sampled via the “STS1TXA_D_1[7:0]”
input pins.
1 – J1 Bytes Only
This selection configures the following.
i.
The STS-1 Receive Telecom Bus Interface to only pulse the
“STS1RXD_C1J1_1” output pin coincident to whenever the J1 byte is
being output via the “STS1RXD_D_1[7:0]” output pins.
Note:
The “STS1RXD_C1J1_1” output pin will NOT be pulsed “high”
whenever the C1 byte is being output via the “STS1RXD_D_1[7:0]”
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output pins).
Bit 2
STS-1
Telecom
Bus Parity
Odd
R/W
j.
The STS-1 Transmit Telecom Bus Interface will expect the
“STS1TXA_C1J1_1” input to only pulse “high” coincident to whenever
the J1 byte is being sampled via the “STS1TXA_D_1[7:0]” input pins.
Note:
The “STS1TXA_C1J1_1” input pin will NOT be pulsed “high”
whenever the C1 byte is being input via the “STS1TXA_D_1[7:0]”
input pins).
Telecom Bus Parity – ODD Parity Select – Channel 1:
This READ/WRITE bit-field permits the user to configure the STS-1 Telecom
Bus Interface, associated with Channel 1 to do the following.
In the Receive (Drop) Direction
Receive STS-1 Telecom Bus to compute either the EVEN or ODD parity over
the contents of the (1) STS1RxD_D_1[7:0] output pins, or (2)
STS1RxD_D_1[7:0] output pins, the states of the STS1RxD_PL_1 and
“STS1RxD_C1J1_1 output pins (depending upon user setting for Bit 3).
In the Transmit (Add) Direction
Transmit STS-1 Telecom Bus to compute and verify the EVEN or ODD parity
over the contents of the (1) STS1TxA_D_1[7:0] input pins, or (2)
STS1TxA_D_1[7:0] input pins, the states of the STS1TxA_PL_1 and
STS1TxA_C1J1_1 input pins (depending upon user setting for Bit 3).
0 – Configures Receive (Drop) Telecom Bus to compute EVEN parity and
configures the Transmit (Add) Telecom Bus to verify EVEN parity
1 – Configures Receive (Drop) Telecom Bus to compute ODD parity and
configures the Transmit (Add) Telecom Bus to verify ODD parity.
Bit 1
STS-1
Telecom
Bus Parity
Disable
R/W
STS-1 Telecom Bus Parity Disable – Channel 1:
This READ/WRITE bit-field permits the user to either enable or disable parity
calculation and placement via the “STSRxD_DP_1” output pin. Further, this
bit field also permits the user to enable or disable parity verification via the
“STS1TxA_DP_1” input pin by the Transmit Telecom Bus.
1 – Disables Parity Calculation (on the Receive Telecom Bus) and Disables
Parity Verification (on the Transmit Telecom Bus.
0 – Enables Parity Calculation and Verification
Bit 0
STS-1
REPHASE
OFF
R/W
STS-1 Telecom Bus – Rephase Disable – Channel 1:
This READ/WRITE bit-field permits the user to configure the Receive STS-1
Telecom Bus to internally compute the Pointer Bytes, based upon the data
that it receives via the “RxD_D[7:0] input pins.
Note:
If the Receive STS-1 Telecom Bus is being provided with pulses
denoting the C1 and J1 bytes (via the “RxD_C1J1” input pin), then
this feature is unnecessary.
1 – Disables Rephase
0 – Enables Rephase
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Table 32: Interface Control Register – Byte 0 – STS-1/STM-0 Telecom Bus 0 (Address Location=
0x013B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
STS-1
Telecom
Bus ON
#0
STS-1
Telecom
Bus TriState # 0
STS-3c
REPHASE
OFF
STS-1
Telecom
Bus Parity
Type # 0
STS-1
Telecom
Bus J1
ONLY
STS-1
Telecom
Bus Parity
Odd
STS-1
Telecom
Bus Parity
Disable
STS-1
REPHASE
OFF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
Bit 7
STS-1
Telecom Bus
ON # 0
R/W
DESCRIPTION
STS-1 Telecom Bus ON – Channel 0:
This READ/WRITE bit-field permits the user to either enable or disable the
Telecom Bus associated with STS-1 Telecom Bus # 0. If the STS-1
Telecom Bus is enabled, then an STS-1 signal will be mapped into
(demapped from) the STS-3 signal. If STS-1 Telecom Bus Interface –
Channel 3 is disabled, then Channel 0 will support the mapping of DS3, E3
or STS-1 into the STS-3 signal.
0 – STS-1 Telecom Bus # 0 is disabled.
In this mode, DS3/E3/STS-1 Channel 0 will now be enabled. Depending
upon user’s selection, the following functional blocks (within Channel 0) will
now be enabled.
If DS3/E3 Framing is supported
• DS3/E3 Framer Block
• DS3/E3 Mapper Block
• DS3/E3 Jitter Attenuator/De-Sync Block
If STS-1 Framing is supported
• Receive STS-1 TOH Processor Block
• Receive STS-1 POH Processor Block
• Transmit STS-1 POH Processor Block
• Transmit STS-1 TOH Processor Block
1 – STS-1 Telecom Bus # 0 is enabled.
In this mode, all DS3/E3 Framer block and STS-1 circuitry associated with
Channel 0 will be disabled.
Bit 6
STS-1
Telecom Bus
Tri-State # 0
R/W
STS-1 Telecom Bus Tri-state – Channel 0:
This READ/WRITE bit-field permits the user to “tri-state” the Telecom Bus
Interface.
0 – Telecom Bus Interface is NOT tri-stated.
1 – Telecom Bus Interface is tri-stated.
Note:
Bit 5
STS-3c
REPHASE
OFF
R/O
This READ/WRITE bit-field is ignored if the STS-1 Transmit and
Receive Telecom Bus Interface is disabled.
STS-3c While Rephase Off:
This READ/WRITE bit-field permits the user to configure the STS-1 Telecom
Bus # 0 to process STS-3c data while the “Rephase” feature is disabled.
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0 – STS-1 Telecom Bus # 0 is processing STS-3 data.
1 – STS-1 Telecom Bus # 0 is processing STS-3c data.
Note:
Bit 4
STS-1
Telecom Bus
Parity Type # 0
R/W
This bit-field is ignored if STS-1 Telecom Bus Interface # 0 has
been configured to operate in the “Rephase” Mode.
STS-1 Telecom Bus Parity Type – Channel 0:
This READ/WRITE bit-field permits the user to define the parameters, over
which “Telecom Bus” parity will be computed.
0 – Parity is computed/verified over the STS-1 Transmit and Receive
Telecom Bus – data bus pins (e.g., STS1TXA_D_0[7:0] and
STS1RXD_D_0[7:0]).
If the user implements this selection, then the following will happen.
a.
The STS-1 Receive Telecom Bus Interface will compute and output
parity (via the “STS1RXD_DP_0” output pin) based upon and
coincident with the data being output via the “STS1RXD_D_0[7:0]”
output pins.
b.
The STS-1 Transmit Telecom Bus Interface will compute and verify
the parity data (which is input via the “STS1TXA_DP_0” input pin)
based upon the data which is being input (and latched) via the
“STS1TXA_D_0[7:0]” input pins.
1 – Parity is computed/verified over the STS-1 Transmit and Receive
Telecom Bus – data bus pins (e.g., STS1TXA_D_0[7:0] and
STS1RXD_D_0[7:0]);
the
STS1TXA_C1J1_0,
STS1RXD_C1J1_0,
STS1TXA_PL_0 and STS1RXD_PL_0 input/output pins.
If the user implements this selection, then the following will happen.
Bit 3
STS-1
Telecom Bus
J1
ONLY
R/W
a.
The STS-1 Receive Telecom Bus Interface will compute and output
parity (via the “STS1RXD_DP_0” output) based upon and
coincident with (1) the data being output via the
“STS1RXD_D_0[7:0]” output
pins, (2) the state of the
“STS1RXD_PL_0” output pin, and (3) the state of the
“STS1RXD_C1J1_0” output pin.
b.
The STS-1 Transmit Telecom Bus Interface will compute and verify
the parity data (which is input via the “STS1TXA_DP_0” input pin)
based upon (1) the data which is being input (and latched) via the
“STS1TXA_D_0[7:0]” input pins, (2) the state of the
“STS1TXA_PL_0” input pin, and (3) the state of the
“STS1TXA_C1J1_0” input pin.
Note:
This bit-field is disabled if the STS-1 Telecom Bus is disabled.
The user can configure the STS-1 Telecom Bus to compute/verify
with either even or odd parity, by writing the appropriate data into
Bit 2 (Telecom Bus Parity – Odd), within this register.
Telecom Bus – J1 Indicator Only – Channel 0:
This READ/WRITE bit-field permits the user to configure how the STS-1
Transmit and Receive Telecom Bus interface handles the
“STS1TXA_C1J1_0” and STS1RXD_C1J1_0” signals, as described below.
0 – C1 and J1 Bytes
This selection configures the following.
a.
The
STS-1
Receive
Telecom
Bus
to
pulse
the
“STS1RXD_C1J1_0” output coincident to whenever the C1 and J1
bytes are being output via the “STS1RXD_D_0[7:0]” output pins.
b.
The STS-1 Transmit Telecom Bus will expect the
“STS1TXA_C1J1_0” input to pulse “high” coincident to whenever
the C1 and J1 bytes are being sampled via the
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“STS1TXA_D_0[7:0]” input pins.
1 – J1 Bytes Only
This selection configures the following.
Bit 2
STS-1
Telecom Bus
Parity Odd
R/W
a.
The STS-1 Receive Telecom Bus Interface to only pulse the
“STS1RXD_C1J1_0” output pin coincident to whenever the J1 byte
is being output via the “STS1RXD_D_0[7:0]” output pins.
Note:
The “STS1RXD_C1J1_0” output pin will NOT be pulsed “high”
whenever the C1 byte is being output via the
“STS1RXD_D_0[7:0]” output pins
b.
The STS-1 Transmit Telecom Bus Interface will expect the
“STS1TXA_C1J1_0” input to only pulse “high” coincident to
whenever the J1 byte is being sampled via the
“STS1TXA_D_0[7:0]” input pins.
Note:
The “STS1TXA_C1J1_0” input pin will NOT be pulsed “high”
whenever the C1 byte is being input via the “STS1TXA_D_0[7:0]”
input pins
Telecom Bus Parity – ODD Parity Select – Channel 0:
This READ/WRITE bit-field permits the user to configure the STS-1
Telecom Bus Interface, associated with Channel 0 to do the following.
In the Receive (Drop) Direction
Receive STS-1 Telecom Bus to compute either the EVEN or ODD parity
over the contents of the (1) STS1RxD_D_0[7:0] output pins, or (2)
STS1RxD_D_0[7:0] output pins, the states of the STS1RxD_PL_0 and
“STS1RxD_C1J1_0 output pins (depending upon user setting for Bit 3).
In the Transmit (Add) Direction
Transmit STS-1 Telecom Bus to compute and verify the EVEN or ODD
parity over the contents of the (1) STS1TxA_D_0[7:0] input pins, or (2)
STS1TxA_D_0[7:0] input pins, the states of the STS1TxA_PL_0 and
STS1TxA_C1J1_0 input pins (depending upon user setting for Bit 3).
0 – Configures Receive (Drop) Telecom Bus to compute EVEN parity and
configures the Transmit (Add) Telecom Bus to verify EVEN parity
1 – Configures Receive (Drop) Telecom Bus to compute ODD parity and
configures the Transmit (Add) Telecom Bus to verify ODD parity.
Bit 1
STS-1
Telecom Bus
Parity Disable
R/W
STS-1 Telecom Bus Parity Disable – Channel 0:
This READ/WRITE bit-field permits the user to either enable or disable
parity calculation and placement via the “STSRxD_DP_0” output pin.
Further, this bit field also permits the user to enable or disable parity
verification via the “STS1TxA_DP_0” input pin by the Transmit Telecom
Bus.
1 – Disables Parity Calculation (on the Receive Telecom Bus) and Disables
Parity Verification (on the Transmit Telecom Bus.
0 – Enables Parity Calculation and Verification
Bit 0
STS-1
REPHASE
OFF
R/W
STS-1 Telecom Bus – Rephase Disable – Channel 0:
This READ/WRITE bit-field permits the user to configure the Receive STS-1
Telecom Bus to internally compute the Pointer Bytes, based upon the data
that it receives via the “RxD_D[7:0] input pins.
Note:
If the Receive STS-1 Telecom Bus is being provided with pulses
denoting the C1 and J1 bytes (via the “RxD_C1J1” input pin), then
this feature is unnecessary.
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1 – Disables Rephase
0 – Enables Rephase
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Table 33: Interface Control Register – STS-1/STM-0 Telecom Bus Interrupt Enable/Status Register
(Address Location= 0x013C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
TB2
RxParity
Error
Interrupt
Status
TB1
RxParity
Error
Interrupt
Status
TB0
RxParity
Error
Interrupt
Status
Unused
TB2
RxParity
Error
Interrupt
Enable
TB1
RxParity
Error
Interrupt
Enable
TB0
RxParity
Error
Interrupt
Enable
R/O
RUR
RUR
RUR
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6
Telecom Bus # 2
Receive Parity
Error Interrupt
Status
RUR
DESCRIPTION
STS-1 Telecom Bus # 2 – Receive Parity Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or “STS-1 Telecom Bus
– Channel 2” has declared a “Receive Parity Error” Interrupt since the last
read of this register.
0 – The “Receive Parity Error” Interrupt has not occurred since the last read
of this register.
1 – The “Receive Parity Error” Interrupt has occurred since the last read of
this register.
Note:
5
Telecom Bus # 1
Receive Parity
Error Interrupt
Status
RUR
This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has
been enabled.
STS-1 Telecom Bus # 1 – Receive Parity Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or “STS-1 Telecom Bus
– Channel 1” has declared a “Receive Parity Error” Interrupt since the last
read of this register.
0 – The “Receive Parity Error” Interrupt has not occurred since the last read
of this register.
1 – The “Receive Parity Error” Interrupt has occurred since the last read of
this register.
Note:
4
Telecom Bus # 0
Receive Parity
Error Interrupt
Status
RUR
This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has
been enabled.
STS-1 Telecom Bus # 0 – Receive Parity Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or “STS-1 Telecom Bus
– Channel 3” has declared a “Receive Parity Error” Interrupt since the last
read of this register.
0 – The “Receive Parity Error” Interrupt has not occurred since the last read
of this register.
1 – The “Receive Parity Error” Interrupt has occurred since the last read of
this register.
Note:
3
Unused
R/O
2
Telecom Bus # 2
– Receive Parity
Error Interrupt
R/W
This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has
been enabled.
STS-1 Telecom Bus # 2 – Receive Parity Error Interrupt Enable
This READ/WRITE bit-field permits the user to either enable or disable the
“R
i P it E
”I t
t f STS 1 T l
B
Ch
l 2 If th
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H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Enable
Rev222...000...000
“Receive Parity Error” Interrupt for STS-1 Telecom Bus – Channel 2. If the
user enables this interrupt, then STS-1 Telecom Bus – Channel 2 will
generate an interrupt anytime the “Receive STS-1 Telecom Bus” detects a
parity error within the incoming STS-1 data.
0 – Disables the “Receive Parity Error” Interrupt.
1 – Enables the “Receive Parity Error” Interrupt.
Note:
1
Telecom Bus # 1
– Receive Parity
Error Interrupt
Enable
R/W
This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has
been enabled.
STS-1 Telecom Bus # 1 – Receive Parity Error Interrupt Enable
This READ/WRITE bit-field permits the user to either enable or disable the
“Receive Parity Error” Interrupt for STS-1Telecom Bus – Channel 1. If the
user enables this interrupt, then STS-1 Telecom Bus – Channel 1 will
generate an interrupt anytime the “Receive STS-1 Telecom Bus” detects a
parity error within the incoming STS-1 data.
0 – Disables the “Receive Parity Error” Interrupt.
1 – Enables the “Receive Parity Error” Interrupt.
Note:
0
Telecom Bus # 0
– Receive Parity
Error Interrupt
Enable
R/W
This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has
been enabled.
STS-1 Telecom Bus # 0 – Receive Parity Error Interrupt Enable
This READ/WRITE bit-field permits the user to either enable or disable the
“Receive Parity Error” Interrupt for STS-1 Telecom Bus – Channel 0. If the
user enables this interrupt, then STS-1 Telecom Bus – Channel 0 will
generate an interrupt anytime the “Receive STS-1 Telecom Bus” detects a
parity error within the incoming STS-1 data.
0 – Disables the “Receive Parity Error” Interrupt.
1 – Enables the “Receive Parity Error” Interrupt.
Note:
This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has
been enabled.
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N
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S
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S
T
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S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 34: Interface Control Register – STS-1/STM-0 Telecom Bus FIFO Status Register (Address
Location = 0x013D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Unused
STS-1
Telecom
Bus Tx
Overrun
Bus 2
STS-1
Telecom
Bus Tx
Underrun
Bus 2
STS-1
Telecom
Bus Tx
Overrun
Bus 1
STS-1
Telecom
Bus Tx
Underrun
Bus 1
STS-1
Telecom
Bus Tx
Overrun
Bus 0
STS-1
Telecom
Bus Tx
Underrun
Bus 0
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6
Unused
R/O
5
STS-1
Telecom Bus –
TxFIFO
Overrun # 2
R/O
DESCRIPTION
STS-1 Telecom Bus – Transmit FIFO Overrun Indicator – Channel 2:
This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus –
Channel 2” is currently declaring a “Transmit FIFO Overrun” condition.
0 – Indicates that “STS-1 Telecom Bus – Channel 2” is NOT declaring a
“Transmit FIFO Overrun” condition.
1 – Indicates that “STS-1 Telecom Bus – Channel 2” is currently declaring a
“Transmit FIFO Overrun” condition.
Note:
4
STS-1
Telecom Bus –
TxFIFO
Underrun # 2
R/O
This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has
been enabled.
STS-1 Telecom Bus – Transmit FIFO Underrun Indicator – Channel 2:
This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus –
Channel 3” is currently declaring a “Transmit FIFO Underrun” condition.
0 – Indicates that “STS-1 Telecom Bus – Channel 2” is NOT declaring a
“Transmit FIFO Underrun” condition.
1 – Indicates that “STS-1 Telecom Bus – Channel 2” is currently declaring a
“Transmit FIFO Underrun” condition.
Note:
3
STS-1
Telecom Bus –
TxFIFO
Overrun # 1
R/O
This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has
been enabled.
STS-1 Telecom Bus – Transmit FIFO Overrun Indicator – Channel 1:
This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus –
Channel 1” is currently declaring a “Transmit FIFO Overrun” condition.
0 – Indicates that “STS-1 Telecom Bus – Channel 1” is NOT declaring a
“Transmit FIFO Overrun” condition.
1 – Indicates that “STS-1 Telecom Bus – Channel 1” is currently declaring a
“Transmit FIFO Overrun” condition.
Note:
2
STS-1
Telecom Bus –
TxFIFO
Underrun # 1
R/O
This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has
been enabled.
STS-1 Telecom Bus – Transmit FIFO Underrun Indicator – Channel 1:
This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus –
Channel 1” is currently declaring a “Transmit FIFO Underrun” condition.
0 – Indicates that “STS-1 Telecom Bus – Channel 1” is NOT declaring a
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
“Transmit FIFO Underrun” condition.
1 – Indicates that “STS-1 Telecom Bus – Channel 1” is currently declaring a
“Transmit FIFO Underrun” condition.
Note:
1
STS-1
Telecom Bus –
TxFIFO
Overrun # 0
R/O
This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has
been enabled.
STS-1 Telecom Bus – Transmit FIFO Overrun Indicator – Channel 0:
This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus –
Channel 0” is currently declaring a “Transmit FIFO Overrun” condition.
0 – Indicates that “STS-1 Telecom Bus – Channel 0” is NOT declaring a
“Transmit FIFO Overrun” condition.
1 – Indicates that “STS-1 Telecom Bus – Channel 0” is currently declaring a
“Transmit FIFO Overrun” condition.
Note:
0
STS-1
Telecom Bus –
TxFIFO
Underrun # 0
R/O
This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has
been enabled.
STS-1 Telecom Bus – Transmit FIFO Underrun Indicator – Channel 0:
This READ-ONLY bit-field indicates whether or not “STS-1 Telecom Bus –
Channel 0” is currently declaring a “Transmit FIFO Underrun” condition.
0 – Indicates that “STS-1 Telecom Bus – Channel 0” is NOT declaring a
“Transmit FIFO Underrun” condition.
1 – Indicates that “STS-1 Telecom Bus – Channel 0” is currently declaring a
“Transmit FIFO Underrun” condition.
Note:
This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has
been enabled.
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S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 35: Interface Control Register – STS-1/STM-0 Telecom Bus FIFO Interrupt Status Register
(Address Location= 0x013E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Unused
STS-1
Telecom
Bus # 2 Tx
Overrun
Interrupt
Status
STS-1
Telecom
Bus # 2 Tx
Underrun
Interrupt
Status
STS-1
Telecom
Bus # 1 Tx
Overrun
Interrupt
Status
STS-1
Telecom
Bus # 1 Tx
Underrun
Interrupt
Status
STS-1
Telecom
Bus # 0 Tx
Overrun
Interrupt
Status
STS-1
Telecom
Bus # 0 Tx
Underrun
Interrupt
Status
R/O
R/O
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6
Unused
R/O
5
STS-1 Telecom
Bus # 2 –
TxFIFO Overrun
Interrupt Status
RUR
DESCRIPTION
STS-1 Telecom Bus – TxFIFO Overrun Interrupt Status – Channel 2:
This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom
Bus – Channel 2” has declared a “TxFIFO Overrun” Interrupt since the last
read of this register.
0 – Indicates that “STS-1 Telecom Bus – Channel 2” has NOT declared a
“TxFIFO Overrun” Interrupt since the last read of this register.
1 – Indicates that “STS-1 Telecom Bus – Channel 2” has declared a
“TxFIFO Overrun” Interrupt since the last read of this register.
Note:
4
STS-1 Telecom
Bus # 2 –
TxFIFO
Underrun
Interrupt Status
RUR
This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has
been enabled.
STS-1 Telecom Bus – TxFIFO Underrun Interrupt Status – Channel 2:
This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom
Bus – Channel 2” has declared a “TxFIFO Underrun” Interrupt since the last
read of this register.
0 – Indicates that “STS-1 Telecom Bus – Channel 2” has NOT declared a
“TxFIFO Underrun” Interrupt since the last read of this register.
1 – Indicates that “STS-1 Telecom Bus – Channel 2” has declared a
“TxFIFO Overrun” Interrupt since the last read of this register.
Note:
3
STS-1 Telecom
Bus # 1 –
TxFIFO Overrun
Interrupt Status
RUR
This bit-field is only active if “STS-1 Telecom Bus – Channel 2” has
been enabled.
STS-1 Telecom Bus – TxFIFO Overrun Interrupt Status – Channel 1:
This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom
Bus – Channel 1” has declared a “TxFIFO Overrun” Interrupt since the last
read of this register.
0 – Indicates that “STS-1 Telecom Bus – Channel 1” has NOT declared a
“TxFIFO Overrun” Interrupt since the last read of this register.
1 – Indicates that “STS-1 Telecom Bus – Channel 1” has declared a
“TxFIFO Overrun” Interrupt since the last read of this register.
Note:
2
STS-1 Telecom
Bus # 1 –
RUR
This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has
been enabled.
STS-1 Telecom Bus – TxFIFO Underrun Interrupt Status – Channel 1:
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TxFIFO
Underrun
Interrupt Status
Rev222...000...000
This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom
Bus – Channel 1” has declared a “TxFIFO Underrun” Interrupt since the last
read of this register.
0 – Indicates that “STS-1 Telecom Bus – Channel 1” has NOT declared a
“TxFIFO Underrun” Interrupt since the last read of this register.
1 – Indicates that “STS-1 Telecom Bus – Channel 1” has declared a
“TxFIFO Overrun” Interrupt since the last read of this register.
Note:
1
STS-1 Telecom
Bus # 0 –
TxFIFO Overrun
Interrupt Status
RUR
This bit-field is only active if “STS-1 Telecom Bus – Channel 1” has
been enabled.
STS-1 Telecom Bus – TxFIFO Overrun Interrupt Status – Channel 0:
This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom
Bus – Channel 0” has declared a “TxFIFO Overrun” Interrupt since the last
read of this register.
0 – Indicates that “STS-1 Telecom Bus – Channel 0” has NOT declared a
“TxFIFO Overrun” Interrupt since the last read of this register.
1 – Indicates that “STS-1 Telecom Bus – Channel 0” has declared a
“TxFIFO Overrun” Interrupt since the last read of this register.
Note:
0
STS-1 Telecom
Bus # 0 –
TxFIFO
Underrun
Interrupt Status
RUR
This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has
been enabled.
STS-1 Telecom Bus – TxFIFO Underrun Interrupt Status – Channel 0:
This RESET-upon-READ bit-field indicates whether or not “STS-1 Telecom
Bus – Channel 0” has declared a “TxFIFO Underrun” Interrupt since the last
read of this register.
0 – Indicates that “STS-1 Telecom Bus – Channel 0” has NOT declared a
“TxFIFO Underrun” Interrupt since the last read of this register.
1 – Indicates that “STS-1 Telecom Bus – Channel 0” has declared a
“TxFIFO Overrun” Interrupt since the last read of this register.
Note:
This bit-field is only active if “STS-1 Telecom Bus – Channel 0” has
been enabled.
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T
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S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 36: Interface Control Register – STS-1/STM-0 Telecom Bus FIFO Interrupt Enable Register
(Address Location= 0x013F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Unused
STS-1
Telecom
Bus # 2 Tx
Overrun
Interrupt
Enable
STS-1
Telecom
Bus # 2 Tx
Underrun
Interrupt
Enable
STS-1
Telecom
Bus # 1 Tx
Overrun
Interrupt
Enable
STS-1
Telecom
Bus # 1 Tx
Underrun
Interrupt
Enable
STS-1
Telecom
Bus # 0 Tx
Overrun
Interrupt
Enable
STS-1
Telecom
Bus # 0 Tx
Underrun
Interrupt
Enable
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6
Unused
R/O
5
STS-1 Telecom
Bus # 2 TxFIFO
Overrun Interrupt
Enable
DESCRIPTION
STS-1 Telecom Bus – TxFIFO Overrun Interrupt Enable – Channel 2:
This READ/WRITE bit-field permits the user to either enable or disable the
“TxFIFO Overrun” Interrupt, associated with STS-1 Telecom Bus –
Channel 2. If the user enables this interrupt, then the “STS-1 Telecom
Bus – Channel 2” will generate an interrupt anytime it declares the
“TxFIFO Overrun” condition.
0 – Disables the “TxFIFO Overrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 2.
1 – Enables the “TxFIFO Overrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 2.
Note:
4
STS-1 Telecom
Bus # 2 TxFIFO
Underrun Interrupt
Enable
R/W
This bit-field is only active if “STS-1 Telecom Bus – Channel 2”
has been enabled.
STS-1 Telecom Bus – TxFIFO Underrun Interrupt Enable – Channel 2:
This READ/WRITE bit-field permits the user to either enable or disable the
“TxFIFO Underrun” Interrupt, associated with STS-1 Telecom Bus –
Channel 2. If the user enables this interrupt, then the “STS-1 Telecom
Bus – Channel 2” will generate an interrupt anytime it declares the
“TxFIFO Underrun” condition.
0 – Disables the “TxFIFO Underrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 2.
1 – Enables the “TxFIFO Underrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 2.
Note:
3
STS-1 Telecom
Bus # 1 TxFIFO
Overrun Interrupt
Enable
R/W
This bit-field is only active if “STS-1 Telecom Bus – Channel 2”
has been enabled.
STS-1 Telecom Bus – TxFIFO Overrun Interrupt Enable – Channel 1:
This READ/WRITE bit-field permits the user to either enable or disable the
“TxFIFO Overrun” Interrupt, associated with STS-1 Telecom Bus –
Channel 1. If the user enables this interrupt, then the “STS-1 Telecom
Bus – Channel 1” will generate an interrupt anytime it declares the
“TxFIFO Overrun” condition.
0 – Disables the “TxFIFO Overrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 1.
1 – Enables the “TxFIFO Overrun” Interrupt, associated with “STS-1
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Telecom Bus – Channel 1.
Note:
2
STS-1 Telecom
Bus # 1 TxFIFO
Underrun Interrupt
Enable
R/W
This bit-field is only active if “STS-1 Telecom Bus – Channel 1”
has been enabled.
STS-1 Telecom Bus – TxFIFO Underrun Interrupt Enable – Channel 1:
This READ/WRITE bit-field permits the user to either enable or disable the
“TxFIFO Underrun” Interrupt, associated with STS-1 Telecom Bus –
Channel 1. If the user enables this interrupt, then the “STS-1 Telecom
Bus – Channel 1” will generate an interrupt anytime it declares the
“TxFIFO Underrun” condition.
0 – Disables the “TxFIFO Underrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 1.
1 – Enables the “TxFIFO Underrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 1.
Note:
1
STS-1 Telecom
Bus # 0 TxFIFO
Overrun Interrupt
Enable
R/W
This bit-field is only active if “STS-1 Telecom Bus – Channel 1”
has been enabled.
STS-1 Telecom Bus – TxFIFO Overrun Interrupt Enable – Channel 0:
This READ/WRITE bit-field permits the user to either enable or disable the
“TxFIFO Overrun” Interrupt, associated with STS-1 Telecom Bus –
Channel 0. If the user enables this interrupt, then the “STS-1 Telecom
Bus – Channel 0” will generate an interrupt anytime it declares the
“TxFIFO Overrun” condition.
0 – Disables the “TxFIFO Overrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 0.
1 – Enables the “TxFIFO Overrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 0.
Note:
0
STS-1 Telecom
Bus # 0 TxFIFO
Underrun Interrupt
Enable
R/W
This bit-field is only active if “STS-1 Telecom Bus – Channel 0”
has been enabled.
STS-1 Telecom Bus – TxFIFO Underrun Interrupt Enable – Channel 0:
This READ/WRITE bit-field permits the user to either enable or disable the
“TxFIFO Underrun” Interrupt, associated with STS-1 Telecom Bus –
Channel 3. If the user enables this interrupt, then the “STS-1 Telecom
Bus – Channel 0” will generate an interrupt anytime it declares the
“TxFIFO Underrun” condition.
0 – Disables the “TxFIFO Underrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 0.
1 – Enables the “TxFIFO Underrun” Interrupt, associated with “STS-1
Telecom Bus – Channel 0.
Note:
This bit-field is only active if “STS-1 Telecom Bus – Channel 0”
has been enabled.
96
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A
N
N
E
L
D
S
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S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 37: Operation General Purpose Input/Output Register – Byte 0 (Address Location= 0x0147)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GPIO_7
GPIO_6
GPIO_5
GPIO_4
GPIO_3
GPIO_2
GPIO_1
GPIO_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
GPIO_7
R/W
DESCRIPTION
General Purpose Input/Output Pin # 7:
The exact function of this READ/WRITE bit-field depends upon whether the
“GPIO_7” pin is configured to be an input or an output pin.
If GPIO_7 is configured to be an input pin:
If GPIO_7 is configured to be an input pin, then this register bit operates as a
READ-ONLY bit-field that reflects the state of the “GPIO_7” (pin number
AA25) input pin.
If the “GPIO_7” input pin is pulled to a logic “HIGH”, then this register bit will be
set to “1”. Conversely, if the “GPIO_7” input pin is pulled to a logic “LOW”,
then this register bit will be set to “0”.
If GPIO_7 is configured to be an output pin:
If GPIO_7 is configured to be an output pin, then the user can control the logic
level of “GPIO_7” by writing the appropriate value into this bit-field.
Setting this bit-field to “0” causes the GPIO_7 output pin to be driven “LOW”.
Conversely, setting this bit-field to “1” causes the GPIO_7 output pin to be
driven “HIGH”.
Note:
6
GPIO_6
R/W
This register bit-field is only active if STS-1 Telecom Bus – Channel 2
is enabled.
General Purpose Input/Output Pin # 6:
The exact function of this READ/WRITE bit-field depends upon whether the
“GPIO_6” pin is configured to be an input or an output pin.
If GPIO_6 is configured to be an input pin:
If GPIO_6 is configured to be an input pin, then this register bit operates as a
READ-ONLY bit-field that reflects the state of the “GPIO_6” (pin number W24)
input pin.
If the “GPIO_6” input pin is pulled to a logic “HIGH”, then this register bit will be
set to “1”. Conversely, if the “GPIO_6” input pin is pulled to a logic “LOW”,
then this register bit will be set to “0”.
If GPIO_6 is configured to be an output pin:
If GPIO_6 is configured to be an output pin, then the user can control the logic
level of “GPIO_6” by writing the appropriate value into this bit-field.
Setting this bit-field to “0” causes the GPIO_6 output pin to be driven “LOW”.
Conversely, setting this bit-field to “1” causes the GPIO_6 output pin to be
driven “HIGH”.
Note:
5
GPIO_5
R/W
This register bit-field is only active if STS-1 Telecom Bus – Channel 2
is enabled.
General Purpose Input/Output Pin # 5:
The exact function of this READ/WRITE bit-field depends upon whether the
“GPIO_5” pin is configured to be an input or an output pin.
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If GPIO_5 is configured to be an input pin:
If GPIO_5 is configured to be an input pin, then this register bit operates as a
READ-ONLY bit-field that reflects the state of the “GPIO_5” (pin number
AC26) input pin.
If the “GPIO_5” input pin is pulled to a logic “HIGH”, then this register bit will be
set to “1”. Conversely, if the “GPIO_5” input pin is pulled to a logic “LOW”,
then this register bit will be set to “0”.
If GPIO_5 is configured to be an output pin:
If GPIO_5 is configured to be an output pin, then the user can control the logic
level of “GPIO_5” by writing the appropriate value into this bit-field.
Setting this bit-field to “0” causes the GPIO_5 output pin to be driven “LOW”.
Conversely, setting this bit-field to “1” causes the GPIO_5 output pin to be
driven “HIGH”.
Note:
4
GPIO_4
R/W
This register bit-field is only active if STS-1 Telecom Bus – Channel 1
is enabled.
General Purpose Input/Output Pin # 4:
The exact function of this READ/WRITE bit-field depends upon whether the
“GPIO_4” pin is configured to be an input or an output pin.
If GPIO_4 is configured to be an input pin:
If GPIO_4 is configured to be an input pin, then this register bit operates as a
READ-ONLY bit-field that reflects the state of the “GPIO_4” (pin number Y25)
input pin.
If the “GPIO_4” input pin is pulled to a logic “HIGH”, then this register bit will be
set to “1”. Conversely, if the “GPIO_4” input pin is pulled to a logic “LOW”,
then this register bit will be set to “0”.
If GPIO_4 is configured to be an output pin:
If GPIO_4 is configured to be an output pin, then the user can control the logic
level of “GPIO_4” by writing the appropriate value into this bit-field.
Setting this bit-field to “0” causes the GPIO_4 output pin to be driven “LOW”.
Conversely, setting this bit-field to “1” causes the GPIO_4 output pin to be
driven “HIGH”.
Note:
3
GPIO_3
R/W
This register bit-field is only active if STS-1 Telecom Bus – Channel 1
is enabled.
General Purpose Input/Output Pin # 3:
The exact function of this READ/WRITE bit-field depends upon whether the
“GPIO_3” pin is configured to be an input or an output pin.
If GPIO_3 is configured to be an input pin:
If GPIO_3 is configured to be an input pin, then this register bit operates as a
READ-ONLY bit-field that reflects the state of the “GPIO_3” (pin number
AB26) input pin.
If the “GPIO_3” input pin is pulled to a logic “HIGH”, then this register bit will be
set to “1”. Conversely, if the “GPIO_3” input pin is pulled to a logic “LOW”,
then this register bit will be set to “0”.
If GPIO_3 is configured to be an output pin:
If GPIO_3 is configured to be an output pin, then the user can control the logic
level of “GPIO_3” by writing the appropriate value into this bit-field.
Setting this bit-field to “0” causes the GPIO_3 output pin to be driven “LOW”.
Conversely, setting this bit-field to “1” causes the GPIO_3 output pin to be
driven “HIGH”.
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Note:
2
GPIO_2
R/W
This register bit-field is only active if STS-1 Telecom Bus – Channel 1
is enabled.
General Purpose Input/Output Pin # 2:
The exact function of this READ/WRITE bit-field depends upon whether the
“GPIO_2” pin is configured to be an input or an output pin.
If GPIO_2 is configured to be an input pin:
If GPIO_2 is configured to be an input pin, then this register bit operates as a
READ-ONLY bit-field that reflects the state of the “GPIO_2” (pin number V23)
input pin.
If the “GPIO_2” input pin is pulled to a logic “HIGH”, then this register bit will be
set to “1”. Conversely, if the “GPIO_2” input pin is pulled to a logic “LOW”,
then this register bit will be set to “0”.
If GPIO_2 is configured to be an output pin:
If GPIO_2 is configured to be an output pin, then the user can control the logic
level of “GPIO_2” by writing the appropriate value into this bit-field.
Setting this bit-field to “0” causes the GPIO_2 output pin to be driven “LOW”.
Conversely, setting this bit-field to “1” causes the GPIO_2 output pin to be
driven “HIGH”.
Note:
1
GPIO_1
R/W
This register bit-field is only active if STS-1 Telecom Bus – Channel 0
is enabled.
General Purpose Input/Output Pin # 1:
The exact function of this READ/WRITE bit-field depends upon whether the
“GPIO_1” pin is configured to be an input or an output pin.
If GPIO_1 is configured to be an input pin:
If GPIO_1 is configured to be an input pin, then this register bit operates as a
READ-ONLY bit-field that reflects the state of the “GPIO_1” (pin number
AC27) input pin.
If the “GPIO_1” input pin is pulled to a logic “HIGH”, then this register bit will be
set to “1”. Conversely, if the “GPIO_1” input pin is pulled to a logic “LOW”,
then this register bit will be set to “0”.
If GPIO_1 is configured to be an output pin:
If GPIO_1 is configured to be an output pin, then the user can control the logic
level of “GPIO_1” by writing the appropriate value into this bit-field.
Setting this bit-field to “0” causes the GPIO_1 output pin to be driven “LOW”.
Conversely, setting this bit-field to “1” causes the GPIO_1 output pin to be
driven “HIGH”.
Note:
0
GPIO_0
R/W
This register bit-field is only active if STS-1 Telecom Bus – Channel 0
is enabled.
General Purpose Input/Output Pin # 0:
The exact function of this READ/WRITE bit-field depends upon whether the
“GPIO_0” pin is configured to be an input or an output pin.
If GPIO_0 is configured to be an input pin:
If GPIO_0 is configured to be an input pin, then this register bit operates as a
READ-ONLY bit-field that reflects the state of the “GPIO_0” (pin number W25)
input pin.
If the “GPIO_0” input pin is pulled to a logic “HIGH”, then this register bit will be
set to “1”. Conversely, if the “GPIO_0” input pin is pulled to a logic “LOW”,
then this register bit will be set to “0”.
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If GPIO_0 is configured to be an output pin:
If GPIO_0 is configured to be an output pin, then the user can control the logic
level of “GPIO_0” by writing the appropriate value into this bit-field.
Setting this bit-field to “0” causes the GPIO_0 output pin to be driven “LOW”.
Conversely, setting this bit-field to “1” causes the GPIO_0 output pin to be
driven “HIGH”.
Note:
This register bit-field is only active if STS-1 Telecom Bus – Channel 0
is enabled.
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Table 38: Operation General Purpose Input/Output Direction Register 0 (Address Location= 0x014B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GPIO_DIR[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
GPIO_DIR[7]
R/W
DESCRIPTION
GPIO_7 Direction Select:
This READ/WRITE bit-field permits the user to configure the “GPIO_7” pin
(pin number AA25) to function as either an input or an output pin.
0 – Configures GPIO_7 to function as an input pin.
1 – Configures GPIO_7 to function as an output pin.
Note:
6
GPIO_DIR[6]
R/W
This register bit-field is only active if STS-1 Telecom Bus Interface –
Channel 2 is enabled.
GPIO_6 Direction Select:
This READ/WRITE bit-field permits the user to configure the “GPIO_6” pin
(pin number W24) to function as either an input or an output pin.
0 – Configures GPIO_6 to function as an input pin.
1 – Configures GPIO_6 to function as an output pin.
Note:
5
GPIO_DIR[5]
R/W
This register bit-field is only active if STS-1 Telecom Bus Interface –
Channel 2 is enabled.
GPIO_5 Direction Select:
This READ/WRITE bit-field permits the user to configure the “GPIO_5” pin
(pin number AC26) to function as either an input or an output pin.
0 – Configures GPIO_5 to function as an input pin.
1 – Configures GPIO_5 to function as an output pin.
Note:
4
GPIO_DIR[4]
R/W
This register bit-field is only active if STS-1 Telecom Bus Interface –
Channel 1 is enabled.
GPIO_4 Direction Select:
This READ/WRITE bit-field permits the user to configure the “GPIO_4” pin
(pin number Y25) to function as either an input or an output pin.
0 – Configures GPIO_4 to function as an input pin.
1 – Configures GPIO_4 to function as an output pin.
Note:
3
GPIO_DIR[3]
R/W
This register bit-field is only active if STS-1 Telecom Bus Interface
– Channel 1 is enabled.
GPIO_3 Direction Select:
This READ/WRITE bit-field permits the user to configure the “GPIO_3” pin
(pin number AB26) to function as either an input or an output pin.
0 – Configures GPIO_3 to function as an input pin.
1 – Configures GPIO_3 to function as an output pin.
Note:
This register bit-field is only active if STS-1 Telecom Bus Interface –
Channel 1 is enabled.
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GPIO_DIR[2]
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GPIO_2 Direction Select:
This READ/WRITE bit-field permits the user to configure the “GPIO_2” pin
(pin number V23) to function as either an input or an output pin.
0 – Configures GPIO_2 to function as an input pin.
1 – Configures GPIO_2 to function as an output pin.
Note:
1
GPIO_DIR[1]
R/W
This register bit-field is only active if STS-1 Telecom Bus Interface
– Channel 0 is enabled.
GPIO_1 Direction Select:
This READ/WRITE bit-field permits the user to configure the “GPIO_1” pin
(pin number AC27) to function as either an input or an output pin.
0 – Configures GPIO_1 to function as an input pin.
1 – Configures GPIO_1 to function as an output pin.
Note:
0
GPIO_DIR[0]
R/W
This register bit-field is only active if STS-1 Telecom Bus Interface –
Channel 0 is enabled.
GPIO_0 Direction Select:
This READ/WRITE bit-field permits the user to configure the “GPIO_0” pin
(pin number W25) to function as either an input or an output pin.
0 – Configures GPIO_0 to function as an input pin.
1 – Configures GPIO_0 to function as an output pin.
Note:
This register bit-field is only active if STS-1 Telecom Bus Interface –
Channel 0 is enabled.
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Table 39: Operation Output Control Register – Byte 1 (Address Location= 0x0150)
BIT 7
BIT 6
BIT 5
8kHz or
STUFF Out
Enable
8kHz OUT
Select
Egress
Direction
Monitored –
STUFF
Output
R/W
R/W
R/W
R/O
R/O
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
8kHz or STUFF
Out Enable
R/W
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R/O
R/O
R/O
0
0
0
Unused
DESCRIPTION
8kHz or STUFF Output Enable – LOF Output Pin:
This READ/WRITE bit-field, along with Bit 6 (8kHz OUT Select) permits
the user to define the role of the LOF output pin (pin AD11). The
relationship between the states of these bit-fields and the corresponding
role of the LOF output pin is presented below.
Bit 7 (8kHz
or STUFF
Out Enable)
Bit 6 (8kHz
OUT Select)
Role of LOF output pin
0
0
LOF or AIS-L Indicator
0
1
LOF or AIS-L Indicator
1
0
Bit Stuff Indicator Output
1
1
8kHz Output
Note:
1. If Bit 7 is set to “0”, then Bit 1 (AIS-L Output Enable) within the “Receive
STS-3 Transport – Auto AIS (in Downstream STS-1s) Control Register
(Address Location= 0x116B) will indictate whether or not pin AD11 is the
“LOF” or the “AIS-L” output indicator.
2. If Bit 1 (AIS-L Output Enable) is set to “0”, then pin AD11 will function
as the LOF output indicator.
3. If Bit 1 (AIS-L Output Enable) is set to “1”, then pin AD11 will function
as the AIS-L output indicator.
6
8kHz OUT Select
R/W
8kHz OUT – LOF Output Pin:
This READ/WRITE bit-field, along with Bit 6 (8kHz OUT Select) permits
the user to define the role of the LOF output pin (pin AD11). The
relationship between the states of these bit-fields and the corresponding
role of the LOF output pin is presented below.
Bit 7 (8kHz or
STUFF Out
Enable)
Bit 6 (8kHz OUT
Select)
Role of LOF output pin
0
0
LOF or AIS-L Indicator
0
1
LOF or AIS-L Indicator
1
0
Bit Stuff Indicator Output
1
1
8kHz Output
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Monitored –STUFF
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R/W
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Egress Direction Monitored – STUFF Output:
If the LOF output pin has been configured to function as a “STUFF
Indicator” output, then it can be configured to reflect the current stuff
opportunities of the channel designated by Bits 7 through 4 (Stuff Indicator
Channel Select[3:0]) within the Operation Output Control Register – Byte
0.
This READ/WRITE bit-field permits the user to configure the LOF output
pin to either reflect the “current stuff opportunities” for the Ingress or
Egress Path of the selected channel.
0 – Configures the LOF output pin to reflect the “current stuff opportunity”
of the Ingress Path of the “selected” channel.
1 – Configures the LOF output pin to reflect the “current stuff opportunity”
of the Egress Path of the “selected” channel.
Note:
4–0
Unused
This bit-field will be ignored if the “selected” channel has been
configured to operate in the STS-1 Mode.
R/O
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Table 40: Operation Output Control Register – Byte 0 (Address Location= 0x0153)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Stuff Indicator Channel
Select[1:0]
Unused
BIT 2
BIT 1
BIT 0
8kHz Source Channel
Select[1:0]
Unused
R/O
R/O
R/W
R/W
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–6
Unused
R/O
5–4
Stuff Indicator
Channel Select[1:0]
R/W
DESCRIPTION
Stuff Indicator – Channel Select[1:0]:
These two (2) READ/WRITE bit-fields permit the user to identify which
of the 3 channels should have their “bit-stuff opportunity” status
reflected on the LOF output pin.
Setting these bit-fields to [0, 0] configures the LOF output pin to reflect
the bit-stuff opportunity status of Channel 0. Likewise, setting these bitfields to [1, 0] configures the LOF output pin to reflect the bit-stuff
opportunity status of Channel 2.
Note:
These bit-fields are ignored if any of the following are true.
1. If the corresponding channel has been configured to operate in the
STS-1 Mode.
2. If the LOF output pin has been configured to function as the LOF or
AIS-L indicator output.
3. If the LOF output pin has been configured to function as an 8kHz
output pin.
3–2
Unused
R/O
1–0
8kHz Source Channel
Select[1:0]
R/W
8kHz Source Channel Select[1:0]:
If the LOF output pin has been configured to output an 8kHz clock
output signal, then the XRT94L33 will derive this 8kHz clock signal,
from the Ingress DS3/E3 or Receive STS-1 signal of the “Selected”
channel.
These two(2) READ/WRITE bit-fields permit the user to specify the
“Selected” channel.
Setting these bit-fields to [0, 0] configures the LOF output pin to output
an 8kHz clock signal, that is derived from the Ingress DS3/E3 or
Receive STS-1 input signal of Channel 0. Likewise, setting these bitfields to [1, 0] configures the LOF output pin to reflect the bit-stuff
opportunity status of Channel 2.
Note:
These bit-fields are ignored if any of the following are true.
1. If the LOF output pin has been configured to function as the LOF or
AIS-L indicator output.
2. If the LOF output pin has been configured to function as the “Stuff
Indicator” output pin.
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Table 41: Operation Slow Speed Port Control Register – Byte 1 (Address Location= 0x0154)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SSI Enable
SSI Insert
SSI Force
Zero
Unused
SSE Enable
SSE Insert
SSE Force
Zero
Unused
R/W
R/W
R/W
R/O
R/W
R/W
R/W
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
SSI Enable
R/W
DESCRIPTION
Slow-Speed Ingress – Interface Port Enable:
This READ/WRITE bit-field permits the user to enable or disable the SSI
(Slow-Speed Ingress) Interface Port.
If the SSI Interface port is enabled, then it can be used to either monitor
(e.g., extract) or to replace (e.g., insert) a DS3, E3 or STS-1 signal, into the
Ingress DS3/E3 or Receive STS-1 path of the “Selected” channel.
0 – Disables the SSI Interface Port.
1 – Enables the SSI Interface Port.
6
SSI Insert
R/W
Slow-Speed Ingress – Interface Port – Insert:
This READ/WRITE bit-field permits the user to configure the SSI Interface
port to either monitor (e.g., extract) an “Ingress DS3/E3” or “Receive STS-1”
signal, or to replace (e.g., insert) a DS3, E3 or STS-1 signal into the Ingress
DS3/E3 or Receive STS-1 path of the “Selected” channel.
If the user configures the SSI Interface port to monitor a given DS3, E3 or
STS-1 signal, then the SSI Interface will then be configured to be an “output”
interface. In this case, the SSI Interface port will consist of an “SSI_POS”,
“SSI_NEG” and “SSI_CLK” output signals. Additionally, a copy of the
Ingress DS3/E3 or Receive STS-1 signal will be output via this output port.
If the user configures the SSI Interface port to replace (e.g., insert) an
“Ingress DS3/E3” or Receive STS-1 signal, then the SSI Interface will then
be configured to be an “input” interface. In this case, the SSI Interface port
will consist of an “SSI_POS”, “SSI_NEG” and “SSI_CLK” input signals.
Additionally, the DS3, E3 or STS-1 signal, that is applied at this input port
will overwrite that of the “Ingress DS3/E3” or the Receive STS-1 signal.
0 – Configures the SSI Interface as an output port that will permit the user to
monitor the “selected” Ingress DS3/E3 or Receive STS-1 signal.
1 – Configures the SSI Interface as an input port. In this configuration, the
DS3, E3 or STS-1 signal that is input via this port will replace/overwrite the
“Ingress” DS3/E3 or Receive STS-1 signal, within the “selected” channel,
prior to being mapped into STS-3.
Note:
5
SSI Force Zero
R/W
This bit-field will be ignored if the SSI Interface port is disabled.
Slow Speed Ingress – Interface Port – Force to All Zeros:
This READ/WRITE bit-field permits the user to force the Ingress DS3/E3 or
Receive STS-1 signal, within the “selected” channel to an “All Zeros”
pattern.
0 – Configures the Ingress DS3/E3 or Receive STS-1 signal (within the
“selected” channel) to flow to the DS3/E3 Mapper Block or to the Transmit
SONET POH Processor block, in a normal manner.
1 – Forces the data, within the Ingress DS3/E3 or Receive STS-1 signal
(within the “selected” channel) to an “All Zeros” pattern.
106
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Note:
4
Unused
R/O
3
SSE Enable
R/W
This bit-field will be ignored if the SSI Interface port is disabled.
Slow-Speed Egress – Interface Port Enable:
This READ/WRITE bit-field permits the user to enable or disable the SSE
(Slow Speed Egress) Interface Port.
If the SSE Interface port is enabled, then it can be used to either monitor
(e.g., extract) or to replace (e.g., insert) a DS3, E3 or STS-1 signal, into the
Egress DS3/E3 or Transmit STS-1 path of the “Selected” channel.
0 – Disables the SSE Interface Port
1 – Enables the SSE Interface Port.
2
SSE Insert
R/W
Slow Speed Egress – Interface Port – Insert:
This READ/WRITE bit-field permits the user to configure the SSE Interface
port to either monitor (e.g., extract) an “Egress DS3/E3” or “Receive STS-1”
signal, or to replace (e.g., insert) a DS3, E3 or STS-1 signal into the Egress
DS3/E3 or Transmit STS-1 path of the “Selected” channel.
If the user configures the SSE Interface port to monitor a given DS3, E3 or
STS-1 signal, then the SSE Interface wil then be configured to be an
“output” interface. In this case, the SSE Interface port will consist of an
“SSE_POS”, “SSE_NEG” and “SSE_CLK” output signals. Additionally, a
copy of the Egress DS3/E3 or Transmit STS-1 signal will be output via this
output port.
If the user configures the SSE Interface port to replace (e.g., insert) an
“Egress DS3/E3” or Transmit STS-1 signal, then the SSE Interface will then
be configured to be an “input” interface. In this case, the SSE Interface port
will consist of an “SSE_POS”, “SSE_NEG” and “SSE_CLK” input signals.
Additionally, the DS3, E3 or STS-1 signal, that is applied at this input port
will overwrite that of the “Egress DS3/E3” or the Transmit STS-1 signal.
0 – Configures the SSE Interface as an output port that will permit the user
to monitor the “selected” Egress DS3/E3 or Transmit STS-1 signal..
1 – Configures the SSE Interface as an input port. In this configuration, the
DS3, E3 or STS-1 signal, that is input via this port will replace/overwrite the
“Egress” DS3/E3 or Transmit STS-1 signal, within the “selected” channel,
prior to being mapped into STS-3.
Note:
1
SSE Force Zero
R/W
This bit-field will be ignored if the SSE Interface port is disabled.
Slow Speed Egress – Interface Port – Force to All Zeros:
This READ/WRITE bit-field permits the user to force the Egress DS3/E3 or
Transmit STS-1 signal, within the “selected” channel to an “All Zeros”
pattern.
0 – Configures the Egress DS3/E3 or Transmit STS-1 signal (within the
“selected” channel) to flow to the DS3/E3/STS-1 LIU IC in a normal manner.
1 – Forces the data, within the Egress DS3/E3 or Transmit STS-1 signal
(within the “selected” channel) to an “All Zeros” pattern.
Note:
0
Unused
This bit-field will be ignored if the SSE Interface port is disabled.
R/O
107
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 42: Operation Slow Speed Port Control Register – Byte 0 (Address Location= 0x0157)
BIT 7
BIT 6
Unused
BIT 5
BIT 4
BIT 3
SSI_Channel_Select[1:0]
BIT 2
Unused
BIT 1
BIT 0
SSE_Channel_Select[1:0]
R/O
R/O
R/W
R/W
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7–6
Unused
R/O
5–4
SSI_Channel_Select[
1:0]:
R/W
DESCRIPTION
Slow-Speed Ingress – Interface Port – Channel Select[1:0]:
These READ/WRITE bit-fields permit the user to select which of the 3
Ingress DS3/E3 or Receive STS-1 signals will be processed via the SSI
Interface port.
Setting SSI_Channel_Select[1:0] to [0, 0] configures the SSI Interface port
to process the Ingress DS3/E3 or Receive STS-1 signal associated with
Channel 0. Likewise, setting SSI_Channel_Select[1:0] to [1, 0] configures
the SSI Interface port to process the Ingress DS3/E3 or Receive STS-1
signal associated with Channel 2.
Note:
3 –2
Unused
R/O
1–0
SSE_Channel_Select
[1:0]
R/W
These bit-fields are ignored if the SSI Interface port is disabled.
Slow Speed Egress – Interface Port – Channel Select[1:0]:
These READ/WRITE bit-fields permit the user to select which of the 3
Egress DS3/E3 or Receive STS-1 signals will be processed via the SSE
Interface port.
Setting SSE_Channel_Select[1:0] to [0, 0] configures the SSE Interface
port to process the Egress DS3/E3 or Transmit STS-1 signal associated
with Channel 0. Likewise, setting SSE_Channel_Select[1:0] to [1, 0]
configures the SSE Interface port to process the Egress DS3/E3 or
Transmit STS-1 signal associated with Channel 2.
Note:
These bit-fields are ignored if the SSE Interface port is disab led.
108
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 43: Operation – DS3/E3/STS-1 Clock Frequency Out of Range Detection – Direction Register
(Address Location= 0x0158)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ON_EGRESS
DIRECTION
Unused
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7–1
Unused
R/O
0
ON_EGRESS_DIRECTION
R/W
DESCRIPTION
Frequency Out of Range Detection on Egress Direction:
This READ/WRITE bit-field permits the user to configure the
“DS3/E3/STS-1 Clock Frequency – Out of Range Detector” to
operate in either the Ingress or Egress direction.
0 – Configures the DS3/E3/STS-1 Clock Frequency – Out of
Range Detector” to operate on the DS3, E3 or STS-1 clock signals
in the Ingress Direction.
1 – Configures the DS3/E3/STS-1 Clock Frequency – Out of
Range Detector” to operate on the DS3, E3 or STS-1 clock signals
in the Egress Direction.
Table 44: Operation – DS3/E3/STS-1Clock Frequency – DS3 Out of Range Detection Threshold
Register (Address Location= 0x015A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DS3_OUT_OF_RANGE_DETECTION_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7–0
DS3_OUT_OF_RANGE_
DETECTION_THR
R/W
DESCRIPTION
DS3 Out of Range – Detection Threshold[7:0]:
These eight READ/WRITE bit-fields permit the user to define (in
terms of ppm) the frequency difference that must exist between a
given DS3 signal (in either the Ingress or Egress direction) and that
of the REFCLK45 input clock signal; before the XRT94L33 will
declare a “DS3 Clock Frequency – Out of Range” condition.
109
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 45: Operation – DS3/E3/STS-1Clock Frequency – STS-1/E3 Out of Range Detection Threshold
Registers (Address Location= 0x015B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
STS-1/E3_OUT_OF_RANGE_DETECTION_THRESHOLD[7:0]
BIT
NUMBER
NAME
TYPE
7–0
STS1/E3_OUT_OF_RAN
GE_DETECTION_THR
R/W
DESCRIPTION
STS-1/E3 Out of Range – Detection Threshold[7:0]:
These eight READ/WRITE bit-fields permit the user to define (in
terms of ppm) the frequency difference that must exist between a
given STS-1 or E3 signal (in either the Ingress or Egress direction)
and that of the REFCLK51/REFCLK34 input clock signal; before the
XRT94L33 will declare a “STS-1/E3 Clock Frequency – Out of
Range” condition.
Table 46: Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Enable Register – Byte 0
(Address Location=0x015D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Out of Range –
Channel 2
Interrupt enable
Out of Range –
Channel 1
Interrupt Enable
Out of Range –
Channel 0
Interrupt Enable
R/O
R/O
R/O
R/O
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-3
Unused
R/O
2
Out of Range – Channel 2
Interrupt Enable
R/W
DESCRIPTION
DS3/E3/STS-1 Frequency – Out of Range – Channel 2 –
Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt
for Channel 2.
If the user enables this interrupt, then the XRT94L33 will generate
an interrupt anytime the frequency of the DS3, E3 or STS-1 signal
(in the selected direction – Ingress or Egress) within Channel 2,
differs from its corresponding Reference Clock signal (e.g.,
REFCLK45, REFCLK34 or REFCLK51) by its “Out of Range
Detection Threshold” (in terms of ppm) or more.
0 – Disables the “DS3/E3/STS-1 Frequency – Out of Range”
Interrupt for Channel 2.
1 – Enables the “DS3/E3/STS-1 Frequency
Interrupt for Channel 2.
1
Out of Range – Channel 1
Interrupt Enable
R/W
- Out of Range”
DS3/E3/STS-1 Frequency – Out of Range – Channel 1 –
Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt
110
XRT94L33
Rev222...000...000
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
for Channel 1.
If the user enables this interrupt, then the XRT94L33 will generate
an interrupt anytime the frequency of the DS3, E3 or STS-1 signal
(in the selected direction – Ingress or Egress) within Channel 1,
differs from its corresponding Reference Clock signal (e.g.,
REFCLK45, REFCLK34 or REFCLK51) by its “Out of Range
Detection Threshold” (in terms of ppm) or more.
0 – Disables the “DS3/E3/STS-1 Frequency – Out of Range”
Interrupt for Channel 1.
1 – Enables the “DS3/E3/STS-1 Frequency
Interrupt for Channel 1.
0
Out of Range – Channel 0
Interrupt Enable
R/W
- Out of Range”
DS3/E3/STS-1 Frequency – Out of Range – Channel 0 –
Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt
for Channel 0.
If the user enables this interrupt, then the XRT94L33 will generate
an interrupt anytime the frequency of the DS3, E3 or STS-1 signal
(in the selected direction – Ingress or Egress) within Channel 0,
differs from its corresponding Reference Clock signal (e.g.,
REFCLK45, REFCLK34 or REFCLK51) by its “Out of Range
Detection Threshold” (in terms of ppm) or more.
0 – Disables the “DS3/E3/STS-1 Frequency – Out of Range”
Interrupt for Channel 0.
1 – Enables the “DS3/E3/STS-1 Frequency
Interrupt for Channel 0.
111
- Out of Range”
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 47: Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Status Register – Byte 0
(Address Location=0x015F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Out of Range –
Channel 2
Interrupt Status
Out of Range –
Channel 1
Interrupt Status
Out of Range –
Channel 0
Interrupt Status
R/O
R/O
R/O
R/O
R/O
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-3
Unused
R/O
2
Out of Range –
Channel 2 Interrupt
Status
RUR
DESCRIPTION
DS3/E3/STS-1 Frequency – Out of Range – Channel 2 – Interrupt
Status:
This RESET-Upon-READ bit-field indicates whether or not the XRT94L33
has declares the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for
Channel 2, since the last read of this register.
0 – Indicates that the “DS3/E3/STS-1 Frequency - Out of Range”
Interrupt for Channel 2 has NOT occurred since the last read of this
register.
1 – Indicates that the “DS3/E3/STS-1 Frequency – Out of Range”
Interrupt for Channel 2 has occurred since the last read of this register.
1
Out of Range –
Channel 1 Interrupt
Status
RUR
DS3/E3/STS-1 Frequency – Out of Range – Channel 1 – Interrupt
Status:
This RESET-Upon-READ bit-field indicates whether or not the XRT94L33
has declares the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for
Channel 1, since the last read of this register.
0 – Indicates that the “DS3/E3/STS-1 Frequency - Out of Range”
Interrupt for Channel 1 has NOT occurred since the last read of this
register.
1 – Indicates that the “DS3/E3/STS-1 Frequency – Out of Range”
Interrupt for Channel 1 has occurred since the last read of this register.
0
Out of Range –
Channel 0 Interrupt
Status
RUR
DS3/E3/STS-1 Frequency – Out of Range – Channel 0 – Interrupt
Status:
This RESET-Upon-READ bit-field indicates whether or not the XRT94L33
has declares the “DS3/E3/STS-1 Frequency – Out of Range” Interrupt for
Channel 0, since the last read of this register.
0 – Indicates that the “DS3/E3/STS-1 Frequency - Out of Range”
Interrupt for Channel 0 has NOT occurred since the last read of this
register.
1 – Indicates that the “DS3/E3/STS-1 Frequency – Out of Range”
Interrupt for Channel 0 has occurred since the last read of this register.
112
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 48: APS Mapping Register (Address Location= 0x0180)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Protection Channel
BIT 1
BIT 0
Protected Channel
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-4
Protection Channel
R/W
Protection Channel:
3-0
Protected Channel
R/W
Protected Channel:
Table 49: APS Control Register - 1:1 & 1:N Protection Map (Address Location= 0x0181)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Group
Enable
APS Type
Timing
Receive
Payload
Bypass
Group
Reset
Line Port In
Use
APS Auto
Switch
Enable
APS Auto
Switch
R/W
R/W
R/W
R/W
R/W
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Group Enable
R/W
DESCRIPTION
Group Enable:
This READ/WRITE bit-field permits the user to enable the APS for this
group.
1 – Enables the APS for this group
2 – Disables the APS for this group
6
APS Type
R/W
APS Type:
This READ/WRITE bit-field permits the user to determine the type of APS
for this group.
0 – Configures the type of APS to be 1+1
1 – Configures the type of APS to be 1:N
5
Timing
R/W
Timing:
This READ/WRITE bit-field permits the user to specify whether the
protection or the protected channel should dominate the timing of transmit
APS.
0 – Protected channel dominates the timing
1 – Protection Channel dominates the timing
4
Receive Payload
Bypass
R/W
Receive Payload Bypass:
This READ/WRITE bit-field permits the user to bypass the receive
payload of protection channel.
0 – Receive payload is not bypassed.
1 – Receive payload is bypassed.
113
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
3
Group Reset
R/W
Rev222...000...000
Group Reset:
This READ/WRITE bit-field permits the user to reset the APS control and
FIFO.
A “0” to “1” transition will cause the APS control and FIFO to be reset.
2
Line Port In Use
R/O
Line Port In Use:
This READ-ONLY bit-field permits the user to check the current line port
being in used for receiving OC3 data.
0 – Port 0 (main port) is the current line port in used
1 – Port 1 (backup port) is the current line port in used
1
APS Auto Switch
Enable
R/W
APS Auto Switch Enable:
This READ/WRITE bit-field permits the user to configure the XRT94L33 to
automatically switch from the “Primary” to the “Redundant” port, whenever
the Receive STS-3 TOH Processor block declares an LOS (Loss of
Signal) condition.
0 – Disables the APS Auto Switch feature. In this mode, the XRT94L33
will not automatically switch from the “Primary” port to the “Redundant”
port, whenever the Receive STS-3 TOH Processor block declares an LOS
condition.
1 – Enables the APS Auto Switch feature
0
APS Switch
R/W
APS Switch:
This READ/WRITE bit-field permits the user to command an APS switch
(from one port to the other) via software control.
0 – Configures the Receive STS-3 TOH Processor block to use the
“Primary Receive” Port.
1 – Configures the Receive STS-3 TOH Processor block to use the
“Redundant Receive” Port.
114
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 50: APS Status Register (Address Location= 0x0194)
BIT 7
BIT 6
Unused
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive APS
Parity Enable
Receive APS
Parity Type
Transmit APS
Parity Enable
Transmit APS
Parity Type
Transmit APS
Parity Error
Receive APS
Parity Error
R/O
R/O
R/W
R/W
R/W
R/W
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-6
Unused
R/O
5
Receive APS Parity
Enable
R/W
DESCRIPTION
Receive APS Parity Enable:
This READ/WRITE bit-field permits the user to enable receive APS
parity check.
0 – Disables receive APS parity check
1 – Enables receive APS parity check
4
Receive APS Parity
Type
R/W
Receive APS Parity Type:
This READ/WRITE bit-field permits the user to specify the type of parity
used for receive APS.
0 – Even parity is used
1 – Odd parity is used
3
Transmit APS Parity
Enable
R/W
Transmit APS Parity Enable:
This READ/WRITE bit-field permits the user to enable transmit APS
parity check
0 – Disables transmit APS parity check
1 – Enables transmit APS parity check
2
Transmit APS Parity
Type
R/W
Transmit APS Parity Type:
This READ/WRITE bit-field permits the user to specify the type of parity
used for transmit APS.
0 – Even parity is used
1 – Odd parity is used
1
Transmit APS Parity
Error
R/O
Transmit APS Parity Error:
This READ-ONLY bit-field permits the user to check the parity error
status in transmit APS module
0 – Indicates “NO” parity error occurs
1 – Indicates parity error occurs
0
Receive APS Parity
Error
R/O
Receive APS Parity Error:
This READ-ONLY bit-field permits the user to check the parity error
status in receive APS module
0 – Indicates “NO” parity error occurs
1 – Indicates parity error occurs
Table 51: APS Status Register (Address Location= 0x0196)
115
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Rev222...000...000
BIT 2
BIT 1
BIT 0
Group Overflow Status [7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Group Overflow Status
R/O
DESCRIPTION
Group Overflow Status:
This READ/WRITE bit-field indicates whether or not a FIFO overflow
has occurred in group n 1+1 APS protection channel.
0 – Indicates “NO” FIFO overflow
1 – Indicates a FIFO overflow
Table 52: APS Status Register (Address Location= 0x0197)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Group Underflow Status [7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Group Underflow Status
R/O
DESCRIPTION
Group Underflow Status:
This READ/WRITE bit-field indicates whether or not a FIFO underflow
has occurred in group n 1+1 APS protection channel.
0 – Indicates “NO” FIFO underflow
1 – Indicates a FIFO underflow
116
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 53: APS Interrupt Register (Address Location= 0x0198)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
Transmit APS
Parity Error
Interrupt Status
Receive APS
Parity Error
Interrupt Status
R/O
R/O
R/O
R/O
R/O
R/O
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-2
Unused
R/O
1
Transmit APS Parity Error
Interrupt Status
RUR
DESCRIPTION
Transmit APS Parity Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
transmit APS module has declared a “Transmit APS Parity Error”
Interrupt since the last read of this register.
0 – The “Transmit APS Parity Error” Interrupt has not occurred
since the last read of this register.
1 - The “Transmit APS Parity Error” Interrupt has occurred since
the last read of this register.
7-0
Receive APS Parity Error
Interrupt Status
RUR
Receive APS Parity Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
receive APS module has declared a “Receive APS Parity Error”
Interrupt since the last read of this register.
0 – The “Receive APS Parity Error” Interrupt has not occurred
since the last read of this register.
1 - The “Receive APS Parity Error” Interrupt has occurred since the
last read of this register
117
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 54: APS Interrupt Register (Address Location= 0x019A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Group Overflow Interrupt Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Group Overflow Interrupt
Status
RUR
DESCRIPTION
Group Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not
group n (0-7) APS protection channel has declared a “FIFO
overflow” Interrupt since the last read of this register.
0 – The “FIFO overflow” Interrupt has not occurred since the
last read of this register.
1 - The “FIFO overflow” Interrupt has occurred since the last
read of this register.
Table 55: APS Interrupt Register (Address Location= 0x019B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Group Underflow Interrupt Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Group Underflow
Interrupt Status
RUR
DESCRIPTION
Group Underflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not group n (07) APS protection channel has declared a “FIFO underflow” Interrupt
since the last read of this register.
0 – The “FIFO underflow” Interrupt has not occurred since the last
read of this register.
1 - The “FIFO underflow” Interrupt has occurred since the last read of
this register.
118
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 56: APS Interrupt Enable Register (Address Location= 0x019C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
Transmit APS
Parity Error
Interrupt Enable
Receive APS
Parity Error
Interrupt Enable
R/O
R/O
R/O
R/O
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-2
Unused
R/O
1
Transmit APS Parity
Error Interrupt Enable
R/W
DESCRIPTION
Transmit APS Parity Error Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the
“Transmit APS Parity Error” Interrupt in Transmit APS module
0 – Disables the “Transmit APS Parity Error” Interrupt
1 – Enables the “Transmit APS Parity Error” Interrupt
7-0
Receive APS Parity
Error Interrupt Enable
R/W
Receive APS Parity Error Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the
“Receive APS Parity Error” Interrupt in Receive APS module
0 – Disables the “Receive APS Parity Error” Interrupt
1 – Enables the “Receive APS Parity Error” Interrupt
Table 57: APS Interrupt Enable Register (Address Location= 0x019E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Group Overflow Interrupt Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Group Overflow
Interrupt Enable
R/W
DESCRIPTION
Group Overflow Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the
“FIFO overflow” interrupt in group n APS protection channel.
0 – Disables “FIFO overflow” interrupt .
1 – Enables “FIFO overflow” Interrupt
119
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 58: APS Interrupt Enable Register (Address Location= 0x019F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Group Underflow Interrupt Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Group Underflow
Interrupt Enable
R/W
DESCRIPTION
Group Underflow Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the
“FIFO underflow” interrupt in group n APS protection channel.
0 – Disables “FIFO underflow” interrupt .
1 – Enables “FIFO underflow” Interrupt
120
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1.3
LINE INTERFACE CONTROL BLOCK
1.3.1
LINE INTERFACE CONTROL REGISTER
Table 59: Line Interface Control Register – Address Map
INDIVIDUAL
REGISTER ADDRESS
ADDRESS LOCATION
0x02
0x0302
Receive Line Interface Control Register – Byte 1
0x00
0x03
0x0303
Receive Line Interface Control Register – Byte 0
0x00
0x04 – 0x06
0x0304 – 0x0306
Reserved
0x00
0x07
0x0307
Receive Line Status Register
0x00
0x08 -0x0A
0x0308 -0x030A
Reserved
0x00
0x0B
0x030B
Receive Line Interrupt Register
0x00
0x0C – 0x0E
0x030C – 0x030E
Reserved
0x00
0x0F
0x030F
Receive Line Interrupt Enable Register
0x00
0x10 – 0x82
0x0310 – 0x0382
Reserved
0x00
0x83
0x0383
Transmit Line Interface Control Register
0x00
REGISTER NAME
121
DEFAULT VALUES
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.3.2
Rev222...000...000
LINE INTERFACE CONTROL REGISTER DESCRIPTION
Table 60: Receive Line Interface Control Register – Byte 1 (Address Location= 0x0302)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Loop-timing
Mode
Split Loop
Back
Unused
Remote
Serial Loop
Back
Unused
Analog
Local Loop
Back Enable
Digital Local
Loop Back
Enable
R/W
R/W
R/W
R/O
R/W
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6
Loop Timing Mode
R/W
DESCRIPTION
Loop-Timing Mode:
This READ/WRITE bit-field permits the user to configure the 94L33 to
operate in the Loop-timing Mode. If the user implements this configuration,
then the Transmit Line Interface Block will use the Recovered Clock as its
timing source.
0 – Configures the Transmit Line Interface Block to use “Local-Timing”
Mode (e.g., the timing source is from the Clock Synthesizer block).
1 – Configures the Transmit Line Interface Block to operate in the “LoopTiming” Mode.
5
Split Loop Back
R/W
Split Loop-back Enable:
This READ/WRITE bit-field permits the user to configure the 94L33 to
operate in the “Split Loop-back” Mode. If the user implements this
configuration, then two types of loop-backs will exist within the chip
simultaneously.
a.
A Local Loop-back
This loop-back path will originate from the Transmit STS-3 TOH
Processor block. It will be routed through a portion of the “Transceiver
circuitry” (through the “Transmit Parallel-to-Serial Converter” block)
and then back to the “Receive Serial-to-Parallel Converter” block,
before being routed to the Receive STS-3 TOH Processor block.
b.
A Remote Loop-back
This loop-back path will originate from the Receive STS-3/STM-1
PECL Interface input. It will be routed through the CDR (Clock & Data
Recovery) block; before being routed to the Transmit STS-3/STM-1
PECL Interface output.
0 – Configures the 94L33 to disable split loop back
1 – Configures the 94L33 to enable split loop back
4
Unused
3
Remote Serial
Loop Back
R/W
Remote Serial Loop-back Enable:
This READ/WRITE bit-field permits the user to configure the 94L33 to
operate in the “Remote Serial Loop-back” Mode. In this mode, the
incoming (Received Data) will enter the device via the Receive STS3/STM-1 PECL Interface Input. This signal will then be processed via the
CDR (Clock and Data Recovery) Block. At this point, this input signal will
proceed via two paths in parallel. In one path, the signal will proceed onto
the “Receive Serial-to-Parallel” Converter and then the Receive STS-3
122
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
TOH Processor block (and so on). The other path will not proceed through
the “Receive Serial-to Parallel” Converter block. Instead this signal will
proceed on towards the “Transmit STS-3/STM-1 PECL Interface Output,
thereby completing the loop-back path.
0 – Configures the 94L33 to NOT operate in the Remote Serial Loop-back
Mode.
1 – Configures the 94L33 to operate in the Remote Serial Loop-back
Mode.
2
Unused
R/O
1
Analog Local Loop
Back Enable
R/W
Analog Local Loop Back:
This READ/WRITE bit field permits the user to configure the 94L33 to
operate in the “Analog Local Loop Back” Mode. If the user implements this
configuration, analog local loop back including data and clock recovery will
be enabled.
0 – Analog local loop back is disabled
1 – Analog local loop back is enabled
0
Digital Local Loop
Back Enable
R/W
Digital Local Loop Back:
This READ/WRITE bit field permits the user to configure the 94L33 to
operate in the “Digital Local Loop Back” Mode. If the user implements this
configuration, digital local loop back NOT including data and clock
recovery will be enabled.
0 – Digital local loop back is disabled
1 – Digital local loop back is enabled
123
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 61: Receive Line Interface Control Register – Byte 0 Address Location= 0x0303)
BIT 7
BIT 6
BIT 5
Receive Line
Interface
Module Power
Down
Redundant
Receive Line
Interface
Module Power
Down
Force Training
Mode Upon
LOS
R/W
R/W
R/W
R/O
R/O
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Receive Line
Interface Module
Power Down
R/W
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R/O
R/O
R/W
0
0
0
Unused
DESCRIPTION
Receive Line Interface Module Power Down:
This READ/WRITE bit field permits the user to power down receive line
interface module
0 – Turn on receive line interface module
1 – Power down receive line interface module
6
Redundant
Receive Line
Interface Module
Power Down
R/W
Redudant Receive Line Interface Module Power Down:
This READ/WRITE bit field permits the user to power down redundant
receive line interface module
0 – Turn on redundant receive line interface module
1 – Power down redundant receive line interface module
5
Force Training
Mode Upon LOS
R/W
Force Training Mode Upon LOS:
This READ/WRITE bit field permits the receive line interface phase lock
loop to stay in training mode as long as the external LOS is asserted.
0 – Receive Line Interface PLL will NOT stay in training mode
1 – Receive Line Interface PLL will stay in training mode
4-0
Unused
R/O
124
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 62: Receive Line Interface Status Register (Address Location= 0x0307)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
BIT 1
BIT 0
Clock Lock
Status
Loss of Signal
Status
Redundant
Receiver Clock
Lock Status
Redundant
Receiver Loss
of Signal Status
R/W
R/O
R/O
R/O
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-4
Unused
R/O
3
Clock Lock
Status
RUR
DESCRIPTION
Clock Lock Status:
This RESET-upon-READ bit field indicates whether or not the clock lock
status is detected by transceiver
0 – Indicates clock lock is NOT detected by transceiver
1 – Indicates clock lock is detected by transceiver
2
Loss of Signal
Status
RUR
Loss of Signal Status:
This RESET-upon-READ bit field indicates whether or not the loss of
signal status is detected by transceiver
0 – Indicates loss of signal is NOT detected by transceiver
1 – Indicates loss of signal is detected by transceiver
1
Redundant
Receiver Clock
Lock Status
RUR
Redundant Receiver Clock Lock Status:
This RESET-upon-READ bit field indicates whether or not the clock lock
status is detected by redundant receiver
0 – Indicates clock lock is NOT detected by redundant receiver
1 – Indicates clock lock is detected by redundant receiver
0
Redundant
Receiver Loss of
Signal Status
RUR
Redundant Receiver Loss of Signal Status:
This RESET-upon-READ bit field indicates whether or not the loss of
signal status is detected by redundant receiver
0 – Indicates loss of signal is NOT detected by redundant receiver
1 – Indicates loss of signal is detected by redundant receiver
125
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 63: Receive Line Interface Interrupt Register (Address Location= 0x030B)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
BIT 1
BIT 0
Clock Lock
Interrupt
Loss of Signal
Interrupt
Redundant
Receiver
Clock Lock
Interrupt
Redundant
Receiver Loss
of Signal
Interrupt
R/W
R/O
R/O
R/O
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-4
Unused
R/O
3
Clock Lock
Interrupt
RUR
DESCRIPTION
Clock Lock Interrupt:
This RESET-upon-READ bit field indicates whether or not a clock lock
interrupt has occurred. A clock lock interrupt occurs when the signal
“Clock Lock Status” (address location: 0x0307) makes a “0” to “1” or “1” to
“0” transition.
0 – Indicates clock lock interrupt is NOT declared.
1 – Indicates clock lock is declared
2
Loss of Signal
Interrupt
RUR
Loss of Signal Interrupt:
This RESET-upon-READ bit field indicates whether or not a loss of signal
interrupt has occurred. A clock lock interrupt occurs when the signal “Loss
of Signal Status” (Address Location: 0x0307) makes a “0” to “1” or “1” to
“0” transition.
0 – Indicates a loss of signal interrupt is NOT declared.
1 – Indicates a loss of signal is declared
1
Redundant
Receiver Clock
Lock Interrupt
RUR
Redundant Receiver Clock Lock Interrupt:
This RESET-upon-READ bit field indicates whether or not a clock lock
interrupt has occurred in the redundant receiver block. A clock lock
interrupt occurs when the signal “Clock Lock Status” (address location:
0x0307) makes a “0” to “1” or “1” to “0” transition.
0 – Indicates clock lock interrupt is NOT declared.
1 – Indicates clock lock is declared
0
Redundant
Receiver Loss of
Signal Interrupt
RUR
Redundant Receiver Loss of Signal Interrupt:
This RESET-upon-READ bit field indicates whether or not a loss of signal
interrupt has occurred in the redundant receiver block. A clock lock
interrupt occurs when the signal “Loss of Signal Status” (Address Location:
0x0307) makes a “0” to “1” or “1” to “0” transition.
0 – Indicates a loss of signal interrupt is NOT declared.
1 – Indicates a loss of signal is declared
126
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 64: Receive Line Interface Interrupt Register (Address Location= 0x030F)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
BIT 1
BIT 0
Clock Lock
Interrupt
Enable
Loss of Signal
Interrupt
Enable
Redundant
Receiver
Clock Lock
Interrupt
Enable
Redundant
Receiver
Loss of Signal
Interrupt
Enable
R/W
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
7-4
NAME
Unused
3
Clock Lock
Interrupt Enable
TYPE
DESCRIPTION
R/O
R/W
Clock Lock Interrupt Enable:
This READ/WRITE bit field disables or enables the clock lock interrupt.
0 – Disables clock lock interrupt
1 – Enables clock lock interrupt
2
Loss of Signal
Interrupt
R/W
Loss of Signal Interrupt Enable:
This READ/WRITE bit field disables or enables the loss of signal interrupt.
0 – Disables loss of signal interrupt
1 – Enables loss of signal interrupt
1
Redundant
Receiver Clock
Lock Interrupt
Enable
R/W
Redundant Receiver Clock Lock Interrupt Enable:
This READ/WRITE bit field disables or enables the clock lock interrupt for
the redundant receiver block.
0 – Disables clock lock interrupt
1 – Enables clock lock interrupt
0
Redundant
Receiver Loss of
Signal Interrupt
R/W
Redundant Receiver Loss of Signal Interrupt Enable:
This READ/WRITE bit field disables or enables the loss of signal interrupt
for the redundant receiver block.
0 – Disables loss of signal interrupt
1 – Enables loss of signal interrupt
127
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 65: Transmit Line Interface Control Register (Address Location= 0x0383)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Transmit
Line
Interface
Module
Power Down
Transmit
Clock
Enable
Clock
Synthesizer
Redundant
Enable
Unused
Unused
R/W
R/W
R/W
R/W
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Transmit Line
Interface Module
Power Down
R/W
BIT 1
BIT 0
Reference Clock Divide
DESCRIPTION
Transmit Line Interface Module Power Down:
This READ/WRITE bit field permits the user to enable or disable both
transmitter data and clock outputs in the transmit line interface module.
0 – Disables both transmitter data and clock outputs in transmit line
interface
1 – Enables both transmitter data and clock outputs in transmit line
interface
6
Transmit Clock
Enable
R/W
Transmit Clock Enable:
This READ/WRITE bit field permits the user to enable or disable the
transmitter clock output.
0 – Disables transmitter clock output
1 – Enables transmitter clock output
5
Clock
Synthesizer
R/W
Clock Synthesizer:
This READ/WRITE bit field permits the user to determine the source of
transmit SONET clock.
0 – Uses reference clock as SONET transmit clock
1 – Uses 19MHz generated by clock synthesizer as SONET transmit clock
4
Redundant
Enable
R/W
Redundant Enable:
This READ/WRITE bit field permits the user to enable or disable the
redundant transmit output pads
0 – Disables redundant transmit output
1 – Enables redundant transmit output
3
Unused
R/W
Serial Loopback:
This READ/WRITE bit field permits the user to enable or disable serial
loopback.
0 – Disables Serial loopback
1 – Enables Serial loopback
2
Unused
R/O
1-0
Reference Clock
Divide
R/W
Reference Clock Divide:
This READ/WRITE bit field permits the user to select the desired reference
clock speed as follows:
00 = 19.44 MHz
128
XRT94L33
Rev222...000...000
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
01 = 38.88 MHz
10 = 51.85 MHz
11 = 77.76 MHz
129
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.4
Rev222...000...000
RECEIVE/TRANSMIT UTOPIA INTERFACE BLOCK
The register map for the Receive/Transmit Utopia Interface Block is presented in the Table below.
Additionally, a detailed description of each of the “Receive/Transmit UTOPIA Interface” Block registers is
presented below.
In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the
XRT94L33, with the “Receive and Transmit UTOPIA Interface Blocks “highlighted” is presented below in
Figure 6
Figure 5: Illustration of the Functional Block Diagram of the XRT94L33, with the Receive/Transmit
UTOPIA Interface Blocks “High-lighted”.
From Channels 1 & 2
Tx
Tx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Rx
Rx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Clock
Clock
Synthesizer
Synthesizer
Block
Block
Tx
TxCell
Cell
Processor
Processor
Block
Block
Tx
TxPLCP
PLCP
Processor
Processor
Block
Block
Tx
TxPPP
PPP
Processor
Processor
Block
Block
Tx
TxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Tx
TxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Tx
TxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxPPP
PPP
Processor
Processor
Block
Block
Rx
RxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
RxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Rx
RxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxCell
Cell
Processor
Processor
Block
Block
Rx
RxPLCP
PLCP
Processor
Processor
Block
Block
Channel 0
To Channel 1 & 2
130
Tx
TxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
Tx
TxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Tx
TxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Rx
RxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Clock
Clock&&
Data
Data
Recovery
Recovery
Block
Block
Rx
RxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Rx
RxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1.4.1
RECEIVE/TRANSMIT UTOPIA INTERFACE BLOCK REGISTER
Table 66: Receive/Transmit UTOPIA Interface Block Register – Address Map
RECEIVE/TRANSMIT UTOPIA INTERFACE REGISTERS
0x0384 – 0x0502
0x0503
0x0504 – 0x0512
0x0513
0x0514 – 0x0516
0x0517
0x0518 – 0x0582
0x0583
0x0584 – 0x0592
0x0593
0x0594 – 0x0596
0x0597
0x0598 – 0x1102
Reserved
0x00
Receive UTOPIA Control Register – Byte 0
0x8F
Reserved
0x00
Receive UTOPIA Port Address
0x00
Reserved
0x00
Receive UTOPIA Port Number
0x00
Reserved
0x00
Transmit UTOPIA Control Register – Byte 0
0x8F
Reserved
0x00
Transmit UTOPIA Port Address
0x00
Reserved
0x00
Transmit UTOPIA Port Number
0x00
Reserved
0x00
131
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.4.2
Rev222...000...000
RECEIVE UTOPIA INTERFACE BLOCK REGISTER DESCRIPTION
Table 67: Receive UTOPIA/POS-PHY Control Register – Byte 0 (Address = 0x0503)
BIT 7
BIT 6
BIT 5
BIT 4
UTOPIA
Level Select
Multi-PHY
Polling
Enable
Back to
Back Polling
Enable
Direct
Status
Indication
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
1
1
1
BIT NUMBER
NAME
TYPE
7
UTOPIA Level Select
R/W
BIT 3
BIT 2
BIT 1
UTOPIA/POS-PHY Data
Bus Width
BIT 0
Cell Size[1:0]
DESCRIPTION
UTOPIA Level Select:
This READ/WRITE bit-field permits the user to select either
UTOPIA level 3, UTOPIA level 2, or UTOPIA level 1 standard
to be used. If the user selects UTOPIA level 3 to be used, the
UTOPIA interface will support cell-level handshakes compliant
to the UTOPIA level 3 standard. If the user selects UTOPIA
level 2 or 1, then the UTOPIA interface will support cell-level
handshakes compliant to both UTOPIA level 2 and 1
standards.
0 – Configures the Receive UTOPIA interface block to use
UTOPIA Level 1 or 2 standards
1 – Configures the Receive UTOPIA interface block to use
UTOPIA Level 3 standard.
6
Multi-PHY Polling Enable
R/W
Multi-PHY Polling Enable:
This READ/WRITE bit-field permits the user to either enable or
disable Multi-PHY Polling for the Receive UTOPIA Interface
block. If the user implements this feature (and configures the
XRT94L33 to operate in the Multi-PHY Mode) then the
RxUClav output pin will be driven (either “high” or “low”) based
upon the fill-status of the Receive FIFO within the Channel that
corresponds to the “Receive UTOPIA Address” that is
currently being applied to the “RxUAddr[4:0]” input pins.
If the user does not implement this feature (and then
configures the XRT94L33 to operate in the Single-PHY Mode),
then the “RxUClav” output pin will unconditionally reflect the
“Receive FIFO fill-status” for Channel 0. No attention will be
paid to the address values placed upon the “RxUAddr[4:0]”
input pins.
0 – Configures the Receive UTOPIA Interface block to operate
in the Single-PHY Mode.
1 – Configures the Receive UTOPIA Interface block to operate
in the Multi-PHY Mode.
5
Back-to-Back Polling Enable
R/W
Back-to-Back Polling Enable:
This READ/WRITE bit-field permits the user to configure the
Receive UTOPIA Interface block to support “Back-to-Back
Polling”.
Ordinarily, for Multi-PHY polling, the user is required to
interleave all UTOPIA Address values (that are to be placed
132
XRT94L33
Rev222...000...000
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
on the “RxUAddr[4:0]” input pins) with the NULL Address (e.g.,
0x1F). However, if the user configures the Receive UTOPIA
Interface block to operate in the “UTOPIA Level 3” Mode, and
if the user also enables “Back-to-Back Polling”, then he/she
does not need to interleave the UTOPIA Addresses with the
NULL Address. In this case, the user can simply apply a
“back-to-back” stream of “relevant” UTOPIA Addresses to the
“RxUAddr[4:0]” input pins, and the XRT94L33 will respond by
driving the RxUClav output pins to the appropriate states
(depending upon the Receive FIFO fill-status).
0 – Disables “Back-to-Back” Polling. In this mode, the user
must interleave all UTOPIA Addresses (that are to be applied
to the “RxUAddr[4:0]” input pins) with the NULL Address.
1 – Enables “Back-to-Back” Polling. In this mode, the user
does not need to interleave all UTOPIA Addresses (that are to
be applied to the “RxUAddr[4:0]” input pins) with the NULL
Address.
Note:
In order to configure the Receive UTOPIA Interface
block to operate in the “Back-to-Back Polling” Mode,
the user must also do the following.
1.Configure the Receive UTOPIA Interface to operate in the
“UTOPIA Level 3” Mode. This is accomplished by setting Bit 7
(UTOPIA Level 3 Disable) within this Register to “0”.
2.Configure the Receive UTOPIA Interface to support “MultiPHY” Polling. This is accomplished by setting Bit 6 (Multi-PHY
Polling Enable) within this register to “1”.
4
Direct Status Indication
Enable
R/W
3-2
UTOPIA/POS-PHY Data
Bus Width[1:0]
R/W
1–0
Cell Size[1:0]
UTOPIA/POS-PHY Data Bus Width[1:0]:
These READ/WRITE bit-fields permit the user to select the
width of the Receive UTOPIA and POS-PHY Data Buses. The
relationship between the contents of these bit-fields and the
corresponding widths of the Receive UTOPIA and POS-PHY
Data Bus is tabulated below.
UTOPIA/POS-PHY
Data Bus Width[1:0]
Corresponding UTOPIA/POSPHY Data Bus Width
00
Not Valid
01
8 bits
10
16 bits
11
Not Valid
Cell Size[1:0]:
These two READ/WRITE bit-fields permit the user to specify
the size of the ATM cell that will be handled by the Receive
UTOPIA Interface blocks. The relationship between the
contents of these bit-fields and the corresponding Cell Sizes
are tabulated below.
Cell Size[1:0]
133
Resulting Cell Size (Bytes)
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
01
53 bytes (Only valid for
UTOPIA Level 1, and if the
UTOPIA Data Bus Width is
set to 8 bits)
10
54 bytes (Only valid for
UTOPIA Levels 1 and 2)
11
56 bytes
Note:
134
Rev222...000...000
The user must bear in mind the UTOPIA Level and
the UTOPIA Data Bus width selected, when
selecting the Cell Size.
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 68: Receive UTOPIA Port Address Register (Address = 0x0513)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Receive UTOPIA Port Address [4:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-5
Unused
R/O
4-0
Receive UTOPIA Port
Address [4:0]
R/W
DESCRIPTION
Receive UTOPIA Port Address[4:0]:
These READ/WRITE register bits, along with the “Receive UTOPIA
Port Number [4:0]” bits (within the “Receive UTOPIA Port Number”
Register (Address = 0x0517) permit the user to assign a unique
Receive UTOPIA address to each of the three STS-1 channels within
the XRT94L33.
For UTOPIA Level 2/3 applications, the user can write in any value,
ranging from 0x00 through 0x1E into this register.
The Receive UTOPIA Address Assignment Procedure:
In order to assign a UTOPIA Address to a given Channel (or Port)
within the XRT94L33, the user must do the following.
a.
Write the value corresponding to a given XRT94L33
Channel into the “Receive UTOPIA Port Number” Register
(Address = 0x0517).
b.
Write the corresponding UTOPIA Address value into this
register.
Once this “two-step” procedure has been executed, then the
XRT94L33 Channel (as specified during step “a”) will be assigned the
“Receive UTOPIA Address” value (as specified during step “b”).
135
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 69: Receive UTOPIA Port Number Register (Address = 0x0517)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Receive UTOPIA Port Number[4:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–5
Unused
R/O
4-0
Receive UTOPIA Port
Number[4:0]
R/W
DESCRIPTION
Receive UTOPIA Port Number[4:0]:
These READ/WRITE register bits, along with the “Receive UTOPIA
Port Address[4:0]” bits (within the “Receive UTOPIA Port Address”
Register (Address = 0x0513) permit the user to assign a unique
Receive UTOPIA address to each of the three STS-1 channels within
the XRT94L33.
In the XRT94L33, the following are the only valid values that can be
written into these register bits, during the “Receive UTOPIA Address
Assignment” process.
0x00 – XRT94L33 Channel 0
0x01 – XRT94L33 Channel 1
0x02 – XRT94L33 Channel 2
The Receive UTOPIA Address Assignment Procedure:
In order to assign a UTOPIA Address to a given Channel (or Port)
within the XRT94L33, the user must do the following.
a.
Write the value corresponding to a given XRT94L33
Channel into this register.
b.
Write the corresponding UTOPIA Address value into the
“Receive UTOPIA Port Address” Register (Address =
0x0513).
Once this “two-step” procedure has been executed, then the
XRT94L33 Channel (as specified during step “a”) will be assigned the
“Receive UTOPIA Address” value (as specified during step “b”).
136
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1.4.3
TRANSMIT UTOPIA INTERFACE BLOCK REGISTER DESCIPTION
Table 70: Transmit UTOPIA/POS-PHY Control Register – Byte 0 (Address = 0x0583)
BIT 7
BIT 6
BIT 5
BIT 4
UTOPIA
Level 3
Disable
Multi-PHY
Polling
Enable
Back to
Back Polling
Enable
Direct
Status
Indication
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
1
1
1
BIT NUMBER
NAME
TYPE
7
UTOPIA Level 3 Disable
R/W
6
Multi-PHY Polling Enable
R/W
BIT 3
BIT 2
BIT 1
UTOPIA/POS-PHY Data
Bus Width
BIT 0
Cell Size[1:0]
DESCRIPTION
Multi-PHY Polling Enable:
This READ/WRITE bit-field permits the user to either enable or
disable Multi-PHY Polling for the Transmit UTOPIA Interface
block. If the user implements this feature (and configures the
XRT94L33 to operate in the Multi-PHY Mode) then the TxUClav
output pin will be driven (either “high” or “low”) based upon the
fill-status of the Transmit FIFO within the Channel that
corresponds to the “Transmit UTOPIA Address” that is currently
being applied to the “TxUAddr[4:0]” input pins.
If the user does not implement this feature (and then configures
the XRT94L33 to operate in the Single-PHY Mode), then the
“TxUClav” output pin will unconditionally reflect the “Transmit
FIFO fill-status” for Channel 0. No attention will be paid to the
address values placed upon the “TxUAddr[4:0]” input pins.
0 – Configures the Transmit UTOPIA Interface block to operate
in the Single-PHY Mode.
1 – Configures the Transmit UTOPIA Interface block to operate
in the Multi-PHY Mode.
5
Back-to-Back Polling
Enable
R/W
Back-to-Back Polling Enable:
This READ/WRITE bit-field permits the user to configure the
Transmit UTOPIA Interface block to support “Back-to-Back
Polling”.
Ordinarily, for Multi-PHY polling, the user is required to interleave
all UTOPIA Address values (that are to be placed on the
“TxUAddr[4:0]” input pins) with the NULL Address (e.g., 0x1F).
However, if the user configures the Transmit UTOPIA Interface
block to operate in the “UTOPIA Level 3” Mode, and if the user
also enables “Back-to-Back Polling”, then he/she does not need
interleave the UTOPIA Addresses with the NULL Address. In
this case, the user can simply apply a “back-to-back” stream of
“relevant” UTOPIA Addresses to the “TxUAddr[4:0]” input pins,
and the XRT94L33 will respond by driving the TxUClav output
pins to the appropriate states (depending upon the Transmit
FIFO fill-status).
0 – Disables “Back-to-Back” Polling. In this mode, the user must
interleave all UTOPIA Addresses (that are to be applied to the
“TxUAddr[4:0]” input pins) with the NULL Address.
1 – Enables “Back-to-Back” Polling. In this mode, the user does
137
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
not need to interleave all UTOPIA Addresses (that are to be
applied to the “TxUAddr[4:0]” input pins) with the NULL Address.
Note:
In order to configure the Transmit UTOPIA Interface
block to operate in the “Back-to-Back Polling” Mode,
the user must also do the following.
1. Configure the Transmit UTOPIA Interface to operate in the
“UTOPIA Level 3” Mode. This is accomplished by setting Bit 7
(UTOPIA Level 3 Disable) within this Register to “0”.
2. Configure the Transmit UTOPIA Interface to support “MultiPHY” Polling. This is accomplished by setting Bit 6 (Multi-PHY
Polling Enable) within this register to “1”.
4
Direct Status Indication
Enable
R/W
3-2
UTOPIA/POS-PHY Data
Bus Width[1:0]
R/W
1–0
Cell Size[1:0]
UTOPIA/POS-PHY Data Bus Width[1:0]:
These READ/WRITE bit-fields permit the user to select the width
of the Transmit UTOPIA and POS-PHY Data Buses. The
relationship between the contents of these bit-fields and the
corresponding widths of the Transmit UTOPIA and POS-PHY
Data Bus is tabulated below.
UTOPIA/POS-PHY
Data Bus Width[1:0]
Corresponding UTOPIA/POSPHY Data Bus Width
00
Not Valid
01
8 bits
10
16 bits
11
Not Valid
Cell Size[1:0]:
These two READ/WRITE bit-fields permit the user to specify the
size of the ATM cell that will be handled by the Transmit UTOPIA
Interface blocks. The relationship between the contents of these
bit-fields and the corresponding Cell Sizes are tabulated below.
Cell Size[1:0]
Resulting Cell Size (Bytes)
00
52 bytes
01
53 bytes (Only valid for
UTOPIA Level 1, and if the
UTOPIA Data Bus Width is
set to 8 bits)
10
54 bytes (Only valid for
UTOPIA Levels 1 and 2)
11
56 bytes
Note:
138
The user must bear in mind the UTOPIA Level and the
UTOPIA Data Bus width selected, when selecting the
Cell Size.
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 71: Transmit UTOPIA Port Address Register (Address = 0x0593)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Transmit UTOPIA Port Address[4:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-5
Unused
R/O
4-0
Transmit UTOPIA
Port Address[4:0]
R/W
DESCRIPTION
Transmit UTOPIA Port Address[4:0]:
These READ/WRITE register bits, along with the “Transmit UTOPIA
Port Number[4:0]” bits (within the “Trasnmit UTOPIA Port Number”
Register (Address = 0x0597) permit the user to assign a unique
Transmit UTOPIA address to each of the three STS-1 channels
within the XRT94L33.
For UTOPIA Level 2/3 applications, the user can write in any value,
ranging from 0x00 through 0x1E into this register.
The Transmit UTOPIA Address Assignment Procedure:
In order to assign a UTOPIA Address to a given Channel (or Port)
within the XRT94L33, the user must do the following.
a.
Write the value corresponding to a given XRT94L33
Channel into the “Transmit UTOPIA Port Number” Register
(Address = 0x0597).
b.
Write the corresponding UTOPIA Address value into this
register.
Once this “two-step” procedure has been executed, then the
XRT94L33 Channel (as specified during step “a”) will be assigned the
“Transmit UTOPIA Address” value (as specified during step “b”).
139
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 72: Transmit UTOPIA Port Number Register (Address = 0x0597)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
Transmit UTOPIA Port Number[4:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–5
Unused
R/O
4-0
Transmit UTOPIA
Port Number[4:0]
R/W
DESCRIPTION
Transmit UTOPIA Port Number[4:0]:
These READ/WRITE register bits, along with the “Transmit UTOPIA
Port Address[4:0]” bits (within the “Transmit UTOPIA Port Address”
Register (Address = 0x0593) permit the user to assign a unique
Transmit UTOPIA address to each of the three STS-1 channels
within the XRT94L33.
In the XRT94L33, the following are the only valid values that can be
written into these register bits, during the “Transmit UTOPIA Address
Assignment” process.
0x00 – XRT94L33 Channel 0
0x01 – XRT94L33 Channel 1
0x02 – XRT94L33 Channel 2
The Transmit UTOPIA Address Assignment Procedure:
In order to assign a UTOPIA Address to a given Channel (or Port)
within the XRT94L33, the user must do the following.
a.
Write the value corresponding to a given XRT94L33
Channel into this register.
b.
Write the corresponding UTOPIA Address value into the
“Transmit UTOPIA Port Address” Register (Address =
0x0593).
Once this “two-step” procedure has been executed, then the
XRT94L33 Channel (as specified during step “a”) will be assigned the
“Transmit UTOPIA Address” value (as specified during step “b”).
140
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1.5
RECEIVE STS-3 TOH PROCESSOR BLOCK
The register map for the Receive STS-3 TOH Processor Block is presented in the Table below. Additionally,
a detailed description of each of the “Receive STS-3 TOH Processor” Block registers is presented below.
In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the
XRT94L33, with the “Receive STS-3 TOH Processor Block “highlighted” is presented below in Figure 6
Figure 6: Illustration of the Functional Block Diagram of the XRT94L33, with the Receive STS-3 TOH
Processor Block “High-lighted”.
From Channels 1 & 2
Tx
Tx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Rx
Rx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Clock
Clock
Synthesizer
Synthesizer
Block
Block
Tx
TxCell
Cell
Processor
Processor
Block
Block
Tx
TxPLCP
PLCP
Processor
Processor
Block
Block
Tx
TxPPP
PPP
Processor
Processor
Block
Block
Tx
TxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Tx
TxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Tx
TxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxPPP
PPP
Processor
Processor
Block
Block
Rx
RxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
RxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Rx
RxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxCell
Cell
Processor
Processor
Block
Block
Rx
RxPLCP
PLCP
Processor
Processor
Block
Block
Channel 0
To Channel 1 & 2
141
Tx
TxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
Tx
TxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Tx
TxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Rx
RxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Clock
Clock&&
Data
Data
Recovery
Recovery
Block
Block
Rx
RxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Rx
RxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.5.1
Rev222...000...000
RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER
Table 73: Receive STS-3 TOH Processor Block Control Register – Address Map
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x00 – 0x02
0x1000 – 0x1102
0x03
0x1103
0x04 – 0x05
0x1104 – 0x1105
0x06
REGISTER NAME
DEFAULT VALUES
Reserved
Receive STS-3 Transport Control Register – Byte 0
0x00
Reserved
0x00
0x1106
Receive STS-3 Transport Status Register – Byte 1
0x00
0x07
0x1107
Receive STS-3 Transport Status Register – Byte 0
0x02
0x08
0x1108
Reserved
0x00
0x09
0x1109
Receive STS-3 Transport Interrupt Status Register – Byte 2
0x00
0x0A
0x110A
Receive STS-3 Transport Interrupt Status Register – Byte 1
0x00
0x0B
0x110B
Receive STS-3 Transport Interrupt Status Register – Byte 0
0x00
0x0C
0x110C
Reserved
0x00
0x0D
0x110D
Receive STS-3 Transport Interrupt Enable Register – Byte 2
0x00
0x0E
0x110E
Receive STS-3 Transport Interrupt Enable Register – Byte 1
0x00
0x0F
0x110F
Receive STS-3 Transport Interrupt Enable Register – Byte 0
0x00
0x10
0x1110
Receive STS-3 Transport B1 Error Count – Byte 3
0x00
0x11
0x1111
Receive STS-3 Transport B1 Error Count – Byte 2
0x00
0x12
0x1112
Receive STS-3 Transport B1 Error Count – Byte 1
0x00
0x13
0x1113
Receive STS-3 Transport B1 Error Count – Byte 0
0x00
0x14
0x1114
Receive STS-3 Transport B2 Error Count – Byte 3
0x00
0x15
0x1115
Receive STS-3 Transport B2 Error Count – Byte 2
0x00
0x16
0x1116
Receive STS-3 Transport B2 Error Count – Byte 1
0x00
0x17
0x1117
Receive STS-3 Transport B2 Error Count – Byte 0
0x00
0x18
0x1118
Receive STS-3 Transport REI-L Error Count – Byte 3
0x00
0x19
0x1119
Receive STS-3 Transport REI-L Error Count – Byte 2
0x00
0x1A
0x111A
Receive STS-3 Transport REI-L Error Count – Byte 1
0x00
0x1B
0x111B
Receive STS-3 Transport REI-L Error Count – Byte 0
0x00
0x1C
0x111C
Reserved
0x00
0x1D – 0x1E
0x111D - 0x111E
Reserved
0x00
0x1F
0x111F
Receive STS-3 Transport K1 Byte Value
0x00
142
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x20 – 0x22
0x1120 – 0x1122
0x23
0x1123
0x24 – 0x26
0x1124 – 0x1126
0x27
0x1127
0x28 – 0x2A
0x1128 – 0x112A
0x2B
0x112B
0x2C, 0x2D
0x112C, 0x112D
0x2E
REGISTER NAME
DEFAULT VALUES
Reserved
0x00
Receive STS-3 Transport K2 Byte Value
0x00
Reserved
0x00
Receive STS-3 Transport S1 Byte Value
0x00
Reserved
0x00
Receive STS-3 Transport – In-Sync Threshold Value
0x00
Reserved
0x00
0x112E
Receive STS-3 Transport – LOS Threshold Value – MSB
0xFF
0x2F
0x112F
Receive STS-3 Transport – LOS Threshold Value – LSB
0xFF
0x30
0x1130
Reserved
0x00
0x31
0x1131
Receive STS-3 Transport – SF Set Monitor Interval – Byte 2
0x00
0x32
0x1132
Receive STS-3 Transport – SF Set Monitor Interval – Byte 1
0x00
0x33
0x1133
Receive STS-3 Transport – SF Set Monitor Interval – Byte 0
0x00
0x34, 0x35
0x1134 – 0x1135
Reserved
0x00
0x36
0x1136
Receive STS-3 Transport – SF Set Threshold – Byte 1
0x00
0x37
0x1137
Receive STS-3 Transport – SF Set Threshold – Byte 0
0x00
0x38, 0x39
0x1138, 0x1139
Reserved
0x00
0x3A
0x113A
Receive STS-3 Transport – SF Clear Threshold – Byte 1
0x00
0x3B
0x113B
Receive STS-3 Transport – SF Clear Threshold – Byte 0
0x00
0x3C
0x113C
Reserved
0x00
0x3D
0x113D
Receive STS-3 Transport – SD Set Monitor Interval – Byte 2
0x00
0x3E
0x113E
Receive STS-3 Transport – SD Set Monitor Interval – Byte 1
0x00
0x3F
0x113F
Receive STS-3 Transport – SD Set Monitor Interval – Byte 0
0x00
0x40, 0x41
0x1140, 0x1141
Reserved
0x00
0x42
0x1142
Receive STS-3 Transport – SD Set Threshold – Byte 1
0x00
0x43
0x1143
Receive STS-3 Transport – SD Set Threshold – Byte 0
0x00
0x44, 0x45
0x1144, 0x1145
Reserved
0x00
0x46
0x1146
Receive STS-3 Transport – SD Clear Threshold – Byte 1
0x00
0x47
0x1147
Receive STS-3 Transport – SD Clear Threshold – Byte 0
0x00
0x48 – 0x4A
0x1148 – 0x114A
Reserved
0x00
0x4B
0x114B
Receive STS-3 Transport – Force SEF Condition
0x00
143
XRT94L33
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S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x4C, 0x4E
0x114C, 0x114E
0x4F
0x114F
0x50, 0x51
0x1150, 0x1151
0x52
REGISTER NAME
Rev222...000...000
DEFAULT VALUES
Reserved
0x00
Receive STS-3 Transport – Receive J0 Trace Buffer Control
0x00
Reserved
0x00
0x1152
Receive STS-3 Transport – SD Burst Error Count Tolerance
– Byte 1
0x00
0x53
0x1153
Receive STS-3 Transport – SD Burst Error Count Tolerance
– Byte 0
0x00
0x54, 0x55
0x1154, 0x1155
Reserved
0x00
0x56
0x1156
Receive STS-3 Transport – SF Burst Error Count Tolerance
– Byte 1
0x00
0x57
0x1157
Receive STS-3 Transport – SF Burst Error Count Tolerance
– Byte 0
0x00
0x58
0x1158
Reserved
0x00
0x59
0x1159
Receive STS-3 Transport – Receive SD Clear Monitor
Interval – Byte 2
0xFF
0x5A
0x115A
Receive STS-3 Transport – Receive SD Clear Monitor
Interval – Byte 1
0xFF
0x5B
0x115B
Receive STS-3 Transport – Receive SD Clear Monitor
Interval – Byte 0
0xFF
0x5C
0x115C
Reserved
0x00
0x5D
0x115D
Receive STS-3 Transport – Receive SF Clear Monitor
Interval – Byte 2
0xFF
0x5E
0x115E
Receive STS-3 Transport – Receive SF Clear Monitor
Interval – Byte 1
0xFF
0x5F
0x115F
Receive STS-3 Transport – Receive SF Clear Monitor –
Byte 0
0xFF
0x60 – 0x62
0x1160 – 0x1162
Reserved
0x00
0x63
0x1163
Receive STS-3 Transport – Auto AIS Control Register
0x00
0x64 – 0x66
0x1164 – 0x1166
Reserved
0x00
0x67
0x1167
Receive STS-3 Transport – Serial Port Control Register
0x00
0x68 – 0x6A
0x1168 – 0x116A
Reserved
0x00
0x6B
0x116B
Receive STS-3 Transport – Auto AIS (in Downstream STS1s) Control Register
0x000
0x6C – 0x79
0x116C – 0x1179
0x7A
0x117A
Receive STS-3 Transport – TOH Capture Indirect Address
0x00
0x7B
0x117B
Receive STS-3 Transport – TOH Capture Indirect Address
0x00
0x7C
0x117C
Receive STS-3 Transport – TOH Capture Indirect Data
0x00
Reserved
144
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x7D
0x117D
Receive STS-3 Transport – TOH Capture Indirect Data
0x00
0x7E
0x117E
Receive STS-3 Transport – TOH Capture Indirect Data
0x00
0x7F
0x117F
Receive STS-3 Transport – TOH Capture Indirect Data
0x00
0x80 – 0xFF
0x1180 – 0x11FF
Reserved
0x00
REGISTER NAME
145
DEFAULT VALUES
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.5.2
Rev222...000...000
RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER DESCRIPTION
Table 74: Receive STS-3 Transport Control Register – Byte 0 (Address Location= 0x1103)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
STS-N OH
Extract
SF Detect
Enable
SD Detect
Enable
Descramble
Disable
SDH/
SONET*
REI-L
Error Type
B2 Error
Type
B1 Error
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
STS-N OH
Extract
R/W
DESCRIPTION
STS-N Overhead Extract (Revision C Silicon Only):
This READ/WRITE bit-field permits the user to configure the RxTOH output
port to output the TOH for all lower-tributary STS-1s within the incoming
STS-3 signal.
0 – Disables this feature. In this mode, the RxTOH output port will only
output the TOH for the first STS-1 within the incoming STS-3 signal.
1 – Enables this feature.
6
SF Detect
Enable
R/W
Signal Failure (SF) Detect Enable:
This READ/WRITE bit-field permits the user to enable or disable SF
Detection by the Receive STS-3 TOH Processor Block.
0 – SF Detection is disabled.
1 – SF Detection is enabled:
5
SD Detect
Enable
R/W
Signal Degrade (SD) Detect Enable:
This READ/WRITE bit-field permits the user to enable or disable SD
Detection by the Receive STS-3 TOH Processor Block.
0 – SD Detection is disabled.
1 – SD Detection is enabled.
4
Descramble
Disable
R/W
De-Scramble Disable:
This READ/WRITE bit-field permits the user to either enable or disable descrambling by the Receive STS-3 TOH Processor block.
0 – De-Scrambling is enabled.
1 – De-Scrambling is disabled.
3
SDH/SONET*
R/W
SDH/SONET Select:
This READ/WRITE bit-field permits the user to configure the Receiver to
operate in either the SONET or SDH Mode.
0 – Configures the Receiver to operate in the SONET Mode.
1 – Configures the Receiver to operate in the SDH Mode.
2
REI-L Error
Type
R/W
REI-L (Line – Remote Error Indicator) Error Type:
This READ/WRITE bit-field permits the user to specify how the “Receive
Transport REI-L Error Count” register is incremented.
0 – Configures the Receive STS-3 TOH Processor block to count REI-L Bit
Errors.
In this case the “Receive Transport REI-L Error Count” register will be
146
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
incremented by the value of the lower nibble within the M0/M1 byte.
1 – Configures the Receive STS-3 TOH Processor block to count REI-L
Frame Errors.
In this case the “Receive Transport REI-L Error Count” register will be
incremented each time the STS-3 Receiver receives a “non-zero” M0/M1
byte.
1
B2 Error Type
R/W
B2 Error Type:
This READ/WRITE bit-field permits the user to specify how the “Receive
Transport B2 Error Count” register is incremented.
0 – Configures the Receive STS-3 TOH Processor block to count B2 bit
errors.
In this case, the “Receive Transport B2 Error Count” register will be
incremented by the number of bits, within the B2 value, that is in error.
1 – Configures the Receive STS-3 TOH Processor block to count B2 frame
errors.
In this case, the “Receive Transport B2 Error Count” register will be
incremented by the number of erred STS-3 frames.
0
B1 Error Type
R/W
B1 Error Type:
This READ/WRITE bit-field permits the user to specify how the “Receive
Transport B1 Error Count” register is incremented.
0 – Configures the Receive STS-3 TOH Processor block to count B1 bit
errors.
In this case, the “Receive Transport B1 Error Count” register will be
incremented by the number of bits, within the B1 value, that is in error.
1 – Configures the Receive STS-3 TOH Processor block to count B2 bit
errors.
In this case, the “Receive Transport B1 Error Count” register will be
incremented by the number of erred STS-3 frames.
147
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 75: Receive STS-3 Transport Status Register – Byte 1 (Address Location= 0x1106)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
J0 Message
Mismatch
Defect
Declared
J0 Message
Unstable
Defect
Declared
AIS_L Defect
Declared
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
J0 Message
Mismatch Defect
Declared
R/O
DESCRIPTION
J0 – Section Trace Mismatch Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring the Section Trace Mismatch condition.
The Receive STS-3 TOH Processor block will declare a J0 (Section Trace)
Mismatch condition, whenever it accepts a J0 Message that differs from the
“Expected J0 Message”.
0 – Section Trace Mismatch Condition is NOT declared.
1 – Section Trace Mismatch Condition is currently declared.
1
J0 Message
Unstable Defect
Declared
R/O
J0 – Section Trace Unstable Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring the Section Trace Instability condition.
The Receive STS-3 TOH Processor block will declare a J0 (Section Trace)
Unstable condition, whenever the “J0 Unstable” counter reaches the value
8. The “J0 Unstable” counter will be incremented for each time that it
receives a J0 message that differs from the “Expected J0 Message”. The
“J0 Unstable” counter is cleared to “0” whenever the Receive STS-3 TOH
Processor block has received a given J0 Message 3 (or 5) consecutive
times.
Note:
Receiving a given J0 Message 3 (or 5) consecutive times also sets
this bit-field to “0”.
0 – Section Trace Instability condition is NOT declared.
1 – Section Trace Instability condition is currently declared.
0
AIS_L
Defect
Declared
R/O
AIS-L (Line AIS) State:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently detecting an AIS-L (Line AIS) pattern in the
incoming STS-3 data stream. AIS-L is declared if bits 6, 7 and 8 (e.g., the
Least Significant Bits, within the K2 byte) value the value “1, 1, 1” for five
consecutive STS-1 frames.
0 – AIS-L is NOT currently declared.
1 – AIS-L is currently being declared.
148
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 76: Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1107)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RDI-L
Defect
Declared
S1 Byte
Unstable
Defect
Declared
(K1, K2)
APS Byte
Unstable
SF Defect
Declared
SD Defect
Declared
LOF
Defect
Declared
SEF
Defect
Declared
LOS
Defect
Declared
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
RDI-L Defect
Declared
R/O
DESCRIPTION
RDI-L (Line Remote Defect Indicator) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring a Line-Remote Defect Indicator (RDI-L), in
the incoming STS-3 signal. RDI-L is declared when bits 6, 7 and 8 (e.g., the
three least significant bits) of the K2 byte contains the “1, 1, 0” pattern in 5
consecutive STS-3 frames.
0 – RDI-L is NOT being declared.
1 – RDI-L is currently being declared.
6
S1 Byte
Unstable
Defect
Declared
R/O
S1 Byte Unstable Defect Declared Condition:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring the “S1 Byte Instability” condition. The
Receive STS-3 TOH Processor block will declare an “S1 Byte Instability”
condition whenever the “S1 Byte Unstable Counter” reaches the value 32. The
“S1 Byte Unstable Counter” is incremented for each time that the Receive STS-3
TOH Processor block receives an S1 byte that differs from the previously
received S1 byte. The “S1 Byte Unstable Counter” is cleared to “0” when the
same S1 byte is received for 8 consecutive STS-3 frames.
Note:
Receiving a given S1 byte, in 8 consecutive STS-3 frames also sets this
bit-field to “0”.
0 – S1 Instability Condition is NOT declared.
1 – S1 Instability Condition is currently declared.
5
(K1, K2)
APS Byte
Unstable
R/O
APS (K1, K2 Byte) Unstable Condition:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring the “K1, K2 Byte Unstable” condition. The
Receive STS-3 TOH Processor block will declare a “K1, K2 Byte Unstable”
condition whenever the Receive STS-3 TOH Processor block fails to receive the
same set of K1, K2 bytes, in 12 consecutive STS-3 frames. The “K1, K2 Byte
Unstable” condition is cleared whenever the Receive STS-3 TOH Processor
block receives a given set of K1, K2 byte values in three consecutive STS-3
frames.
0 – K1, K2 Unstable Condition is NOT currently declared.
1 – K1, K2 Unstable Condition is currently declared.
4
SF Defect
Declared
R/O
SF (Signal Failure) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring the SF defect. The SF defect is declared
when the number of B2 errors observed over a given time interval exceeds a
certain threshold.
0 – SF Defect is NOT being declared.
This bit is set to “0” when the number of B2 errors (accumulated over a given
149
XRT94L33
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T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
interval of time) does not exceed the “SF Declaration” threshold.
1 – SF Defect is being declared.
This bit is set to “1” when the number of B2 errors (accumulated over a given
interval of time) does exceed the “SF Declaration” threshold.
3
SD Defect
Declared
R/O
SD (Signal Degrade) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring the SD defect. The SD defect is declared
when the number of B2 errors observed over a given time interval exceeds a
certain threshold.
0 – SD Defect is NOT being declared.
This bit is set to “0” when the number of B2 errors (accumulated over a given
interval of time) does not exceed the “SD Declaration” threshold.
1 – SD Defect is being declared.
This bit is set to “1” when the number of B2 errors (accumulated over a given
interval of time) does exceed the “SD Declaration” threshold.
2
LOF
Defect
Declared
R/O
LOF (Loss of Frame) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring an LOF defect condition. The Receive
STS-3 TOH Processor block will declare an LOF defect condition, if continues to
declare the SEF (Severely Errored Frame) condition for 3ms (or 24 SONET
frame periods).
0 – LOF is NOT being declared.
1 – LOF is currently being declared.
1
SEF
Defect
Declared
R/O
SEF (Severely Errored Frame) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring an SEF condition. The SEF condition is
declared, if the “SEF Declaration Criteria”; per the settings of the
FRPATOUT[1:0] bits, within the Receive STS-3 Transport – In-Sync Threshold
Value Register (Address Location= 0x112B).
0 – SEF condition is NOT being declared.
1 – SEF condition is currently being declared.
0
LOS
Defect
Declared
R/O
LOS (Loss of Signal) Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-3 TOH
Processor block is currently declaring an LOS (Loss of Signal) defect condition.
The Receive STS-3 TOH Processor block will declare an LOS defect condition if
it detects “LOS_THRESHOLD[15:0]” consecutive “All Zero” bytes in the incoming
STS-3 data stream.
Note:
The user can set the “LOS_THRESHOLD[15:0]” value by writing the
appropriate data into the “Receive STS-3 Transport – LOS Threshold
Value” Register (Address Location= 0x112E and 0x112F).
0 – Indicates that the Receive STS-3 TOH Processor block is NOT currently
declaring an LOS defect condition.
1 – Indicates that the Receive STS-3 TOH Processor block is currently declaring
an LOS defect condition.
150
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 77: Receive STS-3 Transport Interrupt Status Register – Byte 2 (Address Location= 0x1109)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
Change of AIS-L
Condition
Interrupt Status
Change of RDI-L
Condition
Interrupt Status
R/O
R/O
R/O
R/O
R/O
R/O
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-2
Unused
R/O
1
Change of AIS-L
Condition
Interrupt Status
RUR
DESCRIPTION
Change of AIS-L (Line AIS) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
AIS-L Condition” interrupt has occurred since the last read of this register.
0 – The “Change of AIS-L Condition” interrupt has not occurred since the
last read of this register.
1 – The “Change of AIS-L Condition” interrupt has occurred since the last
read of this register.
Note:
0
Change of
RDI-L Condition
Interrupt Status
RUR
The user can obtain the current state of AIS-L by reading the
contents of Bit 0 (AIS-L Defect Declared) within the “Receive STS3 Transport Status Register – Byte 1” (Address Location=
0x1106).
Change of RDI-L (Line - Remote Defect Indicator) Condition Interrupt
Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
RDI-L Condition” interrupt has occurred since the last read of this register.
0 – The “Change of RDI-L Condition” interrupt has not occurred since the
last read of this register.
1 – The “Change of RDI-L Condition” interrupt has occurred since the last
read of this register.
Note:
The user can obtain the current state of RDI-L by reading out the
state of Bit 7 (RDI-L Declared) within the “Receive STS-3
Transport Status Register – Byte 0” (Address Location = 0x1107).
I
151
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 78: Receive STS-3 Transport Interrupt Status Register – Byte 1 (Address Location= 0x110A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New S1
Byte
Interrupt
Status
Change in
S1 Unstable
State
Interrupt
Status
Change in
J0 Message
Unstable
State
Interrupt
Status
New J0
Message
Interrupt
Status
Change in
J0 Mismatch
Condition
Interrupt
Status
Receive
TOH CAP
DONE
Interrupt
Status
Change in
(K1, K2)
APS Bytes
Unstable
State
Interrupt
Status
NEW K1K2
Byte
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
New S1 Byte
Value Interrupt
Status
RUR
DESCRIPTION
New S1 Byte Value Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New S1 Byte
Value” Interrupt has occurred since the last read of this register.
0 – Indicates that the “New S1 Byte Value” Interrupt has NOT occurred
since the last read of this register.
1 – Indicates that the “New S1 Byte Value” interrupt has occurred since the
last read of this register.
Note:
6
Change in S1
Byte Unstable
State Interrupt
Status
RUR
The user can obtain the value for this most recently accepted value
of the S1 byte by reading the “Receive STS-3 Transport S1 Value”
register (Address Location= 0x1127).
Change in S1 Byte Unstable State – Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change in
S1 Byte Unstable State” Interrupt has occurred since the last read of this
register.
0 – Indicates that the “Change in S1 Byte Unstable State” Interrupt has
occurred since the last read of this register.
1 – Indicates that the “Change in S1 Byte Unstable State” Interrupt has not
occurred since the last read of this register.
Note:
5
Change in J0
Message
Unstable State
Interrupt Status
RUR
The user can obtain the current “S1 Unstable” state by reading the
contents of Bit 6 (S1 Unstable) within the “Receive STS-3
Transport Status Register – Byte 0” (Address Location= 0x1107).
Change of J0 (Section Trace) Message Unstable condition – Interrupt
Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of J0
(Section Trace) Message Instability” condition interrupt has occurred since
the last read of this register.
0 – Indicates that the “Change of J0 (Section Trace) Message Instability”
condition interrupt has not occurred since the last read of this register.
1 – Indicates that the “Change of J0 (Section Trace) Message Instability”
condition interrupt has occurred since the last read of this register.
4
New J0 Message
Interrupt Status
RUR
New J0 Trace Message Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New J0
Trace Message” interrupt has occurred since the last read of this register.
0 – Indicates that the “New J0 Trace Message Interrupt” has not occurred
since the last read of this register.
152
XRT94L33
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C
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A
N
N
E
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S
T
S
T
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M
M
A
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A
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M
R
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S
T
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R
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CH
HA
AN
NN
NE
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1 – Indicates that the “New J0 Trace Message Interrupt” has occurred since
the last read of this register.
Note:
3
Change in J0
Mismatch
Condition
Interrupt Status
RUR
The user can read out the contents of the “Receive J0 Trace
Buffer”, which is located at Address location 0x1300 through
0x133F.
Change in J0 – Section Trace Mismatch Condition” Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change in J0
– Section Trace Mismatch Condition” interrupt has occurred since the last
read of this register.
0 – Indicates that the “Change in J0 – Section Trace Mismatch Condition”
interrupt has not occurred since the last read of this register.
1 – Indicates that the “Change in J0 – Section Trace Mismatch Condition”
interrupt has occurred since the last read of this register.
Note:
2
Receive TOH
CAP DONE
Interrupt Status
RUR
The user can determine whether the “J0 – Section Trace
Mismatch” condition is “cleared” or “declared” by reading the state
of Bit 2 (J0_MIS) within the “Receive STS-3 Transport Status
Register – Byte 1 (Address Location= 0x1106).
Receive TOH Capture DONE – Interrupt Status:
This RESET-upon-READ bit-field indicates whether the “Receive TOH Data
Capture” Interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive STS-3 TOH Processor block will
generate an interrupt anytime it has captured the last TOH byte into the
Capture Buffer.
Note:
Once the TOH (of a given STS-3 frame) has been captured and
loaded into the “Receive TOH Capture” buffer, it will remain there
for one SONET frame period.
0 – Indicates that the “Receive TOH Data Capture” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Receive TOH Data Capture” Interrupt has occurred
since the last read of this register.
1
Change in APS
(K1, K2 Byte)
Unstable Status
Interrupt Status
RUR
Change of APS (K1, K2 Byte) Unstable Condition – Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
APS (K1, K2 Byte) Instability Condition” interrupt has occurred since the last
read of this register.
0 – Indicates that the “Change of APS (K1, K2 Byte) Instability Condition”
interrupt has NOT occurred since the last read of this register.
1 – Indicates that the “Change of APS (K1, K2 Byte) Instability Condition”
interrupt has occurred since the last read of this register.
Note:
0
NEW K1K2 Byte
Interrupt Status
RUR
The user can determine whether the “K1, K2 Unstable Condition” is
being declared or cleared by reading out the contents of Bit 5
(APS Unstable), within the “Receive STS-3 Transport Status
Register – Byte 0” (Address Location = 0x1107).
New K1, K2 Byte Value Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New K1, K2
Byte Value” Interrupt has occurred since the last read of this register.
0 – Indicates that the “New K1, K2 Byte Value” Interrupt has NOT occurred
since the last read of this register.
1 – Indicates that the “New K1, K2 Byte Value” Interrupt has occurred since
the last read of this register.
Note:
The user can obtain the contents of the new K1 byte by reading out
153
XRT94L33
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S
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
the contents of the “Receive STS-3 Transport K1 Value” Register
(Address Location= 0x111F). Further, the user can also obtain
the contents of the new K2 byte by reading out the contents of the
“Receive STS-3 Transport K2 Value” Register (Address Location=
0x1123).
154
XRT94L33
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A
N
N
E
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E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 79: Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address Location= 0x110B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change in
SF
Condition
Interrupt
Status
Change in
SD
Condition
Interrupt
Status
Detection of
REI-L Error
Interrupt
Status
Detection of
B2 Error
Interrupt
Status
Detection of
B1 Error
Interrupt
Status
Change of
LOF
Condition
Interrupt
Status
Change of
SEF
Condition
Interrupt
Status
Change of
LOS
Condition
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Change in SF
Condition
Interrupt Status
RUR
DESCRIPTION
Change of Signal Failure (SF) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
SF Condition Interrupt” has occurred since the last read of this register.
0 - The “Change of SF Condition Interrupt” has NOT occurred since the
last read of this register.
1 – The “Change of SF Condition Interrupt” has occurred since the last read
of this register.
Note:
6
Change of SD
Condition
Interrupt Status
RUR
The user can determine the current “SF” condition by reading out
the state of Bit 4 (SF Declared) within the “Receive STS-3
Transport Status Register – Byte 0 (Address Location= 0x1107).
Change of Signal Degrade (SD) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
SD Condition Interrupt” has occurred since the last read of this register.
0 - The “Change of SD Condition Interrupt” has NOT occurred since the
last read of this register.
1 – The “Change of SD Condition Interrupt” has occurred since the last
read of this register.
Note:
5
Detection of REIL Interrupt Status
RUR
The user can determine the current “SD” condition by reading out
the state of Bit 3 (SD Declared) within the “Receive STS-3
Transport Status Register – Byte 0 (Address Location= 0x1107).
Detection of Line – Remote Error Indicator Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Declaration
of Line – Remote Error Indicator” Interrupt has occurred since the last read
of this register.
0 - The “Declaration of Line – Remote Error Indicator” Interrupt has NOT
occurred since the last read of this register.
1 – The “Declaration of Line – Remote Error Indicator” Interrupt has
occurred since the last read of this register.
4
Detection of B2
Error Interrupt
Status
RUR
Detection of B2 Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Detection of
B2 Error Interrupt” has occurred since the last read of this register.
0 - The “Detection of B2 Error Interrupt” has NOT occurred since the last
read of this register.
1 – The “Detection of B2 Error Interrupt” has occurred since the last read of
this register.
155
XRT94L33
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
3
Detection of B1
Error Interrupt
Status
RUR
Rev222...000...000
Detection of B1 Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Detection of
B1 Error Interrupt” has occurred since the last read of this register.
0 - The “Detection of B1 Error Interrupt” has NOT occurred since the last
read of this register.
1 – The “Detection of B1 Error Interrupt” has occurred since the last read of
this register
2
Change of LOF
Interrupt Status
RUR
Change of Loss of Frame (LOF) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
LOF Condition” interrupt has occurred since the last read of this register.
0 – The “Change of LOF Condition” interrupt has NOT occurred since the
last read of this register.
1 – The “Change of LOF Condition” interrupt has occurred since the last
read of this register.
Note:
1
Change of SEF
Condition
Interrupt Status
RUR
The user can determine the current “LOF” condition by reading out
the state of Bit 2 (LOF Defect Declared) within the “Receive STS3 Transport Status Register – Byte 0 (Address Location=
0x1107).
Change of SEF Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
SEF” Condition Interrupt has occurred since the last read of this register.
0 – The “Change of SEF Condition” Interrupt has NOT occurred since the
last read of this register.
1 – The “Change of SEF Condition” Interrupt has occurred since the last
read of this register.
Note:
0
Change of LOS
Condition
Interrupt Status
RUR
The user can determine the current “SEF” condition by reading out
the state of Bit 1 (SEF Defect Declared) within the “Receive STS3 Transport Status Register – Byte 0 (Address Location=
0x1107).
Change of Loss of Signal (LOS) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
LOS Condition” interrupt has occurred since the last read of this register.
0 – The “Change of LOS Condition” Interrupt has NOT occurred since the
last read of this register.
1 – The “Change of LOS Condition” Interrupt has occurred since the last
read of this register.
Note:
The user can determine the current “LOS” status by reading out
the contents of Bit 0 (LOS Defect Declared) within the Receive
STS-3 Transport Status Register – Byte 0 (Address Location=
0x1107).
156
XRT94L33
333---C
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M
M
A
P
P
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R
A
T
M
R
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G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 80: Receive STS-3 Transport Interrupt Enable Register – Byte 2 (Address Location= 0x110D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
Change of AIS-L
Condition
Interrupt Enable
Change of RDI-L
Condition
Interrupt Enable
R/O
R/O
R/O
R/O
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–2
Unused
R/O
1
Change of AIS-L
Condition
Interrupt Enable
R/W
DESCRIPTION
Change of AIS-L (Line AIS) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of AIS-L Condition” interrupt. If the user enables this interrupt,
then the XRT94L33 will generate an interrupt in response to either of the
following conditions.
• When the Receive STS-3 TOH Processor block declares the “AIS-L”
condition.
• When the Receive STS-3 TOH Processor block clears the “AIS-L”
condition.
0 – Disables the “Change of AIS-L Condition” Interrupt.
1 – Enables the “Change of AIS-L Condition” Interrupt.
Note:
0
Change of RDI-L
Condition
Interrupt Enable
R/W
The user can determine the current “AIS-L” condition by reading
out the state of Bit 0 (AIS-L) within the “Receive STS-3 Transport
Status Register – Byte 1” (Address Location= 0x1106).
Change of RDI-L (Line Remote Defect Indicator) Condition Interrupt
Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of RDI-L Condition” interrupt. If the user enables this interrupt,
then the XRT94L33 will generate an interrupt in response to either of the
following conditions.
• When the Receive STS-3 TOH Processor block declares the “RDI-L”
condition.
• When the Receive STS-3 TOH Processor block clears the “RDI-L”
condition.
0 – Disables the “Change of RDI-L Condition” Interrupt.
1 – Enables the “Change of RDI-L Condition” Interrupt.
157
XRT94L33
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A
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R
S
C
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 81: Receive STS-3 Transport Interrupt Enable Register – Byte 1 (Address Location= 0x110E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New S1
Byte
Interrupt
Enable
Change in
S1 Byte
Unstable
State
Interrupt
Enable
Change in
J0 Message
Unstable
State
Interrupt
Enable
New J0
Message
Interrupt
Enable
J0 Mismatch
Interrupt
Enable
Receive
TOH CAP
DONE
Interrupt
Enable
Change in
APS
Unstable
State
Interrupt
Enable
NEW
K1K2 Byte
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
New S1
Byte
Value
Interrupt
Enable
R/W
DESCRIPTION
New S1 Byte Value Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the “New S1 Byte
Value” Interrupt. If the user enables this interrupt, then the Receive STS-3 TOH
Processor block will generate this interrupt anytime it receives and accepts a new S1
byte value. The Receive STS-3 TOH Processor block will accept a new S1 byte after
it has received it for 8 consecutive STS-3 frames.
0 – Disables the “New S1 Byte Value” Interrupt.
1 – Enables the “New S1 Byte Value” Interrupt.
6
Change in
S1
Unstable
State
Interrupt
Enable
R/W
Change in S1 Byte Unstable State Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the “Change
in S1 Byte Unstable State” Interrupt. If the user enables this bit-field, then the
Receive STS-3 TOH Processor block will generate an interrupt in response to either
of the following conditions.
•
When the Receive STS-3 TOH Processor block declares the “S1 Byte Instability”
condition.
•
When the Receive STS-3 TOH Processor block clears the “S1 Byte Instability”
condition.
0 – Disables the “Change in S1 Byte Unstable State” Interrupt.
1 – Enables the “Change in S1 Byte Unstable State” Interrupt.
5
Change in
J0
Message
Unstable
State
Interrupt
Enable
R/W
Change of J0 (Section Trace) Message Instability condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the “Change
of J0 Message Instability Condition” Interrupt. If the user enables this interrupt, then
the Receive STS-3 TOH Processor block will generate an interrupt in response to
either of the following conditions.
•
Whenever the Receive STS-3 TOH Processor block declares the “J0 Message
Instability” condition.
•
Whenever the Receive STS-3 TOH Processor block clears the “J0 Message
Instability” condition.
0 – Disable the “Change of J0 Message Instability” Interrupt.
1 – Enables the “Change of J0 Message Instability” Interrupt.
4
New J0
Message
Interrupt
Enable
R/W
New J0 Trace Message Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the “New J0 Trace
Message” interrupt. If the user enables this interrupt, then the Receive STS-3 TOH
Processor block will generate this interrupt anytime it receives and accepts a new J0
Trace Message. The Receive STS-3 TOH Processor block will accept a new J0
158
XRT94L33
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M
M
A
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P
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R
A
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M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Trace Message after it has received it 3 (or 5) consecutive times.
0 – Disables the “New J0 Trace Message” Interrupt.
1 – Enables the “New J0 Trace Message” Interrupt.
3
J0
Mismatch
Interrupt
Enable
R/W
Change in “J0 – Section Trace Mismatch Condition” interrupt enable:
This READ/WRITE bit-field permits the user to either enable or disable the “Change
in J0 – Section Trace Mismatch condition” interrupt. If the user enables this interrupt,
then the Receive STS-3 TOH Processor block will generate an interrupt in response
to either of the following events.
•
The Receive STS-3 TOH Processor block declares a “J0 – Section Trace
Mismatch” condition.
•
The Receive STS-3 TOH Processor block clears the “J0 – Section Trace
Mismatch” condition.
Note:
2
Receive
TOH CAP
DONE
Interrupt
Enable
R/W
The user can determine whether the “J0 – Section Trace Mismatch”
condition is “cleared or “declared” by reading the state of Bit 2 (J0 Message
Mismatch Defect Declared) within the “Receive STS-3 Transport Status
Register – Byte 1 (Address Location= 0x1106).
Receive TOH Capture DONE – Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the “Receive
TOH Data Capture” interrupt, within the Receive STS-3 TOH Processor Block.
If this interrupt is enabled, then the Receive STS-3 TOH Processor block will
generate an interrupt anytime it has captured the last TOH byte into the Capture
Buffer.
Note:
Once the TOH (of a given STS-3 frame) has been captured and loaded into
the “Receive TOH Capture” buffer, it will remain there for one SONET
frame period.
0 – Disables the “Receive TOH Capture” Interrupt.
1 – Enables the “Receive TOH Capture” Interrupt.
1
0
Change in
APS
Unstable
State
Interrupt
Enable
New K1K2
Byte
Interrupt
Enable
R/W
Change of APS (K1, K2 Byte) Instability Condition - Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the “Change
of APS (K1, K2 Byte) Instability condition” interrupt. If the user enables this interrupt,
then the Receive STS-3 TOH Processor block will generate an Interrupt in response
to either of the following events.
R/W
•
If the Receive STS-3 TOH Processor block declares a “K1, K2 Instability”
condition.
•
If the Receive STS-3 TOH Processor block clears the “K1, K2 Instability”
condition.
New K1, K2 Byte Value Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the “New K1,
K2 Byte Value” Interrupt. If the user enables this interrupt, then the Receive STS-3
TOH Processor block will generate this interrupt anytime it receives and accepts a
new K1, K2 byte value. The Receive STS-3 TOH Processor block will accept a new
K1, K2 byte value, after it has received it within 3 (or 5) consecutive STS-3 frames.
0 – Disables the “New K1, K2 Byte Value” Interrupt.
1 – Enables the “New K1, K2 Byte Value” Interrupt.
159
XRT94L33
333---C
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M
M
A
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P
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R
A
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M
R
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G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 82: Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address Location= 0x110F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change of
SF
Condition
Interrupt
Enable
Change of
SD
Condition
Interrupt
Enable
Detection of
REI-L Error
Interrupt
Enable
Detection of
B2 Error
Interrupt
Enable
Detection of
B1 Error
Interrupt
Enable
Change of
LOF
Condition
Interrupt
Enable
Change of
SEF
Condition
Interrupt
Enable
Change of
LOS
Condition
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Change of SF
Condition
Interrupt Enable
R/W
DESCRIPTION
Change of Signal Failure (SF) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of Signal Failure (SF) Condition” Interrupt. If the user enables this
interrupt, then the XRT94L33 will generate an interrupt anytime the Receive
STS-3 TOH Processor block either declares or clears the SF defect.
0 – Disables the “Change of SF Condition Interrupt”.
1 – Enables the “Change of SF Condition Interrupt”.
6
Change of SD
Condition
Interrupt Enable
R/W
Change of Signal Degrade (SD) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of Signal Degrade (SD) Condition” Interrupt. If the user enables this
interrupt, then the XRT94L33 will generate an interrupt anytime the Receive
STS-3 TOH Processor block either declares or clears the SD defect.
0 – Disables the “Change of SD Condition Interrupt”.
1 – Enables the “Change of SD Condition Interrupt”.
5
Detection of
REI-L Interrupt
Enable
R/W
Detection of Line – Remote Error Indicator Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Declaration of Line – Remote Error Indicator” interrupt. If the user enables
this interrupt, then the XRT94L33 will generate an interrupt anytime the
Receive STS-3 TOH Processor block declares the “REI-L” defect.
0 – Disables the “Line - Remote Error Indicator” Interrupt.
1 – Enables the “Line – Remote Error Indicator” Interrupt.
4
Detection of B2
Error Interrupt
Enable
R/W
Detection of B2 Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of B2 Error” Interrupt. If the user enables this interrupt, then the
XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH
Processor block detects a B2 error.
0 – Disables the “Detection of B2 Error Interrupt”.
1 – Enables the “Detection of B2 Error Interrupt”.
3
Detection of B1
Error Interrupt
Enable
R/W
Detection of B1 Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of B1 Error” Interrupt. If the user enables this interrupt, then the
XRT94L33 will generate an interrupt anytime the Receive STS-3 TOH
Processor block detects a B1 error.
0 – Disables the “Detection of B1 Error Interrupt”.
1 – Enables the “Detection of B1 Error Interrupt”.
160
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
2
Change of LOF
Condition
Interrupt Enable
R/W
Change of Loss of Frame (LOF) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of LOF Condition” interrupt. If the user enables this interrupt, then
the XRT94L33 will generate an interrupt in response to either of the following
conditions.
• When the Receive STS-3 TOH Processor block declares the “LOF”
condition.
• When the Receive STS-3 TOH Processor clears the “LOF” condition.
0 – Disables the “Change of LOF Condition Interrupt.
1 – Enables the “Change of LOF Condition” Interrupt.
1
Change of SEF
Condition
Interrupt Enable
R/W
Change of SEF Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of SEF Condition” Interrupt. If the user enables this interrupt, then
the XRT94L33 will generate an interrupt in response to either of the following
conditions.
• When the Receive STS-3 TOH Processor block declares the “SEF”
condition.
•
When the
”SEF” condition.
Receive
STS-3
TOH
Processor
block
clears
the
0 – Disables the “Change of SEF Condition Interrupt”.
1 – Enables the “Change of SEF Condition Interrupt”.
0
Change of LOS
Condition
Interrupt Enable
R/W
Change of Loss of Signal (LOS) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of LOF Condition” interrupt. If the user enables this interrupt, then
the XRT94L33 will generate an interrupt in response to either of the following
conditions.
• When the Receive STS-3 TOH Processor block declares the “LOF”
condition.
• When the Receive STS-3 TOH Processor block clears the “LOF” condition.
0 – Disables the “Change of LOF Condition Interrupt.
1 – Enables the “Change of LOF Condition” Interrupt.
161
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 83: Receive STS-3 Transport – B1 Error Count Register – Byte 3 (Address Location= 0x1110)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7-0
B1_Error_Count
[31:24]
RUR
DESCRIPTION
B1 Error Count – MSB:
This RESET-upon-READ register, along with “Receive Transport – B1 Error
Count Register – Bytes 2 through 0; function as a 32 bit counter, which is
incremented anytime the Receive STS-3 TOH Processor block detects a B1
byte error.
Note:
1.If the B1 Error Type is configured to be “bit errors”, then the Receive STS-3
TOH Processor block will increment this 32 bit counter by the number of bits,
within the B1 value that are in error.
2.If the B1 Error Type is configured to be “frame errors”, then the Receive
STS-3 TOH Processor block will increment this 32 bit counter by the number
of frames that contain erred B1 bytes.
Table 84: Receive STS-3 Transport – B1 Error Count Register – Byte 2 (Address Location= 0x1111)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
B1_Error_Count[23:16]
BIT NUMBER
NAME
TYPE
7-0
B1_Error_Count
[23:16]
RUR
DESCRIPTION
B1 Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Receive Transport – B1 Error
Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which is
incremented anytime the Receive STS-3 TOH Processor block detects a B1
byte error.
Note:
1.If the B1 Error Type is configured to be “bit errors”, then the Receive STS-3
TOH Processor block will increment this 32 bit counter by the number of bits,
within the B1 value that are in error.
2.If the B1 Error Type is configured to be “frame errors”, then the Receive
STS-3 TOH Processor block will increment this 32 bit counter by the number
of frames that contain erred B1 bytes.
162
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 85: Receive STS-3 Transport – B1 Error Count Register – Byte 1 (Address Location= 0x1112)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B1_Error_Count
[15:8]
RUR
DESCRIPTION
B1 Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Receive Transport – B1 Error
Count Register – Bytes 3, 2 and 0; function as a 32 bit counter, which is
incremented anytime the Receive STS-3 TOH Processor block detects a B1
byte error.
Note:
1.If the B1 Error Type is configured to be “bit errors”, then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of
bits, within the B1 value that are in error.
2.If the B1 Error Type is configured to be “frame errors”, then the Receive
STS-3 TOH Processor block will increment this 32 bit counter by the number
of frames that contain erred B1 bytes.
Table 86: Receive STS-3 Transport – B1 Error Count Register – Byte 0 (Address Location= 0x1113)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B1_Error_Count
[7:0]
RUR
DESCRIPTION
B1 Error Count – LSB:
This RESET-upon-READ register, along with “Receive Transport – B1 Error
Count Register – Bytes 3 through 1; function as a 32 bit counter, which is
incremented anytime the Receive STS-3 TOH Processor block detects a B1
byte error.
Note:
1.If the B1 Error Type is configured to be “bit errors”, then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of
bits, within the B1 value that are in error.
2.If the B1 Error Type is configured to be “frame errors”, then the Receive
STS-3 TOH Processor block will increment this 32 bit counter by the number
of frames that contain erred B1 bytes.
163
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 87: Receive STS-3 Transport – B2 Error Count Register – Byte 3 (Address Location= 0x1114)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count
[31:24]
RUR
DESCRIPTION
B2 Error Count – MSB:
This RESET-upon-READ register, along with “Receive STS-3 Transport –
B2 Error Count Register – Bytes 2 through 0; function as a 32 bit counter,
which is incremented anytime the Receive STS-3 TOH Processor block
detects a B2 byte error.
Note:
1.If the B2 Error Type is configured to be “bit errors”, then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of
bits, within the B2 value that are in error.
2.If the B2 Error Type is configured to be “frame errors”, then the Receive
STS-3 TOH Processor block will increment this 32 bit counter by the number
of frames that contain erred B2 bytes.
Table 88: Receive STS-3 Transport – B2 Error Count Register – Byte 2 Address Location= 0x1115)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count
[23:16]
RUR
DESCRIPTION
B2 Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Receive STS-3 Transport –
B2 Error Count Register – Bytes 3, 1 and 0; function as a 32 bit counter,
which is incremented anytime the Receive STS-3 TOH Processor block
detects a B2 byte error.
Note:
1.If the B2 Error Type is configured to be “bit errors”, then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of
bits, within the B2 value that are in error.
2.If the B2 Error Type is configured to be “frame errors”, then the Receive
STS-3 TOH Processor block will increment this 32 bit counter by the number
of frames that contain erred B2 bytes.
164
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 89: Receive STS-3 Transport – B2 Error Count Register – Byte 1 (Address Location= 0x1116)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count
[15:8]
RUR
DESCRIPTION
B2 Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Receive STS-3 Transport –
B2 Error Count Register – Bytes 3, 2 and 0; function as a 32 bit counter,
which is incremented anytime the Receive STS-3 TOH Processor block
detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the Receive STS3 TOH Processor block will increment this 32 bit counter by the number of
bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the Receive
STS-3 TOH Processor block will increment this 32 bit counter by the number
of frames that contain erred B2 bytes.
Table 90: Receive STS-3 Transport – B2 Error Count Register – Byte 0 (Address Location= 0x1117)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count[7:0]
RUR
DESCRIPTION
B2 Error Count – LSB:
This RESET-upon-READ register, along with “Receive Transport – B2
Error Count Register – Bytes 3 through 1; function as a 32 bit counter,
which is incremented anytime the Receive STS-3 TOH Processor block
detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the Receive
STS-3 TOH Processor block will increment this 32 bit counter by the
number of bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the
Receive STS-3 TOH Processor block will increment this 32 bit counter by
the number of frames that contain erred B2 bytes.
165
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 91: Receive STS-3 Transport – REI-L Error Count Register – Byte 3 (Address Location= 0x1118)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_L_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count
[31:24]
RUR
DESCRIPTION
REI-L Error Count – MSB:
This RESET-upon-READ register, along with “Receive Transport –
REI-L Error Count Register – Bytes 2 through 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-3 TOH
Processor block detects a Line - Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Receive STS-3 TOH Processor block will increment this 32 bit
counter by the value within the REI-L fields of the M1 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then the
Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-L values.
Table 92: Receive STS-3 Transport – REI_L Error Count Register – Byte 2 (Address Location= 0x1119)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_L_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count
[23:16]
RUR
DESCRIPTION
REI-L Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Receive Transport –
REI-L Error Count Register – Bytes 3, 1 and 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-3 TOH
Processor block detects a Line – Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Receive STS-3 TOH Processor block will increment this 32 bit
counter by the value within the REI-L fields of the M1 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then
the Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-L
values.
166
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 93: Receive STS-3 Transport – REI_L Error Count Register – Byte 1 (Address Location= 0x111A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_L_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count[15:8]
RUR
DESCRIPTION
REI-L Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Receive Transport –
REI-L Error Count Register – Bytes 3, 2 and 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-3 TOH
Processor block detects a Line –Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Receive STS-3 TOH Processor block will increment this 32 bit
counter by the value within the REI-L fields of the M1 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then
the Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-L
values.
Table 94: Receive STS-3 Transport – REI_L Error Count Register – Byte 0 (Address Location= 0x111B)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
REI_L_Error_Count[7:0]
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count[7:0]
RUR
DESCRIPTION
REI-L Error Count – LSB:
This RESET-upon-READ register, along with “Receive Transport –
REI-L Error Count Register – Bytes 3 through 1; function as a 32 bit
counter, which is incremented anytime the Receive STS-3 TOH
Processor block detects a Line – Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Receive STS-3 TOH Processor block will increment this 32 bit
counter by the value within the REI-L fields of the M1 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then the
Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-L values.
167
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 95: Receive STS-3 Transport K1 Value (Address Location= 0x111F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Filtered_K1_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Filtered_K1_Value[7:0]
R/O
DESCRIPTION
Filtered/Accepted K1 Value:
These READ-ONLY bit-fields contain the value of the most recently
“filtered” K1 value, that the Receive STS-3 TOH Processor block has
received. These bit-fields are valid if the K1/K2 pair (to which it
belongs) has been received for 3 consecutive STS-3 frames.
This register should be polled by Software in order to determine various
APS codes.
Table 96: Receive STS-3 Transport K2 Value (Address Location= 0x1123)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Filtered_K2_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Filtered_K2_Value[7:0]
R/O
DESCRIPTION
Filtered/Accepted K2 Value:
These READ-ONLY bit-fields contain the value of the most recently
“filtered” K2 value, that the Receive STS-3 TOH Processor block has
received. These bit-fields are valid if the K1/K2 pair (to which it
belongs) has been received for 3 consecutive STS-3 frames.
This register should be polled by Software in order to determine various
APS codes.
168
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 97: Receive STS-3 Transport S1 Value (Address Location= 0x1127)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Filtered_S1_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Filtered_S1_Value[7:0]
R/O
DESCRIPTION
Filtered/Accepted S1 Value:
These READ-ONLY bit-fields contain the value of the most recently
“filtered” S1 value that the Receive STS-3 TOH Processor block has
received. These bit-fields are valid if it has been received for 8
consecutive STS-3 frames.
Table 98: Receive STS-3 Transport – In-Sync Threshold Value (Address Location=0x112B)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
FRPATOUT[1:0]
BIT 1
FRPATIN[1:0]
BIT 0
Unused
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–5
Unused
R/O
4–3
FRPATOUT
[1:0]
R/W
DESCRIPTION
Framing Pattern – SEF Declaration Criteria:
These two READ/WRITE bit-fields permit the user to define the SEF Declaration
criteria for the Receive STS-3 TOH Processor block. The relationship between
the state of these bit-fields and the corresponding SEF Declaration Criteria are
presented below.
FRPATOUT[1:0]
SEF Declaration Criteria
00
The Receive STS-3 TOH Processor block will declare an
SEF condition if either of the following conditions are true
for four consecutive SONET frame periods.
01
•
If the last (of the 3) A1 bytes, in the STS-3 data
stream is erred, or
•
If the first (of the 3) A2 bytes, in the STS-3 data
stream, is erred.
Hence, for this selection, a total of 16 bits are evaluated for
SEF declaration.
10
The Receive STS-3 TOH Processor block will declare an
SEF condition if either of the following conditions are true
for four consecutive SONET frame periods.
•
If the last two (of the 3) A1 bytes, in the STS-3 data
stream, are erred, or
•
If the first two (of the 3) A2 bytes, in the STS-3 data
stream, are erred.
Hence, for this selection, a total of 32 bits are evaluated for
SEF declaration.
169
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
11
Rev222...000...000
The Receive STS-3 TOH Processor block will declare an
SEF condition if either of the following conditions are true
for four consecutive SONET frame periods.
•
If the last three (of the 3) A1 bytes, in the STS-3 data
stream, are erred, or
•
If the first three (of the 3) A2 bytes, in the STS-3 data
stream, are erred.
Hence, for this selection, a total of 48 bits are evaluated for
SEF declaration.
2-1
FRPATIN
[1:0]
R/W
Framing Pattern – SEF Clearance Criteria:
These two READ/WRITE bit-fields permit the user to define the “SEF Clearance”
criteria for the Receive STS-3 TOH Processor block. The relationship between
the state of these bit-fields and the corresponding SEF Clearance Criteria are
presented below.
FRPATIN[1:0]
SEF Clearance Criteria
00
The Receive STS-3 TOH Processor block will clear the
SEF condition if both of the following conditions are true
for two consecutive SONET frame periods.
01
•
If the last (of the 3) A1 bytes, in the STS-3 data
stream is un-erred, and
•
If the first (of the 3) A2 bytes, in the STS-3 data
stream, is un-erred.
Hence, for this selection, a total of 16 bits/frame are
evaluated for SEF clearance.
10
The Receive STS-3 TOH Processor block will clear the
SEF condition if both of the following conditions are true
for two consecutive SONET frame periods.
•
If the last two (of the 3) A1 bytes, in the STS-3 data
stream, are un-erred, and
•
If the first two (of the 3) A2 bytes, in the STS-3 data
stream, are un-erred.
Hence, for this selection, a total of 32 bits/frame are
evaluated for SEF clearance.
11
The Receive STS-3 TOH Processor block will clear the
SEF condition if both of the following conditions are true
for two consecutive SONET frame periods.
•
If the last three (of the 3) A1 bytes, in the STS-3 datastream, are un-erred, and
•
If the first three (of the 3) A2 bytes, in the STS-3 data
stream, are un-erred.
Hence, for this selection, a total of 48 bits/frame are
evaluated for SEF declaration.
0
Unused
R/O
170
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 99: Receive STS-3 Transport – LOS Threshold Value - MSB (Address Location= 0x112E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOS_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
LOS_THRESHOLD[15:8]
R/W
DESCRIPTION
LOS Threshold Value – MSB:
These READ/WRITE bits, along the contents of the “Receive STS-3
Transport – LOS Threshold Value – LSB” register specify the number
of consecutive (All Zero) bytes that the Receive STS-3 TOH
Processor block must detect before it can declare an LOS condition.
Table 100: Receive STS-3 Transport – LOS Threshold Value - LSB (Address Location= 0x112F)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
LOS_THRESHOLD[7:0]
BIT NUMBER
NAME
TYPE
7-0
LOS_THRESHOLD[7:0]
R/W
DESCRIPTION
LOS Threshold Value – LSB:
These READ/WRITE bits, along the contents of the “Receive STS-3
Transport – LOS Threshold Value – MSB” register specify the number
of consecutive (All Zero) bytes that the Receive STS-3 TOH Processor
block must detect before it can declare an LOS condition.
171
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 101: Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 2 (Address Location=
0x1131)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_SET_MONITOR_WINDOW[23:16]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
SF_SET_MONITOR_
WINDOW [23:16]
R/W
SF_SET_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the “Receive STS-3
Transport – SF SET Monitor Interval – Byte 1 and Byte 0” registers
permit the user to specify the number of STS-3 Frame periods that
will constitute a SET Sub-Interval for SF (Signal Failure).
When the Receive STS-3 TOH Processor block is checking for SF, it
will accumulate B2 errors for a total of 8 SET Sub-Interval periods. If
the number of accumulated B2 errors exceeds that of programmed
into the “Receive STS-3 Transport SF SET Threshold” register, then
an SF condition will be declared.
Table 102: Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 1 (Address Location=
0x1132)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_SET_MONITOR_WINDOW[15:8]
BIT
NUMBER
NAME
TYPE
7-0
SF_SET_MONITOR_WINDOW
[15:8]
R/W
DESCRIPTION
SF_SET_MONITOR_INTERVAL (Bits 15 through 8):
These READ/WRITE bits, along the contents of the “Receive
STS-3 Transport – SF SET Monitor Interval – Byte 2 and Byte 0”
registers permit the user to specify the number of STS-3 Frame
periods that will constitute a SET Sub-Interval for SF (Signal
Failure).
When the Receive STS-3 TOH Processor block is checking for
SF, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors
exceeds that of programmed into the “Receive STS-3 Transport
SF SET Threshold” register, then an SF condition will be
declared.
172
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 103: Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 0 (Address Location=
0x1133)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_SET_MONITOR_WINDOW[7:0]
BIT NUMBER
NAME
TYPE
7-0
SF_SET_MONITOR_WINDOW[7:0]
R/W
DESCRIPTION
SF_SET_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Receive STS-3 Transport – SF SET Monitor Interval –
Byte 2 and Byte 1” registers permit the user to specify
the number of STS-3 Frame periods that will constitute
a SET Sub-Interval for SF (Signal Failure).
When the Receive STS-3 TOH Processor block is
checking for SF, it will accumulate B2 bit errors for a
total of 8 SET Sub-Interval periods. If the number of
accumulated B2 bit errors exceeds that of programmed
into the “Receive STS-3 Transport SF SET Threshold”
register, then an SF condition will be declared.
Table 104: Receive STS-3 Transport – Receive SF SET Threshold – Byte 1 (Address Location= 0x1136)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_SET_THRESHOLD[15:8]
R/W
DESCRIPTION
SF_SET_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the “Receive
STS-3 Transport – SF SET Threshold – Byte 0” registers
permit the user to specify the number of B2 bit errors that will
cause the Receive STS-3 TOH Processor block to declare an
SF (Signal Failure) condition.
When the Receive STS-3 TOH Processor block is checking for
SF, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors
exceeds that of programmed into this and the “Receive STS-3
Transport SF SET Threshold – Byte 0” register, then an SF
condition will be declared.
173
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 105: Receive STS-3 Transport – Receive SF SET Threshold – Byte 0 Address Location= 0x1137)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_SET_THRESHOLD[7:
0]
R/W
DESCRIPTION
SF_SET_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the “Receive STS3 Transport – SF SET Threshold – Byte 1” registers permit the user
to specify the number of B2 bit errors that will cause the Receive
STS-3 TOH Processor block to declare an SF (Signal Failure)
condition.
When the Receive STS-3 TOH Processor block is checking for SF,
it will accumulate B2 errors for a total of 8 SET Sub-Interval
periods. If the number of accumulated B2 errors exceeds that of
programmed into this and the “Receive STS-3 Transport SF SET
Threshold – Byte 1” register, then an SF condition will be declared.
Table 106: Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 1 (Address Location=
0x113A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_CLEAR_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_THRESHOLD
[15:8]
R/W
DESCRIPTION
SF_CLEAR_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the “Receive
STS-3 Transport – SF CLEAR Threshold – Byte 0” registers
permit the user to specify the upper limit for the number of B2
bit errors that will cause the Receive STS-3 TOH Processor
block to clear the SF (Signal Failure) condition.
When the Receive STS-3 TOH Processor block is checking for
clearing SF, it will accumulate B2 errors for a total of 8 CLEAR
Sub-Interval periods. If the number of accumulated B2 errors
is less than that programmed into this and the “Receive STS-3
Transport SF CLEAR Threshold – Byte 0” register, then an SF
condition will be cleared.
174
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 107: Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 0 (Address Location=
0x113B)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_CLEAR_THRESHOLD[7:0]
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_THRESHOLD
[7:0]
R/W
DESCRIPTION
SF_CLEAR_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the “Receive
STS-3 Transport – SF CLEAR Threshold – Byte 1” registers
permit the user to specify the upper limit for the number of B2
bit errors that will cause the Receive STS-3 TOH Processor
block to clear the SF (Signal Failure) condition.
When the Receive STS-3 TOH Processor block is checking for
clearing SF, it will accumulate B2 errors for a total of 8 CLEAR
Sub-Interval periods. If the number of accumulated B2 errors
is less than that programmed into this and the “Receive STS-3
Transport SF CLEAR Threshold – Byte 1” register, then an SF
condition will be cleared.
Table 108: Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 2 (Address Location=
0x113D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_SET_MONITOR_WINDOW[23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
SD_SET_MONITOR_WINDOW
[23:16]
R/W
DESCRIPTION
SD_SET_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the
“Receive STS-3 Transport – SD SET Monitor Interval –
Byte 1 and Byte 0” registers permit the user to specify
the number of STS-3 Frame periods that will constitute
a SET Sub-Interval for SD (Signal Degrade)
declaration.
When the Receive STS-3 TOH Processor block is
checking for SD, it will accumulate B2 bit errors for a
total of 8 SET Sub-Interval periods. If the number of
accumulated B2 bit errors exceeds that of programmed
into the “Receive STS-3 Transport SD SET Threshold”
register, then an SD condition will be declared.
175
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 109: Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 1 (Address Location=
0x113E)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
SD_SET_MONITOR_WINDOW[15:8]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
SD_SET_MONITOR_WINDOW[15:8]
R/W
SD_SET_MONITOR_INTERVAL – Bits 15 through 8:
These READ/WRITE bits, along the contents of the
“Receive STS-3 Transport – SD SET Monitor Interval –
Byte 2 and Byte 0” registers permit the user to specify
the number of STS-3 Frame periods that will constitute
a SET Sub-Interval for SD (Signal Degrade)
declaration.
When the Receive STS-3 TOH Processor block is
checking for SD, it will accumulate B2 bit errors for a
total of 8 SET Sub-Interval periods. If the number of
accumulated B2 bit errors exceeds that of programmed
into the “Receive STS-3 Transport SD SET Threshold”
register, then an SD condition will be declared.
Table 110: Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 0 (Address Location=
0x113F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_SET_MONITOR_WINDOW[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
SD_SET_MONITOR_WINDOW[
7:0]
R/W
DESCRIPTION
SD_SET_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Receive STS-3 Transport – SD SET Monitor Interval –
Byte 2 and Byte 1” registers permit the user to specify the
number of STS-3 Frame periods that will constitute a SET
Sub-Interval for SD (Signal Degrade) declaration.
When the Receive STS-3 TOH Processor block is
checking for SD, it will accumulate B2 bit errors for a total
of 8 SET Sub-Interval periods.
If the number of
accumulated B2 bit errors exceeds that of programmed
into the “Receive STS-3 Transport SD SET Threshold”
register, then an SD condition will be declared.
176
XRT94L33
333---C
C
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 111: Receive STS-3 Transport – Receive SD SET Threshold – Byte 1 (Address Location=
0x1142)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SD_SET_THRESHOLD[15:8]
BIT NUMBER
NAME
TYPE
7-0
SD_SET_THRESHOLD[15:8]
R/W
DESCRIPTION
SD_SET_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the “Receive
STS-3 Transport – SD SET Threshold – Byte 0” registers
permit the user to specify the number of B2 bit errors that will
cause the Receive STS-3 TOH Processor block to declare an
SD (Signal Degrade) condition.
When the Receive STS-3 TOH Processor block is checking for
SD, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors
exceeds that of programmed into this and the “Receive STS-3
Transport SD SET Threshold – Byte 0” register, then an SD
condition will be declared.
Table 112: Receive STS-3 Transport – Receive SD SET Threshold – Byte 0 (Address Location=
0x1143)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_SET_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_SET_THRESHOLD[7:0]
R/W
DESCRIPTION
SD_SET_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the “Receive
STS-3 Transport – SD SET Threshold – Byte 1” registers
permit the user to specify the number of B2 bit errors that will
cause the Receive STS-3 TOH Processor block to declare an
SD (Signal Degrade) condition.
When the Receive STS-3 TOH Processor block is checking for
SD, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors
exceeds that of programmed into this and the “Receive STS-3
Transport SD SET Threshold – Byte 1” register, then an SD
condition will be declared.
177
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A
N
N
E
L
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S
T
S
T
O
S
T
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M---111 M
MA
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PP
PE
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AT
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RE
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GIIIS
ST
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S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 113: Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 1 (Address Location=
0x1146)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SD_CLEAR_THRESHOLD[15:8]
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_THRESHOLD[15:8]
R/W
DESCRIPTION
SD_CLEAR_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the
“Receive STS-3 Transport – SD CLEAR Threshold – Byte 0”
registers permit the user to specify the upper limit for the
number of B2 bit errors that will cause the Receive STS-3
TOH Processor block to clear the SD (Signal Degrade)
condition.
When the Receive STS-3 TOH Processor block is checking
for clearing SD, it will accumulate B2 errors for a total of 8
CLEAR Sub-Interval periods. If the number of accumulated
B2 errors is less than that programmed into this and the
“Receive STS-3 Transport SD CLEAR Threshold – Byte 0”
register, then an SD condition will be cleared.
Table 114: Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 1 (Address Location=
0x1147)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_THRESHOLD[7:0]
R/W
DESCRIPTION
SD_CLEAR_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the “Receive
STS-3 Transport – SD CLEAR Threshold – Byte 1” registers
permit the user to specify the upper limit for the number of B2
bit errors that will cause the Receive STS-3 TOH Processor
block to clear the SD (Signal Degrade) condition.
When the Receive STS-3 TOH Processor block is checking for
clearing SD, it will accumulate B2 errors for a total of 8 CLEAR
Sub-Interval periods. If the number of accumulated B2 errors
is less than that programmed into this and the “Receive STS-3
Transport SD CLEAR Threshold – Byte 1” register, then an SD
condition will be cleared.
178
XRT94L33
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A
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P
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A
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T
E
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NN
NE
EL
LD
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S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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Rev222...000...000
Table 115: Receive STS-3 Transport – Force SEF Condition Register (Address Location= 0x114B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SEF FORCE
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–1
Unused
R/O
0
SEF FORCE
R/W
DESCRIPTION
SEF Force:
This READ/WRITE bit-field permits the user to force the Receive STS-3
TOH Processor block to declare an SEF defect. The Receive STS-3 TOH
Processor block will then attempt to reacquire framing.
Writing a “1” into this bit-field configures the Receive STS-3 TOH Processor
block to declare the SEF defect. The Receive STS-3 TOH Processor block
will automatically set this bit-field to “0” once it has reacquired framing (e.g.,
has detected two consecutive STS-3 frames with the correct A1 and A2
bytes).
Table 116: Receive STS-3 Transport – Receive J0 Trace Buffer Control Register (Address Location=
0x114F)
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
BIT 2
READ SEL
ACCEPT
THRD
MSG TYPE
BIT 1
BIT 0
MSG LENGTH
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–5
Unused
R/O
4
READ SEL
R/W
DESCRIPTION
Receive Section Trace (J0) Message Buffer Read Selection:
This READ/WRITE bit-field permits a user to specify which of the following
buffer segments to read.
a.
Valid Message Buffer
b.
Expected Message Buffer
0 – Executing a READ to the Receive Section Trace (J0) Message Buffer, will
return contents within the “Valid Message” buffer.
1 – Executing a READ to the Receive Section Trace (J0) Message Buffer, will
return contents within the “Expected Message Buffer”.
Note:
3
ACCEPT THRD
R/W
In the case of the Receive STS-3 TOH Processor block, the “Receive
J0 Trace Buffer” is located at Address location 0x1300 through
0x133F.
Message Accept Threshold:
This READ/WRITE bit-field permits a user to select the number of consecutive
times that the Receive STS-3 TOH Processor block must receive a given
179
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Section Trace Message, before it is accepted, as described below.
0 – The Receive STS-3 TOH Processor block accepts the Section Message
after it has received it the third time in succession.
1 – The Receive STS-3 TOH Processor block accepts the Section Message
after it has received in the fifth time in succession.
2
MSG TYPE
R/W
Message Alignment Type:
This READ/WRITE bit-field permits a user to specify how the Receive STS-3
TOH Processor block will locate the boundary of the incoming Section Trace
Message, as indicated below.
0 – The Section Trace Message boundary is indicated by “Line Feed”.
1 – The Section Trace Message boundary is indicated by the presence of a “1”
in the MSB of a the first byte (within the J0 Trace Message).
1-0
MSG LENGTH
R/W
J0 Message Length:
These READ/WRITE bit-fields permit the user to specify the length of the J0
Trace Message, that the Receive STS-3 TOH Processor block will receive.
The relationship between the content of these bit-fields and the corresponding
J0 Trace Message Length is presented below.
MSG LENGTH
Resulting J0 Trace Message Length
00
1 Byte
01
16 Bytes
10/11
64 Bytes
180
XRT94L33
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M
M
A
P
P
E
R
A
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M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
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RS
S
Rev222...000...000
Table 117: Receive STS-3 Transport – Receive SD Burst Error Tolerance – Byte 1 (Address Location=
0x1152)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
1
1
1
SD_BURST_TOLERANCE[15:8]
BIT NUMBER
NAME
TYPE
7-0
SD_BURST_TOLERANCE
[15:8]
R/W
DESCRIPTION
SD_BURST_TOLERANCE – MSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-3 Transport – SD BURST Tolerance – Byte 0”
registers permit the user to specify the maximum number of B2
bit errors that the Receive STS-3 TOH Processor block can
accumulate during a single Sub-Interval period (e.g., an STS-3
frame period), when determining whether or not to declare an SD
(Signal Degrade) defect condition.
Note:
The purpose of this feature is to permit the user to
provide some level of B2 error burst filtering, when the
Receive STS-3 TOH Processor block is accumulating
B2 byte errors in order to declare the SD defect
condition. The user can implement this feature in order
to configure the Receive STS-3 TOH Processor block
to detect B2 bit errors in multiple “Sub-Interval” periods
before it will declare the SD defect condition.
Table 118: Receive STS-3 Transport – Receive SD Burst Error Tolerance – Byte 0 (Address Location=
0x1153)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SD_BURST_TOLERANCE[7:0]
BIT NUMBER
NAME
TYPE
7-0
SD_BURST_TOLERANCE
[7:0]
R/W
DESCRIPTION
SD_BURST_TOLERANCE – LSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-3 Transport – SD BURST Tolerance – Byte 1”
registers permit the user to specify the maximum number of B2
bit errors that the Receive STS-3 TOH Processor block can
accumulate during a single Sub-Interval period (e.g., an STS-3
frame period), when determining whether or not to declare an SD
(Signal Degrade) defect condition.
Note:
The purpose of this feature is to permit the user to
provide some level of B2 error burst filtering, when the
Receive STS-3 TOH Processor block is accumulating
B2 byte errors in order to declare the SD defect
condition. The user can implement this feature in order
to configure the Receive STS-3 TOH Processor block
to detect B2 bit errors in multiple “Sub-Interval” periods
before it will declare the SD defect condition.
Table 119: Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 1 (Address Location=
0x1156)
181
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A
N
N
E
L
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S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Rev222...000...000
BIT 2
BIT 1
BIT 0
SF_BURST_TOLERANCE[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_BURST_TOLERANCE[15:8]
R/W
DESCRIPTION
SF_BURST_TOLERANCE – MSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-3 Transport – SF BURST Tolerance – Byte 0”
registers permit the user to specify the maximum number of
B2 bit errors that the Receive STS-3 TOH Processor block
can accumulate during a single Sub-Interval period (e.g., an
STS-3 frame period), when determining whether or not to
declare an SF (Signal Failure) defect condition.
Note:
182
The purpose of this feature is to permit the user to
provide some level of B2 error burst filtering, when
the Receive STS-3 TOH Processor block is
accumulating B2 byte errors in order to declare
the SF defect condition. The user can implement
this feature in order to configure the Receive STS3 TOH Processor block to detect B2 bit errors in
multiple “Sub-Interval” periods before it will
declare the SF defect condition.
XRT94L33
333---C
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A
N
N
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S
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S
T
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S
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S
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M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 120: Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 0 (Address Location=
0x1157)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_BURST_TOLERANCE[7:0]
BIT NUMBER
NAME
TYPE
7-0
SF_BURST_TOLERANCE[7:0]
R/W
DESCRIPTION
SF_BURST_TOLERANCE – LSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-3 Transport – SF BURST Tolerance – Byte 1”
registers permit the user to specify the maximum number of
B2 bit errors that the Receive STS-3 TOH Processor block can
accumulate during a single Sub-Interval period (e.g., an STS-3
frame period), when determining whether or not to declare an
SF (Signal Failure) defect condition.
Note:
The purpose of this feature is to permit the user to
provide some level of B2 error burst filtering, when
the Receive STS-3 TOH Processor block is
accumulating B2 byte errors in order to declare the
SF defect condition. The user can implement this
feature in order to configure the Receive STS-3 TOH
Processor block to detect B2 bit errors in multiple
“Sub-Interval” periods before it will declare the SF
defect condition.
Table 121: Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 2 (Address Location=
0x1159)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_MONITOR_WINDOW[23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_MONITOR_
WINDOW[23:16]
R/W
DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-3 Transport – SD Clear Monitor Interval – Byte
1 and Byte 0” registers permit the user to specify the number
of STS-3 Frame periods that will constitute a CLEAR SubInterval for SD (Signal Degrade).
When the Receive STS-3 TOH Processor block is checking for
clearing the SD defect, it will accumulate B2 errors for a total
of 8 SET Sub-Interval periods. If the number of accumulated
B2 errors is less than that of programmed into the “Receive
STS-3 Transport SD Clear Threshold” register, then the SD
defect will be cleared.
Table 122: Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1 (Address Location=
0x115A)
183
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Rev222...000...000
BIT 2
BIT 1
BIT 0
SD_CLEAR_MONITOR_WINDOW[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_MONITOR_WINDOW[15:8]
R/W
DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL
through 8:
–
Bits
15
These READ/WRITE bits, along with the contents of
the “Receive STS-3 Transport – SD Clear Monitor
Interval – Byte 2 and Byte 0” registers permit the
user to specify the number of STS-3 Frame periods
that will constitute a CLEAR Sub-Interval for SD
(Signal Degrade).
When the Receive STS-3 TOH Processor block is
checking for clearing the SD defect, it will
accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2
errors is less than that of programmed into the
“Receive STS-3 Transport SD Clear Threshold”
register, then the SD defect will be cleared.
Table 123: Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0 (Address Location=
0x115B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_MONITOR_WINDOW[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_MONITOR_WINDOW[
7:0]
R/W
DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-3 Transport – SD Clear Monitor Interval –
Byte 2 and Byte 1” registers permit the user to specify the
number of STS-3 Frame periods that will constitute a
CLEAR Sub-Interval for SD (Signal Degrade).
When the Receive STS-3 TOH Processor block is
checking for clearing the SD defect, it will accumulate B2
errors for a total of 8 SET Sub-Interval periods. If the
number of accumulated B2 errors is less than that of
programmed into the “Receive STS-3 Transport SD Clear
Threshold” register, then the SD defect will be cleared.
Table 124: Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2 (Address Location=
0x115D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
SF_CLEAR_MONITOR_WINDOW[23:16]
184
BIT 1
BIT 0
XRT94L33
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P
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A
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M
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S
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E
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S
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HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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ER
RS
S
Rev222...000...000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_MONITOR_WINDO
W [23:16]
R/W
DESCRIPTION
SF_CLEAR_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-3 Transport – SF Clear Monitor Interval –
Byte 1 and Byte 0” registers permit the user to specify the
number of STS-3 Frame periods that will constitute a
CLEAR Sub-Interval for SF (Signal Failure).
When the Receive STS-3 TOH Processor block is checking
for clearing the SF defect, it will accumulate B2 errors for a
total of 8 SET Sub-Interval periods. If the number of
accumulated B2 errors is less than that of programmed into
the “Receive STS-3 Transport SF Clear Threshold” register,
then the SF defect will be cleared.
Table 125: Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1 (Address Location=
0x115E)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_CLEAR_MONITOR_WINDOW[15:8]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
SF_CLEAR_MONITOR_WINDOW
[15:8]
R/W
SF_CLEAR_MONITOR_INTERVAL – Bits 15 through
8:
These READ/WRITE bits, along with the contents of
the “Receive STS-3 Transport – SF Clear Monitor
Interval – Byte 2 and Byte 0” registers permit the user
to specify the number of STS-3 Frame periods that will
constitute a CLEAR Sub-Interval for SF (Signal
Failure).
When the Receive STS-3 TOH Processor block is
checking for clearing the SF defect, it will accumulate
B2 errors for a total of 8 SET Sub-Interval periods. If
the number of accumulated B2 errors is less than that
of programmed into the “Receive STS-3 Transport SF
Clear Threshold” register, then the SF defect will be
cleared.
Table 126: Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 0 (Address Location=
0x115F)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_CLEAR_MONITOR_WINDOW[7:0]
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BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_MONITOR_WINDOW
[7:0]
R/W
Rev222...000...000
DESCRIPTION
SF_CLEAR_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along with the contents of
the “Receive STS-3 Transport – SF Clear Monitor
Interval – Byte 2 and Byte 1” registers permit the user
to specify the number of STS-3 Frame periods that will
constitute a CLEAR Sub-Interval for SF (Signal
Failure).
When the Receive STS-3 TOH Processor block is
checking for clearing the SF defect, it will accumulate
B2 errors for a total of 8 SET Sub-Interval periods. If
the number of accumulated B2 errors is less than that
of programmed into the “Receive STS-3 Transport SF
Clear Threshold” register, then the SF defect will be
cleared.
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Table 127: Receive STS-3 Transport – Auto AIS Control Register (Address Location= 0x1163)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit
AIS-P
(Downstream)
Upon J0
Message
Unstable
Transmit
AIS-P
(Downstream)
Upon J0
Message
Mismatch
Transmit
AIS-P
(Downstream)
Upon SF
Transmit
AIS-P
(Downstream)
Upon SD
Transmit
AIS-P
(Downstream)
upon Loss
of Optical
Carrier AIS
Transmit
AIS-P
(Downstream)
upon LOF
Transmit
AIS-P
(Downstream)
upon LOS
Transmit
AIS-P
(Downstream)
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
7
NAME
TYPE
Transmit AIS-P
(Down-stream)
upon J0 Message
Unstable
R/W
DESCRIPTION
Transmit Path AIS upon Detection of Unstable Section Trace (J0):
This READ/WRITE bit-field permits the user to configure the Receive
STS-3 TOH Processor block to automatically transmit a Path AIS (AISP) Indicator via the “downstream” traffic (e.g., towards the Receive
SONET POH Processor blocks), anytime it detects an Unstable Section
Trace (J0) condition in the “incoming” STS-3 data-stream.
0 – Does not configure the Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator (via the “downstream” traffic)
whenever it detects an “Unstable Section Trace” condition.
1 – Configures the Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator (via the “downstream” traffic)
whenever it detects an “Unstable Section Trace” condition.
Note:
6
Transmit AIS-P
(Down-stream)
Upon J0 Message
Mismatch
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator, in response to this
defect condition.
Transmit Path AIS (AIS-P) upon Detection of Section Trace (J0)
Message Mismatch:
This READ/WRITE bit-field permits the user to configure the Receive
STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P)
Indicator via the “downstream” traffic (e.g., towards the Receive SONET
POH Processor blocks), anytime it detects a Section Trace (J0) Message
Mismatch condition in the “incoming” STS-3 data stream.
0 – Does not configure the Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator (via the “downstream” traffic)
whenever it detects a “Section Trace Message Mismatch” condition.
1 – Configures the Receive STS-3 TOH Processor block to transmit the
AIS-P indicator (via the “downstream” traffic) whenever it detects a
“Section Trace Message Mismatch” condition.
Note:
5
Transmit AIS-P
(Down-stream) upon
SF
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator, in response to this
defect condition.
Transmit Path AIS upon Signal Failure (SF):
This READ/WRITE bit-field permits the user to configure the Receive
STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P)
Indicator via the “downstream” traffic (e.g., towards the Receive SONET
POH Processor blocks), anytime it declares an SF condition.
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Rev222...000...000
0 – Does not configure the Receive STS-3 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the SF defect.
1 – Configures the Receive STS-3 TOH Processor block to transmit the
AIS-P indicator (via the “downstream” traffic) upon declaration of the SF
defect.
Note:
4
Transmit AIS-P
(Down-stream) upon
SD
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator, in response to this
defect condition.
Transmit Path AIS upon Signal Degrade (SD):
This READ/WRITE bit-field permits the user to configure the Receive
STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P)
Indicator via the “downstream” traffic (e.g., towards the Receive SONET
POH Processor blocks), anytime it declares an SD condition.
0 – Does not configure the Receive STS-3 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the SD defect.
1 – Configures the Receive STS-3 TOH Processor block to transmit the
AIS-P indicator (via the “downstream” traffic) upon declaration of the SD
defect.
Note:
3
Transmit AIS-P
(Down-stream) upon
Loss of Optical
Carrier
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator, in response to this
defect condition.
Transmit Path AIS upon Loss of Optical Carrier condition:
This READ/WRITE bit-field permits the user to configure the Receive
STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P)
Indicator via the “downstream” traffic (e.g., towards the Receive SONET
POH Processor blocks), anytime it detects a “Loss of Optical Carrier”
condition.
0 – Does not configure the Receive STS-3 TOH Processor block to
transmit the AIS-P indicator upon detection of a “Loss of Optical Carrier”
condition.
1 – Configures the Receive STS-3 TOH Processor block to transmit the
AIS-P indicator upon detection of a “Loss of Optical Carrier” condition.
Note:
2
Transmit AIS-P
(Down-stream) upon
LOF
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator, in response to this
defect condition.
Transmit Path AIS upon Loss of Frame (LOF):
This READ/WRITE bit-field permits the user to configure the Receive
STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P)
Indicator via the “downstream” traffic (e.g., towards the Receive SONET
POH Processor block), anytime it declares an LOF condition.
0 – Does not configure the Receive STS-3 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the LOF defect.
1 – Configures the Receive STS-3 TOH Processor block to transmit the
AIS-P indicator (via the “downstream” traffic) upon declaration of the LOF
defect.
Note:
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Receive STS-3 TOH Processor block to
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Rev222...000...000
automatically transmit the AIS-P indicator, in response to this
defect condition.
1
Transmit AIS-P
(Down-stream) upon
LOS
R/W
Transmit Path AIS upon Loss of Signal (LOS):
This READ/WRITE bit-field permits the user to configure the Receive
STS-3 TOH Processor block to automatically transmit a Path AIS (AIS-P)
Indicator via the “downstream” traffic (e.g., towards the Receive SONET
POH Processor block), anytime it declares an LOS condition.
0 – Does not configure the Receive STS-3 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) anytime it
declares the LOS defect.
1 – Configures the Receive STS-3 TOH Processor block to transmit the
AIS-P indicator (via the “downstream” traffic) anytime it declares the LOS
defect.
Note:
0
Transmit AIS-P
(Down-stream)
Enable
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator, in response to this
defect condition.
Automatic Transmission of AIS-P Enable:
This READ/WRITE bit-field serves two purposes.
It permits the user to configure the Receive STS-3 TOH Processor block
to automatically transmit the Path AIS (AIS-P) indicator, via the downstream traffic (e.g., towards the Receive SONET POH Processor blocks),
upon detection of an SF, SD, Section Trace Mismatch, Section Trace
Unstable, LOF, LOS or Loss of Optical Carrier conditions.
It also permits the user to configure the Receive STS-3 TOH Processor
block to automatically transmit a Path AIS (AIS-P) Indicator via the
“downstream” traffic (e.g., towards the Receive SONET POH Processor
blocks) anytime it detects an AIS-L condition in the “incoming “ STS-3
data-stream.
0 – Configures the Receive STS-3 TOH Processor block to NOT
automatically transmit the AIS-P indicator (via the “downstream” traffic)
upon detection of the AIS-L or any of the “above-mentioned” conditions.
1 – Configures the Receive STS-3 TOH Processor block to automatically
transmit the AIS-P indicator (via the “downstream” traffic) upon detection
of any of the “above-mentioned” condition.
Note:
The user must also set the corresponding bit-fields (within this
register) to “1” in order to configure the Receive STS-3 TOH
Processor block to automatically transmit the AIS-P indicator
upon detection of a given alarm/defect condition.
189
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Rev222...000...000
Table 128: Receive STS-3 Transport – Serial Port Control Register (Address Location= 0x1167)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
RxTOH_CLOCK_SPEED[7:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7-4
Unused
R/O
3-0
RxTOH_CLOCK_SPEED[7:0]
R/W
DESCRIPTION
RxTOHClk Output Clock Signal Speed:
These READ/WRITE bit-fields permit the user to specify the
frequency of the “RxTOHClk output clock signal.
The formula that relates the contents of these register bits to
the “RxTOHClk” frequency is presented below.
FREQ = 19.44 /[2 * (RxTOH_CLOCK_SPEED + 1)
Note:
For STS-3/STM-1 applications, the frequency of the
RxTOHClk output signal must be in the range of
0.6075MHz to 9.72MHz
Table 129: Receive STS-3 Transport – Auto AIS (in Downstream STS-1s) Control Register (Address
Location= 0x116B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Unused
Transmit
AIS-P (via
Downstream
STS-1s)
upon LOS
Transmit
AIS-P (via
Downstream
STS-1s)
upon LOF
Transmit
AIS-P (via
Downstream
STS-1s)
upon SD
Transmit
AIS-P (via
Downstream
STS-1s)
upon SF
AIS-L
Output
Enable
Transmit
AIS-P (via
Downstream
STS-1s)
Enable
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7-6
Unused
R/O
5
Transmit AIS-P (via
Downstream STS-1s)
upon LOS
R/W
DESCRIPTION
Transmit AIS-P (via Downstream STS-1s) upon LOS (Loss of
Signal):
This READ/WRITE bit-field permits the user to configure the Transmit
STS-1 POH Processor blocks (in each channel) to automatically transmit
the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals,
anytime the Receive STS-3 TOH Processor block declares the LOS
defect.
0 – Does not configure all “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signals, anytime the Receive STS-3 TOH Processor block
declares the LOS defect.
1 – Configures all “activated” Transmit STS-1POH Processor blocks to
190
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S
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S
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S
S
T
M
M
A
P
P
E
R
A
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M
R
E
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S
T
E
R
S
CH
HA
AN
NN
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LD
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S333///E
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TS
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ST
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M---111 M
MA
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AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
automatically transmit the AIS-P Indicator via the “downstream” STS-1
signals, anytime the Receive STS-3 TOH Processor block declares the
LOS defect.
Note:
1. In the “long-run” the function of this bit-field is exactly the same as that
of Bit 1 (Transmit AIS-P Down-stream – Upon LOS), within the Receive
STS-3 Transport – Auto AIS Control Register (Address Location=
0x1163). The only difference is that this register bit will cause each of
the “downstream” Transmit STS-1 POH Processor blocks to
IMMEDIATELY begin to transmit the AIS-P condition whenever the
Receive STS-3 TOH Processor block declares the LOS defect. This will
permit the user to easily comply with the Telcordia GR-253-CORE
requirements of an NE transmitting the AIS-P indicator downstream
within 125us of the NE declaring the LOS defect.
2. In the case of Bit 1 (Transmit AIS-P Downstream – Upon LOS),
several SONET frame periods are required (after the Receive STS-3
TOH Processor block has declared the LOS defect), before the Transmit
STS-1 POH Processor blocks will begin the process of transmitting the
AIS-P indicators.
3. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
4
Transmit AIS-P (via
Downstream STS-1s)
upon LOF
R/W
Transmit AIS-P (via Downstream STS-1s) upon LOF (Loss of
Frame):
This READ/WRITE bit-field permits the user to configure the Transmit
STS-1 POH Processor blocks (in each channel) to automatically transmit
the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals,
anytime the Receive STS-3 TOH Processor block declares the LOF
defect.
0 – Does not configures all “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signals, anytime the Receive STS-3 TOH Processor block
declares the LOF defect.
1 – Configures all “activated” Transmit STS-1POH Processor blocks to
automatically transmit the AIS-P Indicator via the “downstream” STS-1
signals, anytime the Receive STS-3 TOH Processor block declares the
LOF defect.
Note:
1. In the “long-run” the function of this bit-field is exactly the same as that
of Bit 2 (Transmit AIS-P Down-stream – Upon LOF), within the Receive
STS-3 Transport – Auto AIS Control Register (Address Location=
0x1163). The only difference is that this register bit will cause each of
the “downstream” Transmit STS-1 POH Processor blocks to
IMMEDIATELY begin to transmit the AIS-P condition whenever the
Receive STS-3 TOH Processor block declares the LOF defect. This will
permit the user to easily comply with the Telcordia GR-253-CORE
requirements of an NE transmitting the AIS-P indicator downstream
within 125us of the NE declaring the LOF defect.
2. In the case of Bit 2 (Transmit AIS-P Downstream – Upon LOF),
several SONET frame periods are required (after the Receive STS-3
TOH Processor block has declared the LOS defect), before the Transmit
STS-1 POH Processor blocks will begin the process of transmitting the
AIS-P indicators.
3. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
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N
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S
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MA
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PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
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S
CH
HA
AN
NN
NE
EL
LD
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S333///E
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TS
S---333///S
ST
3
Transmit AIS-P (via
Downstream STS-1s)
upon SD
R/W
Rev222...000...000
Transmit AIS-P (via Downstream STS-1s) upon SD (Signal Degrade):
This READ/WRITE bit-field permits the user to configure the Transmit
STS-1 POH Processor blocks (in each channel) to automatically transmit
the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals,
anytime the Receive STS-3 TOH Processor block declares the SD
defect.
0 – Does not configures all “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signals, anytime the Receive STS-3 TOH Processor block
declares the SD defect.
1 – Configures all “activated” Transmit STS-1POH Processor blocks to
automatically transmit the AIS-P Indicator via the “downstream” STS-1
signals, anytime the Receive STS-3 TOH Processor block declares the
SD defect.
Note:
1. In the “long-run” the function of this bit-field is exactly the same as that
of Bit 4 (Transmit AIS-P Down-stream – Upon SD), within the Receive
STS-3 Transport – Auto AIS Control Register (Address Location=
0x1163). The only difference is that this register bit will cause each of
the “downstream” Transmit STS-1 POH Processor blocks to
IMMEDIATELY begin to transmit the AIS-P condition whenever the
Receive STS-3 TOH Processor block declares the SD defect. This will
permit the user to easily comply with the Telcordia GR-253-CORE
requirements of an NE transmitting the AIS-P indicator downstream
within 125us of the NE declaring the LOS defect.
2. In the case of Bit 1 (Transmit AIS-P Downstream – Upon LOF),
several SONET frame periods are required (after the Receive STS-3
TOH Processor block has declared the SD defect), before the Transmit
STS-1 POH Processor blocks will begin the process of transmitting the
AIS-P indicators.
3. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
2
Transmit AIS-P (via
Downstream STS-1s)
upon SF
R/W
Transmit AIS-P (via Downstream STS-1s) upon Signal Failure (SF):
This READ/WRITE bit-field permits the user to configure the Transmit
STS-1 POH Processor blocks (in each channel) to automatically transmit
the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals,
anytime the Receive STS-3 TOH Processor block declares an SF
condition.
0 – Does not configures all “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signals, anytime the Receive STS-3 TOH Processor block
declares the SF defect.
1 – Configures all “activated” Transmit STS-1POH Processor blocks to
automatically transmit the AIS-P Indicator via the “downstream” STS-1
signals, anytime the Receive STS-3 TOH Processor block declares the
SF defect.
1. In the “long-run” the function of this bit-field is exactly the same as that
of Bit 5 (Transmit AIS-P Down-stream – Upon SF), within the Receive
STS-3 Transport – Auto AIS Control Register (Address Location=
0x1163). The only difference is that this register bit will cause each of
the “downstream” Transmit STS-1 POH Processor blocks to
IMMEDIATELY begin transmit the AIS-P condition whenever the Receive
STS-3 TOH Processor block declares the SF defect. This will permit the
user to easily comply with the Telcordia GR-253-CORE requirements of
an NE transmitting the AIS-P indicator downstream within 125us of the
192
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NE declaring the SF defect.
2. In the case of Bit 5 (Transmit AIS-P Downstream – Upon SF), several
SONET frame periods are required (after the Receive STS-3 TOH
Processor block has declared the SF defect), before the Transmit STS-1
POH Processor blocks will begin the process of transmitting the AIS-P
indicators.
3. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
1
AIS-L Output Enable
R/W
AIS-L Output Enable:
This READ/WRITE bit-field, along with Bits 7 (8kHz or STUFF Out
Enable) within the “Operation Output Control Register – Byte 1” (Address
Location= 0x0150) permit the user to configure the “AIS-L” indicator to be
output via the “LOF” output pin (pin AD11).
If Bit 7 (within the “Operation Output Control Register – Byte 1”) is set to
“0”, then setting this bit-field to “1” configures pin AD11 to function as the
AIS-L output indicator.
If Bit 7 (within the “Operation Output Control Register – Byte 1”) is set to
“0”, then setting this bit-field to “0” configures pin AD11 to function as the
LOF output indicator.
If Bit 7 (within the “Operation Output Control Register – Byte 1) is set to
“1”, then this register bit is ignored.
0
Transmit AIS-P (via
Downstream STS-1s)
Enable
R/W
Automatic Transmission of AIS-P (via the downstream STS-1s)
Enable:
This READ/WRITE bit-field permits the user to configure all “activated”
Transmit STS-1 POH Processor blocks to automatically transmit the AISP indicator, via its “outbound” STS-1 signals, upon detection of an SF,
SD, LOS and LOF condition.
0 – Does not configure the “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P indicator, whenever the
Receive STS-3 TOH Processor block declares either the LOS, LOF, SD
or SF defects.
1 – Configures the “activated” Transmit STS-1 POH Processor blocks to
automatically transmit the AIS-P indicator, whenever the Receive STS-3
TOH Processor block declares either the LOS, LOF, SD or SF defects.
193
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1.6
Rev222...000...000
TRANSMIT STS-3 TOH PROCESSOR BLOCK
The register map for the Transmit STS-3 TOH Processor Block is presented in the Table below. Additionally,
a detailed description of each of the “Transmit STS-3 TOH Processor” block registers is presented below.
In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the
XRT94L33, with the “Transmit STS-3 TOH Processor Block “highlighted” is presented below in Figure 7
Figure 7: Illustration of the Functional Block Diagram of the XRT94L33, with the Transmit STS-3 TOH
Processor Block “High-lighted”.
From Channels 1 & 2
Tx
Tx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Rx
Rx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Clock
Clock
Synthesizer
Synthesizer
Block
Block
Tx
TxCell
Cell
Processor
Processor
Block
Block
Tx
TxPLCP
PLCP
Processor
Processor
Block
Block
Tx
TxPPP
PPP
Processor
Processor
Block
Block
Tx
TxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Tx
TxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Tx
TxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxPPP
PPP
Processor
Processor
Block
Block
Rx
RxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
RxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Rx
RxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxCell
Cell
Processor
Processor
Block
Block
Rx
RxPLCP
PLCP
Processor
Processor
Block
Block
Channel 0
To Channel 1 & 2
194
Tx
TxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
Tx
TxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Tx
TxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Rx
RxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Clock
Clock&&
Data
Data
Recovery
Recovery
Block
Block
Rx
RxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Rx
RxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
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1.6.1
TRANSMIT STS-3 TOH PROCESSOR BLOCK REGISTER
Table 130: Transmit STS-3 TOH Processor Block Registers – Address Map
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x00, 0x01
0x1800 –
0x1901
0x02
REGISTER NAME
DEFAULT VALUES
Reserved
0x00
0x1902
Transmit STS-3 Transport – SONET Transmit Control
Register – Byte 1
0x00
0x03
0x1903
Transmit STS-3 Transport – SONET Transmit Control
Register – Byte 0
0x00
0x04 – 0x15
0x1904 –
0x1915
Reserved
0x00
0x16
0x1916
Reserved
0x00
0x17
0x1917
Transmit STS-3 Transport – Transmit A1 Byte Error Mask –
Low Register – Byte 0
0x00
0x18 – 0x1D
0x1918 –
0x191D
Reserved
0x00
0x1E
0x191E
Reserved
0x00
0x1F
0x191F
Transmit STS-3 Transport – Transmit A2 Byte Error Mask –
Low Register – Byte 0
0x00
0x20 – 0x22
0x1920 –
0x1921
Reserved
0x00
0x23
0x1923
Transmit STS-3 Transport – B1 Byte Error Mask Register
0x00
0x24, 0x25
0x1924 –
0x1925
Reserved
0x00
0x26
0x1926
Reserved
0x00
0x27
0x1927
Transmit STS-3 Transport – Transmit B2 Byte Error Mask
Register – Byte 0
0x00
0x28 – 0x2A
0x1928 –
0x192A
Reserved
0x00
0x2B
0x192B
Transmit STS-3 Transport – Transmit B2 Byte - Bit Error Mask
Register – Byte 0
0x00
0x2C, 0x2D
0x192C –
0x192D
Reserved
0x00
0x2E
0x192E
Transmit STS-3 Transport – K1K2 Byte (APS) Value Register
– Byte 1
0x00
0x2F
0x192F
Transmit STS-3 Transport – K1K2 Byte (APS) Value Register
– Byte 0
0x00
0x30 – 0x32
0x1930 –
0x1931
Reserved
0x00
0x33
0x1933
Transmit STS-3 Transport – RDI-L Control Register
0x00
0x34 – 0x36
0x1934 –
0x1936
Reserved
0x00
195
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EG
GIIIS
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INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x37
0x1937
0x38 – 0x3A
0x1938 –
0x193A
0x3B
0x193B
0x3C – 0x3E
0x193C –
0x193E
0x3F
0x193F
0x40 – 0x42
0x1940 –
0x1942
0x43
REGISTER NAME
Rev222...000...000
DEFAULT VALUES
Transmit STS-3 Transport – M1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3 Transport – S1 Byte Value Register
0x00
Reserved
0x00
Transmit STS-3 Transport – F1 Byte Value Register
0x00
Reserved
0x00
0x1943
Transmit STS-3 Transport – E1 Byte Value Register
0x00
0x44
0x1944
Transmit STS-3 Transport – E2 Byte Control Register
0x00
0x45
0x1945
Reserved
0x00
0x46
0x1946
Transmit STS-3 Transport – E2 Byte Pointer Register
0x00
0x47
0x1947
Transmit STS-3 Transport – E2 Byte Value Register
0x00
0x48 – 0x4A
0x1948 –
0x194A
Reserved
0x00
0x4B
0x194B
Transmit STS-3 Transport – Transmit J0 Byte Value Register
0x00
0x4C – 0x4E
0x194C –
0x194E
Reserved
0x00
0x4F
0x194F
Transmit STS-3 Transport – Transmit J0 Byte Control Register
0x00
0x50 – 0x52
0x1950 –
0x1952
Reserved
0x00
0x53
0x1953
Transmit STS-3 Transport – Serial Port Control Register
0x00
0x54 – 0xFF
0x1954 –
0x19FF
Reserved
0x00
196
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TM
M---111 M
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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Rev222...000...000
1.6.2
TRANSMIT STS-3 TOH PROCESSOR BLOCK REGISTER DESCRIPTION
Table 131: Transmit STS-3 Transport – SONET Transmit Control Register – Byte 1 (Address Location=
0x1902)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
STS-N
Overhead
Insert
E2 Insert
Method
E1 Insert
Method
F1 Insert
Method
S1 Insert
Method
K1K2 Insert
Method
M0M1 Insert
Method[1]
R/O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6
STS-N Overhead
Insert
R/W
DESCRIPTION
STS-N Overhead Insert (Revision C Silicon Only):
This READ/WRITE bit-field permits the user to configure the TxTOH
input port to insert the TOH for all lower-tributary STS-1s within the
outbound STS-3 signal.
0 – Disables this feature. In this mode, the TxTOH input port will only
accept the TOH for the first STS-1 within the outbound STS-3 signal.
1 – Enables this feature.
5
E2 Insert Method
R/W
E2 Byte Insert Method:
This READ/WRITE bit-field permits the user to specify the source of the
contents of the E2 byte, within the “transmit” output STS-3 data stream.
0 – E2 Byte is obtained from “TxTOH” Serial Input Port.
1 – E2 Byte is obtained from the contents within the “Transmit STS-3
Transport – E2 Byte Value” register (Address Location= 0xN947). This
selection provides the user with software control over the value of the
“outbound” E2 byte.
4
E1 Insert Method
R/W
E1 Byte Insert Method:
This READ/WRITE bit-field permits the user to specify the source of the
contents of the E1 byte, within the “transmit” output STS-3 data stream.
0 – E1 Byte is obtained from “TxTOH” Serial Input Port.
1 – E1 Byte is obtained from the contents within the “Transmit STS-3
Transport – E1 Byte Value” register (Address Location= 0xN943). This
selection provides the user with software control over the value of the
“outbound” E1 byte.
3
F1 Insert Method
R/W
F1 Byte Insert Method:
This READ/WRITE bit-field permits the user to specify the source of the
contents of the F1 byte, within the “transmit” output STS-3 data stream.
0 – F1 Byte is obtained from “TxTOH” Serial Input Port.
1 – F1 Byte is obtained from the contents within the “Transmit STS-3
Transport – F1 Byte Value” register (Address Location= 0xN93F). This
selection provides the user with software control over the value of the
“outbound” F1 byte.
2
S1 Insert Method
R/W
S1 Byte Insert Method:
197
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RE
EG
GIIIS
ST
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HA
AN
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S---111 T
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S---333///S
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Rev222...000...000
This READ/WRITE bit-field permits the user to specify the source of the
contents of the S1 byte, within the “transmit” output STS-3 data stream.
0 – S1 Byte is obtained from “TxTOH” Serial Input Port.
1 – S1 Byte is obtained from the contents within the “Transmit STS-3
Transport – S1 Byte Value” register (Address Location= 0xN93B). This
selection provides the user with software control over the value of the
“outbound” S1 byte.
1
K1K2 Insert Method
R/W
K1K2 Byte Insert Method:
This READ/WRITE bit-field permits the user to specify the source of the
contents of the K1 and K2 bytes, within the “transmit” output STS-3 data
stream.
0 – K1 and K2 Bytes are obtained from “TxTOH” Serial Input Port.
1 – K1 and K2 Bytes are obtained from the contents within the “Transmit
STS-3 Transport – K1K2 Byte Value” register – Byte 1 (Address Location
= 0x192E) and the “Transmit STS-3 Transport – K1K2 Byte Value”
register – Byte 2 (Address Location= 0x192F). This selection provides
the user with software control over the value of the “outbound” K1 and K2
bytes.
0
M0M1 Insert
Method[1]
R/W
M0M1 Insert Method – Bit 1:
This READ/WRITE bit-field, along with “M0M1 Insert Method[0]” (located
in the “Transmit STS-3 Transport – SONET Control Register – Byte 0”)
permit the user to specify the source of the contents of the M0/M1 byte,
within the “transmit” output STS-3 data stream.
The relationship between these two bit-fields and the corresponding
source of the M0/M1 byte is presented below.
M0M1 Insert
Method[1:0]
Source of M0/M1 Byte
0
0
From corresponding STS-1 Receiver (B2 Error
Count)
0
1
Obtained from the contents of the “Transmit
STS-3 Transport – M0/M1 Byte Value” register
(Address Location= 0xN937).
1
0
M0/M1 byte is obtained from the “TxTOH”
Serial Input Port.
1
1
From corresponding STS-3 Receiver (B2 Error
Count).
198
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S---111 T
TO
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ST
TS
S---333///S
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TM
M---111 M
MA
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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RS
S
Rev222...000...000
Table 132: Transmit STS-3 Transport – SONET Transmit Control Register – Byte 0 (Address Location=
0x1903)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
M0M1 Insert
Method[0]
Unused
RDI-L Force
AIS-L Force
LOS
Force
Scramble
Enable
B2 Error
Insert
A1A2 Error
Insert
R/W
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
M0M1 Insert
Method[0]
R/W
DESCRIPTION
M0M1 Insert Method – Bit 0:
This READ/WRITE bit-field, along with “M0M1 Insert Method[1]”
(located in the “Transmit STS-3 Transport – SONET Control Register –
Byte 1”) permit the user to specify the source of the contents of the
M0/M1 byte, within the “transmit” output STS-3 data stream.
The relationship between these two bit-fields and the corresponding
source of the M0/M1 byte is presented below.
6
Unused
R/O
5
RDI-L Force
R/W
M0M1 Insert
Method[1:0]
Source of M0/M1 Byte
0
0
From corresponding STS-3 Receiver (B2
Error Count)
0
1
Obtained from the contents of the
“Transmit STS-3 Transport – M0/M1 Byte
Value” register (Address Location=
0xN937).
1
0
M0/M1 byte is obtained from the “TxTOH”
Serial Input Port.
1
1
From corresponding STS-3 Receiver (B2
Error Count).
Transmit Line – Remote Defect Indicator:
This READ/WRITE bit-field permits the user to (by software control)
force the Transmit STS-3 TOH Processor block to generate and
transmit the RDI-L indicator to the remote terminal equipment.
0 – Does not configure the Transmit STS-3 TOH Processor block to
generate and transmit the RDI-L indicator.
1 – Configures the Transmit STS-3 TOH Processor block to generate
and transmit the RDI-L indicator. In this case, the STS-3 Transmitter
will force bits 6, 7 and 8 (of the K2 byte) to the value “1, 1, 0”.
Note:
4
AIS-L Force
R/W
This bit-field is ignored if the Transmit STS-3 TOH Processor
block is transmitting the Line AIS (AIS-L) indicator or the LOS
pattern.
Transmit Line – AIS Indicator:
This READ/WRITE bit-field permits the user to (by software control)
force the Transmit STS-3 TOH Processor block to generate and
transmit the AIS-L indicator to the remote terminal equipment.
0 – Does not configure the Transmit STS-3 TOH Processor block to
199
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N
E
L
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M---111 M
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
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RS
S
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HA
AN
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ST
Rev222...000...000
generate and transmit the AIS-L indicator.
1 – Configures the Transmit STS-3 TOH Processor block to generate
and transmit the AIS-L indicator. In this case, the Transmit STS-3 TOH
Processor block will force all bits (within the “outbound” STS-3 frame)
with the exception of the Section Overhead Bytes to an “All Ones”
pattern.
Note:
3
LOS Force
R/W
This bit-field is ignored if the Transmit STS-3 TOH Processor
block is transmitting the LOS pattern.
Transmit LOS Pattern:
This READ/WRITE bit-field permits the user to (by software control)
force the Transmit STS-3 TOH Processor block to transmit the LOS
(Loss of Signal) pattern to the remote terminal equipment.
0 – Does not configure the Transmit STS-3 TOH Processor block to
generate and transmit the LOS pattern.
1 – Configures the Transmit STS-3 TOH Processor block to transmit the
LOS pattern. In this case, the Transmit STS-3 TOH Processor block
will force all bytes (within the “outbound” SONET frame) to an “All
Zeros” pattern.
2
Scramble Enable
R/W
Scramble Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the Scrambler, within the Transmit STS-3 TOH Processor block circuitry
0 – Disables the Scrambler.
1 – Enables the Scrambler.
1
B2 Error Insert
R/W
Transmit B2 Byte Error Insert Enable:
This READ/WRITE bit-field permits the user to configure the Transmit
STS-3 TOH Processor block to insert errors into the “outbound” B2
bytes, per the contents within the “Transmit STS-3 Transport – Transmit
B2 Byte Error Mask Registers”
0 – Configures the Transmit STS-3 TOH Processor block to NOT insert
errors into the B2 bytes, within the outbound STS-3 signal.
1 – Configures the Transmit STS-3 TOH Processor block to insert
errors into the B2 bytes (per the contents within the “Transmit B2 Byte
Error Mask Registers”).
0
A1A2 Error Insert
R/W
Transmit A1A2 Byte Error Insert Enable:
This READ/WRITE bit-field permits the user to configure the Transmit
STS-3 TOH Processor block to insert errors into the “outbound” A1 and
A2 bytes, per the contents within the “Transmit STS-3 Transport –
Transmit A1 Byte Error Mask” and Transmit A2 Byte Error Mask”
Registers.
0 – Configures the Transmit STS-3 TOH Processor block to NOT insert
errors into the A1 and A2 bytes, within the outbound STS-3 datastream.
1 – Configures the Transmit STS-3 TOH Processor block to insert
errors into the A1 and A2 bytes (per the contents within the “Transmit
A1 Byte Error Mask” and “Transmit A2 Byte Error Mask” Registers.
Table 133: Transmit STS-3 Transport – Transmit A1 Error Mask – Low Register – Byte 0 (Address
Location= 0x1917)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
200
BIT 2
BIT 1
BIT 0
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A1 Error in
STS-1
Channel 2
A1 Error in
STS-1
Channel 1
A1 Error in
STS-1
Channel 0
R/O
R/O
R/O
R/O
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-3
Unused
R/O
2
A1 Error in STS-1
Channel # 2
R/W
DESCRIPTION
A1 Error in STS-1 Channel # 2:
This READ/WRITE bit-field permits the user to configure the Transmit
STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1
Channel 2.
0 – Configures the Transmit STS-3 TOH Processor block to NOT
transmit an erred A1 byte, within STS-1 Channel 2.
1 – Configures the Transmit STS-3 TOH Processor block to transmit
an erred A1 byte, within STS-1 Channel 2.
Note:
1
A1 Error in STS-1
Channel # 1
R/W
This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the
“Transmit STS-3 Transport – SONET Transmit Control
Register – Byte 0 (Address Location= 0x1903) to “1”.
A1 Error in STS-1 Channel # 1:
This READ/WRITE bit-field permits the user to configure the Transmit
STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1
Channel 1.
0 – Configures the Transmit STS-3 TOH Processor block to NOT
transmit an erred A1 byte, within STS-1 Channel 1.
1 – Configures the Transmit STS-3 TOH Processor block to transmit
an erred A1 byte, within STS-1 Channel 1.
Note:
0
A1 Error in STS-1
Channel # 0
R/W
This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the
“Transmit STS-3 Transport – SONET Transmit Control
Register – Byte 0 (Address Location= 0x1903) to “1”.
A1 Error in STS-1 Channel # 0:
This READ/WRITE bit-field permits the user to configure the Transmit
STS-3 TOH Processor block to transmit an erred A1 byte, within STS-1
Channel 0.
0 – Configures the Transmit STS-3 TOH Processor block to NOT
transmit an erred A1 byte, within STS-1 Channel 0.
1 – Configures the Transmit STS-3 TOH Processor block to transmit
an erred A1 byte, within STS-1 Channel 0.
Note:
This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the
“Transmit STS-3 Transport – SONET Transmit Control
Register – Byte 0 (Address Location= 0x1903) to “1”.
Table 134: Transmit STS-3 Transport – Transmit A2 Error Mask – Low Register – Byte 0 (Address
Location= 0x191F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
201
BIT 2
BIT 1
BIT 0
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A2 Error in
STS-1
Channel 2
A2 Error in
STS-1
Channel 1
A2 Error in
STS-1
Channel 0
R/O
R/O
R/O
R/O
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-3
Unused
TYPE
DESCRIPTION
R/O
2
A2 Error in
STS-1
Channel # 2
R/W
A2 Error in STS-1 Channel # 2:
This READ/WRITE bit-field permits the user to configure the Transmit STS-3
TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 2.
0 – Configures the Transmit STS-3 TOH Processor block to NOT transmit an
erred A2 byte, within STS-1 Channel 2.
1 – Configures the Transmit STS-3 TOH Processor block to transmit an erred
A2 byte, within STS-1 Channel 2.
Note:
1
A2 Error in
STS-1
Channel # 1
R/W
This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the
“Transmit STS-3 Transport – SONET Transmit Control Register –
Byte 0 (Address Location= 0x1903) to “1”.
A2 Error in STS-1 Channel # 1:
This READ/WRITE bit-field permits the user to configure the Transmit STS-3
TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 1.
0 – Configures the Transmit STS-3 TOH Processor block to NOT transmit an
erred A2 byte, within STS-1 Channel 1.
1 – Configures the Transmit STS-3 TOH Processor block to transmit an erred
A2 byte, within STS-1 Channel 1.
Note:
0
A2 Error in
STS-1
Channel # 0
R/W
This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the
“Transmit STS-3 Transport – SONET Transmit Control Register –
Byte 0 (Address Location= 0x1903) to “1”.
A2 Error in STS-1 Channel # 0:
This READ/WRITE bit-field permits the user to configure the Transmit STS-3
TOH Processor block to transmit an erred A2 byte, within STS-1 Channel 0.
0 – Configures the Transmit STS-3 TOH Processor block to NOT transmit an
erred A2 byte, within STS-1 Channel 0.
1 – Configures the Transmit STS-3 TOH Processor block to transmit an erred
A2 byte, within STS-1 Channel 0.
Note:
This bit-field is only valid if Bit 0 (A1A2 Error Insert), within the
“Transmit STS-3 Transport – SONET Transmit Control Register –
Byte 0 (Address Location= 0x1903) to “1”.
202
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Table 135: Transmit STS-3 Transport – B1 Byte Error Mask Register (Address Location= 0x1923)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Byte_Error_Mask[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
B1_Byte_Error_Mask [7:0]
R/W
DESCRIPTION
B1 Byte Error Mask[7:0]:
These READ/WRITE bit-fields permit the user to insert bit errors
into the B1 bytes, within the outbound STS-3 data stream.
The Transmit STS-3 TOH Processor block will perform an XOR
operation with the contents of the B1 byte, and this register. The
results of this calculation will be inserted into the B1 byte position
within the “outbound” STS-3 data stream. For each bit-field
(within this register) that is set to “1”, the corresponding bit,
within the B1 byte will be in error.
Note:
For normal operation, the user should set this register
to 0x00.
Table 136: Transmit STS-3 Transport – Transmit B2 Byte Error Mask Register – Byte 0 (Address
Location= 0x1927)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
B2 Error in
STS-1
Channel 2
B2 Error in
STS-1
Channel 1
B2 Error in
STS-1
Channel 0
R/O
R/O
R/O
R/O
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-3
Unused
R/O
2
B2 Error in STS-1
Channel # 2
R/W
DESCRIPTION
B2 Byte Error in STS-1 Channel # 2:
This READ/WRITE bit-field permits the user to configure the Transmit
STS-3 TOH Processor block to transmit an erred B2 byte, within STS-1
Channel 2.
If the user enables this feature, then the Transmit STS-3 TOH Processor
block will perform an XOR operation of the contents of the B2 byte
(within STS-1 Channel 2) and the contents of the “Transmit STS-3
Transport – Transmit B2 Bit Error Mask Register – Byte 0 (Address
Location= 0x192B). The results of this calculation will be written back
into the “B2 byte” position, within STS-1 Channel 2, prior to transmission
to the remote terminal.
0 – Configures the Transmit STS-3 TOH Processor block to NOT insert
errors into the B2 byte, within STS-1 Channel 2.
1 – Configures the Transmit STS-3 TOH Processor block to insert errors
into the B2 byte, within STS-1 Channel 2.
Note:
This bit-field is only valid if Bit 1 (B2 Error Insert), within the
203
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“Transmit STS-3 Transport – SONET Transmit Control
Register – Byte 0 (Address = 0x1903) to “1”.
1
B2 Error in STS-1
Channel # 1
R/W
B2 Byte Error in STS-1 Channel # 1:
This READ/WRITE bit-field permits the user to configure the Transmit
STS-3 TOH Processor block to transmit an erred B2 byte, within STS-1
Channel 1.
If the user enables this feature, then the Transmit STS-3 TOH Processor
block will perform an XOR operation of the contents of the B2 byte
(within STS-1 Channel 1) and the contents of the “Transmit STS-3
Transport – Transmit B2 Bit Error Mask Register – Byte 0 (Address
Location= 0x192B). The results of this calculation will be written back
into the “B2 byte” position, within STS-1 Channel 1, prior to transmission
to the remote terminal.
0 – Configures the Transmit STS-3 TOH Processor block to NOT insert
errors into the B2 byte, within STS-1 Channel 1.
1 – Configures the Transmit STS-3 TOH Processor block to insert errors
into the B2 byte, within STS-1 Channel 1.
Note:
0
B2 Error in STS-1
Channel # 0
R/W
This bit-field is only valid if Bit 1 (B2 Error Insert), within the
“Transmit STS-3 Transport – SONET Transmit Control
Register – Byte 0 (Address Location= 0x1903) to “1”.
B2 Byte Error in STS-1 Channel # 0:
This READ/WRITE bit-field permits the user to configure the Transmit
STS-3 TOH Processor block to transmit an erred B2 byte, within STS-1
Channel 0.
If the user enables this feature, then the Transmit STS-3 TOH Processor
block will perform an XOR operation of the contents of the B2 byte
(within STS-1 Channel 0) and the contents of the “Transmit STS-3
Transport – Transmit B2 Bit Error Mask Register – Byte 0 (Address
Location= 0x192B). The results of this calculation will be written back
into the “B2 byte” position, within STS-1 Channel 0, prior to transmission
to the remote terminal.
0 – Configures the Transmit STS-3 TOH Processor block to NOT insert
errors into the B2 byte, within STS-1 Channel 0.
1 – Configures the Transmit STS-3 TOH Processor block to insert errors
into the B2 byte, within STS-1 Channel 0.
Note:
This bit-field is only valid if Bit 1 (B2 Error Insert), within the
“Transmit STS-3 Transport – SONET Transmit Control
Register – Byte 0 (Address Location= 0x1903) to “1”.
204
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Table 137: Transmit STS-3 Transport – Transmit B2 Bit Error Mask Register – Byte 0 (Address
Location= 0x192B)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
Transmit_B2_Error_Mask[7:0]
BIT
NUMBER
NAME
TYPE
7–0
Transmit_B2_Error_Mask[7:0]
R/W
DESCRIPTION
Transmit B2 Error Mask Byte:
These READ/WRITE bit-fields permit the user to specify exact
which bits, within the “selected” B2 byte (within the outbound
STS-3 signal) will be erred.
If the user configures the Transmit STS-3 TOH Processor block
to transmit one or more erred B2 bytes, then the Transmit STS-3
TOH Processor block will perform an XOR operation of the
contents of the B2 byte (within the “selected” STS-1 Channel)
and the contents of this register. The results of this calculation
will be written back into the “B2 byte” position within the
“selected” STS-1 Channel, prior to transmission to the remote
terminal.
The user can select which STS-1 channels (within the outbound
STS-3 signal) will contain the “erred” B2 byte, by writing the
appropriate data into the “Transmit STS-3 Transport – Transmit
B2 Byte Error Mask Register – Bytes 1 and 0 (Address
Location= 0x1927).
Note:
205
This bit-field is only valid if Bit 1 (B2 Error Insert), within
the “Transmit STS-3 Transport – SONET Transmit
Control Register – Byte 0 (Address Location= 0x1903)
to “1”.
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Table 138: Transmit STS-3 Transport – K1K2 (APS) Value Register – Byte 1 (Address Location=
0x192E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit_K2_Byte_Value[7:0]
BIT NUMBER
NAME
TYPE
7–0
Transmit_K2_Byte_Value[7:0]
R/W
DESCRIPTION
Transmit K2 Byte Value:
If the appropriate “K1K2 Insert Method” is selected, then these
READ/WRITE bit-fields will permit the user to specify the
contents of the K2 byte, within the “outbound” STS-3 signal.
If Bit 1 (K1K2 Insert Method) within the Transmit STS-3
Transport – SONET Transmit Control Register – Byte 1
(Address Location= 0x1902) is set to “1”, then the Transmit
STS-3 TOH Processor block will load the contents of this
register into the “K2” byte-field, within each outbound STS-3
frame.
Note:
These register bits are ignored if Bit 1 (K1K2 Insert
Method) is set to “0”.
Table 139: Transmit STS-3 Transport – K1K2 (APS) Value Register – Byte 0 (Address Location=
0x192F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_K1_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7–0
Transmit_K1_Byte_Value[7:0]
R/W
DESCRIPTION
Transmit K1 Byte Value:
If the appropriate “K1K2 Insert Method” is selected, then these
READ/WRITE bit-fields will permit the user to specify the
contents of the K1 byte, within the “outbound” STS-3 signal.
If Bit 1 (K1K2 Insert Method) within the Transmit STS-3
Transport – SONET Transmit Control Register – Byte 1 (Address
Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH
Processor block will load the contents of this register into the
“K1” byte-field, within each outbound STS-3 frame.
Note:
206
These register bits are ignored if Bit 1 (K1K2 Insert
Method) is set to “0”.
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Table 140: Transmit STS-3 Transport – RDI-L Control Register (Address Location= 0x1933)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
BIT 1
BIT 0
External RDIL Enable
Transmit
RDI-L upon
AIS-L
Transmit RDIL upon LOF
Transmit RDIL upon LOS
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–4
Unused
R/O
3
External RDI-L Enable
R/W
DESCRIPTION
External RDI-L Insertion Enable:
This READ/WRITE bit-field permits the user to configure the
Transmit STS-3 TOH Processor to accept data via the “TxTOH”
input pin, when transmitting the RDI-L indicator to the remote
terminal equipment.
0 – Configures the Transmit STS-3 TOH Processor block to
internally generate the RDI-L indicator, when appropriate.
1 – Configure the Transmit STS-3 TOH Processor block accept
data via the “TxTOH” input pin, when transmitting the RDI-L
indicator.
2
Transmit RDI-L upon AIS-L
R/W
Transmit Line Remote Defect Indicator (RDI-L) upon
Detection of AIS-L:
This READ/WRITE bit-field permits the user to configure the
Transmit STS-3 TOH Processor block to automatically transmit a
RDI-L indicator to the remote terminal anytime (and for the
duration) that the corresponding Receive STS-3 TOH Processor
is declaring the Line AIS (AIS-L) defect condition.
0 – Configures the Transmit STS-3 TOH Processor block to NOT
automatically transmit the RDI-L indicator, whenever (and for the
duration that) the corresponding Receive STS-3 TOH Processor
block is declaring the AIS-L defect condition.
1 – Configures the Transmit STS-3 TOH Processor block to
automatically transmit the RDI-L indicator, whenever (and for the
duration that) the corresponding Receive STS-3 TOH Processor
block declares the AIS-L defect condition.
1
Transmit RDI-L upon LOF
R/W
Transmit Line Remote Defect Indicator (RDI-L) upon
Detection of LOF:
This READ/WRITE bit-field permits the user to configure the
Transmit STS-3 TOH Processor block to automatically transmit a
RDI-L indicator to the remote terminal anytime (and for the
duration) that the corresponding Receive STS-3 TOH Processor
block is declaring the LOF defect.
0 – Configures the Transmit STS-3 TOH Processor to NOT
automatically transmit the RDI-L indicator, whenever the
corresponding Receive STS-3 TOH Processor block declares
the LOF defect.
1 – Configures the Transmit STS-3 TOH Processor block to
automatically transmit the RDI-L indicator, whenever (and for the
duration that) the corresponding Receive STS-3 TOH Processor
block declares the LOF defect.
207
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Transmit RDI-L upon LOS
R/W
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Transmit Line Remote Defect Indicator (RDI-L) upon
Detection of LOS:
This READ/WRITE bit-field permits the user to configure the
Transmit STS-3 TOH Processor block to automatically transmit
the RDI-L indicator to the remote terminal anytime (and for the
duration) that the corresponding Receive STS-3 TOH Processor
block is declaring the LOS defect.
0 – Configures the Transmit STS-3 TOH Processor block to NOT
automatically transmit the RDI-L indicator, whenever the
corresponding Receive STS-3 TOH Processor block declares
the LOS defect.
1 – Configures the Transmit STS-3 TOH Processor block to
automatically transmit the RDI-L indicator, whenever (and for the
duration that) the corresponding Receive STS-3 TOH Processor
block declares the LOS defect.
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E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 141: Transmit STS-3 Transport – M0M1 Byte Value Register (Address Location= 0x1937)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_M0M1_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Transmit_M0M1_Byte_Value
[7:0]
R/W
DESCRIPTION
Transmit M0M1 Byte Value:
If the appropriate “M0M1 Insert Method” is selected, then
these READ/WRITE bit-fields will permit the user to specify the
contents of the M0M1 byte, within the “outbound” STS-3
signal.
If Bit 0 (M0M1 Insert Method – Bit 1) within the Transmit STS3 Transport – SONET Transmit Control Register – Byte 1
(Address Location= 0x1902) and Bit 7 (M0M1 Insert Method –
Bit 0) within the Transmit STS-3 Transport – SONET Transmit
Control Register – Byte 0 (Address Location=0x1903) is set to
“0, 1”, then the Transmit STS-3 TOH Processor block will load
the contents of this register into the “M0M1” byte-field, within
each outbound STS-3 frame.
Note:
These register bits are ignored if the M0M1 Insert
Method[1:0] bits are set to any value other than “0,
1”.
Table 142: Transmit STS-3 Transport – S1 Byte Value Register (Address Location= 0x193B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_S1_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Transmit_S1_Byte_Value[7:0]
R/W
DESCRIPTION
Transmit S1 Byte Value:
If the appropriate “S1 Insert Method” is selected, then these
READ/WRITE bit-fields will permit the user to specify the
contents of the S1 byte, within the “outbound” STS-3 signal.
If Bit 2 (S1 Insert Method) within the Transmit STS-3 Transport –
SONET Transmit Control Register – Byte 1 (Address Location=
0x1902) is set to “1”, then the Transmit STS-3 TOH Processor
block will load the contents of this register into the “S1” byte-field,
within each outbound STS-3 frame.
Note:
209
These register bits are ignored if Bit 2 (S1 Insert
Method) is set to “0”.
XRT94L33
333---C
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T
M
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A
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A
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M
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S
T
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C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 143: Transmit STS-3 Transport – F1 Byte Value Register (Address Location= 0x193F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_F1_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Transmit_F1_Byte_Value[7:0]
R/W
DESCRIPTION
Transmit F1 Byte Value:
If the appropriate “F1 Insert Method” is selected, then these
READ/WRITE bit-fields will permit the user to specify the
contents of the F1 byte, within the “outbound” STS-3 signal.
If Bit 3 (F1 Insert Method) within the Transmit STS-3 Transport
– SONET Transmit Control Register – Byte 1 (Address
Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH
Processor block will load the contents of this register into the
“F1” byte-field, within each outbound STS-3 frame.
Note:
These register bits are ignored if Bit 3 (F1 Insert
Method) is set to “0”.
Table 144: Transmit STS-3 Transport – E1 Byte Value Register (Address Location= 0x1943)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_E1_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Transmit_E1_Byte_Value[7:0]
R/W
DESCRIPTION
Transmit E1 Byte Value:
If the appropriate “E1 Insert Method” is selected, then these
READ/WRITE bit-fields will permit the user to specify the
contents of the E1 byte, within the “outbound” STS-3 signal.
If Bit 4 (E1 Insert Method) within the Transmit STS-3 Transport
– SONET Transmit Control Register – Byte 1 (Address
Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH
Processor block will load the contents of this register into the
“E1” byte-field, within each outbound STS-3 frame.
Note:
210
These register bits are ignored if Bit 4 (E1 Insert
Method) is set to “0”.
XRT94L33
333---C
C
H
A
N
N
E
L
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S
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S
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T
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M
M
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P
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R
A
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M
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E
G
S
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E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 145: Transmit STS-3 Transport – E2 Byte Control Register (Address Location= 0x1944)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Enable
All STS-1s
BIT 2
BIT 1
BIT 0
Unused
R/W
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Enable All STS-1s
R/W
DESCRIPTION
Enable All STS-1s:
This READ/WRITE bit-field permits the user to implement either of the
following configurations options for software control of the E2 byte value,
within the outbound STS-3 signal.
0 – Configures the Transmit STS-3 TOH Processor block to read out the
contents o the “Transmit STS-3 Transport – E2 Byte Value” register and
load that value into the E2 byte (within STS-1 # 1) within the outbound
STS-3 signal.
1 – Configures the Transmit STS-3 TOH Processor block to read out the
contents of the 3 “shadow” registers, and to load these values into the E2
byte positions, within each corresponding STS-1 signal; within the
outbound STS-3 signal.
Note:
6-0
Unused
This register bit is ignored if Bit 5 (E2 Insert Method) within the
“Transmit STS-3 Transport – SONET Transmit Control Register
– Byte 1” (Address Location= 0x1902) is set to “0”.
R/O
211
XRT94L33
333---C
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M
M
A
P
P
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R
A
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M
R
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S
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 146: Transmit STS-3 Transport – E2 Pointer Register (Address Location= 0x1946)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
BIT 0
E2_Pointer[1:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–2
Unused
R/O
1-0
E2_Pointer[1:0]
R/W
DESCRIPTION
E2 Pointer[3:0]:
These READ/WRITE bit-fields permit the user to uniquely identify one of
the 3 STS-1 E2 byte “shadow” registers, when performing read or write
operations to these registers.
If the user has set Bit 7 (Enable All STS-1s), within this register to “1”,
then the contents of these four register bits, act as a pointer to a given
“shadow” register. Once the user specifies this pointer value; then he/she
completes the read or write operation (to or from the “shadow” register) by
performing a read or write to the “Transmit STS-3 Transport – E2 Byte
Value” register (Address Location= 0x1947).
Valid “shadow” pointer values range from “0x00” to “0x02” (where the
pointer value of “0x00” corresponds to the E2 “shadow” register,
corresponding to STS-1 # 1; and so on).
Note:
This register bit is ignored if Bit 7 (Enable All STS-1s) is set to
“1”; or if Bit 5 (E2 Insert Method) within the “Transmit STS-3
Transport – SONET Transmit Control Register – Byte 1”
(Address Location= 0x1902) is set to “0”.
212
XRT94L33
333---C
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A
N
N
E
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S
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S
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M
M
A
P
P
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R
A
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M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 147: Transmit STS-3 Transport – E2 Byte Value Register (Address Location=0x1947)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_E2_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Transmit_E2_Byte_Value[7:0]
R/W
DESCRIPTION
Transmit E2 Byte Value:
The exact function of these register bits depends upon
whether Bit 7 (Enable All STS-1s) within the “Transmit STS-3
Transport – E2 Byte Control” Register (Address Location=
0x1944) has been set to “0” or “1”; as described below.
If “Enable All STS-1s” is set to “0”
If the appropriate “E2 Insert Method” is selected, then these
READ/WRITE bit-fields will permit the user to specify the
contents of the E2 byte, within the “outbound” STS-3 signal.
More specifically, this value will be loaded into the E2 byte
position, within STS-1 # 1 (within the outbound STS-3 signal).
If Bit 5 (E2 Insert Method) within the Transmit STS-3 Transport
– SONET Transmit Control Register – Byte 1 (Address
Location= 0x1902) is set to “1”, then the Transmit STS-3 TOH
Processor block will load the contents of this register into the
“E2” byte-field, within each outbound STS-3 frame.
If “Enable All STS-1s” is set to “1”
In this mode, these register bit permit the user to have direct
READ/WRITE access of the “STS-1 E2 Byte shadow” register;
that is being pointed at by the “E2 Pointer[1:0]” value.
These register bits are ignored if Bit 5 (E2 Insert Method) is set
to “0”.
213
XRT94L33
333---C
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P
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 148: Transmit STS-3 Transport – J0 Byte Value Register (Address Location= 0x194B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit_J0_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Transmit_J0_Value[7:0]
R/W
DESCRIPTION
Transmit J0 Value Byte:
These READ/WRITE bits permit a user to specify the value of the
J0 byte, that will be transmitted via the Transport Overhead, within
the very next STS-3 Frame.
Note:
214
This register is only valid if the Transmit STS-3 TOH
Processor block is configured to read out the contents
from this register and insert it into the J0 byte-field within
each outbound STS-3 frame. The user accomplishes
this by setting Bits 1 and 0 (J0_TYPE), within the
Transmit STS-3 Transport – J0 Byte Control Register
(Address Location= 0x194F) to “1, 0”.
XRT94L33
333---C
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A
N
N
E
L
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S
T
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M
M
A
P
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A
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M
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S
T
E
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S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 149: Transmit STS-3 Transport – Transmitter J0 Control Register (Address Location= 0x194F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
MSG_LENGTH
BIT 0
J0_TYPE
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
1
1
0
0
BIT NUMBER
NAME
TYPE
7–4
Unused
R/O
3–2
MSG_LENGTH[1:0]
R/W
DESCRIPTION
Message Length[1:0]:
These two READ/WRITE bit-fields permit the user to specify the length of
the message that is to be repetitively transmitted via the J0 byte, as
depicted below.
1–0
J0_TYPE[1:0]
R/W
MSG_LENGTH[1:0]
Corresponding Message Length (Bytes)
00
1 Byte
01
16 Bytes
10 or 11
64 Bytes
Transmit J0 Source[1:0]:
These two READ/WRITE bit-fields permit the user to specify the source
of the message that will be transported via the J0 byte/message, within
the outbound STS-3 data-stream, as depicted below.
J0_TYPE[1:0]
Corresponding Source of J0 Byte/Message.
00
Automatically set the J0 Byte, in each “outbound”
STS-3 frame to “0x01”.
01
The “Transmit Section Trace Message Buffer”.
The “Transmit STS-3 Trace Buffer” Memory is
located at Address Location 0x1B00 through
0x1B3F.
From the “Transmit J0 Value[7:0]” Register.
10
In this setting, the Transmit STS-3 TOH Processor
block will read out the contents of the “Transmit J0
Value[7:0]” Register (Address Location= 0x194B),
and will insert this value into the J0 byte of each
outbound STS-3 frame.
From the “TxTOH” Input pin (pin F8).
11
215
XRT94L33
333---C
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M
M
A
P
P
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R
A
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M
R
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S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 150: Transmit STS-3 Transport – Serial Port Control Register (Address Location= 0x1953)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
TxTOH_CLOCK_SPEED[7:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-4
Unused
R/O
3-0
TxTOH_CLOCK_SPEED[7:0]
R/W
DESCRIPTION
TxTOHClk Output Clock Signal Speed:
These READ/WRITE bit-fields permits the user to specify the
frequency of the “TxTOHClk output clock signal.
The formula that relates the contents of these register bits to
the “TxTOHClk” frequency is presented below.
FREQ = 19.44 /[2 * (TxTOH_CLOCK_SPEED + 1)
Note:
216
For STS-3/STM-1 applications, the frequency of the
TxTOHClk output signal must be in the range of
0.6075MHz to 9.72MHz
XRT94L33
333---C
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N
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M
A
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A
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M
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E
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S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1.7
REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK
The register map for the Redundant Receive STS-3 TOH Processor Block is presented in the Table below.
Additionally, a detailed description of each of the “Redundant Receive STS-3 TOH Processor” Block registers
is presented below.
In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the
XRT94L33, with the “Redundant Receive STS-3 TOH Processor Block “highlighted” is presented below in
Figure 6
Figure 8: Illustration of the Functional Block Diagram of the XRT94L33, with the Redundant Receive
STS-3 TOH Processor Block “High-lighted”.
From Channels 1 & 2
Tx
Tx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Rx
Rx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Clock
Clock
Synthesizer
Synthesizer
Block
Block
Tx
TxCell
Cell
Processor
Processor
Block
Block
Tx
TxPLCP
PLCP
Processor
Processor
Block
Block
Tx
TxPPP
PPP
Processor
Processor
Block
Block
Tx
TxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Tx
TxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Tx
TxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxPPP
PPP
Processor
Processor
Block
Block
Rx
RxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
RxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Rx
RxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxCell
Cell
Processor
Processor
Block
Block
Rx
RxPLCP
PLCP
Processor
Processor
Block
Block
Channel 0
To Channel 1 & 2
217
Tx
TxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
Tx
TxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Tx
TxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Rx
RxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Clock
Clock&&
Data
Data
Recovery
Recovery
Block
Block
Rx
RxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Rx
RxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
XRT94L33
333---C
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M
M
A
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P
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A
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.7.1
Rev222...000...000
REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER
Table 151: Redundant Receive STS-3 TOH Processor Block Control Register – Address Map
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x00 – 0x02
0x1600 – 0x1702
0x03
0x1703
0x04 – 0x05
0x1704 – 0x1705
0x06
REGISTER NAME
DEFAULT VALUES
Redundant Receive STS-3 Transport Control Register –
Byte 0
0x00
Reserved
0x00
0x1706
Redundant Receive STS-3 Transport Status Register – Byte
1
0x00
0x07
0x1707
Redundant Receive STS-3 Transport Status Register – Byte
0
0x02
0x08
0x1708
Reserved
0x00
0x09
0x1709
Redundant Receive STS-3 Transport Interrupt Status
Register – Byte 2
0x00
0x0A
0x170A
Redundant Receive STS-3 Transport Interrupt Status
Register – Byte 1
0x00
0x0B
0x170B
Redundant Receive STS-3 Transport Interrupt Status
Register – Byte 0
0x00
0x0C
0x170C
Reserved
0x00
0x0D
0x170D
Redundant Receive STS-3 Transport Interrupt Enable
Register – Byte 2
0x00
0x0E
0x170E
Redundant Receive STS-3 Transport Interrupt Enable
Register – Byte 1
0x00
0x0F
0x170F
Redundant Receive STS-3 Transport Interrupt Enable
Register – Byte 0
0x00
0x10
0x1710
Redundant Receive STS-3 Transport B1 Error Count – Byte
3
0x00
0x11
0x1711
Redundant Receive STS-3 Transport B1 Error Count – Byte
2
0x00
0x12
0x1712
Redundant Receive STS-3 Transport B1 Error Count – Byte
1
0x00
0x13
0x1713
Redundant Receive STS-3 Transport B1 Error Count – Byte
0
0x00
0x14
0x1714
Redundant Receive STS-3 Transport B2 Error Count – Byte
3
0x00
0x15
0x1715
Redundant Receive STS-3 Transport B2 Error Count – Byte
2
0x00
0x16
0x1716
Redundant Receive STS-3 Transport B2 Error Count – Byte
1
0x00
Reserved
218
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
REGISTER NAME
DEFAULT VALUES
0x17
0x1717
Redundant Receive STS-3 Transport B2 Error Count – Byte
0
0x00
0x18
0x1718
Redundant Receive STS-3 Transport REI-L Error Count –
Byte 3
0x00
0x19
0x1719
Redundant Receive STS-3 Transport REI-L Error Count –
Byte 2
0x00
0x1A
0x171A
Redundant Receive STS-3 Transport REI-L Error Count –
Byte 1
0x00
0x1B
0x171B
Redundant Receive STS-3 Transport REI-L Error Count –
Byte 0
0x00
0x1C
0x171C
Reserved
0x00
0x1D – 0x1E
0x171D - 0x171E
Reserved
0x00
0x1F
0x171F
Redundant Receive STS-3 Transport K1 Byte Value
0x00
0x20 – 0x22
0x1720 – 0x1722
Reserved
0x00
0x23
0x1723
Redundant Receive STS-3 Transport K2 Byte Value
0x00
0x24 – 0x26
0x1724 – 0x1726
Reserved
0x00
0x27
0x1727
Redundant Receive STS-3 Transport S1 Byte Value
0x00
0x28 – 0x2A
0x1728 – 0x172A
Reserved
0x00
0x2B
0x172B
Redundant Receive STS-3 Transport – In-Sync Threshold
Value
0x00
0x2C, 0x2D
0x172C, 0x172D
Reserved
0x00
0x2E
0x172E
Redundant Receive STS-3 Transport – LOS Threshold
Value – MSB
0xFF
0x2F
0x172F
Redundant Receive STS-3 Transport – LOS Threshold
Value – LSB
0xFF
0x30
0x1730
Reserved
0x00
0x31
0x1731
Redundant Receive STS-3 Transport – SF Set Monitor
Interval – Byte 2
0x00
0x32
0x1732
Redundant Receive STS-3 Transport – SF Set Monitor
Interval – Byte 1
0x00
0x33
0x1733
Redundant Receive STS-3 Transport – SF Set Monitor
Interval – Byte 0
0x00
0x34, 0x35
0x1734 – 0x1735
Reserved
0x00
0x36
0x1736
Redundant Receive STS-3 Transport – SF Set Threshold –
Byte 1
0x00
0x37
0x1737
Redundant Receive STS-3 Transport – SF Set Threshold –
Byte 0
0x00
219
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x38, 0x39
0x1738, 0x1739
0x3A
Rev222...000...000
REGISTER NAME
DEFAULT VALUES
Reserved
0x00
0x173A
Redundant Receive STS-3 Transport – SF Clear Threshold
– Byte 1
0x00
0x3B
0x173B
Redundant Receive STS-3 Transport – SF Clear Threshold
– Byte 0
0x00
0x3C
0x173C
Reserved
0x00
0x3D
0x173D
Redundant Receive STS-3 Transport – SD Set Monitor
Interval – Byte 2
0x00
0x3E
0x173E
Redundant Receive STS-3 Transport – SD Set Monitor
Interval – Byte 1
0x00
0x3F
0x173F
Redundant Receive STS-3 Transport – SD Set Monitor
Interval – Byte 0
0x00
0x40, 0x41
0x1740, 0x1741
Reserved
0x00
0x42
0x1742
Redundant Receive STS-3 Transport – SD Set Threshold –
Byte 1
0x00
0x43
0x1743
Redundant Receive STS-3 Transport – SD Set Threshold –
Byte 0
0x00
0x44, 0x45
0x1744, 0x1745
Reserved
0x00
0x46
0x1746
Redundant Receive STS-3 Transport – SD Clear Threshold
– Byte 1
0x00
0x47
0x1747
Redundant Receive STS-3 Transport – SD Clear Threshold
– Byte 0
0x00
0x48 – 0x4A
0x1748 – 0x174A
Reserved
0x00
0x4B
0x174B
0x4C, 0x4E
0x174C, 0x174E
0x4F
0x174F
0x50, 0x51
0x1750, 0x1751
0x52
Redundant
Condition
Receive
STS-3 Transport
–
Force
SEF
0x00
Reserved
0x00
Redundant Receive STS-3 Transport – Receive J0 Trace
Buffer Control
0x00
Reserved
0x00
0x1752
Redundant Receive STS-3 Transport – SD Burst Error
Count Tolerance – Byte 1
0x00
0x53
0x1753
Redundant Receive STS-3 Transport – SD Burst Error
Count Tolerance – Byte 0
0x00
0x54, 0x55
0x1754, 0x1755
Reserved
0x00
0x56
0x1756
Redundant Receive STS-3 Transport – SF Burst Error
Count Tolerance – Byte 1
0x00
0x57
0x1757
Redundant Receive STS-3 Transport – SF Burst Error
Count Tolerance – Byte 0
0x00
220
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x58
0x1758
Reserved
0x00
0x59
0x1759
Redundant Receive STS-3 Transport –Receive SD Clear
Monitor Interval – Byte 2
0xFF
0x5A
0x175A
Redundant Receive STS-3 Transport – Receive SD Clear
Monitor Interval – Byte 1
0xFF
0x5B
0x175B
Redundant Receive STS-3 Transport – Receive SD Clear
Monitor Interval – Byte 0
0xFF
0x5C
0x175C
Reserved
0x00
0x5D
0x175D
Redundant Receive STS-3 Transport – Receive SF Clear
Monitor Interval – Byte 2
0xFF
0x5E
0x175E
Redundant Receive STS-3 Transport – Receive SF Clear
Monitor Interval – Byte 1
0xFF
0x5F
0x175F
Redundant Receive STS-3 Transport – Receive SF Clear
Monitor – Byte 0
0xFF
0x60 – 0x62
0x1760 – 0x1762
Reserved
0x00
0x63
0x1763
Redundant Receive STS-3 Transport – Auto AIS Control
Register
0x00
0x64 – 0x66
0x1764 – 0x1766
Reserved
0x00
0x67
0x1767
Redundant Receive STS-3 Transport – Serial Port Control
Register
0x00
0x68 – 0x6A
0x1768 – 0x176A
Reserved
0x00
0x6B
0x176B
Redundant Receive STS-3 Transport – Auto AIS (in
Downstream STS-1s) Control Register
0x00
0x6C – 0x79
0x176C – 0x1779
Reserved
0x00
0x7A
0x117A
Redundant Receive STS-3 Transport – TOH Capture
Indirect Address
0x00
0x7B
0x117B
Redundant Receive STS-3 Transport – TOH Capture
Indirect Address
0x00
0x7C
0x117C
Redundant Receive STS-3 Transport – TOH Capture
Indirect Data
0x00
0x7D
0x117D
Redundant Receive STS-3 Transport – TOH Capture
Indirect Data
0x00
0x7E
0x117E
Redundant Receive STS-3 Transport – TOH Capture
Indirect Data
0x00
0x7F
0x117F
Redundant Receive STS-3 Transport – TOH Capture
Indirect Data
0x00
0x80 – 0xFF
0x1780 – 0x17FF
Reserved
0x00
REGISTER NAME
221
DEFAULT VALUES
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.7.2
Rev222...000...000
REDUNDANT RECEIVE STS-3 TOH PROCESSOR BLOCK REGISTER DESCRIPTION
Table 152: Redundant Receive STS-3 Transport Control Register – Byte 0 (Address Location= 0x1703)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
STS-N OH
Extract
SF Detect
Enable
SD Detect
Enable
Descramble
Disable
SDH/
SONET*
REI-L
Error Type
B2 Error
Type
B1 Error
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
STS-N OH
Extract
R/W
DESCRIPTION
STS-N Overhead Extract (Revision C Silicon Only):
This READ/WRITE bit-field permits the user to configure the RxTOH output
port to output the TOH for all lower-tributary STS-1s within the incoming
STS-3 signal.
0 – Disables this feature. In this mode, the RxTOH output port will only
output the TOH for the first STS-1 within the incoming STS-3 signal.
1 – Enables this feature.
6
SF Detect
Enable
R/W
Signal Failure (SF) Detect Enable:
This READ/WRITE bit-field permits the user to enable or disable SF
Detection by the Redundant Receive STS-3 TOH Processor Block.
0 – SF Detection is disabled.
1 – SF Detection is enabled:
5
SD Detect
Enable
R/W
Signal Degrade (SD) Detect Enable:
This READ/WRITE bit-field permits the user to enable or disable SD
Detection by the Redundant Receive STS-3 TOH Processor Block.
0 – SD Detection is disabled.
1 – SD Detection is enabled.
4
Descramble
Disable
R/W
De-Scramble Disable:
This READ/WRITE bit-field permits the user to either enable or disable descrambling by the Redundant Receive STS-3 TOH Processor block.
0 – De-Scrambling is enabled.
1 – De-Scrambling is disabled.
3
SDH/SONET*
R/W
SDH/SONET Select:
This READ/WRITE bit-field permits the user to configure the Redundant
Receiver to operate in either the SONET or SDH Mode.
0 – Configures the Redundant Receiver to operate in the SONET Mode.
1 – Configures the Redundant Receiver to operate in the SDH Mode.
2
REI-L Error
Type
R/W
REI-L (Line – Remote Error Indicator) Error Type:
This READ/WRITE bit-field permits the user to specify how the “Redundant
Receive Transport REI-L Error Count” register is incremented.
0 – Configures the Redundant Receive STS-3 TOH Processor block to
count REI-L Bit Errors.
222
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
In this case the “Redundant Receive Transport REI-L Error Count” register
will be incremented by the value of the lower nibble within the M0/M1 byte.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
count REI-L Frame Errors.
In this case the “Redundant Receive Transport REI-L Error Count” register
will be incremented each time the STS-3 Redundant Receiver receives a
“non-zero” M0/M1 byte.
1
B2 Error Type
R/W
B2 Error Type:
This READ/WRITE bit-field permits the user to specify how the “Redundant
Receive Transport B2 Error Count” register is incremented.
0 – Configures the Redundant Receive STS-3 TOH Processor block to
count B2 bit errors.
In this case, the “Redundant Receive Transport B2 Error Count” register
will be incremented by the number of bits, within the B2 value, that is in
error.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
count B2 frame errors.
In this case, the “Redundant Receive Transport B2 Error Count” register
will be incremented by the number of erred STS-3 frames.
0
B1 Error Type
R/W
B1 Error Type:
This READ/WRITE bit-field permits the user to specify how the “Redundant
Receive Transport B1 Error Count” register is incremented.
0 – Configures the Redundant Receive STS-3 TOH Processor block to
count B1 bit errors.
In this case, the “Redundant Receive Transport B1 Error Count” register
will be incremented by the number of bits, within the B1 value, that is in
error.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
count B2 bit errors.
In this case, the “Redundant Receive Transport B1 Error Count” register
will be incremented by the number of erred STS-3 frames.
223
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 153: Redundant Receive STS-3 Transport Status Register – Byte 1 (Address Location= 0x1706)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
J0 Message
Mismatch
Defect
Declared
J0 Message
Unstable
Defect
Declared
AIS_L Defect
Declared
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
J0 Message
Mismatch Defect
Declared
R/O
DESCRIPTION
J0 – Section Trace Mismatch Indicator:
This READ-ONLY bit-field indicates whether or not the Redundant Receive
STS-3 TOH Processor block is currently declaring the Section Trace
Mismatch condition. The Redundant Receive STS-3 TOH Processor block
will declare a J0 (Section Trace) Mismatch condition, whenever it accepts a
J0 Message that differs from the “Expected J0 Message”.
0 – Section Trace Mismatch Condition is NOT declared.
1 – Section Trace Mismatch Condition is currently declared.
1
J0 Message
Unstable Defect
Declared
R/O
J0 – Section Trace Unstable Indicator:
This READ-ONLY bit-field indicates whether or not the Redundant Receive
STS-3 TOH Processor block is currently declaring the Section Trace
Instability condition. The Redundant Receive STS-3 TOH Processor block
will declare a J0 (Section Trace) Unstable condition, whenever the “J0
Unstable” counter reaches the value 8. The “J0 Unstable” counter will be
incremented for each time that it receives a J0 message that differs from the
“Expected J0 Message”. The “J0 Unstable” counter is cleared to “0”
whenever the Redundant Receive STS-3 TOH Processor block has
received a given J0 Message 3 (or 5) consecutive times.
Note:
Receiving a given J0 Message 3 (or 5) consecutive times also sets
this bit-field to “0”.
0 – Section Trace Instability condition is NOT declared.
1 – Section Trace Instability condition is currently declared.
0
AIS_L
Defect
Declared
R/O
AIS-L (Line AIS) State:
This READ-ONLY bit-field indicates whether or not the Redundant Receive
STS-3 TOH Processor block is currently detecting an AIS-L (Line AIS)
pattern in the incoming STS-3 data stream. AIS-L is declared if bits 6, 7 and
8 (e.g., the Least Significant Bits, within the K2 byte) value the value “1, 1,
1” for five consecutive STS-1 frames.
0 – AIS-L is NOT currently declared.
1 – AIS-L is currently being declared.
224
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 154: Redundant Receive STS-3 Transport Status Register – Byte 0 (Address Location= 0x1707)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RDI-L
Defect
Declared
S1 Byte
Unstable
Defect
Declared
(K1, K2)
APS Byte
Unstable
SF Defect
Declared
SD Defect
Declared
LOF
Defect
Declared
SEF
Defect
Declared
LOS
Defect
Declared
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
RDI-L Defect
Declared
R/O
DESCRIPTION
RDI-L (Line Remote Defect Indicator) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring a Line-Remote Defect Indicator
(RDI-L), in the incoming STS-3 signal. RDI-L is declared when bits 6, 7 and 8
(e.g., the three least significant bits) of the K2 byte contains the “1, 1, 0” pattern
in 5 consecutive STS-3 frames.
0 – RDI-L is NOT being declared.
1 – RDI-L is currently being declared.
6
S1 Byte
Unstable
Defect
Declared
R/O
S1 Byte Unstable Defect Declared Condition:
This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the “S1 Byte Instability” condition.
The Redundant Receive STS-3 TOH Processor block will declare an “S1 Byte
Instability” condition whenever the “S1 Byte Unstable Counter” reaches the value
32. The “S1 Byte Unstable Counter” is incremented for each time that the
Redundant Receive STS-3 TOH Processor block receives an S1 byte that differs
from the previously received S1 byte. The “S1 Byte Unstable Counter” is cleared
to “0” when the same S1 byte is received for 8 consecutive STS-3 frames.
Note:
Receiving a given S1 byte, in 8 consecutive STS-3 frames also sets this
bit-field to “0”.
0 – S1 Instability Condition is NOT declared.
1 – S1 Instability Condition is currently declared.
5
(K1, K2) APS
Byte Unstable
R/O
APS (K1, K2 Byte) Unstable Condition:
This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the “K1, K2 Byte Unstable”
condition. The Redundant Receive STS-3 TOH Processor block will declare a
“K1, K2 Byte Unstable” condition whenever the Redundant Receive STS-3 TOH
Processor block fails to receive the same set of K1, K2 bytes, in 12 consecutive
STS-3 frames. The “K1, K2 Byte Unstable” condition is cleared whenever the
Redundant Receive STS-3 TOH Processor block receives a given set of K1, K2
byte values in three consecutive STS-3 frames.
0 – K1, K2 Unstable Condition is NOT currently declared.
1 – K1, K2 Unstable Condition is currently declared.
4
SF Defect
Declared
R/O
SF (Signal Failure) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the SF defect. The SF defect is
declared when the number of B2 errors observed over a given time interval
exceeds a certain threshold.
0 – SF Defect is NOT being declared.
This bit is set to “0” when the number of B2 errors (accumulated over a given
225
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
interval of time) does not exceed the “SF Declaration” threshold.
1 – SF Defect is being declared.
This bit is set to “1” when the number of B2 errors (accumulated over a given
interval of time) does exceed the “SF Declaration” threshold.
3
SD Defect
Declared
R/O
SD (Signal Degrade) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring the SD defect. The SD defect is
declared when the number of B2 errors observed over a given time interval
exceeds a certain threshold.
0 – SD Defect is NOT being declared.
This bit is set to “0” when the number of B2 errors (accumulated over a given
interval of time) does not exceed the “SD Declaration” threshold.
1 – SD Defect is being declared.
This bit is set to “1” when the number of B2 errors (accumulated over a given
interval of time) does exceed the “SD Declaration” threshold.
2
LOF
Defect
Declared
R/O
LOF (Loss of Frame) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring an LOF defect condition. The
Redundant Receive STS-3 TOH Processor block will declare an LOF defect
condition, if continues to declare the SEF (Severely Errored Frame) condition for
3ms (or 24 SONET frame periods).
0 – LOF is NOT being declared.
1 – LOF is currently being declared.
1
SEF
Defect
Declared
R/O
SEF (Severely Errored Frame) Defect Declared:
This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring an SEF condition. The SEF
condition is declared, if the “SEF Declaration Criteria”; per the settings of the
FRPATOUT[1:0] bits, within the Redundant Receive STS-3 Transport – In-Sync
Threshold Value Register (Address Location= 0x172B).
0 – SEF condition is NOT being declared.
1 – SEF condition is currently being declared.
0
LOS
Defect
Declared
R/O
LOS (Loss of Signal) Indicator:
This READ-ONLY bit-field indicates whether or not the Redundant Receive STS3 TOH Processor block is currently declaring an LOS (Loss of Signal) defect
condition. The Redundant Receive STS-3 TOH Processor block will declare an
LOS defect condition if it detects “LOS_THRESHOLD[15:0]” consecutive “All
Zero” bytes in the incoming STS-3 data stream.
Note:
The user can set the “LOS_THRESHOLD[15:0]” value by writing the
appropriate data into the “Redundant Receive STS-3 Transport – LOS
Threshold Value” Register (Address Location= 0x172E and 0x172F).
0 – Indicates that the Redundant Receive STS-3 TOH Processor block is NOT
currently declaring an LOS defect condition.
1 – Indicates that the Redundant Receive STS-3 TOH Processor block is
currently declaring an LOS defect condition.
226
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 155: Redundant Receive STS-3 Transport Interrupt Status Register – Byte 2 (Address Location=
0x1709)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
Change of AIS-L
Condition
Interrupt Status
Change of RDI-L
Condition
Interrupt Status
R/O
R/O
R/O
R/O
R/O
R/O
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-2
Unused
R/O
1
Change of AIS-L
Condition
Interrupt Status
RUR
DESCRIPTION
Change of AIS-L (Line AIS) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
AIS-L Condition” interrupt has occurred since the last read of this register.
0 – The “Change of AIS-L Condition” interrupt has not occurred since the
last read of this register.
1 – The “Change of AIS-L Condition” interrupt has occurred since the last
read of this register.
Note:
0
Change of
RDI-L Condition
Interrupt Status
RUR
The user can obtain the current state of AIS-L by reading the
contents of Bit 0 (AIS-L Defect Declared) within the “Redundant
Receive STS-3 Transport Status Register – Byte 1” (Address
Location= 0x1706).
Change of RDI-L (Line - Remote Defect Indicator) Condition Interrupt
Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
RDI-L Condition” interrupt has occurred since the last read of this register.
0 – The “Change of RDI-L Condition” interrupt has not occurred since the
last read of this register.
1 – The “Change of RDI-L Condition” interrupt has occurred since the last
read of this register.
Note:
The user can obtain the current state of RDI-L by reading out the
state of Bit 7 (RDI-L Declared) within the “Redundant Receive
STS-3 Transport Status Register – Byte 0” (Address Location =
0x1707).
227
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 156: Redundant Receive STS-3 Transport Interrupt Status Register – Byte 1 (Address Location=
0x170A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New S1
Byte
Interrupt
Status
Change in
S1 Unstable
State
Interrupt
Status
Change in
J0 Message
Unstable
State
Interrupt
Status
New J0
Message
Interrupt
Status
Change in
J0 Mismatch
Condition
Interrupt
Status
Receive
TOH CAP
DONE
Interrupt
Status
Change in
(K1, K2)
APS Bytes
Unstable
State
Interrupt
Status
NEW K1K2
Byte
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
New S1 Byte
Value Interrupt
Status
RUR
DESCRIPTION
New S1 Byte Value Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New S1 Byte
Value” Interrupt has occurred since the last read of this register.
0 – Indicates that the “New S1 Byte Value” Interrupt has NOT occurred
since the last read of this register.
1 – Indicates that the “New S1 Byte Value” interrupt has occurred since the
last read of this register.
Note:
6
Change in S1
Byte Unstable
State Interrupt
Status
RUR
The user can obtain the value for this most recently accepted value
of the S1 byte by reading the “Redundant Receive STS-3
Transport S1 Value” register (Address Location= 0x1727).
Change in S1 Byte Unstable State – Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change in
S1 Byte Unstable State” Interrupt has occurred since the last read of this
register.
0 – Indicates that the “Change in S1 Byte Unstable State” Interrupt has
occurred since the last read of this register.
1 – Indicates that the “Change in S1 Byte Unstable State” Interrupt has not
occurred since the last read of this register.
Note:
5
Change in J0
Message
Unstable State
Interrupt Status
RUR
The user can obtain the current “S1 Unstable” state by reading the
contents of Bit 6 (S1 Unstable) within the “Redundant Receive
STS-3 Transport Status Register – Byte 0” (Address Location=
0x1707).
Change of J0 (Section Trace) Message Unstable condition – Interrupt
Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of J0
(Section Trace) Message Instability” condition interrupt has occurred since
the last read of this register.
0 – Indicates that the “Change of J0 (Section Trace) Message Instability”
condition interrupt has not occurred since the last read of this register.
1 – Indicates that the “Change of J0 (Section Trace) Message Instability”
condition interrupt has occurred since the last read of this register.
4
New J0 Message
Interrupt Status
RUR
New J0 Trace Message Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New J0
Trace Message” interrupt has occurred since the last read of this register.
228
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0 – Indicates that the “New J0 Trace Message Interrupt” has not occurred
since the last read of this register.
1 – Indicates that the “New J0 Trace Message Interrupt” has occurred since
the last read of this register.
Note:
3
Change in J0
Mismatch
Condition
Interrupt Status
RUR
The user can read out the contents of the “Receive J0 Trace
Buffer”, which is located at Address location 0x1300 through
0x133F.
Change in J0 – Section Trace Mismatch Condition” Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change in J0
– Section Trace Mismatch Condition” interrupt has occurred since the last
read of this register.
0 – Indicates that the “Change in J0 – Section Trace Mismatch Condition”
interrupt has not occurred since the last read of this register.
1 – Indicates that the “Change in J0 – Section Trace Mismatch Condition”
interrupt has occurred since the last read of this register.
Note:
2
Receive TOH
CAP DONE
Interrupt Status
RUR
The user can determine whether the “J0 – Section Trace
Mismatch” condition is “cleared” or “declared” by reading the state
of Bit 2 (J0_MIS) within the “Redundant Receive STS-3 Transport
Status Register – Byte 1 (Address Location= 0x1706).
Receive TOH Capture DONE – Interrupt Status:
This RESET-upon-READ bit-field indicates whether the “Receive TOH Data
Capture” Interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Redundant Receive STS-3 TOH
Processor block will generate an interrupt anytime it has captured the last
TOH byte into the Capture Buffer.
Note:
Once the TOH (of a given STS-3 frame) has been captured and
loaded into the “Receive TOH Capture” buffer, it will remain there
for one SONET frame period.
0 – Indicates that the “Receive TOH Data Capture” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Receive TOH Data Capture” Interrupt has occurred
since the last read of this register.
1
Change in APS
(K1, K2 Byte)
Unstable Status
Interrupt Status
RUR
Change of APS (K1, K2 Byte) Unstable Condition – Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
APS (K1, K2 Byte) Instability Condition” interrupt has occurred since the last
read of this register.
0 – Indicates that the “Change of APS (K1, K2 Byte) Instability Condition”
interrupt has NOT occurred since the last read of this register.
1 – Indicates that the “Change of APS (K1, K2 Byte) Instability Condition”
interrupt has occurred since the last read of this register.
Note:
0
NEW K1K2 Byte
Interrupt Status
RUR
The user can determine whether the “K1, K2 Unstable Condition” is
being declared or cleared by reading out the contents of Bit 5
(APS Unstable), within the “Redundant Receive STS-3 Transport
Status Register – Byte 0” (Address Location = 0x1707).
New K1, K2 Byte Value Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New K1, K2
Byte Value” Interrupt has occurred since the last read of this register.
0 – Indicates that the “New K1, K2 Byte Value” Interrupt has NOT occurred
since the last read of this register.
1 – Indicates that the “New K1, K2 Byte Value” Interrupt has occurred since
229
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
the last read of this register.
Note:
The user can obtain the contents of the new K1 byte by reading out
the contents of the “Redundant Receive STS-3 Transport K1
Value” Register (Address Location= 0x171F). Further, the user
can also obtain the contents of the new K2 byte by reading out the
contents of the “Redundant Receive STS-3 Transport K2 Value”
Register (Address Location= 0x1723).
230
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 157: Redundant Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address Location=
0x170B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change in
SF
Condition
Interrupt
Status
Change in
SD
Condition
Interrupt
Status
Detection of
REI-L Error
Interrupt
Status
Detection of
B2 Error
Interrupt
Status
Detection of
B1 Error
Interrupt
Status
Change of
LOF
Condition
Interrupt
Status
Change of
SEF
Condition
Interrupt
Status
Change of
LOS
Condition
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Change in SF
Condition
Interrupt Status
RUR
DESCRIPTION
Change of Signal Failure (SF) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
SF Condition Interrupt” has occurred since the last read of this register.
0 - The “Change of SF Condition Interrupt” has NOT occurred since the
last read of this register.
1 – The “Change of SF Condition Interrupt” has occurred since the last read
of this register.
Note:
6
Change of SD
Condition
Interrupt Status
RUR
The user can determine the current “SF” condition by reading out
the state of Bit 4 (SF Declared) within the “Redundant Receive
STS-3 Transport Status Register – Byte 0 (Address Location=
0x1707).
Change of Signal Degrade (SD) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
SD Condition Interrupt” has occurred since the last read of this register.
0 - The “Change of SD Condition Interrupt” has NOT occurred since the
last read of this register.
1 – The “Change of SD Condition Interrupt” has occurred since the last
read of this register.
Note:
5
Detection of REIL Interrupt Status
RUR
The user can determine the current “SD” condition by reading out
the state of Bit 3 (SD Declared) within the “Redundant Receive
STS-3 Transport Status Register – Byte 0 (Address Location=
0x1707).
Detection of Line – Remote Error Indicator Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Declaration
of Line – Remote Error Indicator” Interrupt has occurred since the last read
of this register.
0 - The “Declaration of Line – Remote Error Indicator” Interrupt has NOT
occurred since the last read of this register.
1 – The “Declaration of Line – Remote Error Indicator” Interrupt has
occurred since the last read of this register.
4
Detection of B2
Error Interrupt
Status
RUR
Detection of B2 Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Detection of
B2 Error Interrupt” has occurred since the last read of this register.
0 - The “Detection of B2 Error Interrupt” has NOT occurred since the last
read of this register.
1 – The “Detection of B2 Error Interrupt” has occurred since the last read of
231
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
this register.
3
Detection of B1
Error Interrupt
Status
RUR
Detection of B1 Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Detection of
B1 Error Interrupt” has occurred since the last read of this register.
0 - The “Detection of B1 Error Interrupt” has NOT occurred since the last
read of this register.
1 – The “Detection of B1 Error Interrupt” has occurred since the last read of
this register
2
Change of LOF
Interrupt Status
RUR
Change of Loss of Frame (LOF) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
LOF Condition” interrupt has occurred since the last read of this register.
0 – The “Change of LOF Condition” interrupt has NOT occurred since the
last read of this register.
1 – The “Change of LOF Condition” interrupt has occurred since the last
read of this register.
Note:
1
Change of SEF
Condition
Interrupt Status
RUR
The user can determine the current “LOF” condition by reading out
the state of Bit 2 (LOF Defect Declared) within the “Redundant
Receive STS-3 Transport Status Register – Byte 0 (Address
Location= 0x1707).
Change of SEF Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
SEF” Condition Interrupt has occurred since the last read of this register.
0 – The “Change of SEF Condition” Interrupt has NOT occurred since the
last read of this register.
1 – The “Change of SEF Condition” Interrupt has occurred since the last
read of this register.
Note:
0
Change of LOS
Condition
Interrupt Status
RUR
The user can determine the current “SEF” condition by reading out
the state of Bit 1 (SEF Defect Declared) within the “Redundant
Receive STS-3 Transport Status Register – Byte 0 (Address
Location= 0x1707).
Change of Loss of Signal (LOS) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
LOS Condition” interrupt has occurred since the last read of this register.
0 – The “Change of LOS Condition” Interrupt has NOT occurred since the
last read of this register.
1 – The “Change of LOS Condition” Interrupt has occurred since the last
read of this register.
Note:
The user can determine the current “LOS” status by reading out
the contents of Bit 0 (LOS Defect Declared) within the Redundant
Receive STS-3 Transport Status Register – Byte 0 (Address
Location= 0x1707).
232
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 158: Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 2 (Address Location=
0x170D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
Change of AIS-L
Condition
Interrupt Enable
Change of RDI-L
Condition
Interrupt Enable
R/O
R/O
R/O
R/O
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–2
Unused
R/O
1
Change of AIS-L
Condition
Interrupt Enable
R/W
DESCRIPTION
Change of AIS-L (Line AIS) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of AIS-L Condition” interrupt. If the user enables this interrupt,
then the XRT94L33 will generate an interrupt in response to either of the
following conditions.
• When the Redundant Receive STS-3 TOH Processor block declares the
“AIS-L” condition.
• When the Redundant Receive STS-3 TOH Processor block clears the
“AIS-L” condition.
0 – Disables the “Change of AIS-L Condition” Interrupt.
1 – Enables the “Change of AIS-L Condition” Interrupt.
Note:
0
Change of RDI-L
Condition
Interrupt Enable
R/W
The user can determine the current “AIS-L” condition by reading
out the state of Bit 0 (AIS-L) within the “Redundant Receive STS3 Transport Status Register – Byte 1” (Address Location=
0x1706).
Change of RDI-L (Line Remote Defect Indicator) Condition Interrupt
Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of RDI-L Condition” interrupt. If the user enables this interrupt,
then the XRT94L33 will generate an interrupt in response to either of the
following conditions.
• When the Redundant Receive STS-3 TOH Processor block declares the
“RDI-L” condition.
• When the Redundant Receive STS-3 TOH Processor block clears the
“RDI-L” condition.
0 – Disables the “Change of RDI-L Condition” Interrupt.
1 – Enables the “Change of RDI-L Condition” Interrupt.
233
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 159: Redundant Receive STS-3 Transport Interrupt Enable Register – Byte 1 (Address Location=
0x170E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New S1
Byte
Interrupt
Enable
Change in
S1 Byte
Unstable
State
Interrupt
Enable
Change in
J0 Message
Unstable
State
Interrupt
Enable
New J0
Message
Interrupt
Enable
J0 Mismatch
Interrupt
Enable
Receive
TOH CAP
DONE
Interrupt
Enable
Change in
APS
Unstable
State
Interrupt
Enable
NEW
K1K2 Byte
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
New S1 Byte
Value Interrupt
Enable
R/W
DESCRIPTION
New S1 Byte Value Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the “New S1
Byte Value” Interrupt. If the user enables this interrupt, then the Redundant
Receive STS-3 TOH Processor block will generate this interrupt anytime it
receives and accepts a new S1 byte value. The Redundant Receive STS-3
TOH Processor block will accept a new S1 byte after it has received it for 8
consecutive STS-3 frames.
0 – Disables the “New S1 Byte Value” Interrupt.
1 – Enables the “New S1 Byte Value” Interrupt.
6
Change in S1
Unstable State
Interrupt
Enable
R/W
Change in S1 Byte Unstable State Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change in S1 Byte Unstable State” Interrupt. If the user enables this bit-field,
then the Redundant Receive STS-3 TOH Processor block will generate an
interrupt in response to either of the following conditions.
•
When the Redundant Receive STS-3 TOH Processor block declares the
“S1 Byte Instability” condition.
•
When the Redundant Receive STS-3 TOH Processor block clears the “S1
Byte Instability” condition.
0 – Disables the “Change in S1 Byte Unstable State” Interrupt.
1 – Enables the “Change in S1 Byte Unstable State” Interrupt.
5
Change in J0
Message
Unstable State
Interrupt
Enable
R/W
Change of J0 (Section Trace) Message Instability condition Interrupt
Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of J0 Message Instability Condition” Interrupt. If the user enables this
interrupt, then the Redundant Receive STS-3 TOH Processor block will
generate an interrupt in response to either of the following conditions.
•
Whenever the Redundant Receive STS-3 TOH Processor block declares
the “J0 Message Instability” condition.
•
Whenever the Redundant Receive STS-3 TOH Processor block clears the
“J0 Message Instability” condition.
0 – Disable the “Change of J0 Message Instability” Interrupt.
1 – Enables the “Change of J0 Message Instability” Interrupt.
4
New J0
Message
R/W
New J0 Trace Message Interrupt Enable:
234
XRT94L33
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ST
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S---111 T
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ST
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S---333///S
ST
TM
M---111 M
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R ––– A
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MR
RE
EG
GIIIS
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Rev222...000...000
Interrupt
Enable
This READ/WRITE bit-field permits the user to enable or disable the “New J0
Trace Message” interrupt. If the user enables this interrupt, then the
Redundant Receive STS-3 TOH Processor block will generate this interrupt
anytime it receives and accepts a new J0 Trace Message. The Redundant
Receive STS-3 TOH Processor block will accept a new J0 Trace Message
after it has received it 3 (or 5) consecutive times.
0 – Disables the “New J0 Trace Message” Interrupt.
1 – Enables the “New J0 Trace Message” Interrupt.
3
J0 Mismatch
Interrupt
Enable
R/W
Change in “J0 – Section Trace Mismatch Condition” interrupt enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change in J0 – Section Trace Mismatch condition” interrupt. If the user
enables this interrupt, then the Redundant Receive STS-3 TOH Processor
block will generate an interrupt in response to either of the following events.
•
The Redundant Receive STS-3 TOH Processor block declares a “J0 –
Section Trace Mismatch” condition.
•
The Redundant Receive STS-3 TOH Processor block clears the “J0 –
Section Trace Mismatch” condition.
Note:
2
Receive TOH
CAP DONE
Interrupt
Enable
R/W
The user can determine whether the “J0 – Section Trace Mismatch”
condition is “cleared or “declared” by reading the state of Bit 2 (J0
Message Mismatch Defect Declared) within the “Redundant Receive
STS-3 Transport Status Register – Byte 1 (Address Location=
0x1706).
Receive TOH Capture DONE – Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Receive TOH Data Capture” interrupt, within the Redundant Receive STS-3
TOH Processor Block.
If this interrupt is enabled, then the Redundant Receive STS-3 TOH Processor
block will generate an interrupt anytime it has captured the last TOH byte into
the Capture Buffer.
Note:
Once the TOH (of a given STS-3 frame) has been captured and
loaded into the “Receive TOH Capture” buffer, it will remain there for
one SONET frame period.
0 – Disables the “Receive TOH Capture” Interrupt.
1 – Enables the “Receive TOH Capture” Interrupt.
1
0
Change in
APS Unstable
State Interrupt
Enable
New K1K2
Byte Interrupt
Enable
R/W
Change of APS (K1, K2 Byte) Instability Condition - Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of APS (K1, K2 Byte) Instability condition” interrupt. If the user
enables this interrupt, then the Redundant Receive STS-3 TOH Processor
block will generate an Interrupt in response to either of the following events.
R/W
•
If the Redundant Receive STS-3 TOH Processor block declares a “K1, K2
Instability” condition.
•
If the Redundant Receive STS-3 TOH Processor block clears the “K1, K2
Instability” condition.
New K1, K2 Byte Value Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“New K1, K2 Byte Value” Interrupt. If the user enables this interrupt, then the
Redundant Receive STS-3 TOH Processor block will generate this interrupt
anytime it receives and accepts a new K1, K2 byte value. The Redundant
Receive STS-3 TOH Processor block will accept a new K1, K2 byte value,
after it has received it within 3 (or 5) consecutive STS-3 frames.
235
XRT94L33
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M---111 M
MA
AP
PP
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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ER
RS
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CH
HA
AN
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NE
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
0 – Disables the “New K1, K2 Byte Value” Interrupt.
1 – Enables the “New K1, K2 Byte Value” Interrupt.
236
Rev222...000...000
XRT94L33
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M
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A
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 160: Redundant Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address Location=
0x170F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change of
SF
Condition
Interrupt
Enable
Change of
SD
Condition
Interrupt
Enable
Detection of
REI-L Error
Interrupt
Enable
Detection of
B2 Error
Interrupt
Enable
Detection of
B1 Error
Interrupt
Enable
Change of
LOF
Condition
Interrupt
Enable
Change of
SEF
Condition
Interrupt
Enable
Change of
LOS
Condition
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Change of SF
Condition
Interrupt Enable
R/W
DESCRIPTION
Change of Signal Failure (SF) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of Signal Failure (SF) Condition” Interrupt. If the user enables this
interrupt, then the XRT94L33 will generate an interrupt anytime the
Redundant Receive STS-3 TOH Processor block either declares or clears
the SF defect.
0 – Disables the “Change of SF Condition Interrupt”.
1 – Enables the “Change of SF Condition Interrupt”.
6
Change of SD
Condition
Interrupt Enable
R/W
Change of Signal Degrade (SD) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of Signal Degrade (SD) Condition” Interrupt. If the user enables this
interrupt, then the XRT94L33 will generate an interrupt anytime the
Redundant Receive STS-3 TOH Processor block either declares or clears
the SD defect.
0 – Disables the “Change of SD Condition Interrupt”.
1 – Enables the “Change of SD Condition Interrupt”.
5
Detection of
REI-L Interrupt
Enable
R/W
Detection of Line – Remote Error Indicator Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Declaration of Line – Remote Error Indicator” interrupt. If the user enables
this interrupt, then the XRT94L33 will generate an interrupt anytime the
Redundant Receive STS-3 TOH Processor block declares the “REI-L” defect.
0 – Disables the “Line - Remote Error Indicator” Interrupt.
1 – Enables the “Line – Remote Error Indicator” Interrupt.
4
Detection of B2
Error Interrupt
Enable
R/W
Detection of B2 Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of B2 Error” Interrupt. If the user enables this interrupt, then the
XRT94L33 will generate an interrupt anytime the Redundant Receive STS-3
TOH Processor block detects a B2 error.
0 – Disables the “Detection of B2 Error Interrupt”.
1 – Enables the “Detection of B2 Error Interrupt”.
3
Detection of B1
Error Interrupt
Enable
R/W
Detection of B1 Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of B1 Error” Interrupt. If the user enables this interrupt, then the
237
XRT94L33
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S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
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LD
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S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
XRT94L33 will generate an interrupt anytime the Redundant Receive STS-3
TOH Processor block detects a B1 error.
0 – Disables the “Detection of B1 Error Interrupt”.
1 – Enables the “Detection of B1 Error Interrupt”.
2
Change of LOF
Condition
Interrupt Enable
R/W
Change of Loss of Frame (LOF) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of LOF Condition” interrupt. If the user enables this interrupt, then
the XRT94L33 will generate an interrupt in response to either of the following
conditions.
• When the Redundant Receive STS-3 TOH Processor block declares the
“LOF” condition.
• When the Redundant Receive STS-3 TOH Processor clears the “LOF”
condition.
0 – Disables the “Change of LOF Condition Interrupt.
1 – Enables the “Change of LOF Condition” Interrupt.
1
Change of SEF
Condition
Interrupt Enable
R/W
Change of SEF Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of SEF Condition” Interrupt. If the user enables this interrupt, then
the XRT94L33 will generate an interrupt in response to either of the following
conditions.
• When the Redundant Receive STS-3 TOH Processor block declares the
“SEF” condition.
• When the Redundant Receive STS-3 TOH Processor block clears the
”SEF” condition.
0 – Disables the “Change of SEF Condition Interrupt”.
1 – Enables the “Change of SEF Condition Interrupt”.
0
Change of LOS
Condition
Interrupt Enable
R/W
Change of Loss of Signal (LOS) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of LOF Condition” interrupt. If the user enables this interrupt, then
the XRT94L33 will generate an interrupt in response to either of the following
conditions.
• When the Redundant Receive STS-3 TOH Processor block declares the
“LOF” condition.
• When the Redundant Receive STS-3 TOH Processor block clears the
“LOF” condition.
0 – Disables the “Change of LOF Condition Interrupt.
1 – Enables the “Change of LOF Condition” Interrupt.
238
XRT94L33
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NN
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 161: Redundant Receive STS-3 Transport – B1 Error Count Register – Byte 3 (Address
Location= 0x1710)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7-0
B1_Error_Count
[31:24]
RUR
DESCRIPTION
B1 Error Count – MSB:
This RESET-upon-READ register, along with “Redundant Receive Transport –
B1 Error Count Register – Bytes 2 through 0; function as a 32 bit counter,
which is incremented anytime the Redundant Receive STS-3 TOH Processor
block detects a B1 byte error.
Note:
1. If the B1 Error Type is configured to be “bit errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by the
number of bits, within the B1 value that are in error.
2. If the B1 Error Type is configured to be “frame errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by the
number of frames that contain erred B1 bytes.
Table 162: Redundant Receive STS-3 Transport – B1 Error Count Register – Byte 2 (Address
Location= 0x1711)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B1_Error_Count
[23:16]
RUR
DESCRIPTION
B1 Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Redundant Receive Transport –
B1 Error Count Register – Bytes 3, 1 and 0; function as a 32 bit counter, which
is incremented anytime the Redundant Receive STS-3 TOH Processor block
detects a B1 byte error.
Note:
1. If the B1 Error Type is configured to be “bit errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by the
number of bits, within the B1 value that are in error.
2. If the B1 Error Type is configured to be “frame errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by the
number of frames that contain erred B1 bytes.
239
XRT94L33
333---C
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 163: Redundant Receive STS-3 Transport – B1 Error Count Register – Byte 1 (Address
Location= 0x1712)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B1_Error_Count
[15:8]
RUR
DESCRIPTION
B1 Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Redundant Receive Transport
– B1 Error Count Register – Bytes 3, 2 and 0; function as a 32 bit counter,
which is incremented anytime the Redundant Receive STS-3 TOH
Processor block detects a B1 byte error
Note:
1. If the B1 Error Type is configured to be “bit errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by
the number of bits, within the B1 value that are in error.
2. If the B1 Error Type is configured to be “frame errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B1 bytes.
Table 164: Redundant Receive STS-3 Transport – B1 Error Count Register – Byte 0 (Address
Location= 0x1713)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B1_Error_Count
[7:0]
RUR
DESCRIPTION
B1 Error Count – LSB:
This RESET-upon-READ register, along with “Redundant Receive Transport
– B1 Error Count Register – Bytes 3 through 1; function as a 32 bit counter,
which is incremented anytime the Redundant Receive STS-3 TOH
Processor block detects a B1 byte error.
Note:
1. If the B1 Error Type is configured to be “bit errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by
the number of bits, within the B1 value that are in error.
2. If the B1 Error Type is configured to be “frame errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B1 bytes.
Table 165: Redundant Receive STS-3 Transport – B2 Error Count Register – Byte 3 (Address
Location= 0x1714)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
240
BIT 2
BIT 1
BIT 0
XRT94L33
333---C
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M
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P
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S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
B2_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count
[31:24]
RUR
DESCRIPTION
B2 Error Count – MSB:
This RESET-upon-READ register, along with “Redundant Receive STS-3
Transport – B2 Error Count Register – Bytes 2 through 0; function as a 32
bit counter, which is incremented anytime the Redundant Receive STS-3
TOH Processor block detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by
the number of bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B2 bytes.
Table 166: Redundant Receive STS-3 Transport – B2 Error Count Register – Byte 2 Address Location=
0x1715)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count
[23:16]
RUR
DESCRIPTION
B2 Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Redundant Receive STS-3
Transport – B2 Error Count Register – Bytes 3, 1 and 0; function as a 32 bit
counter, which is incremented anytime the Redundant Receive STS-3 TOH
Processor block detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by
the number of bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B2 bytes.
Table 167: Redundant Receive STS-3 Transport – B2 Error Count Register – Byte 1 (Address
Location= 0x1716)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
B2_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
241
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count
[15:8]
RUR
0
0
Rev222...000...000
0
0
DESCRIPTION
B2 Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Redundant Receive STS-3
Transport – B2 Error Count Register – Bytes 3, 2 and 0; function as a 32 bit
counter, which is incremented anytime the Redundant Receive STS-3 TOH
Processor block detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by
the number of bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B2 bytes.
Table 168: Redundant Receive STS-3 Transport – B2 Error Count Register – Byte 0 (Address
Location= 0x1717)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count[7:0]
RUR
DESCRIPTION
B2 Error Count – LSB:
This RESET-upon-READ register, along with “Redundant Receive
Transport – B2 Error Count Register – Bytes 3 through 1; function as a
32 bit counter, which is incremented anytime the Redundant Receive
STS-3 TOH Processor block detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the Redundant
Receive STS-3 TOH Processor block will increment this 32 bit counter by
the number of bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B2 bytes.
Table 169: Redundant Receive STS-3 Transport – REI-L Error Count Register – Byte 3 (Address
Location= 0x1718)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
REI_L_Error_Count[31:24]
242
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M
A
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A
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T
E
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CH
HA
AN
NN
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LD
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S333///E
E333///S
ST
TS
S---111 T
TO
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ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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Rev222...000...000
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count
[31:24]
RUR
DESCRIPTION
REI-L Error Count – MSB:
This RESET-upon-READ register, along with “Redundant Receive
Transport – REI-L Error Count Register – Bytes 2 through 0; function
as a 32 bit counter, which is incremented anytime the Redundant
Receive STS-3 TOH Processor block detects a Line - Remote Error
Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this
32 bit counter by the value within the REI-L fields of the M1 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this
32 bit counter by the number of frames that contain non-zero REI-L
values.
Table 170: Redundant Receive STS-3 Transport – REI_L Error Count Register – Byte 2 (Address
Location= 0x1719)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_L_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
REI_L_Error_Count
[23:16]
RUR
REI-L Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Redundant Receive
Transport – REI-L Error Count Register – Bytes 3, 1 and 0; function as
a 32 bit counter, which is incremented anytime the Redundant Receive
STS-3 TOH Processor block detects a Line – Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32
bit counter by the value within the REI-L fields of the M1 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32
bit counter by the number of frames that contain non-zero REI-L values.
Table 171: Redundant Receive STS-3 Transport – REI_L Error Count Register – Byte 1 (Address
Location= 0x171A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_L_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
243
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A
N
N
E
L
D
S
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S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count[15:8]
RUR
Rev222...000...000
DESCRIPTION
REI-L Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Redundant Receive
Transport – REI-L Error Count Register – Bytes 3, 2 and 0; function
as a 32 bit counter, which is incremented anytime the Redundant
Receive STS-3 TOH Processor block detects a Line –Remote
Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Redundant Receive STS-3 TOH Processor block will increment
this 32 bit counter by the value within the REI-L fields of the M1
byte.
2. If the REI-L Error Type is configured to be “frame errors”, then
the Redundant Receive STS-3 TOH Processor block will increment
this 32 bit counter by the number of frames that contain non-zero
REI-L values.
Table 172: Redundant Receive STS-3 Transport – REI_L Error Count Register – Byte 0 (Address
Location= 0x171B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_L_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count
[7:0]
RUR
DESCRIPTION
REI-L Error Count – LSB:
This RESET-upon-READ register, along with “Redundant Receive
Transport – REI-L Error Count Register – Bytes 3 through 1; function as a
32 bit counter, which is incremented anytime the Redundant Receive
STS-3 TOH Processor block detects a Line – Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32 bit
counter by the value within the REI-L fields of the M1 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then the
Redundant Receive STS-3 TOH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-L values.
Table 173: Redundant Receive STS-3 Transport K1 Value (Address Location= 0x171F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Filtered_K1_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Filtered_K1_Value[7:0]
R/O
DESCRIPTION
Filtered/Accepted K1 Value:
These READ-ONLY bit-fields contain the value of the most recently
244
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T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
“filtered” K1 value, that the Redundant Receive STS-3 TOH Processor
block has received. These bit-fields are valid if the K1/K2 pair (to which
it belongs) has been received for 3 consecutive STS-3 frames.
This register should be polled by Software in order to determine various
APS codes.
Table 174: Redundant Receive STS-3 Transport K2 Value (Address Location= 0x1723)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Filtered_K2_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Filtered_K2_Value
[7:0]
R/O
DESCRIPTION
Filtered/Accepted K2 Value:
These READ-ONLY bit-fields contain the value of the most recently
“filtered” K2 value, that the Redundant Receive STS-3 TOH Processor
block has received. These bit-fields are valid if the K1/K2 pair (to which
it belongs) has been received for 3 consecutive STS-3 frames.
This register should be polled by Software in order to determine various
APS codes.
Table 175: Redundant Receive STS-3 Transport S1 Value (Address Location= 0x1727)
BIT 7
BIT 6
BIT 5
BIT 4
R/O
R/O
R/O
R/O
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/O
R/O
R/O
R/O
0
0
0
0
Filtered_S1_Value[7:0]
BIT NUMBER
NAME
TYPE
7–0
Filtered_S1_Value[7:0]
R/O
DESCRIPTION
Filtered/Accepted S1 Value:
These READ-ONLY bit-fields contain the value of the most recently
“filtered” S1 value that the Redundant Receive STS-3 TOH Processor
block has received. These bit-fields are valid if it has been received
for 8 consecutive STS-3 frames.
Table 176: Redundant
Location=0x172B)
BIT 7
BIT 6
Receive
BIT 5
Unused
STS-3
BIT 4
Transport
BIT 3
–
In-Sync
Threshold
BIT 2
FRPATOUT[1:0]
BIT 1
FRPATIN[1:0]
Value
(Address
BIT 0
Unused
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–5
Unused
R/O
4–3
FRPATOUT[1:0]
R/W
DESCRIPTION
Framing Pattern – SEF Declaration Criteria:
These two READ/WRITE bit-fields permit the user to define the SEF
245
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Declaration criteria for the Redundant Receive STS-3 TOH Processor block.
The relationship between the state of these bit-fields and the corresponding
SEF Declaration Criteria are presented below.
FRPATOUT[1:0]
SEF Declaration Criteria
00
The Redundant Receive STS-3 TOH Processor
block will declare an SEF condition if either of the
following conditions are true for four consecutive
SONET frame periods.
01
•
If the last (of the 3) A1 bytes, in the STS-3 data
stream is erred, or
•
If the first (of the 3) A2 bytes, in the STS-3 data
stream, is erred.
Hence, for this selection, a total of 16 bits are
evaluated for SEF declaration.
10
The Redundant Receive STS-3 TOH Processor
block will declare an SEF condition if either of the
following conditions are true for four consecutive
SONET frame periods.
•
If the last two (of the 3) A1 bytes, in the STS-3
data stream, are erred, or
•
If the first two (of the 3) A2 bytes, in the STS-3
data stream, are erred.
Hence, for this selection, a total of 32 bits are
evaluated for SEF declaration.
11
The Redundant Receive STS-3 TOH Processor
block will declare an SEF condition if either of the
following conditions are true for four consecutive
SONET frame periods.
•
If the last three (of the 3) A1 bytes, in the STS3 data stream, are erred, or
•
If the first three (of the 3) A2 bytes, in the STS3 data stream, are erred.
Hence, for this selection, a total of 48 bits are
evaluated for SEF declaration.
2-1
FRPATIN[1:0]
R/W
Framing Pattern – SEF Clearance Criteria:
These two READ/WRITE bit-fields permit the user to define the “SEF
Clearance” criteria for the Redundant Receive STS-3 TOH Processor block.
The relationship between the state of these bit-fields and the corresponding
SEF Clearance Criteria are presented below.
FRPATIN[1:0]
SEF Clearance Criteria
00
The Redundant Receive STS-3 TOH Processor
bl k ill l
h SEF
di i
if b h f h
246
XRT94L33
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A
N
N
E
L
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S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
evaluated for SEF clearance.
10
The Redundant Receive STS-3 TOH Processor
block will clear the SEF condition if both of the
following conditions are true for two consecutive
SONET frame periods.
•
If the last two (of the 3) A1 bytes, in the STS-3
data stream, are un-erred, and
•
If the first two (of the 3) A2 bytes, in the STS-3
data stream, are un-erred.
Hence, for this selection, a total of 32 bits/frame are
evaluated for SEF clearance.
11
The Redundant Receive STS-3 TOH Processor
block will clear the SEF condition if both of the
following conditions are true for two consecutive
SONET frame periods.
•
If the last three (of the 3) A1 bytes, in the STS-3
data-stream, are un-erred, and
•
If the first three (of the 3) A2 bytes, in the STS3 data stream, are un-erred.
Hence, for this selection, a total of 48 bits/frame are
evaluated for SEF declaration.
0
Unused
R/O
247
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M
M
A
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A
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M
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G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 177: Redundant Receive STS-3 Transport – LOS Threshold Value - MSB (Address Location=
0x172E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOS_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
LOS_THRESHOLD[15:8]
R/W
DESCRIPTION
LOS Threshold Value – MSB:
These READ/WRITE bits, along the contents of the “Redundant
Receive STS-3 Transport – LOS Threshold Value – LSB” register
specify the number of consecutive (All Zero) bytes that the
Redundant Receive STS-3 TOH Processor block must detect before
it can declare an LOS condition.
Table 178: Redundant Receive STS-3 Transport – LOS Threshold Value - LSB (Address Location=
0x172F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOS_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
LOS_THRESHOLD[7:0]
R/W
DESCRIPTION
LOS Threshold Value – LSB:
These READ/WRITE bits, along the contents of the “Redundant
Receive STS-3 Transport – LOS Threshold Value – MSB” register
specify the number of consecutive (All Zero) bytes that the Redundant
Receive STS-3 TOH Processor block must detect before it can declare
an LOS condition.
248
XRT94L33
333---C
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 179: Redundant Receive STS-3 Transport –Receive SF SET Monitor Interval – Byte 2 (Address
Location= 0x1731)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_MONITOR_WINDOW[23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
SF_SET_MONITOR_
WINDOW [23:16]
R/W
SF_SET_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the “Redundant
Receive STS-3 Transport – SF SET Monitor Interval – Byte 1 and
Byte 0” registers permit the user to specify the number of STS-3
Frame periods that will constitute a SET Sub-Interval for SF (Signal
Failure).
When the Redundant Receive STS-3 TOH Processor block is
checking for SF, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors exceeds
that of programmed into the “Redundant Receive STS-3 Transport
SF SET Threshold” register, then an SF condition will be declared.
Table 180: Redundant Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 1 (Address
Location= 0x1732)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_SET_MONITOR_WINDOW[15:8]
BIT
NUMBER
NAME
TYPE
7-0
SF_SET_MONITOR_WINDOW
[15:8]
R/W
DESCRIPTION
SF_SET_MONITOR_INTERVAL (Bits 15 through 8):
These READ/WRITE bits, along the contents of the “Redundant
Receive STS-3 Transport – SF SET Monitor Interval – Byte 2
and Byte 0” registers permit the user to specify the number of
STS-3 Frame periods that will constitute a SET Sub-Interval for
SF (Signal Failure).
When the Redundant Receive STS-3 TOH Processor block is
checking for SF, it will accumulate B2 bit errors for a total of 8
SET Sub-Interval periods. If the number of accumulated B2 bit
errors exceeds that of programmed into the “Redundant Receive
STS-3 Transport SF SET Threshold” register, then an SF
condition will be declared.
249
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M
A
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A
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S
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E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 181: Redundant Receive STS-3 Transport – Receive SF SET Monitor Interval – Byte 0 (Address
Location= 0x1733)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_MONITOR_WINDOW[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_SET_MONITOR_WINDOW[7:0]
R/W
DESCRIPTION
SF_SET_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SF SET
Monitor Interval – Byte 2 and Byte 1” registers permit
the user to specify the number of STS-3 Frame periods
that will constitute a SET Sub-Interval for SF (Signal
Failure).
When the Redundant Receive STS-3 TOH Processor
block is checking for SF, it will accumulate B2 bit errors
for a total of 8 SET Sub-Interval periods. If the number
of accumulated B2 bit errors exceeds that of
programmed into the “Redundant Receive STS-3
Transport SF SET Threshold” register, then an SF
condition will be declared.
Table 182: Redundant Receive STS-3 Transport – Receive SF SET Threshold – Byte 1 (Address
Location= 0x1736)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_SET_THRESHOLD[15:8]
R/W
DESCRIPTION
SF_SET_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SF SET Threshold –
Byte 0” registers permit the user to specify the number of B2
bit errors that will cause the Redundant Receive STS-3 TOH
Processor block to declare an SF (Signal Failure) condition.
When the Redundant Receive STS-3 TOH Processor block is
checking for SF, it will accumulate B2 errors for a total of 8
SET Sub-Interval periods. If the number of accumulated B2
errors exceeds that of programmed into this and the
“Redundant Receive STS-3 Transport SF SET Threshold –
Byte 0” register, then an SF condition will be declared.
Table 183: Redundant Receive STS-3 Transport – Receive SF SET Threshold – Byte 0 Address
Location= 0x1737)
250
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N
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M
M
A
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R
A
T
M
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T
E
R
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NN
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LD
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S333///E
E333///S
ST
TS
S---111 T
TO
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ST
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S---333///S
ST
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M---111 M
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BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_SET_THRESHOLD[7:
0]
R/W
DESCRIPTION
SF_SET_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the “Redundant
Receive STS-3 Transport – SF SET Threshold – Byte 1” registers
permit the user to specify the number of B2 bit errors that will
cause the Redundant Receive STS-3 TOH Processor block to
declare an SF (Signal Failure) condition.
When the Redundant Receive STS-3 TOH Processor block is
checking for SF, it will accumulate B2 errors for a total of 8 SET
Sub-Interval periods. If the number of accumulated B2 errors
exceeds that of programmed into this and the “Redundant Receive
STS-3 Transport SF SET Threshold – Byte 1” register, then an SF
condition will be declared.
Table 184: Redundant Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 1 (Address
Location= 0x173A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_CLEAR_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_THRESHOLD
[15:8]
R/W
DESCRIPTION
SF_CLEAR_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SF CLEAR Threshold
– Byte 0” registers permit the user to specify the upper limit for
the number of B2 bit errors that will cause the Redundant
Receive STS-3 TOH Processor block to clear the SF (Signal
Failure) condition.
When the Redundant Receive STS-3 TOH Processor block is
checking for clearing SF, it will accumulate B2 errors for a total
of 8 CLEAR Sub-Interval periods.
If the number of
accumulated B2 errors is less than that programmed into this
and the “Redundant Receive STS-3 Transport SF CLEAR
Threshold – Byte 0” register, then an SF condition will be
cleared.
Table 185: Redundant Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 0 (Address
Location= 0x173B)
BIT 7
BIT 6
BIT 5
R/W
R/W
R/W
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
SF_CLEAR_THRESHOLD[7:0]
R/W
R/W
251
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M---111 M
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AN
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LD
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S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_THRESHOLD
[7:0]
R/W
1
1
Rev222...000...000
1
1
DESCRIPTION
SF_CLEAR_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SF CLEAR Threshold
– Byte 1” registers permit the user to specify the upper limit for
the number of B2 bit errors that will cause the Redundant
Receive STS-3 TOH Processor block to clear the SF (Signal
Failure) condition.
When the Redundant Receive STS-3 TOH Processor block is
checking for clearing SF, it will accumulate B2 errors for a total
of 8 CLEAR Sub-Interval periods.
If the number of
accumulated B2 errors is less than that programmed into this
and the “Redundant Receive STS-3 Transport SF CLEAR
Threshold – Byte 1” register, then an SF condition will be
cleared.
Table 186: Redundant Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 2 (Address
Location= 0x173D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_SET_MONITOR_WINDOW[23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
SD_SET_MONITOR_WINDOW
[23:16]
R/W
DESCRIPTION
SF_SET_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SF SET
Monitor Interval – Byte 1 and Byte 0” registers permit
the user to specify the number of STS-3 Frame periods
that will constitute a SET Sub-Interval for SD (Signal
Degrade) declaration.
When the Redundant Receive STS-3 TOH Processor
block is checking for SD, it will accumulate B2 bit errors
for a total of 8 SET Sub-Interval periods. If the number
of accumulated B2 bit errors exceeds that of
programmed into the “Redundant Receive STS-3
Transport SD SET Threshold” register, then an SD
condition will be declared.
Table 187: Redundant Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 1 (Address
Location= 0x173E)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
SD_SET_MONITOR_WINDOW[15:8]
252
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AN
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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RS
S
Rev222...000...000
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
SD_SET_MONITOR_WINDOW[15:8]
R/W
SD_SET_MONITOR_INTERVAL – Bits 15 through 8:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD SET
Monitor Interval – Byte 2 and Byte 0” registers permit
the user to specify the number of STS-3 Frame periods
that will constitute a SET Sub-Interval for SD (Signal
Degrade) declaration.
When the Redundant Receive STS-3 TOH Processor
block is checking for SD, it will accumulate B2 bit errors
for a total of 8 SET Sub-Interval periods. If the number
of accumulated B2 bit errors exceeds that of
programmed into the “Redundant Receive STS-3
Transport SD SET Threshold” register, then an SD
condition will be declared.
Table 188: Redundant Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 0 (Address
Location= 0x173F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_SET_MONITOR_WINDOW[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
SD_SET_MONITOR_WINDOW[
7:0]
R/W
DESCRIPTION
SD_SET_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD SET Monitor
Interval – Byte 2 and Byte 1” registers permit the user to
specify the number of STS-3 Frame periods that will
constitute a SET Sub-Interval for SD (Signal Degrade)
declaration.
When the Redundant Receive STS-3 TOH Processor
block is checking for SD, it will accumulate B2 bit errors
for a total of 8 SET Sub-Interval periods. If the number of
accumulated B2 bit errors exceeds that of programmed
into the “Redundant Receive STS-3 Transport SD SET
Threshold” register, then an SD condition will be declared.
Table 189: Redundant Receive STS-3 Transport – Receive SD SET Threshold – Byte 1 (Address
Location= 0x1742)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SD_SET_THRESHOLD[15:8]
BIT NUMBER
NAME
TYPE
DESCRIPTION
253
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M---111 M
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MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
7-0
SD_SET_THRESHOLD[15:8]
R/W
Rev222...000...000
SD_SET_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD SET Threshold –
Byte 0” registers permit the user to specify the number of B2
bit errors that will cause the Redundant Receive STS-3 TOH
Processor block to declare an SD (Signal Degrade) condition.
When the Redundant Receive STS-3 TOH Processor block is
checking for SD, it will accumulate B2 errors for a total of 8
SET Sub-Interval periods. If the number of accumulated B2
errors exceeds that of programmed into this and the
“Redundant Receive STS-3 Transport SD SET Threshold –
Byte 0” register, then an SD condition will be declared.
Table 190: Redundant Receive STS-3 Transport – Receive SD SET Threshold – Byte 0 (Address
Location= 0x1743)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
1
1
1
SD_SET_THRESHOLD[7:0]
BIT NUMBER
NAME
TYPE
7-0
SD_SET_THRESHOLD[7:0]
R/W
DESCRIPTION
SD_SET_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD SET Threshold –
Byte 1” registers permit the user to specify the number of B2
bit errors that will cause the Redundant Receive STS-3 TOH
Processor block to declare an SD (Signal Degrade) condition.
When the Redundant Receive STS-3 TOH Processor block is
checking for SD, it will accumulate B2 errors for a total of 8
SET Sub-Interval periods. If the number of accumulated B2
errors exceeds that of programmed into this and the
“Redundant Receive STS-3 Transport SD SET Threshold –
Byte 1” register, then an SD condition will be declared.
254
XRT94L33
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S
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T
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S
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M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 191: Redundant Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 1 (Address
Location= 0x1746)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_THRESHOLD[15:8]
R/W
DESCRIPTION
SD_CLEAR_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD CLEAR
Threshold – Byte 0” registers permit the user to specify the
upper limit for the number of B2 bit errors that will cause the
Redundant Receive STS-3 TOH Processor block to clear
the SD (Signal Degrade) condition.
When the Redundant Receive STS-3 TOH Processor block
is checking for clearing SD, it will accumulate B2 errors for a
total of 8 CLEAR Sub-Interval periods. If the number of
accumulated B2 errors is less than that programmed into
this and the “Redundant Receive STS-3 Transport SD
CLEAR Threshold – Byte 0” register, then an SD condition
will be cleared.
Table 192: Redundant Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 1 (Address
Location= 0x1747)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_THRESHOLD[7:0]
R/W
DESCRIPTION
SD_CLEAR_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD CLEAR Threshold
– Byte 1” registers permit the user to specify the upper limit for
the number of B2 bit errors that will cause the Redundant
Receive STS-3 TOH Processor block to clear the SD (Signal
Degrade) condition.
When the Redundant Receive STS-3 TOH Processor block is
checking for clearing SD, it will accumulate B2 errors for a total
of 8 CLEAR Sub-Interval periods.
If the number of
accumulated B2 errors is less than that programmed into this
and the “Redundant Receive STS-3 Transport SD CLEAR
Threshold – Byte 1” register, then an SD condition will be
cleared.
Table 193: Redundant Receive STS-3 Transport – Force SEF Condition Register (Address Location=
0x174B)
255
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A
N
N
E
L
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S
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S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Rev222...000...000
BIT 1
BIT 0
Unused
SEF FORCE
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–1
Unused
R/O
0
SEF FORCE
R/W
DESCRIPTION
SEF Force:
This READ/WRITE bit-field permits the user to force the Redundant
Receive STS-3 TOH Processor block to declare an SEF defect. The
Redundant Receive STS-3 TOH Processor block will then attempt to
reacquire framing.
Writing a “1” into this bit-field configures the Redundant Receive STS-3
TOH Processor block to declare the SEF defect. The Redundant Receive
STS-3 TOH Processor block will automatically set this bit-field to “0” once it
has reacquired framing (e.g., has detected two consecutive STS-3 frames
with the correct A1 and A2 bytes).
Table 194: Redundant Receive STS-3 Transport – Receive J0 Trace Buffer Control Register (Address
Location= 0x174F)
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
BIT 2
READ SEL
ACCEPT
THRD
MSG TYPE
BIT 1
BIT 0
MSG LENGTH
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–5
Unused
R/O
4
READ SEL
R/W
DESCRIPTION
Receive Section Trace (J0) Message Buffer Read Selection:
This READ/WRITE bit-field permits a user to specify which of the following
buffer segments to read.
k.
Valid Message Buffer
l.
Expected Message Buffer
0 – Executing a READ to the Receive Section Trace (J0) Message Buffer, will
return contents within the “Valid Message” buffer.
1 – Executing a READ to the Receive Section Trace (J0) Message Buffer, will
return contents within the “Expected Message Buffer”.
Note:
3
ACCEPT THRD
R/W
In the case of the Redundant Receive STS-3 TOH Processor block,
the “Receive J0 Trace Buffer” is located at Address location 0x1300
through 0x133F.
Message Accept Threshold:
This READ/WRITE bit-field permits a user to select the number of consecutive
times that the Redundant Receive STS-3 TOH Processor block must receive a
given Section Trace Message, before it is accepted, as described below.
256
XRT94L33
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A
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P
E
R
A
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M
R
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S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
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PE
ER
R ––– A
AT
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MR
RE
EG
GIIIS
ST
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RS
S
Rev222...000...000
0 – The Redundant Receive STS-3 TOH Processor block accepts the Section
Message after it has received it the third time in succession.
1 – The Redundant Receive STS-3 TOH Processor block accepts the Section
Message after it has received in the fifth time in succession.
2
MSG TYPE
R/W
Message Alignment Type:
This READ/WRITE bit-field permits a user to specify how the Redundant
Receive STS-3 TOH Processor block will locate the boundary of the incoming
Section Trace Message, as indicated below.
0 – The Section Trace Message boundary is indicated by “Line Feed”.
1 – The Section Trace Message boundary is indicated by the presence of a “1”
in the MSB of the first byte (within the J0 Trace Message).
1-0
MSG LENGTH
R/W
J0 Message Length:
These READ/WRITE bit-fields permit the user to specify the length of the J0
Trace Message that the Redundant Receive STS-3 TOH Processor block will
receive. The relationship between the content of these bit-fields and the
corresponding J0 Trace Message Length is presented below.
MSG LENGTH
Resulting J0 Trace Message Length
00
1 Byte
01
16 Bytes
10/11
64 Bytes
Table 195: Redundant Receive STS-3 Transport – Receive SD Burst Error Tolerance – Byte 1 (Address
Location= 0x1752)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_BURST_TOLERANCE[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_BURST_
TOLERANCE
[15:8]
R/W
DESCRIPTION
SD_BURST_TOLERANCE – MSB:
These READ/WRITE bits, along with the contents of the “Redundant
Receive STS-3 Transport – SD BURST Tolerance – Byte 0” registers permit
the user to specify the maximum number of B2 bit errors that the Redundant
Receive STS-3 TOH Processor block can accumulate during a single SubInterval period (e.g., an STS-3 frame period), when determining whether or
not to declare an SD (Signal Degrade) defect condition.
Note:
The purpose of this feature is to permit the user to provide some
level of B2 error burst filtering, when the Redundant Receive STS3 TOH Processor block is accumulating B2 byte errors in order to
declare the SD defect condition. The user can implement this
feature in order to configure the Redundant Receive STS-3 TOH
Processor block to detect B2 bit errors in multiple “Sub-Interval”
periods before it will declare the SD defect condition.
Table 196: Redundant Receive STS-3 Transport – Receive SD Burst Error Tolerance – Byte 0 (Address
Location= 0x1753)
257
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M
A
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R
S
C
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
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M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Rev222...000...000
BIT 2
BIT 1
BIT 0
SD_BURST_TOLERANCE[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_BURST_
TOLERANCE
[7:0]
R/W
DESCRIPTION
SD_BURST_TOLERANCE – LSB:
These READ/WRITE bits, along with the contents of the “Redundant Receive
STS-3 Transport – SD BURST Tolerance – Byte 1” registers permit the user to
specify the maximum number of B2 bit errors that the Redundant Receive
STS-3 TOH Processor block can accumulate during a single Sub-Interval
period (e.g., an STS-3 frame period), when determining whether or not to
declare an SD (Signal Degrade) defect condition.
Note:
The purpose of this feature is to permit the user to provide some level
of B2 error burst filtering, when the Redundant Receive STS-3 TOH
Processor block is accumulating B2 byte errors in order to declare
the SD defect condition. The user can implement this feature in
order to configure the Redundant Receive STS-3 TOH Processor
block to detect B2 bit errors in multiple “Sub-Interval” periods before
it will declare the SD defect condition.
Table 197: Redundant Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 1 (Address
Location= 0x1756)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_BURST_TOLERANCE[15:8]
BIT NUMBER
NAME
TYPE
7-0
SF_BURST_
TOLERANCE
[15:8]
R/W
DESCRIPTION
SF_BURST_TOLERANCE – MSB:
These READ/WRITE bits, along with the contents of the “Redundant Receive
STS-3 Transport – SF BURST Tolerance – Byte 0” registers permit the user to
specify the maximum number of B2 bit errors that the Redundant Receive
STS-3 TOH Processor block can accumulate during a single Sub-Interval
period (e.g., an STS-3 frame period), when determining whether or not to
declare an SF (Signal Failure) defect condition.
Note:
The purpose of this feature is to permit the user to provide some level
of B2 error burst filtering, when the Redundant Receive STS-3 TOH
Processor block is accumulating B2 byte errors in order to declare
the SF defect condition. The user can implement this feature in
order to configure the Redundant Receive STS-3 TOH Processor
block to detect B2 bit errors in multiple “Sub-Interval” periods before
it will declare the SF defect condition.
Table 198: Redundant Receive STS-3 Transport – Receive SF Burst Error Tolerance – Byte 0 (Address
Location= 0x1757)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
SF_BURST_TOLERANCE[7:0]
258
BIT 2
BIT 1
BIT 0
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1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_BURST_
TOLERANCE
[7:0]
R/W
DESCRIPTION
SF_BURST_TOLERANCE – LSB:
These READ/WRITE bits, along with the contents of the “Redundant Receive
STS-3 Transport – SF BURST Tolerance – Byte 1” registers permit the user to
specify the maximum number of B2 bit errors that the Redundant Receive
STS-3 TOH Processor block can accumulate during a single Sub-Interval
period (e.g., an STS-3 frame period), when determining whether or not to
declare an SF (Signal Failure) defect condition.
Note:
The purpose of this feature is to permit the user to provide some level
of B2 error burst filtering, when the Redundant Receive STS-3 TOH
Processor block is accumulating B2 byte errors in order to declare
the SF defect condition. The user can implement this feature in
order to configure the Redundant Receive STS-3 TOH Processor
block to detect B2 bit errors in multiple “Sub-Interval” periods before
it will declare the SF defect condition.
Table 199: Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 2 (Address
Location= 0x1759)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_MONITOR_WINDOW[23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_MONITOR_WINDOW[23:
16]
R/W
DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD Clear
Monitor Interval – Byte 1 and Byte 0” registers permit
the user to specify the number of STS-3 Frame
periods that will constitute a CLEAR Sub-Interval for
SD (Signal Degrade).
When the Redundant Receive STS-3 TOH Processor
block is checking for clearing the SD defect, it will
accumulate B2 errors for a total of 8 SET Sub-Interval
periods. If the number of accumulated B2 errors is
less than that of programmed into the “Redundant
Receive STS-3 Transport SD Clear Threshold”
register, then the SD defect will be cleared.
Table 200: Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1 (Address
Location= 0x175A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_MONITOR_WINDOW[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
259
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SD_CLEAR_MONITOR_WINDOW[15:8]
R/W
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DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL
through 8:
–
Bits
15
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD Clear
Monitor Interval – Byte 2 and Byte 0” registers permit
the user to specify the number of STS-3 Frame
periods that will constitute a CLEAR Sub-Interval for
SD (Signal Degrade).
When the Redundant Receive STS-3 TOH
Processor block is checking for clearing the SD
defect, it will accumulate B2 errors for a total of 8
SET Sub-Interval periods.
If the number of
accumulated B2 errors is less than that of
programmed into the “Redundant Receive STS-3
Transport SD Clear Threshold” register, then the SD
defect will be cleared.
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Table 201: Redundant Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0 (Address
Location= 0x175B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_MONITOR_WINDOW[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_MONITOR_WINDOW[
7:0]
R/W
DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SD Clear Monitor
Interval – Byte 2 and Byte 1” registers permit the user to
specify the number of STS-3 Frame periods that will
constitute a CLEAR Sub-Interval for SD (Signal Degrade).
When the Redundant Receive STS-3 TOH Processor
block is checking for clearing the SD defect, it will
accumulate B2 errors for a total of 8 SET Sub-Interval
periods. If the number of accumulated B2 errors is less
than that of programmed into the “Redundant Receive
STS-3 Transport SD Clear Threshold” register, then the
SD defect will be cleared.
Table 202: Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 2 (Address
Location= 0x175D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_CLEAR_MONITOR_WINDOW[23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_MONITOR_WINDO
W [23:16]
R/W
DESCRIPTION
SF_CLEAR_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SF Clear Monitor
Interval – Byte 1 and Byte 0” registers permit the user to
specify the number of STS-3 Frame periods that will
constitute a CLEAR Sub-Interval for SF (Signal Failure).
When the Redundant Receive STS-3 TOH Processor block
is checking for clearing the SF defect, it will accumulate B2
errors for a total of 8 SET Sub-Interval periods. If the
number of accumulated B2 errors is less than that of
programmed into the “Redundant Receive STS-3 Transport
SF Clear Threshold” register, then the SF defect will be
cleared.
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Table 203: Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 1 (Address
Location= 0x175E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_CLEAR_MONITOR_WINDOW[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
SF_CLEAR_MONITOR_WINDOW
[15:8]
R/W
SF_CLEAR_MONITOR_INTERVAL – Bits 15 through
8:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SF Clear
Monitor Interval – Byte 2 and Byte 0” registers permit
the user to specify the number of STS-3 Frame periods
that will constitute a CLEAR Sub-Interval for SF (Signal
Failure).
When the Redundant Receive STS-3 TOH Processor
block is checking for clearing the SF defect, it will
accumulate B2 errors for a total of 8 SET Sub-Interval
periods. If the number of accumulated B2 errors is less
than that of programmed into the “Redundant Receive
STS-3 Transport SF Clear Threshold” register, then the
SF defect will be cleared.
Table 204: Redundant Receive STS-3 Transport – Receive SF Clear Monitor Interval – Byte 0 (Address
Location= 0x175F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_CLEAR_MONITOR_WINDOW[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_MONITOR_WINDOW
[7:0]
R/W
DESCRIPTION
SF_CLEAR_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SF Clear
Monitor Interval – Byte 2 and Byte 1” registers permit
the user to specify the number of STS-3 Frame periods
that will constitute a CLEAR Sub-Interval for SF (Signal
Failure).
When the Redundant Receive STS-3 TOH Processor
block is checking for clearing the SF defect, it will
accumulate B2 errors for a total of 8 SET Sub-Interval
periods. If the number of accumulated B2 errors is less
than that of programmed into the “Redundant Receive
STS-3 Transport SF Clear Threshold” register, then the
SF defect will be cleared.
262
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Table 205: Redundant Receive STS-3 Transport – Auto AIS Control Register (Address Location=
0x1763)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit
AIS-P
(Downstream)
Upon J0
Message
Unstable
Transmit
AIS-P
(Downstream)
Upon J0
Message
Mismatch
Transmit
AIS-P
(Downstream)
Upon SF
Transmit
AIS-P
(Downstream)
Upon SD
Transmit
AIS-P
(Downstream)
upon Loss
of Optical
Carrier AIS
Transmit
AIS-P
(Downstream)
upon LOF
Transmit
AIS-P
(Downstream)
upon LOS
Transmit
AIS-P
(Downstream)
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
7
NAME
TYPE
Transmit AIS-P
(Down-stream)
upon J0 Message
Unstable
R/W
DESCRIPTION
Transmit Path AIS upon Detection of Unstable Section Trace (J0):
This READ/WRITE bit-field permits the user to configure the Redundant
Receive STS-3 TOH Processor block to automatically transmit a Path
AIS (AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Receive SONET POH Processor blocks), anytime it detects an Unstable
Section Trace (J0) condition in the “incoming” STS-3 data-stream.
0 – Does not configure the Redundant Receive STS-3 TOH Processor
block to automatically transmit the AIS-P indicator (via the “downstream”
traffic) whenever it detects an “Unstable Section Trace” condition.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator (via the “downstream” traffic)
whenever it detects an “Unstable Section Trace” condition.
Note:
6
Transmit AIS-P
(Down-stream)
Upon J0 Message
Mismatch
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Redundant Receive STS-3 TOH Processor
block to automatically transmit the AIS-P indicator, in
response to this defect condition.
Transmit Path AIS (AIS-P) upon Detection of Section Trace (J0)
Message Mismatch:
This READ/WRITE bit-field permits the user to configure the Redundant
Receive STS-3 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the Receive
SONET POH Processor blocks), anytime it detects a Section Trace (J0)
Message Mismatch condition in the “incoming” STS-3 data stream.
0 – Does not configure the Redundant Receive STS-3 TOH Processor
block to automatically transmit the AIS-P indicator (via the “downstream”
traffic) whenever it detects a “Section Trace Message Mismatch”
condition.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) whenever it
detects a “Section Trace Message Mismatch” condition.
Note:
5
Transmit AIS-P
(Down-stream) upon
SF
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Redundant Receive STS-3 TOH Processor block
to automatically transmit the AIS-P indicator, in response to this
defect condition.
Transmit Path AIS upon Signal Failure (SF):
This READ/WRITE bit-field permits the user to configure the Redundant
Receive STS-3 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the Receive
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SONET POH Processor blocks), anytime it declares an SF condition.
0 – Does not configure the Redundant Receive STS-3 TOH Processor
block to transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the SF defect.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the SF defect.
Note:
4
Transmit AIS-P
(Down-stream) upon
SD
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Redundant Receive STS-3 TOH Processor block
to automatically transmit the AIS-P indicator, in response to this
defect condition.
Transmit Path AIS upon Signal Degrade (SD):
This READ/WRITE bit-field permits the user to configure the Redundant
Receive STS-3 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the Receive
SONET POH Processor blocks), anytime it declares an SD condition.
0 – Does not configure the Redundant Receive STS-3 TOH Processor
block to transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the SD defect.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the SD defect.
Note:
3
Transmit AIS-P
(Down-stream) upon
Loss of Optical
Carrier
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Redundant Receive STS-3 TOH Processor block
to automatically transmit the AIS-P indicator, in response to this
defect condition.
Transmit Path AIS upon Loss of Optical Carrier condition:
This READ/WRITE bit-field permits the user to configure the Redundant
Receive STS-3 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the Receive
SONET POH Processor blocks), anytime it detects a “Loss of Optical
Carrier” condition.
0 – Does not configure the Redundant Receive STS-3 TOH Processor
block to transmit the AIS-P indicator upon detection of a “Loss of Optical
Carrier” condition.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
transmit the AIS-P indicator upon detection of a “Loss of Optical Carrier”
condition.
Note:
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Redundant Receive STS-3 TOH Processor block
to automatically transmit the AIS-P indicator, in response to this
defect condition.
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2
Transmit AIS-P
(Down-stream) upon
LOF
R/W
Transmit Path AIS upon Loss of Frame (LOF):
This READ/WRITE bit-field permits the user to configure the Redundant
Receive STS-3 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the Receive
SONET POH Processor block), anytime it declares an LOF condition.
0 – Does not configure the Redundant Receive STS-3 TOH Processor
block to transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the LOF defect.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the LOF defect.
Note:
1
Transmit AIS-P
(Down-stream) upon
LOS
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Redundant Receive STS-3 TOH Processor block
to automatically transmit the AIS-P indicator, in response to this
defect condition.
Transmit Path AIS upon Loss of Signal (LOS):
This READ/WRITE bit-field permits the user to configure the Redundant
Receive STS-3 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the Receive
SONET POH Processor block), anytime it declares an LOS condition.
0 – Does not configure the Redundant Receive STS-3 TOH Processor
block to transmit the AIS-P indicator (via the “downstream” traffic) anytime
it declares the LOS defect.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) anytime it
declares the LOS defect.
Note:
0
Transmit AIS-P
(Down-stream)
Enable
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1” to
configure the Redundant Receive STS-3 TOH Processor block
to automatically transmit the AIS-P indicator, in response to this
defect condition.
Automatic Transmission of AIS-P Enable:
This READ/WRITE bit-field serves two purposes.
It permits the user to configure the Redundant Receive
Processor block to automatically transmit the Path
indicator, via the down-stream traffic (e.g., towards
SONET POH Processor blocks), upon detection of
Section Trace Mismatch, Section Trace Unstable, LOF,
of Optical Carrier conditions.
STS-3 TOH
AIS (AIS-P)
the Receive
an SF, SD,
LOS or Loss
It also permits the user to configure the Redundant Receive STS-3 TOH
Processor block to automatically transmit a Path AIS (AIS-P)
Indicator via the “downstream” traffic (e.g., towards the Receive
SONET POH Processor blocks) anytime it detects an AIS-L condition
in the “incoming “ STS-3 data-stream.
0 – Configures the Redundant Receive STS-3 TOH Processor block to
NOT automatically transmit the AIS-P indicator (via the “downstream”
traffic) upon detection of the AIS-L or any of the “above-mentioned”
conditions.
1 – Configures the Redundant Receive STS-3 TOH Processor block to
automatically transmit the AIS-P indicator (via the “downstream” traffic)
upon detection of any of the “above-mentioned” condition.
Note:
The user must also set the corresponding bit-fields (within this
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S---333///S
ST
Rev222...000...000
register) to “1” in order to configure the Redundant Receive
STS-3 TOH Processor block to automatically transmit the AIS-P
indicator upon detection of a given alarm/defect condition.
Table 206: Redundant Receive STS-3 Transport – Serial Port Control Register (Address Location=
0x1767)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
RxTOH_CLOCK_SPEED[7:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7-4
Unused
R/O
3-0
RxTOH_CLOCK_SPEED[7:0]
R/W
DESCRIPTION
RxTOHClk Output Clock Signal Speed:
These READ/WRITE bit-fields permit the user to specify the
frequency of the “RxTOHClk output clock signal.
The formula that relates the contents of these register bits to
the “RxTOHClk” frequency is presented below.
FREQ = 19.44 /[2 * (RxTOH_CLOCK_SPEED + 1)
Note:
266
For STS-3/STM-1 applications, the frequency of the
RxTOHClk output signal must be in the range of
0.6075MHz to 9.72MHz
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 207: Redundant Receive STS-3 Transport – Auto AIS (in Downstream STS-1s) Control Register
(Address Location= 0x176B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Unused
Transmit
AIS-P (via
Downstream
STS-1s)
upon LOS
Transmit
AIS-P (via
Downstream
STS-1s)
upon LOF
Transmit
AIS-P (via
Downstream
STS-1s)
upon SD
Transmit
AIS-P (via
Downstream
STS-1s)
upon SF
AIS-L
Output
Enable
Transmit
AIS-P (via
Downstream
STS-1s)
Enable
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
TYPE
7-6
Unused
R/O
5
Transmit AIS-P (via
Downstream STS-1s)
upon LOS
R/W
DESCRIPTION
Transmit AIS-P (via Downstream STS-1s) upon LOS (Loss of
Signal):
This READ/WRITE bit-field permits the user to configure the Transmit
STS-1 POH Processor blocks (in each channel) to automatically transmit
the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals,
anytime the Redundant Receive STS-3 TOH Processor block declares
the LOS defect.
0 – Does not configure all “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor
block declares the LOS defect.
1 – Configures all “activated” Transmit STS-1POH Processor blocks to
automatically transmit the AIS-P Indicator via the “downstream” STS-1
signals, anytime the Redundant Receive STS-3 TOH Processor block
declares the LOS defect.
Note:
1. In the “long-run” the function of this bit-field is exactly the same as that
of Bit 1 (Transmit AIS-P Down-stream – Upon LOS), within the
Redundant Receive STS-3 Transport – Auto AIS Control Register
(Address Location= 0x1763). The only difference is that this register bit
will cause each of the “downstream” Transmit STS-1 POH Processor
blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever
the Redundant Receive STS-3 TOH Processor block declares the LOS
defect. This will permit the user to easily comply with the Telcordia GR253-CORE requirements of an NE transmitting the AIS-P indicator
downstream within 125us of the NE declaring the LOS defect.
2. In the case of Bit 1 (Transmit AIS-P Downstream – Upon LOS),
several SONET frame periods are required (after the Redundant Receive
STS-3 TOH Processor block has declared the LOS defect), before the
Transmit STS-1 POH Processor blocks will begin the process of
transmitting the AIS-P indicators.
3.In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
4
Transmit AIS-P (via
Downstream STS-1s)
upon LOF
R/W
Transmit AIS-P (via Downstream STS-1s) upon LOF (Loss of
Frame):
267
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
This READ/WRITE bit-field permits the user to configure the Transmit
STS-1 POH Processor blocks (in each channel) to automatically transmit
the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals,
anytime the Redundant Receive STS-3 TOH Processor block declares
the LOF defect.
0 – Does not configures all “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor
block declares the LOF defect.
1 – Configures all “activated” Transmit STS-1POH Processor blocks to
automatically transmit the AIS-P Indicator via the “downstream” STS-1
signals, anytime the Redundant Receive STS-3 TOH Processor block
declares the LOF defect.
Note:
1. In the “long-run” the function of this bit-field is exactly the same as that
of Bit 2 (Transmit AIS-P Down-stream – Upon LOF), within the
Redundant Receive STS-3 Transport – Auto AIS Control Register
(Address Location= 0x1763). The only difference is that this register bit
will cause each of the “downstream” Transmit STS-1 POH Processor
blocks to IMMEDIATELY begin to transmit the AIS-P condition whenever
the Redundant Receive STS-3 TOH Processor block declares the LOF
defect. This will permit the user to easily comply with the Telcordia GR253-CORE requirements of an NE transmitting the AIS-P indicator
downstream within 125us of the NE declaring the LOF defect.
2. In the case of Bit 2 (Transmit AIS-P Downstream – Upon LOF),
several SONET frame periods are required (after the Redundant Receive
STS-3 TOH Processor block has declared the LOS defect), before the
Transmit STS-1 POH Processor blocks will begin the process of
transmitting the AIS-P indicators.
3. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
3
Transmit AIS-P (via
Downstream STS-1s)
upon SD
R/W
Transmit AIS-P (via Downstream STS-1s) upon SD (Signal Degrade):
This READ/WRITE bit-field permits the user to configure the Transmit
STS-1 POH Processor blocks (in each channel) to automatically transmit
the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals,
anytime the Redundant Receive STS-3 TOH Processor block declares
the SD defect.
0 – Does not configures all “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor
block declares the SD defect.
1 – Configures all “activated” Transmit STS-1POH Processor blocks to
automatically transmit the AIS-P Indicator via the “downstream” STS-1
signals, anytime the Redundant Receive STS-3 TOH Processor block
declares the SD defect.
Note:
1.In the “long-run” the function of this bit-field is exactly the same as that
of Bit 4 (Transmit AIS-P Down-stream – Upon SD), within the Redundant
Receive STS-3 Transport – Auto AIS Control Register (Address
Location= 0x1763). The only difference is that this register bit will cause
each of the “downstream” Transmit STS-1 POH Processor blocks to
IMMEDIATELY begin to transmit the AIS-P condition whenever the
Redundant Receive STS-3 TOH Processor block declares the SD defect.
This will permit the user to easily comply with the Telcordia GR-253CORE requirements of an NE transmitting the AIS-P indicator
268
XRT94L33
Rev222...000...000
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
downstream within 125us of the NE declaring the LOS defect.
2. In the case of Bit 1 (Transmit AIS-P Downstream – Upon LOF),
several SONET frame periods are required (after the Redundant Receive
STS-3 TOH Processor block has declared the SD defect), before the
Transmit STS-1 POH Processor blocks will begin the process of
transmitting the AIS-P indicators.
3. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
2
Transmit AIS-P (via
Downstream STS-1s)
upon SF
R/W
Transmit AIS-P (via Downstream STS-1s) upon Signal Failure (SF):
This READ/WRITE bit-field permits the user to configure the Transmit
STS-1 POH Processor blocks (in each channel) to automatically transmit
the AIS-P (Path AIS) Indicator via the “downstream” STS-1 signals,
anytime the Redundant Receive STS-3 TOH Processor block declares
an SF condition.
0 – Does not configures all “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signals, anytime the Redundant Receive STS-3 TOH Processor
block declares the SF defect.
1 – Configures all “activated” Transmit STS-1POH Processor blocks to
automatically transmit the AIS-P Indicator via the “downstream” STS-1
signals, anytime the Redundant Receive STS-3 TOH Processor block
declares the SF defect.
Note:
1. In the “long-run” the function of this bit-field is exactly the same as that
of Bit 5 (Transmit AIS-P Down-stream – Upon SF), within the Redundant
Receive STS-3 Transport – Auto AIS Control Register (Address
Location= 0x1763). The only difference is that this register bit will cause
each of the “downstream” Transmit STS-1 POH Processor blocks to
IMMEDIATELY begin transmit the AIS-P condition whenever the
Redundant Receive STS-3 TOH Processor block declares the SF defect.
This will permit the user to easily comply with the Telcordia GR-253CORE requirements of an NE transmitting the AIS-P indicator
downstream within 125us of the NE declaring the SF defect.
2. In the case of Bit 5 (Transmit AIS-P Downstream – Upon SF), several
SONET frame periods are required (after the Redundant Receive STS-3
TOH Processor block has declared the SF defect), before the Transmit
STS-1 POH Processor blocks will begin the process of transmitting the
AIS-P indicators.
3. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
1
AIS-L Output Enable
R/W
AIS-L Output Enable:
This READ/WRITE bit-field, along with Bits 7 (8kHz or STUFF Out
Enable) within the “Operation Output Control Register – Byte 1” (Address
Location= 0x0150) permit the user to configure the “AIS-L” indicator to be
output via the “LOF” output pin (pin AD11).
If Bit 7 (within the “Operation Output Control Register – Byte 1”) is set to
“0”, then setting this bit-field to “1” configures pin AD11 to function as the
AIS-L output indicator.
If Bit 7 (within the “Operation Output Control Register – Byte 1”) is set to
“0”, then setting this bit-field to “0” configures pin AD11 to function as the
LOF output indicator.
If Bit 7 (within the “Operation Output Control Register – Byte 1) is set to
269
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
“1”, then this register bit is ignored.
0
Transmit AIS-P (via
Downstream STS-1s)
Enable
R/W
Automatic Transmission of AIS-P (via the downstream STS-1s)
Enable:
This READ/WRITE bit-field permits the user to configure all “activated”
Transmit STS-1 POH Processor blocks to automatically transmit the AISP indicator, via its “outbound” STS-1 signals, upon detection of an SF,
SD, LOS and LOF condition.
0 – Does not configure the “activated” Transmit STS-1 POH Processor
blocks to automatically transmit the AIS-P indicator, whenever the
Redundant Receive STS-3 TOH Processor block declares either the
LOS, LOF, SD or SF defects.
1 – Configures the “activated” Transmit STS-1 POH Processor blocks to
automatically transmit the AIS-P indicator, whenever the Redundant
Receive STS-3 TOH Processor block declares either the LOS, LOF, SD
or SF defects.
1.8
TRANSMIT ATM CELL PROCESSOR BLOCK
270
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
The register map for the Transmit ATM Cell Processor Block is presented in the Table below. Additionally, a
detailed description of each of the “Transmit ATM Cell Processor” block registers is presented below.
In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the
XRT94L33 device, with the “Transmit ATM Cell Processor Blocks “highlighted” is presented below in
Figure 9.
Figure 9: Illustration of the Functional Block Diagram of the XRT94L33 device, with the Transmit ATM
Cell Processor Block “High-lighted”.
From Channels 1 & 2
Tx
Tx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Rx
Rx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Clock
Clock
Synthesizer
Synthesizer
Block
Block
Tx
TxCell
Cell
Processor
Processor
Block
Block
Tx
TxPLCP
PLCP
Processor
Processor
Block
Block
Tx
TxPPP
PPP
Processor
Processor
Block
Block
Tx
TxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Tx
TxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Tx
TxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxPPP
PPP
Processor
Processor
Block
Block
Rx
RxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
RxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Rx
RxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxCell
Cell
Processor
Processor
Block
Block
Rx
RxPLCP
PLCP
Processor
Processor
Block
Block
Channel 0
To Channel 1 & 2
271
Tx
TxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
Tx
TxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Tx
TxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Rx
RxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Clock
Clock&&
Data
Data
Recovery
Recovery
Block
Block
Rx
RxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Rx
RxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.8.1
Rev222...000...000
TRANSMIT ATM CELL PROCESSOR BLOCK REGISTER
Table 208: Transmit ATM Cell Processor Block Register Address Map
TRANSMIT ATM CELL PROCESSOR/ PPP PROCESSOR BLOCK REGISTERS
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04
0xNF00
Transmit ATM Cell Processor Control Register – Byte 3
0x00
0xNF01
Transmit ATM Cell Processor Control Register – Byte 2
0x00
0xNF02
Transmit ATM Cell Processor Control Register – Byte 1
0x00
0xNF03
Transmit ATM Cell/PPP Processor Control Register – Byte 0
0x00
0xNF04
Transmit ATM Status Register
0x00
Reserved
0x00
Transmit ATM Cell/PPP Processor Interrupt Status Register
0x00
Reserved
0x00
Transmit ATM Cell/PPP Processor Interrupt Enable Register
0x00
Reserved
0x00
0xNF13
Transmit ATM Cell Insertion/Extraction Memory Control Register
0x00
0xNF14
Transmit ATM Cell Insertion/Extraction Memory – Byte 3
0x00
0xNF15
Transmit ATM Cell Insertion/Extraction Memory – Byte 2
0x00
0xNF16
Transmit ATM Cell Insertion/Extraction Memory – Byte 1
0x00
0xNF17
Transmit ATM Cell Insertion/Extraction Memory – Byte 0
0x00
0xNF18
Transmit ATM Cell – Idle Cell Header Byte # 1 Register
0x00
0xNF19
Transmit ATM Cell – Idle Cell Header Byte # 2 Register
0x00
0xNF1A
Transmit ATM Cell – Idle Cell Header Byte # 3 Register
0x00
0xNF1B
Transmit ATM Cell – Idle Cell Header Byte # 4 Register
0x00
Reserved
0x00
0xNF1F
Transmit ATM Cell – Idle Cell Payload Byte Register
0x00
0xNF20
Transmit ATM Cell – Test Cell Header Byte # 1 Register
0x00
0xNF21
Transmit ATM Cell – Test Cell Header Byte # 2 Register
0x00
0xNF22
Transmit ATM Cell – Test Cell Header Byte # 3 Register
0x00
0xNF23
Transmit ATM Cell – Test Cell Header Byte # 4 Register
0x00
Reserved
0x00
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF05 –
0xNF0A
0xNF0B
0xNF0C –
0xNF0E
0xNF0F
0xNF10 –
0xNF12
0xNF1C –
0xNF1E
0xNF24 –
0xNF27
0xNF28
272
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xNF29
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF2A
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF2B
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
0xNF2C
Transmit ATM Cell – Discard Cell Count Register – Byte 3
0x00
0xNF2D
Transmit ATM Cell – Discard Cell Count Register – Byte 2
0x00
0xNF2E
Transmit ATM Cell – Discard Cell Count Register – Byte 1
0x00
0xNF2F
Transmit ATM Cell – Discard Cell Count Register – Byte 0
0x00
0xNF30
Transmit ATM Cell – HEC Byte Error Count Register – Byte 3
0x00
0xNF31
Transmit ATM Cell – HEC Byte Error Count Register – Byte 2
0x00
0xNF32
Transmit ATM Cell – HEC Byte Error Count Register – Byte 1
0x00
0xNF33
Transmit ATM Cell – HEC Byte Error Count Register – Byte 0
0x00
0xNF34
Transmit ATM Cell – Parity Error Count Register – Byte 3
0x00
0xNF35
Transmit ATM Cell – Parity Error Count Register – Byte 2
0x00
0xNF36
Transmit ATM Cell – Parity Error Count Register – Byte 1
0x00
0xNF37
Transmit ATM Cell – Parity Error Count Register – Byte 0
0x00
Reserved
0x00
0xNF43
Transmit ATM Controller – Transmit ATM Filter # 0 Control Register
0x00
0xNF44
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 1
0x00
0xNF45
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 2
0x00
0xNF46
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 3
0x00
0xNF47
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 4
0x00
0xNF48
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 1
0x00
0xNF49
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 2
0x00
0xNF4A
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 3
0x00
0xNF4B
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 4
0x00
0xNF4C
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF4D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF4E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF4F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF53
Transmit ATM Controller – Transmit ATM Filter # 1 Control Register
0x00
0xNF54
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 1
0x00
0xNF38 –
0xNF42
0xNF50 –
0xNF52
273
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0xNF55
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 2
0x00
0xNF56
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 3
0x00
0xNF57
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 4
0x00
0xNF58
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 1
0x00
0xNF59
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 2
0x00
0xNF5A
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 3
0x00
0xNF5B
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 4
0x00
0xNF5C
Transmit ATM Cell – Cell Count Register - Byte 3
0x00
0xNF5D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF5E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF5F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF63
Transmit ATM Controller – Transmit ATM Filter # 2 Control Register
0x00
0xNF64
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 1
0x00
0xNF65
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 2
0x00
0xNF66
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 3
0x00
0xNF67
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 4
0x00
0xNF68
Transmit ATM Controller – Transmit ATM Filter # 2 Check – Header Byte 1
0x00
0xNF69
Transmit ATM Controller – Transmit ATM Filter # 2 Check – Header Byte 2
0x00
0xNF6A
Transmit ATM Controller – Transmit ATM Filter # 2 Check – Header Byte 3
0x00
0xNF6B
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 4
0x00
0xNF6C
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF6D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF6E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF6F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF73
Transmit ATM Controller – Transmit ATM Filter # 3 Control Register
0x00
0xNF74
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 1
0x00
0xNF75
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 2
0x00
0xNF76
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 3
0x00
0xNF77
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 4
0x00
0xNF78
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 1
0x00
0xNF60 –
0xNF62
0xNF70 –
0xNF72
274
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L
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E
S
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S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xNF79
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 2
0x00
0xNF7A
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 3
0x00
0xNF7B
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 4
0x00
0xNF7C
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF7D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF7E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF7F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF80 –
0xN102
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M
A
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P
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A
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R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.8.2
Rev222...000...000
TRANSMIT ATM CELL PROCESSOR BLOCK REGISTER DESCRIPTION
Table 209: Transmit ATM Cell Processor Block – Transmit ATM Control Register – Byte 3 (Address =
0xNF00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Table 210: Transmit ATM Cell Processor Block – Transmit ATM Control Register – Byte 2 (Address =
0xNF01)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit ATM Cell
Processor Enable
Unused
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-1
Unused
R/O
0
Transmit ATM Cell
Processor Enable
R/W
DESCRIPTION
Transmit ATM Cell Processor Block Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the Transmit ATM Cell Processor block. If the user wishes to operate a
given Channel in the ATM Mode, then he/she must enable the Transmit
ATM Cell Processor Block.
0 – Disables the Transmit ATM Cell Processor Block
1 – Enables the Transmit ATM Cell Processor Block
Note:
The user must set this bit-field to “1” before he/she begins to
write ATM cell data into the Transmit UTOPIA Interface block.
276
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N
E
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E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 211: Transmit ATM Cell Processor Block – Transmit ATM Control Register – Byte 1 (Address =
0xNF02)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Test Cell
Transmit
Mode
Enable
ONE SHOT
MODE
GFC
Insertion
Enable - Bit
3
GFC
Insertion
Enable – Bit
2
GFC
Insertion
Enable – Bit
1
GFC
Insertion
Enable – Bit
0
COSET
Polynomial
Addition
Regenerate
HEC Byte
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Test Cell Transmit
Mode Enable
R/W
DESCRIPTION
Test Cell Transmit Mode Enable:
This READ/WRITE bit-field permits the user to enable the Test Cell
Transmitter (within the Transmit ATM Cell Processor Block). The user
must implement this configuration option in order to perform diagnostic
operations with Test Cells.
0 – Disables the Test Cell Transmitter.
1 – Enables the Test Cell Transmitter.
Notes:
6
One Shot Mode
R/W
For normal operation, the user should set this bit-field to “1”.
One Shot Mode:
If the user has enabled the Test Cell Transmitter, then this
READ/WRITE bit-field permits the user to either configure the Test Cell
Transmitter into the “One-Shot” or in the “Continuous” Mode.
If the user configures the Test Cell Transmitter into the “One-Shot”
Mode, then (whenever the user implements a “0 to 1” transition within
Bit 7 [Test Cell Transmit Mode Enable] of this register) then the Test
Cell Transmitter will generate and transmit 1024 test cells. Afterwards,
the Test Cell Transmitter will halt its transmission of Test Cells until the
user implements another “0 to 1 transition” within Bit 7 (Test Cell
Transmit Mode Enable) within this register.
If the user configures the Test Cell Transmitter into the “Continuous”
Mode, then the Test Cell Transmitter will continuously generate and
transmit test cells for the duration that Bit 7(Test Cell Transmit Mode
Enable) is set to “1”.
0 – Configures the Test Cell Transmitter to operate in the “Continuous”
Mode.
1 – Configures the “Test Cell Transmitter” to operate in the “One-Shot”
Mode.
5
GFC Insertion
Enable – Bit 3
R/W
4
GFC Insertion
Enable – Bit 2
R/W
3
GFC Insertion
Enable – Bit 1
R/W
2
GFC Insertion
Enable – Bit 0
R/W
1
COSET Polynomial
Addition
R/W
COSET Polynomial Addition:
This READ/WRITE bit-field permits the user to configure the Transmit
ATM Cell Processor block to modulo-add the COSET Polynomial (e.g.,
x^6 + x^4 + x^2 + 1) to the HEC byte value, within each “outbound”
277
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E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
ATM cell.
0 – Configures the Transmit ATM Cell Processor block to NOT
modulo-add the COSET Polynomial to the HEC byte within each
outbound ATM cell.
1 – Configures the Transmit ATM Cell Processor block to modulo-add
the COSET Polynomial to the HEC byte within each outbound ATM
cell.
0
Regenerate HEC
Byte Enable
R/W
Regenerate HEC Byte Enable:
This READ/WRITE bit-field permits the user to configure the Transmit
ATM Cell Processor block to automatically re-compute and insert a
new HEC byte into each ATM cell (that it receives from the Transmit
UTOPIA Interface block) that contains an uncorrectable HEC byte.
0 – Does not configure the Transmit ATM Cell Processor block to
compute and insert a new HEC byte into ATM cells that contains an
“uncorrectable” HEC Byte error.
1 – Configures the Transmit ATM Cell Processor block to compute and
insert a new HEC byte into ATM cells that contains an “uncorrectable”
HEC Byte error.
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N
E
L
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E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 212: Transmit ATM Cell Processor Block – Transmit ATM Control – Byte 0 (Address = 0xNF03)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
HEC Byte
Invert
HEC Byte
Check
Enable
Transmit
UTOPIA
Parity
Check
Enable
Transmit
UTOPIA
Parity Error
– Discard
Transmit
UTOPIA –
ODD Parity
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
HEC Byte Invert
R/W
HEC Byte Invert:
6
HEC Byte Check Enable
R/W
HEC Byte Check Enable:
BIT 2
BIT 1
BIT 0
Scrambler
Enable
Reserved
DESCRIPTION
This READ/WRITE bit-field permits the user to configure the
Transmit ATM Cell Processor block to perform HEC byte checking
of all ATM cells that it receives via the Transmit UTOPIA Interface
block.
0 – Configures the Transmit ATM Cell Processor block to NOT
perform HEC byte checking on all ATM cells that it receives via
the Transmit UTOPIA Interface block.
1 – Configures the Transmit ATM Cell Processor block to perform
HEC byte checking on all ATM cells that it receives via the
Transmit UTOPIA Interface block.
5
Transmit UTOPIA Parity
Check Enable
R/W
Transmit UTOPIA Parity Check Enable:
This READ/WRITE bit-field permits the user to either enable or
disable “Transmit UTOPIA Interface” Parity checking.
If the user enables “Transmit UTOPIA Interface” Parity Checking,
then the Transmit ATM Cell Processor block will compute either
the EVEN or ODD parity value (depending upon the setting of Bit
3 within this register) of each byte or 16-bit word that is input via
the Transmit UTOPIA Data Bus input pins: (TxUData[15:0]).
Afterwards, the Transmit ATM Cell Processor block will compare
this “locally computed” parity value with that which the ATM Layer
Processor has provided to the “TxUPrty” input pin. If the Transmit
ATM Cell Processor detects any discrepancies between these two
parity values (e.g., any parity errors) then it will take action based
upon the user’s settings for Bit 4 (Transmit UTOPIA Parity Error –
Discard).
0 – Disables “Transmit UTOPIA Interface” Parity Checking.
1 – Enables “Transmit UTOPIA Interface” Parity Checking.
4
Transmit UTOPIA Parity
Error - Discard
R/W
Transmit UTOPIA Parity Error – Discard Cell:
This READ/WRITE bit-field permits the user to configure the
Transmit ATM Cell Processor block to either discard or retain (for
further processing) any ATM cell that contains a “Transmit
UTOPIA Interface” parity error.
0 – Configures the Transmit ATM Cell Processor block to retain
(for further processing) all cells that contain “Transmit UTOPIA
Interface” parity errors.
1 – Configures the Transmit ATM Cell Processor block to discard
all cells that contain “Transmit UTOPIA Interface” parity errors.
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A
T
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G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Notes:
3
Transmit UTOPIA – Odd
Parity
R/W
Rev222...000...000
This bit-field is only valid if “Transmit UTOPIA Interface”
Parity Checking has been enabled.
Transmit UTOPIA Parity Value – ODD Parity:
This READ/WRITE bit-field permits the user to configure the
Transmit ATM Cell Processor block to compute either the EVEN
or ODD parity value for each byte or 16-bit word within each cell
that it processes. Each of these parity values will ultimately be
compared with the value that is input via the “TxUPrty” input pin
(on the Transmit UTOPIA Interface block) coincident to when ATM
cell data is being applied to the “TxUData[15:0]” input pins.
0 – Configures the Transmit ATM Cell Processor block to compute
and verify the EVEN Parity value of each byte (or 16-bit word) of
ATM cell data that it processes.
1 – Configures the Transmit ATM Cell Processor block to compute
and verify the ODD Parity value of each byte (or 16-bit word) of
ATM cell data that it processes.
Notes:
2-1
Reserved
0
Scrambler Enable
This bit-field is only value if “Transmit UTOPIA Interface”
Parity Checking has been enabled.
R/O
Cell Payload Scrambler Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the “Cell Payload Scrambler”. If the user enables the “Cell
Payload Scrambler” then the Transmit ATM Cell Processor will
payload self-synchronous scrambling on all cell payloads bytes
(within each outbound ATM cell) with the x^43+1 polynomial.
0 – Disables the Cell Payload Scrambler
1 – Enables the Cell Payload Scrambler
280
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 213: Transmit ATM Cell Processor Block – Transmit ATM Status Register (Address = 0xNF04)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
BIT 0
One Shot DONE
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-1
Unused
R/O
0
One Shot DONE
R/O
DESCRIPTION
One Shot DONE:
This READ-ONLY bit-field indicates whether or not the Test Cell
Transmitter has completed its transmission of 1024 test cells, following
the instant that the user has commanded the Test Cell to transmit this
burst of 1024 cells.
0 – Indicates that the Test Cell Transmitter has NOT completed its
transmission of 1024 test cells.
1 – Indicates that the Test Cell Transmitter has completed its
transmission of 1024 test cells since the last “Transmit Test Cell – One
Shot” command.
Notes:
1. This bit-field is only valid if (1) the Test Cell Transmitter is active
and (2) if the Test Cell Transmitter has been configured to operate in
the “One-Shot” Mode.
2. Once this bit-field has been set to “1”, it will remain at “1” until the
user executes another “Transmit Test Cell – One Shot” command.
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A
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S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 214: Transmit ATM Cell Processor Block – Transmit ATM Interrupt Status Register (Address =
0xNF0B)
BIT 7
BIT 6
Unused
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit
Cell
Extraction
Interrupt
Status
Transmit
Cell Insertion
Interrupt
Status
Transmit
Cell
Extraction
Memory
Overflow
Interrupt
Status
Transmit
Cell Insertion
Memory
Overflow
Interrupt
Status
Detection of
HEC Byte
Error
Interrupt
Status
Detection of
Transmit
UTOPIA
Parity Error
Interrupt
Status
R/O
R/O
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-6
Unused
R/O
5
Transmit Cell
Extraction Interrupt
Status
RUR
DESCRIPTION
Transmit Cell Extraction Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Transmit
Cell Extraction” interrupt has occurred since the last read of this
register.
The Transmit ATM Cell Processor block will generate the “Transmit Cell
Extraction” Interrupt anytime it receives an incoming ATM cell (from the
TxFIFO) and loads an ATM cell into the “Extraction Memory” Buffer.
0 – Indicates that the “Transmit Cell Extraction” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Transmit Cell Extraction” Interrupt has occurred
since the last read of this register.
4
Transmit Cell
Insertion Interrupt
Status
RUR
Transmit Cell Insertion Interrupt
This RESET-upon-READ bit-field indicates whether or not the “Transmit
Cell Insertion” interrupt has occurred since the last read of this register.
The Transmit ATM Cell Processor block will generate the “Transmit Cell
Insertion” Interrupt anytime a cell (residing in the Transmit Cell Insertion
Buffer) is read out of the “Transmit Cell Insertion Buffer” and is loaded
into the outbound ATM cell traffic.
0 – Indicates that the “Transmit Cell Insertion” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Transmit Cell Insertion” Interrupt has occurred
since the last read of this register.
3
Transmit Cell
Extraction Memory
Overflow Interrupt
Status
RUR
Transmit Cell Extraction Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Transmit
Cell Extraction Memory Overflow” Interrupt has occurred since the last
read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime an overflow event has occurred in the “Transmit Cell Extraction
Memory” Buffer.
0 – Indicates that the Transmit ATM Cell Processor block has NOT
declared the “Transmit Cell Extraction Memory Overflow” Interrupt since
the last read of this register.
1 – Indicates that the Transmit ATM Cell Processor block has declared
the “Transmit Cell Extraction Memory Overflow” interrupt since the last
282
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C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
read of this register.
2
Transmit Cell
Insertion Memory
Overflow Interrupt
Status
RUR
Transmit Cell Insertion Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Transmit
Cell Insertion Memory Overflow” Interrupt has occurred since the last
read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime an overflow event has occurred in the “Transmit Cell Insertion
Memory” Buffer.
0 – Indicates that the Transmit ATM Cell Processor block has NOT
declared the “Transmit Cell Insertion Memory Overflow” interrupt since
the last read of this register.
1 – Indicates that the Transmit ATM Cell Processor block has declared
the “Transmit Cell Insertion Memory Overflow” interrupt since the last
read of this register.
1
Detection of HEC
Byte Error Interrupt
RUR
Detection of HEC Byte Error Interrupt:
This RESET-upon-READ bit-field indicates whether or not the “Transmit
ATM Cell Processor block” has declared the “Detection of HEC Byte
Error” Interrupt since the last read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime it has received an ATM cell (from the TxFIFO) that contains a
HEC byte error.
0 – Indicates that the Transmit ATM Cell Processor block has NOT
declared the “Detection of HEC Byte Error” Interrupt since the last read
of this register.
1 – Indicates that the Transmit ATM Cell Processor block has declared
the “Detection of HEC Byte Error” Interrupt since the last read of this
register.
0
Detection of Transmit
UTOPIA Parity Error
Interrupt
Detection of Transmit UTOPIA Parity Error Interrupt:
This RESET-upon-READ bit-field indicates whether or not the “Transmit
ATM Cell Processor” block has declared the “Detection of Transmit
UTOPIA Parity Error” Interrupt since the last read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime it has received an ATM cell byte or 16-bit word (from the
Transmit UTOPIA Interface block) that contains a parity error.
0 – Indicates that the Transmit ATM Cell Processor block has NOT
declared the “Detection of Transmit UTOPIA Parity Error” Interrupt
since the last read of this register.
1 – Indicates that the Transmit ATM Cell Processor block has declared
the “Detection of Transmit UTOPIA Parity Error” Interrupt since the last
read of this register.
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M---111 M
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AT
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Table 215: Transmit ATM Cell Processor Block – Transmit ATM Interrupt Enable Register (Address =
0xNF0F)
BIT 7
BIT 6
Unused
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit
Cell
Extraction
Interrupt
Enable
Transmit
Cell Insertion
Interrupt
Enable
Transmit
Cell
Extraction
Memory
Overflow
Interrupt
Enable
Transmit
Cell Insertion
Memory
Overflow
Interrupt
Enable
Detection of
HEC Byte
Error
Interrupt
Enable
Detection of
Transmit
UTOPIA
Parity Error
Interrupt
Enable
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-6
Unused
5
Transmit Cell
Extraction
Interrupt Enable
TYPE
DESCRIPTION
R/W
Transmit Cell Extraction Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Transmit Cell Extraction” Interrupt.
If the user enables this feature, then the Transmit ATM Cell Processor block
will generate the “Transmit Cell Extraction” Interrupt anytime it receives an
incoming ATM cell (from the TxFIFO) and loads this ATM cell into the
“Transmit Extraction Memory” Buffer.
0 – Disables the “Transmit Cell Extraction” Interrupt.
1 – Enables the “Transmit Cell Extraction” Interrupt
4
Transmit Cell
Insertion
Interrupt Enable
R/W
Transmit Cell Insertion Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Transmit Cell Insertion” Interrupt.
If the user enables this feature, then the Transmit ATM Cell Processor block
will generate the “Transmit Cell Insertion” Interrupt anytime a cell (residing in
the “Transmit Cell Insertion” Buffer) is read out of the “Transmit Cell
Insertion” Buffer and is loaded into the “outbound” ATM cell traffic.
0 – Disables the Transmit Cell Insertion Interrupt.
1 – Enables the Transmit Cell Insertion Interrupt.
3
Transmit Cell
Extraction
Memory
Overflow
Interrupt Enable
R/W
Transmit Cell Extraction Memory Overflow Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Transmit Cell Extraction Memory Overflow” Interrupt.
If the user enables this interrupt, then the Transmit ATM Cell Processor block
will generate an interrupt any time an overflow event has occurred in the
“Transmit Cell Extraction Memory” buffer.
0 – Disables the Transmit Cell Extraction Memory Overflow Interrupt.
1 – Enables the Transmit Cell Extraction Memory Overflow Interrupt.
2
Transmit Cell
Insertion
Memory
Overflow
Interrupt Enable
R/W
Transmit Cell Insertion Memory Overflow Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Transmit Cell Insertion Memory Overflow” Interrupt.
If the user enables this interrupt, then the Transmit ATM Cell Processor block
will generate an interrupt any time an overflow event has occurred in the
“Transmit Cell Insertion Memory” buffer.
284
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Rev222...000...000
0 – Disables the Transmit Cell Insertion Memory Overflow Interrupt.
1 – Enables the Transmit Cell Insertion Memory Overflow Interrupt.
1
Detection of
HEC Byte Error
Interrupt Enable
R/W
Detection of HEC Byte Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of HEC Byte Error Interrupt” within the Transmit ATM Cell
Processor Block.
If the user enables this interrupt, then the Transmit ATM Cell Processor block
will generate an interrupt each time it receives an ATM cell (from the
TxFIFO) that contains a HEC Byte error.
0 – Disables the “Detection of HEC Byte Error” Interrupt.
1 – Enables the “Detection of HEC Byte Error” Interrupt
0
Detection of
Transmit
UTOPIA Parity
Error Interrupt
Enable
Detection of Transmit UTOPIA Parity Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of Transmit UTOPIA Parity Error” Interrupt within the Transmit
ATM Cell Processor block.
If the user enables this interrupt, then the Transmit ATM Cell Processor block
will generate an interrupt each time it receives an ATM cell byte or 16-bit
word (from the TxFIFO) that contains a parity error.
0 – Disables the “Detection of Transmit UTOPIA Parity Error” Interrupt.
1 – Enables the “Detection of Transmit UTOPIA Parity Error” Interrupt.
285
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
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Rev222...000...000
Table 216: Transmit ATM Cell Processor Block – Transmit ATM Cell Insertion/Extraction Memory
Control Register (0xNF13)
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Cell
Extraction
Memory
RESET*
Transmit Cell
Extraction
Memory
CLAV
Transmit Cell
Insertion
Memory
RESET*
Transmit Cell
Insertion
Memory
ROOM
Transmit Cell
Insertion
Memory
WSOC
R/O
R/O
R/O
R/W
R/O
R/W
R/O
W/O
0
0
0
1
0
1
0
0
BIT NUMBER
NAME
7-5
Unused
4
Transmit Cell Extraction
Memory RESET*
TYPE
R/W
DESCRIPTION
Transmit Cell Extraction Memory RESET*:
This READ/WRITE bit-field permits the user to perform a REST
operation to the Transmit Cell Extraction Memory.
If the user writes a “1-to-0 transition” into this bit-field, then the
following events will occur.
•
All of the contents of the Transmit Cell Extraction Memory will
be flushed.
•
All READ and WRITE pointers will be reset to their default
positions.
Notes:
3
Transmit Cell Extraction
Memory CLAV
R/O
Following this RESET event, the user must write the
value “1” into this bit-field in order to enable normal
operation within the Transmit Cell Extraction Memory.
Transmit Cell Extraction Memory – Cell Available Indicator:
This READ-ONLY bit-field indicates whether or not there is at least
ATM cell of data (residing within the Transmit Cell Extraction
Memory) that needs to be read out via the Microprocessor
Interface.
0 – Indicates that the Transmit Cell Extraction Memory is empty
and contains no ATM cell data.
1 – Indicates that the Transmit Cell Extraction Memory contains at
least one ATM cell of data that needs to be read out.
Notes:
2
Transmit Cell Insertion
Memory RESET*
R/W
The user should validate each ATM cell that is being
read out from the Transmit Cell Extraction memory by
checking the state of this bit-field prior to reading out the
contents of ATM cell data residing within the Transmit
Cell Extraction Memory
Transmit Cell Insertion Memory RESET*:
This READ/WRITE bit-field permits the user to perform a RESET
operation to the Transmit Cell Insertion Memory.
If the user writes a “1-to-0 transition” into this bit-field, then the
following events will occur.
•
All of the contents of the Transmit Cell Insertion Memory will
be flushed.
•
All READ and WRITE pointers will be reset to their default
positions.
Notes:
286
Following this RESET event, the user must write the
value “1” into this bit-field in order to enable normal
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TO
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M---111 M
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operation of the Transmit Cell Insertion Memory.
1
Transmit Cell Insertion
Memory ROOM
R/O
Transmit Cell Insertion Memory – ROOM Indicator:
This READ-ONLY bit-field indicates whether or not there is room
(e.g., empty space) available for the contents of another ATM cell
to be written into the Transmit Cell Insertion Memory.
0 – Indicates that the Transmit Cell Insertion Memory does not
contain enough empty space to receive another ATM cell via the
Microprocessor Interface.
1 – Indicates that the Transmit Cell Insertion Memory does contain
enough empty space to receive another ATM cell via the
Microprocessor Interface.
Notes:
0
Transmit Cell Insertion
Memory WSOC
W/O
The user should verify that the Transmit Cell Insertion
Memory has sufficient empty space to accept another
ATM cell of data (via the Microprocessor Interface) by
polling the state of this bit-field prior to writing each cell
into the Transmit Cell Insertion Memory.
Transmit Cell Insertion Memory – Write SOC (Start of Cell):
Whenever the user is writing the contents of an ATM cell into the
Transmit Cell Insertion Memory, then he/she is suppose to
identify/designate the very first byte of this ATM cell by setting this
bit-field to “1”. Whenever the user does this, then the Transmit Cell
Insertion Memory will “know” that the next octet that is written into
the “Transmit ATM Cell Processor Block – Transmit Cell
Insertion/Extraction Memory Data Register – Byte 3 (Address =
0xNF14) is designated as the first byte of the ATM cell currently
being written into the Transmit Cell Insertion Memory.
This bit-field must be set to “0” during all other WRITE operations
to the Transmit ATM Cell Processor – Transmit Cell
Insertion/Extraction Memory Data Register
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A
N
N
E
L
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S
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T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
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HA
AN
NN
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ST
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Rev222...000...000
Table 217: Transmit ATM Cell Processor Block – Transmit Cell Insertion/Extraction Memory Data –
Byte 3 (Address = 0xNF14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit Cell Insertion/Extraction Memory Data[31:24]
BIT NUMBER
NAME
TYPE
7-0
Transmit Cell
Insertion/Extraction
Memory Data[31:24]
R/W
DESCRIPTION
Transmit Cell Insertion/Extraction Memory Data[31:24]:
These READ/WRITE bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory Data – Bytes 2 through 0” support the following functions.
•
They function as the address location for the user to write the
contents of an “outbound” ATM cell into the Transmit Cell
Insertion Memory, via the Microprocessor Interface.
•
They function as the address location, for which the user to
read out the contents of an “inbound” ATM cell from the
Receive Cell Extraction Memory, via the Microprocessor
Interface.
Notes:
1. If the user performs a WRITE operation to this (and the other
three address locations), then he/she is writing ATM cell data into
the Transmit Cell Insertion Memory.
2. If the user performs a READ operation to this (and the other
three address locations), then he/she is reading ATM cell data from
the Transmit Cell Extraction Memory.
3. READ and WRITE operations must be performed in a “32-bit” (4byte “word”) manner. Hence, whenever the user performs a
READ/WRITE operation to these address locations, he/she must
start by writing in or reading out the first byte (of this “4-byte” word)
of a given ATM cell, into/from this particular address location.
Next, the user must perform the READ/WRITE operation (with the
second of this “4-byte” word) to the “Transmit ATM Cell Processor
Block – Transmit Cell Insertion/Extraction Memory – Byte 2
register. Afterwards, the user must perform a READ/WRITE
operation (with the third of this “4-byte” word) to the Transmit ATM
Cell Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 1 register. Finally, the user must perform a READ/WRITE
operation (with the fourth of this “4-byte” word) to the Transmit ATM
Cell Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 0 register. When reading out (writing in) the next four bytes of
a given ATM Cell, the user must repeat this process with a READ
or WRITE operation, from/to this register location, and so on.
4. Whenever the user is writing cell data into the Transmit Cell
Insertion Memory, the size of the Cell is always 56 bytes.
5. Whenever the user is reading cell data from the Transmit Cell
Extraction Memory, the size of the Cell is always 56 bytes.
288
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M
A
P
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A
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E
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S
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HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
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ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
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Rev222...000...000
Table 218: Transmit ATM Cell Processor Block – Transmit Cell Insertion/Extraction Memory Data –
Byte 2 (Address = 0xNF15)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit Cell Insertion/Extraction Memory Data[23:16]
BIT NUMBER
NAME
TYPE
7-0
Transmit Cell
Insertion/Extraction Memory
Data[23:16]
R/W
DESCRIPTION
Transmit Cell Insertion/Extraction Memory Data[23:16]:
These READ/WRITE bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory Data – Bytes 3, 1 and 0” support the following functions.
They function as the address location for the user to write the
contents of an “outbound” ATM cell into the Transmit Cell
Insertion Memory, via the Microprocessor Interface.
They function as the address location, for which the user to read
out the contents of an “inbound” ATM cell from the Receive Cell
Extraction Memory, via the Microprocessor Interface.
Notes:
1. If the user performs a WRITE operation to this (and the other
three address locations), then he/she is writing ATM cell data
into the Transmit Cell Insertion Memory.
2. If the user performs a READ operation to this (and the other
three address locations), then he/she is reading ATM cell data
from the Transmit Cell Extraction Memory.
3. READ and WRITE operations must be performed in a “32-bit”
(4-byte “word”) manner. Hence, whenever the user performs a
READ/WRITE operation to these address locations, he/she must
start by writing in or reading out the first byte (of this “4-byte”
word) of a given ATM cell, into/from the Transmit ATM Cell
Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 3” register. Next, the user must perform the READ/WRITE
operation (with the second of this “4-byte” word) to this particular
address location. Afterwards, the user must perform a
READ/WRITE operation (with the third of this “4-byte” word) to
the Transmit ATM Cell Processor Block – Transmit Cell
Insertion/Extraction Memory – Byte 1 register. Finally, the user
must perform a READ/WRITE operation (with the fourth of this
“4-byte” word) to the Transmit ATM Cell Processor Block –
Transmit Cell Insertion/Extraction Memory – Byte 0 register.
When reading out (writing in) the next four bytes of a given ATM
Cell, the user must repeat this process with a READ or WRITE
operation, from/to this register location, and so on.
4. Whenever the user is writing cell data into the Transmit Cell
Insertion Memory, the size of the Cell is always 56 bytes.
5. Whenever the user is reading cell data from the Transmit Cell
Extraction Memory, the size of the Cell is always 56 bytes.
289
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N
E
L
D
S
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T
S
T
O
S
T
S
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M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
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S333///E
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ST
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Rev222...000...000
Table 219: Transmit ATM Cell Processor Block – Transmit Cell Insertion/Extraction Memory Data –
Byte 1 (Address = 0xNF16)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit Cell Insertion/Extraction Memory Data[15:8]
BIT NUMBER
NAME
TYPE
7-0
Transmit Cell
Insertion/Extraction Memory
Data[15:8]
R/W
DESCRIPTION
Transmit Cell Insertion/Extraction Memory Data[15:8]:
These READ/WRITE bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory Data – Bytes 3, 2 and 0” support the following functions.
•
They function as the address location for the user to write
the contents of an “outbound” ATM cell into the Transmit
Cell Insertion Memory, via the Microprocessor Interface.
•
They function as the address location, for which the user to
read out the contents of an “inbound” ATM cell from the
Receive Cell Extraction Memory, via the Microprocessor
Interface.
Notes:
1. If the user performs a WRITE operation to this (and the other
three address locations), then he/she is writing ATM cell data
into the Transmit Cell Insertion Memory.
2. If the user performs a READ operation to this (and the other
three address locations), then he/she is reading ATM cell data
from the Transmit Cell Extraction Memory.
3. READ and WRITE operations must be performed in a “32-bit”
(4-byte “word”) manner. Hence, whenever the user performs a
READ/WRITE operation to these address locations, he/she must
start by writing in or reading out the first byte (of this “4-byte”
word) of a given ATM cell, into/from the Transmit ATM Cell
Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 3 register. Next, the user must perform the READ/WRITE
operation (with the second of this “4-byte” word) to the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory – Byte 2 register. Afterwards, the user must perform a
READ/WRITE operation (with the third of this “4-byte” word) to
this particular register location. Finally, the user must perform a
READ/WRITE operation (with the fourth of this “4-byte” word) to
the Transmit ATM Cell Processor Block – Transmit Cell
Insertion/Extraction Memory – Byte 0 register. When reading out
(writing in) the next four bytes of a given ATM Cell, the user must
repeat this process with a READ or WRITE operation, from/to
this register location, and so on.
4. Whenever the user is writing cell data into the Transmit Cell
Insertion Memory, the size of the Cell is always 56 bytes.
5. Whenever the user is reading cell data from the Transmit Cell
Extraction Memory, the size of the Cell is always 56 bytes.
290
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M
A
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A
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E
G
S
T
E
R
S
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HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
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ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
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Rev222...000...000
Table 220: Transmit ATM Cell Processor Block – Transmit Cell Insertion/Extraction Memory Data –
Byte 0 (Address = 0xNF17)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit Cell Insertion/Extraction Memory Data[7:0]
BIT NUMBER
NAME
TYPE
7-0
Transmit Cell
Insertion/Extraction
Memory Data[7:0]
R/W
DESCRIPTION
Transmit Cell Insertion/Extraction Memory Data[7:0]:
These READ/WRITE bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory Data – Bytes 3, through 1” support the following functions.
•
They function as the address location for the user to write the
contents of an “outbound” ATM cell into the Transmit Cell
Insertion Memory, via the Microprocessor Interface.
•
They function as the address location, for which the user to
read out the contents of an “inbound” ATM cell from the
Receive Cell Extraction Memory, via the Microprocessor
Interface.
Notes:
1. If the user performs a WRITE operation to this (and the other
three address locations), then he/she is writing ATM cell data into
the Transmit Cell Insertion Memory.
2. If the user performs a READ operation to this (and the other
three address locations), then he/she is reading ATM cell data from
the Transmit Cell Extraction Memory.
3. READ and WRITE operations must be performed in a “32-bit” (4byte “word”) manner. Hence, whenever the user performs a
READ/WRITE operation to these address locations, he/she must
start by writing in or reading out the first byte (of this “4-byte” word)
of a given ATM cell, into/from the Transmit ATM Cell Processor
Block – Transmit Cell Insertion/Extraction Memory – Byte 3
register. Next, the user must perform the READ/WRITE operation
(with the second of this “4-byte” word) to the “Transmit ATM Cell
Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 2 register. Afterwards, the user must perform a READ/WRITE
operation (with the third of this “4-byte” word) to the “Transmit ATM
Cell Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 1” register. Finally, the user must perform a READ/WRITE
operation (with the fourth of this “4-byte” word) to this particular
register location. When reading out (writing in) the next four bytes
of a given ATM Cell, the user must repeat this process with a
READ or WRITE operation, from/to this register location, and so
on.
4. Whenever the user is writing cell data into the Transmit Cell
Insertion Memory, the size of the Cell is always 56 bytes.
5. Whenever the user is reading cell data from the Transmit Cell
Extraction Memory, the size of the Cell is always 56 bytes.
291
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 221: Transmit ATM Cell Processor Block – Transmit ATM Idle Cell Header Byte 1 (Address =
0xNF18)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
Transmit Idle Cell Header Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit Idle Cell
Header Byte – 1 [7:0]
R/W
Transmit Idle Cell Header Byte – 1[7:0]:
These READ/WRITE register bits, along with that in “Transmit ATM
Cell Processor Block – Transmit ATM Idle Cell Header Byte 2 through
Byte 4” registers permit the user to define the header byte pattern of all
Idle Cells that are generated by the Transmit ATM Cell Processor
block.
This register permits the user to define/specify the value of Header
Byte # 1 within each Idle Cell that is generated and transmitted by the
Transmit ATM Cell Processor block.
Table 222: Transmit ATM Cell Processor Block – Transmit ATM Idle Cell Header Byte 2 (Address =
0xNF19)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
Transmit Idle Cell Header Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit Idle Cell
Header Byte – 2 [7:0]
R/W
Transmit Idle Cell Header Byte – 2[7:0]:
These READ/WRITE register bits, along with that in “Transmit ATM
Cell Processor Block – Transmit ATM Idle Cell Header Bytes 1, 3 and
4” registers permit the user to define the header byte pattern of all Idle
Cells that are generated by the Transmit ATM Cell Processor block.
This register permits the user to define/specify the value of Header
Byte # 2 within each Idle Cell that is generated and transmitted by the
Transmit ATM Cell Processor block.
292
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 223: Transmit ATM Cell Processor Block – Transmit ATM Idle Cell Header Byte 3 (Address =
0xNF1A)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
Transmit Idle Cell Header Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit Idle Cell
Header Byte – 3 [7:0]
R/W
Transmit Idle Cell Header Byte – 3[7:0]:
These READ/WRITE register bits, along with that in “Transmit ATM
Cell Processor Block – Transmit ATM Idle Cell Header Bytes 1, 2 and
4” registers permit the user to define the header byte pattern of all Idle
Cells that are generated by the Transmit ATM Cell Processor block.
This register permits the user to define/specify the value of Header
Byte # 3 within each Idle Cell that is generated and transmitted by the
Transmit ATM Cell Processor block.
Table 224: Transmit ATM Cell Processor Block – Transmit ATM Idle Cell Header Byte 4 (Address =
0xNF1B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Idle Cell Header Byte 4 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit Idle Cell
Header Byte – 4 [7:0]
R/W
Transmit Idle Cell Header Byte – 4[7:0]:
These READ/WRITE register bits, along with that in “Transmit ATM
Cell Processor Block – Transmit ATM Idle Cell Header Byte 1 through
Byte 3” registers permit the user to define the header byte pattern of all
Idle Cells that are generated by the Transmit ATM Cell Processor
block.
This register permits the user to define/specify the value of Header
Byte # 4 within each Idle Cell that is generated and transmitted by the
Transmit ATM Cell Processor block.
293
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 225: Transmit ATM Cell Processor Block – Transmit ATM Idle Cell Payload Register (Address =
0xNF1F)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Transmit Idle Cell
Payload Byte[7:0]
R/W
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
Transmit Idle Cell Payload Byte[7:0]
DESCRIPTION
Transmit Idle Cell Payload Byte [7:0]:
These READ/WRITE register bits permit the user to define the value of the
payload bytes of all Idle Cells that are generated and transmitted by the
Transmit ATM Cell Processor block.
Notes:
Each of the 48 payload bytes (within each outbound Idle Cell) will
be assigned the value that is written into this register.
Table 226: Transmit ATM Cell Processor Block – Transmit Test Cell Header Byte – Byte 1 (Address =
0xNF20)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Test Cell Header Byte 1 [7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Transmit Test Cell Header Byte
1[7:0]
R/W
DESCRIPTION
Receive Test Cell Header Byte 1:
These READ/WRITE register bits along with that in the
“Transmit ATM Cell Processor Block – Transmit Cell Header
Byte – Bytes 2 through 4” permit the user to define the
headers of test cells that the Transmit Test Cell Generator
will generate.
This particular register byte permits the user to define the
contents of Header Byte # 1.
Notes:
294
These register bits are only active if the Transmit
Test Cell Generator has been enabled.
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 227: Transmit ATM Cell Processor Block – Transmit Test Cell Header Byte – Byte 2 (Address =
0xNF21)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
Transmit Test Cell Header Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
7–0
Transmit Test Cell Header Byte
2[7:0]
R/W
DESCRIPTION
Receive Test Cell Header Byte 2:
These READ/WRITE register bits along with that in the
“Transmit ATM Cell Processor Block – Transmit Cell Header
Byte – Bytes 1, 3 and 4” permit the user to define the
headers of test cells that the Transmit Test Cell Generator
will generate.
This particular register byte permits the user to define the
contents of Header Byte # 2.
Notes:
These register bits are only active if the Transmit
Test Cell Generator has been enabled.
Table 228: Transmit ATM Cell Processor Block – Transmit Test Cell Header Byte – Byte 3 (Address =
0xNF22)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
Transmit Test Cell Header Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
7–0
Transmit Test Cell Header Byte
3[7:0]
R/W
DESCRIPTION
Receive Test Cell Header Byte 3:
These READ/WRITE register bits along with that in the
“Transmit ATM Cell Processor Block – Transmit Cell Header
Byte – Bytes 1, 2 and 4” permit the user to define the
headers of test cells that the Transmit Test Cell Generator
will generate.
This particular register byte permits the user to define the
contents of Header Byte # 3.
Notes:
295
These register bits are only active if the Transmit
Test Cell Generator has been enabled.
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 229: Transmit ATM Cell Processor Block – Transmit Test Cell Header Byte – Byte 4 (Address =
0xNF23)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
Transmit Test Cell Header Byte 4 [7:0]
BIT NUMBER
NAME
TYPE
7–0
Transmit Test Cell
Header Byte 4[7:0]
R/W
DESCRIPTION
Receive Test Cell Header Byte 4:
These READ/WRITE register bits along with that in the “Transmit ATM
Cell Processor Block – Transmit Cell Header Byte – Bytes 1 through 3”
permit the user to define the headers of test cells that the Transmit Test
Cell Generator will generate.
This particular register byte permits the user to define the contents of
Header Byte # 4.
Notes:
These register bits are only active if the Transmit Test Cell
Generator has been enabled.
Table 230: Transmit ATM Cell Processor Block – Transmit ATM Cell Counter (Address = 0xNF28)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit ATM Cell Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Transmit ATM Cell
Count[31:24]
RUR
DESCRIPTION
Transmit ATM Cell Count – Byte 3[31:24]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Count – Bytes 2 through 0” registers; contain a 32-bit value for the
number of User/Valid cells that have been transmitted by the Transmit
ATM Cell Processor block.
This particular register contains the MSB (Most Significant Byte) value
for this 32-bit expression.
Notes:
1. The contents within these registers include all of the following: All
ATM cells that have been read out from the TxFIFO, or the Transmit
Cell Insertion Buffer.
2. The contents of these registers do not include the number of Idle
Cells that have been generated by the Transmit ATM Cell Processor
block.
3. If the number of Cells reaches the value “0xFFFFFFFF” then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
296
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 231: Transmit ATM Cell Processor Block – Transmit ATM Cell Counter (Address = 0xNF29)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit ATM Cell Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Transmit ATM Cell
Count[23:16]
RUR
DESCRIPTION
Transmit ATM Cell Count – Byte 2[23:16]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Count – Bytes 3, 1 and 0” registers; contain a 32-bit value for the
number of User/Valid cells that have been transmitted by the Transmit
ATM Cell Processor block.
Notes:
1. The contents within these registers include all of the following: All
ATM cells that have been read out from the TxFIFO, or the Transmit
Cell Insertion Buffer.
2. The contents of these registers do not include the number of Idle
Cells that have been generated by the Transmit ATM Cell Processor
block.
3. If the number of Cells reaches the value “0xFFFFFFFF” then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
Table 232: Transmit ATM Cell Processor Block – Transmit ATM Cell Counter (Address = 0xNF2A)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Transmit ATM
Cell Count[15:8]
RUR
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
Transmit ATM Cell Count[15:8]
DESCRIPTION
Transmit ATM Cell Count – Byte 1[15:8]:
This RESET-upon-READ register, along with the “Transmit ATM Cell Count
– Bytes 3, 2 and 0” registers; contain a 32-bit value for the number of
User/Valid cells that have been transmitted by the Transmit ATM Cell
Processor block.
Notes:
1. The contents within these registers include all of the following: All ATM
cells that have been read out from the TxFIFO, or the Transmit Cell
Insertion Buffer.
2. The contents of these registers do not include the number of Idle Cells
that have been generated by the Transmit ATM Cell Processor block.
3. If the number of Cells reaches the value “0xFFFFFFFF” then these
registers will saturate to and remain at this value (e.g., it will NOT overflow
to “0x00000000”).
297
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 233: Transmit ATM Cell Processor Block – Transmit ATM Cell Counter (Address = 0xNF2B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit ATM Cell Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Transmit ATM
Cell Count[7:0]
RUR
DESCRIPTION
Transmit ATM Cell Count – Byte 0[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell Count
– Bytes 3 through 1” registers; contain a 32-bit value for the number of
User/Valid cells that have been transmitted by the Transmit ATM Cell
Processor block.
This particular register contains the LSB (Least Significant Byte) value for
this 32-bit expression.
Notes:
1. The contents within these registers include all of the following: All ATM
cells that have been read out from the TxFIFO, or the Transmit Cell Insertion
Buffer.
2. The contents of these registers do not include the number of Idle Cells
that have been generated by the Transmit ATM Cell Processor block.
3. If the number of Cells reaches the value “0xFFFFFFFF” then these
registers will saturate to and remain at this value (e.g., it will NOT overflow
to “0x00000000”).
298
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 234: Transmit ATM Cell Processor Block – Transmit ATM Cell Discard Cell Count – Byte 3
(Address = 0xNF2C)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
Transmit – Discard Cell Count[31:24]
BIT NUMBER
NAME
TYPE
7-0
Transmit – Discard
Cell Count[31:24]
RUR
DESCRIPTION
Transmit – Discard Cell Count – Byte 3[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit ATM Cell Discard Cell Count – Bytes 2
through 0” registers; contain a 32-bit value for the number of ATM cells
that have been discarded by the Transmit ATM Cell Processor block.
This particular register contains the MSB (Most Significant Byte) value
of this 32-bit expression.
Notes:
1. The contents within these register includes all ATM cells that contain
either a HEC Byte error or a “Transmit UTOPIA Parity” error.
2. If the number of Cells reaches the value “0xFFFFFFFFF” then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
Table 235: Transmit ATM Cell Processor Block – Transmit ATM Cell Discard Cell Count – Byte 2
(Address = 0xNF2D)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
Transmit – Discard Cell Count[23:16]
BIT NUMBER
NAME
TYPE
7-0
Transmit – Discard
Cell Count[23:16]
RUR
DESCRIPTION
Transmit – Discard Cell Count – Byte 2[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit ATM Cell Discard Cell Count – Bytes 3, 1
and 0” registers; contain a 32-bit value for the number of ATM cells that
have been discarded by the Transmit ATM Cell Processor block.
Notes:
1. The contents within these register includes all ATM cells that contain
either a HEC Byte error or a “Transmit UTOPIA Parity” error.
2. If the number of Cells reaches the value “0xFFFFFFFFF” then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
299
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 236: Transmit ATM Cell Processor Block – Transmit ATM Cell Discard Cell Count – Byte 1
(Address = 0xNF2E)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
Transmit – Discard Cell Count[15:8]
BIT NUMBER
NAME
TYPE
7-0
Transmit – Discard
Cell Count[15:8]
RUR
DESCRIPTION
Transmit – Discard Cell Count – Byte 1[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit ATM Cell Discard Cell Count – Bytes 3, 2
and 0” registers; contain a 32-bit value for the number of ATM cells that
have been discarded by the Transmit ATM Cell Processor block.
Notes:
1. The contents within these register includes all ATM cells that contain
either a HEC Byte error or a “Transmit UTOPIA Parity” error.
2. If the number of Cells reaches the value “0xFFFFFFFFF” then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
Table 237: Transmit ATM Cell Processor Block – Transmit ATM Cell Discard Cell Count – Byte 0
(Address = 0xNF2F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit – Discard Cell Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Transmit – Discard
Cell Count[7:0]
RUR
DESCRIPTION
Transmit – Discard Cell Count – Byte 0[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit ATM Cell Discard Cell Count – Bytes 3
through 1” registers; contain a 32-bit value for the number of ATM cells
that have been discarded by the Transmit ATM Cell Processor block.
This particular register contains the LSB (Least Significant Byte) value
of this 32-bit expression.
Notes:
1. The contents within these register includes all ATM cells that contain
either a HEC Byte error or a “Transmit UTOPIA Parity” error.
2. If the number of Cells reaches the value “0xFFFFFFFFF” then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
300
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N
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L
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S
T
S
T
O
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T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 238: Transmit ATM Cell Processor Block – Transmit ATM HEC Byte Error Count Register – Byte
3 (Address = 0xNF30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit – HEC Byte Error Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Transmit – HEC Byte
Error Count[31:24]
RUR
DESCRIPTION
Transmit – HEC Byte Error Count – Byte 3[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit ATM HEC Byte Error Count Register –
Bytes 2 through 0” register; contain a 32-bit value for the number of
ATM cells that contain HEC byte errors (as detected by the Transmit
ATM Cell Processor block).
This particular register functions as the MSB (Most Significant Byte) for
this 32-bit expression.
Notes:
1. This register is valid if the Transmit ATM Cell Processor block has
been configured to compute and verify the HEC byte of each ATM cell
that it receives from the TxFIFO or the “Transmit Cell Insertion Buffer”.
2. If the number of cells reaches the value “0xFFFFFFFF”, then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
Table 239: Transmit ATM Cell Processor Block – Transmit ATM HEC Byte Error Count Register – Byte
2 (Address = 0xNF31)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
Transmit – HEC Byte Error Count[23:16]
BIT NUMBER
NAME
TYPE
7–0
Transmit – HEC Byte
Error Count[23:16]
RUR
DESCRIPTION
Transmit – HEC Byte Error Count – Byte 2[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit ATM HEC Byte Error Count Register –
Bytes 3, 1 and 0” register; contain a 32-bit value for the number of ATM
cells that contain HEC byte errors (as detected by the Transmit ATM
Cell Processor block).
Notes:
1.This register is valid if the Transmit ATM Cell Processor block has
been configured to compute and verify the HEC byte of each ATM cell
that it receives from the TxFIFO or the “Transmit Cell Insertion Buffer”.
2. If the number of cells reaches the value “0xFFFFFFFF”, then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
301
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H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 240: Transmit ATM Cell Processor Block – Transmit ATM HEC Byte Error Count Register – Byte
1 (Address = 0xNF32)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
Transmit – HEC Byte Error Count[15:8]
BIT NUMBER
NAME
TYPE
7–0
Transmit – HEC Byte
Error Count[15:8]
RUR
DESCRIPTION
Transmit – HEC Byte Error Count – Byte 1[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit ATM HEC Byte Error Count Register –
Bytes 3, 2 and 0” register; contain a 32-bit value for the number of ATM
cells that contain HEC byte errors (as detected by the Transmit ATM
Cell Processor block).
Notes:
1. This register is valid if the Transmit ATM Cell Processor block has
been configured to compute and verify the HEC byte of each ATM cell
that it receives from the TxFIFO or the “Transmit Cell Insertion Buffer”.
2. If the number of cells reaches the value “0xFFFFFFFF”, then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
Table 241: Transmit ATM Cell Processor Block – Transmit ATM HEC Byte Error Count Register – Byte
0 (Address = 0xNF33)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
Transmit – HEC Byte Error Count[7:0]
BIT NUMBER
NAME
TYPE
7–0
Transmit – HEC Byte
Error Count[7:0]
RUR
DESCRIPTION
Transmit – HEC Byte Error Count – Byte 0[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit ATM HEC Byte Error Count Register –
Bytes 3 through 1” register; contain a 32-bit value for the number of
ATM cells that contain HEC byte errors (as detected by the Transmit
ATM Cell Processor block).
This particular register functions as the LSB (Least Significant Byte) for
this 32-bit expression.
Notes:
1. This register is valid if the Transmit ATM Cell Processor block has
been configured to compute and verify the HEC byte of each ATM cell
that it receives from the TxFIFO or the “Transmit Cell Insertion Buffer”.
2. If the number of cells reaches the value “0xFFFFFFFF”, then these
registers will saturate to and remain at this value (e.g., it will NOT
overflow to “0x00000000”).
302
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A
N
N
E
L
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S
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S
T
S
T
O
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T
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S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 242: Transmit ATM Cell Processor Block – Transmit UTOPIA Parity Error Count Register – Byte
3 (Address = 0xNF34)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit UTOPIA – Parity Error Count[31:24]
BIT NUMBER
NAME
TYPE
7-0
Transmit UTOPIA –
Parity Error
Count[31:24]
RUR
DESCRIPTION
Transmit UTOPIA Parity Error Count – Byte 3[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit UTOPIA Parity Error Count Register –
Bytes 2 through 0” registers; contains a 32-bit value for the number of
ATM cells that contain “Transmit UTOPIA” Parity (byte or word) errors
(as detected by the Transmit ATM Cell Processor block).
This particular register functions as the MSB (Most Significant Byte) for
this 32-bit expression.
Notes:
if the number of cells reaches the value “0xFFFFFFFF”, then
these registers will saturate to and remain at this value (e.g.,
it will NOT overflow to “0x00000000”).
Table 243: Transmit ATM Cell Processor Block – Transmit UTOPIA Parity Error Count Register – Byte
2 (Address = 0xNF35)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit UTOPIA – Parity Error Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
Transmit UTOPIA –
Parity Error
Count[23:16]
RUR
DESCRIPTION
Transmit UTOPIA Parity Error Count – Byte 2[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit UTOPIA Parity Error Count Register –
Bytes 3, 1 and 0” registers; contains a 32-bit value for the number of
ATM cells that contain “Transmit UTOPIA” Parity (byte or word) errors
(as detected by the Transmit ATM Cell Processor block).
Notes:
if the number of cells reaches the value “0xFFFFFFFF”, then
these registers will saturate to and remain at this value (e.g.,
it will NOT overflow to “0x00000000”).
303
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M
A
P
P
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R
A
T
M
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G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 244: Transmit ATM Cell Processor Block – Transmit UTOPIA Parity Error Count Register – Byte
1 (Address = 0xNF36)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit UTOPIA – Parity Error Count[15:8]
BIT NUMBER
NAME
TYPE
7-0
Transmit UTOPIA –
Parity Error
Count[15:8]
RUR
DESCRIPTION
Transmit UTOPIA Parity Error Count – Byte 1[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit UTOPIA Parity Error Count Register –
Bytes 3, 2 and 0” registers; contains a 32-bit value for the number of
ATM cells that contain “Transmit UTOPIA” Parity (byte or word) errors
(as detected by the Transmit ATM Cell Processor block).
Notes:
if the number of cells reaches the value “0xFFFFFFFF”, then
these registers will saturate to and remain at this value (e.g.,
it will NOT overflow to “0x00000000”).
Table 245: Transmit ATM Cell Processor Block – Transmit UTOPIA Parity Error Count Register – Byte
0 (Address = 0xNF37)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit UTOPIA – Parity Error Count[7:0]
BIT NUMBER
NAME
TYPE
7-0
Transmit UTOPIA –
Parity Error
Count[7:0]
RUR
DESCRIPTION
Transmit UTOPIA Parity Error Count – Byte 0[7:0]:
This RESET-upon-READ register, along with the “Transmit ATM Cell
Processor Block – Transmit UTOPIA Parity Error Count Register –
Bytes 3 through 1” registers; contains a 32-bit value for the number of
ATM cells that contain “Transmit UTOPIA” Parity (byte or word) errors
(as detected by the Transmit ATM Cell Processor block).
This particular register functions as the LSB (Least Significant Byte) for
this 32-bit expression.
Notes:
if the number of cells reaches the value “0xFFFFFFFF”, then
these registers will saturate to and remain at this value (e.g.,
it will NOT overflow to “0x00000000”).
304
XRT94L33
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N
E
L
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S
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T
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T
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M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
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RS
S
Rev222...000...000
Table 246: Transmit ATM Cell Processor Block – Transmit User Cell Filter Control – Filter 0 (Address =
0xNF43)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
BIT 1
BIT 0
Transmit User
Cell Filter # 0
Enable
Copy Cell
Enable
Discard Cell
Enable
Filter if
Pattern Match
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-4
Unused
R/O
3
Transmit User Cell Filter # 0
Enable
R/W
DESCRIPTION
Transmit User Cell Filter # 0 – Enable:
This READ/WRITE bit-field permits the user to either enable
or disable Transmit User Cell Filter # 0.
If the user enables Transmit User Cell Filter # 0, then
Transmit User Cell Filter # 0 will function per the configuration
settings in Bits 2 through 0, within this register.
If the user disables Transmit User Cell Filter # 0, then
Transmit User Cell Filter # 0 then all cells that are applied to
the input of Transmit User Cell Filter # 0 will pass through to
the output of Transmit User Cell Filter # 0.
0 – Disables Transmit User Cell Filter # 0.
1 – Enables Transmit User Cell Filter # 0.
2
Copy Cell Enable
R/W
Copy Cell Enable – Transmit User Cell Filter # 0:
This READ/WRITE bit-field permits the user to either
configure Transmit User Cell Filter # 0 (within the Transmit
ATM Cell Processor Block) to copy all cells that have header
byte patterns that comply with the “user-defined” criteria, per
Transmit User Cell Filter # 0, or to NOT copy any of these
cells.
If the user configures Transmit User Cell Filter # 0 to copy all
cells complying with a certain “header-byte” pattern, then a
copy (or replicate) of this “compliant” ATM cell will be routed
to the Transmit Cell Extraction Buffer.
If the user configures Transmit User Cell Filter # 0 to NOT
copy all cells complying with a certain “header-byte” pattern,
then NO copies (or replicates) of these “compliant” ATM cells
will be made nor will any be routed to the Transmit Cell
Extraction Buffer.
0 – Configures Transmit User Cell Filter # 0 to NOT copy any
cells that have header byte patterns which are compliant with
the “user-defined” filtering criteria.
1 – Configures Transmit User Cell Filter # 0 to copy any cells
that have header byte patterns that are compliant with the
“user-defined” filtering criteria, and to route these copies (of
cells) to the Transmit Cell Extraction Buffer.
Notes:
1
Discard Cell Enable
R/W
This bit-field is only active if “Transmit User Cell
Filter # 0” has been enabled.
Discard Cell Enable – Transmit User Cell Filter # 0:
This READ/WRITE bit-field permits the user to either
305
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A
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A
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C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
configure Transmit User Cell Filter # 0 (within the Transmit
ATM Cell Processor Block) to discard all cells that have
header byte patterns that comply with the “user-defined”
criteria, per Transmit User Cell Filter # 0, or NOT discard any
of these cells.
If the user configures Transmit User Cell Filter # 0 to NOT
discarded any cells that is compliant with a certain “headerbyte” pattern, then the cell will be retained for further
processing.
0 – Configures Transmit User Cell Filter # 0 to NOT discard
any cells that have header byte patterns that are compliant
with the “user-defined” filtering criteria.
1 – Configures Transmit User Cell Filter # 0 to discard any
cells that have header byte patterns that are compliant with
the “user-defined” filtering criteria.
Notes:
0
Filter if Pattern Match
R/W
This bit-field is only active if “Transmit User Cell
Filter # 0” has been enabled.
Filter if Pattern Match – Transmit User Cell Filter # 0:
This READ/WRITE bit-field permits the user to either
configure Transmit User Cell Filter # 0 to filter (based upon
the configuration settings for Bits 1 and 2, in this register)
ATM cells with header bytes that match the “user-defined”
header byte patterns, or to filter ATM cells with header bytes
that do NOT match the “user-defined” header byte patterns.
0 – Configures Transmit User Cell Filter # 0 to filter user cells
that do NOT match the header byte patterns (as defined in
the “ “ registers).
1 – Configures Transmit User Cell Filter # 0 to filter user cells
that do match the header byte patterns (as defined in the “ “
registers).
Notes:
306
This bit-field is only active if “Transmit User Cell
Filter # 0” has been enabled.
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 247: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Pattern Register –
Header Byte 1 (Address = 0xNF44)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 0 – Pattern Register – Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 0 –
Pattern Register – Header Byte
1
R/W
Transmit User Cell Filter # 0 – Pattern Register – Header
Byte 1:
The User Cell filtering criteria (for Transmit User Cell Filter #
0) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 0 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 0 – Check
Register – Header Byte 1” permits the user to define the User
Cell Filtering criteria for “Octet # 1” of the incoming User Cell.
The user will write the header byte pattern (for Octet 1) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 0 – Check Register – Header Byte 1” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
307
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A
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 248: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Pattern Register –
Header Byte 2 (Address = 0xNF45)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 0 – Pattern Register – Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 0 –
Pattern Register – Header Byte
2
R/W
Transmit User Cell Filter # 0 – Pattern Register – Header
Byte 2:
The User Cell filtering criteria (for Transmit User Cell Filter #
0) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 0 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 0 – Check
Register – Header Byte 2” permits the user to define the User
Cell Filtering criteria for “Octet # 2” of the incoming User Cell.
The user will write the header byte pattern (for Octet 2) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 0 – Check Register – Header Byte 2” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
308
XRT94L33
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C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 249: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Pattern Register –
Header Byte 3 (Address = 0xNF46)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 0 – Pattern Register – Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 0 –
Pattern Register – Header Byte
3
R/W
Transmit User Cell Filter # 0 – Pattern Register – Header
Byte 3:
The User Cell filtering criteria (for Transmit User Cell Filter #
0) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 0 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 0 – Check
Register – Header Byte 3” permits the user to define the User
Cell Filtering criteria for “Octet # 3” of the incoming User Cell.
The user will write the header byte pattern (for Octet 3) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 0 – Check Register – Header Byte 3” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
309
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333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 250: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Pattern Register –
Header Byte 4 (Address = 0xNF47)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 0 – Pattern Register – Byte 4 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 0 –
Pattern Register – Header Byte
4
R/W
Transmit User Cell Filter # 0 – Pattern Register – Header
Byte 4:
The User Cell filtering criteria (for Transmit User Cell Filter #
0) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 0 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 0 – Check
Register – Header Byte 4” permits the user to define the User
Cell Filtering criteria for “Octet # 4” of the incoming User Cell.
The user will write the header byte pattern (for Octet 4) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 0 – Check Register – Header Byte 4” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
310
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 251: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Check Register – Byte
1 (Address = 0xNF48)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 0 – Check Register – Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 0 –
Check Register – Header Byte
1
R/W
Transmit User Cell Filter # 0 – Check Register – Header
Byte 1:
The User Cell filtering criteria (for Transmit User Cell Filter #
0) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 0 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 0 – Pattern
Register – Header Byte 1” permits the user to define the User
Cell Filtering criteria for “Octet # 1” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 1” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 – Pattern Register – Header Byte 1” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 1” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Register – Header Byte 1”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 1” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 1” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 0 – Pattern Register – Header Byte 1”).
311
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 252: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Check Register – Byte
2 (Address = 0xNF49)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 0 – Check Register – Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 0 –
Check Register – Header Byte
2
R/W
Transmit User Cell Filter # 0 – Check Register – Header
Byte 2:
The User Cell filtering criteria (for Transmit User Cell Filter #
0) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 0 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 0 – Pattern
Register – Header Byte 2” permits the user to define the User
Cell Filtering criteria for “Octet # 2” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 2” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 – Pattern Register – Header Byte 2” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 2” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Register – Header Byte 2”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 2” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 2” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 0 – Pattern Register – Header Byte 2”).
312
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 253: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Check Register – Byte
3 (Address = 0xNF4A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 0 – Check Register – Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 0 –
Check Register – Header Byte
3
R/W
Transmit User Cell Filter # 0 – Check Register – Header
Byte 3:
The User Cell filtering criteria (for Transmit User Cell Filter #
0) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 0 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 0 – Pattern
Register – Header Byte 3” permits the user to define the User
Cell Filtering criteria for “Octet # 3” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 3” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 – Pattern Register – Header Byte 3” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 3” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Register – Header Byte 3”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 3” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 3” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 0 – Pattern Register – Header Byte 3”).
313
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 254: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Check Register – Byte
4 (Address = 0xNF4B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 0 – Check Register – Byte 4 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 0 –
Check Register – Header Byte
4
R/W
Transmit User Cell Filter # 0 – Check Register – Header
Byte 4:
The User Cell filtering criteria (for Transmit User Cell Filter #
0) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 0 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 0 – Pattern
Register – Header Byte 4” permits the user to define the User
Cell Filtering criteria for “Octet # 4” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 4” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 0 – Pattern Register – Header Byte 4” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 4” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 0 – Pattern
Register – Header Byte 4”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 4” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 4” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 0 – Pattern Register – Header Byte 4”).
314
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 255: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Filtered Cell Count –
Byte 3 (Address = 0xNF4C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 0 – Filtered Cell Count[31:24]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 0 – Filtered
Cell Count[31:24]
RUR
DESCRIPTION
Transmit User Cell Filter # 0 – Filtered Cell Count[31:24]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 0 – Filtered Cell
Count – Bytes 2” through “0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 0 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – User Cell Filter #
0” Register (Address = 0xNF43), these register bits will be incremented
anytime User Cell Filter # 0 performs any of the following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
This particular register contains the MSB (Most Significant Byte) value
for this 32-bit expression.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
315
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 256: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Filtered Cell Count –
Byte 2 (Address = 0xNF4D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 0 – Filtered Cell Count[23:16]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 0 – Filtered
Cell Count[23:16]
RUR
DESCRIPTION
Transmit User Cell Filter # 0 – Filtered Cell Count[23:16]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 0 – Filtered Cell
Count – Bytes 3, 1 and 0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 0 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 0” Register (Address = 0xNF43), these register bits will be
incremented anytime User Cell Filter # 0 performs any of the following
functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
316
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 257: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Filtered Cell Count –
Byte 1 (Address = 0xNF4E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 0 – Filtered Cell Count[15:8]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 0 – Filtered
Cell Count[15:8]
RUR
DESCRIPTION
Transmit User Cell Filter # 0 – Filtered Cell Count[15:8]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 0 – Filtered Cell
Count – Bytes 3, 2 and 0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 0 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 0” Register (Address = 0xNF43), these register bits will be
incremented anytime Transmit User Cell Filter # 0 performs any of the
following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
317
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 258: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 0 – Filtered Cell Count –
Byte 0 (Address = 0xNF4F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 0 – Filtered Cell Count[7:0]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 0 – Filtered
Cell Count[7:0]
RUR
DESCRIPTION
Transmit User Cell Filter # 0 – Filtered Cell Count[7:0]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 0 – Filtered Cell
Count – Bytes 3” through “1” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 0 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 0” Register (Address = 0xNF43), these register bits will be
incremented anytime Transmit User Cell Filter # 0 performs any of the
following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
This particular register contains the LSB (Least Significant Byte) value
for this 32-bit expression.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
318
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
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RS
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Rev222...000...000
Table 259: Transmit ATM Cell Processor Block – Transmit User Cell Filter Control – Filter 1 (Address =
0xNF53)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
BIT 1
BIT 0
Transmit User
Cell Filter # 1
Enable
Copy Cell
Enable
Discard Cell
Enable
Filter if
Pattern Match
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-4
Unused
R/O
3
Transmit User Cell Filter # 1
Enable
R/W
DESCRIPTION
Transmit User Cell Filter # 1 – Enable:
This READ/WRITE bit-field permits the user to either enable
or disable Transmit User Cell Filter # 1.
If the user enables Transmit User Cell Filter # 1, then
Transmit User Cell Filter # 1 will function per the configuration
settings in Bits 2 through 0, within this register.
If the user disables Transmit User Cell Filter # 1, then
Transmit User Cell Filter # 1 then all cells that are applied to
the input of Transmit User Cell Filter # 1 will pass through to
the output of Transmit User Cell Filter # 1.
0 – Disables Transmit User Cell Filter # 1.
1 – Enables Transmit User Cell Filter # 1.
2
Copy Cell Enable
R/W
Copy Cell Enable – Transmit User Cell Filter # 1:
This READ/WRITE bit-field permits the user to either
configure Transmit User Cell Filter # 1 (within the Transmit
ATM Cell Processor Block) to copy all cells that have header
byte patterns that comply with the “user-defined” criteria, per
Transmit User Cell Filter # 1, or to NOT copy any of these
cells.
If the user configures Transmit User Cell Filter # 1 to copy all
cells complying with a certain “header-byte” pattern, then a
copy (or replicate) of this “compliant” ATM cell will be routed
to the Transmit Cell Extraction Buffer.
If the user configures Transmit User Cell Filter # 1 to NOT
copy all cells complying with a certain “header-byte” pattern,
then NO copies (or replicates) of these “compliant” ATM cells
will be made nor will any be routed to the Transmit Cell
Extraction Buffer.
0 – Configures Transmit User Cell Filter # 1 to NOT copy any
cells that have header byte patterns which are compliant with
the “user-defined” filtering criteria.
1 – Configures Transmit User Cell Filter # 1 to copy any cells
that have header byte patterns that are compliant with the
“user-defined” filtering criteria, and to route these copies (of
cells) to the Transmit Cell Extraction Buffer.
Notes:
1
Discard Cell Enable
R/W
This bit-field is only active if “Transmit User Cell
Filter # 1” has been enabled.
Discard Cell Enable – Transmit User Cell Filter # 1:
This READ/WRITE bit-field permits the user to either
319
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A
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E
L
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T
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T
O
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M---111 M
MA
AP
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AT
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ST
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S---111 T
TO
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S---333///S
ST
Rev222...000...000
configure Transmit User Cell Filter # 1 (within the Transmit
ATM Cell Processor Block) to discard all cells that have
header byte patterns that comply with the “user-defined”
criteria, per Transmit User Cell Filter # 1, or NOT discard any
of these cells.
If the user configures Transmit User Cell Filter # 1 to NOT
discarded any cells that is compliant with a certain “headerbyte” pattern, then the cell will be retained for further
processing.
0 – Configures Transmit User Cell Filter # 1 to NOT discard
any cells that have header byte patterns that are compliant
with the “user-defined” filtering criteria.
1 – Configures Transmit User Cell Filter # 1 to discard any
cells that have header byte patterns that are compliant with
the “user-defined” filtering criteria.
Notes:
0
Filter if Pattern Match
R/W
This bit-field is only active if “Transmit User Cell
Filter # 1” has been enabled.
Filter if Pattern Match – Transmit User Cell Filter # 1:
This READ/WRITE bit-field permits the user to either
configure Transmit User Cell Filter # 1 to filter (based upon
the configuration settings for Bits 1 and 2, in this register)
ATM cells with header bytes that match the “user-defined”
header byte patterns, or to filter ATM cells with header bytes
that do NOT match the “user-defined” header byte patterns.
0 – Configures Transmit User Cell Filter # 1 to filter user cells
that do NOT match the header byte patterns (as defined in
the “ “ registers).
1 – Configures Transmit User Cell Filter # 1 to filter user cells
that do match the header byte patterns (as defined in the “ “
registers).
Notes:
320
This bit-field is only active if “Transmit User Cell
Filter # 1” has been enabled.
XRT94L33
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A
N
N
E
L
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S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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ER
RS
S
Rev222...000...000
Table 260: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Pattern Register –
Header Byte 1 (Address = 0xNF54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 1 – Pattern Register – Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 1 –
Pattern Register – Header Byte
1
R/W
Transmit User Cell Filter # 1 – Pattern Register – Header
Byte 1:
The User Cell filtering criteria (for Transmit User Cell Filter #
1) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 1 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 1 – Check
Register – Header Byte 1” permits the user to define the User
Cell Filtering criteria for “Octet # 1” of the incoming User Cell.
The user will write the header byte pattern (for Octet 1) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 1 – Check Register – Header Byte 1” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
321
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M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 261: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Pattern Register –
Header Byte 2 (Address = 0xNF55)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 1 – Pattern Register – Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 1 –
Pattern Register – Header Byte
2
R/W
Transmit User Cell Filter # 1 – Pattern Register – Header
Byte 2:
The User Cell filtering criteria (for Transmit User Cell Filter #
1) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 1 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 1 – Check
Register – Header Byte 2” permits the user to define the User
Cell Filtering criteria for “Octet # 2” of the incoming User Cell.
The user will write the header byte pattern (for Octet 2) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 1 – Check Register – Header Byte 2” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
322
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C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 262: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Pattern Register –
Header Byte 3 (Address = 0xNF56)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 1 – Pattern Register – Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 1 –
Pattern Register – Header Byte
3
R/W
Transmit User Cell Filter # 1 – Pattern Register – Header
Byte 3:
The User Cell filtering criteria (for Transmit User Cell Filter #
1) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 1 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 1 – Check
Register – Header Byte 3” permits the user to define the User
Cell Filtering criteria for “Octet # 3” of the incoming User Cell.
The user will write the header byte pattern (for Octet 3) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 1 – Check Register – Header Byte 3” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
323
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M
A
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P
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A
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 263: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Pattern Register –
Header Byte 4 (Address = 0xNF57)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 1 – Pattern Register – Byte 4 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 1 –
Pattern Register – Header Byte
4
R/W
Transmit User Cell Filter # 1 – Pattern Register – Header
Byte 4:
The User Cell filtering criteria (for Transmit User Cell Filter #
1) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 1 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 1 – Check
Register – Header Byte 4” permits the user to define the User
Cell Filtering criteria for “Octet # 4” of the incoming User Cell.
The user will write the header byte pattern (for Octet 4) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 1 – Check Register – Header Byte 4” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
324
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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S
Rev222...000...000
Table 264: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Check Register – Byte
1 (Address = 0xNF58)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 1 – Check Register – Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 1 –
Check Register – Header Byte
1
R/W
Transmit User Cell Filter # 1 – Check Register – Header
Byte 1:
The User Cell filtering criteria (for Transmit User Cell Filter #
1) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 1 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 1 – Pattern
Register – Header Byte 1” permits the user to define the User
Cell Filtering criteria for “Octet # 1” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 1” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 – Pattern Register – Header Byte 1” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 1” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Register – Header Byte 1”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 1” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 1” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 1 – Pattern Register – Header Byte 1”).
325
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M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 265: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Check Register – Byte
2 (Address = 0xNF59)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 1 – Check Register – Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 1 –
Check Register – Header Byte
2
R/W
Transmit User Cell Filter # 1 – Check Register – Header
Byte 2:
The User Cell filtering criteria (for Transmit User Cell Filter #
1) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 1 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 1 – Pattern
Register – Header Byte 2” permits the user to define the User
Cell Filtering criteria for “Octet # 2” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 2” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 – Pattern Register – Header Byte 2” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 2” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Register – Header Byte 2”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 2” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 2” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 1 – Pattern Register – Header Byte 2”).
326
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 266: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Check Register – Byte
3 (Address = 0xNF5A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 1 – Check Register – Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 1 –
Check Register – Header Byte
3
R/W
Transmit User Cell Filter # 1 – Check Register – Header
Byte 3:
The User Cell filtering criteria (for Transmit User Cell Filter #
1) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 1 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 1 – Pattern
Register – Header Byte 3” permits the user to define the User
Cell Filtering criteria for “Octet # 3” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 3” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 – Pattern Register – Header Byte 3” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 3” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Register – Header Byte 3”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 3” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 3” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 1 – Pattern Register – Header Byte 3”).
327
XRT94L33
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S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 267: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Check Register – Byte
4 (Address = 0xNF5B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 1 – Check Register – Byte 4 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 1 –
Check Register – Header Byte
4
R/W
Transmit User Cell Filter # 1 – Check Register – Header
Byte 4:
The User Cell filtering criteria (for Transmit User Cell Filter #
1) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 1 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 1 – Pattern
Register – Header Byte 4” permits the user to define the User
Cell Filtering criteria for “Octet # 4” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 4” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 1 – Pattern Register – Header Byte 4” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 4” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 1 – Pattern
Register – Header Byte 4”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 4” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 4” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 1 – Pattern Register – Header Byte 4”).
328
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 268: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Filtered Cell Count –
Byte 3 (Address = 0xNF5C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 1 – Filtered Cell Count[31:24]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 1 – Filtered
Cell Count[31:24]
RUR
DESCRIPTION
Transmit User Cell Filter # 1 – Filtered Cell Count[31:24]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 1 – Filtered Cell
Count – Bytes 2” through “0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 1 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – User Cell Filter #
1” Register (Address = 0xNF53), these register bits will be incremented
anytime User Cell Filter # 1 performs any of the following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
This particular register contains the MSB (Most Significant Byte) value
for this 32-bit expression.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
329
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 269: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Filtered Cell Count –
Byte 2 (Address = 0xNF5D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 1 – Filtered Cell Count[23:16]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 1 – Filtered
Cell Count[23:16]
RUR
DESCRIPTION
Transmit User Cell Filter # 1 – Filtered Cell Count[23:16]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 1 – Filtered Cell
Count – Bytes 3, 1 and 0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 1 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 1” Register (Address = 0xNF53), these register bits will be
incremented anytime User Cell Filter # 1 performs any of the following
functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
330
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 270: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Filtered Cell Count –
Byte 1 (Address = 0xNF5E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 1 – Filtered Cell Count[15:8]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 1 – Filtered
Cell Count[15:8]
RUR
DESCRIPTION
Transmit User Cell Filter # 1 – Filtered Cell Count[15:8]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 1 – Filtered Cell
Count – Bytes 3, 2 and 0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 1 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 1” Register (Address = 0xNF53), these register bits will be
incremented anytime Transmit User Cell Filter # 1 performs any of the
following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
331
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 271: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 1 – Filtered Cell Count –
Byte 0 (Address = 0xNF5F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 1 – Filtered Cell Count[7:0]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 1 – Filtered
Cell Count[7:0]
RUR
DESCRIPTION
Transmit User Cell Filter # 1 – Filtered Cell Count[7:0]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 1 – Filtered Cell
Count – Bytes 3” through “1” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 1 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 1” Register (Address = 0xNF53), these register bits will be
incremented anytime Transmit User Cell Filter # 1 performs any of the
following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
This particular register contains the LSB (Least Significant Byte) value
for this 32-bit expression.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
332
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 272: Transmit ATM Cell Processor Block – Transmit User Cell Filter Control – Filter 2 (Address =
0xNF63)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
BIT 1
BIT 0
Transmit User
Cell Filter # 2
Enable
Copy Cell
Enable
Discard Cell
Enable
Filter if
Pattern Match
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-4
Unused
R/O
3
Transmit User Cell Filter # 2
Enable
R/W
DESCRIPTION
Transmit User Cell Filter # 2 – Enable:
This READ/WRITE bit-field permits the user to either enable
or disable Transmit User Cell Filter # 2.
If the user enables Transmit User Cell Filter # 2, then
Transmit User Cell Filter # 2 will function per the configuration
settings in Bits 2 through 0, within this register.
If the user disables Transmit User Cell Filter # 2, then
Transmit User Cell Filter # 2 then all cells that are applied to
the input of Transmit User Cell Filter # 2 will pass through to
the output of Transmit User Cell Filter # 2.
0 – Disables Transmit User Cell Filter # 2.
1 – Enables Transmit User Cell Filter # 2.
2
Copy Cell Enable
R/W
Copy Cell Enable – Transmit User Cell Filter # 2:
This READ/WRITE bit-field permits the user to either
configure Transmit User Cell Filter # 2 (within the Transmit
ATM Cell Processor Block) to copy all cells that have header
byte patterns that comply with the “user-defined” criteria, per
Transmit User Cell Filter # 2, or to NOT copy any of these
cells.
If the user configures Transmit User Cell Filter # 2 to copy all
cells complying with a certain “header-byte” pattern, then a
copy (or replicate) of this “compliant” ATM cell will be routed
to the Transmit Cell Extraction Buffer.
If the user configures Transmit User Cell Filter # 2 to NOT
copy all cells complying with a certain “header-byte” pattern,
then NO copies (or replicates) of these “compliant” ATM cells
will be made nor will any be routed to the Transmit Cell
Extraction Buffer.
0 – Configures Transmit User Cell Filter # 2 to NOT copy any
cells that have header byte patterns which are compliant with
the “user-defined” filtering criteria.
1 – Configures Transmit User Cell Filter # 2 to copy any cells
that have header byte patterns that are compliant with the
“user-defined” filtering criteria, and to route these copies (of
cells) to the Transmit Cell Extraction Buffer.
Notes:
1
Discard Cell Enable
R/W
This bit-field is only active if “Transmit User Cell
Filter # 2” has been enabled.
Discard Cell Enable – Transmit User Cell Filter # 2:
This READ/WRITE bit-field permits the user to either
333
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
configure Transmit User Cell Filter # 2 (within the Transmit
ATM Cell Processor Block) to discard all cells that have
header byte patterns that comply with the “user-defined”
criteria, per Transmit User Cell Filter # 2, or NOT discard any
of these cells.
If the user configures Transmit User Cell Filter # 2 to NOT
discarded any cells that is compliant with a certain “headerbyte” pattern, then the cell will be retained for further
processing.
0 – Configures Transmit User Cell Filter # 2 to NOT discard
any cells that have header byte patterns that are compliant
with the “user-defined” filtering criteria.
1 – Configures Transmit User Cell Filter # 2 to discard any
cells that have header byte patterns that are compliant with
the “user-defined” filtering criteria.
Notes:
0
Filter if Pattern Match
R/W
This bit-field is only active if “Transmit User Cell
Filter # 2” has been enabled.
Filter if Pattern Match – Transmit User Cell Filter # 2:
This READ/WRITE bit-field permits the user to either
configure Transmit User Cell Filter # 2 to filter (based upon
the configuration settings for Bits 1 and 2, in this register)
ATM cells with header bytes that match the “user-defined”
header byte patterns, or to filter ATM cells with header bytes
that do NOT match the “user-defined” header byte patterns.
0 – Configures Transmit User Cell Filter # 2 to filter user cells
that do NOT match the header byte patterns (as defined in
the “ “ registers).
1 – Configures Transmit User Cell Filter # 2 to filter user cells
that do match the header byte patterns (as defined in the “ “
registers).
Notes:
334
This bit-field is only active if “Transmit User Cell
Filter # 2” has been enabled.
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 273: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Pattern Register –
Header Byte 1 (Address = 0xNF64)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 2 – Pattern Register – Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 2 –
Pattern Register – Header Byte
1
R/W
Transmit User Cell Filter # 2 – Pattern Register – Header
Byte 1:
The User Cell filtering criteria (for Transmit User Cell Filter #
2) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 2 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 2 – Check
Register – Header Byte 1” permits the user to define the User
Cell Filtering criteria for “Octet # 1” of the incoming User Cell.
The user will write the header byte pattern (for Octet 1) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 2 – Check Register – Header Byte 1” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
335
XRT94L33
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S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 274: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Pattern Register –
Header Byte 2 (Address = 0XNF65)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 2 – Pattern Register – Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 2 –
Pattern Register – Header Byte
2
R/W
Transmit User Cell Filter # 2 – Pattern Register – Header
Byte 2:
The User Cell filtering criteria (for Transmit User Cell Filter #
2) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 2 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 2 – Check
Register – Header Byte 2” permits the user to define the User
Cell Filtering criteria for “Octet # 2” of the incoming User Cell.
The user will write the header byte pattern (for Octet 2) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 2 – Check Register – Header Byte 2” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
336
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 275: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Pattern Register –
Header Byte 3 (Address = 0xNF66)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 2 – Pattern Register – Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 2 –
Pattern Register – Header Byte
3
R/W
Transmit User Cell Filter # 2 – Pattern Register – Header
Byte 3:
The User Cell filtering criteria (for Transmit User Cell Filter #
2) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 2 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 2 – Check
Register – Header Byte 3” permits the user to define the User
Cell Filtering criteria for “Octet # 3” of the incoming User Cell.
The user will write the header byte pattern (for Octet 3) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 2 – Check Register – Header Byte 3” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
337
XRT94L33
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S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 276: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Pattern Register –
Header Byte 4 (Address = 0xNF67)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 2 – Pattern Register – Byte 4 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 2 –
Pattern Register – Header Byte
4
R/W
Transmit User Cell Filter # 2 – Pattern Register – Header
Byte 4:
The User Cell filtering criteria (for Transmit User Cell Filter #
2) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 2 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 2 – Check
Register – Header Byte 4” permits the user to define the User
Cell Filtering criteria for “Octet # 4” of the incoming User Cell.
The user will write the header byte pattern (for Octet 4) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 2 – Check Register – Header Byte 4” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
338
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 277: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Check Register – Byte
1 (Address = 0xNF68)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 2 – Check Register – Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 2 –
Check Register – Header Byte
1
R/W
Transmit User Cell Filter # 2 – Check Register – Header
Byte 1:
The User Cell filtering criteria (for Transmit User Cell Filter #
2) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 2 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 2 – Pattern
Register – Header Byte 1” permits the user to define the User
Cell Filtering criteria for “Octet # 1” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 1” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 – Pattern Register – Header Byte 1” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 1” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Register – Header Byte 1”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 1” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 1” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 2 – Pattern Register – Header Byte 1”).
339
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 278: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Check Register – Byte
2 (Address = 0xNF69)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 2 – Check Register – Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 2 –
Check Register – Header Byte 2
R/W
Transmit User Cell Filter # 2 – Check Register – Header
Byte 2:
The User Cell filtering criteria (for Transmit User Cell Filter
# 2) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 2 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 2 –
Pattern Register – Header Byte 2” permits the user to
define the User Cell Filtering criteria for “Octet # 2” within
the incoming User Cell.
More specifically, these
READ/WRITE register bits permit the user to specify which
bit(s) in “Octet 2” of the incoming user cell (in the Transmit
ATM Cell Processor Block) are to be checked against the
corresponding bit-fields within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Register – Header Byte 2” by the User Cell Filter, when
determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces
the Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 2” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Register – Header Byte 2”.
Writing a “0” to a particular bit-field in this register causes
the Transmit User Cell Filter to treat the corresponding bit
within “Octet # 2” (in the incoming user cell) as a “don’t
care” (e.g., to forgo the comparison between the
corresponding bit in “Octet # 2” of the incoming user cell
with the corresponding bit-field in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Register – Header Byte 2”).
340
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 279: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Check Register – Byte
3 (Address = 0xNF6A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 2 – Check Register – Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 2 –
Check Register – Header Byte
3
R/W
Transmit User Cell Filter # 2 – Check Register – Header
Byte 3:
The User Cell filtering criteria (for Transmit User Cell Filter #
2) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 2 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 2 – Pattern
Register – Header Byte 3” permits the user to define the User
Cell Filtering criteria for “Octet # 3” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 3” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 – Pattern Register – Header Byte 3” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 3” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Register – Header Byte 3”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 3” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 3” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 2 – Pattern Register – Header Byte 3”).
341
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 280: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Check Register – Byte
4 (Address = 0xNF6B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 2 – Check Register – Byte 4 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 2 –
Check Register – Header Byte
4
R/W
Transmit User Cell Filter # 2 – Check Register – Header
Byte 4:
The User Cell filtering criteria (for Transmit User Cell Filter #
2) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 2 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 2 – Pattern
Register – Header Byte 4” permits the user to define the User
Cell Filtering criteria for “Octet # 4” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 4” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 2 – Pattern Register – Header Byte 4” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 4” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 2 – Pattern
Register – Header Byte 4”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 4” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 4” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 2 – Pattern Register – Header Byte 4”).
342
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 281: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Filtered Cell Count –
Byte 3 (Address = 0xNF6C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 2 – Filtered Cell Count[31:24]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 2 – Filtered
Cell Count[31:24]
RUR
DESCRIPTION
Transmit User Cell Filter # 2 – Filtered Cell Count[31:24]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 2 – Filtered Cell
Count – Bytes 2” through “0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 2 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – User Cell Filter #
2” Register (Address = 0xNF63), these register bits will be incremented
anytime User Cell Filter # 2 performs any of the following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
This particular register contains the MSB (Most Significant Byte) value
for this 32-bit expression.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
343
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 282: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Filtered Cell Count –
Byte 2 (Address = 0xNF6D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 2 – Filtered Cell Count[23:16]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 2 – Filtered
Cell Count[23:16]
RUR
DESCRIPTION
Transmit User Cell Filter # 2 – Filtered Cell Count[23:16]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 2 – Filtered Cell
Count – Bytes 3, 1 and 0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 2 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 2” Register (Address = 0xNF63), these register bits will be
incremented anytime User Cell Filter # 2 performs any of the following
functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
344
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 283: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Filtered Cell Count –
Byte 1 (Address = 0xNF6E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 2 – Filtered Cell Count[15:8]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 2 – Filtered
Cell Count[15:8]
RUR
DESCRIPTION
Transmit User Cell Filter # 2 – Filtered Cell Count[15:8]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 2 – Filtered Cell
Count – Bytes 3, 2 and 0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 2 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 2” Register (Address = 0xNF63), these register bits will be
incremented anytime Transmit User Cell Filter # 2 performs any of the
following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
345
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 284: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 2 – Filtered Cell Count –
Byte 0 (Address = 0xNF6F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 2 – Filtered Cell Count[7:0]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 2 – Filtered
Cell Count[7:0]
RUR
DESCRIPTION
Transmit User Cell Filter # 2 – Filtered Cell Count[7:0]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 2 – Filtered Cell
Count – Bytes 3” through “1” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 2 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 2” Register (Address = 0xNF63), these register bits will be
incremented anytime Transmit User Cell Filter # 2 performs any of the
following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
This particular register contains the LSB (Least Significant Byte) value
for this 32-bit expression.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
346
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 285: Transmit ATM Cell Processor Block – Transmit User Cell Filter Control – Filter 3 (Address =
0xNF63)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
BIT 1
BIT 0
Transmit User
Cell Filter # 3
Enable
Copy Cell
Enable
Discard Cell
Enable
Filter if
Pattern Match
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-4
Unused
R/O
3
Transmit User Cell Filter # 3
Enable
R/W
DESCRIPTION
Transmit User Cell Filter # 3 – Enable:
This READ/WRITE bit-field permits the user to either enable
or disable Transmit User Cell Filter # 3.
If the user enables Transmit User Cell Filter # 3, then
Transmit User Cell Filter # 3 will function per the configuration
settings in Bits 2 through 0, within this register.
If the user disables Transmit User Cell Filter # 3, then
Transmit User Cell Filter # 3 then all cells that are applied to
the input of Transmit User Cell Filter # 3 will pass through to
the output of Transmit User Cell Filter # 3.
0 – Disables Transmit User Cell Filter # 3.
1 – Enables Transmit User Cell Filter # 3.
2
Copy Cell Enable
R/W
Copy Cell Enable – Transmit User Cell Filter # 3:
This READ/WRITE bit-field permits the user to either
configure Transmit User Cell Filter # 3 (within the Transmit
ATM Cell Processor Block) to copy all cells that have header
byte patterns that comply with the “user-defined” criteria, per
Transmit User Cell Filter # 3, or to NOT copy any of these
cells.
If the user configures Transmit User Cell Filter # 3 to copy all
cells complying with a certain “header-byte” pattern, then a
copy (or replicate) of this “compliant” ATM cell will be routed
to the Transmit Cell Extraction Buffer.
If the user configures Transmit User Cell Filter # 3 to NOT
copy all cells complying with a certain “header-byte” pattern,
then NO copies (or replicates) of these “compliant” ATM cells
will be made nor will any be routed to the Transmit Cell
Extraction Buffer.
0 – Configures Transmit User Cell Filter # 3 to NOT copy any
cells that have header byte patterns which are compliant with
the “user-defined” filtering criteria.
1 – Configures Transmit User Cell Filter # 3 to copy any cells
that have header byte patterns that are compliant with the
“user-defined” filtering criteria, and to route these copies (of
cells) to the Transmit Cell Extraction Buffer.
Notes:
1
Discard Cell Enable
R/W
This bit-field is only active if “Transmit User Cell
Filter # 3” has been enabled.
Discard Cell Enable – Transmit User Cell Filter # 3:
This READ/WRITE bit-field permits the user to either
347
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A
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N
E
L
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S
T
S
T
O
S
T
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M---111 M
MA
AP
PP
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ER
R ––– A
AT
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MR
RE
EG
GIIIS
ST
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LD
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S333///E
E333///S
ST
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S---111 T
TO
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S---333///S
ST
Rev222...000...000
configure Transmit User Cell Filter # 3 (within the Transmit
ATM Cell Processor Block) to discard all cells that have
header byte patterns that comply with the “user-defined”
criteria, per Transmit User Cell Filter # 3, or NOT discard any
of these cells.
If the user configures Transmit User Cell Filter # 3 to NOT
discarded any cells that is compliant with a certain “headerbyte” pattern, then the cell will be retained for further
processing.
0 – Configures Transmit User Cell Filter # 3 to NOT discard
any cells that have header byte patterns that are compliant
with the “user-defined” filtering criteria.
1 – Configures Transmit User Cell Filter # 3 to discard any
cells that have header byte patterns that are compliant with
the “user-defined” filtering criteria.
Notes:
0
Filter if Pattern Match
R/W
This bit-field is only active if “Transmit User Cell
Filter # 3” has been enabled.
Filter if Pattern Match – Transmit User Cell Filter # 3:
This READ/WRITE bit-field permits the user to either
configure Transmit User Cell Filter # 3 to filter (based upon
the configuration settings for Bits 1 and 2, in this register)
ATM cells with header bytes that match the “user-defined”
header byte patterns, or to filter ATM cells with header bytes
that do NOT match the “user-defined” header byte patterns.
0 – Configures Transmit User Cell Filter # 3 to filter user cells
that do NOT match the header byte patterns (as defined in
the “ “ registers).
1 – Configures Transmit User Cell Filter # 3 to filter user cells
that do match the header byte patterns (as defined in the “ “
registers).
Notes:
348
This bit-field is only active if “Transmit User Cell
Filter # 3” has been enabled.
XRT94L33
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A
N
N
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L
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S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
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S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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ER
RS
S
Rev222...000...000
Table 286: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Pattern Register –
Header Byte 1 (Address = 0xNF64)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 3 – Pattern Register – Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 3 –
Pattern Register – Header Byte
1
R/W
Transmit User Cell Filter # 3 – Pattern Register – Header
Byte 1:
The User Cell filtering criteria (for Transmit User Cell Filter #
3) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 3 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 3 – Check
Register – Header Byte 1” permits the user to define the User
Cell Filtering criteria for “Octet # 1” of the incoming User Cell.
The user will write the header byte pattern (for Octet 1) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 3 – Check Register – Header Byte 1” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
349
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A
P
P
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R
A
T
M
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G
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T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 287: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Pattern Register –
Header Byte 2 (Address = 0xNF65)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 3 – Pattern Register – Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 3 –
Pattern Register – Header Byte
2
R/W
Transmit User Cell Filter # 3 – Pattern Register – Header
Byte 2:
The User Cell filtering criteria (for Transmit User Cell Filter #
3) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 3 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 3 – Check
Register – Header Byte 2” permits the user to define the User
Cell Filtering criteria for “Octet # 2” of the incoming User Cell.
The user will write the header byte pattern (for Octet 2) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 3 – Check Register – Header Byte 2” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
350
XRT94L33
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A
N
N
E
L
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S
E
S
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S
T
O
S
T
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S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 288: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Pattern Register –
Header Byte 3 (Address = 0xNF66)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 3 – Pattern Register – Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 3 –
Pattern Register – Header Byte
3
R/W
Transmit User Cell Filter # 3 – Pattern Register – Header
Byte 3:
The User Cell filtering criteria (for Transmit User Cell Filter #
3) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 3 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 3 – Check
Register – Header Byte 3” permits the user to define the User
Cell Filtering criteria for “Octet # 3” of the incoming User Cell.
The user will write the header byte pattern (for Octet 3) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 3 – Check Register – Header Byte 3” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
351
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P
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A
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 289: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Pattern Register –
Header Byte 4 (Address = 0xNF67)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 3 – Pattern Register – Byte 4 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 3 –
Pattern Register – Header Byte
4
R/W
Transmit User Cell Filter # 3 – Pattern Register – Header
Byte 4:
The User Cell filtering criteria (for Transmit User Cell Filter #
3) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 3 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 3 – Check
Register – Header Byte 4” permits the user to define the User
Cell Filtering criteria for “Octet # 4” of the incoming User Cell.
The user will write the header byte pattern (for Octet 4) that
he/she wishes to use as part of the “User Cell Filtering”
criteria, into this register. The user will also write in a value
into the “Transmit ATM Cell Processor Block – Transmit User
Cell Filter # 3 – Check Register – Header Byte 4” that
indicates which bits within the first octet of the incoming cells
are to be compared with the contents of this register.
352
XRT94L33
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C
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 290: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Check Register – Byte
1 (Address = 0xNF68)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 3 – Check Register – Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 3 –
Check Register – Header Byte
1
R/W
Transmit User Cell Filter # 3 – Check Register – Header
Byte 1:
The User Cell filtering criteria (for Transmit User Cell Filter #
3) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 3 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 3 – Pattern
Register – Header Byte 1” permits the user to define the User
Cell Filtering criteria for “Octet # 1” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 1” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 – Pattern Register – Header Byte 1” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 1” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Register – Header Byte 1”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 1” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 1” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 3 – Pattern Register – Header Byte 1”).
353
XRT94L33
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M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 291: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Check Register – Byte
2 (Address = 0xNF69)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 3 – Check Register – Byte 2 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 3 –
Check Register – Header Byte
2
R/W
Transmit User Cell Filter # 3 – Check Register – Header
Byte 2:
The User Cell filtering criteria (for Transmit User Cell Filter #
3) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 3 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 3 – Pattern
Register – Header Byte 2” permits the user to define the User
Cell Filtering criteria for “Octet # 2” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 2” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 – Pattern Register – Header Byte 2” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 2” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Register – Header Byte 2”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 2” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 2” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 3 – Pattern Register – Header Byte 2”).
354
XRT94L33
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C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 292: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Check Register – Byte
3 (Address = 0xNF6A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 3 – Check Register – Byte 3 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 3 –
Check Register – Header Byte
3
R/W
Transmit User Cell Filter # 3 – Check Register – Header
Byte 3:
The User Cell filtering criteria (for Transmit User Cell Filter #
3) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 3 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 3 – Pattern
Register – Header Byte 3” permits the user to define the User
Cell Filtering criteria for “Octet # 3” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 3” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 – Pattern Register – Header Byte 3” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 3” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Register – Header Byte 3”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 3” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 3” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 3 – Pattern Register – Header Byte 3”).
355
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 293: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Check Register – Byte
4 (Address = 0xNF6B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit User Cell Filter # 3 – Check Register – Byte 4 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit User Cell Filter # 3 –
Check Register – Header Byte
4
R/W
Transmit User Cell Filter # 3 – Check Register – Header
Byte 4:
The User Cell filtering criteria (for Transmit User Cell Filter #
3) is defined based upon the contents of 9 read/write
registers. These registers are the four “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Registers”, the four “Transmit ATM Cell Processor Block –
Transmit User Cell Filter # 3 – Check Registers” and the
“Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 Control Register.
This READ/WRITE register, along with the “Transmit ATM
Cell Processor Block – Transmit User Cell Filter # 3 – Pattern
Register – Header Byte 4” permits the user to define the User
Cell Filtering criteria for “Octet # 4” within the incoming User
Cell. More specifically, these READ/WRITE register bits
permit the user to specify which bit(s) in “Octet 4” of the
incoming user cell (in the Transmit ATM Cell Processor Block)
are to be checked against the corresponding bit-fields within
the “Transmit ATM Cell Processor Block – Transmit User Cell
Filter # 3 – Pattern Register – Header Byte 4” by the User Cell
Filter, when determine whether to “filter” a given User Cell.
Writing a “1” to a particular bit-field in this register, forces the
Transmit User Cell Filter to check and compare the
corresponding bit in “Octet # 4” (of the incoming user cell)
with the corresponding bit in the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter # 3 – Pattern
Register – Header Byte 4”.
Writing a “0” to a particular bit-field in this register causes the
Transmit User Cell Filter to treat the corresponding bit within
“Octet # 4” (in the incoming user cell) as a “don’t care” (e.g.,
to forgo the comparison between the corresponding bit in
“Octet # 4” of the incoming user cell with the corresponding
bit-field in the “Transmit ATM Cell Processor Block – Transmit
User Cell Filter # 3 – Pattern Register – Header Byte 4”).
356
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 294: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Filtered Cell Count –
Byte 3 (Address = 0xNF6C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 3 – Filtered Cell Count[31:24]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 3 – Filtered
Cell Count[31:24]
RUR
DESCRIPTION
Transmit User Cell Filter # 3 – Filtered Cell Count[31:24]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 3 – Filtered Cell
Count – Bytes 2” through “0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 3 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – User Cell Filter #
3” Register (Address = 0xNF63), these register bits will be incremented
anytime User Cell Filter # 3 performs any of the following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
This particular register contains the MSB (Most Significant Byte) value
for this 32-bit expression.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
357
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 295: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Filtered Cell Count –
Byte 2 (Address = 0xNF6D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 3 – Filtered Cell Count[23:16]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 3 – Filtered
Cell Count[23:16]
RUR
DESCRIPTION
Transmit User Cell Filter # 3 – Filtered Cell Count[23:16]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 3 – Filtered Cell
Count – Bytes 3, 1 and 0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 3 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 3” Register (Address = 0xNF63), these register bits will be
incremented anytime User Cell Filter # 3 performs any of the following
functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
358
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 296: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Filtered Cell Count –
Byte 1 (Address = 0xNF6E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 3 – Filtered Cell Count[15:8]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 3 – Filtered
Cell Count[15:8]
RUR
DESCRIPTION
Transmit User Cell Filter # 3 – Filtered Cell Count[15:8]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 3 – Filtered Cell
Count – Bytes 3, 2 and 0” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 3 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 3” Register (Address = 0xNF63), these register bits will be
incremented anytime Transmit User Cell Filter # 3 performs any of the
following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
359
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 297: Transmit ATM Cell Processor Block – Transmit User Cell Filter # 3 – Filtered Cell Count –
Byte 0 (Address = 0xNF6F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
0
0
0
Transmit User Cell Filter # 3 – Filtered Cell Count[7:0]
BIT NUMBER
NAME
TYPE
7–0
Transmit User Cell
Filter # 3 – Filtered
Cell Count[7:0]
RUR
DESCRIPTION
Transmit User Cell Filter # 3 – Filtered Cell Count[7:0]:
These RESET-upon-READ bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit User Cell Filter # 3 – Filtered Cell
Count – Bytes 3” through “1” register contain a 32-bit expression for the
number of User Cells that have been filtered by Transmit User Cell Filter
# 3 since the last read of this register.
Depending upon the configuration settings within the “Transmit ATM Cell
Processor Block – Transmit User Cell Filter Control – Transmit User Cell
Filter # 3” Register (Address = 0xNF63), these register bits will be
incremented anytime Transmit User Cell Filter # 3 performs any of the
following functions.
• Discards an incoming “User Cell”.
• Copies (or Replicates) an incoming “User Cell” and routes the “copy”
to the Transmit Cell Extraction Buffer.
• Both the above actions.
This particular register contains the LSB (Least Significant Byte) value
for this 32-bit expression.
Notes:
If the number of “filtered cells” reaches the value
“0xFFFFFFFF” then these registers will saturate to and remain
at this value (e.g., it will not overflow to “0x00000000”).
360
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1.9
RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK
The register map for the Receive STS-1 TOH and POH Processor Block is presented in the Table below.
Additionally, a detailed description of each of the “Receive STS-1 TOH and POH Processor” block registers is
presented below.
In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the
XRT94L33 device, with the “Receive STS-1 TOH and POH Processor Blocks “highlighted” is presented below
in
Figure 10
Figure 10: Illustration of the Functional Block Diagram of the XRT94L33 device, with the Receive STS1 TOH and POH Processor Blocks “High-lighted”.
Channel 0
Receive
ReceiveSTS-1
STS-1
Telecom
TelecomBus
Bus
Interface
Interface
Block
Block
Clock
Clock
Synthesizer
Synthesizer
Block
Block
From Channels
1&2
Transmit
Transmit
STS-3
STS-3PECL
PECL
Interface
Interface
Block
Block
Receive
Receive
STS-1
STS-1TOH
TOH
Processor
Processor
Block
Block
Receive
Receive
STS-1
STS-1POH
POH
Processor
Processor
Block
Block
Transmit
Transmit
SONET
SONETPOH
POH
Processor
Processor
Block
Block
Transmit
Transmit
STS-3
STS-3TOH
TOH
Processor
Processor
Block
Block
Transmit
TransmitSTS-3
STS-3
Telecom
TelecomBus
Bus
Interface
Interface
Block
Block
Transmit
Transmit
STS-1
STS-1TOH
TOH
Processor
Processor
Block
Block
Transmit
Transmit
STS-1
STS-1POH
POH
Processor
Processor
Block
Block
Receive
Receive
SONET
SONETPOH
POH
Processor
Processor
Block
Block
Receive
Receive
STS-3
STS-3TOH
TOH
Processor
Processor
Block
Block
Clock
Clock&&
Data
Data
Recovery
Recovery
Block
Block
Transmit
TransmitSTS-1
STS-1
Telecom
TelecomBus
Bus
Interface
Interface
Block
Block
DS3/E3
DS3/E3
Framer
Framer
Block
Block
Receive
ReceiveSTS-3
STS-3
Telecom
TelecomBus
Bus
Interface
Interface
Block
Block
DS3/E3
DS3/E3Jitter
Jitter
Attenuator
Attenuator
Block
Block
DS3/E3
DS3/E3
Mapper
Mapper
Block
Block
To Channels 1 & 2
361
Receive
Receive
STS-3
STS-3PECL
PECL
Interface
Interface
Block
Block
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.9.1
Rev222...000...000
RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK REGISTER
Table 298: Receive STS-1 TOH and POH Processor Block Control Register Address Map
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x00 – 0x02
0xN000 –
0xN102
0x03
0xN103
0x04, 0x05
0xN104 –
0xN105
0x06
REGISTER NAME
DEFAULT
VALUES
Reserved
0x00
Receive STS-1 Transport Control Register – Byte 0
0x00
Reserved
0x00
0xN106
Receive STS-1 Transport Status Register – Byte 1
0x00
0x07
0xN107
Receive STS-1 Transport Status Register – Byte 0
0x02
0x08
0xN108
Reserved
0x00
0x09
0xN109
Receive STS-1 Transport Interrupt Status Register – Byte 2
0x00
0x0A
0xN10A
Receive STS-1 Transport Interrupt Status Register – Byte 1
0x00
0x0B
0xN10B
Receive STS-1 Transport Interrupt Status Register – Byte 0
0x00
0x0C
0xN10C
Reserved
0x00
0x0D
0xN10D
Receive STS-1 Transport Interrupt Enable Register – Byte 2
0x00
0x0E
0xN10E
Receive STS-1 Transport Interrupt Enable Register – Byte 1
0x00
0x0F
0xN10F
Receive STS-1 Transport Interrupt Enable Register – Byte 0
0x00
0x10
0xN110
Receive STS-1 Transport B1 Byte Error Count – Byte 3
0x00
0x11
0xN111
Receive STS-1 Transport B1 Byte Error Count – Byte 2
0x00
0x12
0xN112
Receive STS-1 Transport B1 Byte Error Count – Byte 1
0x00
0x13
0xN113
Receive STS-1 Transport B1 Byte Error Count – Byte 0
0x00
0x14
0xN114
Receive STS-1 Transport B2 Byte Error Count – Byte 3
0x00
0x15
0xN115
Receive STS-1 Transport B2 Byte Error Count – Byte 2
0x00
0x16
0xN116
Receive STS-1 Transport B2 Byte Error Count – Byte 1
0x00
0x17
0xN117
Receive STS-1 Transport B2 Byte Error Count – Byte 0
0x00
0x18
0xN118
Receive STS-1 Transport REI-L Error Count – Byte 3
0x00
0x19
0xN119
Receive STS-1 Transport REI-L Error Count – Byte 2
0x00
0x1A
0xN11A
Receive STS-1 Transport REI-L Error Count – Byte 1
0x00
0x1B
0xN11B
Receive STS-1 Transport REI-L Error Count – Byte 0
0x00
0x1C
0xN11C
Reserved
0x00
0x1D, 0x1E
0xN11D –
0xN11E
Reserved
0x00
0x1F
0xN11F
Receive STS-1 Transport – Received K1 Byte Value Register
0x00
362
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x20 – 0x22
0xN120 –
0xN122
0x23
0xN123
0x24 – 0x26
0xN124 –
0xN126
0x27
0xN127
0x28 – 0x2D
0xN128 –
0xN12D
0x2E
REGISTER NAME
DEFAULT
VALUES
Reserved
0x00
Receive STS-1 Transport – Received K2 Byte Value Register
0x00
Reserved
0x00
Receive STS-1 Transport – Received S1 Byte Value Register
0x00
Reserved
0x00
0xN12E
Receive STS-1 Transport – LOS Threshold Value – MSB
0xFF
0x2F
0xN12F
Receive STS-1 Transport – LOS Threshold Value – LSB
0xFF
0x30
0xN130
Reserved
0x00
0x31
0xN131
Receive STS-1 Transport – Receive SF Set Monitor Interval – Byte
2
0x00
0x32
0xN132
Receive STS-1 Transport – Receive SF Set Monitor Interval – Byte
1
0x00
0x33
0xN133
Receive STS-1 Transport – Receive SF Set Monitor Interval – Byte
0
0x00
0x34, 0x35
0xN134,
0xN135
Reserved
0x00
0x36
0xN136
Receive STS-1 Transport – Receive SF Set Threshold – Byte 1
0x00
0x37
0xN137
Receive STS-1 Transport – Receive SF Set Threshold – Byte 0
0x00
0x38, 0x39
0xN138 –
0xN139
Reserved
0x00
0x3A
0xN13A
Receive STS-1 Transport – Receive SF Clear Threshold – Byte 1
0x00
0x3B
0xN13B
Receive STS-1 Transport – Receive SF Clear Threshold – Byte 0
0x00
0x3C
0xN13C
Reserved
0x00
0x3D
0xN13D
Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte
2
0x00
0x3E
0xN13E
Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte
1
0x00
0x3F
0xN13F
Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte
0
0x00
0x40, 0x41
0xN140 –
0xN141
Reserved
0x00
0x42
0xN142
Receive STS-1 Transport – Receive SD Set Threshold – Byte 1
0x00
0x43
0xN143
Receive STS-1 Transport – Receive SD Set Threshold – Byte 0
0x00
0x44, 0x45
0xN144,
0xN145
Reserved
0x00
0x46
0xN146
Receive STS-1 Transport – Receive SD Clear Threshold – Byte 1
0x00
363
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
DEFAULT
VALUES
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x47
0xN147
0x48 – 0x4A
0xN14B –
0xN14A
0x4B
0xN14B
0x4C – 0x4E
0xN14C –
0xN14E
0x4F
0xN14F
0x50 – 0x51
0xN150 –
0xN151
0x52
0xN152
Receive STS-1 Transport – Receive SD Burst Error Count
Tolerance – Byte 1
0x00
0x53
0xN153
Receive STS-1 Transport – Receive SD Burst Error Count
Tolerance – Byte 0
0x00
0x54, 0x55
0xN154,
0xN155
Reserved
0x00
0x56
0xN156
Receive STS-1 Transport – Receive SF Burst Error Count Tolerance
– Byte 1
0x00
0x57
0xN157
Receive STS-1 Transport – Receive SF Burst Error Count Tolerance
– Byte 0
0x00
0x58
0xN158
Reserved
0x00
0x59
0xN159
Receive STS-1 Transport – Receive SD Clear Monitor Interval –
Byte 2
0x00
0x5A
0xN15A
Receive STS-1 Transport – Receive SD Clear Monitor Interval –
Byte 1
0x00
0x5B
0xN15B
Receive STS-1 Transport – Receive SD Clear Monitor Interval –
Byte 0
0x00
0x5C
0xN15C
Reserved
0x00
0x5D
0xN15D
Receive STS-1 Transport – Receive SF Clear Monitor Interval –
Byte 2
0x00
0x5E
0xN15E
Receive STS-1 Transport – Receive SF Clear Monitor Interval –
Byte 1
0x00
0x5F
0xN15F
Receive STS-1 Transport – Receive SF Clear Monitor Interval –
Byte 0
0x00
0x60 – 0x62
0xN160 –
0xN162
Reserved
0x00
0x63
0xN163
Receive STS-1 Transport – Auto AIS Control Register
0x00
0x64 – 0x6A
0xN164 –
0xN16A
Reserved
0x00
0x6B
0xN16B
Receive STS-1 Transport – Auto AIS (in Downstream STS-1s)
Control Register
0x00
REGISTER NAME
Receive STS-1 Transport – Receive SD Clear Threshold – Byte 0
0x00
Reserved
0x00
Receive STS-1 Transport – Force SEF Condition
0x00
Reserved
0x00
Receive STS-1 Transport – Receive J0 Byte Trace Buffer Control
Register
0x00
Reserved
364
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
DEFAULT
VALUES
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0x6C – 0x82
0xN16C –
0xN182
0x83
0xN183
0x84, 0x85
0xN184 0xN185
0x86
0xN186
Receive STS-1 Path – Control Register – Byte 1
0x87
0xN187
Receive STS-1 Path – Status Register – Byte 0
0x00
0x88
0xN188
Reserved
0x00
0x89
0xN189
Receive STS-1 Path – Interrupt Status Register – Byte 2
0x00
0x8A
0xN18A
Receive STS-1 Path – Interrupt Status Register – Byte 1
0x00
0x8B
0xN18B
Receive STS-1 Path – Interrupt Status Register – Byte 0
0x00
0x8C
0xN18C
Reserved
0x00
0x8D
0xN18D
Receive STS-1 Path – Interrupt Enable Register – Byte 2
0x00
0x8E
0xN18E
Receive STS-1 Path – Interrupt Enable Register – Byte 1
0x00
0x8F
0xN18F
Receive STS-1 Path – Interrupt Enable Register – Byte 0
0x00
0x90 – 0x92
0xN190 –
0xN192
Reserved
0x00
0x93
0xN193
Receive STS-1 Path – SONET Receive RDI-P Register
0x00
0x94, 0x95
0xN194,
0xN195
Reserved
0x00
0x96
0xN196
Receive STS-1 Path – Received Path Label Value (C2 Byte)
Register
0x00
0x97
0xN197
Receive STS-1 Path – Expected Path Label Value (C2 Byte)
Register
0x00
0x98
0xN198
Receive STS-1 Path – B3 Error Count Register – Byte 3
0x00
0x99
0xN199
Receive STS-1 Path – B3 Error Count Register – Byte 2
0x00
0x9A
0xN19A
Receive STS-1 Path – B3 Error Count Register – Byte 1
0x00
0x9B
0xN19B
Receive STS-1 Path – B3 Error Count Register – Byte 0
0x00
0x9C
0xN19C
Receive STS-1 Path – REI-P Error Count Register – Byte 3
0x00
0x9D
0xN19D
Receive STS-1 Path – REI-P Error Count Register – Byte 2
0x00
0x9E
0xN19E
Receive STS-1 Path – REI-P Error Count Register – Byte 1
0x00
0x9F
0xN19F
Receive STS-1 Path – REI-P Error Count Register – Byte 0
0x00
0xA0 – 0xA5
0xN1A0 –
0xN1A5
Reserved
0x00
0xA6
0xN1A6
Receive STS-1 Path – Pointer Value Register – Byte 1
0x00
0xA7
0xN1A7
Receive STS-1 Path – Pointer Value Register – Byte 0
0x00
REGISTER NAME
Reserved
0x00
Receive STS-1 Path – Control Register – Byte 2
0x00
Reserved
0x00
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M---111 M
MA
AP
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
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HA
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ST
INDIVIDUAL
REGISTER
ADDRESS
ADDRESS
LOCATION
0xA8 – 0xBA
0xN1A8 –
0xN1BA
0xBB
0xN1BB
0xBC – 0xBE
0xN1BC –
0xN1BE
0xBF
0xN1BF
0xC0 – 0xC2
0xN1C0 –
0xN1C2
0xC3
0xN1C3
0xC4 – 0xD2
0xN1C4 –
0xN1D2
0xD3
0xN1D3
0xC4-0xC6
0xN1C4 –
0xN1C6
0xD7
0xN1D7
0xD8 – 0xDA
0xN1D8 –
0xN1DA
0xDB
0xN1DB
0xDC – 0xDE
0xN1DC –
0xN1DE
0xDF
0xN1DF
0xE0 – 0xE2
0xN1E0 –
0xN1E2
0xE3
0xN1E3
0xE4 – 0xE6
0xN1E4 –
0xN1E6
0xE7
0xN1E7
0xE8 – 0xEA
0xN1E8 –
0xN1EA
0xEB
0xN1EB
0xEC – 0xEE
0xN1EC –
0xN1EE
0xEF
0xN1EF
0xF0 – 0xF2
0xN1F0 –
0xN1F2
0xF3
0xN1F3
0xF6 – 0xFF
0xN1F6 –
0xN1FF
REGISTER NAME
Rev222...000...000
DEFAULT
VALUES
Reserved
0x00
Receive STS-1 Path – AUTO AIS Control Register
0x00
Reserved
0x00
Receive STS-1 Path – Serial Port Control Register
0x00
Reserved
0x00
Receive STS-1 Path – SONET Receive Auto Alarm Register – Byte
0
0x00
Reserved
Receive STS-1 Path – Receive J1 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive B3 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive C2 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive G1 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive F2 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive H4 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive Z3 Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive Z4 (K3) Byte Capture Register
0x00
Reserved
0x00
Receive STS-1 Path – Receive Z5 Byte Capture Register
0x00
Reserved
0x00
366
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A
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A
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DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
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RS
S
Rev222...000...000
1.9.2
RECEIVE STS-1 TOH AND POH PROCESSOR BLOCK REGISTER DESCRIPTION
Table 299: Receive STS-1 Transport Control Register – Byte 0 (Address Location = 0xN103)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SF Detect
Enable
SD Detect
Enable
Descramble
Disable
Unused
REI-L
Error Type
B2 Error
Type
B1 Error
Type
R/O
R/W
R/W
R/W
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6
SF Detect
Enable
R/W
DESCRIPTION
Signal Failure (SF) Detect Enable:
This READ/WRITE bit-field permits the user to enable or disable SF
Detection by the Receive STS-1 TOH Processor block.
0 – SF Detection is disabled.
1 – SF Detection is enabled:
5
SD Detect
Enable
R/W
Signal Degrade (SD) Detect Enable:
This READ/WRITE bit-field permits the user to enable or disable SD
Detection by the Receive STS-1 TOH Processor block.
0 – SD Detection is disabled.
1 – SD Detection is enabled.
4
Descramble
Disable
R/W
De-Scramble Disable:
This READ/WRITE bit-field permits the user to either enable or disable descrambling by the Receive STS-1 TOH Processor block, associated with
channel N.
0 – De-Scrambling is enabled.
1 – De-Scrambling is disabled.
3
Unused
R/O
2
REI-L Error
Type
R/W
REI-L Error Type:
This READ/WRITE bit-field permits the user to specify how the “Receive
Transport REI-L Error Count” register is incremented.
0 – Configures the Receive STS-1 TOH Processor block to count REI-L Bit
Errors.
In this case the “Receive Transport REI-L Error Count” register will be
incremented by the value of the lower nibble within the M0/M1 byte.
1 – Configures the Receive STS-1 TOH Processor block to count REI-L
Frame Errors.
In this case the “Receive Transport REI-L Error Count” register will be
incremented each time the Receive STS-1 TOH Processor block receives a
“non-zero” M0/M1 byte.
1
B2 Error
Type
R/W
B2 Error Type:
This READ/WRITE bit-field permits the user to specify how the “Receive
367
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Transport B2 Error Count” register is incremented.
0 – Configures the Receive STS-1 TOH Processor block to count B2 bit
errors.
In this case, the “Receive Transport B2 Error Count” register will be
incremented by the number of bits, within the B2 value, that is in error.
1 – Configures the Receive STS-1 TOH Processor block to count B2 frame
errors.
In this case, the “Receive Transport B2 Error Count” register will be
incremented by the number of erred STS-1 frames.
0
B1 Error
Type
R/W
B1 Error Type:
This READ/WRITE bit-field permits the user to specify how the “Receive
Transport B1 Error Count” register is incremented.
0 – Configures the Receive STS-1 TOH Processor block to count B1 bit
errors.
In this case, the “Receive Transport B1 Error Count” register will be
incremented by the number of bits, within the B1 value, that is in error.
1 – Configures the Receive STS-1 TOH Processor block to count B2 bit
errors.
In this case, the “Receive Transport B1 Error Count” register will be
incremented by the number of erred STS-1 frames.
368
XRT94L33
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A
N
N
E
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S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
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R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 300: Receive STS-1 Transport Status Register – Byte 1 (Address Location= 0xN106)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Unused
BIT 2
BIT 1
BIT 0
J0 Message
Mismatch
J0 Message
Unstable
AIS_L
Detected
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–3
Unused
R/O
2
J0 Message
Mismatch
R/O
DESCRIPTION
J0 – Section Trace Mismatch Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently declaring the Section Trace Mismatch condition.
The Receive STS-1 TOH Processor block will declare a J0 (Section Trace)
Mismatch condition, whenever it accepts a J0 Message that differs from the
“Expected J0 Message”.
0 – Section Trace Mismatch Condition is NOT declared.
1 – Section Trace Mismatch Condition is currently declared.
1
J0 Message
Unstable
R/O
J0 – Section Trace Unstable Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently declaring the Section Trace Instability condition.
The Receive STS-1 TOH Processor block will declare a J0 (Section Trace)
Unstable condition, whenever the “J0 Unstable” counter reaches the value 8.
The “J0 Unstable” counter will be incremented for each time that it receives a
J0 message that differs from the “Expected J0 Message”. The “J0 Unstable”
counter is cleared to “0” whenever the Receive STS-3 TOH Processor block
has received a given J0 Message 3 (or 5) consecutive times.
Note:
Receiving a given J0 Message 3 (or 5) consecutive times also sets
this bit-field to “0”.
0 – Section Trace Instability condition is NOT declared.
1 – Section Trace Instability condition is currently declared.
0
AIS_L
Detected
R/O
AIS-L State:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently detecting an AIS-L (Line AIS) pattern in the
incoming STS-1 data stream. AIS-L is declared if bits 6, 7 and 8 (e.g., the
Least Significant Bits, within the K2 byte) value the value “1, 1, 1” for five
consecutive STS-1 frames.
0 – AIS-L is NOT currently declared.
1 – AIS-L is currently being declared.
369
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R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 301: Receive STS-1 Transport Status Register – Byte 0 (Address Location = 0xN107)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RDI-L
Declared
S1 Unstable
APS
Unstable
SF
Detected
SD
Detected
LOF
Defect
Detected
SEF
Defect
Declared
LOS
Defect
Declared
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
RDI-L
Declared
R/O
DESCRIPTION
RDI-L Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is detecting a Line-Remote Defect Indicator, in the incoming
STS-1 signal. RDI-L is declared when bits 6, 7 and 8 (e.g., the three least
significant bits) of the K2 byte contains the “1, 1, 0” pattern in 5 consecutive
STS-1 frames.
0 – RDI-L is NOT being declared.
1 – RDI-L is currently being declared.
6
S1 Unstable
R/O
S1 Unstable Condition:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently declaring the “S1 Byte Instability” condition. The
Receive STS-1 TOH Processor block will declare an “S1 Byte Instability”
condition whenever the “S1 Byte Unstable Counter” reaches the value 32.
The “S1 Byte Unstable Counter” is incremented for each time that the Receive
STS-1 TOH Processor block receives an S1 byte that differs from the
previously received S1 byte. The “S1 Byte Unstable Counter” is cleared to “0”
when the same S1 byte is received for 8 consecutive STS-1 frames.
Note:
Receiving a given S1 byte, in 8 consecutive STS-1 frames also sets
this bit-field to “0”.
0 – S1 Instability Condition is NOT declared.
1 – S1 Instability Condition is currently declared.
5
APS Unstable
R/O
APS (K1, K2 Byte) Instability:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently declaring the “K1, K2 Byte Unstable” condition.
The Receive STS-1 TOH Processor block will declare a “K1, K2 Byte
Unstable” condition whenever the Receive STS-1 TOH Processor block fails to
receive the same set of K1, K2 bytes, in 12 consecutive STS-1 frames. The
“K1, K2 Byte Instability” condition is cleared whenever the STS-1 Receiver
receives a given set of K1, K2 byte values in three consecutive STS-1 frames.
0 – K1, K2 Instability Condition is NOT declared.
1 – K1, K2 Instability Condition is currently declared.
4
SF Detected
R/O
SF (Signal Failure) Defect Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently declaring the SF defect. The SF defect is
declared when the number of B2 errors observed over a given time interval
exceeds a certain threshold.
0 – SF Defect is NOT being declared.
This bit is set to “0” when the number of B2 errors (accumulated over a given
370
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S
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S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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RS
S
Rev222...000...000
interval of time) does not exceed the “SF Declaration” threshold.
1 – SF Defect is being declared.
This bit is set to “1” when the number of B2 errors (accumulated over a given
interval of time) does exceed the “SF Declaration” threshold.
3
SD Detected
R/O
SD (Signal Degrade) Defect Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently declaring the SD defect. The SD defect is
declared when the number of B2 errors observed over a given time interval
exceeds a certain threshold.
0 – SD Defect is NOT being declared.
This bit is set to “0” when the number of B2 errors (accumulated over a given
interval of time) does not exceed the “SD Declaration” threshold.
1 – SD Defect is being declared.
This bit is set to “1” when the number of B2 errors (accumulated over a given
interval of time) does exceed the “SD Declaration” threshold.
2
LOF
Defect
Declared
R/O
LOF (Loss of Frame) Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently declaring the LOF defect. The Receive STS-1
TOH Processor block will declare the LOF defect if it has been declaring the
SEF condition for 24 consecutive STS-1 frame periods. Once the LOF defect
is declared, then the Receive STS-1 TOH Processor block will clear the LOF
defect if it has not been declaring the SEF condition for 3ms (or 24
consecutive STS-1 frame periods).
0 – The Receive STS-1 TOH Processor block is NOT currently declaring the
LOF condition.
1 – The Receive STS-1 TOH Processor block is currently declaring the LOF
condition.
1
SEF
Defect
Declared
R/O
SEF (Severely Errored Frame):
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently declaring an SEF condition. The Receive STS-1
TOH Processor block will declare an SEF condition if it detects Framing
Alignment byte errors in four consecutive STS-1 frames. Once the SEF
condition is declared the Receive STS-1 TOH Processor block will clear the
SEF condition if it detects two consecutive STS-1 frames with un-erred
framing alignment bytes.
0 – Indicates that the Receive STS-1 TOH Processor block is NOT declaring
the SEF condition.
1 – Indicates that the Receive STS-1 TOH Processor block is currently
declaring the SEF condition.
0
LOS
Defect
Declared
R/O
LOS (Loss of Signal) Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 TOH
Processor block is currently declaring an LOS (Loss of Signal) condition. The
Receive STS-1 TOH Processor block will declare an LOS condition if it detects
“LOS_THRESHOLD[15:0]” consecutive “All Zero” bytes in the incoming STS-1
data stream.
Note:
The user can set the “LOS_THRESHOLD[15:0]” value by writing the
appropriate data into the “Receive STS-1 Transport – LOS
Threshold Value” Register (Address Location= 0xN12E and
0xN12F).
0 – Indicates that the Receive STS-1 TOH Processor block is NOT currently
371
XRT94L33
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M
M
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A
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M
R
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S
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E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
declaring an LOS condition.
1 – Indicates that the Receive STS-1 TOH Processor block is currently
declaring an LOS condition.
372
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N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 302: Receive STS-1 Transport Interrupt Status Register – Byte 2 (Address Location= 0xN109)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
Change of AIS-L
Interrupt Status
Change of RDI-L
Interrupt Status
R/O
R/O
R/O
R/O
R/O
R/O
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-2
Unused
R/O
1
Change of AIS-L
Interrupt Status
RUR
DESCRIPTION
Change of AIS-L (Line AIS) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
AIS-L Condition” interrupt has occurred since the last read of this register.
0 – The “Change of AIS-L Condition” interrupt has not occurred since the
last read of this register.
1 – The “Change of AIS-L Condition” interrupt has occurred since the last
read of this register.
Note:
0
Change of
RDI-L Interrupt
Status
RUR
The user can obtain the current state of AIS-L by reading the
contents of Bit 0 (AIS-L Defect Declared) within the “Receive
STS-1 Transport Status Register – Byte 1” (Address Location=
0xN106).
Change of RDI-L (Line - Remote Defect Indicator) Condition Interrupt
Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
RDI-L Condition” interrupt has occurred since the last read of this register.
0 – The “Change of RDI-L Condition” interrupt has not occurred since the
last read of this register.
1 – The “Change of RDI-L Condition” interrupt has occurred since the last
read of this register.
Note:
The user can obtain the current state of RDI-L by reading out the
state of Bit 7 (RDI-L Declared) within the “Receive STS-1
Transport Status Register – Byte 0” (Address Location=
0xN107).
373
XRT94L33
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M
M
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R
A
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S
T
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R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 303: Receive STS-1 Transport Interrupt Status Register – Byte 1 (Address Location= 0xN10A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New S1
Byte
Interrupt
Status
Change in
S1 Unstable
State
Interrupt
Status
Change in
J0 Unstable
State
Interrupt
Status
New J0
Message
Interrupt
Status
J0 Mismatch
Interrupt
Status
Unused
Change in
APS
Unstable
State
Interrupt
Status
NEW K1K2
Byte
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
R/O
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7
New S1 Byte Value
Interrupt Status
RUR
New S1 Byte Value Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“New S1 Byte Value” Interrupt has occurred since the last read
of this register.
0 – Indicates that the “New S1 Byte Value” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “New S1 Byte Value” interrupt has
occurred since the last read of this register.
Note:
6
Change in S1 Byte
Unstable State Interrupt
Status
RUR
The user can obtain the value for this most recently
accepted value of the S1 byte by reading the “Receive
STS-1 Transport S1 Value” register (Address
Location= 0xN127).
Change in S1 Byte Unstable State – Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Change in S1 Byte Unstable State” Interrupt has occurred since
the last read of this register.
0 – Indicates that the “Change in S1 Byte Unstable State”
Interrupt has occurred since the last read of this register.
1 – Indicates that the “Change in S1 Byte Unstable State”
Interrupt has not occurred since the last read of this register.
Note:
5
Change in J0 Message
Unstable State Interrupt
Status
RUR
The user can obtain the current “S1 Unstable” state by
reading the contents of Bit 6 (S1 Unstable) within the
“Receive STS-1 Transport Status Register – Byte 0”
(Address Location= 0xN107).
Change of J0 (Section Trace) Message Unstable condition –
Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Change of J0 (Section Trace) Message Instability” condition
interrupt has occurred since the last read of this register.
0 – Indicates that the “Change of J0 (Section Trace) Message
Instability” condition interrupt has not occurred since the last
read of this register.
1 – Indicates that the “Change of J0 (Section Trace) Message
Instability” condition interrupt has occurred since the last read of
this register.
4
New J0 Message
Interrupt Status
RUR
New J0 Trace Message Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
374
XRT94L33
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LD
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S333///E
E333///S
ST
TS
S---111 T
TO
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ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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S
Rev222...000...000
“New J0 Trace Message” interrupt has occurred since the last
read of this register.
0 – Indicates that the “New J0 Trace Message Interrupt” has not
occurred since the last read of this register.
1 – Indicates that the “New J0 Trace Message Interrupt” has
occurred since the last read of this register.
Note:
3
J0 Mismatch Interrupt
Status
RUR
The user can read out the contents of the “Receive J0
Trace Buffer”, which is located at Address Locations
0xN300 through 0xN33F.
Change in J0 – Section Trace Mismatch Condition” Interrupt
Status:
This RESET-upon-READ bit-field indicates whether or not the
“Change in J0 – Section Trace Mismatch Condition” interrupt has
occurred since the last read of this register.
0 – Indicates that the “Change in J0 – Section Trace Mismatch
Condition” interrupt has not occurred since the last read of this
register.
1 – Indicates that the “Change in J0 – Section Trace Mismatch
Condition” interrupt has occurred since the last read of this
register.
Note:
2
Unused
R/O
1
Change in APS Unstable
State Interrupt Status
RUR
The user can determine whether the “J0 – Section
Trace Mismatch” condition is “cleared” or “declared” by
reading the state of Bit 2 (J0_MIS) within the “Receive
STS-1 Transport Status Register – Byte 1 (Address
Location= 0xN106).
Change of APS (K1, K2 Byte) Instability Condition –
Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Change of APS (K1, K2 Byte) Instability Condition” interrupt has
occurred since the last read of this register.
0 – Indicates that the “Change of APS (K1, K2 Byte) Instability
Condition” interrupt has NOT occurred since the last read of this
register.
1 – Indicates that the “Change of APS (K1, K2 Byte) Instability
Condition” interrupt has occurred since the last read of this
register.
Note:
0
New K1K2 Byte Interrupt
Status
RUR
The user can determine whether the “K1, K2 Instability
Condition” is being declared or cleared by reading out
the contents of Bit 5 (APS_INV), within the “Receive
STS-1 Transport Status Register – Byte 0” (Address
Location= 0xN107).
New K1, K2 Byte Value Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“New K1, K2 Byte Value” Interrupt has occurred since the last
read of this register.
0 – Indicates that the “New K1, K2 Byte Value” Interrupt has
NOT occurred since the last read of this register.
1 – Indicates that the “New K1, K2 Byte Value” Interrupt has
occurred since the last read of this register.
Note:
375
The user can obtain the contents of the new K1 byte by
XRT94L33
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TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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ER
RS
S
CH
HA
AN
NN
NE
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LD
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ST
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S---111 T
TO
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ST
TS
S---333///S
ST
Rev222...000...000
reading out the contents of the “Receive STS-1
Transport K1 Value” Register (Address Location=
0xN11F). Further, the user can also obtain the
contents of the new K2 byte by reading out the
contents of the “Receive STS-1 Transport K2 Value”
Register (Address Location= 0xN123).
376
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A
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A
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R
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S
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HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 304: Receive STS-1 Transport Interrupt Status Register – Byte 0 (Address Location= 0xN10B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change of
SF
Condition
Interrupt
Status
Change of
SD
Condition
Interrupt
Status
Detection of
REI-L Error
Interrupt
Status
Detection of
B2 Error
Interrupt
Status
Detection of
B1 Error
Interrupt
Status
Change of
LOF
Condition
Interrupt
Status
Change of
SEF
Interrupt
Status
Change of
LOS
Condition
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Change of SF
Condition
Interrupt Status
RUR
DESCRIPTION
Change of Signal Failure (SF) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Detection of
SF Interrupt” has occurred since the last read of this register.
0 - The “Change of SF Condition Interrupt” has NOT occurred since the last
read of this register.
1 – The “Change of SF Condition Interrupt” has occurred since the last read of
this register.
Note:
6
Change of SD
Condition
Interrupt Status
RUR
The user can determine the current “SF” condition by reading out the
state of Bit 4( SF Declared) within the “Receive STS-1 Transport
Status Register – Byte 0 (Address Location= 0xN107).
Change of Signal Degrade (SD) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of SD
Condition Interrupt” has occurred since the last read of this register.
0 - The “Change of SD Condition Interrupt” has NOT occurred since the last
read of this register.
1 – The “Change of SD Condition Interrupt” has occurred since the last read of
this register.
Note:
5
Detection of
REI-L Interrupt
Status
RUR
The user can determine the current “SD” condition by reading out the
state of Bit 3 (SD Declared) within the “Receive STS-1 Transport
Status Register – Byte 0 (Address Location= 0xN107).
Detection of Line – Remote Error Indicator Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Detection of
Line – Remote Error Indicator” Interrupt has occurred since the last read of
this register.
0 - The “Detection of Line – Remote Error Indicator” Interrupt has NOT
occurred since the last read of this register.
1 – The “Detection of Line – Remote Error Indicator” Interrupt has occurred
since the last read of this register.
4
Detection of B2
Error Interrupt
Status
RUR
Detection of B2 Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Detection of B2
Error Interrupt” has occurred since the last read of this register.
0 - The “Detection of B2 Error Interrupt” has NOT occurred since the last read
of this register.
1 – The “Detection of B2 Error Interrupt” has occurred since the last read of
this register.
377
XRT94L33
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N
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S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
3
Detection of B1
Error Interrupt
Status
RUR
Rev222...000...000
Detection of B1 Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Detection of B1
Error Interrupt” has occurred since the last read of this register.
0 - The “Detection of B1 Error Interrupt” has NOT occurred since the last read
of this register.
1 – The “Detection of B1 Error Interrupt” has occurred since the last read of
this register
2
Change of LOF
Condition
Interrupt Status
RUR
Change of Loss of Frame (LOF) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of LOF
Condition” interrupt has occurred since the last read of this register.
0 – The “Change of LOF Condition” interrupt has NOT occurred since the last
read of this register.
1 – The “Change of LOF Condition” interrupt has occurred since the last read
of this register.
Note:
1
Change of SEF
Condition
Interrupt Status
RUR
The user can determine the current “LOF” condition by reading out
the state of Bit 2 (LOF Defect Declared) within the “Receive STS-1
Transport Status Register – Byte 0 (Address Location= 0xN107).
Change of SEF Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of SEF
Condition” Interrupt has occurred since the last read of this register.
0 – The “Change of SEF Condition” Interrupt has NOT occurred since the last
read of this register.
1 – The “Change of SEF Condition” Interrupt has occurred since the last read
of this register.
Note:
0
Change of LOS
Condition
Interrupt Status
RUR
The user can determine the current “SEF” condition by reading out
the state of Bit 1 (SEF Defect Declared) within the “Receive STS-1
Transport Status Register – Byte 0 (Address Location= 0xN107).
Change of Loss of Signal (LOS) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change of
LOS Condition” interrupt has occurred since the last read of this register.
0 – The “Change of LOS Condition” Interrupt has NOT occurred since the last
read of this register.
1 – The “Change of LOS Condition” Interrupt has occurred since the last read
of this register.
Note:
The user can determine the current “LOS” status by reading out the
contents of Bit 0 (LOS Defect Declared) within the Receive STS-1
Transport Status Register – Byte 0 (Address Location= 0xN107).
378
XRT94L33
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 305: Receive STS-1 Transport Interrupt Enable Register – Byte 2 (Address Location= 0xN10D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Unused
BIT 1
BIT 0
Change of AIS-L
Condition
Interrupt Enable
Change of RDI-L
Condition
Interrupt Enable
R/O
R/O
R/O
R/O
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–2
Unused
R/O
1
Change of AIS-L
Condition
Interrupt Enable
R/W
DESCRIPTION
Change of AIS-L (Line AIS) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Change of AIS-L Condition” interrupt. If the user enables this
interrupt, then the XRT94L33 device will generate an interrupt in response
to either of the following conditions.
• When the Receive STS-1 TOH Processor block declares the “AIS-L”
condition.
• When the STS-1 Receiver clears the “AIS-L” condition.
0 – Disables the “Change of AIS-L Condition” Interrupt.
1 – Enables the “Change of AIS-L Condition” Interrupt.
0
Change of RDI-L
Condition
Interrupt Enable
R/W
Change of RDI-L (Line Remote Defect Indicator) Condition Interrupt
Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Change of RDI-L Condition” interrupt. If the user enables this
interrupt, then the XRT94L33 device will generate an interrupt in response
to either of the following conditions.
• When the Receive STS-1 TOH Processor block declares the “RDI-L”
condition.
• When the Receive STS-1 TOH Processor clears the “RDI-L” condition.
0 – Disables the “Change of RDI-L Condition” Interrupt.
1 – Enables the “Change of RDI-L Condition” Interrupt.
379
XRT94L33
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 306: Receive STS-1 Transport Interrupt Enable Register – Byte 1 (Address Location= 0xN10E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New S1
Byte
Interrupt
Enable
Change in
S1 Byte
Unstable
State
Interrupt
Enable
Change in
J0 Message
Unstable
State
Interrupt
Enable
New J0
Message
Interrupt
Enable
J0 Mismatch
Interrupt
Enable
Unused
Change in
APS
Unstable
State
Interrupt
Enable
New K1K2
Byte
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
New S1 Byte Value
Interrupt Enable
R/W
DESCRIPTION
New S1 Byte Value Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the “New
S1 Byte Value” Interrupt. If the user enables this interrupt, then the
Receive STS-1 TOH Processor block will generate this interrupt anytime it
receives and accepts a new S1 byte value. The Receive STS-1 TOH
Processor block will accept a new S1 byte after it has received it for 8
consecutive STS-1 frames.
0 – Disables the “New S1 Byte Value” Interrupt.
1 – Enables the “New S1 Byte Value” Interrupt.
6
Change in S1
Unstable State
Interrupt Enable
R/W
Change in S1 Byte Unstable State Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Change in S1 Byte Unstable State” Interrupt. If the user enables this
bit-field, then the Receive STS-1 TOH Processor block will generate an
interrupt in response to either of the following conditions.
•
When the Receive STS-1 TOH Processor block declares the “S1
Byte Instability” condition.
•
When the Receive STS-1 TOH Processor block clears the “S1 Byte
Instability” condition.
0 – Disables the “Change in S1 Byte Unstable State” Interrupt.
1 – Enables the “Change in S1 Byte Unstable State” Interrupt.
5
Change in J0
Message Unstable
State Interrupt
Enable
R/W
Change of J0 (Section Trace) Message Instability condition Interrupt
Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Change of J0 Message Instability Condition” Interrupt. If the user
enables this interrupt, then the Receive STS-1 TOH Processor block will
generate an interrupt in response to either of the following conditions.
•
Whenever the Receive STS-1 TOH Processor block declares the “J0
Message Instability” condition.
•
Whenever the Receive STS-1 TOH Processor block clears the “J0
Message Instability” condition.
0 – Disable the “Change of J0 Message Instability” Interrupt.
1 – Enables the “Change of J0 Message Instability” Interrupt.
4
New J0 Message
Interrupt Enable
R/W
New J0 Trace Message Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the “New
J0 Trace Message” interrupt. If the user enables this interrupt, then the
380
XRT94L33
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S
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R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Receive STS-1 TOH Processor block will generate this interrupt anytime it
receives and accepts a new J0 Trace Message. The Receive STS-1 TOH
Processor block will accept a new J0 Trace Message after it has received
it 3 (or 5) consecutive times.
0 – Disables the “New J0 Trace Message” Interrupt.
1 – Enables the “New J0 Trace Message” Interrupt.
3
J0 Mismatch
Interrupt Enable
R/W
Change in “J0 – Section Trace Mismatch Condition” interrupt
enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Change in J0 – Section Trace Mismatch condition” interrupt. If the
user enables this interrupt, then the Receive STS-1 TOH Processor block
will generate an interrupt in response to either of the following events.
2
Unused
R/O
1
Change in APS
Unstable State
Interrupt Enable
R/W
0
New K1K2 Byte
Interrupt Enable
a.
The Receive STS-1 TOH Processor block declares a “J0 –
Section Trace Mismatch” condition.
b.
The Receive STS-1 TOH Processor block clears the “J0 –
Section Trace Mismatch” condition.
Note:
The user can determine whether the “J0 – Section Trace
Mismatch” condition is “cleared or “declared” by reading the
state of Bit 2 (J0_MIS) within the “Receive STS-1 Transport
Status Register – Byte 1 (Address Location= 0xN106).
Change of APS (K1, K2 Byte) Instability Condition - Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Change of APS (K1, K2 Byte) Instability condition” interrupt. If the
user enables this interrupt, then the Receive STS-1 TOH Processor block
will generate an Interrupt in response to either of the following events.
R/W
a.
If the Receive STS-1 TOH Processor block declares a “K1, K2
Instability” condition.
b.
If the Receive STS-1 TOH Processor block clears the “K1, K2
Instability” condition.
New K1, K2 Byte Value Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “New K1, K2 Byte Value” Interrupt. If the user enables this interrupt,
then the Receive STS-1 TOH Processor block will generate this interrupt
anytime it receives and accepts a new K1, K2 byte value. The Receive
STS-1 TOH Processor block will accept a new K1, K2 byte value, after it
has received it within 3 (or 5) consecutive STS-1 frames.
0 – Disables the “New K1, K2 Byte Value” Interrupt.
1 – Enables the “New K1, K2 Byte Value” Interrupt.
381
XRT94L33
333---C
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M
M
A
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A
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S
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R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 307: Receive STS-1Transport Interrupt Status Register – Byte 0 (Address Location= 0xN10F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Change of
SF
Condition
Interrupt
Enable
Change of
SD
Condition
Interrupt
Enable
Detection of
REI-L Error
Interrupt
Enable
Detection of
B2 Error
Interrupt
Enable
Detection of
B1 Error
Interrupt
Enable
Change of
LOF
Condition
Interrupt
Enable
Change of
SEF
Condition
Interrupt
Enable
Change of
LOS
Condition
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Change of SF
Condition
Interrupt Enable
R/W
DESCRIPTION
Change of Signal Failure (SF) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of Signal Failure (SF) Condition” Interrupt. If the user enables this
interrupt, then the XRT94L33 device will generate an interrupt anytime the
Receive STS-1 TOH Processor block detects an SF condition.
0 – Disables the “Change of SF Condition Interrupt”.
1 – Enables the “Change of SF Condition Interrupt”.
6
Change of SD
Condition
Interrupt Enable
R/W
Change of Signal Degrade (SD) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of Signal Degrade (SD) Condition” Interrupt. If the user enables
this interrupt, then the XRT94L33 device will generate an interrupt anytime
the Receive STS-1 TOH Processor block detects an SD condition.
0 – Disables the “Change of SD Condition Interrupt”.
1 – Enables the “Change of SD Condition Interrupt”.
5
Detection of
REI-L Interrupt
Enable
R/W
Detection of Line – Remote Error Indicator Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of Line – Remote Error Indicator” interrupt. If the user enables
this interrupt, then the XRT94L33 device will generate an interrupt anytime
the Receive STS-1 TOH Processor block detects an REI-L condition.
0 – Disables the “Line - Remote Error Indicator” Interrupt.
1 – Enables the “Line – Remote Error Indicator” Interrupt.
4
Detection of B2
Error Interrupt
Enable
R/W
Detection of B2 Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of B2 Error” Interrupt. If the user enables this interrupt, then the
XRT94L33 device will generate an interrupt anytime the Receive STS-1
TOH Processor block detects a B2 error.
0 – Disables the “Detection of B2 Error Interrupt”.
1 – Enables the “Detection of B2 Error Interrupt”.
3
Detection of B1
Error Interrupt
Enable
R/W
Detection of B1 Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of B1 Error” Interrupt. If the user enables this interrupt, then the
XRT94L33 device will generate an interrupt anytime the Receive STS-1
TOH Processor block detects a B1 error.
0 – Disables the “Detection of B1 Error Interrupt”.
1 – Enables the “Detection of B1 Error Interrupt”.
382
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
2
Change of LOF
Condition
Interrupt Enable
R/W
Change of Loss of Frame (LOF) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of LOF Condition” interrupt. If the user enables this interrupt, then
the XRT94L33 device will generate an interrupt in response to either of the
following conditions.
• When the Receive STS-1 TOH Processor block declares the “LOF”
condition.
• When the Receive STS-1 TOH Processor block clears the “LOF”
condition.
0 – Disables the “Change of LOF Condition Interrupt.
1 – Enables the “Change of LOF Condition” Interrupt.
1
Change of SEF
Condition
Interrupt Enable
R/W
Change of SEF Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of SEF Condition” Interrupt. If the user enables this interrupt,
then the XRT94L33 device will generate an interrupt in response to either
of the following conditions.
• When the Receive STS-1 TOH Processor block declares the “SEF”
condition.
• When the Receive STS-1 TOH Processor block clears the “SEF”
condition.
0 – Disables the “ Change of SEF Condition Interrupt”.
1 – Enables the “Change of SEF Condition Interrupt”.
0
Change of LOS
Condition
Interrupt Enable
R/W
Change of Loss of Signal (LOS) Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of LOF Condition” interrupt. If the user enables this interrupt, then
the XRT94L33 device will generate an interrupt in response to either of the
following conditions.
• When the Receive STS-1 TOH Processor block declares the “LOF”
condition.
• When the Receive STS-1 TOH Processor block clears the “LOF”
condition.
0 – Disables the “Change of LOF Condition Interrupt.
1 – Enables the “Change of LOF Condition” Interrupt.
383
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 308: Receive STS-1 Transport – B1 Error Count Register – Byte 3 (Address Location= 0xN110)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B1_Error_Count[31:24]
RUR
DESCRIPTION
B1 Error Count – MSB:
This RESET-upon-READ register, along with “Receive Transport
– B1 Error Count Register – Bytes 2 through 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 TOH
Processor block detects a B1 byte error.
Note:
1. If the B1 Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of bits, within the B1 value that are in error
2. If the B1 Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B1 bytes.
Table 309: Receive STS-1 Transport – B1 Error Count Register – Byte 2 (Address Location= 0xN111)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B1_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
B1_Error_Count[23:16]
RUR
B1 Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Receive Transport
– B1 Error Count Register – Bytes 3, 1 and 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 TOH
Processor block detects a B1 byte error.
Note:
1. If the B1 Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of bits, within the B1 value that are in error.
2. If the B1 Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B1 bytes.
Table 310: Receive STS-1 Transport – B1 Error Count Register – Byte 1 (Address Location= 0xN112)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
384
BIT 2
BIT 1
BIT 0
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
B1_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B1_Error_Count[15:8]
RUR
DESCRIPTION
B1 Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Receive Transport
– B1 Error Count Register – Bytes 3, 2 and 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 TOH
Processor block detects a B1 byte error.
Note:
1. If the B1 Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of bits, within the B1 value that are in error
2. If the B1 Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B1 bytes.
Table 311: Receive STS-1 Transport – B1 Error Count Register – Byte 0 (Address Location= 0xN113)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
B1_Error_Count[7:0]
BIT NUMBER
NAME
TYPE
7-0
B1_Error_Count[7:0]
RUR
DESCRIPTION
B1 Error Count – LSB:
This RESET-upon-READ register, along with “Receive Transport
– B1 Error Count Register – Bytes 3 through 1; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 TOH
Processor block detects a B1 byte error.
Note:
1. If the B1 Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of bits, within the B1 value that are in error.
2. If the B1 Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B1 bytes.
385
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 312: Receive STS-1 Transport – B2 Error Count Register – Byte 3 (Address Location= 0xN114)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count[31:24]
RUR
DESCRIPTION
B2 Error Count – MSB:
This RESET-upon-READ register, along with “Receive STS-1
Transport – B2 Error Count Register – Bytes 2 through 0; function
as a 32 bit counter, which is incremented anytime the Receive
STS-1 TOH Processor block detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B2 bytes.
Table 313: Receive STS-1 Transport – B2 Error Count Register – Byte 2 (Address Location= 0xN115)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
B2_Error_Count[23:16]
RUR
B2 Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Receive Transport
– B2 Error Count Register – Bytes 3, 1 and 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 TOH
Processor block detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B2 bytes.
386
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 314: Receive STS-1 Transport – B2 Error Count Register – Byte 1 (Address Location= 0xN116)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count[15:8]
RUR
DESCRIPTION
B2 Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Receive Transport –
B2 Error Count Register – Bytes 3, 2 and 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 TOH
Processor block detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain erred B2 bytes.
Table 315: Receive STS-1 Transport – B2 Error Count Register – Byte 0 (Address Location= 0xN117)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B2_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B2_Error_Count[7:0]
RUR
DESCRIPTION
B2 Error Count – LSB:
This RESET-upon-READ register, along with “Receive Transport – B2
Error Count Register – Bytes 3 through 1; function as a 32 bit counter,
which is incremented anytime the Receive STS-1 TOH Processor block
detects a B2 byte error.
Note:
1. If the B2 Error Type is configured to be “bit errors”, then the Receive
STS-1 TOH Processor block will increment this 32 bit counter by the
number of bits, within the B2 value that are in error.
2. If the B2 Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit counter
by the number of frames that contain erred B2 bytes.
387
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 316: Receive STS-1 Transport – REI-L Error Count Register – Byte 3 (Address Location =
0xN118)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
REI_L_Error_Count[31:24]
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count[31:24]
RUR
DESCRIPTION
REI-L Error Count – MSB:
This RESET-upon-READ register, along with “Receive Transport –
REI-L Error Count Register – Bytes 2 through 0; function as a 32
bit counter, which is incremented anytime the Receive STS-1 TOH
Processor block detects a Line - Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the nibble-value within the REI-L field of the M0 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then
the Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-L
values.
Table 317: Receive STS-1 Transport – REI_L Error Count Register – Byte 2 (Address Location=
0xN119)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_L_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count[23:16]
RUR
DESCRIPTION
REI-L Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Receive Transport
– REI-L Error Count Register – Bytes 3, 1 and 0; function as a 32
bit counter, which is incremented anytime the Receive STS-1
TOH Processor block detects a Line – Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the nibble-value within the REI-L field of the M0 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then
the Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-L
values.
388
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 318: Receive STS-1 Transport – REI_L Error Count Register – Byte 1 (Address Location=
0xN11A)
BIT 7
BIT 6
BIT 5
BIT 4
RUR
RUR
RUR
RUR
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
RUR
RUR
RUR
RUR
0
0
0
0
REI_L_Error_Count[15:8]
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count[15:8]
RUR
DESCRIPTION
REI-L Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Receive Transport –
REI-L Error Count Register – Bytes 3, 2 and 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 TOH
Processor block detects a Line –Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the nibble-value within the REI-L field of the M0 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-L
values.
Table 319: Receive STS-1 Transport – REI_L Error Count Register – Byte 0 (Address Location=
0xN11B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_L_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_L_Error_Count[7:0]
RUR
DESCRIPTION
REI-L Error Count – LSB:
This RESET-upon-READ register, along with “Receive Transport –
REI-L Error Count Register – Bytes 3 through 1; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 TOH
Processor block detects a Line – Remote Error Indicator.
Note:
1. If the REI-L Error Type is configured to be “bit errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the nibble-value within the REI-L field of the M0 byte.
2. If the REI-L Error Type is configured to be “frame errors”, then the
Receive STS-1 TOH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-L values.
389
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 320: Receive STS-1 Transport – Received K1 Byte Value (Address Location= 0xN11F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Filtered_K1_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Filtered_K1_Value[7:0]
R/O
DESCRIPTION
Filtered/Accepted K1 Value:
These READ-ONLY bit-fields contain the value of the most recently
“filtered” K1 value, that the Receive STS-1 TOH Processor block has
received. These bit-fields are valid if the K1/K2 pair (to which it
belongs) has been received for 3 consecutive STS-1 frames.
This register should be polled by Software in order to determine
various APS codes.
Table 321: Receive STS-1Transport – Received K2 Byte Value (Address Location= 0xN123)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Filtered_K2_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Filtered_K2_Value[7:0]
R/O
DESCRIPTION
Filtered/Accepted K2 Value:
These READ-ONLY bit-fields contain the value of the most recently
“filtered” K2 value, that the Receive STS-1 TOH Processor block has
received. These bit-fields are valid if the K1/K2 pair (to which it
belongs) has been received for 3 consecutive STS-1 frames.
This register should be polled by Software in order to determine
various APS codes.
390
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 322: Receive STS-1 Transport – Received S1 Byte Value (Address Location= 0xN127)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Filtered_S1_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Filtered_S1_Value[7:0]
R/O
DESCRIPTION
Filtered/Accepted S1 Value:
These READ-ONLY bit-fields contain the value of the most recently
“filtered” S1 value that the Receive STS-1 TOH Processor block has
received. These bit-fields are valid if it has been received for 8
consecutive STS-1 frames.
Table 323: Receive STS-1 Transport – LOS Threshold Value - MSB (Address Location= 0xN12E)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
LOS_THRESHOLD[15:8]
BIT NUMBER
NAME
TYPE
7-0
LOS_THRESHOLD[15:8]
R/W
DESCRIPTION
LOS Threshold Value – MSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – LOS Threshold Value – LSB” register
specify the number of consecutive (All Zero) bytes that the
Receive STS-1 TOH Processor block must detect before it
can declare an LOS condition.
391
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 324: Receive STS-1 Transport – LOS Threshold Value - LSB (Address Location= 0xN12F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOS_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
LOS_THRESHOLD[7:0]
R/W
DESCRIPTION
LOS Threshold Value – LSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1Transport – LOS Threshold Value – MSB” register
specify the number of consecutive (All Zero) bytes that the
Receive STS-1 TOH Processor block must detect before it
can declare an LOS condition.
Table 325: Receive STS-1 Transport – Receive SF SET Monitor Interval – Byte 2 (Address Location=
0xN131 )
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_MONITOR_WINDOW[23:16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_SET_MONITOR_WINDOW[23:1
6]
R/W
DESCRIPTION
SF_SET_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SF SET Monitor Interval –
Byte 1 and Byte 0” registers permit the user to specify
the number of STS-1 Frame periods that will constitute
a SET Sub-Interval for SF (Signal Failure).
When the Receive STS-1 TOH Processor block is
checking for SF, it will accumulate B2 errors for a total
of 8 SET Sub-Interval periods. If the number of
accumulated B2 errors exceeds that of programmed
into the “Receive Transport SF SET Threshold” register,
then an SF condition will be declared.
392
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 326: Receive STS-1 Transport – Receive SF SET Monitor Interval – Byte 1 (Address Location=
0xN132)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_SET_MONITOR_WINDOW[15:8]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
SF_SET_MONITOR_WINDOW[15:8]
R/W
SF_SET_MONITOR_INTERVAL (Bits 15 through 8):
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SF SET Monitor Interval –
Byte 2 and Byte 0” registers permit the user to specify
the number of STS-1 Frame periods that will constitute
a SET Sub-Interval for SF (Signal Failure).
When the Receive STS-1 TOH Processor block is
checking for SF, it will accumulate B2 bit errors for a
total of 8 SET Sub-Interval periods. If the number of
accumulated B2 bit errors exceeds that of
programmed into the “Receive STS-1 Transport SF
SET Threshold” register, then an SF condition will be
declared.
Table 327: Receive STS-1 Transport – Receive SF SET Monitor Interval – Byte 0 (Address Location=
0xN133)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_MONITOR_WINDOW[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_SET_MONITOR_WINDOW[7:0
]
R/W
DESCRIPTION
SF_SET_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SF SET Monitor Interval –
Byte 2 and Byte 1” registers permit the user to specify the
number of STS-1 Frame periods that will constitute a SET
Sub-Interval for SF (Signal Failure).
When the Receive STS-1 TOH Processor block is
checking for SF, it will accumulate B2 bit errors for a total
of 8 SET Sub-Interval periods.
If the number of
accumulated B2 bit errors exceeds that of programmed
into the “Receive STS-1 Transport SF SET Threshold”
register, then an SF condition will be declared.
393
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 328: Receive STS-1 Transport – Receive SF SET Threshold – Byte 1 (Address Location=
0xN136)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_SET_THRESHOLD[15:8]
R/W
DESCRIPTION
SF_SET_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SF SET Threshold – Byte 0” registers permit
the user to specify the number of B2 bit errors that will cause
the Receive STS-1 TOH Processor block to declare an SF
(Signal Failure) condition.
When the Receive STS-1 TOH Processor block is checking for
SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval
periods. If the number of accumulated B2 errors exceeds that
of programmed into this and the “Receive STS-1 Transport SF
SET Threshold – Byte 0” register, then an SF condition will be
declared.
Table 329: Receive STS-1 Transport – Receive SF SET Threshold – Byte 0 (Address Location=
0xN137)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_SET_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_SET_THRESHOLD[7:0]
R/W
DESCRIPTION
SF_SET_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SF SET Threshold – Byte 1” registers permit
the user to specify the number of B2 bit errors that will cause
the Receive STS-1 TOH Processor block to declare an SF
(Signal Failure) condition.
When the Receive STS-1 TOH Processor block is checking for
SF, it will accumulate B2 errors for a total of 8 SET Sub-Interval
periods. If the number of accumulated B2 errors exceeds that
of programmed into this and the “Receive STS-1 Transport SF
SET Threshold – Byte 1” register, then an SF condition will be
declared.
394
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 330: Receive STS-1 Transport – Receive SF CLEAR Threshold – Byte 1 (Address Location=
0xN13A)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_CLEAR_THRESHOLD[15:8]
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_THRESHOLD
[15:8]
R/W
DESCRIPTION
SF_CLEAR_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SF CLEAR Threshold – Byte 0” registers
permit the user to specify the upper limit for the number of B2 bit
errors that will cause the Receive STS-1 TOH Processor block to
clear the SF (Signal Failure) condition.
When the Receive STS-1 TOH Processor block is checking for
clearing SF, it will accumulate B2 errors for a total of 8 CLEAR
Sub-Interval periods. If the number of accumulated B2 errors is
less than that programmed into this and the “Receive STS-1
Transport SF CLEAR Threshold – Byte 0” register, then an SF
condition will be cleared.
Table 331: Receive STS-1 Transport – Receive SF CLEAR Threshold – Byte 0 (Address Location=
0xN13B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_CLEAR_THRESHOLD[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_THRESHOLD
[7:0]
R/W
DESCRIPTION
SF_CLEAR_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SF CLEAR Threshold – Byte 1” registers
permit the user to specify the upper limit for the number of B2 bit
errors that will cause the Receive STS-1 TOH Processor block to
clear the SF (Signal Failure) condition.
When the Receive STS-1 TOH Processor block is checking for
clearing SF, it will accumulate B2 errors for a total of 8 CLEAR
Sub-Interval periods. If the number of accumulated B2 errors is
less than that programmed into this and the “Receive STS-1
Transport SF CLEAR Threshold – Byte 1” register, then an SF
condition will be cleared.
395
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 332: Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte 2 (Address Location=
0xN13D)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
SD_SET_MONITOR_WINDOW[23:16]
BIT NUMBER
NAME
TYPE
7-0
SD_SET_MONITOR_WINDOW
[23:16]
R/W
DESCRIPTION
SF_SET_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SF SET Monitor Interval – Byte 1 and Byte
0” registers permit the user to specify the number of STS-1
Frame periods that will constitute a SET Sub-Interval for SD
(Signal Degrade) declaration.
When the Receive STS-1 TOH Processor block is checking for
SD, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors
exceeds that of programmed into the “Receive STS-1
Transport SD SET Threshold” register, then an SD condition
will be declared.
Table 333: Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte 1 (Address Location=
0xN13E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_SET_MONITOR_WINDOW[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
SD_SET_MONITOR_WINDOW
[15:8]
R/W
DESCRIPTION
SD_SET_MONITOR_INTERVAL – Bits 15 through 8:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SD SET Monitor Interval – Byte 2 and Byte
0” registers permit the user to specify the number of STS-1
Frame periods that will constitute a SET Sub-Interval for SD
(Signal Degrade) declaration.
When the Receive STS-1 TOH Processor block is checking for
SD, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors
exceeds that of programmed into the “Receive STS-1
Transport SD SET Threshold” register, then an SD condition
will be declared.
396
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 334: Receive STS-1 Transport – Receive SD Set Monitor Interval – Byte 0 (Address Location=
0xN13F)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
SD_SET_MONITOR_WINDOW[7:0]
BIT NUMBER
NAME
TYPE
7-0
SD_SET_MONITOR_WINDOW
[7:0]
R/W
DESCRIPTION
SD_SET_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SD SET Monitor Interval – Byte 2 and Byte
1” registers permit the user to specify the number of STS-1
Frame periods that will constitute a SET Sub-Interval for SD
(Signal Degrade) declaration.
When the Receive STS-1 TOH Processor block is checking for
SD, it will accumulate B2 bit errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 bit errors
exceeds that of programmed into the “Receive STS-1
Transport SD SET Threshold” register, then an SD condition
will be declared.
Table 335: Receive STS-1 Transport – Receive SD SET Threshold – Byte 1 (Address Location=
0xN142)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_SET_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_SET_THRESHOLD[15:8]
R/W
DESCRIPTION
SD_SET_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SD SET Threshold – Byte 0” registers
permit the user to specify the number of B2 bit errors that will
cause the Receive STS-1 TOH Processor block to declare an
SD (Signal Degrade) condition.
When the Receive STS-1 TOH Processor block is checking for
SD, it will accumulate B2 errors for a total of 8 SET SubInterval periods. If the number of accumulated B2 errors
exceeds that of programmed into this and the “Receive STS-1
Transport SD SET Threshold – Byte 0” register, then an SD
condition will be declared.
397
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 336: Receive STS-1 Transport – Receive SD SET Threshold – Byte 0 (Address Location=
0xN143)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SD_SET_THRESHOLD[7:0]
BIT NUMBER
NAME
TYPE
7-0
SD_SET_THRESHOLD[7:0]
R/W
DESCRIPTION
SD_SET_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SD SET Threshold – Byte 1” registers permit
the user to specify the number of B2 bit errors that will cause the
Receive STS-1 TOH Processor block to declare an SD (Signal
Degrade) condition.
When the Receive STS-1 TOH Processor block is checking for
SD, it will accumulate B2 errors for a total of 8 SET Sub-Interval
periods. If the number of accumulated B2 errors exceeds that of
programmed into this and the “Receive STS-1 Transport SD SET
Threshold – Byte 1” register, then an SD condition will be
declared.
Table 337: Receive STS-1 Transport – Receive SD CLEAR Threshold – Byte 1 (Address Location=
0xN146)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_THRESHOLD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_THRESHOLD
[15:8]
R/W
DESCRIPTION
SD_CLEAR_THRESHOLD – MSB:
These READ/WRITE bits, along the contents of the “Receive
STS-1 Transport – SD CLEAR Threshold – Byte 0” registers
permit the user to specify the upper limit for the number of B2 bit
errors that will cause the Receive STS-1 TOH Processor block to
clear the SD (Signal Degrade) condition.
When the Receive STS-1 TOH Processor block is checking for
clearing SD, it will accumulate B2 errors for a total of 8 CLEAR
Sub-Interval periods. If the number of accumulated B2 errors is
less than that programmed into this and the “Receive STS-1
Transport SD CLEAR Threshold – Byte 0” register, then an SD
condition will be cleared.
398
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 338: Receive STS-1 Transport – Receive SD CLEAR Threshold – Byte 1 (Address Location=
0xN147)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SD_CLEAR_THRESHOLD[7:0]
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_THRESHOLD[7:0]
R/W
DESCRIPTION
SD_CLEAR_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SD CLEAR Threshold – Byte 1”
registers permit the user to specify the upper limit for the
number of B2 bit errors that will cause the Receive STS-1
TOH Processor block to clear the SD (Signal Degrade)
condition.
When the Receive STS-1 TOH Processor block is checking
for clearing SD, it will accumulate B2 errors for a total of 8
CLEAR Sub-Interval periods. If the number of accumulated
B2 errors is less than that programmed into this and the
“Receive STS-1 Transport SD CLEAR Threshold – Byte 1”
register, then an SD condition will be cleared.
Table 339: Receive STS-1 Transport – Force SEF Condition Register (Address Location= 0xN14B)
BIT 7
BIT 6
BIT 5
R/O
R/O
R/O
0
0
0
BIT 4
BIT 3
BIT 2
BIT 1
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
Unused
BIT NUMBER
NAME
TYPE
7–1
Unused
R/O
0
SEF FORCE
R/W
BIT 0
SEF FORCE
DESCRIPTION
SEF Force:
This READ/WRITE bit-field permits the user to force the Receive STS-1
TOH Processor block (within Channel N) to declare an SEF defect. The
Receive STS-1 TOH Processor block will then attempt to reacquire framing.
Writing a “1” into this bit-field configures the Receive STS-1 TOH Processor
block to declare the SEF defect. The Receive STS-1 TOH Processor block
will automatically set this bit-field to “0” once it has reacquired framing (e.g.,
has detected two consecutive STS-1 frames with the correct A1 and A2
bytes).
399
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 340: Receive STS-1 Transport – Receive J0 Trace Buffer Control Register (Address Location=
0xN14F)
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
BIT 2
READ
SEL
ACCEPT
THRD
MSG
TYPE
BIT 1
BIT 0
MSG LENGTH
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–5
Unused
R/O
4
READ SEL
R/W
DESCRIPTION
J0 Buffer Read Selection:
This READ/WRITE bit-field permits a user to specify which of the following
buffer segments to read.
a.
Valid Message Buffer
b.
Expected Message Buffer
0 – Executing a READ to the Receive J0 Trace Buffer, will return contents
within the “Valid Message” buffer.
1 – Executing a READ to the Receive J0 Trace Buffer, will return contents
within the “Expected Message Buffer”.
Note:
3
ACCEPT THRD
R/W
In the case of the Receive STS-3 TOH Processor block, the “Receive
J0 Trace Buffer” is located at Address Location 0xN300 through
0xN33F.
Message Accept Threshold:
This READ/WRITE bit-field permits a user to select the number of consecutive
times that the Receive STS-1 TOH Processor block must receive a given J0
Trace Message, before it is accepted, as described below.
0 – The Receive STS-1 TOH Processor block accepts the J0 Message after it
has received it the third time in succession.
1 – The Receive STS-1 TOH Processor block accepts the J0 Message after it
has received in the fifth time in succession.
2
MSG TYPE
R/W
Message Alignment Type:
This READ/WRITE bit-field permits a user to specify have the Receive STS-1
TOH Processor block will locate the boundary of the J0 Trace Message, as
indicated below.
0 – Message boundary is indicated by “Line Feed”.
1 – Message boundary is indicated by the presence of a “1” in the MSB of the
first byte (within the J0 Trace Message).
1-0
MSG LENGTH
R/W
J0 Message Length:
These READ/WRITE bit-fields permit the user to specify the length of the J0
Trace Message, that the Receive STS-1 TOH Processor block will receive.
The relationship between the content of these bit-fields and the corresponding
J0 Trace Message Length is presented below.
MSG LENGTH
Resulting J0 Trace Message Length
400
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
00
1 Byte
01
16 Bytes
10/11
64 Bytes
Table 341: Receive STS-1 Transport – Receive SD Burst Error Tolerance – Byte 1 (Address Location=
0xN152)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_BURST_TOLERANCE[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_BURST_TOLERANCE
[15:8]
R/W
DESCRIPTION
SD_BURST_TOLERANCE – MSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-1 Transport – SD BURST Tolerance – Byte 0”
registers permit the user to specify the maximum number of B2
bit errors that the corresponding Receive STS-1 TOH Processor
block can accumulate during a single Sub-Interval period (e.g.,
an STS-1 frame period), when determining whether or not to
declare an SD (Signal Degrade) defect condition.
Note:
401
The purpose of this feature is to permit the user to
provide some level of B2 error burst filtering, when the
Receive STS-1 TOH Processor block is accumulating
B2 byte errors in order to declare the SD defect
condition. The user can implement this feature in
order to configure the Receive STS-1 TOH Processor
block to detect B2 bit errors in multiple “Sub-Interval”
periods before it will declare the SD defect condition.
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 342: Receive STS-1 Transport – Receive SD Burst Error Tolerance – Byte 0 (Address Location=
0xN153)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SD_BURST_TOLERANCE[7:0]
BIT NUMBER
NAME
TYPE
7-0
SD_BURST_TOLERANCE[7:0]
R/W
DESCRIPTION
SD_BURST_TOLERANCE – LSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-1 Transport – SD BURST Tolerance – Byte 1”
registers permit the user to specify the maximum number of
B2 bit errors that the corresponding Receive STS-1 TOH
Processor block can accumulate during a single Sub-Interval
period (e.g., an STS-1 frame period), when determining
whether or not to declare an SD (Signal Degrade) condition.
Note:
402
The purpose of this feature is to permit the user to
provide some level of B2 error burst filtering, when
the Receive STS-1 TOH Processor block is
accumulating B2 byte errors in order to declare the
SD defect condition. The user can implement this
feature in order to configure the Receive STS-1
TOH Processor block to detect B2 bit errors in
multiple “Sub-Interval” periods before it will declare
the SD defect condition.
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 343: Receive STS-1 Transport – Receive SF Burst Error Tolerance – Byte 1 (Address Location=
0xN156)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_BURST_TOLERANCE[15:8]
BIT NUMBER
NAME
TYPE
7-0
SF_BURST_TOLERANCE[15:8]
R/W
DESCRIPTION
SF_BURST_TOLERANCE – MSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-1 Transport – SF BURST Tolerance – Byte 0”
registers permit the user to specify the maximum number of
B2 bit errors that the corresponding Receive STS-1 TOH
Processor block can accumulate during a single Sub-Interval
period (e.g., an STS-1 frame period), when determining
whether or not to declare an SF (Signal Failure) condition.
Note:
403
The purpose of this feature is to permit the user to
provide some level of B2 error burst filtering, when
the Receive STS-1 TOH Processor block is
accumulating B2 byte errors in order to declare the
SF defect condition. The user can implement this
feature in order to configure the Receive STS-1
TOH Processor block to detect B2 bit errors in
multiple “Sub-Interval” periods before it will declare
the SF defect condition.
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 344: Receive STS-1 Transport – Receive SF Burst Error Tolerance – Byte 0 (Address Location=
0xN157)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_BURST_TOLERANCE[7:0]
BIT NUMBER
NAME
TYPE
7-0
SF_BURST_TOLERANCE[7:0]
R/W
DESCRIPTION
SF_BURST_TOLERANCE – LSB:
These READ/WRITE bits, along with the contents of the
“Receive STS-1 Transport – SF BURST Tolerance – Byte 1”
registers permit the user to specify the maximum number of
B2 bit errors that the corresponding Receive STS-1 TOH
Processor block can accumulate during a single Sub-Interval
period (e.g., an STS-1 frame period), when determining
whether or not to declare an SF (Signal Failure) condition.
Note:
The purpose of this feature is to permit the user to provide
some level of B2 error burst filtering, when the Receive STS-1
TOH Processor block is accumulating B2 byte errors in order
to declare the SF defect condition. The user can implement
this feature in order to configure the Receive STS-1 TOH
Processor block to detect B2 bit errors in multiple “SubInterval” periods before it will declare the SF defect condition.
Table 345: Receive STS-1 Transport – Receive SD Clear Monitor Interval – Byte 2 (Address Location=
0xN159)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
1
1
1
SD_CLEAR_MONITOR_WINDOW[23:16]
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_MONITOR_WINDOW
[23:16]
R/W
DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SD Clear Monitor Interval –
Byte 1 and Byte 0” registers permit the user to specify the
number of STS-1 Frame periods that will constitute a
CLEAR Sub-Interval for SD (Signal Degrade).
When the Receive STS-1 TOH Processor block is
checking for clearing the SD defect, it will accumulate B2
errors for a total of 8 SET Sub-Interval periods. If the
number of accumulated B2 errors is less than that of
programmed into the “Receive STS-1 Transport SD Clear
Threshold” register, then the SD defect will be cleared.
404
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 346: Receive STS-1 Transport – Receive SD Clear Monitor Interval – Byte 1 (Address Location=
0xN15A)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SD_CLEAR_MONITOR_WINDOW[15:8]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
SD_CLEAR_MONITOR_WINDOW
[15:8]
R/W
SD_CLEAR_MONITOR_INTERVAL – Bits 15 through
8:
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SD Clear Monitor Interval –
Byte 2 and Byte 0” registers permit the user to specify
the number of STS-1 Frame periods that will constitute a
CLEAR Sub-Interval for SD (Signal Degrade).
When the Receive STS-1 TOH Processor block is
checking for clearing the SD defect, it will accumulate B2
errors for a total of 8 SET Sub-Interval periods. If the
number of accumulated B2 errors is less than that of
programmed into the “Receive STS-1 Transport SD
Clear Threshold” register, then the SD defect will be
cleared.
Table 347: Receive STS-1 Transport – Receive SD Clear Monitor Interval – Byte 0 (Address Location=
0xN15B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD_CLEAR_MONITOR_WINDOW[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
SD_CLEAR_MONITOR_WINDOW
[7:0]
R/W
DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SD Clear Monitor Interval –
Byte 2 and Byte 1” registers permit the user to specify the
number of STS-1 Frame periods that will constitute a
CLEAR Sub-Interval for SD (Signal Degrade).
When the Receive STS-1 TOH Processor block is checking
for clearing the SD defect, it will accumulate B2 errors for a
total of 8 SET Sub-Interval periods. If the number of
accumulated B2 errors is less than that of programmed into
the “Receive STS-1 Transport SD Clear Threshold” register,
then the SD defect will be cleared.
405
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 348: Receive STS-1 Transport – Receive SF Clear Monitor Interval – Byte 2 (Address Location=
0xN15D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
1
1
1
SF_CLEAR_MONITOR_WINDOW[23:16]
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_MONITOR_WINDOW
[23:16]
R/W
DESCRIPTION
SF_CLEAR_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SF Clear Monitor Interval –
Byte 1 and Byte 0” registers permit the user to specify the
number of STS-1 Frame periods that will constitute a
CLEAR Sub-Interval for SF (Signal Failure).
When the Receive STS-1 TOH Processor block is checking
for clearing the SF defect, it will accumulate B2 errors for a
total of 8 SET Sub-Interval periods. If the number of
accumulated B2 errors is less than that of programmed into
the “Receive STS-1 Transport SF Clear Threshold”
register, then the SF defect will be cleared.
Table 349: Receive STS-1 Transport – Receive SF Clear Monitor Interval – Byte 1 (Address Location=
0xN15E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SF_CLEAR_MONITOR_WINDOW[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
SF_CLEAR_MONITOR_WINDOW
[15:8]
R/W
SF_CLEAR_MONITOR_INTERVAL – Bits 15 through
8:
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SF Clear Monitor Interval –
Byte 2 and Byte 0” registers permit the user to specify the
number of STS-1 Frame periods that will constitute a
CLEAR Sub-Interval for SF (Signal Failure).
When the Receive STS-1 TOH Processor block is
checking for clearing the SF defect, it will accumulate B2
errors for a total of 8 SET Sub-Interval periods. If the
number of accumulated B2 errors is less than that of
programmed into the “Receive STS-1 Transport SF Clear
Threshold” register, then the SF defect will be cleared.
406
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 350: Receive STS-1 Transport – Receive SF Clear Monitor Interval – Byte 0 (Address Location=
0xN15F)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
1
1
1
1
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
1
1
1
1
SF_CLEAR_MONITOR_WINDOW[7:0]
BIT NUMBER
NAME
TYPE
7-0
SF_CLEAR_MONITOR_WINDOW
[7:0]
R/W
DESCRIPTION
SF_CLEAR_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Receive STS-1 Transport – SF Clear Monitor Interval –
Byte 2 and Byte 1” registers permit the user to specify the
number of STS-1 Frame periods that will constitute a
CLEAR Sub-Interval for SF (Signal Failure).
When the Receive STS-1 TOH Processor block is
checking for clearing the SF defect, it will accumulate B2
errors for a total of 8 SET Sub-Interval periods. If the
number of accumulated B2 errors is less than that of
programmed into the “Receive STS-1 Transport SF Clear
Threshold” register, then the SF defect will be cleared.
407
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 351: Receive STS-1 Transport – Auto AIS Control Register (Address Location= 0xN163)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit
AIS-P
(Downstream)
upon J0
Message
Unstable
Transmit
AIS-P
(Downstream)
Upon
Section
Trace
Message
Mismatch
Transmit
AIS-P
(Downstream)
upon SF
Transmit
AIS-P
(Downstream)
upon SD
Unused
Transmit
AIS-P
(Downstream)
upon LOF
Transmit
AIS-P
(Downstream)
upon LOS
Transmit
AIS-P
(Downstream)
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7
Transmit AIS-P (Downstream) upon J0
Message Unstable
R/W
Transmit Path AIS upon Detection of Unstable Section Trace
(J0):
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Receive STS-1 POH Processor blocks), anytime it detects an
Unstable Section Trace (J0) condition in the “incoming” STS-1 datastream.
0 – Does not configure the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator (via the “downstream”
traffic) whenever it detects an “Unstable Section Trace” condition.
1 – Configures the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator (via the “downstream”
traffic) whenever it detects an “Unstable Section Trace” condition.
Note:
6
Transmit AIS-P (Downstream) Upon J0
Message Mismatch
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS (AIS-P) upon Detection of Section Trace (J0)
Mismatch:
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Receive STS-1 POH Processor blocks), anytime it detects a Section
Trace (J0) Mismatch condition in the “incoming” STS-1 data stream.
0 – Does not configure the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator (via the “downstream”
traffic) whenever it detects a “Section Trace Mismatch” condition.
1 – Configures the Receive STS-1 TOH Processor block to transmit
the AIS-P indicator (via the “downstream” traffic) whenever it detects
a “Section Trace Mismatch” condition.
Note:
5
Transmit AIS-P (Downstream) upon SF
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS upon Signal Failure (SF):
This READ/WRITE bit-field permits the user to configure the Receive
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STS-1 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Receive STS-1 POH Processor block), anytime it declares an SF
condition.
0 – Does not configure the Receive STS-1 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the SF defect.
1 – Configures the Receive STS-1 TOH Processor block to transmit
the AIS-P indicator (via the “downstream” traffic) upon declaration of
the SF detect.
Note:
4
Transmit AIS-P (Downstream) upon SD
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS upon Signal Degrade (SD):
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Receive STS-1 POH Processor block) anytime it declares an SD
condition.
0 – Does not configure the Receive STS-1 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the SD defect.
1 – Configures the Receive STS-1 TOH Processor block to transmit
the AIS-P indicator (via the “downstream” traffic) upon declaration of
the SD defect.
Note:
3
Unused
R/O
2
Transmit AIS-P (Downstream) upon LOF
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS upon Loss of Frame (LOF):
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Receive STS-1 POH Processor block), anytime it declares an LOF
condition.
0 – Does not configure the Receive STS-1 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the LOF defect.
1 – Configures the Receive STS-1 TOH Processor block to transmit
the AIS-P indicator (via the “downstream” traffic) upon declaration of
the LOF defect.
Note:
1
Transmit AIS-P (Downstream) upon LOS
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS upon Loss of Signal (LOS):
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 TOH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Receive STS-1 POH Processor block), anytime it declares an LOS
condition.
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0 – Does not configure the Receive STS-1 TOH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) anytime it
declares the LOS defect.
1 – Configures the Receive STS-1 TOH Processor block to transmit
the AIS-P indicator (via the “downstream” traffic) anytime it declares
the LOS defect.
Note:
0
AUTO AIS
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Automatic Transmission of AIS-P Enable:
This READ/WRITE bit-field serves two purposes.
It permits the user to configure the Receive STS-1 TOH Processor
block to automatically transmit the Path AIS (AIS-P) indicator, via the
down-stream traffic (e.g., towards the Receive STS-1 POH Processor
block), upon detection of an SF, SD, Section Trace Mismatch,
Section Trace Unstability, LOF or LOS conditions.
It also permits the user to configure the Receive STS-1 TOH
Processor block to automatically transmit a Path AIS (AIS-P)
Indicator via the “downstream” traffic (e.g., towards the Receive STS1 POH Processor block) anytime it detects an AIS-L condition in the
“incoming” STS-1 datastream.
0 – Configures the Receive STS-1 TOH Processor block to NOT
automatically transmit the AIS-P indicator (via the “downstream”
traffic) upon detection of the AIS-L or any of the “above-mentioned”
conditions.
1 – Configures the Receive STS-1 TOH Processor block to
automatically transmit the AIS-P indicator (via the “downstream”
traffic) upon detection of the AIS-L or any of the “above-mentioned”
condition.
Note:
The user must also set the corresponding bit-fields (within
this register) to “1” in order to configure the Receive STS-1
TOH Processor block to automatically transmit the AIS-P
indicator upon detection of a given alarm/defect condition.
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Table 352: Receive STS-1 Transport – Auto AIS (in Downstream STS-1s) Control Register (Address
Location= 0xN16B)
BIT 7
BIT 6
Unused
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit AISP (via
Downstream
STS-1s) upon
LOS
Transmit AISP (via
Downstream
STS-1s) upon
LOF
Transmit AISP (via
Downstream
STS-1s) upon
SD
Transmit AISP (via
Downstream
STS-1s) upon
SF
Unused
Transmit
AIS-P (via
Downstream
STS-1s)
Enable
R/O
R/O
R/W
R/W
R/W
R/W
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-6
Unused
R/O
5
Transmit AIS-P (via
Downstream STS-1s)
upon LOS
R/W
DESCRIPTION
Transmit AIS-P (via Downstream STS-1s) upon LOS (Loss of
Signal):
This READ/WRITE bit-field permits the user to configure the Transmit
SONET POH Processor block (in the corresponding channel) to
automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal), anytime
the Receive STS-1 TOH Processor block declares the LOS defect.
0 – Does not configure the corresponding Transmit SONET POH
Processor blocks to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal), anytime
the Receive STS-1 TOH Processor block declares the LOS defect.
1 – Configure the corresponding Transmit SONETPOH Processor
blocks to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signals (within the outbound STS-3 signal),
anytime the Receive STS-1 TOH Processor block declares the LOS
defect.
Note:
1. In the “long-run” the function of this bit-field is exactly the same as
that of Bit 1 (Transmit AIS-P Down-stream – Upon LOS), within the
Receive STS-1 Transport – Auto AIS Control Register (Address
Location= 0xN163). The only difference is that this register bit will
cause the corresponding “downstream” Transmit SONET POH
Processor block to IMMEDIATELY begin to transmit the AIS-P condition
whenever the Receive STS-1 TOH Processor block declares the LOS
defect. This will permit the user to easily comply with the Telcordia GR253-CORE requirements of an NE transmitting the AIS-P indicator
downstream within 125us of the NE declaring the LOS defect.
In the case of Bit 1 (Transmit AIS-P Downstream – Upon LOS), several
SONET frame periods are required (after the Receive STS-1 TOH
Processor block has declared the LOS defect), before the
corresponding Transmit SONET POH Processor block will begin the
process of transmitting the AIS-P indicator.
2. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
4
Transmit AIS-P (via
Downstream STS-1s)
upon LOF
R/W
Transmit AIS-P (via Downstream STS-1s) upon LOF (Loss of
Frame):
This READ/WRITE bit-field permits the user to configure the Transmit
SONET POH Processor block (in the corresponding channel) to
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automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal), anytime
the Receive STS-1 TOH Processor block declares the LOF defect.
0 – Does not configure the corresponding Transmit SONET POH
Processor block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signals (within the outbound STS-3 signal),
anytime the Receive STS-1 TOH Processor block declares the LOF
defect.
1 – Configures the corresponding Transmit SONET POH Processor
block to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signals (within the outbound STS-3 signal), anytime the Receive
STS-1 TOH Processor block declares the LOF defect.
Note:
1. In the “long-run” the function of this bit-field is exactly the same as
that of Bit 2 (Transmit AIS-P Down-stream – Upon LOF), within the
Receive STS-1 Transport – Auto AIS Control Register (Address
Location= 0xN163). The only difference is that this register bit will
cause the corresponding “downstream” Transmit SONET POH
Processor blocks to IMMEDIATELY begin to transmit the AIS-P
condition whenever the Receive STS-1 TOH Processor block declares
the LOF defect. This will permit the user to easily comply with the
Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P
indicator downstream within 125us of the NE declaring the LOF defect.
In the case of Bit 2 (Transmit AIS-P Downstream – Upon LOF), several
SONET frame periods are required (after the Receive STS-3 TOH
Processor block has declared the LOS defect), before the
corresponding Transmit SONET POH Processor block will begin the
process of transmitting the AIS-P indicator.
2. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
3
Transmit AIS-P (via
Downstream STS-1s)
upon SD
R/W
Transmit AIS-P (via Downstream STS-1s) upon SD (Signal
Degrade):
This READ/WRITE bit-field permits the user to configure the Transmit
SONET POH Processor block (in the corresponding channel) to
automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signals (within the outbound STS-3 signal),
anytime the Receive STS-1 TOH Processor block declares the SD
defect.
0 – Does not configures the corresponding Transmit SONET POH
Processor block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signals (within the outbound STS-3 signal),
anytime the Receive STS-1 TOH Processor block declares the SD
defect.
1 – Configures the corresponding Transmit SONET POH Processor
block to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signal (within the outbound STS-3 signal), anytime the Receive
STS-1 TOH Processor block declares the SD defect.
Note:
1. In the “long-run” the function of this bit-field is exactly the same as
that of Bit 4 (Transmit AIS-P Down-stream – Upon SD), within the
Receive STS-1 Transport – Auto AIS Control Register (Address
Location= 0xN163). The only difference is that this register bit will
cause the corresponding “downstream” Transmit SONET POH
Processor blocks to IMMEDIATELY begin to transmit the AIS-P
condition whenever the Receive STS-1 TOH Processor block declares
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the SD defect. This will permit the user to easily comply with the
Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P
indicator downstream within 125us of the NE declaring the LOS defect.
In the case of Bit 1 (Transmit AIS-P Downstream – Upon LOF), several
SONET frame periods are required (after the Receive STS-1 TOH
Processor block has declared the SD defect), before the corresponding
Transmit SONET POH Processor block will begin the process of
transmitting the AIS-P indicator.
2. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
2
Transmit AIS-P (via
Downstream STS-1s)
upon SF
R/W
Transmit AIS-P (via Downstream STS-1s) upon Signal Failure (SF):
This READ/WRITE bit-field permits the user to configure the Transmit
SONET POH Processor block (in the corresponding channel) to
automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal), anytime
the Receive STS-1 TOH Processor block declares an SF condition.
0 – Does not configures the corresponding Transmit SONET POH
Processor block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal), anytime
the Receive STS-1 TOH Processor block declares the SF defect.
1 – Configures the corresponding Transmit SONET POH Processor
block to automatically transmit the AIS-P Indicator via the “downstream”
STS-1 signal (within the outbound STS-3 signal), anytime the Receive
STS-1 TOH Processor block declares the SF defect.
Note:
In the “long-run” the function of this bit-field is exactly the same as
that of Bit 5 (Transmit AIS-P Down-stream – Upon SF), within the
Receive STS-1 Transport – Auto AIS Control Register (Address
Location= 0xN163). The only difference is that this register bit will
cause the corresponding “downstream” Transmit SONET POH
Processor blocks to IMMEDIATELY begin to transmit the AIS-P
condition whenever the Receive STS-1 TOH Processor block declares
the SF defect. This will permit the user to easily comply with the
Telcordia GR-253-CORE requirements of an NE transmitting the AIS-P
indicator downstream within 125us of the NE declaring the SF defect.
In the case of Bit 5 (Transmit AIS-P Downstream – Upon SF), several
SONET frame periods are required (after the Receive STS-1 TOH
Processor block has declared the SF defect), before the corresponding
Transmit SONET POH Processor blocks will begin the process of
transmitting the AIS-P indicator.
2. In addition to setting this bit-field to “1”, the user must also set Bit 0
(Transmit AIS-P via Downstream STS-1s Enable) within this register, in
order enable this feature.
1
Unused
R/O
0
Transmit AIS-P (via
Downstream STS-1s)
Enable
R/W
Automatic Transmission of AIS-P (via the downstream STS-1s)
Enable:
This READ/WRITE bit-field permits the user to configure the
corresponding Transmit SONET POH Processor block to automatically
transmit the AIS-P indicator, via its “outbound” STS-1 signal (within the
outbound STS-3 signal), upon detection of an SF, SD, LOS and LOF
condition via the Receive STS-1 TOH Processor block.
0 – Does not configure the corresponding Transmit SONET POH
Processor block to automatically transmit the AIS-P indicator, whenever
the Receive STS-1 TOH Processor block declares either the LOS, LOF,
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SD or the SF defects.
1 – Configures the corresponding Transmit SONET POH Processor
block to automatically transmit the AIS-P indicator, whenever the
Receive STS-1 TOH Processor block declares either the LOS, LOF, SD
or the SF defects.
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Table 353: Receive STS-1 Path – Control Register – Byte 2 (Address Location= 0xN183)
BIT 7
BIT 6
BIT 5
BIT 4
Unused
BIT 3
BIT 2
BIT 1
BIT 0
Check
Stuff
RDI-P
Type
REI-P
Error Type
B3 Error Type
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-4
Unused
R/O
3
Check Stuff
R/W
DESCRIPTION
Check (Pointer Adjustment) Stuff Select:
This READ/WRITE bit-field permits the user to enable/disable the SONET
standard recommendation that a pointer increment or decrement operation,
detected within 3 SONET frames of a previous pointer adjustment operation
(e.g., negative stuff, positive stuff) is ignored.
0 – Disables this SONET standard implementation. In this mode, all pointeradjustment operations that are detected will be accepted.
1 – Enables this “SONET standard” implementation. In this mode, all pointeradjustment operations that are detected within 3 SONET frame periods of a
previous pointer-adjustment operation, will be ignored.
2
RDI-P Type
R/W
Path - Remote Defect Indicator Type Select:
This READ/WRITE bit-field permits the user to configure the Receive STS-1
POH Processor block to support either the “Single-Bit” or the “Enhanced” RDIP, as described below.
0 – Configures the Receive STS-1 POH Processor block to support the
Single-Bit RDI-P. In this mode, the Receive STS-1 POH Processor block will
only monitor Bit 5, within the G1 byte (of the incoming SPE data), in order to
declare and clear the RDI-P indicator.
1 – Configures the Receive STS-1 POH Processor block to support the
Enhanced RDI-P (ERDI-P). In this mode, the Receive STS-1 POH Processor
block will monitor bits 5, 6 and 7, within the G1 byte, in order to declare and
clear the RDI-P indicator.
1
REI-P Error
Type
R/W
REI-P Error Type:
This READ/WRITE bit-field permits the user to specify how the “Receive Path
REI-P Error Count” register is incremented.
0 – Configures the Receive STS-1 POH Processor block to count REI-P Bit
Errors.
In this case, the “Receive Path REI-P Error Count” register will be
incremented by the value of the lower nibble within the G1 byte.
1 – Configures the Receive STS-1 POH Processor block to count REI-P
Frame Errors.
In this case, the “Receive Path REI-P Error Count” register will be
incremented by a single count each time the Receive STS-1 POH Processor
block receives a G1 byte, in which bits 1 through 4 are set to a “non-zero”
value.
0
B3 Error Type
R/W
B3 Error Type:
This READ/WRITE bit-field permits the user to specify how the “Receive Path
B3 Error Count” register is incremented.
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0 – Configures the Receive STS-1 POH Processor block to count B3 bit
errors. In this case, the “Receive Path B3 Error Count” register will be
incremented by the number of bits, within the B3 value, that is in error.
1 – Configures the Receive STS-1 POH Processor block to count B3 frame
errors. In this case, the “Receive Path B3 Error Count” register will be
incremented by the number of erred STS-1 frames.
416
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 354: Receive STS-1 Path – Control Register – Byte 1 (Address Location= 0xN186)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
J1
Unstable
Indicator
Unused
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–1
Unused
R/O
0
J1 Unstable
Indicator
R/O
DESCRIPTION
J1 – Path Trace Unstable Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH
Processor block is currently declaring the Path Trace Unstable condition. The
Receive STS-1 POH Processor block will declare a J1 (Path Trace) Unstable
condition, whenever the “J1 Unstable” counter reaches the value “8”. The “J0
Unstable” counter will be incremented for each time that it receives a J1
message that differs from the previously received message. The “J1 Unstable”
counter is cleared to “0” whenever the Receive STS-1 POH Processor block has
received a given J1 Message 3 (or 5) consecutive times.
Note:
Receiving a given J1 Message 3 (or 5) consecutive times also sets this
bit-field to “0”.
0 – Path Trace Instability condition is NOT declared.
1 – Path Trace Instability condition is currently declared.
417
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 355: Receive STS-1 Path – SONET Receive POH Status – Byte 0 (Address Location= 0xN187)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TIM-P
Defect
Declared
C2 Byte
Unstable
Condition
UNEQ-P
Defect
Declared
PLM-P
Defect
Declared
RDI-P
Defect
Declared
RDI-P
Unstable
Condition
LOP-P
Defect
Declared
AIS-P
Defect
Declared
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
TIM-P
Defect
Declared
R/O
DESCRIPTION
Trace Identification Mismatch (TIM-P) Defect Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH
Processor block is currently declaring the “Trace Identification Mismatch”
condition.
The Receive STS-1 POH Processor block will declare the “TIM-P” condition, when
none of the received 64 byte string (received via the J1 byte) matches the
expected 64 byte message.
The Receive STS-1 POH Processor block will clear the “TIM-P” condition, when
80% of the received 64 byte string (received via the J1 byte) matches the
expected 64 byte message.
0 – Indicates that the Receive STS-1 POH Processor block is NOT currently
declaring the TIM-P condition.
1 – Indicates that the Receive STS-1 POH Processor block is currently declaring
the TIM-P condition.
6
C2 Byte
Unstable
Condition
R/O
C2 Byte (Path Signal Label Byte) Unstable Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH
Processor block is currently declaring the “Path Signal Label Byte” Unstable
condition.
The Receive STS-1 POH Processor block will declare a C2 (Path Signal Label
Byte) Unstable condition, whenever the “C2 Unstable” counter reaches the value
“5”. The “C2 Unstable” counter will be incremented for each time that it receives
an SPE with a C2 byte value that differs from the previously received C2 byte
value. The “C2 Unstable” counter is cleared to “0” whenever the Receive STS-1
POH Processor block has received 3 (or 5) consecutive SPEs of the same C2
byte value.
Note:
Receiving a given C2 byte value in 3 (or 5) consecutive SPEs also sets
this bit-field to “0”.
0 – C2 (Path Signal Label Byte) Unstable condition is NOT declared.
1 – C2 (Path Signal Label Byte) Unstable condition is currently declared.
5
UNEQ-P
R/O
Path – Unequipped Indicator (UNEQ-P):
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH
Processor block is currently declaring the UNEQ-P condition.
The Receive STS-1 POH Processor block will declare a UNEQ-P condition, if it
receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set
to 0x00 (which indicates that the SPE is “Unequipped”).
The Receive STS-1 POH Processor block will clear the UNEQ-P condition, if it
receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set
to a value other than 0x00.
0 – Indicates that the Receive STS-1 POH Processor block is NOT declaring the
418
XRT94L33
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C
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A
N
N
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L
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E
S
T
S
T
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S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
UNEQ-P condition.
1 – Indicates that the Receive STS-1 POH Processor block is currently declaring
the UNEQ-P condition.
Note:
4
PLM-P
Defect
Declared
R/O
The Receive STS-1 POH Processor block will not declare the UNEQ-P
condition if it configured to expect to receive STS-1 frames with C2
bytes being set to “0x00” (e.g., if the “Receive STS-1 Path – Expected
Path Label Value” Register –Address Location= 0xN197) is set to
“0x00”.
Path Payload Mismatch Indicator (PLM-P):
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH
Processor block is currently declaring the PLM-P condition.
The Receive STS-1 POH Processor block will declare an PLM-P condition, if it
receives at least five (5) consecutive STS-1 frames, in which the C2 byte was set
to a value other than that which it is expecting to receive.
Whenever the Receive STS-1 POH Processor block is determine whether or not it
should declare the PLM-P defect, it checks the contents of the following two
registers.
• The “Receive STS-1 Path – Received Path Label Value” Register (Address
Location= 0xN196).
• The “Receive STS-1 Path – Expected Path Label Value” Register (Address
Location= 0xN197).
The “Receive STS-1 Path – Expected Path Label Value” Register contains the
value of the C2 bytes, that the Receive STS-1 POH Processor blocks expects to
receive.
The “Receive STS-1 Path – Received Path Label Value” Register contains the
value of the C2 byte, that the Receive STS-1 POH Processor block has most
received “validated” (by receiving this same C2 byte in five consecutive STS-1
frames).
The Receive STS-1 POH Processor block will declare a PLM-P condition, if the
contents of these two register do not match. The Receive STS-1 POH Processor
block will clear the PLM-P condition if whenever the contents of these two
registers do match.
0 – PLM-P defect is currently not being declared.
1 – PLM-P defect is currently being declared.
Note:
3
RDI-P
R/O
The Receive STS-1 POH Processor block will clear the PLM-P defect,
upon detecting the UNEQ-P condition.
Path Remote Defect Indicator (RDI-P):
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH
Processor block is currently declaring the RDI-P condition.
If the Receive STS-1 POH Processor block is configured to support the “Single-bit
RDI-P” function, then it will declare an RDI-P condition if Bit 5 (within the G1 byte
of the incoming STS-1 frame) is set to “1” for “RDI-P_THRD” number of
consecutive STS-1 frames.
If the Receive STS-1 POH Processor block is configured to support the Enhanced
RDI-P” (ERDI-P) function, then it will declare an RDI-P condition if Bits 5, 6 and 7
(within the G1 byte of the incoming STS-1 frame) are set to [0, 1, 0], [1, 0, 1] or [1,
1, 0] for “RDI-P_THRD” number of consecutive STS-1 frames.
0 – Indicates that the Receive STS-1 POH Processor block is NOT declaring an
RDI-P condition.
1 – Indicates that the Receive STS-1 POH Processor block is currently declaring
an RDI-P condition.
419
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Note:
2
RDI-P
Unstable
R/O
Rev222...000...000
The user can specify the value for “RDI-P_THRD” by writing the
appropriate data into Bits 3 through 0 (RDI-P THRD) within the “Receive
STS-1 Path – SONET Receive RDI-P Register (Address Location=
0xN193).
RDI-P (Path – Remote Defect Indicator) Unstable:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH
Processor block is currently declaring the “RDI-P Unstable” condition. The
Receive STS-1 POH Processor block will declare a “RDI-P I Unstable” condition
whenever the “RDI-P Unstable Counter” reaches the value “RDI-P THRD”. The
“RDI-P Unstable” counter is incremented for each time that the Receive STS-1
POH Processor block receives an RDI-P value that differs from that of the
previous STS-1 frame. The “RDI-P Unstable” counter is cleared to “0” whenever
the same RDI-P value is received in “RDI-P_THRD” consecutive STS-1 frames.
Note:
Receiving a given RDI-P value, in “RDI-P_THRD” consecutive STS-1
frames also clears this bit-field to “0”.
0 – RDI-P Unstable condition is NOT declared.
1 – RDI-P Unstable condition is currently declared.
Note:
1
LOP-P
Defect
Declared
R/O
The user can specify the value for “RDI-P_THRD” by writing the
appropriate data into Bits 3 through 0 (RDI-P THRD) within the “Receive
STS-1 Path – SONET Receive RDI-P Register (Address Location=
0xN193).
Loss of Pointer Indicator (LOP-P):
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH
Processor block is currently declaring the LOP (Loss of Pointer) condition.
The Receive STS-1 POH Processor block will declare the LOP-P condition, if it
cannot detect a valid pointer (H1 and H2 bytes, within the TOH) within 8 to 10
consecutive SONET frames. Further, the Receive STS-1 POH Processor block
will declare the LOP-P condition, if it detects 8 to 10 consecutive NDF events.
The Receive STS-1 POH Processor block will clear the LOP-P condition,
whenever the Receive STS-1 POH Processor detects valid pointer bytes (e.g., the
H1 and H2 bytes, within the TOH) and normal NDF value for three consecutive
STS-1 frames.
0 – Indicates that the Receive STS-1 POH Processor block is NOT declaring the
LOP-P condition.
1 – Indicates that the Receive STS-1 POH Processor block is currently declaring
the LOP-P condition.
0
AIS-P
R/O
Path AIS (AIS-P) Indicator:
This READ-ONLY bit-field indicates whether or not the Receive STS-1 POH
Processor block is currently declaring an AIS-P condition. The Receive STS-1
POH Processor block will declare an AIS-P if it detects all of the following
conditions for three consecutive STS-1 frames.
•
The H1, H2 and H3 bytes are set to an “All Ones” pattern.
•
The entire SPE is set to an “All Ones” pattern.
The Receive STS-1 POH Processor block will clear the AIS-P indicator when it
detects a valid STS-1 pointer (H1 and H2 bytes) and a “set” or “normal” NDF for
three consecutive STS-1 frames.
0 – Indicates that the Receive STS-1 POH Processor block is NOT currently
declaring the AIS-P condition.
1 – Indicates that the Receive STS-1 POH Processor block is currently declaring
the AIS-P condition.
Note:
The Receive STS-1 POH Processor block will NOT declare the LOP-P
420
XRT94L33
Rev222...000...000
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
condition if it detects an “All Ones” pattern in the H1, H2 and H3 bytes.
It will, instead, declare the AIS-P condition.
421
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 356: Receive STS-1 Path – SONET Receive Path Interrupt Status – Byte 2 (Address Location=
0xN189)
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Detection of
AIS Pointer
Interrupt
Status
Detection of
Pointer
Change
Interrupt
Status
Unused
Change in
TIM-P
Condition
Interrupt
Status
Change in J1
Unstable
Condition
Interrupt
Status
R/O
R/O
R/O
RUR
RUR
R/O
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–5
Unused
R/O
4
Detection of AIS Pointer
Interrupt Status
RUR
DESCRIPTION
Detection of AIS Pointer Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Detection of AIS Pointer” interrupt has occurred since the last
read of this register.
If this interrupt is enabled, then the Receive STS-1 POH
Processor block will generate this interrupt anytime it detects an
“AIS Pointer” in the incoming STS-1 data stream.
Note:
An “AIS Pointer” is defined as a condition in which both
the H1 and H2 bytes (within the TOH) are each set to
an “All Ones” pattern.
0 – Indicates that the “Detection of AIS Pointer” interrupt has
NOT occurred since the last read of this register.
1 – Indicates that the “Detection of AIS Pointer” interrupt has
occurred since the last read of this register.
3
Detection of Pointer Change
Interrupt Status
RUR
Detection of Pointer Change Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Detection of Pointer Change” Interrupt has occurred since the
last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH
Processor block will generate an interrupt anytime it accepts a
new pointer value (e.g., H1 and H2 bytes, in the TOH bytes).
0 – Indicates that the “Detection of Pointer Change” Interrupt has
NOT occurred since the last read of this register.
1 – Indicates that the “Detection of Pointer Change” Interrupt has
occurred since the last read of this register.
2
Unused
R/O
1
Change in TIM-P Condition
Interrupt Status
RUR
Change in TIM-P (Trace Identification Mismatch) Condition
Interrupt.
This RESET-upon-READ bit-field indicates whether or not the
“Change in TIM-P” Condition interrupt has occurred since the
last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH
Processor block will generate an interrupt in response to either of
the following events.
422
XRT94L33
Rev222...000...000
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
• If the TIM-P condition is declared.
• If the TIM-P condition is cleared.
0 – Indicates that the “Change in TIM-P Condition” Interrupt has
not occurred since the last read of this register.
1 – Indicates that the “Change in TIM-P Condition” Interrupt has
occurred since the last read of this register.
0
Change in J1 Unstable
Condition Interrupt Status
RUR
Change in “J1 (Trace Identification Message) Unstable
Condition” Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Change in J1 Unstable Condition” Interrupt has occurred since
the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH
Processor block will generate an interrupt in response to either of
the following events.
• When the Receive STS-1 POH Processor block declare the
“J1 Unstable” Condition.
• When the Receive STS-1 POH Processor block clears the “J1
Unstable” condition.
0 – Indicates that the “Change in J1 Unstable Condition”
Interrupt has NOT occurred since the last read of this register.
1 – Indicates that the “Change in J1 Unstable Condition”
Interrupt has occurred since the last read of this register.
423
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 357: Receive STS-1 Path – SONET Receive Path Interrupt Status – Byte 1 (Address Location=
0xN18A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New J1
Message
Interrupt
Status
Detection of
REI-P Event
Interrupt
Status
Change in
UNEQ-P
Condition
Interrupt
Status
Change in
PLM-P
Condition
Interrupt
Status
New C2
Byte
Interrupt
Status
Change in
C2 Byte
Unstable
Condition
Interrupt
Status
Change in
RDI-P
Unstable
Condition
Interrupt
Status
New
RDI-P Value
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
New J1
Message
Interrupt Status
RUR
DESCRIPTION
New J1 (Trace Identification) Message Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New J1
Message” Interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will
generate an interrupt anytime it has accepted (or validated) and new J1
(Trace Identification) Message.
0 – Indicates that the “New J1 Message” Interrupt has NOT occurred since
the last read of this register.
1 – Indicates that the “New J1 Message” Interrupt has occurred since the
last read of this register.
6
Detection of
REI-P Event
Interrupt Status
RUR
Detection of REI-P Event Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Detection of
REI-P Event” Interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will
generate an interrupt anytime it detects an REI-P condition in the coming
STS-1 data-stream.
0 – Indicates that the “Detection of REI-P Event” Interrupt has NOT occurred
since the last read of this register.
1 – Indicates that the “Detection of REI-P Event” Interrupt has occurred
since the last read of this register.
5
Change in
UNEQ-P
Condition
Interrupt Status
RUR
Change in UNEQ-P (Path – Unequipped) Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change in
UNEQ-P Condition” interrupt has occurred since the last read of this
register.
If this interrupt is enabled , then the Receive STS-1 POH Processor block
will generate an interrupt in response to either of the following conditions.
• When the Receive STS-1 POH Processor block declares the UNEQ-P
Condition.
• When the Receive STS-1 POH Processor block clears the UNEQ-P
Condition.
0 – Indicates that the “Change in UNEQ-P Condition” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Change in UNEQ-P Condition” Interrupt has occurred
since the last read of this register.
Note:
The user can determine the current state of UNEQ-P by reading
424
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
out the state of Bit 5 (UNEQ-P Defect Declared) within the
“Receive STS-1 Path – SONET Receive POH Status – Byte 0”
Register (Address Location= 0xN187).
4
Change in PLMP Condition
Interrupt Status
RUR
Change in PLM-P (Path – Payload Mismatch) Condition Interrupt
Status:
This RESET-upon-READ bit indicates whether or not the “Change in PLM-P
Condition” interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will
generate an interrupt in response to either of the following conditions.
• When the Receive STS-1 POH Processor block declares the “PLM-P”
Condition.
• When the Receive STS-1 POH Processor block clears the “PLM-P”
Condition.
0 – Indicates that the “Change in PLM-P Condition” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Change in PLM-P Condition” Interrupt has occurred
since the last read of this register.
3
New C2 Byte
Interrupt Status
RUR
New C2 Byte Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New C2
Byte” Interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will
generate an interrupt anytime it has accepted a new C2 byte.
0 – Indicates that the “New C2 Byte” Interrupt has NOT occurred since the
last read of this register.
1 – Indicates that the “New C2 Byte” Interrupt has occurred since the last
read of this register.
2
Change in C2
Byte Unstable
Condition
Interrupt Status
RUR
Change in C2 Byte Unstable Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change in
C2 Byte Unstable Condition” Interrupt has occurred since the last read of
this register.
If this interrupt is enabled , then the Receive STS-1 POH Processor block
will generate an interrupt in response to either of the following events.
• When the Receive STS-1 POH Processor block declares the “C2 Byte
Unstable” condition.
• When the Receive STS-1 POH Processor block clears the “C2 Byte
Unstable” condition.
0 – Indicates that the “Change in C2 Byte Unstable Condition” Interrupt has
NOT occurred since the last read of this register.
1 – Indicates that the “Change in C2 Byte Unstable Condition” Interrupt has
occurred since the last read of this register.
Note:
1
Change in RDIP Unstable
Condition
Interrupt Status
RUR
The user can determine the current state of “C2 Byte Unstable
Condition” by reading out the state of Bit 6 (C2 Byte Unstable
Condition) within the “Receive STS-1 Path – SONET Receive
POH Status – Byte 0” Register (Address Location= 0xN187).
Change in RDI-P Unstable Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change in
RDI-P Unstable Condition” interrupt has occurred since the last read of this
register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will
425
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Rev222...000...000
generate an interrupt in response to either of the following conditions.
• When the Receive STS-1 POH Processor block declares an “RDI-P
Unstable” condition.
• When the Receive STS-1 POH Processor block clears the “RDI-P
Unstable” condition.
0 – Indicates that the “Change in RDI-P Unstable Condition” Interrupt has
NOT occurred since the last read of this register.
1 – Indicates that the “Change in RDI-P Unstable Condition” Interrupt has
occurred since the last read of this register.
Note:
0
New RDI-P
Value Interrupt
Status
RUR
The user can determine the current state of “RDI-P Unstable” by
reading out the state of Bit 2 (RDI-P Unstable Condition) within the
“Receive STS-1 Path – SONET Receive POH Status – Byte 0”
Register (Address Location= 0xN187).
New RDI-P Value Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “New RDI-P
Value” interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor block will
generate this interrupt anytime it receives and “validates” a new RDI-P
value.
0 – Indicates that the “New RDI-P Value” Interrupt has NOT occurred since
the last read of this register.
1 – Indicates that the “New RDI-P Value” Interrupt has occurred since the
last read of this register.
Note:
The user can obtain the “New RDI-P Value” by reading out the
contents of the “RDI-P ACCEPT[2:0]” bit-fields. These bit-fields
are located in Bits 6 through 4, within the “Receive STS-1 Path –
SONET Receive RDI-P Register” (Address Location= 0xN193).
426
XRT94L33
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S---111 T
TO
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ST
TS
S---333///S
ST
TM
M---111 M
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AP
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R ––– A
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MR
RE
EG
GIIIS
ST
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Rev222...000...000
Table 358: Receive STS-1 Path – SONET Receive Path Interrupt Status – Byte 0 (Address Location=
0xN18B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Detection of
B3 Byte
Error
Interrupt
Status
Detection of
New Pointer
Interrupt
Status
Detection of
Unknown
Pointer
Interrupt
Status
Detection of
Pointer
Decrement
Interrupt
Status
Detection of
Pointer
Increment
Interrupt
Status
Detection of
NDF Pointer
Interrupt
Status
Change of
LOP-P
Condition
Interrupt
Status
Change of
AIS-P
Condition
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Detection of B3 Byte
Error Interrupt Status
RUR
DESCRIPTION
Detection of B3 Byte Error Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Detection of B3 Byte Error” Interrupt has occurred since the last read
of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt anytime it detects a B3 byte error in the
incoming STS-1 data stream.
0 – Indicates that the “Detection of B3 Byte Error” Interrupt has NOT
occurred since the last read of this interrupt.
1 – Indicates that the “Detection of B3 Byte Error” Interrupt has
occurred since the last read of this interrupt.
6
Detection of New
Pointer Interrupt
Status
RUR
Detection of New Pointer Interrupt Status:
This RESET-upon-READ indicates whether the “Detection of New
Pointer” interrupt has occurred since the last read of this register.
If the user enables this interrupt, then the Receive STS-1 POH
Processor block will generate an interrupt anytime it detects a new
pointer value in the incoming STS-1 frame.
Note:
Pointer Adjustments with NDF will not generate this interrupt.
0 – Indicates that the “Detection of New Pointer” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Detection of New Pointer” Interrupt has occurred
since the last read of this register.
5
Detection of Unknown
Pointer Interrupt
Status
RUR
Detection of Unknown Pointer Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Detection of Unknown Pointer” interrupt has occurred since the last
read of this register.
If the user enables this interrupt, then the Receive STS-1 POH
Processor block will generate an interrupt anytime that it detects a
“pointer” that does not fit into any of the following categories.
• An Increment Pointer
• A Decrement Pointer
• An NDF Pointer
• An AIS (e.g., All Ones) Pointer
• New Pointer
0 – Indicates that the “Detection of Unknown Pointer” interrupt has NOT
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M---111 M
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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Rev222...000...000
occurred since the last read of this register.
1 – Indicates that the “Detection of Unknown Pointer” interrupt has
occurred since the last read of this register.
4
Detection of Pointer
Decrement Interrupt
Status
RUR
Detection of Pointer Decrement Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Detection of Pointer Decrement” Interrupt has occurred since the last
read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt anytime it detects a “Pointer Decrement”
event.
0 – Indicates that the “Detection of Pointer Decrement” interrupt has
NOT occurred since the last read of this register.
1 – Indicates that the “Detection of Pointer Decrement” interrupt has
occurred since the last read of this register.
3
Detection of Pointer
Increment Interrupt
Status
RUR
Detection of Pointer Increment Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Detection of Pointer Increment” Interrupt has occurred since the last
read of this register.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt anytime it detects a “Pointer Increment”
event.
0 – Indicates that the “Detection of Pointer Increment” interrupt has
NOT occurred since the last read of this register.
1 – Indicates that the “Detection of Pointer Increment” interrupt has
occurred since the last read of this register.
2
Detection of NDF
Pointer Interrupt
Status
RUR
Detection of NDF Pointer Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the
“Detection of NDF Pointer” interrupt has occurred since the last read of
this register. If the user enables this interrupt, then the Receive STS-1
POH Processor block will generate an interrupt anytime it detects an
NDF Pointer event.
0 – Indicates that the “Detection of NDF Pointer” interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Detection of NDF Pointer” interrupt has occurred
since the last read of this register.
1
Change of LOP-P
Condition Interrupt
Status
RUR
Change of LOP-P Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change
in LOP-P Condition” interrupt has occurred since the last read of this
register.
If the user enables this interrupt, then the Receive STS-1 POH
Processor block will generate an interrupt in response to either of the
following events.
•
When the Receive STS-1 POH Processor block declares an “Loss
of Pointer” condition.
•
When the Receive “STS-1 POH Processor” block clears the “Loss
of Pointer” condition.
0 – Indicates that the “Change in LOP-P Condition” interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Change in LOP-P Condition” interrupt has
428
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Rev222...000...000
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M---111 M
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PP
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R ––– A
AT
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RE
EG
GIIIS
ST
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RS
S
occurred since the last read of this register.
Note:
0
Change of AIS-P
Condition Interrupt
Status
RUR
The user can determine the current state of LOP-P by reading
out the state of Bit 1 (LOP-P Defect Declared) within the
“Receive STS-1 Path – SONET Receive POH Status – Byte
0” Register (Address Location=0xN187).
Change of AIS-P Condition Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Change
of AIS-P Condition” Interrupt has occurred since the last read of this
register.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt in response to either of the following
events.
• When the Receive STS-1 POH Processor block declares an AIS-P
condition.
• When the Receive STS-1 POH Processor block clears the AIS-P
condition.
0 – Indicates that the “Change of AIS-P Condition” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Change of AIS-P Condition” Interrupt has
occurred since the last read of this register.
Note:
The user can determine the current state of AIS-P by reading
out the state of Bit 0 (AIS-P Defect Declared) within the
“Receive STS-1 Path – SONET Receive POH Status – Byte
0” Register (Address Location= 0xN187).
429
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N
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O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
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LD
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S333///E
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ST
TS
S---111 T
TO
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ST
TS
S---333///S
ST
Rev222...000...000
Table 359: Receive STS-1 Path – SONET Receive Path Interrupt Enable – Byte 2 (Address Location =
0xN18D)
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Detection of
AIS Pointer
Interrupt
Enable
Detection of
Pointer
Change
Interrupt
Enable
Unused
Change in
TIM-P
Condition
Interrupt
Enable
Change in J1
Unstable
Condition
Interrupt
Enable
R/O
R/O
R/O
R/W
R/W
R/O
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-5
Unused
R/O
4
Detection of AIS Pointer
Interrupt Enable
R/W
DESCRIPTION
Detection of AIS Pointer Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the “Detection of AIS Pointer” interrupt.
If the user enables this interrupt, then the Receive STS-1 POH
Processor block will generate an interrupt anytime it detects an “AIS
Pointer”, in the incoming STS-1 data stream.
Note:
An “AIS Pointer” is defined as a condition in which both the
H1 and H2 bytes (within the TOH) are each set to an “All
Ones” Pattern.
0 – Disables the “Detection of AIS Pointer” Interrupt.
1 – Enables the “Detection of AIS Pointer” Interrupt.
3
Detection of Pointer
Change Interrupt
Enable
R/W
Detection of Pointer Change Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the “Detection of Pointer Change” Interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt anytime it has accepted a new pointer
value.
0 – Disables the “Detection of Pointer Change” Interrupt.
1 - Enables the “Detection of Pointer Change” Interrupt.
2
Unused
R/O
1
Change in TIM-P
Condition Interrupt
Enable
R/W
Change in TIM-P (Trace Identification Mismatch) Condition
Interrupt:
This READ/WRITE bit-field permits the user to either enable or
disable the “Change in TIM-P Condition” interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt in response to either of the following
events.
• If the TIM-P condition is declared.
• If the TIM-P condition is cleared.
0 – Disables the “Change in TIM-P Condition” Interrupt.
1 – Enables the “Change in TIM-P Condition” Interrupt.
0
Change in J1 Unstable
Condition Interrupt
R/W
Change in “J1 (Trace Identification
Condition” Interrupt Status:
430
Message)
Unstable
XRT94L33
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ST
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TM
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MA
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R ––– A
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MR
RE
EG
GIIIS
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Rev222...000...000
Enable
Condition” Interrupt Status:
This READ/WRITE bit-field permits the user to either enable or
disable the “Change in J1 (Trace Identification) Message Unstable
Condition” Interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt in response to either of the following
events.
• When the Receive STS-1 POH Processor block declares the “J1
Unstable” Condition.
• When the Receive STS-1 POH Processor block clears the “J1
Unstable” Condition.
0 – Disables the “Change in J1 Message Unstable Condition”
interrupt.
1 – Enables the “Change in J1 Message Unstable Condition”
interrupt.
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N
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L
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S
T
O
S
T
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M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
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ST
TS
S---333///S
ST
Rev222...000...000
Table 360: Receive STS-1 Path – SONET Receive Path Interrupt Enable – Byte 1 (Address Location=
0xN18E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New J1
Message
Interrupt
Enable
Detection of
REI-P Event
Interrupt
Enable
Change in
UNEQ-P
Condition
Interrupt
Enable
Change in
PLM-P
Condition
Interrupt
Enable
New C2
Byte
Interrupt
Enable
Change in
C2 Byte
Unstable
Condition
Interrupt
Enable
Change in
RDI-P
Unstable
Condition
Interrupt
Enable
New
RDI-P
Value
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
New J1 Message
Interrupt Enable
R/W
DESCRIPTION
New J1 (Trace Identification) Message Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “New J1 Message” Interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt anytime it has accepted (or validated)
and new J1 (Trace Identification) Message.
0 – Disables the “New J1 Message” Interrupt.
1 – Enables the “New J1 Message” Interrupt.
6
Detection of REI-P
Event Interrupt
Enable
R/W
Detection of REI-P Event Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Detection of REI-P Event” Interrupt.
If this interrupt is enabled, then he Receive STS-1 POH Processor
block will generate an interrupt anytime it detects an REI-P condition in
the coming STS-1 data-stream.
0 – Disables the “Detection of REI-P Event” Interrupt.
1 – Enables the “Detection of REI-P Event” Interrupt.
5
Change in UNEQ-P
Condition Interrupt
Enable
R/W
Change in UNEQ-P (Path – Unequipped) Condition Interrupt
Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Change in UNEQ-P Condition” interrupt.
If this interrupt is enabled , then the Receive STS-1 POH Processor
block will generate an interrupt in response to either of the following
conditions.
• When the Receive STS-1 POH Processor block declares the UNEQP Condition.
• When the Receive STS-1 POH Processor block clears the UNEQ-P
Condition.
0 – Disables the “Change in UNEQ-P Condition” Interrupt.
1 – Enables the “Change in UNEQ-P Condition” Interrupt.
4
Change in PLM-P
Condition Interrupt
Enable
R/W
Change in PLM-P (Path – Payload Mismatch) Condition Interrupt
Enable:
This READ/WRITE bit permits the user to either enable or disable the
“Change in PLM-P Condition” interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor
432
XRT94L33
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HA
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LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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S
Rev222...000...000
block will generate an interrupt in response to either of the following
conditions.
• When the Receive STS-1 POH Processor block declares the “PLMP” Condition.
• When the Receive STS-1 POH Processor block clears the “PLM-P”
Condition.
0 – Disables the “Change in PLM-P Condition” Interrupt.
1 – Enables the “Change in PLM-P Condition” Interrupt.
3
New C2 Byte
Interrupt Enable
R/W
New C2 Byte Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “New C2 Byte” Interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt anytime it has accepted a new C2 byte.
0 – Disables the “New C2 Byte” Interrupt.
1 – Enables the “New C2 Byte” Interrupt.
Note:
2
Change in C2 Byte
Unstable Condition
Interrupt Enable
R/W
The user can obtain the value of this “New C2” byte by reading
the contents of the “Receive STS-1 Path – Received Path
Label Value” Register (Address Location= 0xN196).
Change in C2 Byte Unstable Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Change in C2 Byte Unstable Condition” Interrupt.
If this interrupt is enabled , then the Receive STS-1 POH Processor
block will generate an interrupt in response to either of the following
events.
• When the Receive STS-1 POH Processor block declares the “C2
Byte Unstable” condition.
• When the Receive STS-1 POH Processor block clears the “C2 Byte
Unstable” condition.
0 – Disables the “Change in C2 Byte Unstable Condition” Interrupt.
1 – Enables the “Change in C2 Byte Unstable Condition” Interrupt.
1
Change in RDI-P
Unstable Condition
Interrupt Enable
R/W
Change in RDI-P Unstable Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “Change in RDI-P Unstable Condition” interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate an interrupt in response to either of the following
conditions.
• When the Receive STS-1 POH Processor block declares an “RDI-P
Unstable” condition.
• When the Receive STS-1 POH Processor block clears the “RDI-P
Unstable” condition.
0 – Disables the “Change in RDI-P Unstable Condition” Interrupt.
1 – Enables the “Change in RDI-P Unstable Condition” Interrupt.
0
New RDI-P Value
Interrupt Enable
R/W
New RDI-P Value Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the “New RDI-P Value” interrupt.
If this interrupt is enabled, then the Receive STS-1 POH Processor
block will generate this interrupt anytime it receives and “validates” a
433
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T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
new RDI-P value.
0 – Disables the “New RDI-P Value” Interrupt.
1 – Enable the “New RDI-P Value” Interrupt.
434
Rev222...000...000
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 361: Receive STS-1 Path – SONET Receive Path Interrupt Enable – Byte 0 (Address Location=
0xN18F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Detection of
B3 Byte
Error
Interrupt
Enable
Detection of
New Pointer
Interrupt
Enable
Detection of
Unknown
Pointer
Interrupt
Enable
Detection of
Pointer
Decrement
Interrupt
Enable
Detection of
Pointer
Increment
Interrupt
Enable
Detection of
NDF Pointer
Interrupt
Enable
Change of
LOP-P
Condition
Interrupt
Enable
Change of
AIS-P
Condition
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7
Detection of
B3 Byte
Error
Interrupt
Enable
R/W
Detection of B3 Byte Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of B3 Byte Error” Interrupt. If the user enables this interrupt, then the
Receive STS-1 POH Processor block will generate an interrupt anytime it detects
a B3-byte error in the incoming STS-1 data-stream.
0 – Disables the “Detection of B3 Byte Error” interrupt.
1 – Enables the “Detection of B3 Byte Error” interrupt.
6
Detection of
New Pointer
Interrupt
Enable
R/W
Detection of New Pointer Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of New Pointer” interrupt. If the user enables this interrupt, then the
Receive STS-1 POH Processor block will generate an interrupt anytime it detects
a new pointer value in the incoming STS-1 frame.
Note:
Pointer Adjustments with NDF will not generate this interrupt.
0 – Disables the “Detection of New Pointer” Interrupt.
1 – Enables the “Detection of New Pointer” Interrupt.
5
Detection of
Unknown
Pointer
Interrupt
Enable
R/W
Detection of Unknown Pointer Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of Unknown Pointer” interrupt. If the user enables this interrupt, then
the Receive STS-1 POH Processor block will generate an interrupt anytime it
detects a “Pointer Adjustment” that does not fit into any of the following
categories.
• An Increment Pointer.
• A Decrement Pointer
• An NDF Pointer
• AIS Pointer
• New Pointer.
0 – Disables the “Detection of Unknown Pointer” Interrupt.
1 – Enables the “Detection of Unknown Pointer” Interrupt.
4
Detection of
Pointer
Decrement
Interrupt
Enable
R/W
Detection of Pointer Decrement Interrupt Enable:
This READ/WRITE bit-field permits the user to enable or disable the “Detection of
Pointer Decrement” Interrupt. If the user enables this interrupt, then the Receive
STS-1 TOH Processor block will generate an interrupt anytime it detects a
“Pointer-Decrement” event.
0 – Disables the “Detection of Pointer Decrement” Interrupt.
435
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
1 – Enables the “Detection of Pointer Decrement” Interrupt.
3
Detection of
Pointer
Increment
Interrupt
Enable
R/W
Detection of Pointer Increment Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of Pointer Increment” Interrupt. If the user enables this interrupt, then
the Receive STS-1 POH Processor block will generate an interrupt anytime it
detects a “Pointer Increment” event.
0 – Disables the “Detection of Pointer Increment” Interrupt.
1 – Enables the “Detection of Pointer Increment” Interrupt.
2
Detection of
NDF Pointer
Interrupt
Enable
R/W
Detection of NDF Pointer Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of NDF Pointer” Interrupt. If the user enables this interrupt, then the
Receive STS-1 POH Processor block will generate an interrupt anytime it detects
an NDF Pointer event.
0 – Disables the “Detection of NDF Pointer” interrupt.
1 – Enables the “Detection of NDF Pointer” interrupt.
1
Change of
LOP-P
Condition
Interrupt
Enable
R/W
Change of LOP-P Condition Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change in LOP (Loss of Pointer)” Condition interrupt. If the user enables this
interrupt, then the Receive STS-1 POH Processor block will generate an interrupt
in response to either of the following events.
•
When the Receive STS-1 POH Processor block declares a “Loss of Pointer”
condition.
•
When the Receive STS-1 POH Processor block clears the “Loss of Pointer”
condition.
0 – Disable the “Change of LOP” Interrupt.
1 – Enables the “Change of LOP” Interrupt.
Note:
0
Change of
AIS-P
Interrupt
Enable
R/W
The user can determine the current state of “LOP” by reading out the
contents of Bit 1 (LOP) within the “Receive STS-1 Path – SONET
Receive POH Status – Byte 0” (Address Location= 0xN187).
Change of AIS-P Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Change of AIS-P (Path AIS)” interrupt. If the user enables this interrupt, then the
Receive STS-1 POH Processor block will generate an interrupt in response to
either of the following events.
•
When the Receive STS-1 POH Processor block declares an “AIS-P”
condition.
•
When the Receive STS-1 POH Processor block clears the “AIS-P” condition.
0 – Disables the “Change of AIS-P” Interrupt.
1 – Enables the “Change of AIS-P” Interrupt.
Note:
The user can determine the current state of “AIS-P” by reading out the
contents of Bit 0 (AIS-P Defect Declared) within the “Receive STS-1
Path – SONET Receive POH Status – Byte 0” (Address Location=
0xN187).
Table 362: Receive STS-1 Path – SONET Receive RDI-P Register (Address Location= 0xN193)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
436
BIT 2
BIT 1
BIT 0
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Unused
RDI-P_ACCEPT[2:0]
RDI-P THRESHOLD[3:0]
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6-4
RDI-P_ACCEPT[2:0]
R/O
DESCRIPTION
Accepted RDI-P Value:
These READ-ONLY bit-fields contain the value of the most recently
“accepted” RDI-P (e.g., bits 5, 6 and 7 within the G1 byte) value.
Note:
3-0
RDI-P THRESHOLD[3:0]
R/W
A given RDI-P value will be “accepted” by the Receive
STS-1 POH Processor block, if this RDI-P value has been
consistently received in “RDI-P THRESHOLD[3:0]”
number of STS-1 frames.
RDI-P Threshold:
These READ/WRITE bit-fields permit the user to defined the “RDI-P
Acceptance Threshold” for the Receive STS-1 POH Processor
Block.
The “RDI-P Acceptance Threshold” is the number of consecutive
STS-1 frames, in which the Receive STS-1 POH Processor block
must receive a given RDI-P value, before it “accepts” or “validates”
it.
The most recently “accepted” RDI-P value is written into the “RDI-P
ACCEPT[2:0]” bit-fields, within this register.
437
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 363: Receive STS-1 Path – Received Path Label Value (Address Location= 0xN196)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Received_C2_Byte_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Received C2 Byte Value[7:0]
R/O
Received “Filtered” C2 Byte Value:
These READ-ONLY bit-fields contain the value of the most
recently “accepted” C2 byte, via the Receive STS-1 POH
Processor block.
The Receive STS-1 POH Processor block will “accept” a C2
byte value (and load it into these bit-fields) if it has received a
consistent C2 byte, in five (5) consecutive STS-1 frames.
Note:
The Receive STS-1 POH Processor block uses this
register, along the “Receive STS-1 Path – Expected
Path Label Value” Register (Address Location =
0xN197), when declaring or clearing the UNEQ-P
and PLM-P alarm conditions.
Table 364: Receive STS-1 Path – Expected Path Label Value (Address Location= 0xN197)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Expected_C2_Byte_Value[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
BIT NUMBER
NAME
TYPE
7-0
Expected C2 Byte Value[7:0]
R/W
DESCRIPTION
Expected C2 Byte Value:
These READ/WRITE bit-fields permits the user to specify the
C2 (Path Label Byte) value, that the Receive STS-1 POH
Processor block should expect when declaring or clearing the
UNEQ-P and PLM-P alarm conditions.
If the contents of the “Received C2 Byte Value[7:0]” (see
“Receive STS-1 Path – Received Path Label Value” register)
matches the contents in these register, then the Receive STS1 POH will not declare any alarm conditions.
438
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 365: Receive STS-1 Path – B3 Error Count Register – Byte 3 (Address Location= 0xN198)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B3_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B3_Error_Count[31:24]
RUR
DESCRIPTION
B3 Error Count – MSB:
This RESET-upon-READ register, along with “Receive STS-1
Path – B3 Error Count Register – Bytes 2 through 0; function as a
32 bit counter, which is incremented anytime the Receive STS-1
POH Processor block detects a B3 byte error.
Note:
1. If the B3 Error Type is configured to be “bit errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit
counter by the number of bits, within the B3 value that are in error.
2. If the B3 Error Type is configured to be “frame errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit
counter by the number of frames that contain erred B3 bytes.
Table 366: Receive STS-1 Path – B3 Error Count Register – Byte 2 (Address Location= 0xN199)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B3_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B3_Error_Count[23:16]
RUR
DESCRIPTION
B3 Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Receive STS-1 Path –
B3 Error Count Register – Bytes 3, 1 and 0; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 POH
Processor block detects a B3 byte error.
Note:
1. If the B3 Error Type is configured to be “bit errors”, then the Receive
STS-1 POH Processor block will increment this 32 bit counter by the
number of bits, within the B3 value that are in error.
2. If the B3 Error Type is configured to be “frame errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit counter
by the number of frames that contain erred B3 bytes.
439
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 367: Receive STS-1 Path – B3 Error Count Register – Byte 1 (Address Location= 0xN19A)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B3_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-0
B3_Error_Count[15:8]
RUR
B3 Error Count – (Bits 15 through 8):
This RESET-upon-READ register, along with “Receive STS-1
Path – B3 Error Count Register – Bytes 3, 2 and 0; function as a
32 bit counter, which is incremented anytime the Receive STS-1
POH Processor block detects a B3 byte error.
Note:
1. If the B3 Error Type is configured to be “bit errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit
counter by the number of bits, within the B3 value that are in error.
2. If the B3 Error Type is configured to be “frame errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit
counter by the number of frames that contain erred B3 bytes.
Table 368: Receive STS-1 Path – B3 Error Count Register – Byte 0 (Address Location= 0xN19B)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
B3_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
B3_Error_Count[7:0]
RUR
DESCRIPTION
B3 Error Count - LSB:
This RESET-upon-READ register, along with “Receive STS-1 Path – B3
Error Count Register – Bytes 3 through 1; function as a 32 bit counter,
which is incremented anytime the Receive STS-1 POH Processor block
detects a B3 byte error.
Note:
1. If the B3 Error Type is configured to be “bit errors”, then the Receive
STS-1 POH Processor block will increment this 32 bit counter by the
number of bits, within the B3 value that are in error.
2. If the B3 Error Type is configured to be “frame errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit counter by
the number of frames that contain erred B3 bytes.
440
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 369: Receive STS-1 Path – REI-P Error Count Register – Byte 3 (Address Location= 0xN19C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_P_Error_Count[31:24]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_P_Error_Count[31:24]
RUR
DESCRIPTION
REI-P Error Count – MSB:
This RESET-upon-READ register, along with “Receive STS-1 Path
– REI-P Error Count Register – Bytes 2 through 0; function as a 32
bit counter, which is incremented anytime the Receive STS-1 POH
Processor block detects a Path - Remote Error Indicator.
Note:
1. If the REI-P Error Type is configured to be “bit errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit
counter by the nibble-value within the REI-P field of the incoming
G1 byte.
2. If the REI-P Error Type is configured to be “frame errors”, then
the Receive STS-1 POH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-P
values.
Table 370: Receive STS-1 Path – REI_P Error Count Register – Byte 2 (Address Location= 0xN19D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_P_Error_Count[23:16]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_P_Error_Count[23:16]
RUR
DESCRIPTION
REI-P Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Receive STS-1
Path – REI-P Error Count Register – Bytes 3, 1 and 0; function as
a 32 bit counter, which is incremented anytime the Receive STS1 POH Processor block detects a Path – Remote Error Indicator.
Note:
1. If the REI-P Error Type is configured to be “bit errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit
counter by the nibble-value within the REI-P field of the incoming
G1 byte.
2. If the REI-P Error Type is configured to be “frame errors”, then
the Receive STS-1 POH Processor block will increment this 32
bit counter by the number of frames that contain non-zero REI-P
values.
441
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 371: Receive STS-1 Path – REI_P Error Count Register – Byte 1 (Address Location= 0xN19E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_P_Error_Count[15:8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_P_Error_Count[15:8]
RUR
DESCRIPTION
REI-P Error Count – (Bits 15 through 8)
This RESET-upon-READ register, along with “Receive STS-1
Path – REI-P Error Count Register – Bytes 3, 2 and 0; function as
a 32 bit counter, which is incremented anytime the Receive STS-1
POH Processor block detects a Path –Remote Error Indicator.
Note:
1. If the REI-P Error Type is configured to be “bit errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit
counter by the nibble-value within the REI-P field of the incoming
G1 byte.
2. If the REI-P Error Type is configured to be “frame errors”, then
the Receive STS-1 POH Processor block will increment this 32 bit
counter by the number of frames that contain non-zero REI-P
values.
Table 372: Receive STS-1 Path – REI_P Error Count Register – Byte 0 (Address Location= 0xN19F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REI_P_Error_Count[7:0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-0
REI_P_Error_Count[7:0]
RUR
DESCRIPTION
REI-P Error Count – LSB:
This RESET-upon-READ register, along with “Receive STS-1 Path –
REI-P Error Count Register – Bytes 3 through 1; function as a 32 bit
counter, which is incremented anytime the Receive STS-1 POH
Processor block detects a Path – Remote Error Indicator.
Note:
1. If the REI-P Error Type is configured to be “bit errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit counter
by the nibble-value within the REI-P field of the incoming G1 byte.
2. If the REI-P Error Type is configured to be “frame errors”, then the
Receive STS-1 POH Processor block will increment this 32 bit counter
by the number of frames that contain non-zero REI-P values.
442
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Table 373: Receive STS-1 Path – Receive J1 Control Register (Address Location= 0xN1A3)
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
BIT 2
Receive J1 Message
Buffer Read Select
Accept
Threshold
Message
Type
BIT 1
BIT 0
Message Length[1:0]
R/O
R/O
R/O
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–5
Unused
R/O
4
Received J1 Message
Buffer Read Select
R/W
DESCRIPTION
J1 Buffer Read Selection:
This READ/WRITE bit-field permits a user to specify which of the
following buffer segments to read.
a.
Valid Message Buffer
b.
Expected Message Buffer
0 – Executing a READ to the Receive J1 Trace Buffer, will return
contents within the “Valid Message” buffer.
1 – Executing a READ to the Receive J1 Trace Buffer, will return
contents within the “Expected Message Buffer”.
Note:
3
Accept Threshold
R/W
In the case of the Receive STS-1 POH Processor block, the
“Receive J1 Trace Buffer” is located at Address Location
0xN500 through 0xN53F.
Message Accept Threshold:
This READ/WRITE bit-field permits a user to select the number of
consecutive times that the Receive STS-1 POH Processor block
must receive a given J1 Trace Message, before it is accepted, as
described below.
0 – The Receive STS-1 POH Processor block accepts the J1
Message after it has received it the third time in succession.
1 – The Receive SONET POH Processor block accepts the J1
Message after it has received in the fifth time in succession.
2
Message Type
R/O
Message Alignment Type:
This READ/WRITE bit-field permits a user to specify have the
Receive STS-1 POH Processor block will locate the boundary of the
J1 Trace Message, as indicated below.
0 – Message boundary is indicated by “Line Feed”.
1 – Message boundary is indicated by the presence of a “1” in the
MSB of a the first byte (within the J1 Trace Message).
1–0
Message Length[1:0]
R/W
J1 Message Length[1:0]:
These READ/WRITE bit-fields permit the user to specify the length of
the J1 Trace Message, that the Receive STS-1 POH Processor block
will receive. The relationship between the content of these bit-fields
and the corresponding J1 Trace Message Length is presented below.
MSG LENGTH
Resulting J1 Trace Message Length
00
1 Byte
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16 Bytes
10/11
64 Bytes
444
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Table 374: Receive STS-1 Path – Pointer Value – Byte 1 (Address Location= 0xN1A6)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
BIT 0
Current_Pointer Value
MSB[9:8]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-2
Unused
R/O
1–0
Current_Pointer_Value_MSB[7:0]
R/O
DESCRIPTION
Current Pointer Value – MSB:
These READ-ONLY bit-fields, along with that from the
“Receive STS-1 Path – Pointer Value – Byte 0” Register
combine to reflect the current value of the pointer that the
“Receive STS-1 POH Processor” block is using to locate
the SPE within the incoming STS-1 data stream.
Note:
These register bits comprise the Upper Byte value
of the Pointer Value.
Table 375: Receive STS-1 Path – Pointer Value – Byte 0 (Address Location= 0xN1A7)
BIT 7
BIT 6
BIT 5
BIT 4
R/O
R/O
R/O
R/O
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/O
R/O
R/O
R/O
0
0
0
0
Current_Pointer_Value_LSB[7:0]
BIT NUMBER
NAME
TYPE
7–0
Current_Pointer_Value_LSB[7:0]
R/O
DESCRIPTION
Current Pointer Value – LSB:
These READ-ONLY bit-fields, along with that from the
“Receive STS-1 Path – Pointer Value – Byte 1” Register
combine to reflect the current value of the pointer that the
“Receive STS-1 POH Processor” block is using to locate the
SPE within the incoming STS-1 data stream.
Note:
445
These register bits comprise the Lower Byte value
of the Pointer Value.
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Rev222...000...000
Table 376: Receive STS-1 Path – AUTO AIS Control Register (Address Location= 0xN1BB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Transmit
AIS-P
(Downstream)
Upon C2
Byte
Unstable
Transmit
AIS-P
(Downstream)
Upon
UNEQ-P
Transmit
AIS-P
(Downstream)
Upon PLMP
Transmit
AIS-P
(Downstream)
Upon J1
Message
Unstable
Transmit
AIS-P
(Downstream)
upon
TIM-P
Transmit
AIS-P
(Downstream)
upon LOP-P
Transmit
AIS-P
(Downstream)
Enable
R/O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6
Transmit AIS-P
(Downstream) upon C2
Byte Unstable
R/W
DESCRIPTION
Transmit Path AIS upon Detection of Unstable C2 Byte:
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 POH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Transmit SONET POH Processor blocks), anytime it detects an
Unstable C2 Byte condition in the “incoming” STS-1 data-stream.
0 – Does not configure the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator (via the “downstream”
traffic) whenever it detects an “Unstable C2 Byte” condition.
1 – Configures the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator (via the “downstream”
traffic) whenever it detects an “Unstable C2 Byte” condition.
Note:
5
Transmit AIS-P
(Downstream) upon
UNEQ-P
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS upon Detection of Path-Unequipped Defect
(UNEQ-P):
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 POH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Transmit SONET POH Processor blocks), anytime it declares an
UNEQ-P condition.
0 – Does not configure the Receive STS-1 POH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the UNEQ-P defect.
1 – Configures the Receive STS-1 POH Processor block to transmit
the AIS-P indicator (via the “downstream” traffic) upon declaration of
the UNEQ-P defect.
Note:
4
Transmit AIS-P
(Downstream) upon
PLM-P
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS upon Detection of Path-Payload Label
Mismatch Defect (PLM-P):
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 POH Processor block to automatically transmit a Path AIS
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(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Transmit SONET POH Processor blocks), anytime it declares an
PLM-P condition.
0 – Does not configure the Receive STS-1 POH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the PLM-P defect.
1 – Configures the Receive STS-1 POH Processor block to transmit
the AIS-P indicator (via the “downstream” traffic) upon declaration of
the PLM-P defect.
Note:
3
Transmit AIS-P
(Downstream) upon J1
Message Unstable
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS upon Detection of Unstable 1 Message:
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 POH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Transmit SONET POH Processor blocks), anytime it detects an
Unstable J1 Message condition in the “incoming” STS-1 data-stream.
0 – Does not configure the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator (via the “downstream”
traffic) whenever it detects an “Unstable J1 Message” condition.
1 – Configures the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator (via the “downstream”
traffic) whenever it detects an “Unstable J1 Message” condition.
Note:
2
Transmit AIS-P
(Downstream) upon
TIM-P
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS upon Detection of Path-Trace Identification
Message Mismatch Defect (TIM-P):
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 POH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Transmit SONET POH Processor blocks), anytime it declares a TIMP condition.
0 – Does not configure the Receive STS-1 POH Processor block to
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the TIM-P defect.
1 – Configures the Receive STS-1 POH Processor block to transmit
the AIS-P indicator (via the “downstream” traffic) upon declaration of
the TIM-P defect.
Note:
1
Transmit AIS-P
(Downstream) upon
LOP-P
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Transmit Path AIS upon Detection of Loss of Pointer (LOP-P):
This READ/WRITE bit-field permits the user to configure the Receive
STS-1 POH Processor block to automatically transmit a Path AIS
(AIS-P) Indicator via the “downstream” traffic (e.g., towards the
Transmit SONET POH Processor blocks), anytime it declares an
LOP-P condition.
0 – Does not configure the Receive STS-1 POH Processor block to
447
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Rev222...000...000
transmit the AIS-P indicator (via the “downstream” traffic) upon
declaration of the LOP-P defect.
1 – Configures the Receive STS-1 POH Processor block to transmit
the AIS-P indicator (via the “downstream” traffic) upon declaration of
the LOP-P defect.
Note:
0
Transmit AIS-P
(Downstream) Enable
R/W
The user must also set Bit 0 (Transmit AIS-P Enable) to “1”
to configure the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator, in response to
this defect condition.
Automatic Transmission of AIS-P Enable:
This READ/WRITE bit-field serves two purposes.
It permits the user to configure the Receive STS-1 POH Processor
block to automatically transmit the Path AIS indicator, via the downstream traffic (e.g., towards the Transmit SONET POH Processor
blocks), upon detection of an UNEQ-P, PLM-P, LOP-P or LOS
conditions.
It also permits the user to configure the Receive STS-1 POH
Processor block to automatically transmit a Path (AIS-P) Indicator via
the “downstream” traffic (e.g., towards the Transmit SONET POH
Processor blocks) anytime it detects an AIS-P condition in the
“incoming “ STS-1 data-stream.
0 – Configures the Receive STS-1 POH Processor block to NOT
automatically transmit the AIS-P indicator (via the “downstream”
traffic) upon detection of any of the “above-mentioned” conditions.
1 – Configures the Receive STS-1 POH Processor block to
automatically transmit the AIS-P indicator (via the “downstream”
traffic) upon detection of any of the “above-mentioned” condition.
Note:
The user must also set the corresponding bit-fields (within
this register) to “1” in order to configure the Receive STS-1
POH Processor block to automatically transmit the AIS-P
indicator upon detection of a given alarm/defect condition.
448
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Table 377: Receive STS-1 Path – SONET Receive Auto Alarm Register – Byte 0 (Address Location=
0xN1C3)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Transmit
AIS-P (via
Downstream
STS-1s)
upon LOP-P
Transmit
AIS-P (via
Downstream
STS-1s)
upon
PLM-P
Transmit
AIS-P (via
Downstream
STS-1s)
upon
LCD-P
Transmit
AIS-P (via
Downstream
STS-1s)
upon
UNEQ-P
Transmit
AIS-P (via
Downstream
STS-1s)
upon TIM-P
Transmit
AIS-P (via
Downstream
STS-1s)
upon AIS-P
Transmit
DS3 AIS
(via
Downstream
DS3) upon
PDI-P
R/O
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Unused
R/O
6
Transmit AIS-P (via
Downstream STS-1s)
upon LOP-P
R/W
DESCRIPTION
Transmit AIS-P (via Downstream STS-1s) upon LOP-P
This READ/WRITE bit-field permits the user to configure the Transmit
SONET POH Processor block (within the corresponding channel) to
automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the LOP-P
defect.
0 – Does not configure the corresponding Transmit SONET POH
Processor block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the LOP-P
defect.
1 – Configures the corresponding Transmit SONET POH Processor
block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the LOP-P
defect.
5
Transmit AIS-P (via
Downstream STS-1s)
upon PLM-P
R/W
Transmit AIS-P (via Downstream STS-1s) upon PLM-P:
This READ/WRITE bit-field permits the user to configure the Transmit
SONET POH Processor block (within the corresponding channel) to
automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signal, anytime the Receive STS-1 POH
Processor block declares the PLM-P defect.
0 – Does not configure the corresponding Transmit SONET POH
Processor block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the PLM-P
defect.
1 – Configures the corresponding Transmit SONET POH Processor
block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the PLM-P
defect.
4
Transmit AIS-P (via
Downstream STS-1s)
upon
LCD-P
R/W
Transmit AIS-P (via Downstream STS-1s) upon LCD-P:
This READ/WRITE bit-field permits the user to configure the Transmit
STS-1 POH Processor block (within the corresponding channel) to
automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signal, anytime the Receive SONET POH
449
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AT
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Processor block declares the LCD-P defect.
0 – Does not configure the corresponding Transmit STS-1 POH
Processor block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signals, anytime the Receive SONET POH
Processor block declares the LCD-P defect.
1 – Configures the corresponding Transmit STS-1 POH Processor
block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signals, anytime the Receive SONET POH
Processor block declares the LCD-P defect.
3
Transmit AIS-P (via
Downstream STS-1s)
upon UNEQ-P
R/W
Transmit AIS-P (via Downstream STS-1s) upon UNEQ-P:
This READ/WRITE bit-field permits the user to configure the Transmit
SONET POH Processor block (within the corresponding channel) to
automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signal, (within the outbound STS-3 signal)
anytime the Receive STS-1 POH Processor block declares the UNEQP defect.
0 – Does not configure the corresponding Transmit SONET POH
Processor block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the UNEQP defect.
1 – Configures the corresponding Transmit SONET POH Processor
block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the UNEQP defect.
2
Transmit AIS-P (via
Downstream STS-1s)
upon TIM-P
R/W
Transmit AIS-P (via Downstream STS-1s) upon TIM-P:
This READ/WRITE bit-field permits the user to configure the Transmit
SONET POH Processor block (within the corresponding channel) to
automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the TIM-P
defect.
0 – Does not configure the corresponding Transmit SONET POH
Processor block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the TIM-P
defect.
1 – Configures the corresponding Transmit SONET POH Processor
block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the TIM-P
defect.
1
Transmit AIS-P (via
Downstream STS-1s)
upon AIS-P
R/W
Transmit AIS-P (via Downstream STS-1s) upon AIS-P:
This READ/WRITE bit-field permits the user to configure the Transmit
SONET POH Processor block (within the corresponding channel) to
automatically transmit the AIS-P (Path AIS) Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the AIS-P
defect.
0 – Does not configure the corresponding Transmit SONET POH
Processor block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal (within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the AIS-P
defect.
450
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
1 – Configures the corresponding Transmit SONET POH Processor
block to automatically transmit the AIS-P Indicator via the
“downstream” STS-1 signal A(within the outbound STS-3 signal),
anytime the Receive STS-1 POH Processor block declares the AIS-P
defect.
0
Unused
R/O
451
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 378: Receive STS-1 Path – Receive J1 Byte Capture Register (Address Location= 0xN1D3)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
J1_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
J1_Byte_Captured_Value[7:0]
R/O
DESCRIPTION
J1 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the J1 byte,
within the most recently received STS-1 frame.
This particular value is stored in this register for one STS-1
frame period. During the next STS-1 frame period, this value
will be overridden with a new J1 byte value.
Table 379: Receive STS-1 Path – Receive B3 Byte Capture Register (Address Location= 0xN1D7)
BIT 7
BIT 6
BIT 5
BIT 4
R/O
R/O
R/O
R/O
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/O
R/O
R/O
R/O
0
0
0
0
B3_Byte_Captured_Value[7:0]
BIT NUMBER
NAME
TYPE
7–0
B3_Byte_Captured_Value[7:0]
R/O
DESCRIPTION
B3 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the B3 byte,
within the most recently received STS-1 frame.
This particular value is stored in this register for one STS-1
frame period. During the next STS-1 frame period, this value
will be overridden with a new B3 byte value.
452
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 380: Receive STS-1 Path – Receive C2 Byte Capture Register (Address Location= 0xN1DB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
C2_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
C2_Byte_Captured_Value[7:0]
R/O
DESCRIPTION
C2 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the C2 byte,
within the most recently received STS-1 frame.
This particular value is stored in this register for one STS-1
frame period. During the next STS-1 frame period, this value
will be overridden with a new C2 byte value.
Table 381: Receive STS-1 Path – Receive G1 Byte Capture Register (Address Location= 0xN1DF)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
G1_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
G1_Byte_Captured_Value[7:0]
R/O
DESCRIPTION
G1 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the G1 byte,
within the most recently received STS-1 frame.
This particular value is stored in this register for one STS-1
frame period. During the next STS-1 frame period, this value
will be overridden with a new G1 byte value.
453
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 382: Receive STS-1 Path – Receive F2 Byte Capture Register (Address Location=0xN1E3)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
F2_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
F2_Byte_Captured_Value[7:0]
R/O
DESCRIPTION
F2 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the F2 byte,
within the most recently received STS-1 frame.
This particular value is stored in this register for one STS-1
frame period. During the next STS-1 frame period, this value
will be overridden with a new F2 byte value.
Table 383: Receive STS-1 Path – Receive H4 Byte Capture Register (Address Location= 0xN1E7)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
H4_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
H4_Byte_Captured_Value[7:0]
R/O
DESCRIPTION
H4 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the H4 byte,
within the most recently received STS-1 frame.
This particular value is stored in this register for one STS-1
frame period. During the next STS-1 frame period, this value
will be overridden with a new H4 byte value.
454
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 384: Receive STS-1 Path – Receive Z3 Byte Capture Register (Address Location= 0xN1EB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Z3_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Z3_Byte_Captured_Value[7:0]
R/O
DESCRIPTION
Z3 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the Z3 byte,
within the most recently received STS-1 frame.
This particular value is stored in this register for one STS-1
frame period. During the next STS-1 frame period, this value
will be overridden with a new Z3 byte value.
Table 385: Receive STS-1 Path – Receive Z4 (K3) Byte Capture Register (Address Location= 0xN1EF)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Z4(K3)_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Z4(K3)_Byte_Captured_Value[7:0]
R/O
DESCRIPTION
Z4 (K3) Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the Z4
(K3) byte, within the most recently received STS-1 frame.
This particular value is stored in this register for one STS-1
frame period. During the next STS-1 frame period, this
value will be overridden with a new Z4 (K3) byte value.
455
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 386: Receive STS-1 Path – Receive Z5 Byte Capture Register (Address Location= 0xN1F3)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Z5_Byte_Captured_Value[7:0]
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7–0
Z5_Byte_Captured_Value[7:0]
R/O
DESCRIPTION
Z5 Byte Captured Value[7:0]
These READ-ONLY bit-fields contain the value of the Z5 byte,
within the most recently received STS-1 frame.
This particular value is stored in this register for one STS-1
frame period. During the next STS-1 frame period, this value
will be overridden with a new Z5 byte value.
1.10
TRANSMIT ATM CELL PROCESSOR BLOCK
456
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
The register map for the Transmit ATM Cell Processor Block is presented in the Table below. Additionally, a
detailed description of each of the “Transmit ATM Cell Processor” block registers is presented below.
In order to provide some orientation for the reader, an illustration of the Functional Block Diagram for the
XRT94L33 device, with the “Transmit ATM Cell Processor Blocks “highlighted” is presented below in
Figure 9.
Figure 11: Illustration of the Functional Block Diagram of the XRT94L33 device, with the Transmit ATM
Cell Processor Block “High-lighted”.
From Channels 1 & 2
Tx
Tx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Rx
Rx
UTOPIA/
UTOPIA/
POS-PHY
POS-PHY
Interface
Interface
Block
Block
Clock
Clock
Synthesizer
Synthesizer
Block
Block
Tx
TxCell
Cell
Processor
Processor
Block
Block
Tx
TxPLCP
PLCP
Processor
Processor
Block
Block
Tx
TxPPP
PPP
Processor
Processor
Block
Block
Tx
TxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Tx
TxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Tx
TxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxPPP
PPP
Processor
Processor
Block
Block
Rx
RxDS3/E3
DS3/E3
Framer
Framer
Block
Block
Rx
RxDS3/E3
DS3/E3
Mapper
Mapper
Block
Block
Rx
RxSONET
SONET
POH
POH
Processor
Processor
Block
Block
Rx
RxCell
Cell
Processor
Processor
Block
Block
Rx
RxPLCP
PLCP
Processor
Processor
Block
Block
Channel 0
To Channel 1 & 2
457
Tx
TxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
Tx
TxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Tx
TxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Rx
RxSTS-3
STS-3
TOH
TOH
Processor
Processor
Block
Block
Clock
Clock&&
Data
Data
Recovery
Recovery
Block
Block
Rx
RxSTS-3
STS-3
Telecom
Telecom
Bus
BusBlock
Block
Rx
RxSTS-3
STS-3
PECL
PECL
I/F
I/FBlock
Block
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.10.1
Rev222...000...000
TRANSMIT ATM CELL PROCESSOR BLOCK REGISTER
Table 387: Transmit ATM Cell Processor Block Register Address Map
TRANSMIT ATM CELL PROCESSOR/ PPP PROCESSOR BLOCK REGISTERS
Note:
N represents the “Channel Number” and ranges in value from 0x02 to 0x04
0xNF00
Transmit ATM Cell Processor Control Register – Byte 3
0x00
0xNF01
Transmit ATM Cell Processor Control Register – Byte 2
0x00
0xNF02
Transmit ATM Cell Processor Control Register – Byte 1
0x00
0xNF03
Transmit ATM Cell/PPP Processor Control Register – Byte 0
0x00
0xNF04
Transmit ATM Status Register
0x00
Reserved
0x00
Transmit ATM Cell/PPP Processor Interrupt Status Register
0x00
Reserved
0x00
Transmit ATM Cell/PPP Processor Interrupt Enable Register
0x00
Reserved
0x00
0xNF13
Transmit ATM Cell Insertion/Extraction Memory Control Register
0x00
0xNF14
Transmit ATM Cell Insertion/Extraction Memory – Byte 3
0x00
0xNF15
Transmit ATM Cell Insertion/Extraction Memory – Byte 2
0x00
0xNF16
Transmit ATM Cell Insertion/Extraction Memory – Byte 1
0x00
0xNF17
Transmit ATM Cell Insertion/Extraction Memory – Byte 0
0x00
0xNF18
Transmit ATM Cell – Idle Cell Header Byte # 1 Register
0x00
0xNF19
Transmit ATM Cell – Idle Cell Header Byte # 2 Register
0x00
0xNF1A
Transmit ATM Cell – Idle Cell Header Byte # 3 Register
0x00
0xNF1B
Transmit ATM Cell – Idle Cell Header Byte # 4 Register
0x00
Reserved
0x00
0xNF1F
Transmit ATM Cell – Idle Cell Payload Byte Register
0x00
0xNF20
Transmit ATM Cell – Test Cell Header Byte # 1 Register
0x00
0xNF21
Transmit ATM Cell – Test Cell Header Byte # 2 Register
0x00
0xNF22
Transmit ATM Cell – Test Cell Header Byte # 3 Register
0x00
0xNF23
Transmit ATM Cell – Test Cell Header Byte # 4 Register
0x00
Reserved
0x00
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF05 –
0xNF0A
0xNF0B
0xNF0C –
0xNF0E
0xNF0F
0xNF10 –
0xNF12
0xNF1C –
0xNF1E
0xNF24 –
0xNF27
0xNF28
458
XRT94L33
333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
0xNF29
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF2A
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF2B
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
0xNF2C
Transmit ATM Cell – Discard Cell Count Register – Byte 3
0x00
0xNF2D
Transmit ATM Cell – Discard Cell Count Register – Byte 2
0x00
0xNF2E
Transmit ATM Cell – Discard Cell Count Register – Byte 1
0x00
0xNF2F
Transmit ATM Cell – Discard Cell Count Register – Byte 0
0x00
0xNF30
Transmit ATM Cell – HEC Byte Error Count Register – Byte 3
0x00
0xNF31
Transmit ATM Cell – HEC Byte Error Count Register – Byte 2
0x00
0xNF32
Transmit ATM Cell – HEC Byte Error Count Register – Byte 1
0x00
0xNF33
Transmit ATM Cell – HEC Byte Error Count Register – Byte 0
0x00
0xNF34
Transmit ATM Cell – Parity Error Count Register – Byte 3
0x00
0xNF35
Transmit ATM Cell – Parity Error Count Register – Byte 2
0x00
0xNF36
Transmit ATM Cell – Parity Error Count Register – Byte 1
0x00
0xNF37
Transmit ATM Cell – Parity Error Count Register – Byte 0
0x00
Reserved
0x00
0xNF43
Transmit ATM Controller – Transmit ATM Filter # 0 Control Register
0x00
0xNF44
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 1
0x00
0xNF45
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 2
0x00
0xNF46
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 3
0x00
0xNF47
Transmit ATM Controller – Transmit ATM Filter # 0 Pattern – Header Byte 4
0x00
0xNF48
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 1
0x00
0xNF49
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 2
0x00
0xNF4A
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 3
0x00
0xNF4B
Transmit ATM Controller – Transmit ATM Filter # 0 Check – Header Byte 4
0x00
0xNF4C
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF4D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF4E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF4F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF53
Transmit ATM Controller – Transmit ATM Filter # 1 Control Register
0x00
0xNF54
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 1
0x00
0xNF38 –
0xNF42
0xNF50 –
0xNF52
459
XRT94L33
333---C
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
0xNF55
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 2
0x00
0xNF56
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 3
0x00
0xNF57
Transmit ATM Controller – Transmit ATM Filter # 1 Pattern – Header Byte 4
0x00
0xNF58
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 1
0x00
0xNF59
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 2
0x00
0xNF5A
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 3
0x00
0xNF5B
Transmit ATM Controller – Transmit ATM Filter # 1 Check – Header Byte 4
0x00
0xNF5C
Transmit ATM Cell – Cell Count Register - Byte 3
0x00
0xNF5D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF5E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF5F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF63
Transmit ATM Controller – Transmit ATM Filter # 2 Control Register
0x00
0xNF64
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 1
0x00
0xNF65
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 2
0x00
0xNF66
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 3
0x00
0xNF67
Transmit ATM Controller – Transmit ATM Filter # 2 Pattern – Header Byte 4
0x00
0xNF68
Transmit ATM Controller – Transmit ATM Filter # 2 Check – Header Byte 1
0x00
0xNF69
Transmit ATM Controller – Transmit ATM Filter # 2 Check – Header Byte 2
0x00
0xNF6A
Transmit ATM Controller – Transmit ATM Filter # 2 Check – Header Byte 3
0x00
0xNF6B
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 4
0x00
0xNF6C
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF6D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF6E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF6F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF73
Transmit ATM Controller – Transmit ATM Filter # 3 Control Register
0x00
0xNF74
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 1
0x00
0xNF75
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 2
0x00
0xNF76
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 3
0x00
0xNF77
Transmit ATM Controller – Transmit ATM Filter # 3 Pattern – Header Byte 4
0x00
0xNF78
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 1
0x00
0xNF60 –
0xNF62
0xNF70 –
0xNF72
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A
N
N
E
L
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S
E
S
T
S
T
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S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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Rev222...000...000
0xNF79
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 2
0x00
0xNF7A
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 3
0x00
0xNF7B
Transmit ATM Controller – Transmit ATM Filter # 3 Check – Header Byte 4
0x00
0xNF7C
Transmit ATM Cell – Cell Count Register – Byte 3
0x00
0xNF7D
Transmit ATM Cell – Cell Count Register – Byte 2
0x00
0xNF7E
Transmit ATM Cell – Cell Count Register – Byte 1
0x00
0xNF7F
Transmit ATM Cell – Cell Count Register – Byte 0
0x00
Reserved
0x00
0xNF80 –
0xN102
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M
A
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P
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A
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R
E
G
S
T
E
R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
1.10.2
Rev222...000...000
TRANSMIT ATM CELL PROCESSOR BLOCK REGISTER DESCRIPTION
Table 388: Transmit ATM Cell Processor Block – Transmit ATM Control Register – Byte 3 (Address =
0xNF00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Table 389: Transmit ATM Cell Processor Block – Transmit ATM Control Register – Byte 2 (Address =
0xNF01)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit ATM Cell
Processor Enable
Unused
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-1
Unused
R/O
0
Transmit ATM Cell
Processor Enable
R/W
DESCRIPTION
Transmit ATM Cell Processor Block Enable:
This READ/WRITE bit-field permits the user to either enable or disable
the Transmit ATM Cell Processor block. If the user wishes to operate a
given Channel in the ATM Mode, then he/she must enable the Transmit
ATM Cell Processor Block.
0 – Disables the Transmit ATM Cell Processor Block
1 – Enables the Transmit ATM Cell Processor Block
Note:
The user must set this bit-field to “1” before he/she begins to
write ATM cell data into the Transmit UTOPIA Interface block.
462
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S
T
S
T
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S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 390: Transmit ATM Cell Processor Block – Transmit ATM Control Register – Byte 1 (Address =
0xNF02)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Test Cell
Transmit
Mode
Enable
ONE SHOT
MODE
GFC
Insertion
Enable - Bit
3
GFC
Insertion
Enable – Bit
2
GFC
Insertion
Enable – Bit
1
GFC
Insertion
Enable – Bit
0
COSET
Polynomial
Addition
Regenerate
HEC Byte
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
Test Cell Transmit
Mode Enable
R/W
DESCRIPTION
Test Cell Transmit Mode Enable:
This READ/WRITE bit-field permits the user to enable the Test Cell
Transmitter (within the Transmit ATM Cell Processor Block). The user
must implement this configuration option in order to perform diagnostic
operations with Test Cells.
0 – Disables the Test Cell Transmitter.
1 – Enables the Test Cell Transmitter.
Notes:
6
One Shot Mode
R/W
For normal operation, the user should set this bit-field to “1”.
One Shot Mode:
If the user has enabled the Test Cell Transmitter, then this
READ/WRITE bit-field permits the user to either configure the Test Cell
Transmitter into the “One-Shot” or in the “Continuous” Mode.
If the user configures the Test Cell Transmitter into the “One-Shot”
Mode, then (whenever the user implements a “0 to 1” transition within
Bit 7 [Test Cell Transmit Mode Enable] of this register) then the Test
Cell Transmitter will generate and transmit 1024 test cells. Afterwards,
the Test Cell Transmitter will halt its transmission of Test Cells until the
user implements another “0 to 1 transition” within Bit 7 (Test Cell
Transmit Mode Enable) within this register.
If the user configures the Test Cell Transmitter into the “Continuous”
Mode, then the Test Cell Transmitter will continuously generate and
transmit test cells for the duration that Bit 7(Test Cell Transmit Mode
Enable) is set to “1”.
0 – Configures the Test Cell Transmitter to operate in the “Continuous”
Mode.
1 – Configures the “Test Cell Transmitter” to operate in the “One-Shot”
Mode.
5
GFC Insertion
Enable – Bit 3
R/W
4
GFC Insertion
Enable – Bit 2
R/W
3
GFC Insertion
Enable – Bit 1
R/W
2
GFC Insertion
Enable – Bit 0
R/W
1
COSET Polynomial
Addition
R/W
COSET Polynomial Addition:
This READ/WRITE bit-field permits the user to configure the Transmit
ATM Cell Processor block to modulo-add the COSET Polynomial (e.g.,
x^6 + x^4 + x^2 + 1) to the HEC byte value, within each “outbound”
463
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S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
ATM cell.
0 – Configures the Transmit ATM Cell Processor block to NOT
modulo-add the COSET Polynomial to the HEC byte within each
outbound ATM cell.
1 – Configures the Transmit ATM Cell Processor block to modulo-add
the COSET Polynomial to the HEC byte within each outbound ATM
cell.
0
Regenerate HEC
Byte Enable
R/W
Regenerate HEC Byte Enable:
This READ/WRITE bit-field permits the user to configure the Transmit
ATM Cell Processor block to automatically re-compute and insert a
new HEC byte into each ATM cell (that it receives from the Transmit
UTOPIA Interface block) that contains an uncorrectable HEC byte.
0 – Does not configure the Transmit ATM Cell Processor block to
compute and insert a new HEC byte into ATM cells that contains an
“uncorrectable” HEC Byte error.
1 – Configures the Transmit ATM Cell Processor block to compute and
insert a new HEC byte into ATM cells that contains an “uncorrectable”
HEC Byte error.
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S
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S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 391: Transmit ATM Cell Processor Block – Transmit ATM Control – Byte 0 (Address = 0xNF03)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
HEC Byte
Invert
HEC Byte
Check
Enable
Transmit
UTOPIA
Parity
Check
Enable
Transmit
UTOPIA
Parity Error
– Discard
Transmit
UTOPIA –
ODD Parity
R/W
R/W
R/W
R/W
R/W
R/O
R/O
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7
HEC Byte Invert
R/W
HEC Byte Invert:
6
HEC Byte Check Enable
R/W
HEC Byte Check Enable:
BIT 2
BIT 1
BIT 0
Scrambler
Enable
Reserved
DESCRIPTION
This READ/WRITE bit-field permits the user to configure the
Transmit ATM Cell Processor block to perform HEC byte checking
of all ATM cells that it receives via the Transmit UTOPIA Interface
block.
0 – Configures the Transmit ATM Cell Processor block to NOT
perform HEC byte checking on all ATM cells that it receives via
the Transmit UTOPIA Interface block.
1 – Configures the Transmit ATM Cell Processor block to perform
HEC byte checking on all ATM cells that it receives via the
Transmit UTOPIA Interface block.
5
Transmit UTOPIA Parity
Check Enable
R/W
Transmit UTOPIA Parity Check Enable:
This READ/WRITE bit-field permits the user to either enable or
disable “Transmit UTOPIA Interface” Parity checking.
If the user enables “Transmit UTOPIA Interface” Parity Checking,
then the Transmit ATM Cell Processor block will compute either
the EVEN or ODD parity value (depending upon the setting of Bit
3 within this register) of each byte or 16-bit word that is input via
the Transmit UTOPIA Data Bus input pins: (TxUData[15:0]).
Afterwards, the Transmit ATM Cell Processor block will compare
this “locally computed” parity value with that which the ATM Layer
Processor has provided to the “TxUPrty” input pin. If the Transmit
ATM Cell Processor detects any discrepancies between these two
parity values (e.g., any parity errors) then it will take action based
upon the user’s settings for Bit 4 (Transmit UTOPIA Parity Error –
Discard).
0 – Disables “Transmit UTOPIA Interface” Parity Checking.
1 – Enables “Transmit UTOPIA Interface” Parity Checking.
4
Transmit UTOPIA Parity
Error - Discard
R/W
Transmit UTOPIA Parity Error – Discard Cell:
This READ/WRITE bit-field permits the user to configure the
Transmit ATM Cell Processor block to either discard or retain (for
further processing) any ATM cell that contains a “Transmit
UTOPIA Interface” parity error.
0 – Configures the Transmit ATM Cell Processor block to retain
(for further processing) all cells that contain “Transmit UTOPIA
Interface” parity errors.
1 – Configures the Transmit ATM Cell Processor block to discard
all cells that contain “Transmit UTOPIA Interface” parity errors.
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A
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T
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R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Notes:
3
Transmit UTOPIA – Odd
Parity
R/W
Rev222...000...000
This bit-field is only valid if “Transmit UTOPIA Interface”
Parity Checking has been enabled.
Transmit UTOPIA Parity Value – ODD Parity:
This READ/WRITE bit-field permits the user to configure the
Transmit ATM Cell Processor block to compute either the EVEN
or ODD parity value for each byte or 16-bit word within each cell
that it processes. Each of these parity values will ultimately be
compared with the value that is input via the “TxUPrty” input pin
(on the Transmit UTOPIA Interface block) coincident to when ATM
cell data is being applied to the “TxUData[15:0]” input pins.
0 – Configures the Transmit ATM Cell Processor block to compute
and verify the EVEN Parity value of each byte (or 16-bit word) of
ATM cell data that it processes.
1 – Configures the Transmit ATM Cell Processor block to compute
and verify the ODD Parity value of each byte (or 16-bit word) of
ATM cell data that it processes.
Notes:
2-1
Reserved
0
Scrambler Enable
This bit-field is only value if “Transmit UTOPIA Interface”
Parity Checking has been enabled.
R/O
Cell Payload Scrambler Enable:
This READ/WRITE bit-field permits the user to either enable or
disable the “Cell Payload Scrambler”. If the user enables the “Cell
Payload Scrambler” then the Transmit ATM Cell Processor will
payload self-synchronous scrambling on all cell payloads bytes
(within each outbound ATM cell) with the x^43+1 polynomial.
0 – Disables the Cell Payload Scrambler
1 – Enables the Cell Payload Scrambler
466
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N
N
E
L
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S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 392: Transmit ATM Cell Processor Block – Transmit ATM Status Register (Address = 0xNF04)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Unused
BIT 0
One Shot DONE
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-1
Unused
R/O
0
One Shot DONE
R/O
DESCRIPTION
One Shot DONE:
This READ-ONLY bit-field indicates whether or not the Test Cell
Transmitter has completed its transmission of 1024 test cells, following
the instant that the user has commanded the Test Cell to transmit this
burst of 1024 cells.
0 – Indicates that the Test Cell Transmitter has NOT completed its
transmission of 1024 test cells.
1 – Indicates that the Test Cell Transmitter has completed its
transmission of 1024 test cells since the last “Transmit Test Cell – One
Shot” command.
Notes:
1. This bit-field is only valid if (1) the Test Cell Transmitter is active
and (2) if the Test Cell Transmitter has been configured to operate in
the “One-Shot” Mode.
2. Once this bit-field has been set to “1”, it will remain at “1” until the
user executes another “Transmit Test Cell – One Shot” command.
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M
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A
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S
T
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R
S
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 393: Transmit ATM Cell Processor Block – Transmit ATM Interrupt Status Register (Address =
0xNF0B)
BIT 7
BIT 6
Unused
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit
Cell
Extraction
Interrupt
Status
Transmit
Cell Insertion
Interrupt
Status
Transmit
Cell
Extraction
Memory
Overflow
Interrupt
Status
Transmit
Cell Insertion
Memory
Overflow
Interrupt
Status
Detection of
HEC Byte
Error
Interrupt
Status
Detection of
Transmit
UTOPIA
Parity Error
Interrupt
Status
R/O
R/O
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
TYPE
7-6
Unused
R/O
5
Transmit Cell
Extraction Interrupt
Status
RUR
DESCRIPTION
Transmit Cell Extraction Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Transmit
Cell Extraction” interrupt has occurred since the last read of this
register.
The Transmit ATM Cell Processor block will generate the “Transmit Cell
Extraction” Interrupt anytime it receives an incoming ATM cell (from the
TxFIFO) and loads an ATM cell into the “Extraction Memory” Buffer.
0 – Indicates that the “Transmit Cell Extraction” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Transmit Cell Extraction” Interrupt has occurred
since the last read of this register.
4
Transmit Cell
Insertion Interrupt
Status
RUR
Transmit Cell Insertion Interrupt
This RESET-upon-READ bit-field indicates whether or not the “Transmit
Cell Insertion” interrupt has occurred since the last read of this register.
The Transmit ATM Cell Processor block will generate the “Transmit Cell
Insertion” Interrupt anytime a cell (residing in the Transmit Cell Insertion
Buffer) is read out of the “Transmit Cell Insertion Buffer” and is loaded
into the outbound ATM cell traffic.
0 – Indicates that the “Transmit Cell Insertion” Interrupt has NOT
occurred since the last read of this register.
1 – Indicates that the “Transmit Cell Insertion” Interrupt has occurred
since the last read of this register.
3
Transmit Cell
Extraction Memory
Overflow Interrupt
Status
RUR
Transmit Cell Extraction Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the “Transmit
Cell Extraction Memory Overflow” Interrupt has occurred since the last
read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime an overflow event has occurred in the “Transmit Cell Extraction
Memory” Buffer.
0 – Indicates that the Transmit ATM Cell Processor block has NOT
declared the “Transmit Cell Extraction Memory Overflow” Interrupt since
the last read of this register.
1 – Indicates that the Transmit ATM Cell Processor block has declared
the “Transmit Cell Extraction Memory Overflow” interrupt since the last
468
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333---C
C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
read of this register.
2
Transmit Cell
Insertion Memory
Overflow Interrupt
Status
RUR
Transmit Cell Insertion Memory Overflow Interrupt Status:
This RESET-upon-READ bit-field indicates whether or not the Transmit
Cell Insertion Memory Overflow” Interrupt has occurred since the last
read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime an overflow event has occurred in the “Transmit Cell Insertion
Memory” Buffer.
0 – Indicates that the Transmit ATM Cell Processor block has NOT
declared the “Transmit Cell Insertion Memory Overflow” interrupt since
the last read of this register.
1 – Indicates that the Transmit ATM Cell Processor block has declared
the “Transmit Cell Insertion Memory Overflow” interrupt since the last
read of this register.
1
Detection of HEC
Byte Error Interrupt
RUR
Detection of HEC Byte Error Interrupt:
This RESET-upon-READ bit-field indicates whether or not the “Transmit
ATM Cell Processor block” has declared the “Detection of HEC Byte
Error” Interrupt since the last read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime it has received an ATM cell (from the TxFIFO) that contains a
HEC byte error.
0 – Indicates that the Transmit ATM Cell Processor block has NOT
declared the “Detection of HEC Byte Error” Interrupt since the last read
of this register.
1 – Indicates that the Transmit ATM Cell Processor block has declared
the “Detection of HEC Byte Error” Interrupt since the last read of this
register.
0
Detection of Transmit
UTOPIA Parity Error
Interrupt
Detection of Transmit UTOPIA Parity Error Interrupt:
This RESET-upon-READ bit-field indicates whether or not the “Transmit
ATM Cell Processor” block has declared the “Detection of Transmit
UTOPIA Parity Error” Interrupt since the last read of this register.
The Transmit ATM Cell Processor block will generate this interrupt
anytime it has received an ATM cell byte or 16-bit word (from the
Transmit UTOPIA Interface block) that contains a parity error.
0 – Indicates that the Transmit ATM Cell Processor block has NOT
declared the “Detection of Transmit UTOPIA Parity Error” Interrupt
since the last read of this register.
1 – Indicates that the Transmit ATM Cell Processor block has declared
the “Detection of Transmit UTOPIA Parity Error” Interrupt since the last
read of this register.
469
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N
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M---111 M
MA
AP
PP
PE
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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ER
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HA
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NE
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Rev222...000...000
Table 394: Transmit ATM Cell Processor Block – Transmit ATM Interrupt Enable Register (Address =
0xNF0F)
BIT 7
BIT 6
Unused
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit
Cell
Extraction
Interrupt
Enable
Transmit
Cell Insertion
Interrupt
Enable
Transmit
Cell
Extraction
Memory
Overflow
Interrupt
Enable
Transmit
Cell Insertion
Memory
Overflow
Interrupt
Enable
Detection of
HEC Byte
Error
Interrupt
Enable
Detection of
Transmit
UTOPIA
Parity Error
Interrupt
Enable
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT NUMBER
NAME
7-6
Unused
5
Transmit Cell
Extraction
Interrupt Enable
TYPE
DESCRIPTION
R/W
Transmit Cell Extraction Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Transmit Cell Extraction” Interrupt.
If the user enables this feature, then the Transmit ATM Cell Processor block
will generate the “Transmit Cell Extraction” Interrupt anytime it receives an
incoming ATM cell (from the TxFIFO) and loads this ATM cell into the
“Transmit Extraction Memory” Buffer.
0 – Disables the “Transmit Cell Extraction” Interrupt.
1 – Enables the “Transmit Cell Extraction” Interrupt
4
Transmit Cell
Insertion
Interrupt Enable
R/W
Transmit Cell Insertion Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Transmit Cell Insertion” Interrupt.
If the user enables this feature, then the Transmit ATM Cell Processor block
will generate the “Transmit Cell Insertion” Interrupt anytime a cell (residing in
the “Transmit Cell Insertion” Buffer) is read out of the “Transmit Cell
Insertion” Buffer and is loaded into the “outbound” ATM cell traffic.
0 – Disables the Transmit Cell Insertion Interrupt.
1 – Enables the Transmit Cell Insertion Interrupt.
3
Transmit Cell
Extraction
Memory
Overflow
Interrupt Enable
R/W
Transmit Cell Extraction Memory Overflow Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Transmit Cell Extraction Memory Overflow” Interrupt.
If the user enables this interrupt, then the Transmit ATM Cell Processor block
will generate an interrupt any time an overflow event has occurred in the
“Transmit Cell Extraction Memory” buffer.
0 – Disables the Transmit Cell Extraction Memory Overflow Interrupt.
1 – Enables the Transmit Cell Extraction Memory Overflow Interrupt.
2
Transmit Cell
Insertion
Memory
Overflow
Interrupt Enable
R/W
Transmit Cell Insertion Memory Overflow Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Transmit Cell Insertion Memory Overflow” Interrupt.
If the user enables this interrupt, then the Transmit ATM Cell Processor block
will generate an interrupt any time an overflow event has occurred in the
“Transmit Cell Insertion Memory” buffer.
470
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A
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A
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E
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HA
AN
NN
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LD
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S333///E
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ST
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S---111 T
TO
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ST
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S---333///S
ST
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M---111 M
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MR
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EG
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Rev222...000...000
0 – Disables the Transmit Cell Insertion Memory Overflow Interrupt.
1 – Enables the Transmit Cell Insertion Memory Overflow Interrupt.
1
Detection of
HEC Byte Error
Interrupt Enable
R/W
Detection of HEC Byte Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of HEC Byte Error Interrupt” within the Transmit ATM Cell
Processor Block.
If the user enables this interrupt, then the Transmit ATM Cell Processor block
will generate an interrupt each time it receives an ATM cell (from the
TxFIFO) that contains a HEC Byte error.
0 – Disables the “Detection of HEC Byte Error” Interrupt.
1 – Enables the “Detection of HEC Byte Error” Interrupt
0
Detection of
Transmit
UTOPIA Parity
Error Interrupt
Enable
Detection of Transmit UTOPIA Parity Error Interrupt Enable:
This READ/WRITE bit-field permits the user to either enable or disable the
“Detection of Transmit UTOPIA Parity Error” Interrupt within the Transmit
ATM Cell Processor block.
If the user enables this interrupt, then the Transmit ATM Cell Processor block
will generate an interrupt each time it receives an ATM cell byte or 16-bit
word (from the TxFIFO) that contains a parity error.
0 – Disables the “Detection of Transmit UTOPIA Parity Error” Interrupt.
1 – Enables the “Detection of Transmit UTOPIA Parity Error” Interrupt.
471
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R
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C
H
A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
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S---111 T
TO
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ST
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S---333///S
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Rev222...000...000
Table 395: Transmit ATM Cell Processor Block – Transmit ATM Cell Insertion/Extraction Memory
Control Register (0xNF13)
BIT 7
BIT 6
BIT 5
Unused
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Transmit Cell
Extraction
Memory
RESET*
Transmit Cell
Extraction
Memory
CLAV
Transmit Cell
Insertion
Memory
RESET*
Transmit Cell
Insertion
Memory
ROOM
Transmit Cell
Insertion
Memory
WSOC
R/O
R/O
R/O
R/W
R/O
R/W
R/O
W/O
0
0
0
1
0
1
0
0
BIT NUMBER
NAME
7-5
Unused
4
Transmit Cell Extraction
Memory RESET*
TYPE
R/W
DESCRIPTION
Transmit Cell Extraction Memory RESET*:
This READ/WRITE bit-field permits the user to perform a REST
operation to the Transmit Cell Extraction Memory.
If the user writes a “1-to-0 transition” into this bit-field, then the
following events will occur.
•
All of the contents of the Transmit Cell Extraction Memory will
be flushed.
•
All READ and WRITE pointers will be reset to their default
positions.
Notes:
3
Transmit Cell Extraction
Memory CLAV
R/O
Following this RESET event, the user must write the
value “1” into this bit-field in order to enable normal
operation within the Transmit Cell Extraction Memory.
Transmit Cell Extraction Memory – Cell Available Indicator:
This READ-ONLY bit-field indicates whether or not there is at least
ATM cell of data (residing within the Transmit Cell Extraction
Memory) that needs to be read out via the Microprocessor
Interface.
0 – Indicates that the Transmit Cell Extraction Memory is empty
and contains no ATM cell data.
1 – Indicates that the Transmit Cell Extraction Memory contains at
least one ATM cell of data that needs to be read out.
Notes:
2
Transmit Cell Insertion
Memory RESET*
R/W
The user should validate each ATM cell that is being
read out from the Transmit Cell Extraction memory by
checking the state of this bit-field prior to reading out the
contents of ATM cell data residing within the Transmit
Cell Extraction Memory
Transmit Cell Insertion Memory RESET*:
This READ/WRITE bit-field permits the user to perform a RESET
operation to the Transmit Cell Insertion Memory.
If the user writes a “1-to-0 transition” into this bit-field, then the
following events will occur.
•
All of the contents of the Transmit Cell Insertion Memory will
be flushed.
•
All READ and WRITE pointers will be reset to their default
positions.
Notes:
472
Following this RESET event, the user must write the
value “1” into this bit-field in order to enable normal
XRT94L33
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M
A
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AN
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S333///E
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ST
TS
S---111 T
TO
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ST
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S---333///S
ST
TM
M---111 M
MA
AP
PP
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R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
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ER
RS
S
operation of the Transmit Cell Insertion Memory.
1
Transmit Cell Insertion
Memory ROOM
R/O
Transmit Cell Insertion Memory – ROOM Indicator:
This READ-ONLY bit-field indicates whether or not there is room
(e.g., empty space) available for the contents of another ATM cell
to be written into the Transmit Cell Insertion Memory.
0 – Indicates that the Transmit Cell Insertion Memory does not
contain enough empty space to receive another ATM cell via the
Microprocessor Interface.
1 – Indicates that the Transmit Cell Insertion Memory does contain
enough empty space to receive another ATM cell via the
Microprocessor Interface.
Notes:
0
Transmit Cell Insertion
Memory WSOC
W/O
The user should verify that the Transmit Cell Insertion
Memory has sufficient empty space to accept another
ATM cell of data (via the Microprocessor Interface) by
polling the state of this bit-field prior to writing each cell
into the Transmit Cell Insertion Memory.
Transmit Cell Insertion Memory – Write SOC (Start of Cell):
Whenever the user is writing the contents of an ATM cell into the
Transmit Cell Insertion Memory, then he/she is suppose to
identify/designate the very first byte of this ATM cell by setting this
bit-field to “1”. Whenever the user does this, then the Transmit Cell
Insertion Memory will “know” that the next octet that is written into
the “Transmit ATM Cell Processor Block – Transmit Cell
Insertion/Extraction Memory Data Register – Byte 3 (Address =
0xNF14) is designated as the first byte of the ATM cell currently
being written into the Transmit Cell Insertion Memory.
This bit-field must be set to “0” during all other WRITE operations
to the Transmit ATM Cell Processor – Transmit Cell
Insertion/Extraction Memory Data Register
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
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ST
TS
S---333///S
ST
Rev222...000...000
Table 396: Transmit ATM Cell Processor Block – Transmit Cell Insertion/Extraction Memory Data –
Byte 3 (Address = 0xNF14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit Cell Insertion/Extraction Memory Data[31:24]
BIT NUMBER
NAME
TYPE
7-0
Transmit Cell
Insertion/Extraction
Memory Data[31:24]
R/W
DESCRIPTION
Transmit Cell Insertion/Extraction Memory Data[31:24]:
These READ/WRITE bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory Data – Bytes 2 through 0” support the following functions.
•
They function as the address location for the user to write the
contents of an “outbound” ATM cell into the Transmit Cell
Insertion Memory, via the Microprocessor Interface.
•
They function as the address location, for which the user to
read out the contents of an “inbound” ATM cell from the
Receive Cell Extraction Memory, via the Microprocessor
Interface.
Notes:
1. If the user performs a WRITE operation to this (and the other
three address locations), then he/she is writing ATM cell data into
the Transmit Cell Insertion Memory.
2. If the user performs a READ operation to this (and the other
three address locations), then he/she is reading ATM cell data from
the Transmit Cell Extraction Memory.
3. READ and WRITE operations must be performed in a “32-bit” (4byte “word”) manner. Hence, whenever the user performs a
READ/WRITE operation to these address locations, he/she must
start by writing in or reading out the first byte (of this “4-byte” word)
of a given ATM cell, into/from this particular address location.
Next, the user must perform the READ/WRITE operation (with the
second of this “4-byte” word) to the “Transmit ATM Cell Processor
Block – Transmit Cell Insertion/Extraction Memory – Byte 2
register. Afterwards, the user must perform a READ/WRITE
operation (with the third of this “4-byte” word) to the Transmit ATM
Cell Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 1 register. Finally, the user must perform a READ/WRITE
operation (with the fourth of this “4-byte” word) to the Transmit ATM
Cell Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 0 register. When reading out (writing in) the next four bytes of
a given ATM Cell, the user must repeat this process with a READ
or WRITE operation, from/to this register location, and so on.
4. Whenever the user is writing cell data into the Transmit Cell
Insertion Memory, the size of the Cell is always 56 bytes.
5. Whenever the user is reading cell data from the Transmit Cell
Extraction Memory, the size of the Cell is always 56 bytes.
474
XRT94L33
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S
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M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 397: Transmit ATM Cell Processor Block – Transmit Cell Insertion/Extraction Memory Data –
Byte 2 (Address = 0xNF15)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit Cell Insertion/Extraction Memory Data[23:16]
BIT NUMBER
NAME
TYPE
7-0
Transmit Cell
Insertion/Extraction Memory
Data[23:16]
R/W
DESCRIPTION
Transmit Cell Insertion/Extraction Memory Data[23:16]:
These READ/WRITE bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory Data – Bytes 3, 1 and 0” support the following functions.
They function as the address location for the user to write the
contents of an “outbound” ATM cell into the Transmit Cell
Insertion Memory, via the Microprocessor Interface.
They function as the address location, for which the user to read
out the contents of an “inbound” ATM cell from the Receive Cell
Extraction Memory, via the Microprocessor Interface.
Notes:
1. If the user performs a WRITE operation to this (and the other
three address locations), then he/she is writing ATM cell data
into the Transmit Cell Insertion Memory.
2. If the user performs a READ operation to this (and the other
three address locations), then he/she is reading ATM cell data
from the Transmit Cell Extraction Memory.
3. READ and WRITE operations must be performed in a “32-bit”
(4-byte “word”) manner. Hence, whenever the user performs a
READ/WRITE operation to these address locations, he/she must
start by writing in or reading out the first byte (of this “4-byte”
word) of a given ATM cell, into/from the Transmit ATM Cell
Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 3” register. Next, the user must perform the READ/WRITE
operation (with the second of this “4-byte” word) to this particular
address location. Afterwards, the user must perform a
READ/WRITE operation (with the third of this “4-byte” word) to
the Transmit ATM Cell Processor Block – Transmit Cell
Insertion/Extraction Memory – Byte 1 register. Finally, the user
must perform a READ/WRITE operation (with the fourth of this
“4-byte” word) to the Transmit ATM Cell Processor Block –
Transmit Cell Insertion/Extraction Memory – Byte 0 register.
When reading out (writing in) the next four bytes of a given ATM
Cell, the user must repeat this process with a READ or WRITE
operation, from/to this register location, and so on.
4. Whenever the user is writing cell data into the Transmit Cell
Insertion Memory, the size of the Cell is always 56 bytes.
5. Whenever the user is reading cell data from the Transmit Cell
Extraction Memory, the size of the Cell is always 56 bytes.
475
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A
N
N
E
L
D
S
E
S
T
S
T
O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 398: Transmit ATM Cell Processor Block – Transmit Cell Insertion/Extraction Memory Data –
Byte 1 (Address = 0xNF16)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit Cell Insertion/Extraction Memory Data[15:8]
BIT NUMBER
NAME
TYPE
7-0
Transmit Cell
Insertion/Extraction Memory
Data[15:8]
R/W
DESCRIPTION
Transmit Cell Insertion/Extraction Memory Data[15:8]:
These READ/WRITE bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory Data – Bytes 3, 2 and 0” support the following functions.
•
They function as the address location for the user to write
the contents of an “outbound” ATM cell into the Transmit
Cell Insertion Memory, via the Microprocessor Interface.
•
They function as the address location, for which the user to
read out the contents of an “inbound” ATM cell from the
Receive Cell Extraction Memory, via the Microprocessor
Interface.
Notes:
1. If the user performs a WRITE operation to this (and the other
three address locations), then he/she is writing ATM cell data
into the Transmit Cell Insertion Memory.
2. If the user performs a READ operation to this (and the other
three address locations), then he/she is reading ATM cell data
from the Transmit Cell Extraction Memory.
3. READ and WRITE operations must be performed in a “32-bit”
(4-byte “word”) manner. Hence, whenever the user performs a
READ/WRITE operation to these address locations, he/she must
start by writing in or reading out the first byte (of this “4-byte”
word) of a given ATM cell, into/from the Transmit ATM Cell
Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 3 register. Next, the user must perform the READ/WRITE
operation (with the second of this “4-byte” word) to the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory – Byte 2 register. Afterwards, the user must perform a
READ/WRITE operation (with the third of this “4-byte” word) to
this particular register location. Finally, the user must perform a
READ/WRITE operation (with the fourth of this “4-byte” word) to
the Transmit ATM Cell Processor Block – Transmit Cell
Insertion/Extraction Memory – Byte 0 register. When reading out
(writing in) the next four bytes of a given ATM Cell, the user must
repeat this process with a READ or WRITE operation, from/to
this register location, and so on.
4. Whenever the user is writing cell data into the Transmit Cell
Insertion Memory, the size of the Cell is always 56 bytes.
5. Whenever the user is reading cell data from the Transmit Cell
Extraction Memory, the size of the Cell is always 56 bytes.
476
XRT94L33
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N
E
L
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T
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S
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S
T
M
M
A
P
P
E
R
A
T
M
R
E
G
S
T
E
R
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
Rev222...000...000
Table 399: Transmit ATM Cell Processor Block – Transmit Cell Insertion/Extraction Memory Data –
Byte 0 (Address = 0xNF17)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
0
0
0
Transmit Cell Insertion/Extraction Memory Data[7:0]
BIT NUMBER
NAME
TYPE
7-0
Transmit Cell
Insertion/Extraction
Memory Data[7:0]
R/W
DESCRIPTION
Transmit Cell Insertion/Extraction Memory Data[7:0]:
These READ/WRITE bit-fields, along with that in the “Transmit
ATM Cell Processor Block – Transmit Cell Insertion/Extraction
Memory Data – Bytes 3, through 1” support the following functions.
•
They function as the address location for the user to write the
contents of an “outbound” ATM cell into the Transmit Cell
Insertion Memory, via the Microprocessor Interface.
•
They function as the address location, for which the user to
read out the contents of an “inbound” ATM cell from the
Receive Cell Extraction Memory, via the Microprocessor
Interface.
Notes:
1. If the user performs a WRITE operation to this (and the other
three address locations), then he/she is writing ATM cell data into
the Transmit Cell Insertion Memory.
2. If the user performs a READ operation to this (and the other
three address locations), then he/she is reading ATM cell data from
the Transmit Cell Extraction Memory.
3. READ and WRITE operations must be performed in a “32-bit” (4byte “word”) manner. Hence, whenever the user performs a
READ/WRITE operation to these address locations, he/she must
start by writing in or reading out the first byte (of this “4-byte” word)
of a given ATM cell, into/from the Transmit ATM Cell Processor
Block – Transmit Cell Insertion/Extraction Memory – Byte 3
register. Next, the user must perform the READ/WRITE operation
(with the second of this “4-byte” word) to the “Transmit ATM Cell
Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 2 register. Afterwards, the user must perform a READ/WRITE
operation (with the third of this “4-byte” word) to the “Transmit ATM
Cell Processor Block – Transmit Cell Insertion/Extraction Memory –
Byte 1” register. Finally, the user must perform a READ/WRITE
operation (with the fourth of this “4-byte” word) to this particular
register location. When reading out (writing in) the next four bytes
of a given ATM Cell, the user must repeat this process with a
READ or WRITE operation, from/to this register location, and so
on.
4. Whenever the user is writing cell data into the Transmit Cell
Insertion Memory, the size of the Cell is always 56 bytes.
5. Whenever the user is reading cell data from the Transmit Cell
Extraction Memory, the size of the Cell is always 56 bytes.
477
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A
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N
E
L
D
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T
S
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O
S
T
S
TM
M---111 M
MA
AP
PP
PE
ER
R ––– A
AT
TM
MR
RE
EG
GIIIS
ST
TE
ER
RS
S
CH
HA
AN
NN
NE
EL
LD
DS
S333///E
E333///S
ST
TS
S---111 T
TO
OS
ST
TS
S---333///S
ST
Rev222...000...000
Table 400: Transmit ATM Cell Processor Block – Transmit ATM Idle Cell Header Byte 1 (Address =
0xNF18)
BIT 7
BIT 6
BIT 5
BIT 4
R/W
R/W
R/W
R/W
0
0
0
0
BIT 3
BIT 2
BIT 1
BIT 0
R/W
R/W
R/W
R/W
0
0
0
0
Transmit Idle Cell Header Byte 1 [7:0]
BIT NUMBER
NAME
TYPE
DESCRIPTION
7–0
Transmit Idle Cell
Header Byte – 1 [7:0]
R/W
Transmit Idle Cell Header Byte – 1[7:0]:
These READ/WRITE register bits, along with that in “Transmit ATM
Cell Processor Block – Transmit ATM Idle