GS1578A HD-LINX® II Multi-Rate Dual Slew-Rate Cable Driver GS1578A Data Sheet Features Description • SMPTE 292M, SMPTE 344M and SMPTE 259M compliant • Dual coaxial cable driving outputs with selectable slew rate The GS1578A is a second generation high-speed BiCMOS integrated circuit designed to drive one or two 75Ω co-axial cables. • 50Ω differential PECL input • Pb-free and RoHS compliant • Seamless interface to other HD-LINX® II family products • Single 3.3V power supply operation • Operating temperature range: 0°C to 70°C Applications • SMPTE 292M, SMPTE 344M and SMPTE 259M Coaxial Cable Serial Digital Interfaces. The GS1578A may drive data rates up to 1.485Gb/s and provides two selectable slew rates in order to achieve compliance to SMPTE 259M, SMPTE 344M and SMPTE 292M. The GS1578A accepts a LVPECL level differential input that may be AC coupled. External biasing resistors at the inputs are not required. Power consumption is typically 168mW using a 3.3V power supply. The GS1578A is Pb-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous subcomponents are RoHS compliant. BANDGAP REFERENCE AND BIASING CIRCUIT SDI INPUT DIFFERENTIAL PAIR RSET SDO OUTPUT STAGE & CONTROL SDI SDO SD/HD Functional Block Diagram 33657 - 4 March 2006 1 of 15 www.gennum.com GS1578A Data Sheet Contents Features ........................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................3 1.1 Pin Assignment ...............................................................................................3 1.2 Pin Descriptions ..............................................................................................3 2. Electrical Characteristics ...........................................................................................4 2.1 Absolute Maximum Ratings ............................................................................4 2.2 Solder Reflow Profiles .....................................................................................4 2.3 DC Electrical Characteristics ..........................................................................5 2.4 AC Electrical Characteristics ...........................................................................6 3. Input / Output Circuits ...............................................................................................7 4. Detailed Description ..................................................................................................8 4.1 Input Interfacing ..............................................................................................8 4.2 Output Interfacing ...........................................................................................8 4.3 Output Return Loss Measurement ................................................................11 4.4 Output Amplitude (RSET) .............................................................................11 5. Application Information............................................................................................12 5.1 PCB Layout ...................................................................................................12 5.2 Typical Application Circuit .............................................................................12 6. Package & Ordering Information .............................................................................13 6.1 Package Dimensions ....................................................................................13 6.2 Recommended PCB Footprint ......................................................................14 6.3 Packaging Data .............................................................................................14 6.4 Ordering Information .....................................................................................14 7. Revision History ......................................................................................................15 33657 - 4 March 2006 2 of 15 GS1578A Data Sheet 1. Pin Out SDI 1 SDI 2 NC NC NC NC 1.1 Pin Assignment 16 15 14 13 12 SDO 11 SDO GS1578A (top view) VEE 3 10 SD / HD RSET 4 9 VCC 8 NC NC NC 7 NC 6 5 Center Pad (bottom of package) Figure 1-1: 16-Pin QFN 1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number Name Timing Type Description 1,2 SDI, SDI Analog Input Serial digital differential input. 3 VEE – Power Most negative power supply connection. Connect to GND. 4 RSET Analog Input External output amplitude control resistor. 5,6,7,8,13,14, 15,16 NC – – No Connect. Not bonded internally. 9 VCC – Power Most positive power supply connection. Connect to +3.3V. 10 SD/HD Non Synchronous Input Output slew rate control. When set HIGH, the output will meet SMPTE 259M rise/fall time specifications. When set LOW, the serial outputs will meet SMPTE 292M rise/fall time specifications. 11,12 SDO, SDO Analog Output Serial digital differential output. – Center Pad – Power Connect to most negative power supply plane following the recommendations in Recommended PCB Footprint on page 14. 33657 - 4 March 2006 3 of 15 GS1578A Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Value Supply Voltage -0.5V to 3.6 VDC Input ESD Voltage 2kV Storage Temperature Range -50°C < Ts < 125°C Input Voltage Range (any input) -0.3 to (VCC +0.3)V Operating Temperature Range 0°C to 70°C Solder Reflow Temperature 260°C 2.2 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-1.The recommended standard Pb reflow profile is shown in Figure 2-2. Temperature 60-150 sec. 20-40 sec. 260˚C 250˚C 3˚C/sec max 217˚C 6˚C/sec max 200˚C 150˚C 25˚C Time 60-180 sec. max 8 min. max Figure 2-1: Maximum Pb-free Solder Reflow Profile (Preferred) 33657 - 4 March 2006 4 of 15 GS1578A Data Sheet 60-150 sec. Temperature 10-20 sec. 230˚C 220˚C 3˚C/sec max 183˚C 6˚C/sec max 150˚C 100˚C 25˚C Time 120 sec. max 6 min. max Figure 2-2: Standard Pb Reflow Profile (Pb-free package) 2.3 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Supply Voltage VCC – 3.135 3.3 3.465 V Power Consumption PD TA = 25°C – 168 – mW Supply Current Is TA = 25°C – 51 64 mA Output Voltage VCMOUT Common mode – VCC - VOUT – V Input Voltage VCMIN Common mode 1.6 + ΔVSDI/2 – VCC - ΔVSDI/2 V SD/HD Input VIH – 2.4 – – V VIL – – – 0.8 V 33657 - 4 March 2006 5 of 15 GS1578A Data Sheet 2.4 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VDD = 3.3V, TA = 0°C to 70°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Notes Serial input data rate DRSDO – – – 1.485 Gb/s 1 Additive jitter – 1.485Gb/s – 22 – psp-p – – 270Mb/s – 20 – psp-p – tr, tf SD/HD=0 – – 220 ps 2 tr, tf SD/HD=1 400 – 800 ps 2 Mismatch in rise/fall time Utr, Utf – – – 30 ps – Duty cycle distortion – SD/HD=0 – – 30 ps – – SD/HD=1 – – 100 ps – – SD/HD=0 – – 10 % – – SD/HD=1 – – 8 % – Output Return Loss ORL – 15 – – dB – Output Voltage Swing VOUT Single Ended into 75Ω external load 750 800 850 mVp-p – 300 – 2000 mVp-p – Rise/Fall time Overshoot RSET = 750Ω Input Voltage Swing UVSDI Differential NOTES: 1. The input coupling capacitor must be set accordingly for lower data rates. 2. Rise/Fall time measured between 20% and 80%. 33657 - 4 March 2006 6 of 15 GS1578A Data Sheet 3. Input / Output Circuits VCC SDI SDI VCC 10k 5k 10k 10k Figure 3-1: Differential Input Stage (SDI/SDI) Vcc SDO SDO IREF Figure 3-2: Differential Output Stage (SDO/SDO) VCC On Chip Reference SD/HD Figure 3-3: Slew Rate Select Input Stage 33657 - 4 March 2006 7 of 15 GS1578A Data Sheet 4. Detailed Description 4.1 Input Interfacing SDI/SDI are high impedance differential inputs. The equivalent input circuit is shown in Figure 3-1. Several conditions must be observed when interfacing to these inputs: • The differential input signal amplitude must be between 300 and 2000mVpp. • The common mode voltage range must be as specified in the DC Electrical Characteristics on page 5. • For input trace lengths longer than approximately 1cm, the inputs should be terminated as shown in the Typical Application Circuit. The GS1578A inputs are self-biased, allowing for simple AC coupling to the device. For serial digital video, a minimum capacitor value of 4.7µF should be used to allow coupling of pathological test signals. A tantalum capacitor is recommended. SD/HD Input Pin The GS1578A SDO rise and fall times can be set to comply with both SMPTE 259M/344M and SMPTE 292M. For all SMPTE 259M standards, or any data rate that requires longer rise and fall time characteristics, the SD/HD pin must be set HIGH by the application layer. For SMPTE 292M standards and signals which require faster rise and fall times, this pin should be set LOW. 4.2 Output Interfacing The GS1578A outputs are current mode, and will drive 800mV into a 75Ω load. These outputs are protected from accidental static damage with internal static protection diodes. The SMPTE 292M, SMPTE 344M and SMPTE 259M standards require that the output of a cable driver have a source impedance of 75Ω and a return loss of at least 15dB between 5MHz and 1.485GHz. In order for an SDI output circuit using the GS1578A to meet this specification, the output application circuit shown in Typical Application Circuit on page 12 is recommended. The value of LCOMP will vary depending on the PCB layout, with a typical value of 5.6nH. A 4.7µF capacitor is used for AC coupling the output of the device. This value is chosen to ensure that pathological signals can be coupled without a significant DC component occurring. Please see Application Information on page 12 for more details. 33657 - 4 March 2006 8 of 15 GS1578A Data Sheet Figure 4-1: Output signal for 270Mb/s input Figure 4-2: Output signal for 1.485Gb/s input 33657 - 4 March 2006 9 of 15 GS1578A Data Sheet The output protection diodes act as a varactor (voltage controlled capacitor) as shown in Figure 4-3. Therefore, when measuring return loss at the GS1578A output, it is necessary to take the measurement for both a logic high and a logic low output condition. Consequently, the output capacitance of the device is dependent on the logic state of the output. GS1578A SDO SDO Figure 4-3: Static Protection Diodes 33657 - 4 March 2006 10 of 15 GS1578A Data Sheet 4.3 Output Return Loss Measurement To perform a practical return loss measurement, it is necessary to force the GS1578A output to a DC high or low condition. The actual measured return loss will be based on the outputs being static at VCC or VCC-1.6V. Under normal operating conditions the outputs of the device swing between VCC-0.4V and VCC-1.2V, so the measured value of return loss will not represent the actual operating return loss. A simple method of calculating the values of actual operating return loss is to interpolate the two return loss measurements. In this way, the values of return loss are estimated at VCC-0.4V and VCC-1.2V based on the measurements at VCC and VCC-1.6V. The two values of return loss (high and low) will typically differ by several decibels. If the measured return loss is RH for logic high and RL for logic low, then the two values can be interpolated as follows: RIH = RH- (RH-RL)/4 and RIL = RL+(RH-RL)/4 where RIH is the interpolated logic high value and RIL is the interpolated logic low value. For example, if RH = -18dB and RL = -14dB, then the interpolated values are RIH = -17dB and RIL = -15dB. 4.4 Output Amplitude (RSET) The output amplitude of the GS1578A is set to 800mVp-p with a tolerance of ±7% using an RSET resistor of 750Ω. A ±1% SMT resistor should be used. The RSET resistor is part of the high speed output circuit of the GS1578A. The resistor should be placed as close as possible to the RSET pin. In addition, the PCB capacitance should be minimized at this node by removing the PCB groundplane beneath the RSET resistor and the RSET pin. NOTE: Only an RSET value of 750Ω ±1% should be used. Using other values for RSET is not recommended. 33657 - 4 March 2006 11 of 15 GS1578A Data Sheet 5. Application Information 5.1 PCB Layout Special attention must be paid to component layout when designing serial digital interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: • The PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to changes in trace impedance. • The PCB groundplane is removed under the GS1578A output components to minimize parasitic capacitance. • The PCB ground plane is removed under the GS1578A RSET pin and resistor to minimize parasitic capacitance. • Input and output BNC connectors are surface mounted in-line to eliminate a transmission line stub caused by a BNC mounting via high speed traces which are curved to minimize impedance variations due to change of PCB trace width. 5.2 Typical Application Circuit * 5.6n 75 4u7 49.9 DIFFERENTIAL DATA INPUT 10n 1 2 3 4 49.9 GS1578A SDI SDI VEE RSET SDO SDO SD/HD VCC 12 11 10 9 75 75 VCC 750 VCC 10n 75 * 5.6n 4u7 BNC 4u7 BNC 4u7 * TYPICAL VALUE: VARIES WITH LAYOUT VCC 10n SD/HD NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted. Figure 5-1: Typical Application Circuit 33657 - 4 March 2006 12 of 15 GS1578A Data Sheet 6. Package & Ordering Information 6.1 Package Dimensions A 2.76+/-0.10 0.40+/-0.05 4.00+/-0.05 DATUM A PIN 1 AREA 2X 2.76+/-0.10 4.00+/-0.05 B CENTER TAB DETAIL B 0.15 C DATUM B 0.15 C 2X 0.35+/-0.05 0.65 0.20 REF 16X 0.10 C C 0.10 CAB 0.05 C DATUM A OR B 16X 0.08 C SEATING PLANE 0.65/2 0.00-0.05 0.85+/-0.05 TERMINAL TIP 0.65 DETAIL B SCALE:NTS 33657 - 4 March 2006 13 of 15 GS1578A Data Sheet 6.2 Recommended PCB Footprint 0.35 0.65 0.55 3.70 2.76 CENTER PAD NOTE: All dimensions are in millimeters. 2.76 3.70 The Center Pad should be connected to the most negative power supply plane (VEE) by a minimum of 5 vias. NOTE: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations. 6.3 Packaging Data Parameter Value Package Type 4mm x 4mm 16-pin QFN Package Drawing Reference JEDEC M0220 Moisture Sensitivity Level 3 Junction to Case Thermal Resistance, θj-c 31.0°C/W Junction to Air Thermal Resistance, θj-a (at zero airflow) 43.8°C/W Psi 11.0°C/W Pb-free and RoHS compliant Yes 6.4 Ordering Information GS1578A 33657 - 4 Part Number Package Temperature Range GS1578ACNE3 16-pin QFN 0°C to 70°C March 2006 14 of 15 GS1578A Data Sheet 7. Revision History Version ECR PCN Date Changes and/or Modifications A 135502 – February 2005 New document. 0 136045 – February 2005 Convert to Preliminary Data Sheet. 1 137132 – June 2005 Converted to Data Sheet. Changed title of Figure 2-2 to clarify that it is the Pb reflow profile. Updated SD additive jitter number in the AC electrical characteristics table to be typically 20psp-p. Updated dimensions on center pad of the PCB footprint in Section 6.2 to match the dimensions of the center pad of the device. Corrected part number in ordering information. Rephrased the RoHS Compliant statement. 2 137885 – September 2005 Corrected process to BiCMOS. Updated eye diagrams in Section 4.2. 3 139113 38124 January 2006 Corrected Input Differential Swing to 2200mV. 4 139637 38695 March 2006 Corrected pad standoff height and tolerances for pad width & package dimension. Corrected pad shape. CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 2005 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 33657 - 4 March 2006 15 of 15 15